Analog-to-digital converter

In electronics, an analog-to-digital converter (ADC, A/D, or A-to-D) is

a system that converts an analog signal, such as a sound picked up by a
microphone or light entering a digital camera, into a digital signal. An
ADC may also provide an isolated measurement such as an electronic
device that converts an input analog voltage or current to a digital
number representing the magnitude of the voltage or current.
Typically, the digital output is a two's complement binary number that
is proportional to the input, but there are other possibilities.
There are several ADC architectures. Due to the complexity and the
need for precisely matched components, all but the most specialized
ADCs are implemented as integrated circuits (ICs). These typically
take the form of metal–oxide–semiconductor (MOS) mixed-signal
integrated circuit chips that integrate both analog and digital circuits.
A digital-to-analog converter (DAC) performs the reverse function; it
converts a digital signal into an analog signal.

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Sampling rate
The analog signal is continuous in time and it is necessary to convert
this to a flow of digital values. It is therefore required to define the rate
at which new digital values are sampled from the analog signal. The
rate of new values is called the sampling rate or sampling frequency of
the converter. A continuously varying bandlimited signal can be
sampled and then the original signal can be reproduced from the
discrete-time values by a reconstruction filter. The Nyquist–Shannon
sampling theorem implies that a faithful reproduction of the original
signal is only possible if the sampling rate is higher than twice the
highest frequency of the signal.

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Since a practical ADC cannot make an instantaneous conversion, the
input value must necessarily be held constant during the time that the
converter performs a conversion (called the conversion time). An input
circuit called a sample and hold performs this task—in most cases by
using a capacitor to store the analog voltage at the input, and using an
electronic switch or gate to disconnect the capacitor from the input.
Many ADC integrated circuits include the sample and hold subsystem
internally.

Types
These are the most common ways of implementing an electronic ADC:

Direct-conversion
A direct-conversion ADC or flash ADC has a bank of comparators
sampling the input signal in parallel, each firing for their decoded
voltage range. The comparator bank feeds a logic circuit that generates
a code for each voltage range. Direct conversion is very fast, capable

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of gigahertz sampling rates, but usually has only 8 bits of resolution or
fewer, since the number of comparators needed, 2N – 1, doubles with
each additional bit, requiring a large, expensive circuit. ADCs of this
type have a large die size, a high input capacitance, high power
dissipation, and are prone to produce glitches at the output (by
outputting an out-of-sequence code). Scaling to newer submicrometre
technologies does not help as the device mismatch is the dominant
design limitation. They are often used for video, wideband
communications or other fast signals in optical storage. There are four
different types of direct ADCs.

Parallel comparator ADC

This is the simplest ADC. It is at the same time the fastest and the
most expensive technique. The circuit consists of a resistive divider
network, a set of op-amp comparators and a priority encoder. A small
amount of hysteresis is built into the comparator to resolve any
problems that might occur if both inputs were of equal voltage. At
each node of the resistive divider, a comparison voltage is available.
The purpose of the circuit is to compare the analog input voltage with
each of the node voltages. The circuit has the advantage of high speed
as the conversion takes place simultaneously rather than sequentially.
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Typical conversion time is 100 ns or less. Conversion time is limited
only by the speed of the comparator and of the priority encoder. This
type of ADC has the disadvantage that the number of comparators
required almost doubles for each added bit. Also, the larger the value
of n, the more complex is the priority encoder.
Counter type ADC
The D to A converter can be easily turned around to provide the
inverse function A to D conversion. The principle is to adjust the
DAC's input code until the DAC's output comes within ±1⁄2 LSB to
the analog input which is to be converted to binary digital form.
Servo tracking ADC
It is an improved version of a counting ADC. The circuit consists of an
up-down counter with the comparator controlling the direction of the
count. The analog output of the DAC is compared with the analog
input. If the input is greater than the DAC output signal, the output of
the comparator goes high and the counter is caused to count up. The
tracking ADC has the advantage of being simple. The disadvantage,
however, is the time needed to stabilize as a new conversion value is
directly proportional to the rate at which the analog signal changes.
Successive approximation
A successive-approximation ADC uses a comparator to successively
narrow a range that contains the input voltage. At each successive step,
the converter compares the input voltage to the output of an internal
digital to analog converter which might represent the midpoint of a
selected voltage range. At each step in this process, the approximation
is stored in a successive approximation register (SAR). For example,
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consider an input voltage of 6.3 V and the initial range is 0 to 16 V.
For the first step, the input 6.3 V is compared to 8 V (the midpoint of
the 0–16V range). The comparator reports that the input voltage is less
than 8 V, so the SAR is updated to narrow the range to 0–8 V. For the
second step, the input voltage is compared to 4 V (midpoint of 0–8 V).
The comparator reports the input voltage is above 4 V, so the SAR is
updated to reflect the input voltage is in the range 4–8V. For the third
step, the input voltage is compared with 6 V (halfway between 4 V and
8 V); the comparator reports the input voltage is greater than 6 volts,
and search range becomes 6–8 V. The steps are continued until the
desired resolution is reached.

Ramp-compare
A ramp-compare ADC produces a saw-tooth signal that ramps up or
down then quickly returns to zero. When the ramp starts, a timer starts
counting. When the ramp voltage matches the input, a comparator
fires, and the timer's value is recorded. Timed ramp converters require
the fewest transistors. The ramp time is sensitive to temperature
because the circuit generating the ramp is often a simple oscillator.
There are two solutions: use a clocked counter driving a DAC and then
use the comparator to preserve the counter's value, or calibrate the
timed ramp. A special advantage of the ramp-compare system is that
comparing a second signal just requires another comparator, and
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another register to store the voltage value. A very simple (nonlinear)
ramp converter can be implemented with a microcontroller and one
resistor and capacitor.[12] Vice versa, a filled capacitor can be taken
from an integrator, time-to-amplitude converter, phase detector,
sample and hold circuit, or peak and hold circuit and discharged. This
has the advantage that a slow comparator cannot be disturbed by fast
input changes.

Wilkinson
The Wilkinson ADC was designed by D. H. Wilkinson in 1950. The
Wilkinson ADC is based on the comparison of an input voltage with
that produced by a charging capacitor. The capacitor is allowed to
charge until its voltage is equal to the amplitude of the input pulse (a
comparator determines when this condition has been reached). Then,
the capacitor is allowed to discharge linearly, which produces a ramp
voltage. At the point when the capacitor begins to discharge, a gate
pulse is initiated. The gate pulse remains on until the capacitor is
completely discharged. Thus, the duration of the gate pulse is directly
proportional to the amplitude of the input pulse. This gate pulse
operates a linear gate which receives pulses from a high-frequency
oscillator clock. While the gate is open, a discrete number of clock
pulses pass through the linear gate and are counted by the address
register. The time the linear gate is open is proportional to the
amplitude of the input pulse, thus the number of clock pulses recorded
in the address register is proportional also. Alternatively, the charging
of the capacitor could be monitored, rather than the discharge.[13][14]

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Integrating
An integrating ADC (also dual-slope or multi-slope ADC) applies the
unknown input voltage to the input of an integrator and allows the
voltage to ramp for a fixed time period (the run-up period). Then a
known reference voltage of opposite polarity is applied to the
integrator and is allowed to ramp until the integrator output returns to
zero (the run-down period). The input voltage is computed as a
function of the reference voltage, the constant run-up time period, and
the measured run-down time period. The run-down time measurement
is usually made in units of the converter's clock, so longer integration
times allow for higher resolutions. Likewise, the speed of the converter
can be improved by sacrificing resolution. Converters of this type (or
variations on the concept) are used in most digital voltmeters for their
linearity and flexibility.

Charge balancing ADC

The principle of charge balancing ADC is to first convert the input
signal to a frequency using a voltage-to-frequency converter. This
frequency is then measured by a counter and converted to an output
code proportional to the analog input. The main advantage of these
converters is that it is possible to transmit frequency even in a noisy
environment or in isolated form. However, the limitation of this circuit
is that the output of V/F converter depends upon an RC product whose
value cannot be easily maintained with temperature and time.
Dual-slope ADC
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The analog part of the circuit consists of a high input impedance
buffer, precision integrator and a voltage comparator. The converter
first integrates the analog input signal for a fixed duration and then it
integrates an internal reference voltage of opposite polarity until the
integrator output is zero. The main disadvantage of this circuit is the
long duration time. They are particularly suitable for accurate
measurement of slowly varying signals such as thermocouples and
weighing scales.
Delta-encoded
A delta-encoded ADC or counter-ramp has an up-down counter that
feeds a digital to analog converter (DAC). The input signal and the
DAC both go to a comparator. The comparator controls the counter.
The circuit uses negative feedback from the comparator to adjust the
counter until the DAC's output is close enough to the input signal. The
number is read from the counter. Delta converters have very wide
ranges and high resolution, but the conversion time is dependent on the
input signal level, though it will always have a guaranteed worst-case.
Delta converters are often very good choices to read real-world
signals. Most signals from physical systems do not change abruptly.
Some converters combine the delta and successive approximation
approaches; this works especially well when high frequencies are
known to be small in magnitude.
Pipelined
A pipelined ADC (also called subranging quantizer) uses two or more
steps of subranging. First, a coarse conversion is done. In a second
step, the difference to the input signal is determined with a digital to

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analog converter (DAC). This difference is then converted finer, and
the results are combined in a last step. This can be considered a
refinement of the successive-approximation ADC wherein the
feedback reference signal consists of the interim conversion of a whole
range of bits (for example, four bits) rather than just the next-most-
significant bit. By combining the merits of the successive
approximation and flash ADCs this type is fast, has a high resolution,
and only requires a small die size.
Sigma-delta
A sigma-delta ADC (also known as a delta-sigma ADC) oversamples
the desired signal by a large factor and filters the desired signal band.
Generally, a smaller number of bits than required are converted using a
Flash ADC after the filter. The resulting signal, along with the error
generated by the discrete levels of the Flash, is fed back and subtracted
from the input to the filter. This negative feedback has the effect of
noise shaping the error due to the Flash so that it does not appear in the
desired signal frequencies. A digital filter (decimation filter) follows
the ADC which reduces the sampling rate, filters off unwanted noise
signal and increases the resolution of the output (sigma-delta
modulation, also called delta-sigma modulation).
Time-interleaved
A time-interleaved ADC uses M parallel ADCs where each ADC
samples data every M:th cycle of the effective sample clock. The result
is that the sample rate is increased M times compared to what each
individual ADC can manage. In practice, the individual differences
between the M ADCs degrade the overall performance reducing the

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spurious-free dynamic range (SFDR).[15] However, technologies exist
to correct for these time-interleaving mismatch errors.
Intermediate FM stage
An ADC with intermediate FM stage first uses a voltage-to-frequency
converter to convert the desired signal into an oscillating signal with a
frequency proportional to the voltage of the desired signal, and then
uses a frequency counter to convert that frequency into a digital count
proportional to the desired signal voltage. Longer integration times
allow for higher resolutions. Likewise, the speed of the converter can
be improved by sacrificing resolution. The two parts of the ADC may
be widely separated, with the frequency signal passed through an opto-
isolator or transmitted wirelessly. Some such ADCs use sine wave or
square wave frequency modulation; others use pulse-frequency
modulation. Such ADCs were once the most popular way to show a
digital display of the status of a remote analog sensor.
References

 Knoll, Glenn F. (1989). Radiation Detection and

Measurement (2nd ed.). New York: John Wiley & Sons. 

 Nicholson, P. W. (1974). Nuclear Electronics. New York: John

Wiley & Sons. pp. 315–316. 

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