9.2 A 253mW/Channel 4TX/4RX Pulsed Chirping Phased-Array Radar TRX in 65nm CMOS For X-Band Synthetic - Aperture Radar Imaging

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ISSCC 2018 / SESSION 9 / WIRELESS TRANSCEIVERS AND TECHNIQUES / 9.

9.2 A 253mW/Channel 4TX/4RX Pulsed Chirping Phased- Figure 9.2.2 shows the key building block circuits. For the 400MHz fractional DLL,
Array Radar TRX in 65nm CMOS for X-Band Synthetic- a 16b, 3rd-order ΔΣ modulator (DSM) selects the outputs of 4 adjacent voltage-
control delay cells (VCDCs) to form the required fractional delay that is mapped
Aperture Radar Imaging to the VDM to further generate four delayed clocks for the DDSs. The DDS mainly
consists of a 20b frequency/phase accumulator-based digital modulation core
Liheng Lou1, Kai Tang1, Bo Chen1, Ting Guo1, Yisheng Wang2, and a linear/nonlinear hybrid digital-to-analog convertor (DAC). It achieves 10b
Wensong Wang1, Zhongyuan Fang1, Zhe Liu1, Yuanjin Zheng1 quarter wave-resolution with a 4b coarse DAC and a 6b fine DAC using 1b to
generate a full sine wave. The PS, implemented as an I/Q vector sum phase shifter
1
Nanyang Technological University, Singapore, Singapore after a 2-stage polyphase filter, employs a compact 6b binary-weighted current-
2
Singapore University of Technology and Design, Singapore, Singapore source array (CSA) associating with a 3b current-bleeding CSA for
constant-current calibration and phase trimming. A 3-stage transformer-coupled
Airborne or spaceborne synthetic aperture radar (SAR) targeted for micro- PA achieves 25.1dB gain and 15.2dBm saturated output power. A programmable
unmanned aerial vehicles (UAV) or micro-satellites is capable of observing large gain (PG) LNA is employed to adapt to echoes’ power level. The first-stage
area under all weather conditions with strong penetration, and finds many common-source LNA uses a transistor with a size of 96μm/60nm to reduce the
emerging applications in defence, geology, oceanography, agriculture and other NF, and the cascade transistor arrays of the second stage are used to program
areas [1]. Phased-array SAR, operating in three modes of spotlight, stripmap and the LNA gain. An on-chip balun is designed to match the single-ended LNA to a
scanSAR, can significantly improve the spatial resolution and detection SNR by following differential neutralized dynamic current-injection-based Gilbert mixer.
steering the beams to the targets. The existing SAR system is still constrained by The RXBB is composed of a fixed gain stage (GS), coarse GSs, a 5th-order elliptic
power, size, and performance for payload in micro-UAVs/micro-satellites. This Gm-C BPF, a fine GS and a linear output buffer. These stages are interleaved to
paper describes the development of an X-band phased-array radar TRX IC achieve a tunable frequency range of 60 to 280MHz (for both dechirping and
achieving a power of 253mW/channel, and resolution of <30cm, with a die size <280MHz chirp downconversion) and a gain range of 0 to 60dB in steps of 1dB.
of 7.8mm2.
The phased-array TRX chip was fabricated in a 65nm CMOS process (Fig. 9.2.7)
Conventional radar systems are narrowband systems and beamforming is and consumes 253mW/channel at 1.2V (33.8mW DLL MPS, 21.5mW DDS,
achieved using phase shifters. To achieve a wideband phased-array operation, a 22.9mW PLL, 15.2mW PS, 111.2mW PA, 23.6mW RX RFFE, 50.2mW RXBB).
true time delay is required in each element [2]. In addition, there always exists The chip was mounted on a PCB for testing. The measured spectrum of the TX
the trade-off between large-angle beamforming and achieving fine-angle output is shown in Fig. 9.2.3, with 9.7dBm output power (After the 5dB loss from
resolution. To solve these issues, a two-stage delay control with calibration is the PCB, cable and SMA is taken into account, the calibrated TX has output power
employed in the transmitter, where a DLL is used to control the coarse true time of 14.7dBm), <2dB ripple, 1GHz (10%) BW, 1.69ps DLL RMS jitter and
delay of the baseband chirp and a compact active phase shifter in the RF path is -118.8dBc/Hz PLL PN at 1MHz offset. PS exhibits <1.7° phase RMSE and <0.6dB
used for fine delay tuning. As shown in Fig. 9.2.1, a DLL-based multiphase gain RMSE. In Fig. 9.2.4, the RX RFFE attains variable gain of 15.3 to 28.6dB from
synthesizer (MPS) generates the multiphase delayed clocks with precise delay 9.5 to 10.5GHz, <1.1dB ripple, -37dBm IP1dB, and 5.7-to-6.5dB DSB NF (7.1-to-
control [2]. Then each clock is used as a reference clock input to a corresponding 7.9dB DSB NF for RX at 28.6dB RFFE gain). The RXBB gain and frequency
direct digital synthesizer (DDS) in baseband chirp generation that then gets phase- responses are shown at three typical settings. The delay-line test shows that the
reserved upconverted to an RF wideband chirp by a PLL. In this way, a relatively dechirped pulse from RFFE output achieves -12.9dB peak sidelobe ratio (PSLR)
large time delay (tens of ps) in coarse steps between adjacent RF chirp signals for the 33.8kHz tone and phase coherence of 0.45° RMS at the chirp rate of
can be obtained through the MPS, and fine time-delay adjustment (<1ps) is 1MHz/μs, similarly applied to other frequencies. The -3dB BW of the main lobe is
subsequently achieved with a 6b phase shifter. For the beamforming receiver, measured as 0.52kHz, which translates to a long-range resolution of <30cm. An
digital beamforming is a more flexible way to apply advanced algorithms. The implementation of 8dBi Vivaldi antenna with 6GHz bandwidth is demonstrated.
receiver is capable of working in two modes: without or with stretch processing With phased-array synthetic aperture formed, it achieves an azimuth resolution
[3]. An external reference LO generator chip is developed for both processing <17cm.
modes. For the former mode, direct downconversion is applied, and the
downconverted IF signals will occupy the same bandwidth as the RF chirps, Figure 9.2.5 shows a typical TRX radiation pattern co-tested with the 4×4 Vivaldi
requiring at least double the bandwidth in ADC sampling; For the latter mode, a antenna array of -53dB isolation. For TX beamsteering, a chirp rate of 1 to
time-of-return (TOR) predictor with <0.1μs delay resolution estimates the starting 10MHz/μs is adopted; For RX beamforming, the dechirped IF signals are collected
time of the LO chirps with the knowledge of the UAV/Satellite’s altitude, and then to form digital beamforming off-line. With antennas 6cm apart from each other,
activates the reference LO chirp of the same slope rate as the RF chirp for the TX can beamsteer across angles up to ±60° with steps of 1°, and the RX can
compressing the signal bandwidth, significantly relaxing the requirement on the continuously scan the same range with a resolution of <1°, which enhances the
ADCs. spatial resolution in SAR imaging. Performance of the phased-array prototype
and some prior arts [3-6] are summarized in Fig. 9.2.6. The X-band SAR is widely
The paper presents a 4TX/4RX pulsed chirping phased-array TRX for SAR used for airborne and spaceborne applications though only a few IC
operating at X-band. As shown in Fig. 9.2.1, the MPS employing fractional DLLs implementations have been reported. The competed design of the phased-array
and a Vernier delay matrix (VDM) [2] provides a maximum clock time delay up to radar IC makes it well suited for micro-UAV and micro-satellite applications.
200ps with 20ps steps for coarse delay tuning with jitter of 1.67ps RMS. It resorts
to 174ps delay to achieve a maximum beamsteering angle of ±60° when antennas References:
are separated by 2λ (6cm) pitch. A compact DDS is employed for tunable [1] Christopher F. Barnes, Synthetic Aperture Radar. Barnes, 2015.
baseband chirp generation with frequency from 74.2 to 82.1MHz, chirp duration [2] L. Wang, et al., “3–5 GHz 4-Channel UWB Beamforming Transmitter with 1°
of 20μs to 1ms and pulse repetition rate of 1ms. The PLLs work as closed-loop Scanning Resolution Through Calibrated Vernier Delay Line in 0.13-μm CMOS,”
frequency multipliers to obtain 10GHz centred chirps up to 1GHz BW with a IEEE JSSC, vol. 47, pp. 3145-3159, Dec. 2012.
linearity of 183kHz-to-1.1MHz RMSE, which preserves the same relative true time [3] J. Yu, et al., “An X-Band Radar Transceiver MMIC with Bandwidth Reduction
delay between RF chirps as those of MPS outputs and governs a resolution of in 0.13μm SiGe Technology,” IEEE JSSC, vol. 49, pp. 1905-1915, Sept. 2014.
<30cm for long-range detection. An active phase shifter (PS) is used to attain a [4] B. Ku, et al., “A 77–81-GHz 16-Element Phased-Array Receiver with ±50° Beam
fine beamsteering resolution of 1° that requires 5.86° phase-shift resolution, Scanning for Advanced Automotive Radars,” IEEE TMTT, vol. 62, pp. 2823-2832,
translating to 1.67ps true time delay. The ripple at the TX output is minimized to Nov. 2014.
<2dB by employing a saturated power amplifier (PA), and with the LNA having [5] P. Chen, et al., “A 94GHz 3D-Image Radar Engine with 4TX/4RX Beamforming
0.2dB gain ripple in RX, no significant paired echo is observed. The RX baseband Scan Technique in 65nm CMOS,” ISSCC, pp.146-147, Feb. 2013.
(RXBB) is employed after a mixer with interleaved filter and programmable-gain [6] T. Chu, et al., “A Short-Range UWB Impulse-Radio CMOS Sensor for Human
amplifier (PGA) stages to improve the linearity to the IP1dB of -5dBm and suppress Feature Detection,” ISSCC, pp. 294-296, Feb. 2011.
the antenna leakage and other IF interferences by >60dB.

160 • 2018 IEEE International Solid-State Circuits Conference 978-1-5090-4940-0/18/$31.00 ©2018 IEEE
ISSCC 2018 / February 13, 2018 / 9:00 AM

Figure 9.2.1: The proposed phased array TRX IC architecture. Figure 9.2.2: Circuit schematics of the MPS, DDS, PS, VGLNA and RXBB.

Figure 9.2.3: Measured DLL jitter (top left), PLL PN (top right), TX chirp Figure 9.2.4: Measured RX RFFE (top left), RXBB (top right), dechirped
spectrum (bottom left), and PS RMSE (bottom right). spectrum and phase coherence (bottom left), and antenna S11 (bottom right).

Figure 9.2.5: 4TX beamsteering radiation pattern (top left), 4RX beamforming
pattern (top right), and phased array radar prototype (bottom). Figure 9.2.6: Performance summary and comparison.

DIGEST OF TECHNICAL PAPERS • 161


ISSCC 2018 PAPER CONTINUATIONS

Figure 9.2.7: Die micrograph and layout.

• 2018 IEEE International Solid-State Circuits Conference 978-1-5090-4940-0/18/$31.00 ©2018 IEEE

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