1260 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO.

5, MAY 2018

A Low-Cost Scalable 32-Element 28-GHz Phased

Array Transceiver for 5G Communication Links
Based on a 2 × 2 Beamformer Flip-Chip Unit Cell
Kerim Kibaroglu , Student Member, IEEE, Mustafa Sayginer , Member, IEEE,
and Gabriel M. Rebeiz, Fellow, IEEE

Abstract— This paper presents a scalable 28-GHz phased-array

architecture suitable for fifth-generation (5G) communication
links based on four-channel (2 × 2) transmit/receive (TRX) quad-
core chips in SiGe BiCMOS with flip-chip packaging. Each
channel of the quad-core beamformer chip has 4.6-dB noise
figure (NF) in the receive (RX) mode and 10.5-dBm output
1-dB compression point (OP1dB) in the transmit (TX) mode with
6-bit phase control and 14-dB gain control. The phase change
with gain control is only ±3°, allowing orthogonality between
the variable gain amplifier and the phase shifter. The chip has
high RX linearity (IP1dB = −22 dBm/channel) and consumes
130 mW in the RX mode and 200 mW in the TX mode at P1dB
per channel. Advantages of the scalable all-RF beamforming
architecture and circuit design techniques are discussed in detail.
4- and 32-element phased-arrays are demonstrated with detailed
data link measurements using a single or eight of the four-
channel TRX core chips on a low-cost printed circuit board
with microstrip antennas. The 32-element array achieves an
effective isotropic radiated power (EIRP) of 43 dBm at P1dB,
a 45-dBm saturated EIRP, and a record-level system NF of 5.2 dB
when the beamformer loss and transceiver NF are taken into
account and can scan to ±50° in azimuth and ±25° in elevation
with < −12-dB sidelobes and without any phase or amplitude
calibration. A wireless link is demonstrated using two 32-element
phased-arrays with a state-of-the-art data rate of 1.0–1.6 Gb/s
in a single beam using 16-QAM waveforms over all scan angles
at a link distance of 300 m.
Index Terms— 28-GHz, beamforming, data link, error vector
magnitude (EVM), fifth-generation (5G), flip-chip, Ka-band,
mm-wave, multiple-input multiple-output (MIMO), phased-
array, printed circuit board (PCB) antenna, quadrature ampli- Fig. 1. Scalable N × N 5G phased-array architecture based on a 2 × 2
tude modulation (QAM), receiver, SiGe, transmitter. beamformer unit cell.

I. I NTRODUCTION the order of 1–10 Gb/s by utilizing the available bandwidth at

mm-wave bands, such as 28, 39, and 60 GHz. To overcome
T HE fifth-generation (5G) communication links promise a
revolution in mobile communications with data rates on the increased path loss at mm-wave bands, the next generation
communication links will rely on directive communications,
Manuscript received August 30, 2017; revised November 18, 2017; accepted enabled by phased-array techniques and can result in lower
December 25, 2017. Date of publication January 31, 2018; date of current
version April 23, 2018. This work was supported in part by Facebook, in part power consumption compared with sub-6-GHz links due to
by Keysight Technologies, and in part by the Defense Advanced Research the array antenna gain [1]–[3]. While phased-arrays have been
Projects Agency (DARPA). This paper was approved by Guest Editor Osama used for many years for defense applications and satellite
Shanaa. (Corresponding author: Kerim Kibaroglu.)
K. Kibaroglu and G. M. Rebeiz are with the Electrical and Computer communications, their cost needs to be significantly low-
Engineering Department, University of California at San Diego, La Jolla, CA ered for massive use in 5G applications. This requires the
92093 USA (e-mail: [email protected]; [email protected]). use of highly integrated chips based on silicon technologies
M. Sayginer was with the Electrical and Computer Enginnering Depart-
ment, University of California at San Diego, La Jolla, CA 92093 USA. (SiGe or CMOS) rather than GaAs- or InP-based modules
He is now with Nokia Bell Labs, Murray Hill, NJ 07974 USA (e-mail: [4]–[12], low-cost printed circuit board (PCB) designs, and a
[email protected]). great reduction in testing costs by eliminating array calibration.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. A scalable, low-cost phased-array capable of scanning in both
Digital Object Identifier 10.1109/JSSC.2018.2791481 azimuth and elevation at mm-wave frequencies is needed to
0018-9200 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
KIBAROGLU et al.: LOW-COST SCALABLE 32-ELEMENT 28-GHz PHASED ARRAY TRANSCEIVER 1261

deliver Gb/s data to several users at a link distance on the may only require 16–32 elements. This architecture allows
order of hundreds of meters. both to be implemented using the same silicon beamformer
Recently, there have been several demonstrations of phased- chip. Note that a single-chip solution with an integrated
array-based data links in the mm-wave bands [4]–[7]. All of transceiver [8] may be preferable for cell phones due to its
these phased-arrays rely on an all-RF beamforming architec- reduced form factor if 8–16 elements are required.
ture for reduced power consumption due to the elimination of Third, the scalable array architecture results in a more robust
a mixer for each channel (for LO or IF beamforming), reduced design and uniform heat distribution over the aperture. If one
complexity by eliminating the LO distribution network to of the core chips does not work or underperforms, this results
several chips in a large array, and the ability to cancel any in a loss of only four elements out of 32–256 elements and will
out-of-beam interferer before the mixer (at the sum point), have minimal impact on the system performance compared
resulting in higher dynamic range [13], [14]. The antennas with the loss of a chip with 16 channels. This architecture
can be placed on-chip [4] or integrated on the PCB [5]–[8], also spreads out the heat, generated mostly by the power
and the beamformer core chip may include the RF front end amplifiers (PAs), over the aperture instead of confining it to
only [4] or, for a large number of channels on-chip, include a single large chip at the center of the array. This makes it
the up-/downconversion mixers and synthesizers in addition to significantly easier to cool the array resulting in a more robust
the RF front end [5]–[8]. performance.
This paper expands on [15] and presents a 32-element Fourth, the 2 × 2 beamformer chips can be directly flipped
(4 × 8) 28-GHz phased-array transceiver for 5G communica- on the PCB without a multi-layer laminate interposer due to
tions based on 2×2 beamformer core chips. Section II presents the reduced number of I/O ports compared with a phased-
the scalable phased-array architecture and Section III presents array chip with larger number of elements. This also results
system analysis for a 32-element array. Circuit blocks and in a lower cost PCB with a reduced number of layers, since
breakout measurements are presented in Section IV. Section V the routing complexity is minimal and there is no LO or IF
presents the system measurements of 2 × 2 and 4 × 8 arrays distribution networks to several chips in the phased-array.
and Section VI concludes this paper. Finally, by separating the phased-array front-end chip and
the transceiver chip, this architecture offers great flexibility.
II. 5G P HASED -A RRAY T RANSCEIVER A RCHITECTURE In this paper, both chips have been designed in the TowerJazz
The scalable 28-GHz phased-array architecture used in this SBC18H3 SiGe BiCMOS process [16], but this two-chip
work is shown in Fig. 1 and is based on 2 × 2 transmit/receive solution allows for different IC processes to be used for the
(TRX) beamformer chips which are flipped on one side of beamformer chip and the transceiver chip. For example, the RF
a PCB with the antennas placed on the other side. Each beamformer can be designed in SiGe for increased output
chip contains four TRX channels with phase and gain con- power, reliability, and low-NF, whereas the transceiver chip
trol implemented using an all-RF beamforming architecture. can be designed in highly scaled CMOS and can incorporate
Since the core chip contains only four elements, a separate the baseband functionality as well. Also, a multi-pole filter
transceiver chip is designed for up-/downconversion to an IF with a sharp rejection response can be placed before the
(or baseband) signal and can be placed every 16, 32, or 64 ele- transceiver chip, thereby greatly reducing the out-of-band
ments depending on the system requirements. interferers and eliminating any LO radiation (in IF-based
Compared with previous work which has relied on a large architectures).
number of elements on a single chip [5], [6], [8], this One disadvantage of this architecture is that the transceiver
architecture offers significant advantages. First, the routing needs to compensate for the additional ohmic loss of the
distance from the chip to the antenna feeds is minimized which Wilkinson network and provide a high output power to drive
greatly reduces the loss and improves both the system noise the array. This can be alleviated in 256-element arrays by
figure (NF) and the transmitted power, therefore allowing for a incorporating bidirectional line amplifiers every 64 or 128 ele-
much longer link distance for the same aperture size and power ments on the PCB to compensate for the division and ohmic
consumption. For example, LG in [7] recently reported a feed loss or by placing a transceiver every 64 elements with reduced
line loss of 2 dB between the antenna and the chip, whereas output power levels. Simulations for 16-, 32-, and 64-element
in this work, the equivalent loss is only 0.5 dB, resulting in arrays show that no additional line amplifiers are required [see
3-dB improvement in the system SNR. The feed lines to the Section III and Fig. 5(a)].
antennas can also be designed to be of equal length which, While this paper is based on four-element beamformer
when combined with the symmetric design of the Wilkinson chips to generate a single beam, the same architecture can
network and the 2 × 2 TRX beamformer chips, can eliminate be used to build a dual-polarized dual-beam TRX core chip
any phased-array calibration for further cost reduction. which can generate two simultaneous beams for polarization-
Second, the array can be scaled to any size while main- based multiple-input multiple-output (MIMO) systems. Each
taining symmetry. An example 64-element (8 × 8) array is chip would then include eight channels, four of which are
shown in Fig. 1 with a transceiver chip placed at the common combined together into two common ports for the vertical and
port after the Wilkinson combiner/divider network on the PCB. horizontal polarizations. These chips would feed into dual-
Base stations are likely going to require 64 to 256+ elements polarized antennas, and two RF beamformers on the PCB
to meet the effective isotropic radiated power (EIRP) require- together with two transceivers at the sum points would be used.
ments for increased coverage, whereas end-user equipment This dual-beam architecture still retains all the benefits of the
1262 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 5, MAY 2018

TABLE I
C OMPARISON OF 2 × 2 Q UAD B EAMFORMER AND L ARGER IC D ESIGN A PPROACHES

Fig. 3. Block diagram of the 2 × 2 TRX beamformer core chip.

Fig. 2. Required output power per element for different EIRP values versus across the array and includes the antenna ohmic and mismatch
number of array elements.
loss (∼1 dB) and the feed line loss (∼0.5 dB), and L M is the
scalable array architecture outlined previously and summarized power loss due to any amplitude and phase mismatch between
in Table I. the elements (∼0.5 dB). G ANT is approximated using
 
III. 32-E LEMENT P HASED -A RRAY S YSTEM A NALYSIS 4π Nx dx N y d y
G ANT = 10log − L ANT (2)
This section presents the 2 × 2 phased-array beamformer λ2
core chip and system specifications along with the design flow. where λ is the wavelength in air, Nx and N y are the number
First, the array EIRP must be chosen and the output power of array elements in the horizontal and vertical directions,
required per element at P1dB (Pout) is determined based on the dx and d y are the antenna spacings in the horizontal and
number of array elements. Given an EIRP, Pout is calculated vertical directions, and L ANT includes the antenna ohmic and
using mismatch loss and feed line loss.
Fig. 2 presents the required Pout for different EIRP values
Pout = EIRP − 10logN − G ANT + L M (1)
and array sizes. In this paper, we chose Pout to be around
where N is the number of array elements, G ANT is the 10 dBm for low power consumption per chip and to mit-
N-element TRX antenna gain assuming uniform distribution igate the thermal issues discussed in Section II. An EIRP
KIBAROGLU et al.: LOW-COST SCALABLE 32-ELEMENT 28-GHz PHASED ARRAY TRANSCEIVER 1263

Fig. 4. (a) System calculations for the 32-element TRX beamformer based on a 2 × 2 TRX beamformer core chip. (b) Interferer locations for the RX linearity
calculations.

of 43–49 dBm can be achieved with an array size of

N = 32–64 (4 × 8 or 8 × 8 elements). This was calculated
for a single-beam design in which the common ports of all
four-element chips are summed on the PCB.
The transmit (TX) chip gain of the 2 × 2 TRX core chip
(Fig. 3) must then be chosen such that a transceiver chip at
the sum point will be able to deliver enough power to operate
the 32-element array at the P1dB level. This gain is defined as
the output power per channel divided by the available power
at the chip input and includes the 6-dB on-chip Wilkinson
division loss and the 2.2-dB on-chip Wilkinson, transmission-
line, and balun ohmic loss. For a TX channel gain of 20 dB
[see Fig. 4(a) for channel definition] and an OP1dB Fig. 5. (a) OP1dB required from the transceiver chip to obtain 10.5-dBm
of 10.5 dBm, the chip TX gain is 11.8 dB and the required OP1dB per channel and (b) system NF for different channel gains and array
sizes.
input P1dB for each 2 × 2 beamformer chip is −0.3 dBm. For
a 32-element array and starting from the transceiver, the RF
power is distributed using a PCB-based Wilkinson network to
eight beamformer chips (1:8) with a division loss of 9 dB and where R is the link distance, L ATM is the atmospheric
an ohmic network loss of 4 dB. The ohmic network loss is due attenuation at 28 GHz (0.15 dB/km [17]), and G EL is the
to the PCB Wilkinson loss of 0.4 dB/stage and a transmission- microstrip patch antenna element gain (4.5 dB: 6 dB antenna
line loss of 0.5 dB/cm, all at 28 GHz. This results in a required directivity for dx = 0.5λ and d y = 0.63λ − 1.5-dB antenna
transceiver output power of 12.7 dBm for a 32-element array. and feed line loss). The factor ((4π R)/λ)2 is called the
Fig. 5(a) presents the required transceiver OP1dB for sev- path loss factor (PLF) and is 111 dB at 28 GHz at a range
eral array sizes and TX channel gains at a fixed OP1dB of 300 m. Assuming a base station transmitting with an EIRP
of 10.5-dBm/channel. A transceiver OP1dB of ∼18 dBm is of 65 dBm at a distance of 50–300 m, PEL is −26 to −41 dBm
required for a 64-element array due to the additional 5-dB loss which sets the linearity requirement per channel. An IP1dB
arising from 3 dB more division loss and 2 dB more ohmic of −22-dBm/channel was chosen for this paper, since the
loss in the 1:16 beamformer. In hindsight, it would have been microstrip antenna has a wide pattern and can receive several
better to design the TX channel gain to be 27 dB to keep the interfering base stations from several directions simultane-
transceiver output power <10 dBm up to 64 elements. ously, resulting in a complex interference signal with high
In the receive (RX) mode, the received power per antenna peak-to-average-power ratio (PAPR) at the antenna port.
element (at the chip port) PEL is calculated using The linearity of a phased-array is complex to define and
  depends on the incidence angle of the interferer signals
λ 2 [Fig. 4(b)]. First, all interferers are received by each antenna
PEL = EIRP + 10log − L ATM + G EL (3)
4π R element and fed to the low-noise amplifier (LNA) and the
1264 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 5, MAY 2018

RX channel. The interferers are amplified, phase-shifted, and

added together in the 1:32 or 1:64 Wilkinson network, and
interferers located at angular directions away from the main
lobe are dissipated in the Wilkinson beamformer and are
present at the transceiver port with reduced intensity given
by the phased-array sidelobes (−15 to −30-dB depending
on how far away from the main lobe) [18]. The interferers
at angles close to the main lobe are not attenuated by the
Wilkinson beamformer and are present at the transceiver with
full intensity. Note that the main lobe is constantly being
steered over wide angles, and an interferer located in a sidelobe
at timeframe t1 may be in the main lobe at timeframe t2 .
The worst case design is for an interferer in the main-
lobe direction. Referring to Fig. 4(a) with an RX channel
gain of 20 dB, an input P1dB of −22 dBm, and an on-chip
Wilkinson loss of 2.2 dB, the OP1dB per 2 × 2 beamformer
chip is −22 dBm + 20 dB RX gain + 6 dB (four channels)
− 2.2-dB ohmic loss − 1 dB for compression = 0.8 dBm. This
RX OP1dB increases to +5.8 dBm at the transceiver (sum)
port when power from all eight beamformer chips are added
together [0.8 dBm + 9 dB (eight chips) − 4-dB Wilkinson Fig. 6. (a) Schematic of SPDT. Measured (b) insertion loss and (c) matching
ohmic loss = 5.8 dBm]. This shows that a very high linearity and isolation.
transceiver is required if the interferer is at −22 dBm/antenna
element and in the main-lobe direction. Note that an IP1dB
of −22 dBm/element is conservative and assumes several ensuring stability and avoiding any performance degradation
65-dBm EIRP base stations at 50 m away. The RX OP1dB at due to bump inductance when the chip is flipped on a PCB.
the sum point of the array can also be reduced using 5–8-dB A bidirectional 4:1 Wilkinson network is used to combine the
gain control on each channel without affecting the system NF. signals from four channels in the RX mode or to divide the
In general, a transceiver IP1dB of −3 to 0 dBm is sufficient signal to four channels in the TX mode.
for most cases, and such a transceiver will have an NF of Channel selection, phase, and gain settings are controlled
∼10–15 dB at 28 GHz. through a serial peripheral interface (SPI) which can operate
It can be shown that the NF of an active antenna array up to a clock frequency of 100 MHz. A separate hardwire
should be calculated using the electronic gain from the antenna T/R switch is used to enable fast switching between the TX
port to the transceiver and includes only the ohmic losses of and RX modes. All pads have electrostatic discharge (ESD)
all the Wilkinson combiner stages and not any signal addition protection and all internal bias currents are generated from
[19]. For the 32-element array, there is a total ohmic loss two external reference currents, one for the PAs and another
of 6.2 dB following the RX channel, followed by a high- for all other blocks.
linearity mixer with 10–15-dB single-sideband NF (Fig. 4). The schematic of the single-ended SPDT at the antenna
The 2 × 2 TRX beamformer chip has an RX channel gain port is shown in Fig. 6(a). A shunt switch using reverse-
of 20 dB and an RX NF of 4.6 dB, and the resulting system saturated HBTs [20] is employed to achieve low insertion
NF is 5.2–6.2 dB using the Friis equation. loss. The shunt switch emitter length is chosen to be 15 μm
Fig. 5(b) presents the system NF for different RX gains which results in an ON-resistance, RON = 5.4  and an
and array sizes with a 2 × 2 TRX beamformer NF of 4.6 dB OFF -capacitance, C OFF = 37.8 fF. The HBTs are turned on
and a transceiver NF of 10 dB. It can be seen that the in the isolation mode with a bias current of 600 μA generated
additional ohmic loss from the combiner has little impact on through a CMOS current mirror. A lumped CLC impedance
the system NF for an RX channel gain >20 dB, demonstrating inverter with a compact area is used to isolate the TX and RX
the scalability of this architecture. paths, and one capacitor is implemented using the C OFF of the
shunt HBT transistor. Fig. 6(b) and (c) present measurements
done on an SPDT breakout cell for the ANT to TX path. The
IV. C IRCUIT D ESIGN AND B UILDING
measured insertion loss is 1.45 dB and the measured isolation
B LOCK M EASUREMENTS
is 19 dB at 28 GHz and agree well with simulations. This
Fig. 3 presents the beamformer core chip block diagram. level of isolation is adequate, since all bias currents of the
Each TRX channel includes a single-ended single-pole double- TX (RX) blocks are turned off in the RX (TX) mode. The
throw switch (SPDT) at the antenna port (ANT), variable gain IP1dB from the TX port to the antenna port is 15 dBm and
amplifiers (VGAs), phase shifters with 6-bit phase control, results in 0.3-dB gain compression when driven by a PA with
and a differential SPDT on the Wilkinson side. All circuit an OP1dB of 12 dBm. The switch linearity is limited by the
blocks are differential except for the SPDT at the antenna turn-on voltage of the shunt HBTs in the OFF state [21]. The
port and the first LNA stage. This is to achieve low NF while simulated switching time is 105 ns.
KIBAROGLU et al.: LOW-COST SCALABLE 32-ELEMENT 28-GHz PHASED ARRAY TRANSCEIVER 1265

Fig. 8. VM design based on a compensated QAF network.

The second method uses a Keysight PNA-X calibrated up

to the probe tips. The measured LNA NF is 2.6–2.7 dB at
27–28 GHz and the results agree within ±0.1 dB for both
measurement methods and with simulations.
The LNA is followed by a 6-bit vector modulator (VM)
phase shifter shown in Fig. 8. Two orthogonal vectors are gen-
erated by a quadrature-all-pass filter (QAF) network. Unlike
conventional designs where the QAF is designed for a capac-
itive load [23], [24], the QAF in this paper is designed for a
50- load using an LC compensation network. The compen-
Fig. 7. (a) Schematic of the two-stage LNA. (b) Measured S-parameters
with 5-dB gain control. (c) Measured NF. sation network is eventually merged into the VM VGA input
matching network resulting in different series capacitance
values for the I- and Q-VGAs. This results in an overall nar-
A. RX Channel rowband response, but lower NF compared with conventional
designs. The layout of the QAF network is also shown in Fig. 8
The RX channel consists of a single-ended LNA followed
and is critical in generating I/Q vectors with high accuracy.
by a passive balun and a differential LNA stage with 5-dB gain
The I/Q vectors are scaled and added using 6-bit VGAs
control. This is then followed by a 6-bit active phase shifter
controlled by a custom 6-bit current DAC to achieve 5.6° phase
and a VGA with 4-bit gain control.
steps with low-gain imbalance. The gain control mechanism
The LNA is shown in Fig. 7(a). The single-ended first stage
used in the second LNA stage is employed for the VM as well
has a gain of 6–7 dB with an NF of 2.0–2.1 dB at 28 GHz.
as all VGA blocks. Since this VM topology has a fixed tail
Since the medium-voltage HBTs with high- f T in this process
current and uses current steering at the cascode node, gm of the
have a breakdown voltage of 1.6 V, the common-emitter stage
input transistors remains constant for all phase settings. This
is operated from a supply of 1.2 V while all other blocks
results in a constant input impedance and the VM can operate
in the chip use a supply of 2.2 V. The gain control is based
up to its P1dB without any phase distortion against input
on current steering at the cascode node proposed in [22] to
power. The RX channel linearity is limited by the VM IP1dB
achieve linear-in-dB gain control. The measured S-parameters
of −7 dBm.
of an LNA breakout are shown in Fig. 7(b). The test cell
The VM is followed by a high-linearity VGA block (Fig. 9)
includes an additional balun at the output port for single-
with 9-dB gain control and employs a similar current-steering
ended measurements and the balun loss of 1.1 dB was not
topology as the second LNA stage. The measured phase
deembedded. The LNA has a gain of 15.2 dB at 28 GHz and
change is < ±3° over 9-dB gain control. The low phase
the measurements agree well with simulations. The measured
change is critical in order to taper the beam and to calibrate
phase change is < ±1.5° over 5-dB gain control.
any mismatch between elements in an array using a simple
The NF of the LNA was measured using two different
algorithm.
methods and the results are shown in Fig. 7(c). The first
method (labeled SA) uses a Keysight 346CK01 noise source
with an excess noise ratio of 12 dB at 28 GHz followed by B. TX Channel
the LNA under test. The LNA is followed by an external The TX channel uses a similar 6-bit phase shifter as the
amplifier with 32-dB gain and 4.5-dB NF to suppress the noise RX channel (Fig. 8) followed by a VGA with 14-dB gain
contribution of the spectrum analyzer and the measured NF control, similar to the RX VGA. Since VGAs that do not
is plotted after the cable and probe losses are deembedded. employ attenuators typically have constant IP1dB with gain
1266 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 5, MAY 2018

Fig. 11. Schematic of the differential SPDT on the Wilkinson side.

24 mA at the P1dB power level. The cascode is loaded by

a 1:1 transformer balun which also provides ESD protection
Fig. 9. VGA schematic with 4-bit gain control using current steering at the at the antenna ports. The transformer balun is implemented
cascode node. using a single turn in the top two metal layers [Fig. 10(a)] with
L = 260 pH, Q = 17.5, and a coupling value of 0.6 which
results in an insertion loss of 0.8 dB at 28 GHz.
The measured S-parameters of a PA breakout are shown
in Fig. 10(b) and show excellent agreement with simulations.
The breakout includes an extra balun at the input side for
single-ended measurements and its loss was not deembedded.
The PA can deliver an output power of 12 dBm at 28 GHz with
a power-added efficiency (PAE) of 13% at P1dB. Note that this
PAE includes the differential to a single-ended transformer.
A critical metric for a PA operating under modu-
lation is the AM–PM distortion, since 5G data links
will rely on complex modulated waveforms with high
PAPR. The measured AM–AM and AM–PM distortion
are shown in Fig. 10(c) at 28 GHz, and the AM–PM
is <8° at P1dB with a total bias current of 24 mA. This
ensures that the PA can amplify complex waveforms with little
distortion.
The RX and TX channels are combined on the Wilkinson
side using the differential SPDT shown in Fig. 11. The design
is similar to the single-ended SPDT at the antenna port and
uses shunt reverse-saturated HBTs. The layout is designed to
match the TX and RX channel layouts, resulting in larger area
and 0.1-dB higher loss compared with the single-ended SPDT.
The four channels are combined using a 4:1 differential
Fig. 10. (a) Class-AB PA schematic. (b) Measured S-parameters. Wilkinson combiner/divider network with a simulated ohmic
(c) Measured AM–AM and AM–PM distortion. loss of 1.1 dB including the interconnecting transmission
lines. Each Wilkinson is based on a wideband lumped CLC
control, the output power will drop when the gain is reduced. implementation to achieve compact area [25] and the 100-
Therefore, the VGA would need to deliver enough power to isolation resistors are placed very close to the input ports to
the PA in the lowest gain setting in order to operate the PA achieve >20-dB isolation. This is followed by a passive balun
at P1dB which would lead to very high power consumption with 1.1-dB loss to enable single-ended routing on the PCB
in the VGA. In this design, the TX VGA can deliver an from the chip common port. Fig. 12 summarizes the gain, NF,
OP1dB of 3 dBm to the following PA (which has an IP1dB and IP1dB of all building blocks in the core chip.
of −1 dBm) to ensure that the channel OP1dB does not drop
within 4 dB of gain control. This gain control can be used for C. 2 × 2 TRX Chip Measurements
array calibration or to taper the beam. The chips were fabricated in the TowerJazz SBC18H3 SiGe
The PA is implemented with a single-stage pseudo- BiCMOS process with a size of 2.5×4.7 mm2 and a minimum
differential cascode topology biased in class-AB [Fig. 10(a)]. pad (bump) spacing of 400 μm (Fig. 13). The measured
The nominal bias current is 12 mA/branch and increases to S-parameters of a single-channel are shown in Fig. 14 from
KIBAROGLU et al.: LOW-COST SCALABLE 32-ELEMENT 28-GHz PHASED ARRAY TRANSCEIVER 1267

Fig. 12. Gain, NF, and IP1dB of the 2 × 2 TRX beamformer core chip
blocks.

Fig. 13. Chip photograph of 2 ×2 TRX core chip with 400-μm pitch bumps.

the common port to the antenna port with the port definitions
shown in Fig. 12. The S-parameter measurements include the
ohmic loss of the Wilkinson network and the balun at the
common port, but 6 dB has been added to both TX and RX
S-parameter measurements to characterize the channel
response together with the on-chip Wilkinson network ohmic
loss. In the RX mode, the actual chip gain will be the same
as presented in Fig. 14. In the TX mode, the actual chip gain
will be 6 dB lower due to 6-dB division loss to four channels.
The measured RX and TX channel gain is 20 dB
[Fig. 14(a) and (b)] and the measurements agree well with
simulations. The measured reverse isolation is −55 to −60 dB
in both the TX and RX modes. Fig. 14(c) presents the insertion
phase for all 64 phase states in the RX mode and Fig. 14(d)
shows the corresponding RX gain for all 64 phase states. The
measured average rms phase error in the RX and TX modes
is 3.4° and the average rms gain error is 0.5 dB at 29 GHz
[Fig. 14(j)]. The measured NF for all phase states is shown
in Fig. 14(e) (4.6–4.8 dB) and is the lowest reported-to-date
for a TRX beamformer chip at 28 GHz.
Previous work using vector modulator phase shifters at Fig. 14. Measured (a) RX channel S-parameters, (b) TX channel
mm-waves have reported significant distortion in phase states S-parameters, (c) RX phase states, (d) RX gain for all phase states, (e) RX
against input power [26], [27]. The measured RX channel NF for all phase states, (f) RX insertion phase versus input power, (g) RX
gain control, (h) TX gain control, (i) channel phase change with gain control,
insertion phase for 16 phase states is shown in Fig. 14(f) and (j) phase shifter rms gain and phase errors.
against input power, and the VM can operate well up to the RX
IP1dB of −22 dBm due to the VM topology employed with
a fixed tail current (see Fig. 8). Beyond P1dB, there is some The measured gain states are shown in Fig. 14(g) and (h).
phase distortion due to AM–PM conversion, but the phase Both TX and RX modes have 14-dB gain control (5-dB
characteristic against input power is similar for all phase states LNA control and 9-dB VGA control for the RX mode) and
and the phase difference is conserved. the measured channel phase change is < ±3° over 14-dB
1268 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 5, MAY 2018

Fig. 17. (a) 4-layer PCB stackup for the low-cost 32-element (4 × 8)
Fig. 15. (a) Measurement setup of the flip-chip TRX array with 2 × 2 TRX array, and (b) top and bottom views of the array PCB with flip-chip
antennas on a PCB. Measured (b) gain and (c) phase of all four channels in beamformer ICs and PCB integrated microstrip antennas.
the RX mode.

Fig. 18. (a) PCB design of the 2 × 2 flip-chip unit cell (M1 and M4 are
shown) and (b) simulated antenna impedance (S11 ) at the chip port including
the antenna feed line.

The chip consumes 130-mW/channel in the RX mode with

an IP1dB of −22 dBm and an input third-order intercept point
(IIP3) of −12 dBm. In the TX mode, the chip consumes
200-mW/channel at the OP1dB of 10.5 dBm. Note that the
RX power consumption is high due to the very high IP1dB
specifications.

V. S YSTEM M EASUREMENTS
A. 2 × 2 TRX Phased-Array Measurements
Fig. 16. Measured EVM using two single-chip TRX array boards at The 2 × 2 TRX chip was first flipped on a test board with
(a) different back-off levels and (b) different symbol rates for various
modulation schemes at 1-m link distance.
a single 6.6-mil RF layer and 2 × 2 antennas on the same
side as the chip, as presented in [28]. The chip was tested in
the RX mode in the far-field using a vector network analyzer
gain control range [Fig. 14(i)]. This allows for a near-perfect (VNA) and a standard gain horn antenna as the transmitter
orthogonality between gain and phase control and allows the [Fig. 15(a)]. The channels were turned on individually using
user to compensate for chip-to-chip variations and taper the the SPI control. A gain difference of ±1 dB [Fig. 15(b)] and
array over a wide range without the need for additional phase a phase difference of ±2° was obtained between the four
trimming. channels within the test antenna S11 bandwidth of 400 MHz
KIBAROGLU et al.: LOW-COST SCALABLE 32-ELEMENT 28-GHz PHASED ARRAY TRANSCEIVER 1269

Fig. 19. Measured (a) E-plane and (b) H-plane patterns of the 4 × 8 TRX array in the RX mode at 29.5 GHz, (c) 3-D pattern (H-plane is shown), and
(d) fine resolution beam steering in the H-plane without calibration. Measured H-plane patterns at boresight (e) without calibration and (f) with calibration.
Calibrated and uncalibrated patterns are almost identical.

[Fig. 15(c)]. The gain difference can easily be corrected using ground plane. The via-fed microstrip antenna can achieve an
the VGA on each channel, but this is not required as presented S11 bandwidth of 2 GHz (28.5–30.5 GHz) when the feed line is
in Section V-B. Also, part of the gain difference could be due included in the antenna-to-chip matching network [Fig. 18(b)].
to standing waves in the test setup. Since the channel responses The antenna efficiency of ∼90% and S11 of −10 dB results
match well, the gain increases as N2 as the number of channels in 1-dB antenna ohmic and mismatch loss. M1 is used for the
increases [Fig. 15(b)]. 8:1 Wilkinson network based on standard λ/4 transmission
The 2 × 2 array has a measured EIRP of 24.5 dBm at lines and lumped 100  resistors are placed on M1 to provide
29 GHz with a 3-dB bandwidth of 28.4–29.4 GHz. A 1-m isolation. M1 and M2 layers are also used as RF ground for the
test link was set up using two of these 2 × 2 TRX arrays and Wilkinson network and for digital control and bias distribution.
the error vector magnitude (EVM) was measured using various The scanning requirements for the 4 × 8 array are ±50° in
modulations and back-off levels (Fig. 16). The back-off level azimuth and ±25° in elevation for a 50–300-m 5G data link.
is defined as the difference between the average symbol power An antenna spacing, d x = 5 mm in the horizontal direction
and the 2 ×2 array P1dB. The maximum data rate measured is (0.5λ at 30 GHz) and d y = 6.3 mm (0.63λ at 30 GHz)
3.6 Gb/s using 64-quadrature amplitude modulation (QAM) at in the vertical direction are chosen to satisfy this scanning
8-dB back-off and 4.0 Gb/s using 16-QAM at 6-dB back-off. requirement without a grating lobe [29]. Note that the antennas
The measured EVM increases above 400-Mbaud symbol rate are vertically polarized, and therefore, the E-plane and H-plane
and is limited by the antenna S11 bandwidth of 400 MHz. scans are in the elevation and azimuth directions, respectively.
The 32-element phased-array antenna patterns were mea-
B. 32-Element (4 × 8) TRX Phased-Array Measurements sured in an anechoic chamber in the RX mode and are shown
To achieve higher EIRP and Gb/s data links at hundreds in Fig. 19. First, the E- and H-plane patterns were measured
of meters, a 32-element (4 × 8) phased-array was designed at 29.5 GHz without any phase or amplitude calibration
with the PCB stackup shown in Fig. 17(a). The cost of this and agree very well with simulations [Fig. 19(a) and (b)].
stackup is very low, since it uses only four RF layers with two The peak of the array pattern closely follows the simulated
RO4350B cores of 13.3-mil thickness. The top and bottom H-plane element factor [∼ cos1.3 (θ )], and the array gain is
views of the 32-element array PCB are shown in Fig. 17(b), 5 dB lower at ±50° scan angle. The sidelobe levels are
and the PCB design of the 2×2 unit cell is shown in Fig. 18(a). < −12 dB over all scan angles (no taper used) due to the
The beamformer chips are flipped on M1, the antennas are symmetric design of the beamformer chips and the Wilkinson
placed on M4, and the chip-to-antenna feed line loss is only distribution network. This shows that the 32-element phased-
0.5 dB at 29 GHz. A 10 mil (250 μm) via hole is used from array can be used without any calibration, thus greatly reduc-
M1 to M4 to feed the antenna, with M3 used as the antenna ing the testing costs. A 3-D pattern plot at boresight from the
1270 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 5, MAY 2018

for 5.6° phase shifter steps, these quantization lobes remain

< −29 dB even at large scan angles [31] and do not appear
in the measured patterns, since they are at a much lower level
than the typical array sidelobes (−12 to −20 dB).
The placement of the chips on the PCB and any small
deviation between the PCB traces will cause slight mismatches
between the phase and gain response of the array elements and
could result in higher sidelobes, wider beamwidth, and lower
EIRP. In order to test this, the 32-element array was calibrated
by measuring the phase and gain of each element in the far-
field using a VNA after turning on the elements individually.
A maximum gain and phase difference of ±1.5 dB and
±10° was measured between the elements. This difference
was then calibrated using the gain and phase control on
each element and the measured boresight H-plane patterns are
shown in Fig. 19(e) and (f) (before and after calibration). The
simulated patterns based on the measured response of each
channel are also plotted and agree well with measurements.
The 3-dB beamwidth at normal incidence is approximated
using
0.886λ
BW3 dB  (4)
Nx d x
for uniform distribution. This results in 12.8° at 29.5 GHz
with the antenna spacing used. With calibration, the 3-dB
beamwidth is reduced from 13.3° to 12.8° which is the
theoretically expected value. However, the sidelobe levels for
Fig. 20. (a) Measured calibrated and uncalibrated EIRP of the 4 × 8 array the uncalibrated array are already < −12 dB, and these
at P1dB and Psat. (b) Measured EIRP versus scan angle in the H-plane at measurements prove that the array can work with excellent
29 GHz.
performance without any calibration.
The 32-element phased-array EIRP was then measured
with and without calibration [Fig. 20(a)]. The peak EIRP is
achieved at 28.5–29 GHz and is 43 dBm at P1dB and 45 dBm
at the saturated output power (Psat ), with a 3-dB bandwidth of
∼27.5–30.5 GHz. The array was calibrated at an input power
close to P1dB in the TX mode at 29 GHz, and therefore,
the calibrated EIRP is 0.5 dB higher than the uncalibrated
EIRP at P1dB at 29 GHz. Note that the uncalibrated phased-
aray Psat levels are slightly higher than the calibrated phased-
array results, since the VGAs are not used to lower the gain
for some channels. The measured EIRP at 29 GHz versus scan
angle in the H-plane is shown in Fig. 20(b) (with and without
calibration) and agrees with the measured H-plane patterns
[Fig. 19(b)]. Overall, the results indicate that the 32-element
Fig. 21. Measured EVM versus symbol rate for different modulation schemes
at 5-m link distance using two 32-element 5G phased-arrays. array operates well without calibration due to its symmetrical
design.
A 5-m link was set up using two 32-element arrays and
H-plane view is shown in Fig. 19(c) and agrees well with the the measured EVM values at normal incidence for different
E- and H-plane 2-D patterns. modulations and symbol rates are shown in Fig. 21 at the
The 6-bit phase shifter step is 5.6° which would result in back-off level equal to the PAPR of the modulated waveform.
a minimum beam step of 1.8° if a progressive phase shift is The maximum measured data rate was 6 Gb/s with 16-QAM
applied between the elements, but the beam can be steered in with 12.6% EVM, again limited by the antenna bandwidth
much finer resolution as demonstrated in [30]. For example, [no forward error correction (FEC) or equalization used]. The
by setting the phases of the eight antenna columns to {0°, array can support up to 2-Gb/s 256-QAM modulation with
0°, 5.6°, 5.6°, 11.2°, 11.2°, 17°, 17°}, the average phase 2.1% EVM. The EVM was then measured using the Verizon
change per unit cell becomes 2.8° and the beam can be steered pre-5G 64-QAM OFDM waveform with eight-component car-
in the H-plane with 1° steps as shown in Fig. 19(d). The riers spaced at 100 MHz. Fig. 22 presents the measured con-
phase interpolation will result in quantization lobes. However, stellations and spectra for the first-two and last-two component
KIBAROGLU et al.: LOW-COST SCALABLE 32-ELEMENT 28-GHz PHASED ARRAY TRANSCEIVER 1271

Fig. 22. Measured constellations and spectra using the Verizon pre-5G 64-QAM orthogonal frequency division multiplexing (OFDM) waveform with eight-
component carriers spaced at 100 MHz (800-MHz total bandwidth). Carrier frequencies and measured EVM values are shown for four carriers with a worst
case EVM of −35.7 dB (1.64%).

performance of the 32-element array at a link distance

of 300 m. Without using digital predistortion (DPD), the TX
array should operate at 6–7-dB back-off for a 16-QAM wave-
form with 2.55-dB PAPR which increases to 6.6 dB when
a root-raised-cosine filter with a roll-off factor α = 0.35 is
applied [32]. This results in an average EIRP of 36–37 dBm
with a peak symbol power of 42–43-dBm under modulation.
The total received power, PR , system noise, PN , and the SNR
at the receiver output are calculated using
PR = EIRP − PLF − L ATM + G ANT − L MIS (5)
PN = 10log(kT(1 + α)B) + NFSYS (6)
SNR = PR − PN (7)
where G ANT is the TRX antenna gain (19 dB) including 1-dB
antenna and mismatch loss and 0.5-dB feed-line loss, L MIS
is the power loss due to array misalignments (1 dB), k is
Boltzmann’s constant, T is the absolute temperature, B is the
modulation bandwidth, NFSYS is the system NF calculated
for Fig. 24(a) (7.5 dB) and EIRP is that of the TX array
at 6–7-dB back-off. Since the receiver SNR is dominated by
the noise floor, other sources of EVM degradation, such as LO
phase noise, receiver I/Q mismatch, and TX nonlinearity can
be ignored in estimating the expected EVM. Any incoming
signal at the image frequency (LO − IF) will also be greatly
attenuated by the narrowband antennas and the TRX chips
and will not degrade the EVM. The calculated SNR is plotted
in Fig. 23(a) for different modulation bandwidths at normal
Fig. 23. Simulated (a) SNR and (b) corresponding EVM at different
modulation bandwidths for a 300-m link using 32-element phased-arrays. incidence, ±50° scan in the azimuth (H-plane) and ±20° scan
in the elevation (E-plane) direction [see Fig. 20(a) and (b)].
carriers. The measured EVM values are shown with the worst Fig. 23(b) presents the corresponding EVM obtained from
case EVM of 1.64% at 12-dB back-off from P1dB. the calculated SNR using

C. 300-Meter 5G Link Measurements EVM(%) = 100 ∗ 10(−(SNR+PAPR)/20) (8)

Based on the EIRP and short distance EVM measurements, where PAPR is that of the ideal constellation before any
a link budget can be calculated to determine the expected filtering is applied [32]. The EVM limits to achieve a bit-error
1272 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 5, MAY 2018

Fig. 24. (a) Measurement setup of the 300-m communication link. (b) Measured constellations at different link distances, data rates, scan angles, and
modulations.

TABLE II
C OMPARISON W ITH S TATE - OF - THE -A RT mm-WAVE P HASED -A RRAY T RANSCEIVERS

rate <10−3 are also marked [33]. Based on these calculations, 1.5-Gb/s (375 Mbaud) using 16-QAM over all scan angles.
the 32-element array can operate at 300 m with a maximum The simulations do not take into account any gain and phase
data rate of 600-Mb/s (100 Mbaud) using 64-QAM, and ripple within the modulation bandwidth due to the components
KIBAROGLU et al.: LOW-COST SCALABLE 32-ELEMENT 28-GHz PHASED ARRAY TRANSCEIVER 1273

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IEEE Trans. Microw. Theory Techn., vol. 60, no. 11, pp. 3431–3439, nication engineering from Istanbul Technical Uni-
Nov. 2012. versity (ITU), Istanbul, Turkey, in 2004, 2007, and
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[29] C. A. Balanis, Antenna Theory: Analysis and Design, 4th ed. Hoboken, Gabriel M. Rebeiz (S’86–M’88–SM’93–F’97)
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[30] B. H. Ku et al., “A 77–81-GHz 16-element phased-array receiver with Institute of Technology, Pasadena, CA, USA.
±50◦ beam scanning for advanced automotive radars,” IEEE Trans. From 1988 to 2004, he was with the University
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[31] M. Skolnik, Ed., Radar Handbook, 3rd ed. New York, NY, USA: optimized the dielectric-lens antenna which is the
McGraw-Hill, 2008. most widely used antenna at millimeter-wave and
[32] (1994). Characteristics of Digital Fixed Wireless Systems Below terahertz frequencies. His group also developed
About 17 GHz. [Online]. Available: http://www.itu.int/dms_pubrec/itu- 6–18-GHz, 30–35-GHz, 40–50-GHz, 77–86-GHz,
r/rec/f/R-REC-F.1101-0-199409-I!PDF-E.pdf and 90–110-GHz 8- and 16-element phased
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IEEE J. Solid-State Circuits, vol. 52, no. 9, pp. 2277–2291, Sep. 2017. phased arrays with on-chip antennas, and the first SiGe millimeter-wave
silicon passive imager chip at 85–105 GHz. His group also demonstrated
high-performance RF MEMS tunable filters at 0.7–6 GHz, RF MEMS
phase shifters at 1–100 GHz, and high-power high-reliability RF MEMS
metal-contact switches. As a consultant, he helped develop 24- and 77-GHz
single-chip SiGe automotive radars, phased arrays operating at X- to
W-band for defense and commercial applications, such as SATCOM,
automotive, and point-to-point, digital beamforming systems, and several
industrial RF MEMS switches. He is currently a member of the National
Academy, a Distinguished Professor and the Wireless Communications
Industry Chair Professor in electrical and computer engineering with
the University of California at San Diego (UCSD), La Jolla, CA, USA.
He has authored or coauthored over 650 IEEE publications, and authored
the book RF MEMS: Theory, Design and Technology (Wiley, 2003). He has
graduated 64 Ph.D. students and 21 post-doctoral Fellows. He currently leads a
group of 18 Ph.D. students and post-doctoral Fellows in the area of millimeter-
wave radio-frequency integrated circuits (RFICs), tunable microwave circuits,
RF MEMS, and planar millimeter-wave antennas and terahertz systems.
Dr. Rebeiz was a recipient of the URSI Koga Gold Medal, the IEEE
Microwave Theory and Technique Society (IEEE MTT-S) 2000 and
2014 Microwave Prize, the IEEE MTT-S 2010 Distinguished Educator Award,
the IEEE Antennas and Propagation Society (AP-S) 2011 John D. Kraus
Kerim Kibaroglu (S’13) received the B.S. degree Antenna Award, the 2012 Intel Semiconductor Technology Council
in electronics engineering from Sabancı University, Outstanding Researcher in Microsystems, an R&D100 2014 Award for his
Istanbul, Turkey, in 2013, and the M.S. degree in work on phased-array automotive radars, the 2014 IEEE Daniel E. Noble
electrical and computer engineering from the Uni- Field Medal for his work on RF MEMS, and the IEEE AP-S 2015
versity of California at San Diego, La Jolla, CA, Harold A. Wheeler Applications Prize Paper Award. He was also a
USA, in 2015, where he is currently pursuing the recipient of the 1997–1998 Eta Kappa Nu Professor of the Year Award,
Ph.D. degree. the 1998 College of Engineering Teaching Award, and the 1998 Amoco
In 2017, he was an Intern with Intel Corpora- Teaching Award given to the best undergraduate teacher at the University
tion, Hillsboro, OR, USA, where he was involved of Michigan, and the 2008 Teacher of the Year Award of the Jacobs School
in millimeter-wave circuits for 5G systems. His of Engineering, UCSD. He was a National Science Foundation Presidential
current research interests include RF/analog and Young Investigator and the 2003 IEEE MTT-S Distinguished Young Engineer.
millimeter-wave integrated circuits and systems in silicon technologies for His students have received a total of 22 Best Paper Awards from the IEEE
wideband receivers and phased-array systems for high data rate wireless MTT-S, RFICs, and AP-S conferences. He has been an Associate Editor of
communications. the IEEE T RANSACTIONS ON M ICROWAVE T HEORY AND T ECHNIQUES ,
Mr. Kibaroglu was a recipient of the Analog Devices Outstanding Student and a Distinguished Lecturer of the IEEE MTT-S, the IEEE AP-S, and the
Designer Award in 2016. IEEE Solid-State Circuits Society.