Programmable Interrupt Controller: Submitted To

8259 (PIC)
PROGRAMMABLE INTERRUPT
CONTROLLER
Submitted To:
Dr. Shaheena Sultana
Associate Professor ,
Notre Dame University Bangladesh
Submitted By:
MD. JAHIDUL ISLAM
ID:181120023
INTRODUCTION TO 8259 (PIC)
• 8259 microprocessor is defined as Programmable Interrupt
Controller (PIC) microprocessor. There are 5 hardware
interrupts and 2 hardware interrupts in 8086. By connecting
8259 with CPU, we can increase the interrupt handling
capability. 8259 combines the multi- interrupt input sources into
a single interrupt output. Interfacing of single Programmable
Interrupt Controller provides 8 interrupts inputs from IR0-IR7.
• For example, Interfacing of 8086 and 8259 increases the

interrupt handling capability of 8086 microprocessor from 5 to 8
interrupt levels
8259
Features of 8259 (PIC) Microprocessor
• 8259 is designed for 8085 and 8086 microprocessor.

• It can be programmed either in level triggered or in edge
triggered interrupt level.
• We can masked individual bits of interrupt request register.
• We can increase interrupt handling capability upto 64 interrupt
level by cascading further 8259 Programmable Interrupt
Controller.
• Clock cycle is not required.
PIN CONFIGURATION
Pins
VCC: 5V Power Supply.
GND: Ground.
CS (Chip Select): It works when it is active low. This pin enables
RD and WR operation between CPU and 8259.
WR(Write): It works when it is active low. When CS is low ,
enables 8259 for write operation and also enables to accept
command words from the CPU.
RD(Read): It works when it is active low. It enables 8259 to
release status onto the data bus for the CPU.
D0-D7(I/O Bi-directional Data Bus) : Used as bi-directional data
bus. Transfer the control , status and interrupt-vector information
through this bus.
CAS0-CAS2 (I/O Cascade Lines): It is used to control a multiple

8259 Structure. These pins are outputs for a master 8259A and
inputs for a slave 8259.
SP/EN(I/O Slave Program/Enable Buffer): A dual function pin. A

active low pin. When it is used in buffer mode , it can be used as
an output to control buffer transceivers(EN). If it is not in buffer
mode , it is used as an input to designate a master (SP=1) or
slave (SP=0)
INT(Interrupt): A active high pin. Used to interrupt the CPU.

IR0-IR7(Interrupt Request): There are Eight asynchronous
interrupt request inputs. These interrupt requests can be
programmed for level-trigger or edge-triggered mode.
INTA(Interrupt Acknowledge): This pin is active low when a

valid interrupt request is asserted. Use to enable 8259 interrupt
vector data onto the data bus by a sequence of interrupt
acknowledge pulse issued by the CPU.
A0(Address Line): Works in the conjunction with the CS , WR

and RD pins. Used to read various commands words the CPU
writes and the status the CPU wishes to read by 8259.
Connected to the CPU A0 address line.
It 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade
Buffer Comparator, Control Logic, Priority Resolver and 3 registers- ISR,
IRR, IMR.
Data bus buffer –
This Block is used as a mediator between 8259 and 8086
microprocessor by acting as a buffer. It takes the control word from the
8086 microprocessor and transfer it to the control logic of 8259
microprocessor. After selection of Interrupt by 8259 microprocessor, it
transfer the opcode of the selected Interrupt and address of the Interrupt
service sub routine to the other connected microprocessor. The data
bus buffer consists of 8 bits represented as D0-D7. Thus, shows that a
maximum of 8 bits data can be transferred at a time.
Read/Write logic –
This block works only when the value of pin CS is low (as this pin is
active low). This block is responsible for the flow of data depending
upon the inputs of RD and WR. These two pins are active low pins used
for read and write operations.
Control logic –
It is the center of the microprocessor and controls the functioning of every
block. It has pin INTR which is connected with other microprocessor for
taking interrupt request and pin INT for giving the output. If 8259 is enabled,
and the other microprocessor Interrupt flag is high then this causes the
value of the output INT pin high and in this way 8259 responds to the
request made by other microprocessor
Interrupt request register (IRR) –

It stores all the interrupt level which are requesting for Interrupt services.
Interrupt service register (ISR) –

It stores the interrupt level which are currently being executed.
Interrupt mask register (IMR) –

It stores the interrupt level which have to be masked by storing the masking
bits of the interrupt level.
Priority resolver –
It examines all the three registers and set the priority of interrupts and according to the
priority of the interrupts, interrupt with highest priority is set in ISR register. Also, it reset the
interrupt level which is already been serviced in IRR.
Cascade buffer –
To increase the Interrupt handling capability, we can further cascade more number of pins
by using cascade buffer. So, during increment of interrupt capability, CSA lines are used to
control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) – This pin is set to high when it works in master
mode else in slave mode. In Non Buffered mode, SP/EN pin is used to specify whether
8259 work as master or slave and in Buffered mode, SP/EN pin is used as an output to
enable data bus.
8259 interfacing with 8086
CONNECTIONS:
The data lines of an 8259 are connected to the lower half of the system data bus;
because the 8086 expects to receive interrupt types on these lower eight data lines
The interrupt request signal INT from the 8259 is connected to the INTR input of
the 8086
INTA from the 8086 is connected to INTA on the 8259.

THANK YOU

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8259 (PIC)

• For example, Interfacing of 8086 and 8259 increases the

• 8259 is designed for 8085 and 8086 microprocessor.

CAS0-CAS2 (I/O Cascade Lines): It is used to control a multiple

SP/EN(I/O Slave Program/Enable Buffer): A dual function pin. A

INT(Interrupt): A active high pin. Used to interrupt the CPU.

INTA(Interrupt Acknowledge): This pin is active low when a

A0(Address Line): Works in the conjunction with the CS , WR

Interrupt request register (IRR) –

Interrupt service register (ISR) –

Interrupt mask register (IMR) –

INTA from the 8086 is connected to INTA on the 8259.

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