8259A Programmable Interrupt Controller

8259A PROGRAMMABLE
INTERRUPT CONTROLLER
8259A PIC
Able to handle a number of interrupts at a
time.
Takes care of a number of simultaneously
appearing interrupt requests along with
their types and priorities.
Compatible with 8-bit as well as 16-bit
processors.
8259A PIC- FEATURES
Manage 8 interrupts according to the
instructions written into the control registers.
Vector an interrupt request anywhere in the
memory map. However all the 8 interrupts are
spaced at an interval of four to eight locations.
Resolve 8 levels of interrupt priorities in variety
of modes.
Mask each interrupt request individually.
Read the status of pending interrupts, in-service
interrupts and masked interrupts.
8259A PIC- FEATURES
Be set up to accept either the level triggered or
the edge triggered interrupt request.
Be expanded to 64 priority levels by cascading
additional 8259As.
Compatible with 8-bit as well as 16-bit
processors.
8259A PIC- BLOCK DIAGRAM
It includes 8 blocks.
Control logic
Read/Write logic
Data bus buffer
Three registers (IRR,ISR and IMR)
Priority resolver
Cascade Buffer
8259A PIC- INTERRUPTS AND CONTROL
LOGIC SECTION
This section consists of
IRR (Interrupt
IRR
Request Register) 8 interrupt inputs set
corresponding bits of
ISR (In-Service
IRR
Register)
Used to store the
Priority Resolver
information about the
IMR (Interrupt Mask interrupt inputs
Register) requesting service.
Control logic block
LOGIC SECTION
ISR PRIORITY RESOLVER
Determines the priorities of

Used to store information interrupts requesting services
(which set corresponding bits
about the interrupts of IRR)
currently being serviced. It determines the priorities as
dictated by priority mode set by
OCWs.
The bit corresponding to
* OCWs Operation highest priority input is set in
Control Word. ISR during input.
Examines three registers and
determines whether INT
should be sent to MPU.
LOGIC SECTION
IMR
This register can be programmed by an OCW to
store the bits which mask specific interrupts.
IMR operates on the IRR.
An interrupt which is masked by software (By
programming the IMR) will not be recognized
and serviced even if it sets corresponding bits in
the IRR.
LOGIC SECTION
CONTROL LOGIC
Has two pins:
INT (Interrupt) Output
( Interrupt Acknowledge) Input
INT Connected to Interrupt pin of MPU.
When interrupt occurs this pin goes high.
DATA BUS BUFFER
8 bit
Bidirectional
Tri-state Buffer used to Interface the 8259 to the
system data bus.
Control words, Status words and vectoring data
are all passed through the data bus buffer.
8259A PIC- CASCADE BUFFER/
COMPARATOR
Generates control signals for cascade operation.
Also generates buffer enable signals.
8259 cascaded with other 8259s
Interrupt handling capacity to 64 levels
Former is called master and latter is slave.
8259 can be set up as master or slave by
pin in non-buffered mode or by software if it is to
be operated in the buffered mode of operation.
8259A PIC- INTERRUPT OPERATION
To implement interrupt, the interrupt Enable FF must be
enabled by writing EI instruction.
8259A should be initialized by writing control words in
the control register.
8259 requires two types of control words:
ICW Used to set up proper conditions
and specify RST vector address.
OCW Used to perform functions such as
masking interrupts, setting up status
read operations etc.
After 8259A is initialized, the following sequence of
events occurs when one or more interrupt request lines
go high.
1. IRR stores the Interrupt requests.

2. Priority Resolver Checks three registers:
IRR for interrupt requests.
IMR for Masking bits.
ISR for the interrupt request being serviced.
It resolves the priority and sets the INT high
when appropriate.
3. MPU acknowledges the interrupt by sending
interrupt acknowledge.
4. After is received, the appropriate priority

bit in the ISR is set to indicate which level is
being served and the corresponding bit in the
IRR is reset to that request is accepted. Then
op-code for CALL instruction is placed on the
Data Bus.
5. When MPU decodes the CALL instruction, it
places two more signals on the data
bus.
6. When 8259 receives second , it

places lower order byte of CALL address
on the data bus.
Third High order byte.
The CALL address is the vector memory
location for the interrupt. This address is
placed in control register during
initialization.
7. During third pulse, the ISR bit is reset

either automatically (AEOI) or by a command
word that must be issued at the end of the
service routine (EOI). This option is determined
by the ICW.
8. The program sequence is transferred to the
memory location specified by the CALL
instruction.
AEOI Automatic End of Interrupt Mode
EOI End of Interrupt Mode
8259A- OPERATING MODES
FULLY NESTED MODE:
General purpose mode.
All IRs are arranged from highest to lowest.
IR0 Highest IR7Lowest
AUTOMATIC ROTATION MODE:

In this mode, a device after being serviced, receives the
lowest priority.
SPECIFIC ROTATION MODE:

Similar to automatic rotation mode, except that the user
can select any IR for the lowest priority, thus fixing all
other priorities.

8259A Programmable Interrupt Controller

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8259A PROGRAMMABLE

Determines the priorities of

1. IRR stores the Interrupt requests.

4. After is received, the appropriate priority

6. When 8259 receives second , it

7. During third pulse, the ISR bit is reset

AUTOMATIC ROTATION MODE:

SPECIFIC ROTATION MODE:

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