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TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133

SLVSAG7E – NOVEMBER 2011 – REVISED AUGUST 2016

TPS6213x 3-V to17-V, 3-A Step-Down Converter In 3x3 QFN Package

1 Features 3 Description
•
1 DCS-Control™ Topology The TPS6213X family is an easy to use synchronous
step down DC-DC converter optimized for
• Input Voltage Range: 3 to 17V applications with high power density. A high switching
• Up to 3A Output Current frequency of typically 2.5MHz allows the use of small
• Adjustable Output Voltage from 0.9 to 6V inductors and provides fast transient response as well
• Pin-Selectable Output Voltage (nominal, + 5%) as high output voltage accuracy by use of the DCS-
Control™ topology.
• Programmable Soft Start and Tracking
With their wide operating input voltage range of 3V to
• Seamless Power Save Mode Transition
17V, the devices are ideally suited for systems
• Quiescent Current of 17µA (typ.) powered from either a Li-Ion or other batteries as well
• Selectable Operating Frequency as from 12V intermediate power rails. It supports up
• Power Good Output to 3A continuous output current at output voltages
between 0.9V and 6V (with 100% duty cycle mode).
• 100% Duty Cycle Mode The output voltage startup ramp is controlled by the
• Short Circuit Protection soft-start pin, which allows operation as either a
• Over Temperature Protection standalone power supply or in tracking configurations.
Power sequencing is also possible by configuring the
• Pin to Pin Compatible with TPS62140 and
Enable and open-drain Power Good pins.
TPS62150
• Available in a 3 × 3 mm, QFN-16 Package In Power Save Mode, the devices draw quiescent
current of about 17μA from VIN. Power Save Mode,
entered automatically and seamlessly if load is small,
2 Applications maintains high efficiency over the entire load range.
• Standard 12-V Rail Supplies In Shutdown Mode, the device is turned off and
• POL Supply from Single or Multiple Li-Ion Battery shutdown current consumption is less than 2μA.
• Solid-State Disk Drives The device, available in adjustable and fixed output
• Embedded Systems voltage versions, is packaged in a 16-pin VQFN
package measuring 3 × 3 mm (RGT).
• LDO replacement
• Mobile PCs, Tablet, Modems, Cameras Device Information(1)
• Server, Microserver PART NUMBER PACKAGE BODY SIZE (NOM)
• Data Terminal, Point of Sales (ePOS) TPS6213x VQFN (16) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.

Typical Application Schematic Efficiency vs Output Current

(3 .. 17)V 1 / 2.2 µH 1.8V / 3A 100
PVIN SW

AVIN VOS 100kΩ 90

10μF 0.1μF
EN PG 22μF
TPS62131 VIN=5V VIN=12V VIN=17V
80
Efficiency (%)

SS/TR FB
3.3nF
DEF AGND
70
FSW PGND

60
Copyright © 2016, Texas Instruments Incorporated
50 VOUT=3.3V
fsw=1.25MHz
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Output Current (A) G001

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133
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Table of Contents
1 Features .................................................................. 1 9.1 Application Information............................................ 13
2 Applications ........................................................... 1 9.2 Typical Application ................................................. 13
3 Description ............................................................. 1 9.3 System Examples ................................................... 25
4 Revision History..................................................... 2 10 Power Supply Recommendations ..................... 29
5 Device Comparison Table..................................... 4 11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
6 Pin Configuration and Functions ......................... 4
11.2 Layout Example .................................................... 30
7 Specifications......................................................... 5
11.3 Thermal Information .............................................. 31
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5 12 Device and Documentation Support ................. 32
12.1 Device Support .................................................... 32
7.3 Recommended Operating Conditions....................... 5
12.2 Documentation Support ....................................... 32
7.4 Thermal Information .................................................. 5
12.3 Receiving Notification of Documentation Updates 32
7.5 Electrical Characteristics........................................... 6
12.4 Related Links ........................................................ 32
7.6 Typical Characteristics .............................................. 7
12.5 Community Resources.......................................... 33
8 Detailed Description .............................................. 8
12.6 Trademarks ........................................................... 33
8.1 Overview ................................................................... 8
12.7 Electrostatic Discharge Caution ............................ 33
8.2 Functional Block Diagram ......................................... 8
12.8 Glossary ................................................................ 33
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 11 13 Mechanical, Packaging, and Orderable
Information ........................................................... 33
9 Application and Implementation ........................ 13

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (June 2016) to Revision E Page

• Changed the TJ MAX value From: 125°C To: 150°C in the Absolute Maximum Ratings ..................................................... 5
• Changed (TJ = –40°C to 85°C) To: (TJ = –40°C to 125°C) in the Electrical Characteristics conditions ................................ 6
• Added a test condition for IQ at TA = -40°C to +85°C in the Electrical Characteristics........................................................... 6
• Added Table 1 and Table 2 ................................................................................................................................................. 10

Changes from Revision C (January 2015) to Revision D Page

• Added "Pin to Pin Compatible with TPS62140 and TPS62150" to Features list .................................................................. 1
• Added "Server, Microserver"; and, "Data Terminal, Point of Sales (ePOS)" to Applications list ........................................... 1
• Changed the Device Comparison Table format ..................................................................................................................... 4
• Changed Thermal Information table ...................................................................................................................................... 5
• Added Switching Frequency graphs for 1.0-V, 1.8-V, and 5.0-V applications. .................................................................... 20
• Corrected System Examples schematics. ............................................................................................................................ 25
• Changed Layout Example pictorial....................................................................................................................................... 30
• Added Community Resources section ................................................................................................................................ 33

Changes from Revision B (June 2013) to Revision C Page

• Added Device Information and ESD Rating tables, Feature Description section, Device Functional Modes,
Programming section, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
• Added "(PWM mode operation)" text string to VUVLO spec Test Conditions for clarification. ................................................. 6
• Changed second paragraph of SS/TR description for clarification. .................................................................................... 10

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Changes from Revision A (September 2012) to Revision B Page

• Added device TPS62130A to data sheet Header................................................................................................................... 1

• Added device TPS62130A to Device Comparison table. ....................................................................................................... 4
• Added text to Power Good section regarding TPS63130A. ................................................................................................. 10
• Added pin option to Footnote statement for Pin-Selectable Output Voltage (DEF) section................................................. 10
• Added text to Frequency Selection (FSW) section regarding pin control............................................................................. 11
• Added text to Tracking Function section for clarification. ..................................................................................................... 17
• Added application example regarding TPS62130A device. ................................................................................................. 25

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5 Device Comparison Table

PART NUMBER OUTPUT VOLTAGE Power Good Logic Level (EN=Low)

TPS62130 adjustable High Impedance
TPS62130A adjustable Low
TPS62131 1.8 V High Impedance
TPS62132 3.3 V High Impedance
TPS62133 5.0 V High Impedance

6 Pin Configuration and Functions

16-Pin VQFN With Exposed Thermal Pad (RGT)

Top View

PGND

PGND

VOS

EN
16 15 14 13

SW 1 12 PVIN

SW 2 Exposed 11 PVIN
Thermal Pad
SW 3 10 AVIN

PG 4 9 SS/TR

5 6 7 8
FSW

DEF
FB

AGND

Pin Functions
PIN (1)
I/O DESCRIPTION
NO. NAME
1,2,3 SW O Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and
output capacitor.
4 PG O Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires
pull-up resistor)
5 FB I Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is recommended
to connect FB to AGND on fixed output voltage versions for improved thermal performance.
6 AGND Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
7 FSW I Switching Frequency Select (Low ≈ 2.5MHz, High ≈ 1.25MHz (2) for typical operation) (3)
8 DEF I Output Voltage Scaling (Low = nominal, High = nominal + 5%) (3)
Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference
9 SS/TR I
rise time. It can be used for tracking and sequencing.
10 AVIN I Supply voltage for control circuitry. Connect to same source as PVIN.
11,12 PVIN I Supply voltage for power stage. Connect to same source as AVIN.
13 EN I Enable input (High = enabled, Low = disabled) (3)
14 VOS I Output voltage sense pin and connection for the control loop circuitry.
15,16 PGND Power Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
Exposed Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane. See the Layout
Thermal Pad Example. Must be soldered to achieve appropriate power dissipation and mechanical reliability.

(1) For more information about connecting pins, see Detailed Description and Application and Implementation sections.
(2) Connect FSW to VOUT or PG in this case.
(3) An internal pull-down resistor keeps logic level low, if pin is floating.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating junction temperature range (unless otherwise noted)
MIN MAX UNIT
AVIN, PVIN –0.3 20
V
EN, SS/TR –0.3 VIN+0.3
Pin voltage range (2)
SW –0.3 VIN+0.3 V
DEF, FSW, FB, PG, VOS –0.3 7 V
Power Good sink current PG 10 mA
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.

7.2 ESD Ratings

VALUE UNIT
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge (1) Charged-device model (CDM), per JEDEC specification JESD22- V
±500
C101 (3)

(1) ESD testing is performed according to the respective JESD22 JEDEC standard.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN MAX UNIT
Supply Voltage, VIN (at AVIN and PVIN) 3 17 V
Operating junction temperature, TJ –40 125 °C

7.4 Thermal Information

TPS6213X
THERMAL METRIC (1) UNITS
RGT 16 PINS
RθJA Junction-to-ambient thermal resistance 45
RθJCtop Junction-to-case(top) thermal resistance 53.6
RθJB Junction-to-board thermal resistance 17.4
°C/W
ψJT Junction-to-top characterization parameter 1.1
ψJB Junction-to-board characterization parameter 17.4
RθJCbot Junction-to-case(bottom) thermal resistance 4.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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7.5 Electrical Characteristics

over operating junction temperature (TJ = –40°C to 125°C), typical values at VIN = 12 V and TA=25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range (1) 3 17 V
EN=High, IOUT = 0 mA, 17 30
IQ Operating quiescent current µA
device not switching TA = -40°C to +85°C 17 25
ISD 1.5 25
Shutdown current (2) EN=Low µA
TA = -40°C to +85°C 1.5 4
VUVLO Falling Input Voltage (PWM mode operation) 2.6 2.7 2.8 V
Undervoltage lockout threshold
Hysteresis 200 mV
TSD Thermal shutdown temperature 160
°C
Thermal shutdown hysteresis 20
CONTROL (EN, DEF, FSW, SS/TR, PG)
High level input threshold voltage (EN,
VH 0.9 0.65 V
DEF, FSW)
VL Low level input threshold voltage (EN, 0.45
0.3 V
DEF, FSW)
ILKG Input leakage current (EN, DEF, FSW) EN=VIN or GND; DEF, FSW=VOUT or GND 0.01 1 µA
Rising (%VOUT) 92% 95% 98%
VTH_PG Power good threshold voltage
Falling (%VOUT) 87% 90% 94%
VOL_PG Power good output low IPG=–2mA 0.07 0.3 V
ILKG_PG Input leakage current (PG) VPG=1.8V 1 400 nA
ISS/TR SS/TR pin source current 2.3 2.5 2.7 µA
POWER SWITCH
VIN≥6V 90 170
High-side MOSFET ON-resistance mΩ
VIN=3V 120
RDS(ON)
VIN≥6V 40 70
Low-side MOSFET ON-resistance mΩ
VIN=3V 50
High-side MOSFET forward current VIN =12V, TA= 25°C
ILIMF 3.6 4.2 4.9 A
limit (3)
OUTPUT
ILKG_FB Input leakage current (FB) TPS62130, VFB=0.8V 1 100 nA
Output voltage range (TPS62130) VIN ≥ VOUT 0.9 6.0 V
DEF (Output voltage programming) DEF=0 (GND) VOUT
DEF=1 (VOUT) VOUT+5%
PWM mode operation, VIN ≥ VOUT +1V 785.6 800 814.4
PWM mode operation, VIN ≥ VOUT +1V,
Initial output voltage accuracy (4) 788.0 800 812.8 mV
VOUT TA = –10°C to 85°C
Power Save Mode operation, COUT=22µF 781.6 800 822.4
Tracking Feedback Voltage (TPS62130) VSS/TR = 350mV 212.6 225 237.4 mV
Load regulation (5) VIN=12V, VOUT=3.3V, PWM mode operation 0.05 %/A
3V ≤ VIN ≤ 17V, VOUT=3.3V, IOUT= 1A, PWM
Line regulation (5) 0.02 %/V
mode operation

(1) The device is still functional down to Under Voltage Lockout (see parameter VUVLO).
(2) Current into AVIN+PVIN pin.
(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit And Short
Circuit Protection section).
(4) This is the accuracy provided at the FB pin for the adjustable VOUT version (line and load regulation effects are not included). For the
fixed output voltage versions the (internal) resistive divider is included.
(5) Line and load regulation depend on external component selection and layout (see Figure 22 and Figure 23).

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7.6 Typical Characteristics

Figure 1. Quiescent Current Figure 2. Shutdown Current

200.0 100.0
180.0
160.0 125°C 80.0
RDSon High−Side (mΩ)

RDSon Low−Side (mΩ)

140.0 125°C
120.0 85°C 60.0 85°C
100.0 25°C
25°C
80.0 40.0
60.0 −10°C
−10°C
40.0 −40°C 20.0 −40°C
20.0
0.0 0.0
0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0 0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0
Input Voltage (V) G001 Input Voltage (V) G001

Figure 3. High-Side Switch Resistance Figure 4. Low-Side Switch Resistance

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8 Detailed Description

8.1 Overview
The TPS6213X synchronous switched mode power converters are based on DCS-Control™ (Direct Control with
Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of
hysteretic, voltage mode and current mode control including an AC loop directly associated to the output voltage.
This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage.
It sets the switching frequency, which is constant for steady state operating conditions, and provides immediate
response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The
internally compensated regulation network achieves fast and stable operation with small external components
and low ESR capacitors.
The DCS-ControlTM topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.5MHz or 1.25MHz with a controlled frequency
variation depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to
sustain high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly
with the load current. Since DCS-ControlTM supports both operation modes within one single building block, the
transition from PWM to Power Save Mode is seamless without effects on the output voltage.
Fixed output voltage versions provide smallest solution size and lowest current consumption, requiring only 4
external components. An internal current limit supports nominal output currents of up to 3A.
The TPS6213X family offers both excellent DC voltage and superior load transient regulation, combined with
very low output voltage ripple, minimizing interference with RF circuits.

8.2 Functional Block Diagram

PG AVIN PVIN PVIN

Soft Thermal
UVLO PG control
start Shtdwn
HS lim

comp

EN*
SW
SS/TR
power gate
control logic SW
control drive
*
DEF
SW
FSW*

comp

LS lim

VOS direct control

& ramp
compensation

_
FB comparator timer tON
error
amplifier
+
DCS - ControlTM

*
This pin is connected to a pull down resistor internally AGND PGND PGND
(see Feature Description section).

* This pin is connected to a pull down resistor internally (see Feature Description section).

Figure 5. TPS62130 and TPS62130A (Adjustable Output Voltage)

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Functional Block Diagram (continued)

PG AVIN PVIN PVIN

Soft Thermal
UVLO PG control
start Shtdwn
HS lim

comp

EN*
SW
SS/TR
power gate
control logic SW
control drive
DEF*
SW
FSW*

comp

LS lim

VOS direct control

& ramp
compensation

_
FB* comparator timer tON
error
amplifier
+
DCS - ControlTM

*
This pin is connected to a pull down resistor internally AGND PGND PGND
(see Feature Description section).

* This pin is connected to a pull down resistor internally (see Feature Description section).

Figure 6. TPS62131/2/3 (Fixed Output Voltage)

space

8.3 Feature Description

8.3.1 Enable / Shutdown (EN)
When Enable (EN) is set High, the device starts operation. Shutdown is forced if EN is pulled Low with a
shutdown current of typically 1.5µA. During shutdown, the internal power MOSFETs as well as the entire control
circuitry are turned off. The internal resistive divider pulls down the output voltage smoothly. The EN signal must
be set externally to High or Low. An internal pull-down resistor of about 400kΩ is connected and keeps EN logic
low, if Low is set initially and then the pin gets floating. It is disconnected if the pin is set High.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.

8.3.2 Soft Start / Tracking (SS/TR)

The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high-
impedance power sources or batteries. When EN is set to start device operation, the device starts switching after
a delay of about 50µs and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR
pin. See Figure 40 and Figure 41 for typical startup operation.

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Feature Description (continued)

Using a very small capacitor (or leaving SS/TR pin un-connected) provides fastest startup behavior. There is no
theoretical limit for the longest startup time. The TPS6213X can start into a pre-biased output. During monotonic
pre-biased startup, both the power MOSFETs are not allowed to turn on until the device's internal ramp sets an
output voltage above the pre-bias voltage. As long as the output is below about 0.5V a reduced current limit of
typically 1.6A is set internally. If the device is set to shutdown (EN=GND), undervoltage lockout or thermal
shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low level. Returning from those states
causes a new startup sequence as set by the SS/TR connection.
A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage will follow this voltage
in both directions up and down (see Application and Implementation).

8.3.3 Power Good (PG)

The TPS6213X has a built in power good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an
open-drain output that requires a pull-up resistor (to any voltage below 7 V). It can sink 2 mA of current and
maintain its specified logic low level. With TPS62130 it is high impedance when the device is turned off due to
EN, UVLO or thermal shutdown. TPS62130A features PG=Low in this case and can be used to actively
discharge VOUT (see Figure 47). VIN must remain present for the PG pin to stay Low. See SLVA644 for
application details. If not used, the PG pin should be connected to GND but may be left floating.
space

Table 1. Power Good Pin Logic Table (TPS62130)

PG Logic Status
Device State
High Impedance Low
VFB ≥ VTH_PG √
Enable (EN=High)
VFB ≤ VTH_PG √
Shutdown (EN=Low) √
UVLO 0.7 V < VIN < VUVLO √
Thermal Shutdown TJ > TSD √
Power Supply Removal VIN < 0.7 V √

space

Table 2. Power Good Pin Logic Table (TPS62130A)

PG Logic Status
Device State
High Impedance Low
VFB ≥ VTH_PG √
Enable (EN=High)
VFB ≤ VTH_PG √
Shutdown (EN=Low) √
UVLO 0.7 V < VIN < VUVLO √
Thermal Shutdown TJ > TSD √
Power Supply Removal VIN < 0.7 V √

space

8.3.4 Pin-Selectable Output Voltage (DEF)

The output voltage of the TPS6213X devices can be increased by 5% above the nominal voltage by setting the
DEF pin to High (1). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal
voltage allows adapting the power supply voltage to the variations of the application hardware. More detailed
information on voltage margining using TPS6213X can be found in SLVA489. A pull down resistor of about 400
kΩ is internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating after
initially set to Low. The resistor is disconnected if the pin is set High.
(1) Maximum allowed voltage is 7 V. Therefore, it is recommended to connect it to VOUT or PG, not VIN.
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8.3.5 Frequency Selection (FSW)

To get high power density with very small solution size, a high switching frequency allows the use of small
external components for the output filter. However switching losses increase with the switching frequency. If
efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz
typ.) by pulling FSW to High. It is mandatory to start with FSW=Low to limit inrush current, which can be done by
connecting to VOUT or PG. Running with lower frequency a higher efficiency, but also a higher output voltage
ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typ.). To get low ripple and full output
current at the lower switching frequency, it's recommended to use an inductor of at least 2.2 µH. The switching
frequency can be changed during operation, if needed. A pull down resistor of about 400kOhm is internally
connected to the pin, acting the same way as at the DEF Pin (see above).

8.3.6 Under Voltage Lockout (UVLO)

If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the
power FETs. The under voltage lockout threshold is set typically to 2.7V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 200mV.

8.3.7 Thermal Shutdown

The junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 160°C
(typ), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG
goes high impedance. When Tj decreases below the hysteresis amount, the converter resumes normal
operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented
on the thermal shut down temperature.

8.4 Device Functional Modes

8.4.1 Pulse Width Modulation (PWM) Operation
The TPS6213X operates with pulse width modulation in continuous conduction mode (CCM) with a nominal
switching frequency of 2.5 MHz or 1.25 MHz, selectable with the FSW pin. The frequency variation in PWM is
controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output
current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device
enters Power Save Mode at the boundary to discontinuous conduction mode (DCM). This happens if the output
current becomes smaller than half the inductor's ripple current.

8.4.2 Power Save Mode Operation

The TPS6213X enters its built in Power Save Mode seamlessly if the load current decreases. This secures a
high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor current is
discontinuous.
In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in
both directions.
TPS6213X includes a fixed on-time circuitry. An estimate for this on-time, in steady-state operation with FSW =
Low, is:
space
VOUT
t ON = × 400ns
V IN (1)
space
For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also the off-time can
reach its minimum value at high duty cycles. The output voltage remains regulated in such case. Using tON, the
typical peak inductor current in Power Save Mode can be approximated by:
space

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Device Functional Modes (continued)

(V IN - VOUT )
I LPSM ( peak ) = × t ON
L (2)
space
When VIN decreases to typically 15% above VOUT, the TPS6213X won't enter Power Save Mode, regardless of
the load current. The device maintains output regulation in PWM mode.

8.4.3 100% Duty-Cycle Operation

The duty cycle of the buck converter is given by D=VOUT/VIN and increases as the input voltage comes close to
the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal set
point. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of
battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
spacing
VIN (min) = VOUT (min) + I OUT (RDS ( on ) + RL ) (3)
where
IOUT is the output current,
RDS(on) is the RDS(on) of the high-side FET and
RL is the DC resistance of the inductor used.

8.4.4 Current Limit And Short Circuit Protection

The TPS6213X devices have protection against heavy load and short circuit events. If a short circuit is detected
(VOUT drops below 0.5 V), the current limit is reduced to 1.6 A typically. If the output voltage rises above 0.5 V,
the device runs in normal operation again. At heavy loads, the current limit determines the maximum output
current. If the current limit is reached, the high-side FET is turned off. Avoiding shoot through current, then the
low-side FET switches on to allow the inductor current to decrease. The low-side current limit is typically 3.5 A.
The high-side FET turns on again only if the current in the low-side FET has decreased below the low-side
current limit threshold.
The output current of the device is limited by the current limit (see Electrical Characteristics). Due to internal
propagation delay, the actual current can exceed the static current limit during that time. The dynamic current
limit can be calculated as follows:
spacing
VL
I peak ( typ ) = I LIMF + × t PD
L (4)
where
ILIMF is the static current limit, specified in the Electrical Characteristics,
L is the inductor value,
VL is the voltage across the inductor (VIN - VOUT) and
tPD is the internal propagation delay.
spacing
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:
spacing

I peak (typ ) = I LIMF +

(VIN - VOUT )× 30ns
L (5)
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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS6213X is a switched mode step-down converter, able to convert a 3V to 17V input voltage into a 0.9V to
6V output voltage, providing up to 3A. It needs a minimum amount of external components. Apart from the LC
output filter and the input capacitors, only the TPS62130 (TPS62130A) with adjustable output voltage needs an
additional resistive divider to set the output voltage level.

9.2 Typical Application

space
(3 .. 17)V 1 / 2.2 µH VOUT / 3A
PVIN SW

AVIN VOS 100k

C1
10uF C7 C3
EN PG R1
0.1uF 22uF
TPS62130
SS/TR FB
C5
3.3nF DEF AGND R2

FSW PGND

Figure 7. 3A Step-Down Converter for Point-Of-Load Power Supply Using TPS62130

space

9.2.1 Design Requirements

The following design guideline provides a component selection to operate the device within the recommended
operating conditions. Using the FSW pin, the design can be optimized for highest efficiency or smallest solution
size and lowest output voltage ripple. For highest efficiency set FSW = High and the device operates at the lower
switching frequency. For smallest solution size and lowest output voltage ripple set FSW = Low and the device
operates with higher switching frequency. The typical values for all measurements are VIN = 12 V, VOUT = 3.3 V
and T = 25°C, using the external components of Table 3.
The component selection used for measurements is given as follows:

Table 3. List Of Components (1)

REFERENCE DESCRIPTION MANUFACTURER
IC 17V, 3A Step-Down Converter, QFN TPS62130RGT, Texas Instruments
L1 2.2µH, 0.165 x 0.165 in XFL4020-222MEB, Coilcraft
C1 10µF, 25V, Ceramic, 1210 Standard
C3 22µF, 6.3V, Ceramic, 0805 Standard
C5 3300pF, 25V, Ceramic, 0603 Standard
C7 0.1µF, 25V, Ceramic, 0603 Standard
R1 depending on VOUT
R2 depending on VOUT
R3 100kΩ, Chip, 0603, 1/16W, 1% Standard

(1) See Third-Party Products Disclaimer.

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9.2.2 Detailed Design Procedure

9.2.2.1 Programming The Output Voltage

While the output voltage of the TPS62130 (TPS62130A) is adjustable, the TPS62131/2/3 are programmed to
fixed output voltages. For fixed output voltage versions, the FB pin is pulled down internally and may be left
floating. It is recommended to connect to AGND to improve thermal resistance. The adjustable version can be
programmed for output voltages from 0.9 V to 6 V by using a resistive divider from VOUT to AGND. The voltage at
the FB pin is regulated to 800mV. The value of the output voltage is set by the selection of the resistive divider
from Equation 6. It is recommended to choose resistor values which allow a current of at least 2uA, meaning the
value of R2 shouldn't exceed 400 kΩ. Lower resistor values are recommended for highest accuracy and most
robust design. For applications requiring lowest current consumption, the use of fixed output voltage versions is
recommended.
space
æV ö
R1 = R 2 ç OUT - 1÷
è 0.8V ø (6)
space
In case the FB pin gets opened, the device clamps the output voltage at the VOS pin internally to about 7.4V.

9.2.2.2 External Component Selection

The external components have to fulfill the needs of the application, but also the stability criteria of the devices
control loop. The TPS6213X is optimized to work within a range of external components. The LC output filter's
inductance and capacitance have to be considered together, creating a double pole, responsible for the corner
frequency of the converter (see Output Filter And Loop Stability). Table 4 can be used to simplify the output filter
component selection. Checked cells represent combinations that are proven for stability by simulation and lab
test. Further combinations should be checked for each individual application. See SLVA463 for details.

Table 4. Recommended LC Output Filter Combinations (1)

4.7µF 10µF 22µF 47µF 100µF 200µF 400µF
0.47µH
1µH √ √ √ √
2.2µH √ √ (2) √ √ √
3.3µH √ √ √ √
4.7µH

(1) The values in the table are nominal values. The effective capacitance was considered to vary by +20% and -50%.
(2) This LC combination is the standard value and recommended for most applications.

spacing
The TPS6213X can be run with an inductor as low as 1µH. FSW should be set Low in this case. However, for
applications running with the low frequency setting (FSW=High) or with low input voltages, 2.2µH is
recommended.

9.2.2.2.1 Inductor Selection

The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-
PSM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under
static load conditions.
spacing
DI L(max)
I L(max) = I OUT (max) +
2 (7)
spacing

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æ V ö
ç 1 - OUT ÷
ç V IN (max) ÷
DI L(max) = VOUT ×ç ÷
L ×f
ç (min) SW ÷
ç ÷
è ø (8)
where
IL(max) is the maximum inductor current,
ΔIL is the Peak to Peak Inductor Ripple Current,
L(min) is the minimum effective inductor value and
fSW is the actual PWM Switching Frequency.
spacing
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS6213X and are recommended for use:

Table 5. List Of Inductors (1)

Type Inductance [µH] Current [A] (2) Dimensions [LxBxH] MANUFACTURER
mm
XFL4020-102ME_ 1.0 µH, ±20% 4.7 4 x 4 x 2.1 Coilcraft
XFL4020-152ME_ 1.5 µH, ±20% 4.2 4 x 4 x 2.1 Coilcraft
XFL4020-222ME_ 2.2 µH, ±20% 3.8 4 x 4 x 2.1 Coilcraft
IHLP1212BZ-11 1.0 µH, ±20% 4.5 3 x 3.6 x 2 Vishay
IHLP1212BZ-11 2.2 µH, ±20% 3.0 3 x 3.6 x 2 Vishay
SRP4020-3R3M 3.3µH, ±20% 3.3 4.8 x 4 x 2 Bourns
VLC5045T-3R3N 3.3µH, ±30% 4.0 5 x 5 x 4.5 TDK

(1) See Third-Party Products Disclaimer

(2) Lower of IRMS at 40°C rise or ISAT at 30% drop.

spacing
The inductor value also determines the load current at which Power Save Mode is entered:
space
1
I load ( PSM ) = DI L
2 (9)
space
Using Equation 8, this current level can be adjusted by changing the inductor value.

9.2.2.2.2 Capacitor Selection

9.2.2.2.2.1 Output Capacitor

The recommended value for the output capacitor is 22uF. The architecture of the TPS6213X allows the use of
tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output
voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it's recommended to use X7R or X5R dielectric. Using a higher value can
have some advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode (see
SLVA463).
Note: In power save mode, the output voltage ripple depends on the output capacitance, its ESR and the peak
inductor current. Using ceramic capacitors provides small ESR and low ripple.

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9.2.2.2.2.2 Input Capacitor

For most applications, 10µF will be sufficient and is recommended, though a larger value reduces input current
ripple further. The input capacitor buffers the input voltage for transient events and also decouples the converter
from the supply. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied
from the same input source, it's required to place a capacitance of 0.1uF from AVIN to AGND, to avoid potential
noise coupling. An RC, low-pass filter from PVIN to AVIN may be used but is not required.

9.2.2.2.2.3 Soft Start Capacitor

A capacitance connected between SS/TR pin and AGND allows a user programmable start-up slope of the
output voltage. A constant current source supports 2.5µA to charge the external capacitance. The capacitor
required for a given soft-start ramp time for the output voltage is given by:
spacing
2.5mA
C SS = t SS × [F ]
1.25V (10)
where
CSS is the capacitance (F) required at the SS/TR pin and
tSS is the desired soft-start ramp time (s).
spacing

NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore the right capacitor
value has to be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.

spacing

9.2.2.3 Tracking Function

If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50mV and 1.2V, the
FB pin will track the SS/TR pin voltage as described in Equation 11 and shown in Figure 8.
spacing
VFB » 0.64 × VSS / TR (11)
VSS/
TR [V]
1.2

0.8

0.4

0.2 0.4 0.6 0.8 VFB [V]

Figure 8. Voltage Tracking Relationship

spacing

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Once the SS/TR pin voltage reaches about 1.2 V, the internal voltage is clamped to the internal feedback voltage
and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior,
as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage,
the device does not sink current from the output. So, the resulting decrease of the output voltage may be slower
than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not
exceed the voltage rating of the SS/TR pin which is VIN + 0.3 V.
If the input voltage drops into undervoltage lockout or even down to zero, the output voltage will go to zero,
independent of the tracking voltage. Figure 9 shows how to connect devices to get ratiometric and simultaneous
sequencing by using the tracking function.

VOUT1
PVIN SW

AVIN VOS

EN PG
TPS62130
SS/TR FB

DEF AGND

FSW PGND

VOUT2
PVIN SW

AVIN VOS

R1 EN PG
TPS62130
SS/TR FB

R2 DEF AGND

FSW PGND

Copyright © 2016, Texas Instruments Incorporated

Figure 9. Sequence For Ratiometric And Simultaneous Startup

spacing
spacing
The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower or the same as
VOUT1.
A sequential startup is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. Ratiometric start up
sequence happens if both supplies are sharing the same soft start capacitor. Equation 10 calculates the soft start
time, though the SS/TR current has to be doubled. Details about these and other tracking and sequencing
circuits are found in SLVA470.
Note: If the voltage at the FB pin is below its typical value of 0.8V, the output voltage accuracy may have a wider
tolerance than specified.

9.2.2.4 Output Filter And Loop Stability

The devices of the TPS6213X family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 12:
space
1
f LC =
2p L × C (12)
space

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Proven nominal values for inductance and ceramic capacitance are given in Table 4 and are recommended for
use. Different values may work, but care has to be taken on the loop stability which will be affected. More
information including a detailed LC stability matrix can be found in SLVA463.
The TPS6213X devices, both fixed and adjustable output voltage versions, include an internal 25pF feedforward
capacitor, connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a
pole and zero in the control loop with the resistors of the feedback divider, per equation Equation 13 and
Equation 14:
spacing
1
f zero =
2p × R1 × 25 pF (13)
spacing
1 æ 1 1 ö
f pole = × çç + ÷÷
2p × 25 pF R
è 1 R 2 ø (14)
spacing
Though the TPS6213X devices are stable without the pole and zero being in a particular location, adjusting their
location to the specific needs of the application can provide better performance in Power Save mode and/or
improved transient response. An external feedforward capacitor can also be added. A more detailed discussion
on the optimization for stability vs. transient response can be found in SLVA289 and SLVA466.

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9.2.3 Application Curves

VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)

100.0 100.0
90.0 90.0
80.0 80.0
VIN=17V
70.0 VIN=12V 70.0

Efficiency (%)
Efficiency (%)

60.0 60.0 IOUT=10mA IOUT=1A

50.0 50.0 IOUT=1mA IOUT=100mA
40.0 40.0
30.0 30.0
20.0 20.0
10.0 10.0
0.0 0.0
0.0001 0.001 0.01 0.1 1 10 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) Input Voltage (V)
VOUT = 5 V VOUT = 5 V

Figure 10. Efficiency with 1.25 MHz Figure 11. Efficiency with 1.25 MHz

100.0 100.0
90.0 90.0
80.0 80.0
70.0 70.0
Efficiency (%)
Efficiency (%)

60.0 VIN=17V 60.0 IOUT=10mA IOUT=1A

50.0 VIN=12V 50.0 IOUT=1mA IOUT=100mA
40.0 40.0
30.0 30.0
20.0 20.0
10.0 10.0
0.0 0.0
0.0001 0.001 0.01 0.1 1 10 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) Input Voltage (V)
VOUT = 5 V VOUT = 5 V

Figure 12. Efficiency with 2.5 MHz Figure 13. Efficiency with 2.5 MHz

100.0 100.0
90.0 90.0
80.0 80.0
70.0 VIN=12V VIN=17V 70.0
Efficiency (%)
Efficiency (%)

60.0 VIN=5V 60.0 IOUT=1A IOUT=100mA IOUT=10mA IOUT=1mA

50.0 50.0
40.0 40.0
30.0 30.0
20.0 20.0
10.0 10.0
0.0 0.0
0.0001 0.001 0.01 0.1 1 10 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) Input Voltage (V)
VOUT = 3.3 V VOUT = 3.3 V

Figure 14. Efficiency with 1.25 MHz Figure 15. Efficiency with 1.25 MHz

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VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)

100.0 100.0
90.0 90.0
80.0 80.0
70.0 70.0

Efficiency (%)
Efficiency (%)

60.0 VIN=12V VIN=17V 60.0 IOUT=100mA IOUT=1mA

50.0 VIN=5V 50.0 IOUT=10mA IOUT=1A
40.0 40.0
30.0 30.0
20.0 20.0
10.0 10.0
0.0 0.0
0.0001 0.001 0.01 0.1 1 10 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) Input Voltage (V)
VOUT = 3.3 V VOUT = 3.3 V

Figure 16. Efficiency with 2.5 MHz Figure 17. Efficiency with 2.5 MHz

100.0 100.0
90.0 90.0
80.0 80.0
70.0 Efficiency (%) 70.0
Efficiency (%)

VIN=12V VIN=17V IOUT=1A

60.0 60.0 IOUT=100mA
IOUT=10mA
50.0 VIN=5V 50.0 IOUT=1mA
40.0 40.0
30.0 30.0
20.0 20.0
10.0 10.0
0.0 0.0
0.0001 0.001 0.01 0.1 1 10 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) Input Voltage (V)
VOUT = 1.8 V VOUT = 1.8 V

Figure 18. Efficiency with 1.25 MHz Figure 19. Efficiency with 1.25 MHz

100.0 100.0
90.0 90.0
80.0 80.0
70.0 70.0
Efficiency (%)
Efficiency (%)

60.0 VIN=12V VIN=17V 60.0 IOUT=1A

50.0 50.0 IOUT=100mA
VIN=5V IOUT=10mA
40.0 40.0 IOUT=1mA
30.0 30.0
20.0 20.0
10.0 10.0
0.0 0.0
0.0001 0.001 0.01 0.1 1 10 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) Input Voltage (V)
VOUT = 0.9 V VOUT = 0.9 V

Figure 20. Efficiency with 1.25 MHz Figure 21. Efficiency with 1.25 MHz

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VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)

3.40 3.40

VIN=17V IOUT=10mA
IOUT=1mA
3.35 3.35
Output Voltage (V)

Output Voltage (V)

VIN=12V

3.30 3.30

VIN=5V IOUT=1A IOUT=100mA

3.25 3.25

3.20 3.20
0.0001 0.001 0.01 0.1 1 10 4 7 10 13 16
Output Current (A) Input Voltage (V)

Figure 22. Output Voltage Accuracy (Load Regulation) Figure 23. Output Voltage Accuracy (Line Regulation)

4 4

3.5 IOUT=2A IOUT=3A 3.5

Switching Frequency (MHz)

Switching Frequency (MHz)

3 3

2.5 2.5

2 2
IOUT=0.5A IOUT=1A
1.5 1.5

1 1

0.5 0.5

0 0
6 8 10 12 14 16 18 0 0.5 1 1.5 2 2.5 3
Input Voltage (V) G000 Output Current (A) G000

FSW = Low VOUT = 5 V FSW = Low VOUT = 5 V

Figure 24. Switching Frequency vs Input Voltage Figure 25. Switching Frequency vs Output Current

4 4

3.5 IOUT=2A IOUT=3A 3.5

Switching Frequency (MHz)

Switching Frequency (MHz)

3 3

2.5 2.5

2 2
IOUT=0.5A IOUT=1A
1.5 1.5

1 1

0.5 0.5

0 0
4 6 8 10 12 14 16 18 0 0.5 1 1.5 2 2.5 3
Input Voltage (V) G000 Output Current (A) G000

FSW = Low VOUT = 3.3 V FSW = Low VOUT = 3.3 V

Figure 26. Switching Frequency vs Input Voltage Figure 27. Switching Frequency vs Output Current,

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VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)

4 4

3.5 3.5
Switching Frequency (MHz)

Switching Frequency (MHz)

3 IOUT=2A IOUT=3A 3

2.5 2.5

2 2
IOUT=0.5A IOUT=1A
1.5 1.5

1 1

0.5 0.5

0 0
3 5 7 9 11 13 15 17 0 0.5 1 1.5 2 2.5 3
Input Voltage (V) G000 Output Current (A) G000

FSW = Low VOUT = 1.8 V FSW = Low VOUT = 1.8 V

Figure 28. Switching Frequency vs Input Voltage Figure 29. Switching Frequency vs Output Current

3 3

2.5 2.5
Switching Frequency (MHz)

Switching Frequency (MHz)

IOUT=2A IOUT=3A

2 2

1.5 1.5
IOUT=1A
1 IOUT=0.5A 1

0.5 0.5

0 0
3 5 7 9 11 13 15 17 0 0.5 1 1.5 2 2.5 3
Input Voltage (V) G000 Output Current (A) G000

FSW = Low VOUT = 1 V FSW = Low VOUT = 1 V

Figure 30. Switching Frequency vs Input Voltage Figure 31. Switching Frequency vs Output Current

0.05 6
5.5
5
0.04 −40°C
Output Voltage Ripple (V)

4.5
Output Current (A)

4
0.03 3.5
VIN=17V VIN=5V
3
2.5 25°C
0.02
85°C
2
1.5
0.01
1
VIN=12V 0.5
0 0
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Output Current (A) Input Voltage (V)

Figure 32. Output Voltage Ripple Figure 33. Maximum Output Current

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VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)

100 100
90 VIN=5V 90 VIN=12V
80 80 VIN=5V
VIN=12V
70 VIN=17V 70 VIN=17V
PSRR (dB)

PSRR (dB)
60 60
50 50
40 40
30 30
20 VOUT=3.3V, IOUT=1A 20 VOUT=3.3V, IOUT=0.1A
10 L=2.2uH (XFL4020) 10 L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF Cin=10uF, Cout=22uF
0 0
10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M
Frequency (Hz) G000
Frequency (Hz) G000

FSW = 2.5 Mhz FSW = 2.5 MHz

Figure 34. Power Supply Rejection Ratio Figure 35. Power Supply Rejection Ratio

VIN = 12 VOUT = 3.3 V with 50 mV/Div IOUT = 0.5 to 3 to 0.5 A

Figure 36. PWM-PSM-Transition Figure 37. Load Transient Response

Figure 38. Load Transient Response of Figure 37, Figure 39. Load Transient Response of Figure 37,
Rising Edge Falling Edge

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 23

TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133
SLVSAG7E – NOVEMBER 2011 – REVISED AUGUST 2016 www.ti.com

VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)

Figure 40. Startup Into 100 mA Figure 41. Startup Into 3 A

IOUT = 1 A IOUT = 10 mA

Figure 42. Typical Operation In PWM Mode Figure 43. Typical Operation In Power Save Mode

125 125

115 115
Free−Air Temperature (°C)
Free−Air Temperature (°C)

105 105

95 95

85 85

75 75

65 65

55 55
0 0.5 1 1.5 2 2.5 3 3.5 0 2 4 6 8 10 12
Output Current (A) Output Power (W)
FSW = 2.5 MHz TPS62130EVM FSW = 2.5 MHz TPS62130EVM
L = 2.2 µH (XFL4020) L = 2.2 µH (XFL4020)

Figure 44. Maximum Ambient Temperature Figure 45. Maximum Ambient Temperature

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www.ti.com SLVSAG7E – NOVEMBER 2011 – REVISED AUGUST 2016

9.3 System Examples

9.3.1 LED Power Supply
The TPS62130 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower
values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid
excessive power loss. Since this pin provides 2.5µA, the feedback pin voltage can be adjusted by an external
resistor per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode
voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TPS62130.
Figure 46 shows an application circuit, tested with analog dimming:
spacing
(4 .. 17) V 2.2 µH
PVIN SW

AVIN VOS

10uF 0.1uF EN PG 22uF

ADIM TPS62130
SS/TR FB

187k DEF AGND 0.1R

FSW PGND

Figure 46. Single Power LED Supply

spacing
The resistor at SS/TR sets the FB voltage to a level of about 300mV and is calculated from Equation 15.
spacing
V FB = 0.64 × 2.5mA × R SS / TR (15)
spacing
spacing
The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage
accordingly. The minimum input voltage has to be rated according the forward voltage needed by the LED used.
More information is available in the Application Note SLVA451.
spacing

9.3.2 Active Output Discharge

The TPS62130A pulls the PG pin Low, when the device is shut down by EN, UVLO or thermal shutdown.
Connecting PG to VOUT through a resistor can be used to discharge VOUT in those cases (see Figure 47). The
discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For reliability,
keep the maximum current into the PG pin less than 10mA.
spacing
spacing

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SLVSAG7E – NOVEMBER 2011 – REVISED AUGUST 2016 www.ti.com

System Examples (continued)

(3 .. 17)V 1 / 2.2 µH Vout / 3A

PVIN SW
TPS62130A
AVIN VOS
R3
10uF 0.1uF EN PG R1 22uF

SS/TR FB
3.3nF
DEF AGND R2

FSW PGND

Figure 47. Discharge VOUT Through PG Pin with TPS62130A

9.3.3 –3.3V Inverting Power Supply

The TPS62130 can be used as inverting power supply by rearranging external circuitry as shown in Figure 48.
As the former GND node now represents a voltage level below system ground, the voltage difference between
VIN and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 16).
spacing
VIN + VOUT £ VIN max (16)
spacing
spacing

10uF

(3 .. 13.7)V 2.2µH
PVIN SW

AVIN VOS
10uF
EN PG 1.21M
0.1uF TPS62130 22uF
SS/TR FB
3.3nF
DEF AGND 383k
-3.3V
FSW PGND

Figure 48. –3.3 V Inverting Power Supply

spacing
The transfer function of the inverting power supply configuration differs from the buck mode transfer function,
incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output
capacitance of at least 22µF is recommended. A detailed design example is given in SLVA469.
spacing

9.3.4 Various Output Voltages

The following example circuits show how to use the various devices and configure the external circuitry to furnish
different output voltages at 3A.
spacing
spacing

26 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133
www.ti.com SLVSAG7E – NOVEMBER 2011 – REVISED AUGUST 2016

System Examples (continued)

(5 .. 17)V 1 / 2.2 µH 5V / 3A
PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 22uF
TPS62133
SS/TR FB
3.3nF
DEF AGND

FSW PGND

Figure 49. 5V/3A Power Supply

spacing
spacing
spacing
(3.3 .. 17)V 1 / 2.2 µH 3.3V / 3A
PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 22uF
TPS62132
SS/TR FB
3.3nF
DEF AGND

FSW PGND

Figure 50. 3.3V/3A Power Supply

spacing
spacing
(3 .. 17)V 1 / 2.2 µH 2.5V / 3A
PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 390k 22uF
TPS62130
SS/TR FB
3.3nF
DEF AGND 180k

FSW PGND

Figure 51. 2.5V/3A Power Supply

spacing
spacing

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 27

TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133
SLVSAG7E – NOVEMBER 2011 – REVISED AUGUST 2016 www.ti.com

System Examples (continued)

(3 .. 17)V 1 / 2.2 µH 1.8V / 3A

PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 22uF
TPS62131
SS/TR FB
3.3nF
DEF AGND

FSW PGND

Figure 52. 1.8V/3A Power Supply

spacing
spacing
spacing
(3 .. 17)V 1 / 2.2 µH 1.5V / 3A
PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 130k 22uF
TPS62130
SS/TR FB
3.3nF
DEF AGND 150k

FSW PGND

Figure 53. 1.5V/3A Power Supply

spacing
spacing
(3 .. 17)V 1 / 2.2 µH 1.2V / 3A
PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 75k 22uF
TPS62130
SS/TR FB
3.3nF
DEF AGND 150k

FSW PGND

Figure 54. 1.2V/3A Power Supply

spacing
spacing

28 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133
www.ti.com SLVSAG7E – NOVEMBER 2011 – REVISED AUGUST 2016

System Examples (continued)

(3 .. 17)V 1 / 2.2 µH 1V / 3A
PVIN SW

AVIN VOS 100k

10uF 0.1uF
EN PG 51k 22uF
TPS62130
SS/TR FB
3.3nF
DEF AGND 200k

FSW PGND

Figure 55. 1V/3A Power Supply

spacing

10 Power Supply Recommendations

The TPS6213X are designed to operate from a 3-V to 17-V input voltage supply. The input power supply's output
current needs to be rated according to the output voltage and the output current of the power rail application.

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 29

TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133
SLVSAG7E – NOVEMBER 2011 – REVISED AUGUST 2016 www.ti.com

11 Layout

11.1 Layout Guidelines

A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TPS6213X demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation and noise sensitivity.
See Figure 56 for the recommended layout of the TPS6213X, which is designed for common external ground
connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad. On the
PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the system
ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to VOUT at the output
capacitor. To avoid noise coupling into the VOS line, this connection should be separated from the VOUT power
line/plane as shown in Layout Example.
Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load
current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore the input and output capacitance should be placed as close as possible to the IC
pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an
alternating current should outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (e.g.
SW). As they carry information about the output voltage, they should be connected as close as possible to the
actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB
resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground
plane.
The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve
appropriate power dissipation.
The recommended layout is implemented on the EVM and shown in its Users Guide, SLVU437. Additionally, the
EVM Gerber data are available for download here, SLVC394.

11.2 Layout Example

space

AGND

C5 R1
C7
R2
AGND
FSW
DEF

FB

VIN SS/TR

AVIN
PG

SW

PVIN SW

PVIN SW
PGND

PGND
VOS
EN

C1 C3 L1

VOUT

GND
Figure 56. Layout Example

30 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133
www.ti.com SLVSAG7E – NOVEMBER 2011 – REVISED AUGUST 2016

11.3 Thermal Information

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB by soldering the Exposed Thermal Pad
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note (SZZA017), and (SPRA953).
The TPS6213X is designed for a maximum operating junction temperature (Tj) of 125°C. Therefore the maximum
output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by
the package and the surrounding PCB structures. Since the thermal resistance of the package is fixed,
increasing the size of the surrounding copper area and improving the thermal connection to the IC can reduce
the thermal resistance. To get an improved thermal behavior, it's recommended to use top layer metal to connect
the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for
improved thermal performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
Experimental data, taken from the TPS62130 EVM, shows the maximum ambient temperature (without additional
cooling like airflow or heat sink), that can be allowed to limit the junction temperature to at most 125°C (see
Figure 44).

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 31

TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133
SLVSAG7E – NOVEMBER 2011 – REVISED AUGUST 2016 www.ti.com

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

• Application Report, Voltage Margining Using the TPS62130 SLVA489
• Application Report, Using the TPS62150 as Step-Down LED Driver With Dimming SLVA451
• Application Report, Using the TPS6215x in an Inverting Buck-Boost Topology SLVA469
• Application Report, Optimizing the TPS62130/40/50/60/70 Output Filter SLVA463
• Application Report, TPS62130/40/50 Sequencing and Tracking SLVA470
• Application Report, Optimizing Transient Response of Internally Compensated dc-dc Converters With
Feedforward Capacitor SLVA289
• Application Report, Using a Feedforward Capacitor to Improve Stability and Bandwidth of
TPS62130/40/50/60/70 SLVA466
• Application Report, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
SZZA017
• Application Report, Semiconductor and IC Package Thermal Metrics SPRA953
• User's Guide, TPS62130EVM-505, TPS62140EVM-505, and TPS62150EVM-505 Evaluation Modules
SLVU437
• EVM Gerber Data, SLVC394

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.4 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 6. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TPS62130 Click here Click here Click here Click here Click here
TPS62130A Click here Click here Click here Click here Click here
TPS62131 Click here Click here Click here Click here Click here
TPS62132 Click here Click here Click here Click here Click here
TPS62133 Click here Click here Click here Click here Click here

32 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated

 TPS62130, TPS62130A, TPS62131, TPS62132, TPS62133
www.ti.com SLVSAG7E – NOVEMBER 2011 – REVISED AUGUST 2016

12.5 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.6 Trademarks
DCS-Control, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 33

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS62130ARGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 PA6I

TPS62130ARGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 PA6I

TPS62130RGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 PTSI

TPS62130RGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 PTSI

TPS62131RGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 QVX

TPS62131RGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 QVX

TPS62132RGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 QVY

TPS62132RGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 QVY

TPS62133RGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 QVZ

TPS62133RGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 QVZ

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS62130A :

• Automotive: TPS62130A-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62130ARGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62130ARGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62130RGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62130RGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62130RGTT VQFN RGT 16 250 180.0 12.5 3.3 3.3 1.1 8.0 12.0 Q2
TPS62130RGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62131RGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62131RGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62132RGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62132RGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62133RGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62133RGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS62130ARGTR VQFN RGT 16 3000 552.0 367.0 36.0
TPS62130ARGTT VQFN RGT 16 250 552.0 185.0 36.0
TPS62130RGTR VQFN RGT 16 3000 552.0 367.0 36.0
TPS62130RGTR VQFN RGT 16 3000 338.0 355.0 50.0
TPS62130RGTT VQFN RGT 16 250 338.0 355.0 50.0
TPS62130RGTT VQFN RGT 16 250 552.0 185.0 36.0
TPS62131RGTR VQFN RGT 16 3000 367.0 367.0 35.0
TPS62131RGTT VQFN RGT 16 250 210.0 185.0 35.0
TPS62132RGTR VQFN RGT 16 3000 367.0 367.0 35.0
TPS62132RGTT VQFN RGT 16 250 210.0 185.0 35.0
TPS62133RGTR VQFN RGT 16 3000 367.0 367.0 35.0
TPS62133RGTT VQFN RGT 16 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
RGT0016C SCALE 3.600
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.1 B
A
2.9

PIN 1 INDEX AREA

3.1
2.9

1.0 C
0.8

SEATING PLANE

0.05 0.08
0.00

1.68 0.07 (0.2) TYP

5 8
EXPOSED
THERMAL PAD
12X 0.5 4
9

4X SYMM
1.5

1
12
0.30
16X
0.18
16 13 0.1 C A B
PIN 1 ID SYMM
(OPTIONAL) 0.05

0.5
16X
0.3

4222419/C 04/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGT0016C VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.68)
SYMM
16 13

16X (0.6)

1
12

16X (0.24)
SYMM

(2.8)
(0.58)
TYP
12X (0.5)
9
4

( 0.2) TYP
VIA

5 8
(R0.05) (0.58) TYP
ALL PAD CORNERS
(2.8)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4222419/C 04/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGT0016C VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.55)
16 13

16X (0.6)

1
12

16X (0.24)

17 SYMM

(2.8)

12X (0.5)

9
4

METAL
ALL AROUND

5 8
SYMM
(R0.05) TYP

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X

4222419/C 04/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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