Laboratory Exercise 6: Adders, Subtractors, and Multipliers
Laboratory Exercise 6: Adders, Subtractors, and Multipliers
Laboratory Exercise 6: Adders, Subtractors, and Multipliers
The purpose of this exercise is to examine arithmetic circuits that add, subtract, and multiply numbers. Each
circuit will be described in Verilog and implemented on an Intel FPGA DE10-Lite, DE0-CV, DE1-SoC, or DE2-
115 board.
Part I
Consider again the four-bit ripple-carry adder circuit used in lab exercise 2; its diagram is reproduced in Figure 1.
b3 a3 c b2 a2 c b1 a1 c b 0 a 0 c in
3 2 1
carry FA FA FA FA
s3 s2 s1 s0
Q D overflow c in 0
Use this construct to implement a circuit shown in Figure 2. This+circuit, which is often called an accumulator, is
used to add the value of an input A to itself repeatedly. The circuit8 includes a carry out from the adder, as well as
an overflow output signal. If the input A is considered as a 2’s-complement number, then overflow should be set
to 1 in the case where the output sum produced does not representR a correct 2’s-complement result.
Q
1
carry FA FA FA FA
s3 s2 s1 s0
A
8
R
Clock Q
Logic
Q D
circuit 0
+
8
Q D
R
Q
overflow carry S
Part II
Extend the circuit from Part I to be able to both add and subtract numbers. To do so, introduce an add_sub input
to your circuit. When add_sub is 1, your circuit should subtract A from S, and when add_sub is 0 your circuit
should add A to S as in Part I.
Part III
Figure 3a gives an example of paper-and-pencil multiplication P = A × B, where A = 11 and B = 12.
a3 a2 a1 a0
x b3 b2 b1 b0
1 0 1 1 a3 b0 a2 b0 a1 b0 a0 b0
1 1 x 1 1 0 0
x 1 2 a3 b1 a2 b1 a1 b1 a0 b1
0 0 0 0
2 2 0 0 0 0 a3 b2 a2 b2 a1 b2 a0 b2
1 1 1 0 1 1 a3 b3 a2 b3 a1 b3 a0 b3
1 0 1 1
1 3 2 p7 p6 p5 p4 p3 p2 p1 p0
1 0 0 0 0 1 0 0
We compute P = A × B as an addition of summands. The first summand is equal to A times the ones digit of B.
The second summand is A times the tens digit of B, shifted one position to the left. We add the two summands to
form the product P = 132.
Part b of the figure shows the same example using four-bit binary numbers. To compute P = A × B, we first form
summands by multiplying A by each digit of B. Since each digit of B is either 1 or 0, the summands are either
2
shifted versions of A or 0000. Figure 3c shows how each summand can be formed by using the Boolean AND
operation of A with the appropriate bit of B.
A four-bit circuit that implements P = A × B is illustrated in Figure 4. Because of its regular structure, this type
of multiplier circuit is called an array multiplier. The shaded areas correspond to the shaded columns in Figure 3c.
In each row of the multiplier AND gates are used to produce the summands, and full adder modules are used to
generate the required sums.
a3 a2 a3 a1 a2 a0 a1 a0
b0
b1
b a b a b a b a
c o FA c i c o FA c i c o FA c i c o FA c i 0
s s s s
a3 a2 a1 a0
b2
b a b a b a b a
c o FA c i c o FA c i c o FA c i c o FA c i 0
s s s s
a3 a2 a1 a0
b3
b a b a b a b a
c o FA c i c o FA c i c o FA c i c o FA c i 0
s s s s
p7 p6 p5 p4 p3 p2 p1 p0
3
Part IV
In Part III, an array multiplier was implemented using full adder modules. At a higher level, a row of full adders
functions as an n-bit adder and the array multiplier circuit can be represented as shown in Figure 5.
a3 a2 a1 a0
b0
a3 a2 a1 a0
b1
b3 a3 b2 a2 b1 a1 b0 a0
co n-bit Adder ci 0
s3 s2 s1 s0
a3 a2 a1 a0
b2
b3 a3 b2 a2 b1 a1 b0 a0
co n-bit Adder ci 0
s3 s2 s1 s0
a3 a2 a1 a0
b3
b3 a3 b2 a2 b1 a1 b0 a0
co n-bit Adder ci 0
s3 s2 s1 s0
p7 p6 p5 p4 p3 p2 p1 p0
Each n-bit adder adds a shifted version of A for a given row and the partial product of the row above. Abstracting
the multiplier circuit as a sequence of additions allows us to build larger multipliers. The multiplier should consist
of n-bit adders arranged in a structure shown in Figure 5. Use this approach to implement an 8 x 8 multiplier
circuit with registered inputs and outputs, as shown in Figure 6.
4
Data inputs
8 8
EA E D D E EB
Clock Q Q
A B
Multiplier
16
D
R
Q
4. Test the functionality of your design by inputting various data values and observing the generated products.
Part V
Part IV showed how to implement multiplication A × B as a sequence of additions, by accumulating the shifted
versions of A one row at a time. Another way to implement this circuit is to perform addition using an adder tree.
An adder tree is a method of adding several numbers together in a parallel fashion. This idea is illustrated in
Figure 7. In the figure, numbers A, B, C, D, E, F , G, and H are added together in parallel. The addition A + B
happens simultaneously with C + D, E + F and G + H. The result of these operations are then added in parallel
again, until the final sum P is computed.
5
A B C D E F G H
+ + + +
+ +
+
P
In this part you are to implement an 8 x 8 multiplier circuit by using the adder-tree approach. Inputs A and B, as
well as the output P should be registered as in Part IV.
6
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