AOZ1033AI

EZBuck™ 3A Synchronous Buck Regulator

Not Recommended For New Designs

General Description Features
The AOZ1033A is a high efficiency, easy to use, 3A z 4.5V to 18V operating input voltage range
synchronous buck regulator. The AOZ1033A works from z Synchronous Buck: 80mΩ internal high-side switch
4.5V to 18V input voltage range, and provides up to 3A of and 30mΩ internal low-side switch with integrated
continuous output current with an output voltage adjust- schottky diode

s
able down to 0.8V.
z High efficiency: up to 95%

n
The AOZ1033A comes in a SO-8 package and is rated z Internal soft start

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over a -40°C to +85°C operating ambient temperature z Output voltage adjustable to 0.8V

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range.
z 3A continuous output current
z Fixed 600kHz PWM operation

D
Replacement Part:
z Pulse skipping at light load for high efficiency over
AOZ3013PI (same package) entire load range

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AOZ3103DI (smaller package) z Cycle-by-cycle current limit
z Pre-bias start-up

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z Short-circuit protection
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z Thermal shutdown
Fo
z SO-8 package

Applications
d

z Point of load DC/DC converters

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z LCD TV
z Set top boxes
en

z DVD/Blu-ray players/recorders
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z Cable modems
z PCIe graphics cards
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z Telecom/Networking/Datacom equipment
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Typical Application
R

VIN
ot

C1
22µF
N

VIN
L1 4.7µH
EN VOUT
AOZ1033 LX

COMP R1
C2, C3
RC FB 22µF

CC AGND PGND R2

Figure 1. 3.3V 3A Synchronous Buck Regulator

Rev. 1.1 October 2010 www.aosmd.com Page 1 of 15

 AOZ1033AI

Ordering Information
Part Number Ambient Temperature Range Package Environmental
AOZ1033AI -40°C to +85°C SO-8 RoHS Compliant
Green Product

AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.

Pin Configuration

n s
PGND 1 8 LX

ig
VIN 2 7 LX

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AGND 3 6 EN

D
FB 4 5 COMP

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SO-8
(Top View)

Pin Description r N
Fo
Pin Number Pin Name Pin Function
1 PGND Power ground. PGND needs to be electrically connected to AGND.
d
de

2 VIN Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high, the
device starts up.
en

3 AGND Analog ground. AGND is the reference point for controller section. AGND needs to be
electrically connected to PGND.
m

4 FB Feedback input. The FB pin is used to set the output voltage via a resistive voltage divider
between the output and AGND.
om

5 COMP External loop compensation pin. Connect a RC network between COMP and AGND to
compensate the control loop.
ec

6 EN Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the
device. Do not leave it open.
R

7, 8 LX Switching node. PWM output connection to inductor.

ot
N

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 AOZ1033AI

Block Diagram
VIN

EN UVLO 5V LDO Internal OTP

& POR Regulator +5V

+
ISen
–
Reference Softstart
& Bias Q1

s
ILimit

n
ig
+
+ PWM Level
0.8V

es
PWM Shifter
EAmp – Control
FB – Comp +
Logic
+ FET LX

D
Driver
Q2
COMP

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Frequency

N
Foldback 600kHz
Comparator
+
0.2V – r
Fo
Over-Voltage
Protection
Comparator
+
d

–
de

0.96V
en

AGND PGND
m

Absolute Maximum Ratings Recommended Operating Conditions

om

Exceeding the Absolute Maximum ratings may damage the

The device is not guaranteed to operate beyond the Maximum
device.
Recommended Operating Conditions.
ec

Parameter Rating Parameter Rating

Supply Voltage (VIN) 20V
Supply Voltage (VIN) 4.5V to 18V
R

LX to AGND -0.7V to VIN+0.3V

Output Voltage Range 0.8V to VIN
LX to AGND -3V for 20 nS
Ambient Temperature (TA) -40°C to +85°C
ot

EN to AGND -0.3V to VIN+0.3V

Package Thermal Resistance
N

FB to AGND -0.3V to 6V SO-8 (ΘJA) 87°C/W

COMP to AGND -0.3V to 6V SO-8 (ΘJC) 30°C/W

PGND to AGND -0.3V to +0.3V Package Power Dissipation (PD) @

25°C Ambient
Junction Temperature (TJ) +150°C SO-8 1.15W
Storage Temperature (TS) -65°C to +150°C
ESD Rating(1) 2.0kV
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.

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 AOZ1033AI

Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

VIN Supply Voltage 4.5 18 V
VUVLO Input under-voltage lockout VIN rising 4.1 V
threshold VIN falling 3.7 V
IIN Supply current (Quiescent) IOUT = 0, VFB = 1.2V, VEN >1.2V 1.6 2.5 mA
IOFF Shutdown supply current VEN = 0V 1 10 μA
VFB Feedback Voltage TA = 25°C 0.788 0.8 0.812 V

s
Load regulation 0.5 %

n
Line regulation 1 %

ig
IFB Feedback voltage input current 200 nA

es
VEN EN input threshold Off threshold 0.6 V
On threshold 2 V

D
VHYS EN input hysteresis 100 mV
MODULATOR

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fO Frequency 400 450 500 kHz
DMAX Maximum Duty Cycle 100 %

N
tMIN Minimum On Time 150 ns
Error amplifier voltage gain 500 V/V
r
Fo
Error amplifier transconductance 200 μA / V
PROTECTION
ILIM Current Limit 3.8 4.2 A
d

VOVP Over-Voltage Protection Off threhsold 960 mV

de

On threshold 860 mV
Over-temperature shutdown limit TJ rising 150 °C
en

TJ falling 100 °C
tSS Soft Start Interval 3 ms
m

OUTPUT STAGE
High-side switch on-resistance VIN = 12V 80 100 mΩ
om

VIN = 5V 130 180 mΩ

Low-side switch on-resistance VIN = 12V 30 36 mΩ
ec

VIN = 5V 56 70 mΩ
R
ot
N

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 AOZ1033AI

Typical Performance Characteristics

Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.

Light Load (DCM) Operation Full Load (CCM) Operation

sn
ig
es
D
1us/div 1us/div

ew
Start Up to Full Load Short Circuit Protection

r N
Fo
d
de
en
m

1ms/div 4ms/div
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50% to 100% Load Transient Short Circuit Recovery

ec
R
ot
N

100us/div 10ms/div

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 AOZ1033AI

Efficiency

AOZ1033AI Efficiency
Efficiency (VIN = 12V) vs. Load Current Efficiency (VIN = 5V) vs. Load Current
100 100
90 90
80 80
70 70
Efficiency (%)

Efficiency (%)
60 VO = 1.2V 60 VO = 1.2V
VO = 1.8V VO = 1.8V
50 50 VO = 3.3V

s
VO = 3.3V
VO = 5V

n
40 40

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30 30
20 20

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10 10

D
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0

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IOUT (A) IOUT (A)

r N
Fo
Thermal Derating
d

Thermal de-rating curves for SO-8 package part under typical input and output condition based on the evaluation board.
de

25°C ambient temperature and natural convection (air speed < 50LFM) unless otherwise specified.
Derating Curves at 5V/6V Input Derating Curves at 12V Input
en

5 5
m

4 4
Output Current (IO)

Output Current (IO)

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1.2V, 1.8V Output 1.2V, 1.8V, 3.3V, 5.0V Output

3 3
3.3V Output

2 2
ec

1 1
R

0 0
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25 35 45 55 65 75 85 25 35 45 55 65 75 85
N

Ambient Temperature (TA) Ambient Temperature (TA)

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 AOZ1033AI

Detailed Description Comparing with regulators using freewheeling Schottky

diodes, the AOZ1033A uses freewheeling NMOSFET to
The AOZ1033A is a current-mode step down regulator
realize synchronous rectification. It greatly improves the
with integrated high-side PMOS switch and a low-side
converter efficiency and reduces power loss in the
NMOS switch. It operates from a 4.5V to 18V input volt-
low-side switch.
age range and supplies up to 3A of load current. The
duty cycle can be adjusted from 6% to 100% allowing a The AOZ1033A will enter the discontinuous conduction
wide range of output voltage. Features include enable mode at light load. Several pulses may be skipped in
control, Power-On Reset, input under voltage lockout, between switching cycles at very light load, it further
output over voltage protection, active high power good improving light load efficiency.
state, fixed internal soft-start and thermal shut down.
The AOZ1033A uses a P-Channel MOSFET as the

s
The AOZ1033A is available in SO-8 package. high-side switch. It saves the bootstrap capacitor nor-

n
mally seen in a circuit which is using an NMOS switch. It

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Enable and Soft Start allows 100% turn-on of the high-side switch to achieve
The AOZ1033A has internal soft start feature to limit linear regulation mode of operation. The minimum volt-

es
in-rush current and ensure the output voltage ramps up age drop from VIN to VO is the load current times DC
smoothly to regulation voltage. A soft start process resistance of MOSFET plus DC resistance of buck induc-

D
begins when the input voltage rises to 4.1V and voltage tor. It can be calculated by equation below:
on EN pin is HIGH. In soft start process, the output volt-
V O_MAX = V IN – I O × R DS ( ON )

ew
age is ramped to regulation voltage in typically 2.2ms.
The 2.2ms soft start time is set internally.
where;

N
The EN pin of the AOZ1033A is active high. Connect the VO_MAX is the maximum output voltage;,
EN pin to VIN if enable function is not used. Pull it to
VIN is the input voltage from 4.5V to 18V,
r
ground will disable the AOZ1033A. Do not leave it open.
Fo
IO is the output current from 0A to 3A, and
The voltage on EN pin must be above 2V to enable the
AOZ1033A. When voltage on EN pin falls below 0.6V, the RDS(ON) is the on resistance of internal MOSFET. The value is
AOZ1033A is disabled. If an application circuit requires between 97mΩ and 200mΩ depending on input voltage and
d

junction temperature.
the AOZ1033A to be disabled, an open drain or open col-
de

lector circuit should be used to interface to EN pin.

Switching Frequency
The AOZ1033A switching frequency is fixed and set by
en

Steady-State Operation
Under steady-state conditions, the converter operates an internal oscillator. The practical switching frequency
in fixed frequency and Continuous-Conduction Mode could range from 500kHz to 700kHz due to device varia-
m

(CCM). tion.
om

The AOZ1033A integrates an internal P-MOSFET as the Output Voltage Programming

high-side switch. Inductor current is sensed by amplifying Output voltage can be set by feeding back the output to
the voltage drop across the drain to source of the high
ec

the FB pin by using a resistor divider network. In the

side power MOSFET. Output voltage is divided down by application circuit shown in Figure 1. The resistor divider
the external voltage divider at the FB pin. The difference
R

network includes R1 and R2. Usually, a design is started

of the FB pin voltage and reference is amplified by the by picking a fixed R2 value and calculating the required
internal transconductance error amplifier. The error volt-
ot

R1 with equation below.

age, which shows on the COMP pin, is compared against
the current signal, which is sum of inductor current signal ⎛ R 1⎞
N

and ramp compensation signal, at PWM comparator V O = 0.8 × ⎜ 1 + -------⎟

input. If the current signal is less than the error voltage, ⎝ R 2⎠
the internal high-side switch is on. The inductor current
flows from the input through the inductor to the output. Some standard value of R1, R2 and most used output
When the current signal exceeds the error voltage, the voltage values are listed in Table 1 on the next page.
high-side switch is off. The inductor current is freewheel-
ing through the internal low-side N-MOSFET switch to
output. The internal adaptive FET driver guarantees no
turn on overlap of both high-side and
low-side switch.

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 AOZ1033AI

Table 1. Thermal Protection

Vo (V) R1 (kΩ) R2 (kΩ) An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
0.8 1.0 open high side PMOS if the junction temperature exceeds
1.2 4.99 10 150°C. The regulator will restart automatically under the
1.5 10 11.5 control of soft-start circuit when the junction temperature
decreases to 100°C.
1.8 12.7 10.2
2.5 21.5 10 Application Information
3.3 31.1 10
The basic AOZ1033A application circuit is show in
5.0 52.3 10 Figure 1. Component selection is explained below.

n s
The combination of R1 and R2 should be large enough to Input Capacitor

ig
avoid drawing excessive current from the output, which The input capacitor must be connected to the VIN pin and
will cause power loss. PGND pin of AOZ1033A to maintain steady input voltage

es
and filter out the pulsing input current. The voltage rating
Since the switch duty cycle can be as high as 100%, the of input capacitor must be greater than maximum input

D
maximum output voltage can be set as high as the input voltage plus ripple voltage.
voltage minus the voltage drop on upper PMOS and

ew
inductor. The input ripple voltage can be approximated by equa-
tion below:
Protection Features

N
IO ⎛ VO ⎞ VO
The AOZ1033A has multiple protection features to pre- ΔV IN = ----------------- × ⎜ 1 – ---------⎟ × ---------
vent system circuit damage under abnormal conditions. r f × C IN ⎝ V IN⎠ V IN
Fo
Over Current Protection (OCP) Since the input current is discontinuous in a buck con-
The sensed inductor current signal is also used for over verter, the current stress on the input capacitor is another
concern when selecting the capacitor. For a buck circuit,
d

current protection. Since the AOZ1033A employs peak

current mode control, the COMP pin voltage is propor- the RMS value of input capacitor current can be calcu-
de

tional to the peak inductor current. The COMP pin volt- lated by:
age is limited to be between 0.4V and 2.5V internally.
en

The peak inductor current is automatically limited cycle VO ⎛ VO ⎞

- ⎜ 1 – --------
I CIN_RMS = I O × -------- -⎟
by cycle. V IN ⎝ V IN⎠
m

When the output is shorted to ground under fault condi-

if we let m equal the conversion ratio:
om

tions, the inductor current decays very slow during a

switching cycle because of Vo=0V. To prevent cata- VO
strophic failure, AOZ1033A detects the duration the over- --------
- = m
ec

current condition occurs. If the over-current condition V IN

occurs for certain period, AOZ1033A totally turns off for a
period of time, then restarts. If the fault is still there, then
R

The relation between the input capacitor RMS current

the chip will be off again. The converter will initiate a soft and voltage conversion ratio is calculated and shown in
start once the over-current condition disappears.
ot

Figure 2 on the next page. It can be seen that when VO is

half of VIN, CIN is under the worst current stress. The
N

Power-On Reset (POR)

worst current stress on CIN is 0.5 x IO.
A power-on reset circuit monitors the input voltage. When
the input voltage exceeds 4.1V, the converter starts oper-
ation. When input voltage falls below 3.7V, the converter
will be shut down.

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 AOZ1033AI

0.5 The inductor takes the highest current in a buck circuit.

The conduction loss on inductor need to be checked for
thermal and efficiency requirements.
0.4
Surface mount inductors in different shape and styles are
ICIN_RMS(m) 0.3 available from Coilcraft, Elytone and Murata. Shielded
IO inductors are small and radiate less EMI noise. But they
0.2 cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
0.1
Output Capacitor
0 The output capacitor is selected based on the DC output

s
0 0.5 1
voltage rating, output ripple voltage specification and rip-

n
m
ple current rating.

ig
Figure 2. ICIN vs. Voltage Conversion Ratio The selected output capacitor must have a higher rated

es
voltage specification than the maximum desired output
For reliable operation and best performance, the input voltage including ripple. De-rating needs to be consid-

D
capacitors must have current rating higher than ICIN_RMS ered for long term reliability.
at worst operating conditions. Ceramic capacitors are

ew
preferred for input capacitors because of their low ESR Output ripple voltage specification is another important
and high current rating. Depending on the application cir- factor for selecting the output capacitor. In a buck con-
cuits, other low ESR tantalum capacitor may also be verter circuit, output ripple voltage is determined by

N
used. When selecting ceramic capacitors, X5R or X7R inductor value, switching frequency, output capacitor
type dielectric ceramic capacitors should be used for value and ESR. It can be calculated by the equation
their better temperature and voltage characteristics. Note
r
below:
Fo
that the ripple current rating from capacitor manufactures 1
are based on certain amount of life time. Further ΔV O = ΔI L × ⎛ ESR CO + -------------------------⎞
⎝ 8×f×C ⎠
de-rating may be necessary in practical design. O
d
de

Inductor where;
The inductor is used to supply constant current to output CO is output capacitor value, and
en

when it is driven by a switching voltage. For given input ESRCO is the Equivalent Series Resistor of output capacitor.
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is: When low ESR ceramic capacitor is used as output
m

capacitor, the impedance of the capacitor at the switching

VO ⎛ VO ⎞
om

ΔI L = ----------- × ⎜ 1 – --------
-⎟ frequency dominates. Output ripple is mainly caused by
f×L ⎝ V IN⎠ capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
ec

The peak inductor current is: 1

ΔV O = ΔI L × -------------------------
8×f×C
R

ΔI L O
I Lpeak = I O + --------
2 If the impedance of ESR at switching frequency domi-
ot

nates, the output ripple voltage is mainly decided by

High inductance gives low inductor ripple current but capacitor ESR and inductor ripple current. The output rip-
N

requires larger size inductor to avoid saturation. Low rip- ple voltage calculation can be further simplified to:
ple current reduces inductor core losses. It also reduces
RMS current through inductor and switches, which
ΔV O = ΔI L × ESR CO
results in less conduction loss. Usually, peak to peak rip-
ple current on inductor is designed to be 20% For lower output ripple voltage across the entire operat-
to 30% of output current. ing temperature range, X5R or X7R dielectric type of
ceramic, or other low ESR tantalum are recommended to
When selecting the inductor, make sure it is able to han- be used as output capacitors.
dle the peak current without saturation even at the high-
est operating temperature.

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 AOZ1033AI

In a buck converter, output capacitor current is continu- where;

ous. The RMS current of output capacitor is decided by GEA is the error amplifier transconductance, which is
the peak to peak inductor ripple current. It can be calcu- 200 x 10-6 A/V,
lated by: GVEA is the error amplifier voltage gain, which is 500 V/V, and
ΔI L C2 is compensation capacitor in Figure 1.
I CO_RMS = ----------
12 The zero given by the external compensation network,
capacitor C2 and resistor R3, is located at:
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When 1
f Z2 = -----------------------------------
the buck inductor is selected to be very small and induc- 2π × C C × R C
tor ripple current is high, output capacitor could be over-

s
stressed.

n
To design the compensation circuit, a target crossover

ig
frequency fC for close loop must be selected. The system
Loop Compensation
crossover frequency is where control loop has unity gain.

es
The AOZ1033A employs peak current mode control for The crossover is the also called the converter bandwidth.
easy use and fast transient response. Peak current mode Generally a higher bandwidth means faster response to
control eliminates the double pole effect of the output

D
load transient. However, the bandwidth should not be too
L&C filter. It greatly simplifies the compensation loop high because of system stability concern. When design-
design.

ew
ing the compensation loop, converter stability under all
line and load condition must be considered.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system

N
Usually, it is recommended to set the bandwidth to be
in frequency domain. The pole is dominant pole can be equal or less than 1/10 of switching frequency. The
calculated by: r
AOZ1033A operates at a frequency range from 500kHz
Fo
1 to 700kHz. It is recommended to choose a crossover fre-
f P1 = -----------------------------------
2π × C O × R L quency equal or less than 40kHz.

f C = 40kHz
d

The zero is a ESR zero due to output capacitor and its

de

ESR. It is can be calculated by:

The strategy for choosing RC and CC is to set the cross
1 over frequency with RC and set the compensator zero
en

f Z1 = ------------------------------------------------
2π × C O × ESR CO with CC. Using selected crossover frequency, fC, to calcu-
late RC:
m

where; VO 2π × C 2
om

CO is the output filter capacitor, R C = f C × ---------- × -----------------------------

-
V G ×G
FB EA CS
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
ec

where;
The compensation design is actually to shape the con- fC is desired crossover frequency. For best performance, fC is
R

verter control loop transfer function to get desired gain set to be about 1/10 of switching frequency,
and phase. Several different types of compensation net- VFB is 0.8V,
ot

work can be used for the AOZ1033A. For most cases, a GEA is the error amplifier transconductance, which is
series capacitor and resistor network connected to the 200 x 10-6 A/V, and
N

COMP pin sets the pole-zero and is adequate for a stable GCS is the current sense circuit transconductance, which is 6.68
high-bandwidth control loop. A/V.

In the AOZ1033A, FB pin and COMP pin are the inverting The compensation capacitor CC and resistor RC together
input and the output of internal error amplifier. A series R make a zero. This zero is put somewhere close to the
and C compensation network connected to COMP pro- dominate pole fP1 but lower than 1/5 of selected cross-
vides one pole and one zero. The pole is: over frequency. CC can is selected by:

G EA 1.5
f P2 = ------------------------------------------- C C = -----------------------------------
2π × C C × G VEA 2π × R C × f P1

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 AOZ1033AI

Equation above can also be simplified to: Please see the thermal de-rating curves for maximum
load current of the AOZ1033A under different ambient
CO × RL
C C = --------------------- temperature.
RC
The thermal performance of the AOZ1033A is strongly
affected by the PCB layout. Extra care should be taken
An easy-to-use application software which helps to by users during design process to ensure that the IC will
design and simulate the compensation loop can be found operate under the recommended environmental condi-
at www.aosmd.com. tions.

Thermal Management and Layout The AOZ1033A is standard SO-8 package. Several lay-
Consideration out tips are listed below for the best electric and thermal

s
performance. Figure 3 on the next page illustrates a PCB
In the AOZ1033A buck regulator circuit, high pulsing cur-

n
layout example of AOZ1033A.
rent flows through two circuit loops. The first loop starts

ig
from the input capacitors, to the VIN pin, to the LX pins, 1. The LX pins are connected to internal PFET and

es
to the filter inductor, to the output capacitor and load, and NFET drains. They are low resistance thermal con-
then return to the input capacitor through ground. Current duction path and most noisy switching node. Con-
flows in the first loop when the high side switch is on. The

D
nected a large copper plane to LX pin to help thermal
second loop starts from inductor, to the output capacitors dissipation.
and load, to the low side NMOSFET. Current flows in the

ew
second loop when the low side NMOSFET is on. 2. Do not use thermal relief connection to the VIN and
the PGND pin. Pour a maximized copper area to the
In PCB layout, minimizing the two loops area reduces the PGND pin and the VIN pin to help thermal dissipa-

N
noise of this circuit and improves efficiency. A ground tion.
plane is strongly recommended to connect input capaci- r3. Input capacitor should be connected to the VIN pin
tor, output capacitor, and PGND pin of the AOZ1033A.
Fo
and the PGND pin as close as possible.
In the AOZ1033A buck regulator circuit, the major power 4. A ground plane is preferred. If a ground plane is not
dissipating components are the AOZ1033A and the out- used, separate PGND from AGND and connect them
d

put inductor. The total power dissipation of converter cir- only at one point to avoid the PGND pin noise cou-
de

cuit can be measured by input power minus output pling to the AGND pin.
power. 5. Make the current trace from LX pins to L to Co to the
en

P total_loss = V IN × I IN – V O × I O PGND as short as possible.

6. Pour copper plane on all unused board area and
m

The power dissipation of inductor can be approximately connect it to stable DC nodes, like VIN, GND or
calculated by output current and DCR of inductor. VOUT.
om

7. Keep sensitive signal trace far away form the LX

P inductor_loss = IO2 × R inductor × 1.1
pins.
ec

The actual junction temperature can be calculated with

R

power dissipation in the AOZ1033A and thermal imped-

ance from junction to ambient.
ot

T junction = ( P total_loss – P inductor_loss ) × Θ JA

N

The maximum junction temperature of AOZ1033A is

150°C, which limits the maximum load current capability.

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 AOZ1033AI

ns
ig
es
D
ew
r N
Fo
d
de
en

Figure 3. AOZ1033A (SO-8) PCB layout

m
om
ec
R
ot
N

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 AOZ1033AI

Package Dimensions, SO-8L

D Gauge Plane Seating Plane
e 0.25
8
L

s
E E1

n
ig
es
h x 45°

D
1 C
θ

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7° (4x)

r N
A2 A
0.1
Fo
b A1
d
de
en

Dimensions in millimeters Dimensions in inches

m

Symbols Min. Nom. Max. Symbols Min. Nom. Max.

2.20
A 1.35 1.65 1.75 A 0.053 0.065 0.069
om

A1 0.10 — 0.25 A1 0.004 — 0.010

A2 1.25 1.50 1.65 A2 0.049 0.059 0.065
b 0.31 — 0.51 b 0.012 — 0.020
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5.74 c 0.17 — 0.25 c 0.007 — 0.010

D 4.80 4.90 5.00 D 0.189 0.193 0.197
R

E1 3.80 3.90 4.00 E1 0.150 0.154 0.157

1.27 e 1.27 BSC e 0.050 BSC
ot

E 5.80 6.00 6.20 E 0.228 0.236 0.244

h 0.25 — 0.50 h 0.010 — 0.020
N

L 0.40 — 1.27 L 0.016 — 0.050

0.80
Unit: mm θ 0° — 8° θ 0° — 8°

Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils.
4. Dimension L is measured in gauge plane.
5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.

Rev. 1.1 October 2010 www.aosmd.com Page 13 of 15

 AOZ1033AI

Tape and Reel Dimensions

SO-8 Carrier Tape P1 See Note 3

D1
P2
T
See Note 5
E1

E2 E

See Note 3

s
B0

n
K0 D0

ig
A0 P0 Feeding Direction
Unit: mm

es
Package A0 B0 K0 D0 D1 E E1 E2 P0 P1 P2 T
SO-8 6.40 5.20 2.10 1.60 1.50 12.00 1.75 5.50 8.00 4.00 2.00 0.25

D
(12mm) ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10

ew
SO-8 Reel

N
W1

r
Fo
S
G

N
M K
d

V
de

R
en

W
m

Tape Size Reel Size M N W W1 H K S G R V

om

12mm ø330 ø330.00 ø97.00 13.00 17.40 ø13.00 10.60 2.00 — — —

±0.50 ±0.10 ±0.30 ±1.00 +0.50/-0.20 ±0.50
ec
R

SO-8 Tape
Leader/Trailer
ot

& Orientation
N

Trailer Tape Components Tape Leader Tape

300mm min. or Orientation in Pocket 500mm min. or
75 empty pockets 125 empty pockets

Rev. 1.1 October 2010 www.aosmd.com Page 14 of 15

 AOZ1033AI

Part Marking

Z1033AI
Part Number Code
FAYWLT

n s
ig
Fab & Assembly Location Assembly Lot Code

es
Year & Week Code

D
ew
r N
Fo
d
de

LEGAL DISCLAIMER
en

Applications or uses as critical components in life support devices or systems are not authorized. AOS does not
assume any liability arising out of such applications or uses of its products. AOS reserves the right to make
m

changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the
om

product for their intended application. Customer shall comply with applicable legal requirements, including all
applicable export control rules, regulations and limitations.

AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at:
ec

http://www.aosmd.com/terms_and_conditions_of_sale
R

LIFE SUPPORT POLICY

ot

ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
N

As used herein:

1. Life support devices or systems are devices or 2. A critical component in any component of a life
systems which, (a) are intended for surgical implant into support, device, or system whose failure to perform can
the body or (b) support or sustain life, and (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in a significant injury of
the user.

Rev. 1.1 October 2010 www.aosmd.com Page 15 of 15