Datasheet

Multi-Channel Power Supply LSI Series for Car Electronics

Multi-channel Power Supply IC

for Car Audio Systems
BD49101AEFS-M
General Description Key Specifications
The BD49101AEFS-M LSI is a multi-channel power  Input Voltage Range: 5.5V to 25V(VIN0=BCAP)
supply IC that can provide all necessary supply voltages  DCDC1(controller):
for automobile audio systems. The IC has two Switching  DCDC2(with low power mode for MCU): 1A
Power Supplies (DCDC), five Regulators (REG) and a  REG1(output voltage variable): 500mA
High Side switch. This single power supply system can  REG2(output voltage variable): 100mA
provide the required voltages to all systems including the  REG3(output voltage variable): 300mA
MCU, CD, tuner, USB, illumination, audio circuits and  REG4(output voltage variable for USB): 1.5A
others.  REG5(output voltage variable): 50mA
The IC system is based on switching regulator which  High side SW: 500mA
has high efficiency then you can suppress heat of IC  Standby Current: 100µA(Typ)
than before. And it has low power mode operation or  REG4 Over Current Detect Accuracy: ±20%
voltage control function so that you can get ①High  Operating Temperature Range: -40°C to +85°C
Efficiency ②Low IQ and ③easiness of power supply  DCDC Switching Frequency: 200kHz to 500kHz
design.
Package W(Typ) x D(Typ) x H(Max)
Features HTSSOP-A44 18.50mm x 9.50mm x 1.00mm
(Note1)
 AEC-Q100 Qualified
 Integrated 7 channels of Power Supply for Car Audio
・2 DCDC (Integrated 1 Controller )
・5 REG
 1 High Side Switch channel
 Integrated Low Power Standby REG for MCU Power
Supply
 REG4 Cable Impedance Compensation
2
 I C Interface
 Selectable Oscillator Frequency using External
Resistance
 External Clock Synchronization
 Power Supply Control Function (Power on/off
Sequencer). HTSSOP-A44
 Low Voltage, Over Voltage and REG4 Over Current
Detect Flag
 Integrated Protection Circuitry:
・Over Voltage Input Protection
・Over Current Protection
・Thermal Shutdown
(Note1:Grade3)

Applications
 Car Audio and Infotainment

○Product structure:Silicon monolithic integrated circuit ○This product is not designed for protection against radioactive rays
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Pin Configuration

VOUT5 ADJ5
VIN0 EN
BCAP REG4EN
VINSW ECO
N.C. BSENS
HSW REG4OCB
GND4 SDA
SW2 SCL
FB2 SYNC
INV2 GND1
VOUT0 RT
VIN1 GND2
ADJ1 VOUT3
VOUT1 ADJ3
ADJ2 VIN3
VOUT2 VIN4
GND3 CLCAL
N.C. VOCAL
VIN2 ADJ4
SNSH VOUT4
SNSL INV1
GATE1 FB1

Figure 1. Pin Configuration(s)

Pin Description
Pin Pin
Symbol Function Symbol Function
NO NO
1 VOUT5 REG5 voltage output 23 FB1 DCDC1 Error Amp output
2 VIN0 Battery power supply connection pin 24 INV1 DCDC1 Error Amp Input
3 BCAP Back-up capacity connection pin 25 VOUT4 REG4 voltage output
4 VINSW Power supply for high side switch 26 ADJ4 REG4 output voltage adjustment
REG4 output USB cable impedance
5 N.C. － 27 VOCAL
calibration setting
6 HSW High side switch output 28 CLCAL REG4 over current protection setting
7 GND4 Ground 29 VIN4 Power supply for built-in FET REG4
8 SW2 DCDC2 switching output 30 VIN3 Power supply for built-in FET REG3
9 FB2 DCDC2 Error Amp output 31 ADJ3 REG3output voltage adjustment
10 INV2 DCDC2 Error Amp Input 32 VOUT3 REG3 voltage output
11 VOUT0 STBREG voltage output 33 GND2 Ground
12 VIN1 Power supply for built-in FET REG1 34 RT Oscillator frequency setting
13 ADJ1 REG1 output voltage adjustment 35 GND1 Ground
14 VOUT1 REG1 voltage output 36 SYNC External synchronization signal input
2
15 ADJ2 REG2 output voltage adjustment 37 SCL I C-bus clock input
2
16 VOUT2 REG2 voltage output 38 SDA I C-bus data input
17 GND3 Ground 39 REG4OCB Error flag output
18 N.C. － 40 BSENS Error flag output
19 VIN2 Power supply for built-in FET REG2 41 ECO Low power mode switch
20 SNSH DCDC1 current detection 42 REG4EN REG4 Enable
21 SNSL DCDC1 current detection 43 EN Enable
22 GATE1 DCDC1 outside FET gate drive 44 ADJ5 REG5 output voltage adjustment
“N.C” pins are not connected into internal circuits.

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Block Diagram

SNSH
20
TSD 21
SYNC SNSL
Ext CLK 36 22
DCDC1
DCDC1 GATE1
RT
34 OSC (Controller) output
FB1
23

INTERNAL 24
REGULATOR INV1
VIN0
2 SW2 DCDC2
8

BCAP output
3 9 FB2
DCDC2
BCLDET 10
/BCOVP INV2
VIN2
19 11
VOUT0
STB_REG
REG2
VOUT2
16
output REG2 LDET/OVP
ADJ2
15
VIN1
12

REG5 REG1
VOUT5 VOUT1
1 14

output REG5 REG1 output

ADJ1
ADJ5 13
44

VINSW VIN3
4 30

Hi-side SW
Hside REG3
6 VOUT3
HSW SW 32
output
REG3 output
ADJ3
31

BSENS
40 VIN4
29
REG4OCB
39 REG4
VOUT4
ECO 25
41
output
EN ADJ4
43 26
REG4EN
42 REG4
VOCAL
(calibrate) 27
SDA
38
SCL
37 I2C I/F ・Each ch on/off CLCAL
・LDET setting 28

35 33 17 7
GND1 GND2 GND3 GND4

Figure 2. Block Diagram

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Description of Blocks
・DCDC2 – STBREG Switch Function
The ECO input is used to switch between operating mode and low power standby mode.
(This function is for a 3.3V I/O microcomputer because of the 3.3V fixed STBREG output)
The function of the ECO input is as follows:
 ECO = H – Normal Operating Mode (DCDC2 operating).
 ECO = L – Low Power Standby Mode (STBREG operating).

・Sequence of VIN0 start up, Low Power Standby mode

8.3V
VIN0

①
BCAP 4.7V

Soft start
Max 5ms

DCDC2/
DCDC2 STBREG DCDC2 STBREG
STBREG 1.25V
=VIN1

1.25V
REG1

ECO

BSENS

EN
ACK

SCL

SDA
Slave Address A

Figure 3. Timing Chart of VIN0 start up, Low Power Standby Mode

① When BD49101AEFS starts up, it starts in the normal operation mode (DCDC2 operation), independent of ECO
setting. An internal regulator, the reference voltage circuit, and the OSC circuit start up when the voltage of the
BCAP pin exceeds low voltage protection release voltage (4.7V).
2
② Following the first access to the I C interface, the ECO input is able to control the operating mode (normal or low
2
power standby). ECO must be set to the desired operating mode prior to accessing the I C interface for the first
time.
③ The conditions of independent of ECO setting is shown below.
 Input power supply for VIN0 at the first time
 BCAP voltage becomes under 4.5V
 DCDC2 detects over current and DCDC2 restarts
2
At each condition ECO setting become effective after you send I C command and receive ACK.

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・Relations of BCAP Voltage and Operating Mode

When the voltage of the BCAP pin decreases under BCAP low voltage detection voltage (4.5V),
the registers are initialized and the ECO pin setting becomes invalid and forcibly changed to low power mode.
Afterwards, when BCAP voltage increases over BCAP low detection release voltage (4.7V)
without under POWER ON reset voltage (3.1V), the mode change to DCDC2 mode. (ECO pin setting is invalid.)
If BCAP voltage increases with under POWER ON reset voltage, the operation is same as VIN0 start up.

BCAP voltage

4.7V BCLDET release

4.5V BCLDET detect

3.1V POWER_ON reset voltage

0V

µ-con 3.3V supply OFF DCDC2 STBREG DCDC2 STBREG OFF DCDC2
voltage

Figure 4. Relation of BCAP Voltage and Operating Mode

・Mode Changing (Normal Operation Mode ⇔ Low Power Mode)

When the ECO pin is changed from 0V to 3.3V, it changes from the low power mode to the normal operation mode.
When it changes from the low power mode to the normal operation mode, the output voltage drops according to the
load current. (Figure 5)
(ex.) ：Supply Voltage 14.4V, Output Capacitor 100µF, Load Current 200mA: Output Drop Voltage= -80mV(Typ)
We recommend that you save consumption current of the microcomputer in 200mA within 1ms when the mode is
changed to normal operation mode (Figure 6).

3.3V
ECO
0V

3.3V
VOUT0 ～80mV

（Output Capa=100µF,Load Current 200mA）

Figure 5. Timing Chart of Mode Changing (Normal Operation Mode ⇔ Low Power Mode)

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more than 1ms

μ-con
consumption 200mA

0mA
3.3V
ECO　voltage
0V

Low power mode normal operation mode

Figure 6. Image of Increasing Consumption Current when Switching

from Low Power Mode to Normal Operation Mode

USB Supply Calibration (REG4).

The VOCAL input is used to adjust for cable impedance between the supply and USB connector. This
adjustment will correct for voltage drop across the cable as a function of the current flow thus maintaining a
constant voltage at the connector. Compensation of up to 0.5Ω of cable impedance can be achieved.
The CLCAL input is used to set the over current threshold, up to a maximum of 1.5A.Please refer 2-(3)-②
Setting of cable impedance calibration

Over Current Protection (OCP)

All regulators and high side switch have over current protection. When OCP is detected, the following
conditions will apply:
 DCDC1: After disabled for a certain period, it will attempt to restart automatically.
 DCDC2 : After disabled for a certain period, it will attempt to restart automatically
and the register will be initialized.
 REG4 – Current limit circuit will operate and REG4OCB is activated (Low).
 Other regulators and a high side switch – Current limit circuit will operate.

REG1 to 5, STBREG High side switch

VOUT

VOUT

Current at Current at IOUT

IOUT shorted
shorted
Figure 7. REG, High Side Switch Example of the Characteristics about Output Voltage vs Output Current

Battery Voltage Monitoring Function and BSENS Output

The BSENS output is active (High) when over voltage protection(OVP) is active. OVP becomes active when
VIN0 exceeds 20.2V(Typ) OVP is cleared when VIN0 falls below 18.2V(Typ).
BSENS is also active (High) when VIN0 falls below 7.8V(Typ, initial register condition), afterwards BSENS is
cleared when VIN0 exceeds 8.3V (Typ, initial register condition).
This low detection (LDET) voltage can change from 5.7V to 6.4V, and from 7.7V to 8.4V with writing register
(Initial setting is 7.8V).

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VIN0 Voltage

20.2V
18.2V
Variable in 15 steps
by I2C register setting

8.3V
7.8V

LDET detect→H OVP detect→H LDET detect→H

3.3
BSENS
0

Figure 8. Timing Chart of OVP/LDET Detection

REG4OCB Output

3.3V
REG4EN
0V

5.2V
VOUT4
0V TSS4
short output short output
3ms(typ) short output
Soft start time OCP threshold
IOCP(variable)
IOUT4
1.5A
(Load current =1.5A)
short current short current
0A (100mA typ) (100mA typ)
OCP delay time
TDELAY4
13.7ms(typ)
13.7ms(typ)
3.3V
REG4OCB

0V

Figure 9. Timing Chart of REG4OCB Output

REG4 starts by a soft start in 3ms(Typ). And when detecting over current detection the REG4OCB output is
active (Low) after 13.7ms continuous over current condition.

External Synchronization
The SYNC input is used to synchronize the switching frequency of DCDC1 and DCDC2. A signal in the
range of 200kHz – 500kHz can be input. The input signal must be at a higher frequency than that set by the
resistor on RT input and should be configured between 0.6 to 1.5 times the set frequencies.(when SYNC
Duty=45 to 55%)
When it changes from internal oscillation mode to external synchronization mode, it changes after it is inputted
continuously 3 pulses.
When it changes from external synchronization mode to internal oscillation mode, it changes within a period of
internal oscillator frequency after SYNC input sets L. When SYNC input sets H, it doesn’t change to internal
oscillation mode. The high pulse within 50ns(like unexpected noise etc.) input could stop DCDC operation. In
that case you can take measure by inserting damping resister etc. to reduce the pulse.
At first applying of power on VIN0(BCAP), SYNC pin must be under “input L level” max value until VODC2
rises up. If it is not so, the IC could not start normally.
It can adjust to the phase of switching pulse between DCDC1 and DCDC2 by the duty of SYNC input.
The switching positive edge timing of DCDC1,2 is below.
 DCDC1: synchronized the negative edge of SYNC input.
 DCDC2: synchronized the positive edge of SYNC input

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The EN and the REG4EN pins

When the EN pin is set to H, I2C register setting is available, and when set to L, all register reset.
This function enable all REG and HSW channel expect DCDC2/STBREG and REG1 to OFF.
REG4EN is the enable pin of REG4 and can control REG4 through REG4_EN register or REG4EN.
When the EN pin is set to L, REG4 becomes OFF even if the REG4EN pin is set to H.

Output Conditions
Input Pin Register
STBREG DCDC2 REG1 DCDC1 REG2,3,5 REG4 HSW

L=OFF Reset
EN － － －
need resetting when turning ON (input"L")
L=OFF
REG4EN － － － － －
H=ON (Note 1)
－ －

L=STBREG
ECO H=DCDC2
－ － － － － －

(Note 1) When the EN pin input H.

Figure 10. Table of EN control

2
I C Interface
2
The I C interface allows access to the internal registers. The internal registers are used for the following
functions:
 Enable the high side switch and power supplies except for DCDC2-STBREG.
 Setting LDET – VIN0 low voltage detection threshold.
 Detecting high side switch over current condition (address 0x04)

For Protect and Detect Functions and Enable Function

Output Conditions Error Flag

Register
STBREG DCDC2 REG1 DCDC1 REG2,3,5 REG4 HSW BSENS REG4OCB

fold back － － － － － － － －
STBREG －
limit

－ restart － (Note 2) － －
DCDC2 (Note 1) OFF Reset
fold back
REG1 － － － － － － － － －
limit
over
restart
current DCDC1 － － － － － － － － －
(Note 1)
detection fold back
REG2,3,5 － － － － － － － － －
limit
fold back
REG4 － － － － －
limit
－ ○ －

－ － － － － － fold back － － －
HSW limit

－ － － (Note 3) － － －
TSD OFF
tharmal LDET － － － － － － －
power ○ － －
supply OVP － － － － － － －
voltage ON OFF
detection BCLDET (Note 4) (Note 4)
－ OFF(Note 2) － － Reset

BCOVP － － － OFF(Note 3) － － －

(Note 1) When detecting each output is limited in minimum duty and dropping output and INV voltage then restarts after 1024clk.
(Note 2) When detecting each output doesn’t restart.
(Note 3) When detecting each output restarts.
(Note 4) When detecting BCAP low voltage the operation mode switches to standby mode without depending on the ECO setting.

Figure 11. Table of EN Protect and Detect Functions

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Absolute Maximum Ratings(Ta=25°C)

Parameter Symbol Limits Unit

Power Supply Voltage (PIN2,4,19) VCC -0.3 to +42 V

Input Voltage (PIN37,38,41-43) Vin -0.3 to +7 V

Pin Voltage 1(PIN1,3,6,8,16,22) VPIN1 -0.3 to +42 V

Pin Voltage 2(PIN20,21) VPIN2 VIN0 – 7 to VIN0 V

Pin Voltage 3(PIN9-15,23-32,34,36,39,40,44) VPIN3 -0.3 to +7 V

Operating Temperature Range Topr -40 to +85 °C

Storage Temperature Range Tstg -55 to +150 °C

(Note 1)
Power Dissipation Pd 6.19 W

Maximum Junction Temperature Tjmax 150 °C

3 2
(Note 1) Reduce by 49.5mW/°C, when mounted on 4-layer PCB of 70x70x16mm (Copper foil area on the reverse side of PCB: 70x70mm ).
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated
over the absolute maximum ratings.

Recommended Operating Ratings

Parameter Symbol Limits Unit

Operating Power Supply Voltage1(VIN0,BCAP) VINopr 5.5 to 25 V

Output Voltage Range 1(DCDC1/2) VOUTopr1 0.8 to VINopr V

0.8 to 2.4 (REG1)
Output Voltage Range 2(REG1/3/4) VOUTopr2 0.8 to VIN3,4 - VSATRG3,4 V
(REG3.4)
0.8 to 10.5 (REG2)
Output Voltage Range 3(REG2/5) VOUTopr3 V
0.8 to 8.5 (REG5)

DCDC Switching Frequency fSW 200 to 500 kHz

Oscillator Frequency Setting Resistance RT 27 to 82 kΩ

External Sync Frequency fCLK 200 to 500 kHz

External Synchronization Pulse Duty DCLK 20 to 80 %

REG4 Over Current Detection Set Resistance RCLCAL 5 to 50 kΩ

REG4 Cable Impedance Compensation Set Resistance RVOCAL 0 to 230 Ω

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Electrical Characteristics

(Unless otherwise specified, Ta= 25°C, VIN0=BCAP=14.4V, EN=3.3V, VOUT1=1.25V, VOUT2=5.78V, VOUT3=3.3V,
VOUT4=5.2V, VOUT5=5.0V)
Spec Values
Parameter Symbol Unit Conditions
Min Typ Max
【Consumption Current】

Standby Current ISTB － 100 150 μA ECO=0V, EN=0V

ECO=3.3V, EN=3.3V, Io=0A
Circuit Current IQ － 5.0 7.5 mA
ENABLE=0x7F
【Over Voltage Detection】

Detection Threshold Voltage VOVPON 18.2 20.2 22.2 V

Release Threshold Voltage VOVPOFF 16.2 18.2 20.2 V

【Low Voltage Detection】

Detection Threshold Voltage VLDETON 7.5 7.8 8.1 V

LDET_SETTING=0x09
Release Threshold Voltage VLDETOFF 8.0 8.3 8.6 V

【OSC】

Oscillator Frequency FOSC 285 300 315 kHz RT=51kΩ

【DCDC1】

Reference Voltage VREF1_DC1 0.784 0.800 0.816 V

Over Current Detection
VOCP_TH_DC1 - 0.1 - V SNSH-SNSL
Threshold Voltage
Maximum FB1 Voltage VFB1H - 3.0 - V INV1=0V

Minimum FB1 Voltage VFB1L - 0.8 - V INV1=2V

FB1 Sink Current IFB1SINK -800 -400 -200 µA FB1=1V, INV1=1V

FB1 Source Current IFB1SOURCE 50 100 200 µA FB1=1V, INV1=0.6V

VIN
Maximum GATE1 Voltage VGT1H - - V INV1=2V
+0.3V
Minimum GATE1 Voltage VGT1L 8.1 - - V INV1=0V

Soft Start TSS1 - - 5 ms

【DCDC2】

Reference Voltage VREF1_DC2 0.784 0.800 0.816 V

Output Current Capacity IODC2 1 - - A

Maximum FB2 Voltage VFB2H - 3.0 - V INV2=0V

Minimum FB2 Voltage VFB2L - 0.8 - V INV2=2V

FB2 Sink Current IFB2SINK -800 -400 -200 µA FB2=1V, INV2=1V

FB2 Source Current IFB2SOURCE 50 100 200 µA FB2=1V, INV2=0.6V

Soft Start TSS2 - - 5 ms

Power MOS FET ON
RON 125 250 500 mΩ IO=800mA
Resistance

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Spec Values
Parameter Symbol Unit Conditions
Min Typ Max
【STBREG】

Reference Voltage VREF_STLD 3.234 3.300 3.366 V

Load Current Capacity IOSTLD 200 - - mA

Line Regulation ⊿VISTLD - - 15 mV VIN0=7 to 18V, Io=5mA

Load Regulation ⊿VLSTLD - - 30 mV IO=5m to 200mA

Ripple Rejection RRSTLD - 70 - dB Frp=100Hz, VIN0rp=1Vpp

I/O Voltage Difference VSATSTLD - - 0.6 V IO=100mA

【REG1】

Reference Voltage VREF_LD1 0.588 0.600 0.612 V

Load Current Capacity IOLD1 500 - - mA VIN1=3.3V

Line Regulation ⊿VILD1 - - 10 mV VIN1=3 to 6V, Io=5mA

Load Regulation ⊿VLLD1 - - 20 mV IO=5m to 500mA

Ripple Rejection RRLD1 - 70 - dB Frp=100Hz, VIN1rp=1Vpp

I/O Voltage Difference VSATLD1 - - 1.0 V IO=250mA

【REG2】

Reference Voltage VREF_LD2 0.777 0.793 0.809 V

Load Current Capacity IOLD2 100 - - mA

Line Regulation ⊿VILD2 - - 25 mV VIN2=9 to 18V, Io=5mA

Load Regulation ⊿VLLD2 - - 50 mV IO=5mA to 100mA

Ripple Rejection RRLD2 - 70 - dB Frp=100Hz, VIN2rp=1Vpp

I/O Voltage Difference VSATLD2 - - 0.65 V IO=50mA

【REG3】

Reference Voltage VREF_LD3 0.784 0.800 0.816 V

Load Current Capacity IOLD3 300 - - mA VIN3=6V

Line Regulation ⊿VILD3 - - 20 mV VIN3=4.0 to 6.5V, Io=5mA

Load Regulation ⊿VLLD3 - - 40 mV IO=5m to 300mA

Ripple Rejection RRLD3 - 70 - dB Frp=100Hz, VIN3rp=1Vpp

I/O Voltage Difference VSATLD3 - - 0.6 V IO=150mA

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Spec Values
Parameter Symbol Unit Conditions
Min Typ Max
【REG4】

Reference Voltage VREF_RG4 0.784 0.800 0.816 V

Load Current Capacity IORG4 1.5 － － A VIN4=6V,VOCAL=0Ω

Line Regulation ⊿VIRG4 － － 50 mV VIN4=5.6 to 6.5V, Io=5mA

Load Regulation ⊿VLRG4 － － 40 mV Io=5m to 1.5A

Ripple Rejection RRRG4 － 55 － dB Frp=100Hz, VIN4rp=1Vpp

I/O Voltage Difference VSATRG4 － － 0.4 V Io=1.5A

Over Current Detection VIN4=6V, CLCAL= 6.8kΩ,
IOCP1 1.18 1.47 1.76 A
Threshold 1 VOCAL=0Ω
Over Current Detection VIN4=6V, CLCAL= 15kΩ,
IOCP2 534 667 800 mA
Threshold 2 VOCAL=0Ω
Voltage Adjusted For Cable VIN4=6.5V,Io=1.0A,
Vcal 5.32 5.46 5.60 V
Impedance(0.26Ω) VOCAL=120Ω
Soft Start Time TSS4 － 3 － ms

OCP Delay Time TDELAY4 8.7 13.7 18.7 ms fsw = 300kHz

【REG5】

Reference Voltage VREF_RG5 0.784 0.800 0.816 V

Load Current Capacity IORG5 50 － － mA

Line Regulation ⊿VIRG5 － － 25 mV VIN0=9 to 18V, Io=5mA

Load Regulation ⊿VLRG5 － － 50 mV Io=5mA to 50mA

Ripple Rejection RRRG5 － 70 － dB Frp=100Hz, VIN5rp=1Vpp

I/O Voltage Difference VSATRG5 － － 0.65 V Io=25mA

【High Side SW】

Output Current Capacity IOSW1 500 - - mA

ON Resistance RON_SW1 － - 3 Ω IO=500mA

【Digital IO】
(EN,REG4EN,ECO,SYNC,BSENS,REG4OCB)
For pin EN, REG4EN,
Input H level VIH 2.6 - - V
ECO,SYNC
For pin EN, REG4EN,
Input L level VIL - - 0.8 V
ECO,SYNC
Input Pulldown Resistance1 RIND1 － 100k － Ω For pin REG4EN, ECO,SYNC

Input Pulldown Resistance2 RIND2 － 660k － Ω For pin EN

For pin BSENS,REG4OCB
Output H level VOH 2.6 - - V
IO=1mA
For pin BSENS,REG4OCB
Output L level VOL - - 0.8 V
IO= -1mA

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Typical Performance Curves(reference)

200 200

150 150
Standby Current[μA]

Standby Current[μA]
100 100

50 50

0 0
-40 -20 0 20 40 60 80 0 5 10 15 20 25
Ambient Temperature:Ta[°C] Input Voltage:VIN[V]

Figure 12. Standby Current vs Temperature Figure 13. Standby Current vs Input Voltage

8 8

7 7

6
Circuit Current:ICC[mA]

6
Circuit Current:ICC[mA]

5 5

4 4

3 3

2 2

1 1

0 0
-40 -20 0 20 40 60 80 0 5 10 15 20 25
Ambient Temperature:Ta[°C] Input Voltage:VIN[V]

Figure 14. Circuit Current vs Temperature Figure 15. Circuit Current vs Input Voltage

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315 0.816

312 0.812
Oscillator Frequency:fosc[kHz]

309

Reference Voltage:VREF[V]
0.808
306
0.804
303

300 0.8

297 0.796
294
0.792
291
0.788
288 RT=51kΩ
285 0.784
-40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80
Ambient Temperature:Ta[°C] Ambient Temperature:Ta[℃]

Figure 16. Oscillator Frequency vs Temperature Figure 17. DCDC1 Reference Voltage vs Temperature

100 6.09

90
6.06
80
Output Voltage:Vo[V]

70
6.03
Efficiency[%]

60

50 6.00

40
5.97
30

20
VIN0 =14.4V 5.94
10 VO=6.0V VIN0 =14.4V
f=300kHz VO=6V
0 5.91
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Output Current:lo[A] Output Current:lo[A]

Figure 18. DCDC1 Efficiency vs Output Current Figure 19. DCDC1 Output Voltage vs Output Current

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0.816 100

90
0.812
80
Reference Voltage:VREF[V]

0.808
70

Efficiency[%]
0.804
60

0.800 50

0.796 40

30
0.792
20
VIN0=14.4V
0.788
10 VO=3.3V
f=300kHz
0.784 0
-40 -20 0 20 40 60 80 0.0 0.2 0.4 0.6 0.8 1.0
Ambient Temperature:Ta[°C] Output Current:lo[A]

Figure 20. DCDC2 Reference Voltage vs Temperature Figure 21. DCDC2 Conversion Efficiency vs Output Current

3.42 525

475
3.40
ON Resistance:Ron[mΩ]

425
Output Voltage:Vo[V]

375
3.38

325

3.36 275

225
3.34
VIN0=14.4V
f=300kHz 175
Io=800mA
3.32 125
0.0 0.2 0.4 0.6 0.8 1.0 -40 -20 0 20 40 60 80
Output Current:lo[A] Ambient Temperature:Ta[°C]

Figure 22. DCDC2 Output Voltage vs Output Current Figure 23. DCDC2 FET ON Resistance vs Temperature

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525 3.366

475
3.344

Reference Voltage:VREF[V]
ON Resistance:Ron[mΩ]

425
3.322
375

325 3.300

275
3.278
225
3.256
175
Io=800mA
125 3.234
0 5 10 15 20 25 -40 -20 0 20 40 60 80
Input Voltage:VIN[V] Ambient Temperature:Ta[°C]

Figure 24. DCDC2 FET ON Resistance vs Input Voltage Figure 25. STBREG Reference Voltage vs Temperature

3.50 90
Io=5mA
80
3.00 Io=20mA
70
Output Voltage:Vo[V]

Ripple Rejection:RR[dB]

2.50
60

2.00 50

1.50 40

30 Io=200mA
1.00
20
0.50 VIN0 =14.4V
10
Vrp=1Vpp
0.00 0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 100 1k 10k 100k
Output Current:lo[A] Frequency:f[Hz]

Figure 26. STBREG Output Voltage vs Output Current Figure 27. STBREG Ripple Rejection vs Frequency

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3.5 0.612

3.0
0.608

Reference Voltage:VREF[V]
Output Voltage:Vo[V]

2.5
0.604
2.0
0.600
1.5

0.596
1.0

0.5 0.592

Io=100mA
0.0 0.588
0 5 10 15 20 25 -40 -20 0 20 40 60 80
Input Voltage:VIN[V] Ambient Temperature:Ta[°C]

Figure 28. STBREG Output Voltage vs Input Voltage Figure 29. REG1 Reference Voltage vs Temperature

1.4 90
VIN1 =3.3V
80
1.2 Vrp=1Vpp
70
Ripple Rejection:RR[dB]
Output Voltage:Vo[V]

1.0
60

0.8 50
Io=5mA
40
0.6
Io=100mA
30
0.4
20
0.2 10
VIN1=3.3V
VO=1.25V Io=1000mA
0.0 0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 100 1k 10k 100k

Output Current:lo[A] Frequency:f[Hz]

Figure 30. REG1 Output Voltage vs Output Current Figure 31. REG1 Ripple Rejection vs Frequency

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2.0 0.816

0.812

Reference Voltage:VREF[V]
1.5 0.808
Output Voltage:Vo[V]

0.804

1.0 0.800

0.796

0.5 0.792

VO=1.25V 0.788
Io=250mA
0.0 0.784
0 1 2 3 4 5 6 7 -40 -20 0 20 40 60 80
Input Voltage:VIN[V] Ambient Temperature:Ta[°C]

Figure 32. REG1 Output Voltage vs Input Voltage Figure 33. REG2 Reference Voltage vs Temperature

10 90

9 80
8 Io=5mA
70
Ripple Rejection:RR[dB]
Output Voltage:Vo[V]

7
60
6
50
5 Io=10mA
40
4
30
3 Io=100mA
20
2
VIN2 =14.4V
1 VIN2=14.4V 10
Vrp=1Vpp
VO=8.8V
0 0
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 100 1k 10k 100k
Output Current:lo[A] Frequency:f[Hz]

Figure 34. REG2 Output Voltage vs Output Current Figure 35. REG2 Ripple Rejection vs Frequency

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10 0.816

0.812
8

Reference Voltage:VREF[V]
0.808
Output Voltage:Vo[V]

0.804
6

0.800

4 0.796

0.792
2
VO=8.8V 0.788
Io=50mA
0 0.784
0 5 10 15 20 25 -40 -20 0 20 40 60 80
Input Voltage:VIN[V] Ambient Temperature:Ta[°C]

Figure 36. REG2 Output Voltage vs Input Voltage Figure 37. REG3 Reference Voltage vs Temperature

3.5 90

80
3.0
70
Output Voltage:Vo[V]

Ripple Rejection:RR[dB]

2.5 Io=5mA
60
2.0 50

1.5 40

30 Io=30mA
1.0
20 Io=300mA

0.5
VIN3=6V 10 VIN3 =6V
VO=3.3V Vrp=1Vpp
0.0 0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 100 1k 10k 100k
Output Current:lo[A] Frequency:f[Hz]

Figure 38. REG3 Output Voltage vs Output Current Figure 39. REG3 Ripple Rejection vs Frequency

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6.0 0.816
5.5
0.812
5.0

Reference Voltage:VREF[V]
4.5 0.808
Output Voltage:Vo[V]

4.0
0.804
3.5
3.0 0.800
2.5
0.796
2.0
1.5 0.792
1.0
0.788
0.5 VO=3.3V
Io=150mA
0.0 0.784
0 1 2 3 4 5 6 7 -40 -20 0 20 40 60 80
Input Voltage:VIN[V] Ambient Temperature:Ta[°C]

Figure 40. REG3 Output Voltage vs Input Voltage Figure 41. REG4 Reference Voltage vs Temperature

6 90
VIN4=6V
80 Vrp=1Vpp
5
70
Output Voltage:Vo[V]

Ripple Rejection:RR[dB]

Io=5mA
4 60

50
3
40 Io=150mA

2 30

VIN4=6V 20 Io=1500mA
1 VO=5.2V
RCLCAL=6.8kΩ
RVOCAL=0Ω 10

0 0
0.0 0.4 0.8 1.2 1.6 100 1k 10k 100k
Output Current:Io[A] Frequency:f[Hz]

Figure 42. REG4 Output Voltage vs Output Current Figure 43. REG4 Ripple Rejection vs Frequency

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6.0 5.19
5.5
5.17
5.0
4.5 5.15
Output Voltage:Vo[V]

Output Voltage:Vo[V]
4.0
5.13
3.5
3.0 5.11
2.5
5.09
2.0
1.5 5.07
1.0
Io=1.5A 5.05 VIN4=6V
0.5 RVOCAL=0Ω RVOCAL=120Ω
0.0 5.03
0 1 2 3 4 5 6 7 0.0 0.5 1.0 1.5
Input Voltage:VIN[V] Output Current:lo[A]

Figure 44. REG4 Output Voltage vs Input Voltage Figure 45. Voltage Adjusted for Cable Impedance
vs Output Current

0.816 6

0.812
5
Reference Voltage:VREF[V]

0.808
Output Voltage:Vo[V]

4
0.804

0.800 3

0.796
2
0.792
1
0.788 VIN5=14.4V
VO=5V
0.784 0
-40 -20 0 20 40 60 80 0.00 0.02 0.04 0.06 0.08 0.10 0.12
Ambient Temperature:Ta[°C] Output Current:lo[A]

Figure 46. REG5 Reference Voltage vs Temperature Figure 47. REG5 Output Voltage vs Output Current

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90 6.0
5.5
80
5.0
70
4.5

Output Voltage:Vo[V]
Ripple Rejection:RR[dB]

60 Io=5mA 4.0
3.5
50
3.0
Io=10mA
40 2.5
30 2.0
Io=50mA 1.5
20
1.0
10 VIN5=14.4V
Vrp=1Vpp 0.5 Io=25mA
0 0.0
100 1k 10k 100k 0 5 10 15 20 25

Frequency:f[Hz] Input Voltage:VIN[V]

Figure 48. REG5 Ripple Rejection vs Frequency Figure 49. REG5 Output Voltage vs Input Voltage

16 3.0

14
ON Resistance:Ron[Ω]

12 2.5
Output Voltage:Vo[V]

10

8 2.0

4 1.5

2
VIN0=14.4V VIN0=14.4V
0 1.0
0 200 400 600 800 1000 1200 -40 -20 0 20 40 60 80
Output Current:lo[mA] Ambient Temperature:Ta[°C]

Figure 50. HSW Output Voltage vs Output Current Figure 51. HSW ON Resistance vs Temperature

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3.0
ON Resistance:Ron[Ω]

2.5

2.0

1.5

1.0
0 5 10 15 20 25
Input Voltage:VIN[V]

Figure 52. HSW ON Resistance vs Input Voltage

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2
I C-bus Block
(1) Electrical Specifications and Timing for Bus Lines and I/O Stages

SDA

tBUF
tF tHD;STA tSP
tLOW tR T

SCL

tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA Sr tSU;STO

T T
P S P

2
Figure 53. Definition of timing on the I C-bus

2
Table 1. Characteristics of the SDA and SCL Bus Lines for I C-bus Devices
(Unless specified particularly, Ta=25°C, VIN0=14.4V)
2
Fast-mode I C-bus
Parameter Symbol Unit
Min Max
1 SCL Clock Frequency fSCL 0 400 kHz
2 Bus Free Time between a STOP and START Condition tBUF 1.3 － μs
Hold Time (repeated) Start Condition
3 tHD;STA 0.6 － μs
(After this period, the first clock pulse is generated.)
4 LOW Period of the SCL Clock tLOW 1.3 － μs
5 HIGH Period of the SCL Clock tHIGH 0.6 － μs
6 Set-up Time for a Repeated START Condition tSU;STA 0.6 － μs
0.06
7 Data Hold Time tHD;DAT (Note 1) － μs
8 Data Setup Time tSU;DAT 120 － ns
9 Setup Time for STOP Condition tSU;STO 0.6 － μs
All values referred to VIH min and VIL max levels (see Table 2).

(Note 1) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min. of the SCL signal) in order to bridge the
undefined region of the falling edge of SCL.
About 7(tHD;DAT), 8(tSU;DAT), make it the setup which a margin is fully in .

2
Table 2. Characteristics of the SDA and SCL I/O stages for I C-bus Devices
Fast-mode devices
Parameter Symbol Unit
Min Max
10 LOW Level Input Voltage: VIL -0.3 +1 V
11 HIGH Level Input Voltage: VIH 2.3 5 V
12 Pulse Width of Spikes which must be suppressed by the input filter. tSP 0 50 ns
13 LOW Level Output Voltage: at 3mA sink current VOL1 0 0.4 V
14 Input Current each I/O pin with an input voltage between 0.4V and 4.5V. Ii -10 +10 μA

ｔHD;STA ｔHD;DAT ｔSU;DAT ｔSU;STO

：2us ：1us ：1us ：2us

SCL

ｔBUF ｔLOW ｔHIGH

：4us ：3us ：1us

SDA

SCL clock frequency：250kHz

2
Figure 54. A Command Timing Example in the I C Data Transmission

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2
(2)I C-bus Format

MSB LSB MSB LSB MSB LSB

S Slave Address A Select Address A Data A P
1bit 8bit 1bit 8bit 1bit 8bit 1bit 1bit
S = Start Conditions (Recognition of Start Bit)
Slave Address = Recognition of Slave Address. 7 bits in upper order are voluntary.
The least significant bit is “L” due to writing.
A = Acknowledge Bit (SDA “L”)
A = Not Acknowledge Bit (SDA “H”)
Select Address = Select ENABLE / LDET SETTING / HSW OCP.
Data = Data on ENABLE / LDET SETTING / HSW OCP
P = Stop Condition (Recognition of Stop Bit)
2
(3)I C-bus Interface・Protocol

1)Write Mode Fundamental

S Slave Address A Select Address A Data A P
MSB LSB MSB LSB MSB LSB

2)Auto Increment(The selection address does increment(+1) the number of data.)

S Slave Address A Select Address A Data1 A Data2 A ････ DataN A P
MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB
(Example) ①Data 1 is set as data of the address specified in the selection address.
②Data 2 is set as data of the address specified in the selection address +1.
③Data N is set as data of the address specified in the selection address +N-1

3)Composition that cannot be transmitted(In this case, the selection address only 1 is set.)
S Slave Address A Select Address1 A Data A Select Address 2 A Data A P
MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB
(Attention) When you transmit data as selection address 2 next to data,
it doesn't recognize as selection address 2, and it recognizes it as
data.

4)Read Mode Protocol(Address 0x04 Read)

S Slave Address A REQ Address A Select Address A P
MSB 0xD8 LSB MSB 0xD0 LSB MSB 0x04 LSB

S Slave Address A ※READ DATA A P

MSB 0xD9 LSB MSB LSB Because read data outputs with synchronizing with falling edge
of SCL, it latches with synchronizing with rising edge of SCL.

(4)Slave Address

MSB LSB
A6 A5 A4 A3 A2 A1 A0 R/W
1 1 0 1 1 0 0 1/0

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Register Map

Select DATA
Items init
Address D7 D6 D5 D4 D3 D2 D1 D0
ENABLE 01 0x02 － HSW_EN REG5_EN REG4_EN REG3_EN REG2_EN REG1_EN DCDC1_EN
LDET
02 0x09 － － － － LDET[3:0]
SETTING
HSW HSW
04 0x00 － － － － － － －
OCP OCP

・Select Address 01 : ENABLE

Select DATA
Items init
Address D7 D6 D5 D4 D3 D2 D1 D0
ENABLE 01 0x02 － HSW_EN REG5_EN REG4_EN REG3_EN REG2_EN REG1_EN DCDC1_EN
D[0]: DCDC1_EN ・・・DCDC1 enable control. D[4]: REG4_EN ・・・REG4 enable control.
“0”: OFF (Initial Value) “0”: OFF (Initial Value)
“1”: ON “1”: ON
D[1]: REG1_EN ・・・REG1 enable control. D[5]: REG5_EN ・・・REG5 enable control.
“0”: OFF “0”: OFF (Initial Value)
“1”: ON (Initial Value) “1”: ON
D[2]: REG2_EN ・・・REG2 enable control. D[6]: HSW_EN ・・・HSW enable control.
“0”: OFF (Initial Value) “0”: OFF (Initial Value)
“1”: ON “1”: ON
D[3]: REG3_EN ・・・REG3 enable control.
“0”: OFF (Initial Value)
“1”: ON

・Select Address 02 : LDET SETTING

Select DATA
Items init
Address D7 D6 D5 D4 D3 D2 D1 D0
LDET
02 0x09 － － － － LDET[3:0]
SETTING
D[3:0]: LDET ・・・ The low voltage detect threshold of the pin VIN0 is set. When the pin VIN0 becomes below the set
threshold, the pin BSENS becomes L.
“0000”: 5.7V “1000”: 7.7V
“0001”: 5.8V “1001”: 7.8V (Initial Value)
“0010”: 5.9V “1010”: 7.9V
“0011”: 6.0V “1011”: 8.0V
“0100”: 6.1V “1100”: 8.1V
“0101”: 6.2V “1101”: 8.2V
“0110”: 6.3V “1110”: 8.3V
“0111”: 6.4V “1111”: 8.4V

・Select Address 04 : HSW OCP (Read only)

Select DATA
Items Init
Address D7 D6 D5 D4 D3 D2 D1 D0
HSW HSW
04 0x00 － － － － － － －
OCP OCP
D[0]: HSW OCP ・・・ Detecting HSW over current condition
“0”: No detected (Initial Value)
“1”: Detected

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Application Example

4.7µF
50V
SNSH
20
TSD 21 24mΩ(OCP:4.2A)

SYNC SNSL
Ext CLK 36 22 6.0V
Damping 22µH DCDC1
DCDC1 GATE1
Resistor
RT CD-Drive
51kΩ
34 OSC (Controller) 100µF
16V 130kΩ
560pF
output
16V
(fosc=300kHz) FB1 1%
1%
23 39kΩ 1kΩ
680pF 390pF
INTERNAL 24 6.3V 6.3V 20kΩ
VBAT LC filter
REGULATOR INV1 1%
VIN0
2 SW2
3.3V
1µF 8 47µH DCDC2
50V
390pF
μ-con
BCAP 100µF 240kΩ 10V output
1%
220µF 3 9 FB2 10V
1kΩ
50V 75kΩ
1000µF
50V
DCDC2 470pF 220pF
10µF BCLDET 6.3V 6.3V 75kΩ
50V 10 1%
/BCOVP INV2
VIN2
19 11
1µF VOUT0
8.8V 50V STB_REG
REG2
VOUT2
Audio 16
output 1µF 390kΩ REG2 LDET/OVP
16V 1% ADJ2
15
39kΩ VIN1
1%
12
1µF
10V 1.25V
5.0V REG5 REG1
VOUT5 VOUT1
LCD 1 14 μ-con RAM
output 1µF 430kΩ REG5 REG1 470kΩ
1%
4.7µF output
1% ADJ1 10V
16V ADJ5 13
44 430kΩ
82kΩ 1%
1%

VINSW VIN3
4 30
4.7µF 1µF

Hi-side SW 50V 10V

REG3
3.3V
Hside
ILM 6 VOUT3
output HSW SW 32 Tuner
REG3 470kΩ 4.7µF output
ADJ3 1%
10V
31
150kΩ
1%

BSENS
40 VIN4
29
1µF
REG4OCB 10V 5.2V
39 REG4
VOUT4
ECO 25 USB
41
880kΩ 120µF output
EN ADJ4 1% 10V
43 26
160kΩ
1%
REG4EN
42 REG4
VOCAL
(calibrate) 27
120Ω 4.7µF
SDA 6.3V
38 (VCAL:0.26Ω setting)
1%
SCL
37 I2C I/F ・Each ch on/off CLCAL
・LDET setting 28
5.1kΩ
(OCP:1.96A setting)
35 33 17 7 1%
GND1 GND2 GND3 GND4

Please put this BCAP capacitor near the BCAP pin as much as possible.
※　We recommend you use less than 1% accuracy resistor with voltage, frequency, OCP detect and cable compensation setting.
※ This in an example. Please decide all parts after enough evaluations and verifications.

Figure 55. Application Example

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Selection of Components Externally Connected

1. Setting External Components for DCDC
Vin
Cbulk
SNSH Cin

Rcl
SNSL
GATE1
L
DCDC Vo
(Controller) D Co C1
R1 Rs
FB1
R3
C2 R2
INV1

Figure 56. External Components for DCDC

(1) Setting Output Voltage

To set output voltage, connect R1 between VOUT and INV, R2 between INV and GND.
Furthermore, set the R1 and R2 to 10k–1MΩ.
VOUT = VINV x (R1 + R2)/R2 [V]
VINV : INV Voltage 0.8V(Typ),

(2) Selection of Coil L

The value of the coil can be obtained by the formula shown below:
( V IN - VO ) × VO
L =
V IN × f × ΔI L
△IL: Output Ripple Current
△IL should typically be approximately 20 to 30% of Iomax (the maximum load current of DCDC)

If this coil is not set to the optimum value, normal (continuous) oscillation may not be achieved. Furthermore, set the
value of the coil with an adequate margin so that the peak current passing through the coil will not exceed the rated
current of the coil.

(3) Selection of Output Capacitors

The output capacitor can be determined according to the output ripple voltage △Vpp required. Obtain the required ESR
value by the formula shown below and then select the capacitance.

( V IN - VO ) × VO
ΔIL =
L × f × V IN
ΔIL × V O
ΔVpp = ΔIL × ESR +
2 × Co × f × V IN

Set the rating of the capacitor with an adequate margin to the output voltage. Also, set the maximum allowable ripple
current with an adequate margin to △IL. Furthermore, the output rise time should be shorter than the soft start time.
Select the output capacitor having a value smaller than that obtained by the formula shown below.

1.7ms × { ILIMIT - I O(Max) }

C MAX =
VO
ILIMIT: DCDC Over Current Limit Value 0.1/Rcl[A] (DCDC1)
3.6 [A] (DCDC2)
Rcl: Resistance between SNSH and SNSL

If these capacitances are not optimum, faulty startup may result.

( ※1.7m is soft start time(min) )

(4) Selection of Diodes

Set diode rating with an adequate margin to the maximum load current. Also, make setting of the rated inverse voltage
with an adequate margin to the maximum input voltage.
A diode with a low forward voltage and short reverse recovery time will provide high efficiency.

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(5) Selection of Input Capacitors

Be sure to insert a ceramic capacitor of 2 to 10µF for Cin
Furthermore, connect the capacitor Cbulk to keep input voltage.
The capacitor Cbulk should have a low ESR and a significantly large ripple current. The ripple current IRMS can be
obtained by the following formula:

IRMS = Io x Vo x ( Vin – Vo ) / Vin2

Select capacitors that can accept this ripple current.

If the capacitance of CIN and C28 is not optimum, the IC may malfunction.

(6) Setting of Phase Compensation

The following section summarizes the targeted characteristics of this application for the stability condition of DCDC.
・At a 1(0dB)gain, the phase delay is 150°or less(i.e. the phase margin is 30° or more).
・The GBW for this occasion is 1/10 or less of the switching frequency.
Vin

L Vo

Re
D
Co

Figure 57. LC Filter of DCDC

1
fr = [Hz] (LC Resonance Point)
2π × L × Co
1
fESR = [Hz] (Phase Lead)
2π × Re × Co
Replace a secondary phase delay(-180°) with a secondary phase lead by inserting two-phase leads, to ensure
the stability through the phase compensation.
Vo
C3

C1 C2 R3
R1
Rs

ERR1
R2 INV1
FB1

Figure 58. Phase Compensation

1 [Hz] (Phase Lead)
f z1 =
2π × R1 × C1
1
f z2 = [Hz] (Phase Lead)
2π × R3 × C2
Setting fz1,fz2 to be half to 2 times a frequency as large as fr provides an appropriate phase margin.
For output capacitors that have high ESR, because fESR(phase lead) occurs near LC resonance point,
it is unnecessary to insert fz1(phase lead).
For output capacitors that have low ESR, insert fz1(phase lead) and fp1 obtained by the following formula
and adjust frequency response.
C2 + C3 [Hz] (Phase Delay)
fp1 =
2π × R3 × C2 × C3

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The setting value above is simple estimate. Consequently, the setting may be adjusted on the actual system.
Furthermore, since these characteristics vary with the layout of PCB loading conditions, precise calculations
should be made on the actual system.
To check on the actual frequency characteristics, use a FRA or a gain-phase analyzer. Moreover, there is a
method of guessing the room degree by the loading response, too, when these measuring instruments do not
exist. The response is low when the change of the output when it is made to change under no load to the
maximum load is monitored, and there are a lot of variation quantities. It can be said that the phase margin
degree is little when there are a lot of ringing frequencies after it changes. As the standard, it is two times or
more of ringing. However, a quantitative phase margin degree cannot be confirmed.

Maximum load
Load
0

Inadequate phase margin

Output voltage

Adequate phase margin

Figure 59. Load Response

(7) Setting of the Threshold for DCDC1 Over Current Protection

When the peak of the inductor current gets over the over current protection values, over current protection circuit
operates. The over current protection values can be obtained by the following formula:
100mV
Iocp =
Rcl
(8) Selection of the Pch FET for DCDC1
・VDS＜-Vin
・VGS＜-5V(Typ)
・Allowable Current ＞ Output Current + Ripple Current
※Recommended more than the threshold for over current protection
※The FET with low on resistance will provide high efficiency.

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2. Setting External Components for REG

VIN

Cin

REG VOUT

Co
ADJ R1

R2

Figure 60. External Components for REG

Output Input Voltage Range[V] OCP Current Threshold[A] Output Capacitance[µF]

ch
Voltage[V] Min Typ Max Min Typ Max Min Typ Max
(Note 1)
REG1 1.25 2.25 3.3 6.5 0.5 1.0 1.5 4.7 - -
(Note 1)
REG2 8.8 9.45 14.4 25 0.15 0.30 0.45 1 - -
(Note 1)
REG3 3.3 3.9 6 6.5 0.3 0.6 0.9 4.7 - -
(Note 1)
REG4 5.2 5.6 6 6.5 Typ-20% Variable Typ+20% 47 - -
(Note 1)
REG5 5 5.65 14.4 25 0.05 0.10 0.15 1 - -
(Note 1) the value when Output Voltage is indicated above

Figure 61. Each REG’s Specification of BD49101AEFS-M

(1) Setting Output Voltage

To set output voltage, connect R2 between ADJ and GND, R1 between VOUT and ADJ.
Furthermore, set the R1 to 100kΩ(400kΩ for REG3) or more.
VOUT = VADJ x (R1+R2)/R2 [V]
VADJ:ADJ Voltage(=Reference Voltage) REG3,REG4,REG5: 0.8V(Typ),
REG1: 0.6V(Typ),
REG2: 0.793V(Typ)

(2) Selection of Output Capacitors

To prevent from oscillation, insert output capacitor. Check to Figure 61 about minimum capacitance of each REG.
(Temperature characteristic is excluded) It may be use ceramic capacitors.
Because steep change and input voltage change have effect on output voltage change, please confirm output
capacitance in actual application.

(3) Over Current Protection(OCP) Threshold

The OCP threshold depends on output voltage setting value. Especially if you set lower voltage than indicated shown
as Figure 61, OCP threshold value decrease.

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(4) Setting of REG4 Over Current Protection Threshold and Cable Impedance Calibration
① Setting of Over Current Protection Threshold
The over current protection threshold (IRG4OCP) can be set by the resistance connected with CLCAL (RCLCAL).
The threshold can be obtained by the following formula (Typical Characteristic)

RCLCAL[Ω] = 5.1k x 1.96A / IRG4OCP[A]

The relation between resistance and the threshold is decided as shown in the figure below.

2.0 1.96
OCP Threshold Current : IRG4OCP [A]

1.79 RCLCAL[kΩ] IRG4OCP[A]

5.1 1.96
1.5 1.47
5.6 1.79
6.8 1.47
1.22 8.2 1.22
10.0 1.00
1.0 1.00 12.0 0.83
0.83 15.0 0.67
0.67 18.0 0.56
0.56 22.0 0.45
0.5 0.45
0.37 0.30 27.0 0.37
0.26 0.21
0.18 33.0 0.30
39.0 0.26
0.0 47.0 0.21
0 10 20 30 40 50 60 56.0 0.18
OCP Threshold Current Setting
Resistance : RCLCAL [kΩ]

Figure 62. Setting of Over Current Protection Threshold

② Setting of Cable Impedance Calibration

The cable impedance (RCABLE) calibration value can be set by the resistance connected with the VOCAL pin (RVOCAL).
This value can be obtained by the following formula (Typical Characteristic):

RVOCAL[Ω] = RCABLE[Ω] x 2400 / VOUT4

VOUT4: REG4 Output Setting Value(Typ)

250
RVOCAL[Ω]
RCABLE[Ω]
Output Voltage Compensation Setting

VOUT4 =5.2V VOUT4=5.2V

200 0.000 0
0.022 10
Resistance : RVOCAL [Ω]

0.039 18
150 0.085 39
0.163 75
0.217 100
100 0.238 110
0.260 120
0.282 130
50 0.325 150
0.347 160
0.390 180
0 0.433 200
0 0.1 0.2 0.3 0.4 0.5 0.477 220
Cable Resistance : RCABLE [Ω] 0.520 240

Figure 63. Setting of Cable Impedance Calibration

When you set cable impedance, please assume VOUT4 absolute maximum rating(7.0V) and I/O voltage difference(0.4V max)
so that the cable impedance calibration cause rising output voltage.

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③Setting of the VOCAL Capacitor

VIN4
Vin

Cin

REG4 VOUT4 Vo

Co
VOCAL

CVOCAL RVOCAL

Figure 64. Capacitance of the VOCAL pin (CVOCAL)

For the oscillation of REG4 cable impedance calibration circuit, insert more than 4.7µF capacitor to VOCAL
as shown above.

(5) The VOUT0 Pin Setting

Be sure to connect DCDC2 output with the VOUT0 pin. (refer to Figure 55.)
The VOUT0 pin is a power supply for I/O pin (36-43pin). Therefore, if VOUT0 and VODC2 output would not be
connected, you could not set external synchronization, register and DCDC2/STBREG mode or could not get BSENS or
REG4OCB output signal.

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3. Setting the Oscillator Frequency (FOSC)

An internal oscillator frequency can be set by the resistance connected with the RT pin.
The relation between resistance and the oscillator frequency is decided as shown in the figure below. (Typical Characteristic)

550

RT[kΩ] FOSC[kHz]
Oscillator Frequency:Fosc[kHz]

500
27 537
450 30 489
33 449
400 36 415
39 386
350 43 353
47 324
300 51 300
56 275
250 62 250
68 229
200 75 209
82 192
150 91 174
20 30 40 50 60 70 80 90 100
Oscillator Frequency Setting
Resistance: RT [kΩ]

Figure 65. Oscillator Frequency vs RT

Thermal Reduction Characteristics

10

9
Power Dissipation : Pd [W]

7
6.19W
6

5 ※Reduce by 49.5 mW/°C,when mounted on 4-layer PCB

3
of 70 x 70 x 16 mm
4 2
(Copper foil area on the reverse side of PCB: 70 x 70mm ).
3

0
25 50 75 100 125 150

Ambient Temperature : Ta [℃]

Figure 66. Thermal Reduction Characteristics

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I/O Equivalence Circuit(s)

Pin Pin Pin Pin

Equivalent Circuit Equivalent Circuit
No. Name No. Name

VINSW

14 VOUT1 BCAP VIN 1,2,3,0 Internal Internal Internal

Regulator 10kΩ Regulator Regulator

16 VOUT2 VOUT1,2,3,5
6 HSW HSW
32 VOUT3 700kΩ 20kΩ
600kΩ 20kΩ
91kΩ 115kΩ
1 VOUT5 9kΩ 35kΩ

BCAP Internal Internal

Regulator
BCAP BCAP Regulator
FB1,2
20Ω
23 FB1
8 SW2 1kΩ
SW2 9 FB2
100kΩ

BCAP
Internal
Regulator BCAP
BCAP

12 INV1
11 VOUT0
19 INV2 INV1,2
VOUT0
5kΩ 2500kΩ

800kΩ

13 ADJ1 Internal SNSH SNSH

Regulator SNSH
BCAP 10kΩ 5kΩ
15 ADJ2

31 ADJ3 ADJ1,2,3,4,5 21 SNSL

SNSL
26 ADJ4 2kΩ

44 ADJ5

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Pin Pin Pin Pin

Equivalent Circuit Equivalent Circuit
No. Name No. Name

SNSH SNSH
VIN4

SNSH

VOUT4
22 GATE1 25 VOUT4 350kΩ 10kΩ
GATE1 60.125kΩ
5kΩ
40kΩ
150kΩ

Internal
VIN4 VIN4 Regulator
Internal
Internal Regulator
Regulator
Internal
Regulator
27 VOCAL 28 CLCAL
VOCAL CLCAL
500kΩ 5kΩ

500kΩ

Internal
Regulator
Internal
Regulator BCAP VOUT0

34 RT 36 SYNC 2kΩ
SYNC
RT
50Ω 30kΩ
100kΩ

VOUT0 VOUT0

2kΩ 2kΩ
37 SCL SCL 38 SDA SDA

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Pin Pin Pin Pin

Equivalent Circuit Equivalent Circuit
No. Name No. Name

BCAP VOUT0
BCAP VOUT0
EN
43
BSENS EN,REG4EN,
40
REG4 2kΩ
BSENS, 42 ECO
REG4 EN
39 REG4OCB
OCB 100kΩ
41
ECO
(EN:660kΩ)

Figure 67. I/O Equivalence Circuit(s)

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Operational Notes

1. Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.

2. Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.

3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

4. Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5. Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the board size
and copper area to prevent exceeding the Pd rating.

6. Recommended Operating Conditions

These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.

7. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush
current may flow instantaneously due to the internal powering sequence and delays, especially if the IC
has more than one power supply. Therefore, give special consideration to power coupling capacitance,
power wiring, width of ground wiring, and routing of connections.

8. Operation Under Strong Electromagnetic Field

Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.

9. Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.

10. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.

11. Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.

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Operational Notes – continued

12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Resistor Transistor (NPN)
Pin A Pin B B Pin B
C
Pin A E

P B C
P+ P+ P+ N P P+
N N N N Parasitic N N N
E
Elements
Parasitic
P Substrate P Substrate
Elements
GND GND GND GND
Parasitic Parasitic N Region
Elements Elements close-by
Figure 68. Example of monolithic IC structure

13. Ceramic Capacitor

When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.

14. Area of Safe Operation (ASO)

Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe
Operation (ASO).

15. Thermal Shutdown Circuit(TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins except DCDC2/STBREG
and REG1. When the Tj falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.

16. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.

17. DCDC2 Short Current Protection (SCP)

While OCP operates, if the output voltage falls below 70%, SCP will start up. If SCP operates, the output will be OFF
period of 1024 pulse. It extends the output OFF time to reduce the average output current. In addition, when power
start-up this feature is masked until it reaches the output voltage is set to prevent the startup imperfection.

18. BCAP Over Voltage Protection (BCOVP)

The output except DCDC2/STBREG and REG1 will be turned OFF when BCAP voltage exceeds 30V(Typ).
When the voltage falls under 28V(Typ), those outputs restarts. Please care the range of use voltage.

19. BCAP Voltage Slew Rate Limitation

When the large voltage slew rate would input on the BCAP pin over 1 V/µs, the IC could be reset. Please care with a
bypass capacitor or input LC filter etc. to reduce the slew rate.

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Ordering Information

B D 4 9 1 0 1 A E F S - ME2

Part Number Package M: for Packaging and forming specification

EFS: HTSSOP-A44 Auto- E2: Embossed tape and reel
motive

Physical Dimension, Tape and Reel Information

Marking Diagrams

HTSSOP-A44 (TOP VIEW)

Part Number Marking

D49101AEFS LOT Number

1PIN MARK

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Revision History

Date Revision Changes

06.Apr.2015 001 New Release
23.Jun.2016 002 Correction of descriptions, Add descriptions of function, Change format

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 Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment ,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN USA EU CHINA
CLASSⅢ CLASSⅡb
CLASSⅢ CLASSⅢ
CLASSⅣ CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PAA-E Rev.003
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.

Notice-PAA-E Rev.003
© 2015 ROHM Co., Ltd. All rights reserved.
 Datasheet

General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.

2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.

3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.

Notice – WE Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.