HCM | July 2021

What we do: IC Design

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Table of Content

A Growing IC Design Industry in Vietnam

LSI Overall Introduction

Design Flow

Working Infrastructure Setup

Working Model & Resource Development

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 A Growing IC Design Industry
1 in Vietnam
1. A Growing IC Design Industry in Vietnam(01/2021)

Currently, there are more than 5500 engineers in Vietnam working on semiconductor domain 9
2. IC Design Industry
 LSI Overall Introduction
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2. LSI Overall Introduction

ANALOG LOGIC DESIGN

CIRCUIT &
DESIGN VERIFICATION

SYSTEM DESIGN: SYSTEM

CUSTOM ANALOG DESIGN: LOGIC DESIGN: FPGA DESIGN:
 HLS - High Level Synthesis  Analog/Mixed
DESIGN Signal Design &  Behavioral Modelling  Functional and gate-level
Design Simulation.  Spec to RTL design validation.
 Spec Development  Custom Layout & Verification  RTL Design  Design-for-test services
 IP & Library Development  IO / Standard Library and  Function Verification  Custom FPGA IP cores
 System Validation Custom IP Development (UVM/OVM)  RTL coding: VHDL, Verilog
 Virtual Prototyping  Physical Verification  Simulation & Code Coverage
 System Modeling (DRC/LVS/DFM)  Verification IP Development

LOGIC SYNTHESIS & DFT: PHYSICAL DESIGN: POST-SILICON SERVICE: FIELD APPLICATION ENGINEER:
 Logic Synthesis  Floor Planning  Silicon Validation  Hardware Design
 Timing Analysis  Placement & Routing  FPGA prototyping  PCB Design & Assembly
 DFT (JTAG, SCAN, BIST)  Clock Tree Synthesis  Test/Validation Board  ATE Engineering
 STA – Static Timing Analysis  Physical Verification  Silicon Bring Up  Embedded Engineering
(DRC/LVS)
 Power/Area Optimization

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 RTL Design and Verification Flow
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3. RTL Design and Verification
 RTL Design and Verification
o MCU, CPU, PCIe, DDR, AMBA Bus, USB, UFS
o ARM CPU Customization and ARM-based SoC Verification.
o Static Verification: Static RTL check, CDC verification, Formal Verification.
o Work with AMBA Bus(AXI4, AXI3, AHB, APB) and Peripheral IPs (IIC, WDT,UART, Timer, DMAC,
SD Card…).
‒ HDL Languages:
 C/C++, Verilog, VHDL, System Verilog, UVM, System C, Matlab, scripting languages(Tcl, Cshell,Perl)

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3. RTL Design

Input
Full flow of Design flow: Customer
Specification, Coding and Static requirements

Check Analyze and investigate

requirement

Specification
Tools and Techniques:
System Specification - Document
Processing Tool (MS
Office)
Architecture Design

Coding and Static Check

RTL coding
Tools and Techniques:
- Verilog,
SystemVerilog,
Design rule check VHDL
- Spyglass/Lint

Y
Bug? Bug analyze & report
N

Main
tain
Deliver to customer
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3. RTL Design Flow
 1.ic_design_flow.pptx
3. RTL Verification

Input
Full flow of verification: Planning, Customer Specifications +
requirements RTL design
Verification Executing and
Analyze and investigate
Maintain requirement Tools and Techniques:
- Question and Answer

Planning
Features extraction - Checklist
- Vplaner

Coverage model planning

Test scenarios/Checked item

listing
Environment
investigation/building Tools and Techniques:
- VCS/NcSim
Test scenarios making - VCFormal/JasperGold
- DVE/Verdi/SimVision
- VCS URG/Cadence IMC

Executing
Simulation/Formal and
debugging
Y
Bug? Bug analyze & report
N
Regression and analyze
functional/code coverage

N Coverage
reaches? Y

Main
tain
Deliver to customer Maintain env./test-cases
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 3. EDA Tool
Methodology Language Tool
Verilog/VHDL Cadence: Incisive Enterprise Simulator (ncvlog, ncvhdl,
ncelab, ncsim, irun, simvision), Verification IPs (AMBA,
SystemVerilog PCIe, USB, MIPI, SATA, memory model, I2C, I2S, JTAG,
UART), Stratus, IMC.
Direct Verification
Synopsys: VCS MX, Verdi, Verification IPs (AMBA, PCIe,
USB, MIPI, SATA, memory model, I2C, I2S, JTAG, UART),
SystemC
URG.
Mentor Graphics: ModelSim/QuestaSim.
Cadence: Incisive Enterprise Simulator (ncvlog, ncvhdl,
ncelab, ncsim, irun, simvision), UVM/OVM/Assertion-
Random Verification
SystemVerilog Based Verification IP, IMC.
(UVM/OVM/Assertion-Based)
Synopsys: VCS MX, Verdi, UVM/OVM/Verification, URG.
Mentor Graphics: ModelSim/QuestaSim.
Cadence: JasperGold.
Formal Verification SystemVerilog Synopsys: VC Formal.

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19
ASIC Physical Implementation – Tools
Design Flow Task EDA Tool
Synopsys Design Compiler
Logic synthesis
Cadence RTL Compiler
Synopsys DFT Compiler
Design for test
Synopsys BSD Compiler
Floorplanning Cadence Encounter EDI
Design implementation Cadence Encounter EDI
Physical implementation
Synopsys IC Compiler and IC Compiler II
Cadence QRC
RC extraction
Mentor Graphics xRC
Engineering change order (ECO) Cadence Conformal ECO

Static timing analysis Synopsys PrimeTime

Timing constraint validation Cadence Conformal CCD
Formal verification Synopsys Formality
Design verification Low power verification Cadence Conformal CLP
Cadence NC-Sim
Simulation
Synopsys VCS
Physical verification Mentor Graphics Calibre
RTL code purification Synopsys LEDA
Power noise analysis Cadence EPS
Design Analysis (optional)
Waveform analysis Synopsys Verdi
Crosstalk analysis Synopsys PrimeTime-SI
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ASIC’s flow
ccs.db Design Constraint

• Logic synthesis
Library RTL SDC

• Low Power design

Pre-synthesis with
• Design for Test new constraint
Synthesis DC, DFT, Formality

• Formality NO Pre-layout
PTS
STA
• Floor-planning
YES

• Place & Route Place & Route ICC

• Parasitic Extraction
Back Annotation Extract-RCXT
• Static Timing Analysis
NO
• Signal Integrity Analysis Post-layout
STA PTS/PTSI

• Power Analysis NO
YES

Physical Verification
• Physical verification Calibre

RTL update YES

DRC/LVS/ERC/ANT/DEN NO
Post-Layout
Simulation VCS-MX
• Shell, TCL, Python Languages YES

Tape-out

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4 Field Application Engineer Service
FAE - PCB Design
Designing Verification

 High-Speed rules
 Multi-Layer PCB Design  High-Power Circuit Design and Power
 Design For Test (DFT) and Design for
 High-Speed and High-Density SMT Distribution Design
Manufacturing (DFM)
PCB Design • Matched Length Design
 IPC Standard
 Blind, Buried, and Micro Via • Impedance Control For Single-Ended
 Signal Integrity (SI) verification
 Mixed-Signal Design and Differential pair
 EMI/EMC
 Micro-BGA and Multi-BGA Package • EMI/EMC Compliance
 PCB Thermal Analysis
Types
 In-process cross QC
 RF Design
 Flexible PCB Design

• PCB Fabrication Drawings • Gerber Data

Our • Assembly Detail Drawings • Drill Data
Deliverables • PCB Design Database • Board Test Reports
• Schematic Design Database • Customized Output Files (3D, PDF, …)
FAE - PCB Layout Design Flow

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FAE - PCB Design Tools
• Cadence Allegro
• Altium Designer
• Mentor Graphics Expedition Enterprise
• Valor NPI
• Hyper Lynx
• Zuken – Design Gateway
• Solid work

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FAE - PCB Case study TCU device
• Scope: Schematic capture, PCB layout, PCB verification, PCB Assembly

Concept Design Schematic Capture Board Layout

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Case Study – Product Engineering
1-stop shop for product development; from H/W Engineering (PCB
design & firmware development) to Software Solutions (iOS & Android
Apps, AWS IOT Services)

Mobile App-Demonstration
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Why Study and Learn IC design
• Not a spectator sport -> Learn/ Do/ Issue
• Practice/Experience
Project
No. Descriptions Target
1 CPU Design and simulation RTL, Verilog, VHDL, IC
2 IP design and Simulation RTL, Verilog, VHDL, IC
3 Cache of CPU RTL, Verilog, VHDL, IC
4 BUS system: AXI, AHB RTL, Verilog, VHDL, IC
5 DSP IP: Video, Audio RTL,
6 System on FPGA RTL, FPGA
Exam
 Review with slide:
1.IC Design Overview
2.What is SoC System? (System on Chip)
3.What is IP?(Intelligent Property)
4.FPGA vs ASIC design
5.A.I in IC Design ( FPGA)
THANK YOU

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CS #9: FPGA-based ADAS Hardware Implementation

Key Features Hardware Resource

 Resolutions HD  Zynq 7000- Z7010 Xilinx
1280x1080  20% LUT
 Frames 60 fps  5% DSP
 Real time Yes  6% Flip-flops
 HDMI Yes  0% DDR3(External ram)
Hardware Demonstration
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 CS #10: FPGA interfacing board for special automotive
H01

Scope
H03
Design the FPGA-based system with features of: Temperature I/O Extend
Sensor FMC card

A. High-end FPGA chipset with enough Giga –TRx IOs to support:

1. 12xEthernet ports with RJ45/SFP+ interface 13 CAN

• MAC Ethernet IP core GPRMC

Rx CAN PHY CAN H

• PHY CHIP (external for RJ45 if required)

GPS PPS
Tx (CAN R bus
DSP CAN L
transceiver)
H08
• Software/driver
D/A
XO
Control

10Mhz
GPS_ OCXO 13 Ethernet

2. 12xGMSL ports OCXO

IMU
SPI/I2C
125Mhz

• Verilog code for interface

Clock
156.25Mhz Oscillator

GTx Tx

• PHY IC communication connect GMSL interface

SFP+ Rx

• Driver control the interface 2.5Gbps

Quad GMSL
Deserializer
MIPI CSI-4
4 lanes

Rx FlexRay PHY H
Tx
3. 8 lanes PCIe gen 3 FPGA Tx_en
(FlexRay
transceiver)
L
R bus

• IP core 2.5Gbps
Quad GMSL
Deserializer
MIPI CSI-4
4 lanes GTx
SATA1

• Verilog for Bridge controller

GTx
GTx
SATA2
SATA3 H02
GTx SATA4

• Software/Driver 2.5Gbps
Quad GMSL
Deserializer
MIPI CSI-4
4 lanes
UART1_Rx

4. 4xSATA ports UART1_Tx

• IP core GTx
USB1 3.0

• Verilog for Bridge controller Oscillator

SMA connector GTx USB2 3.0
GTx
USB3 3.0
GTx

• Software/Driver
USB4 3.0

SW& button GTx

PCIe3x8
H09
B. External PHY of: 12xCAN, 2xFlexray, 4xUART and 4xUSB LED
PCIe 3.0 x8

• IPs core Fan controller Power manager

• PHY chip for USB3.0 (if required) H04 & H05

• Software/Driver

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