L4981A

 L4981B

POWER FACTOR CORRECTOR

CONTROL BOOST PWM UP TO 0.99P.F.

LIMIT LINE CURRENT DISTORTION TO < 5%
MULTIPOWER BCD TECHNOLOGY
UNIVERSAL INPUT MAINS
FEED FORWARD LINE AND LOAD REGULA-
TION
AVERAGE CURRENT MODE PWM FOR
MINIMUM NOISE SENSITIVITY
HIGH CURRENT BIPOLAR AND DMOS TO-
TEM POLE OUTPUT
LOW START-UP CURRENT (0.3mA TYP.) DIP20 SO20
UNDER VOLTAGE LOCKOUT WITH HYS-
TERESIS AND PROGRAMMABLE TURN ON
THRESHOLD ORDERING NUMBERS: L4981X (DIP20)
OVERVOLTAGE, OVERCURRENT PROTEC- L4981XD (SO20)
TION
PRECISE 2% ON CHIP REFERENCE EX-
TERNALLY AVAILABLE
SOFT START trol functions for designing a high efficiency-mode
power supply with sinusoidal line current con-
sumption.
DESCRIPTION The L4981 can be easily used in systems with
The L4981 I.C. provides the necessary features mains voltages between 85V to 265V without any
to achieve a very high power factor up to 0.99. line switch. This new PFC offers the possibility to
Realized in BCD 60II technology this power factor work at fixed frequency (L4981A) or modulated
corrector (PFC) pre-regulator contains all the con- frequency (L4981B) optimizing the size of the in-

BLOCK DIAGRAM

September 1998 1/17

L4981A - L4981B

put filter; both the operating frequency modes soft start are included. To limit the number of the
working with an average current mode PWM con- external components, the device integrates pro-
troller, maintaining sinusoidal line current without tections as overvoltage and overcurrent. The
slope compensation. overcurrent level can be programmed using a
Besides power MOSFET gate driver, precise volt- simple resistor for L4981A. For a better precision
age reference (externally available), error ampli- and for L4981B an external divider must be used.
fier, undervoltage lockout, current sense and the

ABSOLUTE MAXIMUM RATINGS

Symbol Pin Parameter Value Unit
VCC 19 Supply Voltage (ICC ≤50mA) (*) selflimit V
IGDRV 20 Gate driv. output peak current (t = 1µs) SINK 2 Α
. SOURCE 1.5 A
VGDRV Gate driv. output voltage t = 0.1µs -1 V
Voltages at pins 3, 14, 7, 6, 12, 15 -0.3 to 9 V
VVA-OUT 13 Error Amplifier Voltage -0.3 to 8.5 V
IAC 4 AC Input Current 5 mA
Voltages at pin 8, 9 -0.5 to 7 V
VCA-OUT 5 Current Amplifier Volt. (Isource = -20mA; Isink = 20mA) -0.3 to 8.5 V
VROSC 17 Voltage at pin 17 -0.3 to 3 V
11, 18 Voltage at pin 11, 18 -0.3 to 7 V
ICOSC 18 Input Sink Current 15 mA
IFREQ-MOD 16 Frequency Modulation Sink Current (L4981B) 5 mA
V SYNC 16 Sync. Voltage (L4981A) -0.3 to 7 V
V IPK 2 Voltage at pin 2 -0.3 to 5.5 V
Voltage at Pin 2 t = 1µs -2 V
Ptot Power Dissipation at Tamb = 70°C (DIP20) 1 W
Power Dissipation at Tamb = 70°C (SO20) 0.6 W
Top Operating Ambient Temperature -40 to 125 °C
Tstg StorageTemperature -55 to 150 °C
(*) Maximum package power dissipation limits must be observed.

PIN CONNECTIONS (Top views)

L4981A L4981B

2/17
 L4981A - L4981B

THERMAL DATA
Symbol Parameter DIP 20 SO 20 Unit
Rth j-amb Thermal Resistance Junction-ambient 80 120 °C/W
PIN FUNCTIONS
N. Name Description
1 P-GND Power ground.
2 IPK L4981A peak current limiting. A current limitation is obtained using a single resistor connected
between Pin 2 and the sense resistor. To have a better precision another resistor between Pin
2 and a reference voltage (Pin 11) must be added.

L4981B peak current limiting. A precise current limitation is obtained using two external
resistor only. These resistors must be connected between the sense resistor, Pin 2 and the
reference voltage.
3 OVP Overvoltage protection. At this input are compared an internal precise 5.1V (typ) voltage
reference with a sample of the boost output voltage obtained via a resistive voltage divider in
order to limit the maximum output peak voltage.
4 IAC Input for the AC current. An input current proportional to the rectified mains voltage generates,
via a multiplier, the current reference for the current amplifier.
5 CA-OUT Current amplifier output. An external RC network determinates the loop gain.
6 LFF Load feedforward; this voltage input pin allows to modify the multiplier output current
proportionally to the load, in order to give a faster response versus load transient. The best
control is obtained working between 1.5V and 5.3V. If this function is not used, connect this pin
to the voltage reference (pin = 11).
7 VRMS Input for proportional RMS line voltage. the VRMS input compesates the line voltage changes.
Connecting a low pass filter between the rectified line and the pin 7, a DC voltage proportional
to the input line RMS voltage is obtained. The best control is reached using input voltage
between 1.5V and 5.5V. If this function is not used connect this pin to the voltage reference
(pin = 11).
8 MULT-OUT Multiplier output. This pin common to the multiplier output and the current amplifier N.I. input is
an high impedence input like ISENSE. The MULT-OUT pin must be taken not below -0.5V.
9 ISENSE Current amplifier inverting input. Care must be taken to avoid this pin goes down -0.5V.
10 S-GND Signal ground.
11 VREF Output reference voltage (typ = 5.1V).Voltage refence at ± 2% of accuracy externally available,
it’s internally current limited and can deliver an output current up to 10mA.
12 SS A capacitor connected to ground defines the soft start time. An internal current generator
delivering 100µA (typ) charges the external capacitor defining the soft start time constant. An
internal MOS discharge, the external soft start capacitor both in overvoltage and UVLO
conditions.
13 VA-OUT Error amplifier output, an RC network fixes the voltage loop gain characteristics.
14 VFEED Voltage error amplifier inverting input. This feedback input is connected via a voltage divider to
the boost output voltage.
15 P-UVLO Programmable under voltage lock out threshold input. A voltage divider between supply
voltage and GND can be connected in order to program the turn on threshold.
16 SYNC This synchronization input/output pin is CMOS logic compatible. Operating as SYNC in, a
(L4981A) rectangular wave must be applied at this pin. Opearting as SYNC out, a rectangular clock
pulse train is available to synchronize other devices.
FREQ-MOD Frequency modulation current input. An external resistor must be connected between pin 16
(L4981B) and the rectified line voltage in order to modulate the oscillator frequency. Connecting pin 16 to
ground a fixed frequency imposed by ROSC and COSC is obtained.
17 R OSC An external resistor connected to ground fixes the constant charging current of COSC.
18 C OSC An external capacitor connected to GND fixes the switching frequency.
19 VCC Supply input voltage.
20 GDRV Output gate driver. Bipolar and DMOS transistors totem pole output stage can deliver peak
current in excess 1A useful to drive MOSFET or IGBT power stages.

3/17
L4981A - L4981B

ELECTRICAL CHARACTERISTICS (Unless otherwise specified VCC = 18V, COSC = 1nF,

ROSC = 24KΩ, CSS = 1µF, VCA-OUT = 3.5V, VISENSE = 0V, VLFF = VREF, IAC = 100µA, VRMS = 1V,
VFEED = GND, VIPK = 1V, V OVP = 1V, TJ = 25°C
Symbol Prameter Test Condition Min. Typ. Max. Unit
ERROR AMPLIFIER SECTION
VIO Input Offset Voltage –25°C < TJ < 85°C ±8 mV
IIB Input Bias Current VFEED = 0V -500 -50 500 nA
Open Loop Gain 70 100 dB
V13H Output High voltage VFEED = 4.7V 5.5 6.5 7.5 V
IVA-OUT = -0.5mA
V13L Output Low Voltage VFEED = 5.5V 0.4 1 V
IVA-OUT = 0.5mA
-I13 Output Source Current VFEED = 4.7V; VVA-OUT = 3.5V 2 10 mA
I13 Output Sink Current VFEED = 5.5V; VVA-OUT = 3.5V 4 20 mA
REFERENCE SECTION
Vref Reference Output Voltage –25°C < TJ < 85°C 4.97 5.1 5.23 V
Tj = 25°C Iref = 0 5.01 5.1 5.19 V
∆Vref Load Regulation 1mA ≤ Iref ≤ 10mA 3 15 mV
–25°C < TJ < 85°C
∆Vref Line Regulation 12V ≤ VCC ≤ 19V 3 10 mV
–25°C < TJ < 85°C
Iref sc Short Circuit Current Vref = 0V 20 30 50 mA
OSCILLATOR SECTION
fosc Initial Accuracy Tj = 25°C 85 100 115 KHz
Frequency Stability 12V ≤ VCC ≤ 19V 80 100 120 KHz
–25°C < TJ < 85°C
Vsvp Ramp Valley to Peak 4.7 5 5.3 V
I18C Charge Current VCOSC = 3.5V 0.45 0.55 0.65 mA
I18D Discharge Current VCOSC = 3.5V 11.5 mA
V 18 Ramp Valley Voltage 0.9 1.15 1.4 V
SYNC SECTION (Only for L4981A)
tW Output Pulse Width 50% Amplitude 0.3 0.8 µs
I16 Sink Current with Low Output VSYNC = 0.4V 0.4 0.8 mA
Voltage VCOSC = 0V
-I16 Source Current with High Output VSYNC = 4.5V 1 6 mA
Voltage VCOSC = 6.7V
V16L Low Input Voltage 0.9 V
V16H High Input Voltage 3.5 V
td Pulse for Synchronization 800 ns
FREQUENCY MODULATION FUNCTION (Only for L4981B)
f18max Maximum Oscillation Frequency VFREQ-MOD = 0V (Pin 16) Ifreq = 0 85 100 115 KHz
f18min Minimum Oscillator Frequency IFREQ-MOD = 360µA (Pin 16) 74 KHz
VVRMS = 4V (Pin 7)
IFREQ-MOD = 180µA (Pin 16) 76 KHz
VVRMS = 2V (Pin 7)
SOFT START SECTION
ISS Soft Start Source Current VSS = 3V 60 100 140 µA
V12sat Output Saturation Voltage V3 = 6V, ISS = 2mA 0.1 0.25 V

4/17
 L4981A - L4981B

ELECTRICAL CHARACTERISTICS (continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY VOLTAGE
VCC Operating Supply Voltage 19.5 V
OVER VOLTAGE PROTECTION COMPARATOR
Vthr Rising Threshold Voltage Vref 5.1 Vref V
-20mV +20mV
V3Hys Hysteresis 180 250 320 mV
I3 Input Bias Current 0.05 1 µA
td Propagation delay to output VOVP = Vthr +100mV 1 2 µs
OVER CURRENT PROTECTION COMPARATOR
V th Threshold Voltage ±30 mV
td Propagation delay to Output VOCP = Vthr -0.2V 0.4 0.9 µs
Iipk Current Source Generator VIPK = -0.1V only for L4981A 65 85 105 µA
IL Leakage Current VIPK = -0.1V only for L4981B 5 µA
CURRENT AMPLIFIER SECTION
Voffset Input Offset Voltage VMULT OUT = VSENSE = 3.5V ±2 mV
I9bias Input Bias Current VSENSE = 0V -500 50 500 nA
Open Loop Gain 1.1V ≤ VCA OUT ≤ 6V 70 100 dB
SVR Supply Voltage Rejection 12V ≤ VCC ≤ 19V 68 90 dB
VMULT OUT = 3.5V VSENSE = 3.5V
V5H Output High Voltage VMULT OUT = 200mV 6.2 V
ICA OUT = -0.5mA, VIAC = 0V
V 5L Output Low Voltage VMULT OUT = -200mV 0.9 V
ICA OUT = 0.5mA, VIAC = 0V
-I5 Output Source Current VMULT OUT = 200mV, 2 10 mA
I5 Output Sink Current VIAC = 0V, VCA-OUT = 3.5V 2 10 mA
OUTPUT SECTION
V20L Output Voltage Low ISINK = 250mA 0.5 0.8 V
V20H Output Voltage High ISOURCE = 250mA 11.5 12.5 V
VCC = 15V
tr Output Voltage Rise Time COUT = 1nF 50 150 ns
tf Output Voltage Fall Time COUT = 1nF 30 100 ns
VGDRV Voltage Clamp ISOURCE = 0mA 13 16 19 V
TOTAL STANDBY CURRENT SECTION
I19start Supply Current before start up VCC = 14V 0.3 0.5 mA
I19on Supply Current after turn on VIAC = 0V, VCOSC = 0, 8 12 mA
Pin17 = Open
I19 Operating Supply Current Pin20 = 1nF 12 16 mA
VCC Zener Voltage (*) 20 25 30 V
UNDER VOLTAGE LOCKOUT SECTION
Vth ON Turn on Threshold 14.5 15.5 16.5 V
Vth OFF Turn off Threshold 9 10 11 V
Programmable Turn-on Threshold Pin 15 to VCC = 220K 10.6 12 13.4 V
Pin15 to GND = 33K
LOAD FEED FORWARD
ILFF Bias Current V6 = 1.6V 70 140 µA
V6 = 5.3V 200 300 µA
VI Input Voltage Range 1.6 5.3 V
(*) Maximum package power dissipation limits must be observed.

5/17
L4981A - L4981B

ELECTRICAL CHARACTERISTICS (continued)

Symbol Prameter Test Condition Min. Typ. Max. Unit
MULTIPLIER SECTION
Multipler Output Current VVA-OUT = 4V, VRMS = 2V, 20 35 52 µA
VMULTOUT = 0, VLFF = 5.1V
IAC = 50µA, COSC = 0V
VVA-OUT = 4V, VRMS = 2V, 100 135 170 µA
VMULTOUT = 0, VLFF = 5.1V
IAC = 200µA, COSC = 0V
VVA-OUT = 2V, VRMS = 2V, 10 20 30 µA
VMULTOUT = 0, VLFF = 5.1V
IAC = 100µA, COSC = 0V
VVA-OUT = 2V, VRMS = 4V, 2 5.5 11 µA
VMULTOUT = 0, VLFF = 5.1V
IAC = 100µA, COSC = 0V
VVA-OUT = 4V, VRMS = 4V, 10 22 34 µA
VMULTOUT = 0, VLFF = 5.1V
IAC = 100µA, COSC = 0V
VVA-OUT = 4V, VRMS = 2V, 20 37 54 µA
VMULTOUT = 0, VLFF = 2.5V
COSC = 0V, IAC = 200µA
VVA-OUT = 4V, VRMS = 4V 20 39 54 µA
VMULTOUT = 0, VLFF = 5.1V
IAC = 200µA, COSC = 0V
VVA-OUT = 2V, VRMS = 4V, -2 0 2 µA
VMULTOUT = 0, VLFF = 5.1V
IAC = 0, COSC = 0V
K Multiplier Gain 0.37

(VVA−OUT − 1.28) ⋅ (0.8 ⋅ VLFF − 1.28)

IMULT−OUT = K ⋅ IAC
(VVRMS)2

(VVA−OUT − 1.28)
if VLFF = VREF; IMULT−OUT = IAC
2
⋅ K1
(VVRMS)

where: K1 = 1V

Figure 1: MULTI-OUT vs. IAC (VRMS = 1.7V; Figure 2: MULTI-OUT vs. IAC (VRMS = 2.2V;
VLFFD = 5.1V) VLFFD = 5.1V)

6/17
 L4981A - L4981B

Figure 3: MULTI-OUT vs. IAC (VRMS = 4.4V; Figure 4: MULTI-OUT vs. IAC (VRMS = 5.3V;
VLFFD = 5.1V) VLFFD = 5.1V)

Figure 5: MULTI-OUT vs. IAC (VRMS = 1.7V; Figure 6: MULTI-OUT vs. IAC (VRMS = 2.2V;
VLFFD = 2.5V) VLFFD = 2.5V)

Figure 7: MULTI-OUT vs. IAC (VRMS = 4.4V; Figure 8: MULTI-OUT vs. IAC (VRMS = 5.3V;
VLFFD = 2.5V) VLFFD = 2.5V)

7/17
L4981A - L4981B

Figure 9A: L4981A Power Factor Corrector (200W)

T
+
R6 D1 Vo=400V
C7
C12
D4
R14 R15 R1 R9
R7
C8 D3 C5 C9

FUSE
BRIDGE R8 R12
Vi
7 4 1 19 13 14
85VAC-265VAC 3 C2
C11
D2
15
C1 L4981A R13
16 20 MOS

6
2 8 5 9 18 10 17 12 11

D5 R17 R2 R10
R21

R5 C3

R11 R3 R4 C4 R16 C6 C10

RS
-
D93IN029B

PART LIST

RS 0.07(3 x .22) 1/2W 5% C1 470nF 400V

R1 820kΩ 1/4W 1% C2 100µF 450V
R2 10kΩ 1/4W 1% C3 2.2nF
R3 1.8kΩ 1/4W 5% C4 1nF
R4 1.8kΩ 1/4W 5% C5 100µF 25V
R5 18kΩ 1/4W 5% C6 1µF 16V
R6 1.2MΩ 1/4W 5% C7 220nF 63V
R7 360kΩ 1/4W 5% C8 220nF 63V
R8 33kΩ 1/4W 5% C9 330nF
R9 1.8MΩ 1/4W 1% C10 1µF 16V
R10 21kΩ 1/4W 1% C11 270pF 400V
R11 402Ω 1/4W 1% C12 8.2nF 100V
R12 120kΩ 1/4W 5% D1 STTA506D
R13 27Ω 1/4W 5% D2, D3 1N4148
R14 1MΩ 1/4W 1% D4 18V 1/2W
R15 120kΩ 1/2W 5% D5 BYT11-600
R16 30kΩ 1/4W 5% MOS STH/STW15NA50
R17 1.8kΩ 4W 1% FUSE = 4A/250V
R21 5.1kΩ 1/4W 1%
BRIDGE = 4 x P600M

T= primary: 88 turns of 12 x 32 AWG (0.2mm) fSW = 80kHz PO = 200W

secondary: 9 turns of # 27AWG (0.15mm) VOUT = 400V Irms max = 2.53A
core: B1ET3411A THOMSON - CSF VOVP = 442V IPK max = 6.2A
gap: 1,6mm for a total primary inductance of
0.9mH

8/17
 L4981A - L4981B

Figure 9B: L4981B Power Factor Corrector (200W)

T
+
R22 R6 D1 Vo=400V
C7
C12
D4
R14 R15 R1 R9
R7
C8 D3 C5 C9

FUSE
BRIDGE R8 R12
Vi
7 4 1 19 13 14
85VAC-265VAC 3 C2
C11
D2
15
C1 L4981B R13
16 20 MOS

6
2 8 5 9 18 10 17 12 11

D5 R17 R2 R10
R21

R5 C3

R11 R3 R4 C4 R16 C6 C10

RS
-
D95IN220

PART LIST

RS 0.07(3 x .22) 1/2W 5% C1 470nF 400V

R1 820kΩ 1/4W 1% C2 100µF 450V
R2 10kΩ 1/4W 1% C3 2.2nF
R3 1.8kΩ 1/4W 5% C4 1.1nF
R4 1.8kΩ 1/4W 5% C5 100µF 25V
R5 18kΩ 1/4W 5% C6 1µF 16V
R6 1.2MΩ 1/4W 5% C7 220nF 63V
R7 360kΩ 1/4W 5% C8 220nF 63V
R8 33kΩ 1/4W 5% C9 330nF
R9 1.8MΩ 1/4W 1% C10 1µF 16V
R10 21kΩ 1/4W 1% C11 270pF 400V
R11 402Ω 1/4W 1% C12 8.2nF 100V
R12 120kΩ 1/4W 5% D1 STTA506D
R13 27Ω 1/4W 5% D2, D3 1N4148
R14 1MΩ 1/4W 1% D4 18V 1/2W
R15 120kΩ 1/2W 5% D5 BYT11-600
R16 24kΩ 1/4W 5% MOS STH/STW15NA50
R17 1.8kΩ 4W 1%
FUSE = 4A/250V
R21 5.1kΩ 1/4W 1%
R22 1.1MΩ 1/4W 1%
BRIDGE = 4 x P600M

T= primary: 88 turns of 12 x 32 AWG (0.2mm) fSW = 80 to 92kHz PO = 200W

secondary: 9 turns of # 27AWG (0.15mm) VOUT = 400V Irms max = 2.53A
core: B1ET3411A THOMSON - CSF VOVP = 442V IPK max = 6.2A
gap: 1,6mm for a total primary inductance of
0.9mH

9/17
L4981A - L4981B

Figure 10: Reference Voltage vs. Source Refer- Figure 11: Reference Voltage vs. Supply Voltage
ence Current

Figure 12: Reference Voltage vs. Junction Tem- Figure 13: Switching Frequency vs. Junction
perature Temperature

Figure 14: Gate Driver Rise and Fall Time Figure 15: Operating Supply Current vs. Supply
Voltage

10/17
 L4981A - L4981B

Figure 16: Programmable Under Voltage Lock- Figure 17: Modulation Frequency Normalized in
out Thresholds an Half Cycle of the Mains Voltage

Vl fsw
1 1

0.8 0.8

R22 = R23 ⋅ 6.8

0.4 0.4

0.2 0.2

0 0
0 45 90 135 180
R23 (Kohm) Electrical degrees

Table 1: Programmable Under Voltage Lockout Thresholds.

VCC ON VCC OFF R22 R23
11V 10V 82kΩ 12kΩ
12V 10.1V 220kΩ 33kΩ
13V 10.5V 430kΩ 62kΩ
14V 10.8V 909kΩ 133kΩ
14.5V 10.9V 1.36MΩ 200kΩ
15V 11V 2.7MΩ 390kΩ

Figure 18: Oscillator Diagram

11/17
L4981A - L4981B

Figure 19: 200W Evaluation Board Circuit.

T= primary: 75 turns of litz wire 20 x 32 AWG (0.2mm)

secondary: 8 turns of # 27AWG (0.15mm)
core: B1ET3411A THOMSON - CSF
gap: 1.4mm for a total primary inductance of 0.7mH
fsw = 100kHz; VO = 400V; PO = 200W

NOTE: voltage available at pin 6 by R20 and Q3, ensures Q2 to be turned

Start Up Circuit off.
Usually the VCC capacitor (C11 in fig. 19) can be charged by a resistor
drawing current from the rectified mains. In the evaluation board Programmable Under voltage Lockout
instead the start up circuit composed by (Q2+R19+R15+Dz) has The PCB allows to insert a couple of resistor (R22, R23) to modify
been designed to perform a fast and effective supply in all the the threshold input voltage. Please refer to fig. 16 and table1.
conditions. Once that the L4981A/B has started, the reference

12/17
 L4981A - L4981B

Figure 20: P.C. Board and Component Layout of Evaluation Board Circuit (1:1 scale).

13/17
L4981A - L4981B

The evaluation board has been designed using: a a NTC resistor can be used.
faster not dissipative start-up circuit, a diode (D2) The PFC demoboard performances has been
to speed-up the MOS start-off time and (even if a evaluated testing the following parameters:
single resistor can be used) an external divider to PF (power factor), A-THD (percentage of current
improve the precision of the overcurrent thresh- total harmonic distortion), H3..H9 (percentage of
old. current’s nth harmonic amplitude), ∆Vo (output
Further there is a possibility to change the input voltage ripple), Vo (output voltage), η (efficiency).
threshold voltage using an external divider (R23 The test configuration, equipments and results
and R22) and if an inrush current problem arises are:

AC POWER PM1200 EMI PFC

SOURCE AC POWER FILTER L4981 LOAD
LARCET /3KW ANALYSER DEMO

D94IN057

Vi f Pi PF A-THD H3 H5 H7 H9 VO ∆VO PO η
(Vrms) (Hz) (W) (%) (%) (%) (%) (%) (V) (V) (W) (%)
88 60 222 0.999 2.94 1.98 0.61 0.55 0.70 390 8 200 90.2
110 60 220 0.999 1.79 1.40 0.40 0.31 0.28 392 8 201 91.6
132 60 218 0.999 1.71 1.16 0.40 0.35 0.31 394 8 202 92.8
180 50 217 0.999 1.88 1.52 0.65 0.40 0.34 396 8 203 93.8
220 50 217 0.997 2.25 1.68 0.83 0.57 0.48 398 8 204 94.2
260 50 216 0.995 3.30 1.84 1.30 0.39 0.73 400 8 205 95.2

EMI/RFI FILTER the AC source and the demoboard under test,

The harmonic content measurement has been while the efficiency has been calculated without
done using an EMI/RFI filter interposed between the filter contribution.

T1 T2
LINE C1 PFC

C
EARTH
D94IN052

where:
T1 = 1mH C1 = 0.33µF, 630V
T2 = 27mH C2 = 2.2nF, 630V

14/17
 L4981A - L4981B

SO20 PACKAGE MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 2.35 2.65 0.093 0.104

A1 0.1 0.3 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 12.6 13 0.496 0.512

E 7.4 7.6 0.291 0.299

e 1.27 0.050

H 10 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.4 1.27 0.016 0.050

K 0 (min.)8 (max.)

L
h x 45°

B e K A1 C
H

20 11

1 10

SO20MEC

15/17
L4981A - L4981B

DIP20 PACKAGE MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.254 0.010

B 1.39 1.65 0.055 0.065

b 0.45 0.018

b1 0.25 0.010

D 25.4 1.000

E 8.5 0.335

e 2.54 0.100

e3 22.86 0.900

F 7.1 0.280

I 3.93 0.155

L 3.3 0.130

Z 1.34 0.053

16/17
 L4981A - L4981B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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