196 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 44, NO.

1, JANUARY/FEBRUARY 2008

An Active-Clamp Push–Pull Converter for Battery

Sourcing Applications
Tsai-Fu Wu, Senior Member, IEEE, Jin-Chyuan Hung, Member, IEEE, Jeng-Tsuen Tsai, Cheng-Tao Tsai,
and Yaow-Ming Chen, Senior Member, IEEE

Abstract—This paper presents an active-clamp push–pull con-

verter for battery sourcing applications. A pair of auxiliary
switches, resonant inductors, and clamping capacitors is added to
the primary side of the transformer to clamp voltage spike and re-
cycle the energy trapped in the leakage inductors. In the proposed
active-clamp push–pull converter, since both main and auxiliary
switches can be turned ON with zero-voltage switching, switch-
ing loss can be reduced and conversion efficiency therefore can be
improved significantly. Furthermore, the proposed converter can
eliminate potential flux-imbalance problems existing in the con-
ventional push–pull converter. In this paper, a 1 kW active-clamp
push–pull converter was implemented, from which experimental
results have shown that efficiency improvement and surge sup-
pression can be achieved effectively. It is relatively feasible for
applications to battery sourcing converters.
Index Terms—Active clamp, push–pull converter, zero-voltage
switching (ZVS).
Fig. 1. Schematic diagram of the proposed push–pull converter with active-
clamp circuits.
I. INTRODUCTION
ATTERY souring applications include mostly a lot of unin-
B terruptible power supplies (UPSs), which have been used
broadly to supply clean and uninterrupted power to loads. In
have been presented in [2]–[4], which can achieve zero-voltage
switching (ZVS) to increase conversion efficiency, while their
UPS applications, they need dischargers to draw power from component stress and circulation energy are still high. In addi-
batteries. In practice, the voltage level of batteries is usually tion, the converters are regulated by variable frequency control,
much lower than that of dc-link bus; thus, a converter with a and it is difficult to design optimal filters, which would increase
high step-up voltage ratio is required for the dischargers. Fur- cost and control complexity. To release these problems, the ZVS
thermore, to effectively utilize the energy stored in batteries, the push–pull converters were proposed in [5], [6]. These converters
dischargers should be designed with high efficiency. with two synchronous switches in the secondary circuits pro-
To achieve a high step-up voltage ratio, a common solution is vide the ZVS opportunity for all of the active switches. Although
using a push–pull converter [1]. However, leakage inductor of these converters present the advantages of a pulse-width modu-
the transformer would induce voltage spike that results in high lation (PWM) control and high efficiency, their active switches
component stress, low conversion efficiency, and high noise are located both on the primary and the secondary sides of
level. The other drawback of a push–pull converter is the flux- the transformer, increasing their driving complexity and cost.
imbalance problem [1]. To alleviate these drawbacks, several In [7], two active-clamp circuits are added to the primary side
kinds of soft-switching push–pull converters have been pro- of the transformer for recycling leakage energy and limiting the
posed in literature [2]–[7]. The resonant push–pull converters voltage spike. In the converter, the clamping circuits can also
achieve the ZVS, which makes the converter more viable. How-
Paper IPCSD-07-059, presented at the 2005 IEEE Applied Power Electron- ever, since its active-clamp circuits are a boost type, voltage
ics Conference and Exposition, Austin, TX, March 6–10, and approved for
publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the stresses imposed on the active switches are much higher than
Industrial Power Converter Committee of the IEEE Industry Applications Soci- twice the input voltage. Thus, the component stress has not been
ety. Manuscript submitted for review April 3, 2005 and released for publication minimized yet. In this paper, a buck-boost type of active-clamp
July 11, 2007.
T.-F. Wu, C.-T. Tsai, and Y.-M. Chen are with the Elegant Power Ap- circuits is proposed, and voltage stresses of the active switches
plication Research Center (EPARC), Department of Electrical Engineering, can be limited to twice the input voltage, reducing the compo-
National Chung Cheng University, Chia-Yi 621, Taiwan, R.O.C. (e-mail: nent stress significantly. The proposed converter is depicted in
[email protected]; [email protected]; [email protected]).
J.-C. Hung and J.-T. Tsai are with NuLight Technology Corporation, Fig. 1.
Tainan 741, Taiwan, R.O.C. (e-mail: [email protected]; smilearmy2001@ In the paper, operational principle of the proposed converter
yahoo.com.tw). is described in Section II. Section III presents the steady-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. state analysis of the converter, from which design procedure is
Digital Object Identifier 10.1109/TIA.2007.912748 summarized. Experimental results obtained from a prototype
0093-9994/$25.00 © 2008 IEEE

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WU et al.: AN ACTIVE-CLAMP PUSH–PULL CONVERTER FOR BATTERY SOURCING APPLICATIONS 197

cle the trapped energy back to the source during the clamping
period.
To simplify description of the operational modes, the follow-
ing assumptions are made.
1) Capacitance of Cclam p1 , Cclam p2 , or CO is large enough
so that the voltages across them can hold constant over a
switching period.
2) Capacitance of Cclam p1 and that of Cclam p2 are identical,
and inductance of LL K 1 and that of LL K 2 are identical.
3) All of the switching devices, MOSFETs and diodes, are
ideal.
Based on the aforementioned assumptions, operation of the
proposed converter over a half switching period can be di-
vided into five modes. Fig. 3 shows the topological modes
of the proposed converter over half the switching cycle, and
Fig. 2 shows its key conceptual voltage and current waveforms.
The operation of the converter is explained mode by mode as
follows.
Mode 1 [Fig. 3(a), T0 ≤ t < T1 ]: At T0 , auxiliary switch Q3 is
turned OFF while Q4 is still conducting. In this mode, leakage
inductor LK 1 resonates with Cr 1 and Cr 3 . Capacitor Cr 3 is
Fig. 2. Driving signals and current and voltage waveforms of the key compo- continuously charged toward VClam p1 + VI , while capacitor
nents in the proposed converter. Cr 1 is discharged down to zero. To achieve an ZVS feature
for switch Q1 , the energy trapped in leakage inductor LK 1
should satisfy the following inequality:
built with the proposed converter are presented in Section IV to
0.5 × [iL K 1 (T0 )]2 LL K 1 ≥ 0.5 × [vD S 1 (T0 )]2 (Cr 1 //Cr 3 ).
verify its feasibility. Finally, the paper is concluded in Section V.
(1)
During this mode, inductor LK 2 keeps to release its stored en-
ergy through D4 to the capacitor Cclam p2 . On the secondary side
II. OPERATION OF THE PROPOSED PUSH–PULL CONVERTER
of the transformer, rectifier diodes D5 –D8 begin to freewheel.
As shown in Fig. 1, the proposed converter consists of the
following components: two main switches Q1 and Q2 , a center- Mode 2 [Fig. 3(b), T1 ≤ t < T2 ]: Mode 2 starts with voltage
tapped transformer T1 , four output rectifier diodes D5 –D8 , two vD S 1 dropping to zero at T1 . Inductor current iL K 1 forces the
output filter inductors LO 1 and LO 2 , two sets of clamping cir- body diode D1 conducting and creating an ZVS condition for
cuits, and two output filter capacitors CO 1 and CO 2 . The clamp- Q1 . The driving signal should be applied to Q1 at this time
ing circuits are composed of two auxiliary switches Q3 and Q4 , interval to achieve an ZVS feature. Inductor current iL K 1 (t)
leakage inductors LK 1 and LK 2 of the transformer, two clamp- increases linearly, which can be expressed as follows:
ing capacitors Cclam p1 and Cclam p2 and snubbers Cr 1 –Cr 4 that VI
can limit the rising rate of voltage, reducing turn-OFF loss signif- iL K 1 (t) = iL K 1 (T1 ) + t. (2)
LK 1
icantly. Switches Q1 and Q3 , as well as Q2 and Q4 , are driven
When inductor current iL K 1 (t) goes beyond the zero level,
in an asymmetrical complementary manner with a dead time to
Q1 can be turned ON with the ZVS.
achieve ZVS.
Meanwhile, leakage inductor LK 2 releases its trapped en-
The driving signals and current and voltage waveforms of
ergy continuously to clamping capacitor Cclam p2 . The inductor
key components are shown in Fig. 2. When Q1 is turned ON
current iL K 2 (t) can be expressed as follows
while Q3 is turned OFF, the current flows through LK 1 , Q1 and
winding NP 1 , which will couple a current to the secondary −VC c l a m p 2
iL K 2 (t) = iL K 2 (T1 ) + t. (3)
side and flow through NS 1 , NS 2 , D5 , D8 , LO 1 , and LO 2 to the LL K 2
load. When Q1 is turned OFF while Q3 is turned ON, leakage
On the secondary side of the transformer, rectifier diodes
inductor LK 1 will resonate with capacitors Cr 1 and Cr 3 . When
D5 –D8 are freewheeling. This mode ends when iL K 1 (t) reaches
the voltage across Cr 3 drops to zero, D3 is forced to forward
the reflected current of the output inductor current iL o1 .
bias, and then, the energy trapped in the leakage inductor is
recycled to Cclam p1 . After a quarter of the resonant period of Mode 3 [Fig. 3(c), T2 ≤ t < T3 ]: At T2 , the converter starts
LK 1 and Cclam p1 , capacitor Cclam p1 begins to release its stored to transfer power from the input through the transformer to
energy through Q3 , LK 1 and the transformer to the load. It the load, and diodes D6 and D7 tend to be reversely bi-
is worth mentioning that flux balance can be always insured ased. Inductor LK 1 is linearly charged while inductor LK 2 is
because the clamping circuits help to reset the core and recy- still releasing its trapped energy to Cclam p2 . Then, capacitor

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198 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 44, NO. 1, JANUARY/FEBRUARY 2008

Fig. 3. Topological modes existing in the proposed converter operation over half a switching cycle.

Cclam p2 begins to release its trapped energy through Q4 , LK 2 , and

and the transformer to the load. Inductor currents iL K 1 (t) and n(VI − vL K 1 ) − 0.5VO
iL K 2 (t) can be expressed as follows iL o2 (t) = × t + iL o2 (T2 ) (7)
Lo2
(VI − VN p1 ) where vL K 1 is the voltages across LK 1 , and n = NS 1 /NP 1 =
iL K 1 (t) = iL K 1 (T2 ) + t (4)
LL K 1 NS 2 /NP 2 is the secondary to the primary turns ratio of trans-
former T1 .
and
−(VC c l a m p 2 + VN p2 ) Mode 4 [Fig. 3(d), T3 ≤ t < T4 ]: At T3 , main switch Q1 is
iL K 2 (t) = iL K 2 (T2 ) + t (5) turned OFF and auxiliary switch Q3 still stays in the OFF state.
LL K 2
In this mode, leakage inductor LK 1 releases its energy to
where VN p1 and VN p2 are the voltages across the windings NP 1 capacitors Cr 1 and Cr 3 with a resonant manner. Capacitor
and NP 2 , respectively. On the secondary side of the transformer, Cr 1 is charged toward (VI + VC c l a m p 1 ), while capacitor Cr 3
the current flows through the paths of NS 1 –D5 –LO 1 –CO 1 and is discharged down to zero. To achieve an ZVS feature for
NS 2 –D8 –CO 2 –LO 2 . Inductor currents iL o1 and iL o2 are lin- switch Q3 , the energy tapped in leakage inductor LK 1 should
early increased, which can be expressed as follows: satisfy the inequality
n(VI − vL K 1 ) − 0.5VO 0.5 × [iL K 1 (T3 )]2 LK 1 ≥ 0.5 × [vD S 3 (T3 )]2 (Cr 1 //Cr 3 ).
iL o1 (t) = × t + iL o1 (T2 ) (6) (8)
Lo1

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WU et al.: AN ACTIVE-CLAMP PUSH–PULL CONVERTER FOR BATTERY SOURCING APPLICATIONS 199

During this mode, capacitor Cclam p2 continuously releases

its stored energy. On the secondary side of the transformer,
the current flows through the paths of NS 1 –D5 –LO 1 –CO 1 and
NS 2 –D8 –CO 2 –LO 2 .
Mode 5 [Fig. 3(e), T4 ≤ t < T5 ]: Mode 5 starts with voltage
vD S 3 dropping to zero at T4 . Inductor current iL K 1 forces the
body diode D3 conducting and creating an ZVS condition
for Q3 . The driving signal should be applied to Q3 at this
time interval to achieve an ZVS feature. In this mode, the
energy trapped in LK 1 is recycled to Cclam p1 . Due to the
capacitance of Cclam p1 is large enough, voltage VClam p1 will
hold constant. Inductor current iL K 1 is linearly discharged,
which can be expressed as follows:
−(VClam p1 + VN p1 )
iL K 1 (t) = iL K 1 (T4 ) + t. (9)
LK 1
During this mode, capacitor Cclam p2 continuously releases Fig. 4. Simplified key current and voltage waveforms of the proposed con-
its stored energy. On the secondary side of the transformer, verter.
the current flows through the paths of NS 1 –D5 –LO 1 –CO 1 and
NS 2 –D8 –CO 2 –LO 2 . Mode 5 ends when auxiliary switch Q4 is
turned OFF.
When auxiliary switch Q4 is turned OFF at the end of mode
5, operation of the other half switching cycle will start.
In the proposed converter, both of main and auxiliary active
switches are operated with the ZVS, and the energy trapped
in the leakage inductors can be recovered. With the clamping
circuit, the main switches can be operated with low voltage
spikes, reducing component stresses significantly. The proposed
converter can reduce not only switching loss but also turns
ratio of a transformer over a conventional push–pull converter. Fig. 5. Plots of voltages V C la m p 1 and V C la m p 2 versus duty ratio D for various
input voltages.
Detailed analysis and parameter design are presented in the
following section.

III. ANALYSIS AND DESIGN

A. Voltage Transfer Ratio and Clamped Voltage
In the steady-state operation of the proposed converter, the
time intervals T0 to T1 and T3 to T4 are very short as compared
to one switching period. Thus, they will not be considered in the
analysis of dc voltage transfer ratio, and the simplified wave-
forms are shown in Fig. 4. In Fig. 4, the duty ratio D is the on
time of main switch Q1 or Q2 , and TS represents the switching
Fig. 6. Plots of normalized voltage ratio α versus duty ratio D.
period of the converter operation. Since inductance of LK 1 and
LK 2 is less than that of the magnetizing inductors of the center-
tapped transformer, the voltages across LK 1 and LK 2 can be the duty ratio is usually limited to being lower than 0.5 in the
also neglected from the analysis. converter design. When ignoring the charging time of the leak-
According to the volt–second balance principle of the induc- age inductors, the input-to-output transfer ratio can be derived
tors, the voltages across Cclam p1 and Cclam p2 can be derived as as
follows: Vo
= 2n(D + D2 ) (11)
D VI
VC c l a m p 1 = VC c l a m p 2 = VC c l a m p = VI . (10)
1−D where n = NS 1 /NP 1 = NS 2 /NP 2 . From (11), we can plot the
From (10), we can plot the relationship between voltage curves showing the relationship between D and normalized
VC c l a m p and duty ratio D for different input voltages, as il- input-to-output voltage ratio α = (VO /VI )/n, as illustrated in
lustrated in Fig. 5. According to the plots, voltage VC c l a m p will Fig. 6. It can be observed from the curve denoted with “theo-
go beyond input voltage VI when D is greater than 0.5 that will retical” that the proposed converter can yield a higher step-up
result in a high voltage stress imposed on the components. Thus, voltage ratio than that of a conventional hard switching one.

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200 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 44, NO. 1, JANUARY/FEBRUARY 2008

Fig. 7. Plots of normalized lost duty ratio ∆T S /DT S versus output current
Fig. 8. Plots of voltage V D S 1 versus duty ratio D for various input voltages.
IO for various input voltages.

Charging time of the leakage inductor will reduce the effective steady state, as illustrated in Fig. 4. Thus, absolute values of the
duty ratio. The lost duty time interval ∆TS can be expressed as peak inductor current and its valley current will be identical.
The averaged currents flowing through main switches Q1 and
2nIO LK 1 Q2 , auxiliary switches Q3 and Q4 , and diodes D5 –D8 can be
∆TS = (12)
VI derived as
where IO is the average output current. During the charging ID S 1 = ID S 3 = 2nIO (D + D2 )/D (17)
time, there is no power delivered to the load. Thus, the input-
to-output transfer ratio shown in (11) should be corrected to the ID S 3 = ID S 4 = 0 (18)
expression
and

 2 
Vo ∆TS ∆TS ID 5 = ID 6 = ID 7 = ID 8 = IO /[2(D + D2 )].
= 2n D − + D− . (13) (19)
VI TS TS
Their peak currents therefore can be expressed as
From (12), we can sketch the curves showing the relationship
between normalized lost duty (∆TS /DTS ) and IO for different 1
ID S 1,P K = ID S 1 + Im (20)
values of input voltage VI , as illustrated in Fig. 7. The lost duty 2
is proportional to the output current and leakage inductance, ID S 2,P K = ID S 1,P K (21)
while it is inversely proportional to the input voltage. In the
converter, leakage inductor LK 1 is used for achieving the ZVS. and
Larger leakage inductance can achieve the ZVS over a wider IO
ID 5 = ID 6 = ID 7 = ID 8 = (22)
load range. However, it will result in a larger duty loss and 2(D + D2 )
need a transformer with higher turns ratio, which in turn will
where
result in low efficiency. Thus, the lost duty ratio in the proposed
converter is a critical issue. In practice, the lost duty ratio should VI
Im = DTS (23)
be limited to below 10% of the minimum duty ratio to ensure Lm
high efficiency and low current stress. Analytical expressions of and Im is the magnetizing current of transformer T1 .
the component stresses are derived in the following section. From (12)–(14), we can plot the curves showing the rela-
tionship between duty ratio D and component stress VD S 1 for
B. Voltage and Current Stresses different values of input voltage VI , as illustrated in Fig. 8. It can
According to the previous description of the operational be observed that the voltage stresses of Q1 –Q4 are increased
modes, the voltages across main switches Q1 and Q2 , auxil- with increase of D.
iary switches Q3 and Q4 , and rectifier diodes D5 –D8 can be In the converter with the active-clamp circuits, both the volt-
derived as follows age stresses of the main switches and auxiliary switches can be
reduced. Lower switch voltage stress implies that switches with
VD S 1 = VD S 2 = VI + V C c l a m p (14) lower rds (ON) can be used. Moreover, the trapped energy in the
VD S 3 = VD S 4 = VI + VC c l a m p (15) leakage inductor can be recovered. It is notable that the problem
results from voltage spike can be eliminated in the proposed
and converter.
In the conventional push–pull converter, a potential problem
VD 5 = VD 6 = VD 7 = VD 8 = 2VO . (16)
of flux imbalance will limit its applications. The active-clamp
Applying amp–second balance principle to capacitors circuits adopted in the converter can eliminate this problem,
Cclam p1 and Cclam p2 can yield that two of the gray areas and which is explained as follows. In practice, a real circuit would
two of the grid areas should be, respectively, identical in the have different duty ratios for the main switches, which will

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WU et al.: AN ACTIVE-CLAMP PUSH–PULL CONVERTER FOR BATTERY SOURCING APPLICATIONS 201

1) From the specifications of the input low-line voltage VI =

VI (low ) and the output voltage VO , a maximum duty ratio
D = Dm ax < 0.5 is selected, and then, an appropriate
normalized voltage ratio α can be determined from the
curves shown in Fig. 6 (a larger value of D will result in
lower current stress).
2) According to the determined α and the input high-line
voltage VI = VI (high) , the minimum duty ratio D = Dm in
can be read from the curves shown in Fig. 6.
3) According to the determined α and the specified input
voltage, turns ratio n can be calculated from (9).
Fig. 9. Plots of the ZVS region relating to L K 1 and Io at V I = 60 V. 4) According to the determined n and Dm in , VD S 1 and vD S 3
can be determined from (14) and (15).
5) Verify if the voltage stresses of VD S 1 and vD S 3 are below
result in different magnetizing as well as leakage inductor cur- the rated voltage of the MOSFETs. If it is not, decrease the
rents. Since the leakage inductor currents will be recycled to the values of turns ratio n, and repeat steps 1–4.
clamping capacitor, a larger current will result in more charges 6) From Fig. 9 and the minimum output current for achieving
stored in the clamping capacitor. Then, the capacitor voltage the ZVS, the leakage inductor can be determined.
will increase. The increase of the clamping capacitor voltage
will in turn provide a larger product of volt–second that can be
used to balance the excessive flux inducing from a larger duty IV. EXPERIMENTAL RESULTS
ratio. The volt–second and amp–second balances in the leak- To illustrate the analysis and discussion, a 1 kW prototype of
age inductors, transformer, and clamping capacitors can always a discharger with active-clamp circuits was built. The schematic
hold in the steady state. Thus, with the active-clamp circuits, diagram of the proposed converter is depicted in Fig. 1 and its
potential flux-imbalance problems can be solved. Furthermore, specifications are listed as follows:
the active-clamp circuits can help to achieve the ZVS features. 1) input voltage: 40–60 VDC ;
The condition for achieving the ZVS is derived in the following 2) output voltage: 400 VDC ;
section. 3) output current: 2.5 A;
4) switching frequency: 50 kHz.
C. Condition for ZVS With these specifications and choosing Dm ax = 0.42, nor-
According to (1) and (8), it is necessary to store enough malized voltage ratio α = 1.2 can be determined from Fig. 6.
energy in the leakage inductor to achieve the ZVS at switch According to the determined α = 1.2 and the low-line voltage
turn-ON transition. Because the ZVS transient period of switch VI = 40 V, turns ratio n = 8 can be determined from (11).
Q1 is less than that of switch Q3 , the ZVS condition for both Voltage stress VD S 1 = 100 V of switch Q1 and voltage stress
active switches should be determined by (1). From, (1), (14), vD S 3 = 100 V of switch Q3 can be determined from (14) and
(17), (20), and (23), we can obtain the inequality (15), respectively. If the minimum output current is limited to
0.75 A for achieving an ZVS condition, the leakage inductor
(Cr 1 //Cr 3 )(VI − VC c l a m p )2 can be then determined as 4 µH from Fig. 9. Although the ZVS
LK 1 = LK 2 ≥ (24)
(ID S 1 + Im )2 does not sustain at the load current below 0.75A, it will not
cause thermal problems at converter operation.
which can be used to determine a proper leakage inductor. Ac-
The components of the power stage are designed as follows:
cording to (24), the ZVS condition for the switches is depending
1) Q1 , Q2 : IRFP260;
on (Cr 1 //Cr 3 ), LK 1 , VI , and IO . The parasitic capacitors Cr 1
2) D5 –D8 : HFA08TB120;
and Cr 3 of the power MOSFETs are used as the resonant capac-
3) Q3 , Q4 : FB61N15D;
itors in the proposed converter. For determining leakage induc-
4) Cclam p1 , Cclam p2 : 2.2 µF/200 V;
tance, we can plot the curves showing the relationship between
5) Lm 1 , Lm 2 : 35 µH, 35 µH;
leakage inductance LK 1 and output current IO under different
6) CO 1 , CO 2 : 470 µF/250 V;
input voltages, as illustrated in Fig. 9. The inductance should be
7) LK 1 , LK 2 : 4 µH, 4 µH;
selected from the gray area for achieving the ZVS. From Fig. 9,
8) LO 1 , LO 2 : 600 µH, 600 µH;
it can be seen that the ZVS region of the proposed converter
9) T1 : TDK EE55; NP 1 = NP 2 = 4 T; NS 1 = NS 2 =32 T.
will shrink with increase of input voltage and decrease of output
Fig. 10 shows the measured waveforms from a push–pull
current.
converter without clamping circuit to illustrate high voltage
spike across the active switch. Figs. 11 and 12 show measured
D. Summary of Design Procedure waveforms of drain–source voltage and current to illustrate low
Based on the equations and curves discussed previously, a voltage stress and no spike at switches Q1 and Q3 . Figs. 13
design procedure of the proposed converter is summarized as and 14 show measured waveforms of drain–source voltage and
follows. current to illustrate an ZVS feature. Fig. 15 shows efficiency

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202 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 44, NO. 1, JANUARY/FEBRUARY 2008

Fig. 10. Measured waveforms of gate signal V G S 1 , drain–source voltage

V D S 1 and current ID S 1 from converter without active-clamp circuits illustrat- Fig. 13. Measured waveforms of drain–source voltage V D S 1 and current
ing high voltage spike across Q 1 . ID S 1 illustrating an ZVS feature.

Fig. 11. Measured waveforms of drain–source voltage V D S 1 and current

ID S 1 from the proposed converter illustrating a low voltage stress and no spike Fig. 14. Measured waveforms of drain–source voltage V D S 2 and current
at switch Q 1 . ID S 2 illustrating an ZVS feature.

Fig. 12. Measured waveforms of drain–source voltage V D S 2 and current

ID S 2 from the proposed converter illustrating a low voltage stress and no Fig. 15. Plots of efficiency versus power for the proposed converter and the
spikes at switch Q 3 . hard switching without the active-clamp circuits.

measurements from the proposed converter and a hard switch-

ing one, from which it can be seen that efficiency has been
improved significantly and the maximum efficiency can reach
91%. Fig. 16 shows measurements of output voltage under in-
put and load variations, from which it can be observed that tight
regulation can be achieved.
Measured results from a hard switching and the proposed
push–pull converters are listed in Tables I and II. Tables III and
IV summarize their loss analysis results. In Table III, the total
loss of MOSFET switching loss, diode switching loss, and snubber
loss is 51.62 W. This significant loss can be reduced when the
active-clamp circuits are adopted. Even though the active-clamp
circuits used to achieve the ZVS cause extra conduction loss Fig. 16. Output voltage plots of the proposed converter under input and load
(∼4.64 W), the overall power loss is still far below that of variations illustrating a tight output regulation.

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WU et al.: AN ACTIVE-CLAMP PUSH–PULL CONVERTER FOR BATTERY SOURCING APPLICATIONS 203

TABLE I its hard-switching counterpart. Conversion efficiency has been

MEASURED RESULTS FROM A HARD-SWITCHING PUSH–PULL CONVERTER
improved significantly in the proposed converter.

V. CONCLUSION
This paper has proposed a push–pull converter with active-
clamp circuits. In the paper, analysis of the converter has been
presented in detail, from which design equations and circuit
parameters were derived. The proposed converter can be oper-
ated with constant switching frequency and PWM control. By
adopting the active-clamp circuits, energy trapped in the leakage
inductors can be recovered, the ZVS features can be achieved,
and voltage spike can be suppressed effectively. Moreover, po-
tential flux-imbalance problems with the transformer can be
eliminated from the proposed converter. Experimental results
TABLE II have verified that the proposed converter can achieve high effi-
MEASURED RESULTS FROM THE PROPOSED PUSH–PULL CONVERTER WITH
ACTIVE-CLAMP CIRCUITS ciency over a wide load range. It is relatively feasible for high
step-up discharger applications.

REFERENCES
[1] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics,
2nd ed. Norwell, MA: Kluwer, 2001, pp. 159–160.
[2] M. J. Ryan, W. E. Brumsickle, D. M. Divan, and R. D. Lorenz, “A new
ZVS LCL-resonant push–pull DC–DC converter topology,” IEEE Trans.
Ind. Appl., vol. 34, no. 5, pp. 1164–1174, Sep./Oct. 1998.
[3] I. Boonyaroonate and S. Mori, “A new ZVCS resonant push–pull DC/DC
converter topology,” in Proc. Appl. Power Electron. Conf., 2002, pp. 1097–
1100.
[4] J. Ying, Q. Zhu, H. Lin, and Z. Wu, “A zero-voltage-switching (ZVS)
push–pull DC/DC converter for UPS,” in Proc. IEEE Power Electron.
Drive Syst. Conf., 2003, pp. 1495–1499.
[5] M. Shoyama and K. Harada, “Zero-voltage-switched push–pull DC–DC
TABLE III converter,” in Proc. Power Electron. Spec. Conf., 1991, pp. 223–229.
LOSS ANALYSIS OF A HARD-SWITCHING PUSH–PULL CONVERTER AT 1 KW [6] M. Shoyama and K. Harada, “Zero-voltage-switching realized by magne-
tizing current of transformer in push–pull current-fed DC–DC,” in Proc.
Power Electron. Spec. Conf., 1993, pp. 178–184.
[7] R. Torrico-Bascope, F. L. M. Antunes, and I. Barbi, “Optimal double
ZVS-PWM active-clamping forward converter with inputs connected in
series and parallel,” in Proc. IEEE Power Electron. Spec. Conf., 2004,
pp. 1621–1626.

Tsai-Fu Wu (S’88–M’91–SM’98) received the B.S.

degree in electronic engineering from the National
Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in
1983, the M.S. degree in electrical and computer en-
gineering from Ohio University, Athens, in 1988, and
the Ph.D. degree in electrical engineering and com-
puter science from the University of Illinois, Chicago,
in 1992.
TABLE IV From 1985 to 1986, he was a System Engineer in
LOSS ANALYSIS OF THE PROPOSED PUSH–PULL CONVERTER AT 1 KW SAMPO, Inc., Taipei Hsien, Taiwan, where he was
engaged in developing and designing graphic termi-
nals. From 1988 to 1992, he was a Teaching and Research Assistant in the De-
partment of Electrical Engineering and Computer Science (EECS), University
of Illinois. Since 1993, he has been with the Electrical Engineering Department,
National Chung Cheng University, Chia-Yi, Taiwan, where he is currently a
Professor, and the Director of the Elegant Power Application Research Center
(EPARC). His current research interests include developing and modeling of
power converters, design of electronic dimming ballasts for fluorescent lamps,
metal halide lamps and plasma display panels, design of solar array supplied
inverters for grid connection, and design of pulsed-electrical-field generators
for transdermal drug delivery and food pasteurization.
Dr. Wu is the recipient of three Best Paper Awards from Taipei Power Elec-
tronics Association during 2003–2005. In 2005, he was rated as one of the top
5% outstanding researchers by the National Science Council, Taiwan. He is a
Senior Member of the International Commission on Illumination (CIE).

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204 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 44, NO. 1, JANUARY/FEBRUARY 2008

Jin-Chyuan Hung (S’99–M’05) received the B.S. Cheng-Tao Tsai was born in Taiwan, R.O.C., in
degree in biomedical engineering from Chung Yuan 1962. He received the B.S. degree in electrical
Christian University, Chung-Li, Taiwan, R.O.C., in engineering from Feng Chia University, Taichung,
1989, and the M.S. and Ph.D. degrees in electrical Taiwan, in 1991, and the M.S. degree in electrical
engineering from the National Chung Cheng Univer- engineering in 2003 from the National Chung Cheng
sity, Chia-Yi, Taiwan, in 1996 and 2005, respectively. University, Chia-Yi, Taiwan, where he is currently
From 1996 to 1999, he was an Electrical Engineer working toward the Ph.D. degree in the Department
at the Industry Technology Research Institute (ITRI), of Electrical Engineering.
Hsin-Chu, Taiwan, where he was engaged in devel- His current research interests include design of
oping and designing high-voltage power supplies for switching-mode power supplies, power factor cor-
X-ray generators, and where, from 2000 to 2002, he rection technology, and chargers for electric vehicle.
was a Design Engineer, developing hybrid electric vehicles (EVs). From 2005
to 2006, he was an R&D Manager at Delta Optoelectronics, Inc., Hsin-Chu,
Taiwan, where he was involved in developing and designing driving systems
of mercury-free flat fluorescent lamp (FFL) for liquid-crystal display (LCD)
backlight applications. In 2006, he joined NuLight Technology Corporation,
Tainan, Taiwan, where he is currently a Vice Division Director. His current
research interests include development of soft-switching converters, design of
the driving system of dielectric barrier discharge (DBD) lamps, and design of
converters for EVs.

Yaow-Ming Chen (S’96–M’98–SM’05) received the

B.S. degree from the National Cheng-Kung Univer-
Jeng-Tsuen Tsai was born in Hsinchu, Taiwan, sity, Tainan, Taiwan, R.O.C., in 1989, and the M.S.
R.O.C., in 1980. He received the B.S. degree from and Ph.D. degrees from the University of Missouri,
the National Formosa University, Yunlin, Taiwan, in Columbia, in 1993 and 1997, respectively, all in elec-
2003, and the M.S. degree from the National Chung trical engineering.
Cheng University, Chia-Yi, Taiwan, in 2005, all in From 1997 to 2000, he was with I-Shou Univer-
electrical engineering. sity, Kaohsiung, Taiwan, as an Assistant Professor.
In 2006, he joined NuLight Technology Corpora- In 2000, he joined the National Chung Cheng Uni-
tion, Tainan, Taiwan, as a Senior Engineer. His cur- versity, Chia-Yi, Taiwan, where he is currently an
rent research interests include developing and design- Associate Professor in the Department of Electrical
ing of converter topologies, power-factor correctors, Engineering. His current research interests include power electronic converters,
and flat-fluorescent lamp drivers. power system harmonics and compensation, and intelligent control.

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