Defective Pixel Correction

Henrik Backe-Hansen

Master of Science in Electronics

Submission date: June 2010
Supervisor: Einar Johan Aas, IET
Co-supervisor: Christian Stephansen, Aptina Norway

Norwegian University of Science and Technology

Department of Electronics and Telecommunications
Problem Description
Implementing a system for detection and correction of defective pixels onto an FPGA

Assignment given: 05. January 2010

Supervisor: Einar Johan Aas, IET
 Defect Pixel Correction
by

Henrik Backe-Hansen

Masters Thesis
A thesis submitted in partial fulllment for the requirement for the degree of Master of
Technology

Supervisors: Prof. Einar Johan Aas and Christian Stephansen

June 23, 2010

Norwegian University of Science and Technology

Department of Electronics and Telecommunication
Assignment
This assignment species that the candidate must nd a method of detecting defective
pixels in a data stream from an image sensor and correcting them. All the processing is
to take place in hardware and the system should be completed to such a degree that it
can function with the constraints imposed when operating in a real time environment.
This master's thesis is a continuation of a project [22] with the goal of implementing
algorithms for detecting and correcting defective pixels in an image,with the processing
done in software. The median, conservative smoothing, gradient and adaptive algorithm
were programmed in software and then compared with each other based on their peak
signal to noise ratio, mean square error, mean absolute error, simulation time, and survey
results.The survey was issued by showing the resulting images from the various algorithms
with the same amount of noise added pre correction. The results show a correlation be-
tween the statistical values and what the survey showed to be the best image. In other
words, the image with the highest levels of the measured values was also the image most
participants thought was the best image. It was therefore concluded that the median
algorithm produced the best results in terms of measured values and visual inspection,
and as, such would be a good choice to implement as part of a master's thesis project.
The median algorithm will be implemented in hardware using a development board with
an Xilinx virtex 5 fpga.Once the vhdl programming is complete, an embedded system
will store the values from the algorithm onto a ash memory.The data can then be in-
spected by measuring values and be subject to visual inspection. Assignment was given
05.January 2010.

Supervisors: Einar Johan Aas, NTNU

Christian Stephansen, Aptina Norway

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Abstract
When using CMOS technology for image sensors, there is a possibility that any given
pixel is defective and will thus produce a value that does not correlate to the amount of
light it was subject to. As such, the processing unit will calculate a value that diers
from the value produced if the transistor was working correctly. Having a pixel with a
defective value can manifest itself as a light spot or a dark spot depending on whether the
transistor for that pixel is on or o. In some areas where the value of the defective pixel
does not dier greatly from its neighbors, the image will not appear as degraded in the
eyes of the viewer as if the defective value was in great contrast to its surroundings.The
ability to compensate for the defective pixels with an algorithm will result in a more
robust device that is not required to function perfectly in order to produce an image. It
also translates into prot as a company can sell image sensors that would otherwise have
been discarded by testing procedures.

This report is organized with chapter 1 providing the introduction to the assignment in
terms of the nature of defective pixels and also creating a context with explanation as
to why it is an important aspect of manufacturing image sensors .Chapter 2 describes
the development board that is utilized and how an embedded system can utilize a vhdl
peripheral. It also shows what components will go into making an embedded system with
the required functionality. The theory behind components and techniques used in this
project is in chapter 3. The vhdl les to be added to a peripheral so that they can be
accessed by the cpu, and the architectures of the vhdl les and microblaze are placed
in chapter 4. Chapter 5 contains the simulations of the input images with dierent
noise levels and threshold levels in addition to tests designed to determine the embedded
systems functional ability.The vhdl les and the microblaze systems are synthesized with
the resulting numbers revealed in chapter 6. The tools used in this project are listed
in chapter 7 with their version number. Chapter 8 contains discussions regarding the
results and techniques in this project. The concluding remarks and the further work for
the project are in chapter 9 and 10, respectively. A list of terms will explain abbreviations
used in this report.

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Preface
This report along with the system produced are the nal products of a project that
aimed at implementing a defective pixel correction algorithm with all the processing
done in hardware. It also concludes the master's degree with specialization in design of
digital systems from the Norwegian University of Science and Technology in Trondheim,
Norway. The project spans a wide area with designing both hardware and software to
communicate with the hardware. As such, it has been necessary to consult with a few
key persons in order to get the project completed, and they all deserve recognition for
their contributions. Christian Stephansen at Aptina Norway was instrumental in oering
in-depth information regarding the demands on an image sensor. He also gave input to
what the end goal of the thesis should be. Professor Einar Johan Aas was the supervisor
at the university who was also a part of determining the goal of the thesis along with
valuable input as to the organization of the report and serving as a technical consultant.
Jan Anders Mathisen was kind enough to lend me the Xilinx evaluation board and point
out places to learn about the board that facilitated getting into programming at an early
stage. He has also been a technical consultant for helping me problem solve building
the microblaze system at times where I was at a stand still. My American relatives Teri
Venker and Terry Jacobson graciously opened their home to me and allowed me to live
with them in Madison, Wisconsin for the duration of the thesis so I could experience
another culture while doing the research.

Madison, Wisconsin, U.S.A. June 23, 2010

Henrik Backe-Hansen
[email protected]

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Contents

1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Static Defect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Pixel Defect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.3 Programmable Threshold . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 System 4
2.1 Xilinx ML501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Microblaze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.1 Creating an embedded system with platform studio . . . . . . . . 5
2.2.2 System Ace Controller . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.3 RS232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.5 Creating an intellectual property . . . . . . . . . . . . . . . . . . 11
2.2.6 Access Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.7 Adding c source le . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 Supporting Theory 17
3.1 Median Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Types of Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 Salt and pepper noise . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.2 Gaussian Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.1 Histogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.2 Contrast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.3 Bayer Color Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.4 PGM Image Format . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Number representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.1 Hexadecimal scale with base 16 . . . . . . . . . . . . . . . . . . . 22
3.4.2 Decibel scale with base 10 . . . . . . . . . . . . . . . . . . . . . . 23
3.5 Text representation using ascii . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 Measured Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6.1 Mean Square Error (MSE) . . . . . . . . . . . . . . . . . . . . . . 24
3.6.2 Mean absolute error(MAE) . . . . . . . . . . . . . . . . . . . . . 24

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 3.6.3 Peak signal to noise ratio (PSNR) . . . . . . . . . . . . . . . . . . 25
3.6.4 Real time constraints . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7 TextIO vhdl package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4 Architecture 26
4.1 VHDL Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.1 Size Package Module . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.2 Median module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.3 Image_core Module . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1.4 Ctrl Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 Microblaze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.1 Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.2 Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4 Matlab scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.4.1 Reading Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.4.2 Write Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.4.3 Measuring Statistical Values . . . . . . . . . . . . . . . . . . . . . 36

5 Simulation 37
5.1 VHDL module testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.1.1 Median Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.1.2 Image_core Testing . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1.3 Ctrl Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2 Test of the whole VHDL system . . . . . . . . . . . . . . . . . . . . . . . 41
5.2.1 Dierent noise levels . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2.2 Dierent threshold values . . . . . . . . . . . . . . . . . . . . . . 45
5.3 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.4 Microblaze simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.4.1 System Ace write to card . . . . . . . . . . . . . . . . . . . . . . . 49
5.4.2 Interrupt testing . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.4.3 Read value from peripheral register . . . . . . . . . . . . . . . . . 50

6 Synthesis 52
6.1 VHDL Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.2 Microblaze Syntethization . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7 Tools 54

8 Discussion 55
8.1 Vhdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.2 Microblaze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.3 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.4 Real time operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.5 Comparison with 2009 fall project . . . . . . . . . . . . . . . . . . . . . . 57
8.6 Interpreting images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.7 Border pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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 8.8 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.9 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9 Concluding remarks 59

10 Further Work 60

Bibliography 61

Appendices 63
.1 VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
.1.1 VHDL Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . 63
.1.2 VHDL Test Benches . . . . . . . . . . . . . . . . . . . . . . . . . 105
.2 Microblaze les . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
.2.1 mss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
.2.2 mhs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
.2.3 ucf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
.2.4 xparameters.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
.3 Microblaze Synthesize . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
.4 Matlab Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
.4.1 Read Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
.4.2 Write Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
.4.3 Measuring Values . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
.4.4 Median algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
.5 C Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
.5.1 Test Compact ash . . . . . . . . . . . . . . . . . . . . . . . . . . 178
.5.2 Test interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
.5.3 Test interrupt with read and write . . . . . . . . . . . . . . . . . 181
.6 Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
.6.1 Original Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
.6.2 Lena Images from dierent noise levels . . . . . . . . . . . . . . . 186
.6.3 Lena Images from dierent threshold levels . . . . . . . . . . . . . 197
.6.4 Field Images from dierent noise levels . . . . . . . . . . . . . . . 205
.6.5 Field Images from dierent threshold levels . . . . . . . . . . . . . 216
.6.6 Canyon Images from dierent noise levels . . . . . . . . . . . . . . 224
.6.7 Canyon Images from dierent threshold levels . . . . . . . . . . . 235
.6.8 Image from software simulation . . . . . . . . . . . . . . . . . . . 243

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List of Figures

2.1 Xilinx ML501 development board . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Choosing a board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Choosing peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5 Base System Builder Complete . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Create Custom Peripheral guide step 1 . . . . . . . . . . . . . . . . . . . 12
2.7 Peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.8 Interupt service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.9 Peripheral registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.10 Peripheral Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.11 Peripheral hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.12 Import peripheral complete . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.13 Microblaze address map . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Truncated Original Image Values . . . . . . . . . . . . . . . . . . . . . . 17

3.2 Resulting Truncated Image Values . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Impact of salt and pepper noise . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Impact of Gaussian noise . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Image histogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 High and Low contrast histograms . . . . . . . . . . . . . . . . . . . . . . 21
3.7 Bayer Filter [5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8 Example PGM le format . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9 Hexadecimal number representation . . . . . . . . . . . . . . . . . . . . . 23

4.1 Vhdl le hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2 Size package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3 Median Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4 Median module state machine . . . . . . . . . . . . . . . . . . . . . . . . 28
4.5 Image_core Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.6 Image_core module state machine . . . . . . . . . . . . . . . . . . . . . . 30
4.7 Ctrl Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.8 Ctrl module state machine . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.9 Vhdl Peripheral hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.10 Microblaze Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.11 Microprocessor hardware specication example . . . . . . . . . . . . . . . 34
4.12 User constraint le example . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.13 Microprocessor software specication . . . . . . . . . . . . . . . . . . . . 35

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5.1 Input Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2 Output Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3 Image_core input sequence . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.4 Image_core end of execution . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.5 Input Image with noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.6 Output image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.7 Ctrl output sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.8 Peak signal to noise ratio for dierent noise levels . . . . . . . . . . . . . 42
5.9 Mean square error for dierent noise levels . . . . . . . . . . . . . . . . . 43
5.10 Mean absolute error for dierent noise levels . . . . . . . . . . . . . . . . 43
5.11 Simulation times for dierent noise levels . . . . . . . . . . . . . . . . . . 44
5.12 Simulation times per pixel . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.13 Peak signal to noise ratio for dierent threshold levels . . . . . . . . . . . 46
5.14 Mean square error for dierent threshold levels . . . . . . . . . . . . . . . 47
5.15 Mean absolute error for dierent threshold levels . . . . . . . . . . . . . . 47
5.16 Simulation times for dierent threshold levels . . . . . . . . . . . . . . . 48
5.17 Compact ash read and write simulation . . . . . . . . . . . . . . . . . . 49
5.18 File written by the isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.19 Test Read from a Register . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1 Synthesis delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.2 Synthesis resource utilization . . . . . . . . . . . . . . . . . . . . . . . . . 53

1 Original noise free Lena image . . . . . . . . . . . . . . . . . . . . . . . . 183

2 Original noise free Canyon image . . . . . . . . . . . . . . . . . . . . . . 184
3 Original noise free Field image . . . . . . . . . . . . . . . . . . . . . . . . 185
4 Lena image with noise level 0.001 . . . . . . . . . . . . . . . . . . . . . . 186
5 Restored Lena image from noise level 0.001 . . . . . . . . . . . . . . . . 186
6 Lena image with noise level 0.002 . . . . . . . . . . . . . . . . . . . . . . 187
7 Restored Lena image from noise level 0.002 . . . . . . . . . . . . . . . . 187
8 Lena image with noise level 0.004 . . . . . . . . . . . . . . . . . . . . . . 188
9 Restored Lena image from noise level 0.004 . . . . . . . . . . . . . . . . 188
10 Lena image with noise level 0.006 . . . . . . . . . . . . . . . . . . . . . . 189
11 Restored image from noise level 0.006 . . . . . . . . . . . . . . . . . . . 189
12 Lena image with noise level 0.008 . . . . . . . . . . . . . . . . . . . . . . 190
13 Restored Lena image from noise level 0.008 . . . . . . . . . . . . . . . . 190
14 Lena image with noise level 0.01 . . . . . . . . . . . . . . . . . . . . . . 191
15 Restored Lena image from noise level 0.01 . . . . . . . . . . . . . . . . . 191
16 Lena image with noise level 0.02 . . . . . . . . . . . . . . . . . . . . . . 192
17 Restored Lena image from noise level 0.02 . . . . . . . . . . . . . . . . . 192
18 Lena image with noise level 0.04 . . . . . . . . . . . . . . . . . . . . . . 193
19 Restored Lena image from noise level 0.04 . . . . . . . . . . . . . . . . . 193
20 Lena image with noise level 0.06 . . . . . . . . . . . . . . . . . . . . . . 194
21 Restored Lena image from noise level 0.06 . . . . . . . . . . . . . . . . . 194
22 Lena image with noise level 0.08 . . . . . . . . . . . . . . . . . . . . . . 195
23 Restored Lena image from noise level 0.08 . . . . . . . . . . . . . . . . . 195
24 Lena image with noise level 0.1 . . . . . . . . . . . . . . . . . . . . . . . 196

xii
25 Restored Lena image from noise level 0.1 . . . . . . . . . . . . . . . . . 196
26 Lena image with noise level 0.02 . . . . . . . . . . . . . . . . . . . . . . 197
27 Restored Lena image from threshold level 1 . . . . . . . . . . . . . . . . 197
28 Restored Lena image from threshold level 4 . . . . . . . . . . . . . . . . 198
29 Restored Lena image from threshold level 8 . . . . . . . . . . . . . . . . 198
30 Restored Lena image from threshold level 12 . . . . . . . . . . . . . . . 199
31 Restored image from threshold level 16 . . . . . . . . . . . . . . . . . . . 199
32 Restored Lena image from threshold level 20 . . . . . . . . . . . . . . . 200
33 Restored Lena image from threshold level 22 . . . . . . . . . . . . . . . 200
34 Restored Lena image from threshold level 26 . . . . . . . . . . . . . . . 201
35 Restored Lena image from threshold level 30 . . . . . . . . . . . . . . . 201
36 Restored Lena image from threshold level 34 . . . . . . . . . . . . . . . 202
37 Restored Lena image from threshold level 38 . . . . . . . . . . . . . . . 202
38 Restored Lena image from threshold level 42 . . . . . . . . . . . . . . . 203
39 Restored Lena image from threshold level 46 . . . . . . . . . . . . . . . 203
40 Restored Lena image from threshold level 50 . . . . . . . . . . . . . . . 204
41 Field image with noise level 0.001 . . . . . . . . . . . . . . . . . . . . . . 205
42 Restored Field image from noise level 0.001 . . . . . . . . . . . . . . . . 205
43 Field image with noise level 0.002 . . . . . . . . . . . . . . . . . . . . . . 206
44 Restored Field image from noise level 0.002 . . . . . . . . . . . . . . . . 206
45 Field image with noise level 0.004 . . . . . . . . . . . . . . . . . . . . . . 207
46 Restored Field image from noise level 0.004 . . . . . . . . . . . . . . . . 207
47 Field image with noise level 0.006 . . . . . . . . . . . . . . . . . . . . . . 208
48 Restored Field image from noise level 0.006 . . . . . . . . . . . . . . . . 208
49 Field image with noise level 0.008 . . . . . . . . . . . . . . . . . . . . . . 209
50 Restored Field image from noise level 0.008 . . . . . . . . . . . . . . . . 209
51 Field image with noise level 0.01 . . . . . . . . . . . . . . . . . . . . . . 210
52 Restored Field image from noise level 0.01 . . . . . . . . . . . . . . . . . 210
53 Field image with noise level 0.02 . . . . . . . . . . . . . . . . . . . . . . 211
54 Restored Field image from noise level 0.02 . . . . . . . . . . . . . . . . . 211
55 Field image with noise level 0.04 . . . . . . . . . . . . . . . . . . . . . . 212
56 Restored Field image from noise level 0.04 . . . . . . . . . . . . . . . . . 212
57 Field image with noise level 0.06 . . . . . . . . . . . . . . . . . . . . . . 213
58 Restored Field image from noise level 0.06 . . . . . . . . . . . . . . . . . 213
59 Field image with noise level 0.08 . . . . . . . . . . . . . . . . . . . . . . 214
60 Restored Field image from noise level 0.08 . . . . . . . . . . . . . . . . . 214
61 Field image with noise level 0.1 . . . . . . . . . . . . . . . . . . . . . . . 215
62 Restored Field image from noise level 0.1 . . . . . . . . . . . . . . . . . 215
63 Field image with noise level 0.02 . . . . . . . . . . . . . . . . . . . . . . 216
64 Restored Field image from threshold level 1 . . . . . . . . . . . . . . . . 216
65 Restored Field image from threshold level 4 . . . . . . . . . . . . . . . . 217
66 Restored Field image from threshold level 8 . . . . . . . . . . . . . . . . 217
67 Restored Field image from threshold level 12 . . . . . . . . . . . . . . . 218
68 Restored Field image from threshold level 16 . . . . . . . . . . . . . . . 218
69 Restored Field image from threshold level 20 . . . . . . . . . . . . . . . 219
70 Restored Field image from threshold level 22 . . . . . . . . . . . . . . . 219

xiii
71 Restored Field image from threshold level 26 . . . . . . . . . . . . . . . 220
72 Restored Field image from threshold level 30 . . . . . . . . . . . . . . . 220
73 Restored Field image from threshold level 34 . . . . . . . . . . . . . . . 221
74 Restored Field image from threshold level 38 . . . . . . . . . . . . . . . 221
75 Restored Field image from threshold level 42 . . . . . . . . . . . . . . . 222
76 Restored Field image from threshold level 46 . . . . . . . . . . . . . . . 222
77 Restored Field image from threshold level 50 . . . . . . . . . . . . . . . 223
78 Canyon image with noise level 0.001 . . . . . . . . . . . . . . . . . . . . 224
79 Restored Canyon image from noise level 0.001 . . . . . . . . . . . . . . . 224
80 Canyon image with noise level 0.002 . . . . . . . . . . . . . . . . . . . . 225
81 Restored Canyon image from noise level 0.002 . . . . . . . . . . . . . . . 225
82 Canyon image with noise level 0.004 . . . . . . . . . . . . . . . . . . . . 226
83 Restored Canyon image from noise level 0.004 . . . . . . . . . . . . . . . 226
84 Canyon image with noise level 0.006 . . . . . . . . . . . . . . . . . . . . 227
85 Restored Canyon image from noise level 0.006 . . . . . . . . . . . . . . . 227
86 Canyon image with noise level 0.008 . . . . . . . . . . . . . . . . . . . . 228
87 Restored Canyon image from noise level 0.008 . . . . . . . . . . . . . . . 228
88 Canyon image with noise level 0.01 . . . . . . . . . . . . . . . . . . . . . 229
89 Restored Canyon image from noise level 0.01 . . . . . . . . . . . . . . . 229
90 Canyon image with noise level 0.02 . . . . . . . . . . . . . . . . . . . . . 230
91 Restored Canyon image from noise level 0.02 . . . . . . . . . . . . . . . 230
92 Canyon image with noise level 0.04 . . . . . . . . . . . . . . . . . . . . . 231
93 Restored Canyon image from noise level 0.04 . . . . . . . . . . . . . . . 231
94 Canyon image with noise level 0.06 . . . . . . . . . . . . . . . . . . . . . 232
95 Restored Field image from noise level 0.06 . . . . . . . . . . . . . . . . . 232
96 Canyon image with noise level 0.08 . . . . . . . . . . . . . . . . . . . . . 233
97 Restored Canyon image from noise level 0.08 . . . . . . . . . . . . . . . 233
98 Canyon image with noise level 0.1 . . . . . . . . . . . . . . . . . . . . . 234
99 Restored Canyon image from noise level 0.1 . . . . . . . . . . . . . . . . 234
100 Canyon image with noise level 0.02 . . . . . . . . . . . . . . . . . . . . . 235
101 Restored Canyon image from threshold level 1 . . . . . . . . . . . . . . . 235
102 Restored Canyon image from threshold level 4 . . . . . . . . . . . . . . . 236
103 Restored Canyon image from threshold level 8 . . . . . . . . . . . . . . . 236
104 Restored Canyon image from threshold level 12 . . . . . . . . . . . . . . 237
105 Restored Canyon image from threshold level 16 . . . . . . . . . . . . . . 237
106 Restored Canyon image from threshold level 20 . . . . . . . . . . . . . . 238
107 Restored Canyon image from threshold level 22 . . . . . . . . . . . . . . 238
108 Restored Canyon image from threshold level 26 . . . . . . . . . . . . . . 239
109 Restored Canyon image from threshold level 30 . . . . . . . . . . . . . . 239
110 Restored Canyon image from threshold level 34 . . . . . . . . . . . . . . 240
111 Restored Canyon image from threshold level 38 . . . . . . . . . . . . . . 240
112 Restored Canyon image from threshold level 42 . . . . . . . . . . . . . . 241
113 Restored Canyon image from threshold level 46 . . . . . . . . . . . . . . 241
114 Restored Canyon image from threshold level 50 . . . . . . . . . . . . . . 242
115 Restored Lena image when using the software algorithm designed in the
2009 fall project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

xiv
116 Restored eld image when using the software algorithm designed in the
2009 fall project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
117 Restored canyon image when using the software algorithm designed in the
2009 fall project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

xv
List of Tables

5.1 Software algorithm results . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.1 Software utilized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

xvi
List of Terms
FPGA Field Programmable Gate Array
FLASH Memory that can retain data even when not powered
CPU Central Processing Unit i.e. processor
NTNU Norwegian University of Science and Technology
CMOS Complimentary Metal Oxide Semiconductor
MATLAB Mathematical tool for technical computing
I/O UNIT Input and Output unit
VHDL Hardware Descriptive Language
INTERRUPT Signal to the cpu that an IO unit needs attention
TEXTIO Vhdl package that enables write to le and read from le
BAYER SENSOR A way of representing colors from an image sensor
MICROBLAZE Xilinx soft core cpu on the fpga
BSB Base system builder to help make embedded design
XPS Xilinx platform studio, a tool for working with the cpu
RS232 Serial communication protocol
LCD Liquid Crystal Display
LED Light Emitting Diode
HARVARD ARCHITECTURE Separate storage for instruction and data
DDR2 MEMORY Double Data Rata Synchronous Memory
DSLR Digital Single Lens Reex
FPS Frames per Second
BSB Base System Builder
,
PLB Processor Local Bus
ILMB Instruction Local Memory Bus
DLMB Data Local Memory Bus
BRAM,BRAM Storage elements inside the fpga
DSP Digital Signal Processing
NETLIST Physical description of the system
BITFILE A letype used to program the fpga
BITSTREAM The information inside a Bit le
ISR Interrupt Service Routine
BAUDRATE Rate at which new symbols arrive on a serial line
PARITY Error checking mechanism for serial communication
START BIT Bit that starts a serial communication
STOP BIT Bit that signies stop of data
UART Universal Asynchronous Receive Transmit
FIFO First in First out stack memory
IP Intellectual Property
IPIC Intellectual Property Interconnect
IPIF Intellectual Property Interface
HEADER FILE File that contains the method of a c le with the same name
WRAPPER FILE Vhdl representation of a system component
MS Milli Second
NS Nano Second

xvii
MHZ Mega Hertz
HZ Hertz
KHZ Kilo Hertz
LUT Look Up Table
SLICE Programmable fpga elements that contains LUTs
KB Kilo Byte
GB Giga Byte
PGM Portable Gray Map
CF Compact Flash
HEXADECIMAL Number representation with base 16
MHS Microprocessor Hardware Specication
MSS Microprocessor Software Specication
UCF User Constraint File
dB Decibel
GB Giga Byte (109 byte)
F-stop 1 f-stops is Decreasing / Increasing the amount of light by a factor of two
.vhd VHDL FILE POSTFIX

xviii
Chapter 1

Introduction

This thesis is the continuation of a project that was aimed at creating, comparing and
evaluating dierent methods for correcting defective pixels in an image with all the pro-
cessing done in software. The projects aims at implementing the best method from the
software project into hardware. The assignment is specied by Aptina Norway in con-
junction with the Norwegian University of Science and Technology.

1.1 Background
Defective pixels are caused by an error in the fabrication of the image sensor that trans-
lates into a transistor being either static on or static o and will thus translate into the
cpu interpreting false value from the pixel. The next sections will describe how defective
pixels can manifest themselves on an image and variables involved in the detecting and
correcting algorithm.

1.1.1 Static Defect

Static defective pixels in an image are types of defects that will contribute towards de-
grading the image on every exposure and in the same way every time.That means that
a defective pixel in position (a,b) in the image will show the same value on every image
regardless of the amount of light it is subjected to. Static defective pixels can further
be divided into two categories of "always-on" and "always-o" where an always o tran-
sistor never has any current owing through it and with an always on transistor having
current owing through it at all times. In a correctly working pixel, the current that
ows through a transistor is correlated with the exposure time of the image. A transistor
with no current owing through it will always be interpreted by the cpu as the value 0,
corresponding the white color using an 8- bit gray scale color representation. Having a
transistor that has current owing through it at all times will be interpreted by the cpu
as the value 255 using the same 8-bit gray scale color representation and it will result in a
black color. The idea behind defective pixel correction is to replace defective pixels with

1
the median of the neighboring pixels of the same color according to the Bayer image lter
pattern found in section 3.3.3. The end result will have new pixels in the positions of
the defective pixels going into the algorithm. The dierent correcting algorithms mostly
dier in the way they calculate the value of the pixel that was defective.The median
algorithm utilizes the value of the nine neighboring pixels and replaces the defective pixel
with the median of the neighboring pixels.The task becomes even more complex as it is
advantageous to have a new pixel value not being based on values that are themselves
defective. An even more complex issue is the demands put on an image senor from a
camera application when operating in real time and making sure that the system can
cope with the demands.

1.1.2 Pixel Defect

Single defective pixels in an image are situations where the surrounding neighboring pixels
are giving o the correct value. Multiple defective pixels, however, can have defective
pixels as neighbors, thus complicating the search for working pixels on which to base the
new values.

Individual Pixel Defect

With only a single defective pixel in an area, the corrective measure is to assign a new
value to the position of the defective pixel based on the nine neighboring pixels of the
same color. The algorithm designed adds a two pixel border of the value 127 (for 8
bit image). The border will enable searching for defective pixels at edges and corners
all with the same algorithm. The downside to using a border with xed values is that
defective pixels towards corners and edges gets a value that is not based on the values in
the vicinity but rather a xed value, which can lead to a somewhat strange color for that
pixel.

Multiple Pixel Defects

An image exposed to high levels of noise is prone to have situations where a defective
pixel has a defective pixel as its neighbor of the same color. The adaptiveness of the
proposed algorithm will detect this and treat it accordingly by ensuring that no defective
values are used in the calculation of a pixel.That is accomplished by having the detection
and correction done in separate steps by searching through the image and marking all the
positions that are defective. The correction algorithm can then correct values based for
every position that is defective while still not utilizing values that are agged as defective.
In the case of a defective value being a target for calculation of another defective pixel,
the rst defective is replaced by the number 127, which is the middle value for 8-bit
values.

2
1.1.3 Programmable Threshold
In order to classify any pixel as defective they need to be compared with their neighbors
of the same color.The detection algorithm, therefore, needs to know the highest and
lowest value of the neighboring pixels, excluding the value of the pixel in question, in
order to ascertain whether or not the position should be classied as defective. The
threshold [30] is the value that is added to the highest value and subtracted from the
lowest value in order to produce an acceptance range of values that are considered to be
not defective. Having a value falling outside this range will require the pixels position
to be classied as defective. Dierent images may require dierent threshold in order to
produce the best result. That is why the threshold variable can be altered in the vhdl le
package. An image with high contrast has large dierences between closely related pixels
without the pixels being defective while a low contrasting image does not have such large
dierences.The programmable threshold is designed to account for dierent images being
processed with dierent thresholds.

1.2 Motivation
Being able to correct defective pixels from an image sensor with defective values has the
benet of being able to sell image sensors with defective values that would otherwise have
been rejected by test procedures. It will also enable the correction of defects that occur
only after some time and so make a more robust device as far as errors are concerned.

1.3 Objective
This project aims at producing a system that can detect and correct defective pixel values
from an image with all the signal processing is done in hardware. A software system is
required to read values produced by the processing unit. The resulting image will have
to be interpreted visually by a human eye and by the means of statistical values in order
to ascertain the algorithm's ability to correct pixels. The resulting image will be a more
esthetically pleasing version of the noise degraded input image with fewer visual pixel
defects.

3
Chapter 2

System

2.1 Xilinx ML501

Figure 2.1: Xilinx ML501 development board

Xilinx ML501 is an evaluation board with a vertex 5 fpga and a soft core microblaze pro-
cessor. It has built in DDR2 memory and system-ace to communicate with the compact
ash card, and serial communication using the rs232 protocol. It has an LCD display
and pushbuttons and LED lights as general purpose I/O. It also has input and output
capabilities as far as audio and video are concerned. This project merely utilized a few
of its features.The name of the physical pins on the board are specied in [26].

4
2.2 Microblaze
Microblaze is a soft core cpu using Harvard Architecture on the evaluation board. It
contains separate data local memory bus (dlmb) and instruction local memory bus (ilmb)
in addition to a processor local bus (plb) for connecting the cpu to peripheral components.
The system can be customized by adding peripheral units with dierent functionality in
order to tailor a system to specic needs. The cpu model used in the system includes some
peripheral units like the system ace controller, vhdl design, rs232 and interrupt controller.
The system ace controller is an interface for communication with the compact ash card
using read and write commands.The vhdl peripheral contains the vhdl les that actually
do the correction processing of defective pixels. Those values are then stored in a register
that is accessible by software functions.The next section will explain the methods in the
system ace interface and the storing of values from the vhdl peripheral. The interrupt
controller relays any interrupt from a peripheral to the cpu so it can execute its interrupt
service routine. The rs232 is the default standard input and output for the processor,
but it will not be utilized in this project as a debugging tool.

2.2.1 Creating an embedded system with platform studio

The Xilinx platform studio has a feature called the base system builder wizard that greatly
simplies the task of creating an embedded system to interact with the fpga as it asks
for the dierent parameters in the system and then produces templates and drivers for
the system [31, 32].The wizard will ask where the project is to be placed on the disk and
the name of the system. Based on those inputs it creates a folder with all the necessary
les for the project.The various postxes for the les in project directory can be found
in [20]. The wizard then asks if the designer would like to specify a custom board or to
use an already made development board in the list. The project used a Xilinx ml501 as
is evident in gure 2.2.

Figure 2.2: Choosing a board

The wizard will oer the option to make the processor as a stand alone system or as

5
one of many processors in a system. The next step in the wizard is specifying the clock
frequency at which the cpu is to operate.There may be some limitation for the frequency
for certain peripherals as they may need a certain frequency. Here, the option to add
some memory to the processor is also available that can be turned into cache memory
for the processor.This project will stay with the default 125 MHz frequency and 8 KB of
local memory for instructions and data.

Figure 2.3: Choosing peripherals

Figure 2.3 shows how dierent I/O units can be added to the plb bus and also internal
peripherals can be added to the cpu.The external I/O devices communicate with recourses
on the board like the LED and the push buttons, in addition to resources o the chip like
ethernet, and rs232. The application screen shown in gure 2.4 lets the designer choose
what memory to run the built in tests o of and also the standard input and output for
the system. This project does not have any external memory, so all instructions for the
cpu are stored in local block ram inside the fpga.The RS232 serial connection is default
as the standard input and output. It will remain in the system to fulll its duties but
it will not be used for printing status messages as the computer used does not have an
RS232 serial port.

6
 Figure 2.4: Applications

The wizard is now done with all the information it needed to set up the system and
after some waiting time the screen will show what is in gure 2.5, which is the home
screen of the system with information on the hardware connection as well as the soft-
ware les.The applications tab shows the two default projects TestApp_Memory and
TestApp_Perppherial that were created by the wizard. These two projects can be used
to run a test on the system so to ensure that it the hardware can communicate with the
software correctly for both the memory and the connected peripheral units. The "Ports"
tab in the gure shows all the internal and external ports associated with the cpu's ad-
dress space while the "Addresses" tab shows the address range of all the peripherals
connected plb bus.

7
 Figure 2.5: Base System Builder Complete

It is now time to download the two created test projects to the fpga, one by one, to make
sure that the cpu can access the connected peripherals. The rst step is to go to the
software tab in the main window to "generate libraries and dsp". That will create the
libraries with functions that are associated with the peripherals in the system. It is then
time to make this project the default project for initializing the bram on the fpga, which
means that the data in this project will be placed in the block ram for instructions so
that the cpu will execute those instruction when it is turned on. The software source
code has to be compiled with the "build project" command.The result of compiling the
source is an executable le. The "generate netlist" command reads the executable le and
generates an vhdl description of the components in the system and then runs synthesis
on those les while the "generate bitstream" takes the netlist les and creates a bit-le
that contains the entire embedded system.The bit le is the same format that is used to
program an fpga.The software source les needs to be injected into the bitstream in order
to get the cpu to execute those instructions. The bit le is complete when the software
has been injected into the bit le, and can be downloaded to the fpga with the Impact
tool.The Impact tool can program the fpga by creating an ace le or by using a cable to
the fpga. For this project it will create an ace le from the bit le which in turn is copied
into the compact ash card at address 6. All that is left is to insert the compact ash
card into the card reader on the board, power it up, and select the ace le at position
6 as the source le for the cpu. Running the TestApp_peripheral will do a test of the
connected peripherals e.g. printing strings to a computer connected to the rs232 serial
port or ash the LEDs if they are connected.

8
2.2.2 System Ace Controller
The system ace controller is an interface between the compact ash card and the processor
local bus. It makes sure that the plb bus and the cf card can communicate and that the
timing is correct.The controller and all its specications are given in [29]. The library
generated for the system ace controller contains functions to read from the device and
write to the device. There is, however, a library called xilinx xilfatfs [28] that further
simplies the interaction with the cf card by the means of functions to open, read, write
and close a le. The functions available using the Xilfatfs library, for interacting with the
compact ash card, are:

sysace_fopen (le, mode)

sysace_fread (buer,size,count,le)
sysace_fwrite (buer, size, count,le)
sysace_fclose (le)
sysace_mkdir (path)
sysace_chdir (path)
Interaction with the cf card requires that certain steps are done in the correct order.
The rst step is to make a directory where the le should be located and then open the
le in read or write mode, depending on what is the desired operation. The directory is
specied using the sysace_mkdir command while opening a le in write mode is done
with the sysace_fopen(le, 'w') function. It is now ready for communication with the cf
card using the sysace_fwrite function (assuming that the le was opened in write mode).
Upon completion of writing the data, the le has to be closed using the sysace_fclose
function. The function sysace_fread is used when the target le is opened in read mode,
and the sysace_chdir is a function to change a working directory.

2.2.3 RS232
The rs232 protocol is a communication protocol for serial communication with one trans-
mitter and one receiver. The signals used in the communication can be seen in [24] along
with the parameters used to setup communication between two participants. Platform
studio oers a version of the rs232 called uart lite that only contains the receive and
transmit pin as external pins from the chip.This has the added benet of not requiring
knowledge of the entire rs-232 protocol in order to initiate communication. Uart lite is
also the default std_in and std_out for the cpu. This module can be used for printing
status messages to a connected computer so it is in fact a debugging tool for the software
platform.A serial communication contains several parameters that must have the same
values on the transmitter and the receiver side for the receiver to decode the message
correctly. Parameters that need to be specied are the stop bit, start bit, baud rate and
parity. The start bit is a message to the receiver that the rst bit of the message is being
transfered.This is based on the protocol being asynchronous and therefore used the start
bit to synchronize with the transmitter. The start bit will therefore synchronize receiver

9
and transmitter. The stop bit denotes the end of the message and acts as a resynchroniza-
tions tool if the receiver, for whatever reason, did not receive the start bit and therefore
not the message. The parity bit is an error checking tool where the transmitter generates
a bit value that the receiver can use to determine whether it received the same message
that was sent.

2.2.4 Interrupts
There are two basic methods for a peripheral to let the processor know that it needs
attention;polling and interrupts. Polling is a method where the processor will ask the
various peripherals if they have any data for the processor. It will ask each peripheral
every time period. This method can work great for systems that only operate on data
from peripherals, but will not be such a great choice if the data from the peripherals is
not essential for the processing at all times.This system will only act on the data from
the interrupts, but it was chosen to use an interrupt controller in order to gain experience
with setting up and handling interrupts. Xps oers an interrupt controller that relays
interrupts from the peripherals to the cpu. It is connected to the cpu's interrupt port,
on one side, and the interrupt signal from the peripheral on the other side. Interrupt
based systems are methods where the peripherals will tell the processor when it needs
attention and thus only take up processing time when it needs to communicate with the
cpu. Good tutorials for creating interrupt based systems can be found in [14, 27].
The system implemented for this project utilizes an interrupt based processor so that it
receives an interrupt from the vhdl peripheral that it wants attention, and the processor
will go into its interrupt service routine (isr) to execute the instructions for that inter-
rupt.When an interrupt "res", the processor will store its current values and go into
its isr. When the processor completes its isr, it will load the values it had prior to the
interrupt as to continue execution where it left o before the interrupt.

Interrupt Controller

The vhdl peripheral will set the interrupt ag of the interrupt controller when it needs
to communicate with the processor. One interrupt line can be directly connected to the
processor's interrupt port, but having multiple interrupt lines requires the implementation
of an interrupt controller that can act as an arbiter to make sure every interrupt gets
serviced. It will act as a decoder for interrupt lines for various peripherals as the processor
has only one interrupt port.The interrupt controller can relay information to the cpu of
the peripheral that triggered an interrupt so the correct isr is executed. When a peripheral
sets the interrupt ag high, that will signal to the interrupt controller that it wants to
communicate with the processor and the interrupt controller in turn sets the processor's
interrupt line high.This is the message to the cpu to go into the isr of the source of the
interrupt. The specications of the interrupt controller can be found in [33].

10
Interrupt enabling

When setting up interrupts on a processor it is essential that they are set up correctly
on all devices that set, handle and relay the interrupt. It needs to be enabled on the
peripheral, interrupt controller and in microblaze in this situation. It is also important
that the interrupts are acknowledged on the peripheral and the interrupt controller before
de asserting the processor interrupt line to low.This is to avoid a situation where an
interrupt is never acknowledged and is therefore blocking all other instruction to the cpu
as the cpu will think the peripheral is asking for a new interrupt and go into its isr again.

Interrupt service routine

Isr is the instructions that are executed every time a given peripheral triggers an interrupt.
Dierent peripherals have dierent isr that are executed. It is therefore imperative that
the source of the interrupt is found so as to ensure the correct isr is being executed. On
this project the vhdl peripheral will assert the interrupt signal on the bus and then it is
sent to the interrupt controller that will relay the interrupt to the processor.

2.2.5 Creating an intellectual property

Xps has a wizard for creating peripherals that can be connected to the cpu in such a
manner that the designer does not need to know the specics of the bus protocol in
order to access data on a peripheral but can rather communicate on the bus using a few
signals.Tutorials on how to create an custom IP and utilize its features can be found at
[1, 25]. Figure 2.6 shows the start of the guide where the designer can choose to create
a template for a custom peripheral or import an already-made peripheral. Choosing
to create a template results in the wizard creating the vhdl wrapper les that enable
communication between the custom ip functionality and the plb bus. Once a peripheral
is created and the default vhdl les created by the wizard altered, the peripheral has to
be imported back into xps with the new changes in order to get a custom ip with the
desired functionality.

11
 Figure 2.6: Create Custom Peripheral guide step 1

The ipif screen shown in gure 2.7 is where the designer will choose what modules to
be implemented into the peripheral. The ability to have read and write fo, interrupts,
memory space or register space can all be specied in the ipif section.This project will
utilize an interrupt mechanism for the peripheral to communicate to the cpu that it needs
attention and it will include the default checked boxes in the "user logic software register"
and "include data phase timer".

Figure 2.7: Peripheral interface

The user logic software register was chosen by the designer so a determination has to
be made as to how many software accessible registers the peripheral should contain.
These registers are named slv_reg0slv_reg(N-1) for N specied registers. It can been
seen from the vhdl le user_logic that it species how to read and write to any of the
accessible registers.

12
 Figure 2.8: Interupt service

The next step is specifying the number of interrupts needed in the system and also if
the interrupts should be captured as inverted, low level or high level. The wizard will
create signals in the user_logic le that is connected to the interrupt signal on the plb
bus. The interrupt mechanism can therefore be accessed by assigning a signal within the
vhdl module. By opting for the user logic register in gure 2.7, the number of registers
is specied in gure 2.9. The number of registers chosen can be seen in the user_logic
module with each register having a signal assigned, in order for functions in software to
read from the registers and write to the registers.

Figure 2.9: Peripheral registers

13
The ipic is the tab where all the signals from the ipif module to the user_logic module
are specied, also with the option of checking a new signal that the designer may opt to
use. The signals in the tab are shown in gure 2.10.These signals represent a simplied
version of the plb bus signals. The signals will be utilized in the peripheral in order to
communicate with the ipif that in turn communicates with the plb bus.

Figure 2.10: Peripheral Interconnect

The hierarchy of the custom peripheral is shown in gure 2.11 with the peripheral being
the top level module with the ipif module on the level below and the user_logic module
on the lowest level.There are options for the wizard to create ISE project les for the
peripheral and also to make templates for the driver of the peripheral. The created ISE
project facilitates easier importation into platform studio as the les can be synthesized
prior to being imported.

Figure 2.11: Peripheral hierarchy

The custom peripheral wizard has now created the two vhdl les as a wrapper for the
peripheral. The les are called my_custom_ip_register.vhd and user_logic.vhd where

14
my_custom_ip_register.vhd is the wrapper for the ipif while the user_logic is the le
where the designer can add functionality given the set of signals shown in gure 2.10.
These les are located in the pcores folder in the working directory. The folder contains
all custom ip modules created by the wizard.

Figure 2.12: Import peripheral complete

The newly created custom ip is located in the IP catalog under user cores and must
now be added to the project and have a connection to the plb bus established. The
only step left then is to go to the address tab in order to assign an address range for
the peripheral so that the processor can communicate with it. The hardware part of
connecting the peripheral is now complete but the designer still needs to run the "generate
libraries and dsp" command from the software tab in order to create the new libraries
with the functions that are associated with the custom peripheral. When the libraries
are generated the software will recognize the functions associated with the peripheral.

2.2.6 Access Peripherals

The cpu has a memory map that indicates which addresses belong to which peripheral.
The memory map is a division of the total memory of the cpu divided by the dierent
peripherals and their memory needs so that every unit can be accessed by using those ad-
dresses.The various peripherals may need dierent space allocated in the memory so they
will thus have narrower address ranges. The Xilinx Platform Studio makes this memory
map an automated feature so the user does not need to specify anything other than the

15
memory needed for each peripheral. There are two variables that are important when a
peripheral is to be accessed; the base address and the high address. The base address
is the starting address for the peripheral and the high address is the end address of the
peripheral. Both addresses are given in hexadecimal numbers.The example given in gure
2.13 illustrates the dierent peripherals in the system along with their base address, high
address, memory size and connection to the bus. The modules all have header les that
describe the methods that are associated with that peripheral and also the oset to the
dierent registers within a peripheral. Within the custom peripheral there are methods
for reading from a register, writing to a register and setting up interrupts.

Figure 2.13: Microblaze address map

The cpu can access the system ace controller using the address range from base address
to high address. The size of the address space can be determined by subtracting the
base address from the high address. As an example the high address of the system ace
controller is 0x8360FFFF and the base address is 0x83600000. Subtracting the base
address from the high address leaves us with the address space in bytes. The address
space of the system ace controller is 65536 or 64k.The amount of memory is also shown in
the address map in order to simplify the calculation of the amount of memory for a given
peripheral.The header le of a given peripheral species what the dierent addresses of
the peripheral will accomplish.

2.2.7 Adding c source le

Creating a new c source le for a project is done by clicking on the sources tab and the
select "add existing le or add new le". This will create a new le to one of the two
processes created by the wizard.The c code will be executed by the cpu if the process
it belongs to is set to initialize the block ram.The le is accessible from the "sources"
menu in that process. Utilizing functions from a peripheral requires that its header le
is included at the start of the c le and also added to the "header" menu in the process.

16
Chapter 3

Supporting Theory

This chapter will contain the information needed to understand the techniques used in the
project, and evaluate the results of the algorithm for detecting and correcting defective
pixels in an image.

3.1 Median Filter

This thesis employs a median algorithm for correcting pixels that are classied as defec-
tive. The algorithm will then gather the values of the eight neighbors of the same color,
and assign the median of those values as the new value at that position. Figure 3.1 shows
some values that will be used to explain the operating procedure of the median lter.
Let's assume that the threshold for detection is 10. That means that any value higher
than threshold + the highest value, or lower than threshold - lowest value is classied as
defective.
 .. .. .. .. .. 
. . . . .
 . . . . . . 114 115 102 92 72 . . . . . .
 
 . . . . . . 140 115 128 111 121 . . . . . .
 
 . . . . . . 100 101 127 103 113 . . . . . .
 
 . . . . . . 141 201 90 131 61 . . . . . .
 
 . . . . . . 117 119 99 97 120 . . . . . .
 
.. .. .. .. ..
. . . . .

Figure 3.1: Truncated Original Image Values

The rst step with this algorithm is to calculate the maximum and minimum values not
including the pixel in question.The values chosen for the middle pixel in ascending order
are {72 99 100 102 113 114 117 120 127}. The extreme values, not including the mid-
dle pixel, are 72 and 120. The middle pixel will be classied as defective when using a
threshold larger than 7 and classied as a working pixel with a threshold lower than 7. In
this instance it is assumed that the threshold is such that the middle pixel is classied as

17
defective. Next step in to replace the defective value with the median of the neighboring
pixels of the same color. In this example the median is 113.
 .. .. .. .. .. 
. . . . .
... ... 114 115 102 92 72 . . . . . .
 

... ... 140 115 128 111 121 . . . . . .
 

... ... 100 101 113 103 113 . . . . . .
 

... ... 141 201 90 131 61 . . . . . .
 

... ... 117 119 99 97 120 . . . . . .
 
.. .. .. .. ..

. . . . .

Figure 3.2: Resulting Truncated Image Values

3.2 Types of Noise

In the previous sections the main focus has been on detecting and correcting defective
pixels. The appearance of a defect pixel can be seen as noise when put under scrutiny
from an observer. It is therefore possible to model a defective pixel as noise on a test-
image in order to conclude which algorithm produces the most esthetically pleasing image
when removing the noise. There are two dominating sources of noise in an image; salt
and pepper noise and Gaussian noise. The next section will describe them in detail.

3.2.1 Salt and pepper noise

Salt and pepper noise is a somewhat typical noise seen on images with defective pixels. It
manifests itself as white spots (salt) or black spots (pepper) on the image [19]. A white
spot is caused by a false saturation on the image sensor while the black spot is caused
by a failed response of the same image sensor. These defects are usually the result of
an error on the fabrication of the image sensor. It can be modeled in matlab were a
value (typically 0.01)will determine the probability that a given pixel is corrupted with
noise and so interpreted as either a black or white pixel. Statistically this kind of noise
has zero mean value and is, thus, described completely by its variance. This kind of
noise can be successfully removed based on the understanding that the corrupted pixels
will have a very high or very low value. As such it will stand out in comparison to its
neighboring pixels, assuming that they work correctly, and the removing lter does not
need to be very complex, although a very good reconstruction of an image still requires a
degree of complexity in the algorithm to deal with dierent contrast in the same image.
Figure 1 shows an original Lena image [15] and 3.4(b) shows the same image corrupted
with salt and pepper noise. The algorithm presented in this thesis will start with an
image corrupted by noise and then manipulate it to get as close to the original images as
possible.

18
 (a) Lena (b) Lena corrupted by salt and pepper
noise

Figure 3.3: Impact of salt and pepper noise

3.2.2 Gaussian Noise

Gaussian noise is a noise type that can corrupt pixels with any value within the range of
values [11]. Some pixels may be slightly altered while others may be severely altered, thus
making the job of detecting and correcting them far more dicult. This type of noise can
be added to an image when it is transferred over a noisy information channel. As it is not
the scope of this project to remove Gaussian noise, it is only serves the purpose of adding
to the understanding of how dierent noise sources corrupt an image. Gaussian noise has
a probability density function (pdf) that describes the probability of a value being within
a certain range (see equation (3.1)).The Gaussian noise also has a zero mean value and
is described by its variance.
1 2
F (x) = √ e−(x−µ) /2σ
2
(3.1)
σ 2π
In equation (3.1) µ is the mean value and σ is the standard deviation. For a normal
distribution the µ is zero and σ is 1.The fact that pixels corrupted by Gaussian noise
can have any value makes them harder to detect and correct in the time domain. They
may not stand apart from the neighboring pixels, like with the salt and pepper noise,
but rather be assigned random values to random pixels.Figure 3.4 shows the impact of
Gaussian noise on an image alongside the original image.

19
 (a) Lena (b) Lena corrupted by Gaussian noise

Figure 3.4: Impact of Gaussian noise

3.3 Images
3.3.1 Histogram
Most modern digital cameras have the option of displaying the histogram of the image
along with the image itself on the screen of the camera. The histogram is a graphical
representation of the exposure with regards to the balance of highlights, mid-tones and
shadows [13]. Having few components in the shadow-or-highlights will result in an image
that is over exposed or under exposed. A perfect exposure will have components in all
the three regions in a histogram. Using an 8-bit image will result in a histogram in the
range of 0255(sometimes expressed as 8 F -stops). Figure 3.5 shows the dierent tones
of an image with its corresponding grey-level range. Looking at the histogram it can be
concluded that the image has all its components within the mid-tone and shadows area
and as such does not have any highlight components. The rectangular bar at the bottom
represents the grey scale with color level and corresponding pixel count.

Figure 3.5: Image histogram

20
3.3.2 Contrast
A histogram contains several important aspects that will tell a photographer how the
dierent components within the image relate to one another. There are, however, other
measures that can be read from the histogram such as the overall contrast of an image and
exposure. The contrast is the ratio of the largest component and the smallest component
of the histogram. A small ratio, corresponding to a narrow set of values on a histogram,
will cause the image to have a low contrast. Having a large ratio will result in a high
contrast image.

(a) High Contrast (b) Low Contrast

Figure 3.6: High and Low contrast histograms

3.3.3 Bayer Color Filter

The Bayer color lter [4] is used for arranging colors on a square image sensor. It consists
of 50% green, 25 % blue and 25% red.The green color is usually divided into green for
red and green for blue so that it really is composed of four dierent colors. Since it has
more than twice as much green values as red and blue combined, it is sometimes called
RGBG or RGGB. The correction algorithms need to evaluate only pixels with the same
color for any given position which is done by looking at pixel (i± 2, j± 2) assuming that
the middle pixel is at position (i,j). The Bayer values are light intensities of red, green,

Figure 3.7: Bayer Filter [5]

and blue from the image sensor. It is the job of the processor to convert these light
intensities into pixel values in order to obtain a RGB image, which is done by looking at
the intensity of the neighboring pixels. Each intensity can range from 0 to 255 in an 8
bit image thus resulting in 16.7 million possible combinations. It can be observed that
the next neighbor of the same color is two pixels up, down, left and right so that will
dictate how the search for neighbors will go on.This pattern will be utilized in the vhdl
part in order to nd the next neighbors of the same color to be able to classify a pixel as
defective.

21
3.3.4 PGM Image Format
PGM image formats [18] is an abbreviation for P ortable Gray M ap where the pixel
values indicate a light intensity. An image with 8 bits per pixel will result in 256 dierent
levels from black to white. The interesting aspect of PGM image format is that there is
no data compression so the pixel values can be read directly from the image. The le
format consists of a le header and the image data. The header consists of a number P1-
P5, the size of the image in the x and y direction, and the maximum value. An example
PGM le showing the number eight looks like gure 3.8.

P2
5 7
15
0 0 0 0 0
0 15 15 15 0
0 15 0 15 0
0 15 15 15 0
0 15 0 15 0
0 15 15 15 0
0 0 0 0 0
Figure 3.8: Example PGM le format

3.4 Number representation

There are several ways of representing a number with the decimal system begin the
predominant system. In scientic research there are situations where using the decimal
system would be inecient, e.g representing large memory spaces.The hexadecimal scale
is used when dealing with cpu address spaces while the logarithmic scale is used in
measuring decibel in an audio visual system.

3.4.1 Hexadecimal scale with base 16

The hexadecimal number system [12] is a positional system with a radix or base of 16.
There are then sixteen distinct values in the hexadecimal system where 0 − 9 is the same
as the decimal 0 − 9 and A − F represents decimal 10 − 15. The hexadecimal number
3CB is equal, in decimal, to (3 ∗ 162 ) + (12 ∗ 161 ) + (11 ∗ 160 ) = 971. A hexadecimal
number is often denoted by a 0x number as a prex or as a postx number16 . The use
of an identier is to avoid ambiguity with the number as the decimal number 14010 is
not equal to the hexadecimal number 14016 . Figure 3.9 shows the dierent hexadecimal
numbers along with their decimal value and its binary value.

22
 Hex Decimal Binary
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
A 10 1010
B 11 1011
C 12 1100
D 13 1101
E 14 1110
F 15 1111

Figure 3.9: Hexadecimal number representation

Hexadecimal numbers can be broken down to a binary representation by replacing each

number by its binary representation according to gure 3.9. Hexadecimal numbers are
used in this project for representing addresses in the address space of the cpu. An address
can have the value 0x2F, where the prex denotes that it is a hexadecimal number. The
number 2 is replaced by the binary representation of 2 (0010) and the F is replaced by the
binary representation of F (1111).The binary representation of 0x2F is therefore 00101111
but the leading zeros in a binary representation can be skipped so the resulting number
is 101111.The hexadecimal representation can be used to represent large numbers with
fewer digits than its binary and decimal representation.

3.4.2 Decibel scale with base 10

The logarithmic scale [16, 9] used the logarithm of a value instead of the value itself. The
value 100 is replaced by 3, as 3 ∗ log10 is 100. There are dierent bases, or radix for the
logarithmic scale but for measuring decibel (dB) the base 10 is used for the calculations.
Large values become more manageable when using the logarithmic scale. Humans hear
in a logarithmic scale, so that is why it is extensively used to measure the quality of
an audio systems. The decibel values will be used when measuring the peak signal to
noise ratio in the simulation chapter. The formula for calculating a decibel value is in
equation (3.2), where p0 and p1 are the measured values from inp ut to output.
Po
[H]dB = 10 ∗ log10 ( ) (3.2)
P1
An increase in decibel from 4 dB to 5 dB represents an increase from 2.51 to 3.16 in real
value. Having zero decibel from a system means that the output and the input have the

23
same physical value. If the fraction P0 /P1 is larger than one, the resulting decibel value
is positive while it is negative if the fraction is less than one [8].

3.5 Text representation using ascii

Ascii is the abbreviation for American standard code for information interchange [3, 2] and
is a numerical representation of the alphabet.This is useful as a computer cannot interpret
a character but rather the ascii value of the character.The initial ascii setup contained 127
characters and thus required seven bits in order to represent all possible combinations.
Most of these characters are printable characters like letters and numbers while some
characters are non-printable but these are mostly now being considered obsolete.An upper
case letter and a lower case letter do have dierent representation in the ascii coding
scheme. Having more bits available introduces more possible symbols to be represented
in order to include special letters from dierent languages. [3] shows the 256 symbols
that are represented by 8 bits.The word t-e-s-t is interpreted by a computer as 116-101-
115-116 using an 8 bit ascii table.

3.6 Measured Values

When comparing two images, there are several values that describes the image. The next
section will show the measures used in this project.

3.6.1 Mean Square Error (MSE)

m−1 n−1
1 XX
M SE = (I(i, j) − L(i, j))2 (3.3)
mn i=0 j=0

Equation (3.3), used for images, measures the squared dierence between the recon-
structed image and the original image. The reconstructed image will not be pixel wise
identical to the original image and this method measures how far they are apart in
squared value [21]. I(i,j) is the value of the reconstructed image while L(i,j) is the value
of the original image. Lower values of mse will translate into a better quality image (see
equation 3.5).

3.6.2 Mean absolute error(MAE)

The mean absolute error [17] shows how the values of the reconstructed image compare
to the values of the same pixel in the original image and averages that value. Equation

24
(3.4) shows the formula for calculating the mean absolute error. 3.4
m−1 n−1
1 XX
M AE = |I(i, j) − L(i, j)| (3.4)
mn i=1 j=1

3.6.3 Peak signal to noise ratio (PSNR)

Peak signal to noise ratio indicates how the maximum signal power compares with the
maximum noise power for two images. It is a measure to tell how much an image is pixel
wise altered from its original. It is therefore a good measure to determine the quality of
the reconstructed image compared to the noise free image [34]. The higher value of psnr
translates into a better image quality when comparing two images.
 
2 k2
 
M AXi 2  (3.5)
P SN R = 10 log10 = 20 log10  q P
M SE 1 m−1 P n−1
|I(i, j) − L(i, j)|2
mn i=0 j=0

In the equation above the m and n are the size of the image matrix, I and J are the two
images to be inspected and k is the number of bits used to represent the image.

3.6.4 Real time constraints

Modern DSLR cameras have the ability to expose multiple frames in a sequence within a
short time frame, and those cameras are said to have high frames per second (fps) rate.
The task of correcting defective pixel's from those types of camera introduces a time
constraint criteria in order to keep up with the new frames shot. Exposing 30 frames
per second means that each frame takes 33 milliseconds to complete. The correction
algorithm should therefore utilize a fraction of the time of the frame itself in order to be
ecient. Utilizing a correction algorithm will inevitably lead to a slower fps rate but that
may be a tradeo worth doing if the images come out with a noticeable lower noise level.

3.7 TextIO vhdl package

The textIO is a vhdl package that enables reading from a le and writing to a le when
running a test bench in simulation in software. Values from the simulation can be stored
in a le in a pre-determined location and the simulation can get its values from a le and
then use them in a test bench. This is a useful tool in order to specify multiple input
values without the hassle of having to write every value in a vhdl le.The package reads
one line with the "readline" command. The line is then stored in a variable that has to
be split up if there are multiple values in a line.The "writeline" command writes a value
from a variable to a line. That line is written to the le with the "write" command. The
directory of the pre and post x of the le are specied using the "FILE" command along
with the operating mode (read / write).

25
Chapter 4

Architecture

This chapter will introduce the modules that makes up the system for correcting defective
pixels in a vhdl peripheral and also the modules used in conjunction with the cpu. The
top level module is microblaze with the vhdl les that does the processing as a peripheral
to that cpu. The cpu will read a value from the register inside the vhdl peripheral each
time an interrupt res and store the value on the cf card.

4.1 VHDL Architecture

Figure 4.1 shows the hierarchy of the vhdl les that does the processing with the ctrl
module as the top level module but it should be noted that the user_logic.vhd is on
a higher hierarchical level than the ctrl module and the my_custom_ip_register.vhd
as the top level vhdl le for the entire peripheral. The my_custom_ip_register.vhd is
the interface from the bus to the user_logic.vhd where the signal mapping of the ctrl,
image_core, median and size modules takes place.

ctrl package
size

Median
image_core

Figure 4.1: Vhdl le hierarchy

26
4.1.1 Size Package Module
The size package contains variables that are used by the various modules of the system.
The reason for using a package is to avoid having to declare the same variables in all the
modules, in addition to making it easier to change a value as it only needs to be changed
one place. The values are accessible for the modules that implement the package. These
values are shown in gure 4.2 where the "size_x" and the "size_y" are the size of the
image to be corrected with the "th" being the threshold value used in the classication
of a defective value. The "bits" variable is the number of bits per pixel. Eight bits per
pixel is equivalent to 256 levels. "Bit_depth" is merely two to the power of bits. (28 =
256). The "data" is an array that contains the values of the image and those values are
converted from the image to an array of the values of the image in such a way that vhdl
will recognize the array of values and be able to read those values.

bits
bit_depth
size_x

Size package size_y

th
data_array

Figure 4.2: Size package

4.1.2 Median module

clk
done
rst median
enable
data_in Median
module

Figure 4.3: Median Module

The median module is the module that calculates the median of any given array, with
its input and output signals are given in gure 4.3. The enable signal will cause the
state machine to make a transition from "idle" state to the "read_values" state and the

27
signal also denotes that a new input value is present at the input. That value is stored in
an array called "data" at the position indicated by the "packet_counter" variable. The
next state is the "idle" state where the state machine will wait for more values. When
all the values have been stored in the "data" array, indicated by the "packet_counter" =
8, there will be a state transition to the "start" state. This state is the starting state for
the double for-loop that will go through all the values in the array and swap two values if
the value at "index" is larger than the value at ("index" +1).The "count" variable is that
is incremented by one each time a value at "index" is smaller than the value at "index
+1 and so does not need to swap place. When the for loop can go through the entire
array without swapping any values, that is an indication that the array is in ascending
order.This happens when the "count" variable is equal to 8. At that point the next
state is "three" where the done ag is set high and the median value set to the value of
position 4 in the nine value array. Figure 4.4 shows a graphical representation of the
state machine built for this median module along with the signals that will cause a state
change.The actual vhdl code for the median module can be found in section .1.1

reset
enable = '0'

idle
enable = '1'
packet_counter /= 9
three read_values

twoindex =8 start
packet_counter = 9
count=8

index /=8
one

Figure 4.4: Median module state machine

4.1.3 Image_core Module

clk core_out
rst do
mod_en
core_in Image_core
di module

Figure 4.5: Image_core Module

28
The image core is the module where all the processing on the image is done. Its input and
output signals are shown in gure 4.5.The state machine for the image_core is starting
in the "idle" state where it will assign the data out (do) ag to low while waiting for the
mod_en signal to be high. Then the next state is "read_values" where the values are
inputted serially and stored in an array called bayer_array. The values are stored as if
they where from an image sensor in order to duplicate the reading pattern [23]. These
are the values from an image so the size of the bayer_array is the same as the size of
the pixels within the image. The values are stored in such a manner that it corresponds
to the way data are read from a bayer image sensor.The transition to the next state
happens when all the values are in their correct place in the array, and the next state is
"padding127". This is a state where a new array is created, with the sizes in the x and
y direction being four pixels larger than the bayer_array. All the positions are assigned
with the value 127. The next state is the data_mapping state where the original values
in the bayer_array are mapped into the new array in such a way that the values in
the bayer_array are surrounded by a two-pixel border of the value 127. The reason for
adding this border is to be able to use a single algorithm to go through the entire image
including edges and corners as corners and edges are lacking some neighboring pixels of
the same color. The next step is to nd the defective values in the image one-by-one,
and that is done in the "nd_defects" state. The way a pixel is classied as defective
is that its value is higher than the threshold value plus the highest of its neighbors or
lower than the threshold value minus the lowest of its neighboring values. A defective
pixel will be assigned a '1' on that position in the pixel_map, which is an array with
the same size as the img_array but where all the positions have the value 0 or 1.The
reasoning for doing detection and correction in two dierent steps is to avoid using the
value of a pixel at a defective position as a basic for a new value. The correction takes
place in the "correct" state by going through the pixel_map and selecting the positions
that have a '1' entry. Then an array is composed with the values of the neighboring pixels
of the same color. If one of those values are at a position that is classied as defective,
the value 127 is assigned in the array instead of the defective value.The array of the
neighboring values are sent to the median module serially by assigning the enable signal
to high and assigning values of the array to the data_in port of the median module. The
above mentioned procedure is done on all the locations that are classied as defective.
The last step in the "correct" state is to wait for the median module to produce its result
and assign the new value to the correct location in the array. Since the two pixel border
is there just for aiding the algorithm with searching for defective values in corners and
edges, the border values are removed in the "de_mapping" state. The corrected values
are mapped into the bayer_array where they will be assigned to the output of the module
in the "read_out" state. The values are assigned to the core_out port along with the
data out (do) signal set high when a new value is assigned. Upon completion of assigning
all the values to the output the state machine is done with the image in question and set
into the "idle" state.The graphical representation of the state machine can be found in
gure 4.6 and the vhdl code is in section .1.1.

29
 reset

mod_en = '0'
mod_en = '1'
idle readvalue x_cor = size_x -1
x_cor = size_x-1

read_out padding127

de_mapping data_mapping

a = size_x +2
correct f ind_def ects

Figure 4.6: Image_core module state machine

4.1.4 Ctrl Module

clk data_out
rst

Ctrl module

Figure 4.7: Ctrl Module

The crtl module is the top level module in the processing part of the peripheral with its
ports being shown in gure 4.7. It only needs the clock signal to start it's instruction
and its responsible for assigning the correct ags in order to read and write values to and
from the image_core. It consists of a process that assigns values to the image_core and a
process that reads the values from the image_core and outputs them to the output of the
ctrl module.The process that reads values from the array within the size package contains
a small state machine. The "idle" state of the state machine assigns the mod_en ag
high and then makes the transition into the "start" state which is nothing more than a
delay state to get the timing right. The variable sent_count keeps track of the number
of values sent to the image_core, and this value is checked in the state "one" so it can be
ascertained when all the values are sent.The mod_en ag is de asserted in the "one" state
and then it makes a transition to the state "two" where the various values are assigned
to the core_in port of the image_core.The state machine described here can be found in

30
gure 4.8. The second process of the ctrl module reads the values from the image_core
and assigns them to its output.This is triggered when the data out (do) signal from the
image_core is assigned to '1'. The vhdl code for the ctrl module can be found in section
.1.1.

idle

start

sent_count = size_x * size_y

one

sent_count /= size_x * size_y

two

Figure 4.8: Ctrl module state machine

4.2 Note
Even though the vhdl les, shown in gure 4.1, showed correct behavior when simulated it
seems impossible to run synthesis on the les as the ISE synthesis tool runs out of memory
before completing the synthesis. The decision was therefore made, in accordance with
the supervisor, to proceed without running synthesis on the vhdl les. This will make
it impossible to test the system on the fpga so the simulation of the vhdl les will serve
as an indications of the system's ability to detect and correct defective pixel values. The
custom ip module is still implemented in the system but with limited functionality. It will
contain a process for generating interrupts and test the ability to write to a peripheral
register and read from a peripheral register.
The peripheral will show how the ctrl.vhd module can be mapped in the user_logic.vhd
le with its mapping of signals. A successful test will provide evidence that the embedded
system can handle reading a value from a register and store it on a cf card.

4.3 Microblaze
The microblaze system contains both hardware and software that enables communication
between the cpu and its peripherals. The next section deals with the hardware part of
the microblaze system while the preceding section deals with the software part of the
system.

31
4.3.1 Hardware Architecture
Vhdl Peripheral

Figure 4.9: Vhdl Peripheral hierarchy

The xps wizard created the template for the peripheral to be connected to the cpu by
the plb bus. It also created the interface necessary for the peripheral to communicate
with the plb bus signals. The ipif communicates with the plb bus using the entire set
of plb bus signals. The ipic is the interface between the ipif and the user modules and
custom functionality can be added here or custom vhdl module can be mapped from this
module. The vhdl le user_logic.vhd created by the wizard needs to be altered in order
to get the correct functionality where a value is read from a register and stored in a le
on the cf card. The user_logic le has been altered by adding a process that will generate
an enable signal and also the component mapping of the ctrl module. It should also be
mentioned that the user_logic le has six software accessible registers, represented by the
signals slv_reg0slv_reg5. The le also contains both a process for reading the values
of a register and a process for writing values to a register. The process that generates
the interrupt also has a reset signal that will reset the interrupt on the peripheral. The
reset signal reads its value from bit 0 in the slv_reg0 register so writing a 0 to that
position in slv_reg0 resets the interrupt. The le also contains a component mapping for
the ctrl module where the clock and reset signals are mapped from the Bus2IP_Clk and
Bus2IP_Reset that is a part of the plb bus signals. The output signal of the ctrl module
is mapped to a signal called output so the value of the output can be read by reading
slv_reg1.

Connections

The Microblaze system is made up of the components described in section 2 that will
now be connected to the plb bus so their functions can be utilized by some software
on the cpu. The base system builder wizard and the create peripheral wizard described
in section 2 made a system with a block diagram that is given in gure 4.10. The
custom peripheral was given the address range from 0xCCC00000 to 0xCC0FFFF when
the tool generated the addresses. Since there is an interrupt controller in the system it

32
is important that it is connected correctly from the vhdl peripheral all the way to the
processor. The peripheral's interrupt signal is connected to the interrupt controllers Intr
port, and its Irq port is connected to the cpu's interrupt port. The block diagram of the
hardware connections in Microblaze is seen in gure 4.10 where it is apparent that the
interrupt controller, my_custom_ip_register and the cpu share a common yellow mark
on the top right corner that indicates the handler, source and target, respectively, of the
interrupt mechanism.

Figure 4.10: Microblaze Block Diagram

The microprocessor hardware specication.mhs le for the system denes the hardware
components used along with the bus architecture, peripherals, processor ,system connec-

33
tivity and address space [20]. The le is located in the main program directory and can
be found in section .2.2.

Figure 4.11: Microprocessor hardware specication example

Figure 4.11 shows the hardware settings for the interrupt controller with its name,
hardware version, high address, base address, bus interface and ports with the signals
connected to the ports. The user constraint le .ucf for the system species how the
signals inside the fpga are connected to external pins on the fpga. It can be specied
which clock on the chip that is used in a design with the ucf le. The le is stored in the
data folder in the program directory and can be found in section .2.3.

Figure 4.12: User constraint le example

Figure 4.12 show how the vhdl signals fpga_0_clk_1_sys_clk_pin is connected to the
external pin of the fpga called AD8.

4.3.2 Software Architecture

The hardware description and connections of the peripheral are now complete so the
designer can utilize the functions of the peripheral in order to achieve the desired result.
First, let's look at the header les that are of interest for this project, starting with the
xparameters header le (section .2.4) which is the le with the address ranges of all the
components connected to the cpu. The sysace_stdio.h provides functions to read, write,
open and close the compact ash card in addition to specifying the directory of the le to
be interacted with. The my_custom_ip_register.h contains functions for reading data
from the register in the peripheral and functions to write data to the register. The header
les mb_interface.h and xintc.h contains all the functionality to setup interrupts, handle
interrupts and acknowledge interrupts on the interrupt controller and on microblaze.
The functionality of the c source le as based around interrupts so the le consists of an
interrupt service routine and the setup of the interrupts in addition to writing data to
the cf card and reading data from registers within the peripheral.

34
Setting up the interrupts requires that an interrupt handler is registered and the en-
abling of interrupts in all modules that process, send or receive interrupts. Regis-
tering an interrupt handler is done with the "XIntc_RegisterHandler" function found
in the xintc_i.h le which is accessible through the xintc.h le. This is the connec-
tion between the interrupt signal from the peripheral and the interrupt service routine
for that peripheral. Interrupts needs to be enabled in the custom ip, interrupt con-
troller and microblaze so that it can function correctly. It is set up in the interrupt
controller by using "XIntc_mMasterEnable" function and the "XIntc_mEnableIntr"
function found in the xintc.h le. The custom ip enables interrupt by using the "
MY_CUSTOM_IP_REGISTER_EnableInterrupt" command in the my_custom_ip_register.h
le. The last step is to enable interrupts on the processor, and that is done with the "mi-
croblaze_enable_interrupts();" command found in the mb_interface.h le.
Every time there is an interrupt, the cpu will execute the same piece of code over and
over again. That code includes functions to setup a le directory, open the le, read the
data from a register and write that value to a le on the compact ash card, close the
le and acknowledge the interrupt on the peripheral and in the interrupt controller. The
specication of a directory is completed by using the "sysace_mkdir" command from
the sysace_stdio.h le. The same le contains the functions sysace_fopen,sysace_fclose,
sysace_fwrite to open, close and write to the card, respectively. A data value is read from
a software accessible register by using the "MY_CUSTOM_IP_REGISTER_mReadReg"
command. This is a general function to read from a register so it is important to get the
register oset value correct as not to read from another register. The oset for all the
ve registers within the peripheral are dened in the my_custom_ip_register.h header
le.The base address of the peripheral is dened in the "xparameters.h" le. The c source
les used to test the dierent aspects of the peripheral in this project can be found in
sections .5.1,.5.2,.5.3.
The microprocessor software specication le .mss species the driver name, driver ver-
sion and the hardware instance to be used on. The .mss le for the system can be found
in section .2.1.

Figure 4.13: Microprocessor software specication

Figure 4.13 shows the driver setup for the interrupt controller.Notice how the hardware
instance name is the same name as the instance name specied in the mhs le.

4.4 Matlab scripts

Matlab is a great tool for working with images in software as it has the ability to read an
array of values from an image and it can write an array of values to an image le. These

35
abilities will be utilized for this project in order to obtain the image data and to make an
image from the output values. The next subsections will go into how this is done. This is
a good way of evaluating the results of the simulation as the processing vhdl les cannot
be synthesized.

4.4.1 Reading Image

The vhdl modules would normally, in a camera environment, be fed data from an image
sensor. This will be duplicated with the aid of Matlab by writing a script, called im-
age_in.m that reads an image from a le, adds noise and then stores the resulting array
as a format that vhdl can recognize as an array of values.The script can be found in sec-
tion .4.1.This script reads all the values in an image and stores them in a two-dimensional
array. The desired noise is then injected into the array of values and then it is written
in a format (value1, value2) and stored in a text le. The content of the le can then be
pasted into the package vhdl le and read by the vhdl modules.

4.4.2 Write Image

A Matlab script is also required to read the values in the le written by the textIO
package and then convert it to an image. This is done in the image_out.m le that can
be found in section .4.2.The script reads the values in the le produced by the textIO
package and then makes a two dimensional array that is written to a PGM image le
and stored. Upon completion the images needs to be inverted in a photo editing software
before receiving the results in the simulation chapter.

4.4.3 Measuring Statistical Values

The values used to make the graphs in chapter 5 were gathered using a Matlab script. It
reads the original image along with the restored images and stores them in two dierent
two dimensional arrays. A double for-loop searches through the two arrays in order
to calculate the mean absolute error, mean square error and the peak signal to noise
ratio.The script can be found in section .4.3.

36
Chapter 5

Simulation

All the modules used in this system have been tested to ensure correct behavior on every
level of the hierarchy both in terms of vhdl les and software modules. The next sections
will show how the various modules have been tested and the results. All the testing has
been done at the clock frequency of 100MHz in Active HDL.

5.1 VHDL module testing

The vhdl les that makes up the vhdl peripheral have been tested using a test benches
created in activeHDL, in order to ensure that they will exhibit correct behavior. The
following sub sections will show results from simulation of the various modules and then
bring it all together with a simulation of all the processing les in the peripheral.

5.1.1 Median Testing

The median module was tested by inputting an array of values and then make sure that
the output median value was indeed the median of the input values. Figure 5.1 shows
an input sequence where all the values are inputed serially and then stored in an array,
called data, within the module.

37
 Figure 5.1: Input Sequence

The input array for the median module is {115,113,127,127,127,127,141,105,127}. The

same array in ascending order is {105,113,115,127,127,127,127,127,141}, and that corre-
sponds to the data array in the median module. Thus, the module produced the correct
median value for that array. Figure 5.2 shows the end of the execution of the median
module, for these values, where the done signal is assigned high and the median value is
assigned to the median port.

Figure 5.2: Output Sequence

5.1.2 Image_core Testing

The image_core is on a higher hierarchical level than the median module. Its job is to
search through a two dimensional array of image values in order to determine the positions
of the defective pixels. It will input the correct neighboring pixels to the median module
and wait for it to produce the median value. The best way to test this module is to input
the values from an image with noise and then make an image of the output values in
order to visually conrm that the image does in fact have lower levels of noise.

38
 Figure 5.3: Image_core input sequence

Figure 5.3 shows the input signals that are utilized in the image_core module when
values from an image are inputed to the image_core module. They are then stored in an
array called bayer_array. Figure 5.4 shows that the state machine in the image_core
module returns to idle state when it's done with the processing of the input image.

Figure 5.4: Image_core end of execution

The output values from the image_core module are stored in a le using the textIO
package. Those values are then run through the Matlab script in order to get an image
from the values. The values that are sent into the image_core module are from the
Lena [15] image that has been corrupted by noise with the probability of 0.01(1%). The
input image is shown in gure 5.5.

39
 Figure 5.5: Input Image with noise

Figure 5.6 shows the resulting output image from the image_core and stored in the
textIO based le. It is clear that the resulting image is a great improvement over the
noise corrupted input image.

Figure 5.6: Output image

40
5.1.3 Ctrl Testing
Testing the ctrl module is done by using the same input values as when testing the
image_core, but this time the only output signals will be the new image values as that
is the only signal declared as output signal in the ctrl module.

Figure 5.7: Ctrl output sequence

Figure 5.7 shows how the output values of the image are assigned to the output of the ctrl
module. This will occur until all the values have been assigned to the data_out signal.
All the values are then stored in a le using the textIO package so the content of the le
can be made into an image with the image_out.m matlab script. The image is identical
to gure 5.6 which is only to be expected as there is no added processing happening in
the ctrl module. Testing these modules individually proved that they exhibit the correct
behavior as intended.

5.2 Test of the whole VHDL system

The whole system will now be simulated using the values obtained from the textIO vhdl
package in order to visually and statistically verify that the resulting image is an image
with less noise quantities than the image corrupted with noise. The Lena image(256x256)
[15], Field image(500x500) [10] and the canyon image(200x300) [7] will be used as
input images with dierent noise levels and threshold levels. These images have dierent
contrast levels and dierent numbers of pixels so it will be a test of the algorithm's ability
to correct pixels from dierent contrast images and also the scalability of the algorithm.
In addition to putting the image under visual scrutiny, a few key values will be measured
that are relevant when comparing images. The next sections will show the resulting graphs
from the resulting images with dierent noise levels and dierent threshold values.

5.2.1 Dierent noise levels

The input images were simulated with dierent noise levels in the interval 0.001−0.1. The
mean square error, mean absolute error, peak signal to noise ratio and the simulation time
were recorded for every noise level and all the simulation took place with the threshold
value at 10. The resulting images can be found in sections .6.2, .6.4, .6.6 along with
the input image corrupted by noise. It is therefore possible to view and compare the
input image and the output image in order to ascertain the algorithm's ability to remove
defective pixels.

41
Peak Signal to Noise Ratio

The typical values for peak signal to noise ratio for an image with lossy compression is
between 30 − 50. That range can be a guideline to evaluate at which noise levels the
resulting image will be of sucient quality. The starting value for the peak signal to
noise ratio for the Lena image is 38 at the noise level of 0.001 while the end value at the
noise level of 0.1 is 22. That means that the algorithm produces acceptable quality with
peak signal to noise ratios for noise levels from 0.001 − 0.02, as can be seen from gure
5.8. It shows the trajectory as a function of noise density, and it is evident that there
is an almost inverse exponential relationship between the two except from a few values
near the beginning of the graph. The eld image does have a lower starting value for
the peak signal to noise ratio than the Lena image while it follows a similar trajectory.
It will have sucient quality in the noise range 0.001 − −0.03. The canyon image has
its highest peak signal to noise ratio of 23 and will thus not qualify for comparison as it
never has a value over 30.

Figure 5.8: Peak signal to noise ratio for dierent noise levels

Mean Square Error

Figure 5.9 shows how the mean square error relates to dierent noise densities. There
is an exponential growth, for the Lena image, in the mean square error with the starting
value of 0.043 at 0.001 noise level and ends at 1.33 at 0.1 noise level. The mean square
error relates to the peak signal to noise ratio (see section 3.6.1) so that a lower mean
square error translates into a higher peak signal to noise ratio. As such, optimizing either
one of the values will result in a higher peak signal to noise ratio. The canyon image
has a similar trajectory with a higher peak than the trajectory for the Lena image. The
trajectory for the eld image had a much lower peak signal to noise ratio and thus a
higher mean square error trajectory.

42
 Figure 5.9: Mean square error for dierent noise levels

Mean Absolute Error

The mean absolute error for the three input images with dierent noise levels is shown in
gure 5.10. The trajectory of the Lena image follows an exponential path with a starting
point of 0.68 at 0.001 noise level and ends at 3.03 at 0.1 noise level. Comparing gure
5.9 and gure 5.10 shows a similar trajectory only with the mean absolute error having
a higher values than the graph of the mean square error. The canyon image has a similar
trajectory while the trajectory of the eld image has a higher value at all noise levels.

Figure 5.10: Mean absolute error for dierent noise levels

43
Simulation times

As with any system required to operate in real time it does have certain demands as far as
time is concerned. These simulation times will, therefore, prove or disprove the systems
ability to meet those demands that would be imposed in a real time environment.

Figure 5.11: Simulation times for dierent noise levels

Figure 5.11 shows the time it took in order to complete a simulation at the dierent
noise levels for the three input images. All the values of time on the y axis are measured
in milliseconds. At low noise densities the simulation for the Lena image time is less than
4 milliseconds.That is equivalent is 250 times per second, which would be fast enough
for most camera applications.The highest simulation time comes, not surprisingly, at the
highest noise level, results in up to 7.5 milliseconds. That is the same as 133 times
per second. In terms of simulation time, this algorithm has sucient capabilities to be
placed in a real time camera environment. The canyon image has a simulation time of
5 milliseconds for small quantities of noise and 9 milliseconds for high noise quantities.
Those numbers represents 200 and 111 times per second. The eld image does have the
highest simulation times of the three images with 21 milliseconds for low noise quantities
and 34 which is equivalent to 47 times per second.The images uses 34 milliseconds for
high noise quantities which is 29 times per second. Another important aspect of the
algorithm is its scalability in terms of simulation time per pixel. An image with a higher
number of pixels will require a longer simulation time. It is therefore a trade o for the
designer as to how large pixel wise images are required and the time limitation imposed
by the environment.

44
 Figure 5.12: Simulation times per pixel

Figure 5.12 shows the simulation times per pixel for the dierent noise levels. The Lena
image causes the lowest simulation time despite containing more pixels than the canyon
image. The eld image has many more pixels than the eld image but still has about the
same simulation time. Given the values from the three images, it's possible to interpolate
a trajectory in order to estimate the simulation time any image with a given number of
pixels.

5.2.2 Dierent threshold values

This section contains data that was gathered with a constant noise level of 0.02 while the
threshold value has been changed within the range 2 − 50 for all the images. The goal of
these simulations is to determine whether altering the threshold for an image will result
in higher peak signal to noise ratio. The resulting images from the simulation are placed
in sections .6.3, .6.5, .6.7.

Peak Signal to Noise Ratio

Figure 5.13 reveals that a threshold of 20 − 30 is the best level in order to obtain the
highest peak signal to noise ratio for the Lena image. Choosing to use the optimized
threshold level of 25 as opposed to the default level 10 does only increase the peak signal
to noise ratio from 34.5dB to 36dB. Some situations may have this as a trade o worth
doing, while others may opt for a shortened simulation time and a smaller peak signal
to noise ratio.The canyon image does have a spike in the peak signal to noise ratio in
the 10 − 15 range but it is otherwise pretty much has a constant decline at all threshold
levels. The value of the spike is so small that in most cases it will not amount to anything
but increased simulation time.
The eld image does have the highest peak signal to noise ratio for the lowest possible

45
threshold levels. It is clear that this image will require a low threshold in order to produce
the highest peak signal to noise ratio. The higher threshold levels also means that areas
with low contrasts and defective pixel may not be corrected because th threshold level
is too high. As such, it is best to go for the lowest threshold that produces the desired
peak signal to noise ratio.

Figure 5.13: Peak signal to noise ratio for dierent threshold levels

Mean Square Error

Figure 5.14 shows that mean square error for the three images. The Lena image does
have an optimum level that corresponds to the optimum level of the peak signal to noise
ratio in the range 20 − 30. The canyon image does have its lowest mean square error
in the range 10 − 15 and the eld image has its lowest mean square error at low noise
quantities.

46
 Figure 5.14: Mean square error for dierent threshold levels

Mean Absolute Error

Figure 5.14 shows the relationship between the mean square error and the noise density.
The Lena image still produces the least amount of mean absolute error with a low point
in the range 15 − 35. The canyon image has its low point in the range 15 − 30 and the
eld image has its lowest values towards the lowest threshold value.

Figure 5.15: Mean absolute error for dierent threshold levels

47
Simulation times

The simulation times are shown in gure 5.16. The led image has the highest simulation
time with 40 milliseconds for low threshold levels and 20 milliseconds for high threshold
levels. Both the canyon image and the Lena image have a simulation time of 10 mil-
liseconds for low noise levels and 5 milliseconds for high threshold levels. The simulation
time should, however, be considered of less importance when tailoring the algorithm to
produce best results for a given image as long as it meets the constraints imposed on it
by its real time environment.

Figure 5.16: Simulation times for dierent threshold levels

5.3 Software algorithms

This section will show the results of the simulations of the median algorithm that were
designed in software in my last semester's project with the three images as input. The
matlab script .4.4 was used for the simulations with the threshold of 10 and with the
noise level of 0.02.The resulting images from the simulation can be found in section .6.8.

Lena Field Canyon

psnr(dB) 35.1 31.6 32.75
time(s) 3.03 6.5 1.28

Table 5.1: Software algorithm results

48
5.4 Microblaze simulation
The vhdl peripheral in the microblaze system is a module to test how values can be read
to and from the peripheral and how to use interrupts and interacting with the cf card.
Values are read from the compact ash card into the peripheral in the rst test of the
system ace controller. The resulting output value from the peripheral is stored in a le
on the compact ash card by using interrupt. The testing will start with the interaction
with the cf card, followed by the interrupt mechanism and reading and writing values to
and from registers.

5.4.1 System Ace write to card

The simulation of the compact ash card will verify that les can be read from a le on
the cf card and stored back into another le on the card in the same directory. The input
le directory is in the root directory of the cf card with a le named "input.txt". The le
will contain ve integer values, and the le opened in notepad is shown in gure 5.17(a).
The read data is stored in a character buer called "readBuer" before it is written to a
le called "output.txt". Figure 5.17 shows that the output le contains the same data
as the input le and thus verifying that the cf card can be written to and read from. The
c code used to test the read and write capabilities of the cf card can be found in section
.5.1.

(a) Input le (b) Output le

Figure 5.17: Compact ash read and write simulation

5.4.2 Interrupt testing

Setting up an interrupt based system requires that the interrupts are enabled on all the
components that deal with an interrupt. It is also necessary to register a handler that is
invoked whenever the interrupt "res". One interrupt handler is required for every device
that communicates with the cpu by the means of interrupts. The source le requires one
function to enable the setup the interrupt on microblaze, the interrupt controller and
the my_custom_ip_register and a function to be executed when an interrupt res. The
init() function in the source code(section .5.2) contains all the required functions for

49
the interrupt mechanism to work correctly. It will register an interrupt handler, enable
interrupts on the interrupt controller my_custom_ip_register and microblaze. The init()
function only needs to be run once when the cpu is turned on. The function intr_handler()
is the interrupt service routine that is executed on every interrupt. A simple test of the
interrupts is to write some data to the cf card in the isr. Inspecting the output le will
determine if the correct data has been written to the card. For this test the data written
to a le on the cf card contains the characters "test", which means that it will be written
to the card if the isr is executed. Interaction with the cf card proves to work correctly
unless there is an absence of data, in a le with the correct name, written to the card.
Figure 5.18 shows the data written to the card by the isr, and it is the same data as the
isr was instructed to write. The le is therefore evidence that the interrupt was set up
correctly and that it was assigned by the custom ip module.

Figure 5.18: File written by the isr

5.4.3 Read value from peripheral register

This section was the last to be tested as it requires both the interrupt mechanism and
the read and write methods for the cf card to function correctly in addition to adding
functions to write data to a peripheral register and to read data from the register. A
hexadecimal value of A2 (162 in decimal value) is written to register 3 in the peripheral
unit before the init() function sets up the interrupts. The isr is altered so that it reads
the value of register 3 from the peripheral unit and stores it in a variable before writing
it to the predetermined le on the cf card. Having the le contain the same value as the
one written to the card will be evidence that interaction with the peripheral is working.

Figure 5.19: Test Read from a Register

50
Figure 5.19 shows the le produced by the isr and stored on the card. The output le
contains values that are coded in ascii so that it will not show A216 or 16210 but rather
the ascii symbol with the decimal value of 162. The resulting le produced by the isr, in
gure 5.19, shows the ascii symbol of the values it read from the register. Using the ascii
table at [3] reveals that the symbol written is at the 162nd position and thus conrming
that reading from the register and writing to the register works correctly.

51
Chapter 6

Synthesis

6.1 VHDL Synthesis

The vhdl les that do the processing part of this project cannot be synthesized in the
vhdl hierarchy they are built as the Xilinx ise synthetization tool eventually runs out
of memory without giving any error message. In accordance with the supervisor at the
university, the vhdl les will not be synthesized as part of this project. The vhdl les
created by the wizard for the custom ip will, however, be synthesized as part of running
synthesis on microblaze. The area report will thus only be for the vhdl les created by
the wizard.

6.2 Microblaze Syntethization

The embedded system created in platform studio are synthesized by the "generate netlist"
command and the synthesis report is stored in the report folder in the project directory.
The synthesis report for the design can be found in section .3. The maximum delay
through the system is 6.18 ns which gives a clock frequency of the system of 161.34 MHz.
The clock frequency and variable related to the clock are found in gure 6.2.

Figure 6.1: Synthesis delay

Figure 6.1 shows a part from the synthesis report regarding the resources utilized for
the system. The design utilizes 9% of the available registers and 10% of the available
LUTs. These numbers shows that the design only utilizes a small amount of resources on

52
the chip as can be expected for a such a small system. Many systems of this kind will
have area limitations so that utilizing a small percentage of the resources is always great
news. The I/O utilization is at 7% and with 66% of ram/fo utilized. The reason for
having such a large percentage of ram/fo utilization is a combination of the requirement
of storing values within the peripheral that can be read by the cpu, in addition to only
having 64 kb of memory to begin with.

Figure 6.2: Synthesis resource utilization

53
 Chapter 7

Tools

This project has required a handful of tools in order to deal with the dierent aspects
of the design from converting an image in software to adding peripheral, to the cpu
to synthesizing the complete design. The computer used in this project has a 32 bit
Windows Vista Home Basic operating system with Service pack 2, dual processor where
each processor has a frequency of 2.26GHz, and the computer has 3.0 GB ram. Matlab
was the tool used to convert an image from a le to an array in the vhdl package le
and to convert values from the simulation to an image. The hardware programming and
simulation were done in Active HDL software, and when the simulation showed correct
behavior it was synthesized in ISE project navigator, which is part of the Xilinx web pack.
The creation of the embedded design took place in platform studio which also did the
synthezation of the embedded design. The design could then be implemented to the fpga
with the Impact tool which is a part of the webpack from Xilinx. The various software
and version number type can be seen from table 7.1.

Development board Xilinx ML501

Matlab Matlab Version 7.4.0.287(R2007a) Copyright 1984-2007 The MathWorks, Inc
Active HDL Active HDS version 7.2.1644 Student Edition, Copyright(c) ALDEC, Inc All rights reserved
ISE Project Navigator version 11.5, Copyright (c) 1995-2009
ISE Project Navigator version 12.1, Copyright (c) 1995-2009
Platform studio Xilinx Platform Studio 11.5, Copyright (c) 1995-2009 Xilinx, Inc
Platform studio Xilinx Platform Studio 12.1, Copyright (c) 1995-2009 Xilinx, Inc
Impact ISE impact4 version 11.5, copyright (c) 1995-2009, Inc
Impact ISE impact4 version 12.1, copyright (c) 1995-2009, Inc

Table 7.1: Software utilized

54
Chapter 8

Discussion

The discussion of the results from the hardware and software part of this project are
given separately in order to put the results into context.

8.1 Vhdl
The vhdl le median.vhd is the only le that will synthesize in the project navigator
tool because it is at the lowest level in the vhdl hierarchy. The other vhdl les cannot
be synthesized so the simulation of the les in conjunction with the textIO package and
Matlab scripts will serve as the bases for determining this design's ability to operate in
a real time system. It is clearly not desirable not to be able to synthesize the vhdl les
as it introduces uncertainties as to whether the system will have the same behavior in
hardware as it exhibited in the simulation in software. It also introduces no evidence
as to the physical size of the vhdl les that will inevitably require a higher utilization
of resources as the majority of all the processing is done there. The only area values
that are given is the area of the two vhdl wrapper les created by the import custom ip
wizard in order to set up communication between the custom ip and the plb bus. It is
also assumed that adding the other vhdl les will introduce a longer delay path in the
design, which will lead to a lower clock frequency.

8.2 Microblaze
The embedded system was created and synthesized in the platform studio. The design
shows that it has a high clock frequency and a low resource utilization except for ram
usage. This can be explained by the fact that the system really does very little processing.
The other peripherals show higher clock frequencies than the processor so the cpu is the
weakest link when calculating the maximum clock frequency. The code written to interact
with the cf card, set up interrupts and reading from a register and writing to a register
are shown to work as desired. Testing the system by writing values to a le on a cf card
would prove to be a better way of testing the system if the output data were written in

55
decimal number as opposed to ascii code as the data could be written into matlab with
a simple script.

8.3 Simulation
The graphs based on the data from the simulations data shows that a high peak signal to
noise ratio leads to a low mean square error and mean absolute error. This is also obvious
from looking at equations (3.4), (3.3), (3.5) that optimizing for one of the variables
will result in an optimization for all the variables.Simulating the images with dierent
thresholds introduced the concept of being able to optimize an image in order to achieve
higher peak signal to noise ratio and lower mean square error and mean absolute error
on an image-by-image basis. As an illustration, the peak signal to noise ratio for 0.02
noise level with the threshold at 10 is 34.59dB. The simulation of the dierent thresholds
revealed that the optimum threshold for the highest peak signal to noise ratio was 20−30.
The peak signal to noise ratio for the threshold of 26 with 0.02 nose level is 36.04dB.
Those numbers show that there is something to gain by optimizing the threshold, but
that is at the expense of higher simulation times as the optimum threshold level has
to be determined based on simulations on dierent threshold levels. The simulation for
correcting the defective pixels can only be run after the threshold level has been found.
Having the threshold value at 10 seems to be a good general purpose value as the peak
signal to noise ratio is close to the peak signal to noise ratio at the optimized threshold
level.

8.4 Real time operation

Modern cameras like the Canon 7d [6] have the ability to expose multiple images at a fast
rate of frames per second. The Canon 7d can shoot 8 frames per second at continuous
shooting. That introduces a limit as to how long a correction algorithm can use and still
keep up with new data arriving from the sensor. Shooting 8 frames per second translates
into 125 milliseconds per image. The simulation times for the 256x256 pixel test image
vary between 3.5 and 7.5 millisecond depending on the noise level. Assuming an average
simulation time of (3.5+7.5)/2 = 5.5 milliseconds the time frame for a single exposure
increased from 125 millisecond to 130.5 millisecond. This results in the frames per second
being reduced from 8 to 7.6. The time it takes to correct an image is a small fraction of
the time it takes to expose an image, which is what is desirable as the main function of
the system is to expose images. The eld image used an average simulation time of 28
milliseconds and thus increased the time for each exposure to a total of 153 milliseconds,
which is equivalent to 6.5 exposures per second with the 8 fps initially. The canyon image
has an average simulation time of 6.5 milliseconds which makes the total exposure time
131.5 milliseconds. That enables the camera to have a fps rate of 7.6 which is the same
as for the Lena image.

56
8.5 Comparison with 2009 fall project
The simulation of the algorithm designed in my 2009 fall project was re-simulated with
the Lena, eld and canyon images in order to compare it with statistical values and
simulation times of the same algorithm designed in hardware. The comparison values
were both gathered during simulation using a threshold of 10 and a noise level of 0.02.
The simulation times and the peak signal to noise ratios for the software algorithms are
shown in gure .6.8.The Lena image took 3.03 seconds to simulate in software and 4.46
milliseconds in hardware so a tremendous amount of execution time is saved when doing
the processing in hardware.The corresponding peak signal to noise ratio from the software
algorithm is 35.1 dB while it is 34.5 dB for the version where all the processing is done
in hardware. The eld image took 6.5 seconds to simulate in hardware while it took
24.76 milliseconds. The peak signal to noise ratio was 31.6 dB for the software version
and 21.66 milliseconds for the hardware version.The canyon image took 1.28 seconds to
simulate in software with a corresponding peak signal to noise ratio of 32.74 dB while the
hardware version was simulated in 5.64 milliseconds with a peak signal to noise ratio of
31.33 dB. The above data shows that doing the processing in hardware for this algorithm
executes much faster with a somewhat lower peak signal to noise ratio.

8.6 Interpreting images

The values resulting from the vhdl simulation have been interpreted by a Matlab script in
order to get the values, stored by the textIO package, into a two dimensional array that
in turn can be written to an image. There is, however, a phenomena where an image may
be inverted when the Matlab script image_out.m ( .4.2) is done executing. These images
therefore needs to be entered into a photo editing software where the images have to be
inverted. I have found no clue to the nature of this phenomena in the PGM standards so
it is still an unsolved mystery.

8.7 Border pixels

Defective pixels near an edge or a corner will use the border-pixels in order to nd the new
value for a pixel. As the border-pixels all have the value 127 it may replace a pixel with
a value that does not represent its neighbors. A better way of making a border might be
to create the border as a mirror of the values in the rst two rows and columns in such a
way that the rst border row will have the same values as the second row of the image,
looking at the upper edge. The new pixel values will then have a value corresponding to
the neighboring pixels.

57
8.8 Tools
Xilinx released the 12.1 version of the ise webpack and the platform studio as the project
are ongoing so that is the reason that both the 11.5 version and the 12.1 version was
listed in the tools chapter.

8.9 Appendix
The package vhdl le contains an array with all the values from the input images and it
was not possible to get Latex to add that le to the appendix as the pdatex compiler kept
shutting down when attempting to compile. The le is therefore added to the appendix
without the array with the image values. The values in the array are specied in the
signal the data_array.

58
Chapter 9

Concluding remarks

This project aimed at making an algorithm to detect and correct defective pixels in
images, and with all the processing done in hardware. The simulations show that the
algorithm is exhibiting correct behavior with the output values represented as an image
showing less quantity of noise than the input. The project has met the goals that were
associated with the assignment even though simulation had to take place in several steps
as opposed to if the vhdl le could have been synthesized.

59
Chapter 10

Further Work

The project has been simulated in software but has not been synthesized due to ISE
software is unable to synthesize the design as it runs out of memory. Further work for
the project can then be divided into getting the algorithm to a working stage in an fpga
and improving the design once it is working. The embedded system has a peripheral that
outputs values to a register in the same manner as the vhdl peripheral was intended to
do. The user_logic.vhd le and the ctrl.vhd can be altered to accommodate the ability
to read values from a le into the ctrl module. The ctrl.vhd module needs to add in input
signal for data. It would then read the input signal, and relay them to the image_core
module. The value can be read from a slv_reg in the peripheral. The output values
from the ctrl module can be mapped to the output signal of the user_logic. The value
can now be read by software by reading slv_reg1. The border pixels should be given
values that represents the values of the images as opposed to having a xed value for all
images. This can be done by having the border rows mirror the value of the edges of the
image. The values on the border would then ensure that a better replacement value for
the pixel was used. That would make the system more functional as it can operate on
any set of values given that the size of the image is the same. The task of improving the
system once operational is about making tradeos between the variables in the design
like execution time and resource utilization. It is therefore imperative that the system is
operational and that the limitation of the target device is known before attempting to
optimize the system.

60
Bibliography

[1] Adding a custom ip , http://www.youtube.com/watch?v=DkjVXeqRKjE&feature=

related.
[2] Ascii table , http://en.wikipedia.org/wiki/ASCII.
[3] Ascii table , http://www.web-source.net/symbols.htm.
[4] Bayer lter, http://en.wikipedia.org/wiki/Bayer_filter.
[5] Bayer image lter , http://en.wikipedia.org/wiki/Bayer_filter.
[6] Canon 7d , http://shop.usa.canon.com/webapp/wcs/stores/servlet/product_
10051_10051_230851_-1.
[7] Canyon image , http://bluemesaphotography.com/hye/wp-content/uploads/
2009/07/IMGP8596Crop6by9BW-200x300.jpg.
[8] Decibel measuring , http://www.phys.unsw.edu.au/jw/dB.html.
[9] Decibel scale , http://en.wikipedia.org/wiki/Decibel.
[10] Field image , http://www.thephotoargus.com/wp-content/uploads/2009/11/
bw47.jpg.
[11] Gaussian noise , http://en.wikipedia.org/wiki/Gaussian_noise.
[12] Hexadecimal nubers , http://en.wikipedia.org/wiki/Hexadecimal.
[13] Histogram , http://www.cambridgeincolour.com/tutorials/histograms1.
htm..
[14] Interrupt in microblaze tutorial, http://www.fpgadeveloper.com/2008/10/
timer-with-interrupts.html.
[15] Lena image, http://www.cs.cmu.edu/~chuck/nsipg/nsi.html.
[16] Logarithmic nubers , http://en.wikipedia.org/wiki/Logarithmic_scale.
[17] Mean absolute error http://www.fmi.uni-sofia.bg/vesta/Virtual_Labs/freq/
freq6.html.
[18] Pgm le format, http://netpbm.sourceforge.net/doc/pgm.html.
[19] Salt and pepper noise , http://en.wikipedia.org/wiki/Salt_and_pepper_noise.

61
[20] Xilinx le extensions, http://www.xilinx.com/itp/xilinx8/help/platform_
studio/html/ps_r_gst_project_files.htm.
[21] Mood A., F Graybill, and D Boes. Introduction to the Theory of Statistics. McGraw-
Hill, 3rd edition, 1974.
[22] Henrik Backe-Hansen. Defective pixel correction. Technical report, 2009.
[23] Nokia Coroporation. Smia 1.0 part 1:functional spesication. Technical report, 2004.
[24] Granite Island group. Rs232 interface. Technical report.
[25] Rod Jesman, Fernando Martinez Vanilla, and Jafar Saniie. Microblaze tutorial cre-
ating a simple embedded system and adding custom peripheral using xilinx edk
software tools. Technical report.
[26] Xilinx. Ml501 evalutaion platform. Technical report.
[27] Xilinx. Using and creating interrupt-based systems. Technical report, 2005.
[28] Xilinx. Libxil fatle system(fatfs). Technical report, 2006.
[29] Xilinx. System ace compactash solution. Technical report, 2008.
[30] Xilinx. Defective pixel correction v1.0. Technical report, 2009.
[31] Xilinx. Edk concepts, tools, and techniques. Technical report, 2009.
[32] Xilinx. Embedded system tools reference guide. Technical report, 2009.
[33] Xilinx. Logicore ip xps interrupt controller (v2.01a). Technical report, 2010.
[34] Wang Yuanji, Li Jianhua, Lu Yi, Fu Yao, and Jiang Qinzhong. Image quality eval-
uation based on image weighted separating block peak signal to noise ratio, 2003.

62
.1 VHDL
.1.1 VHDL Source Code
Median Module

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− T i t l e : median . vhd
−− Design : defect_pixel_corr
−− Author : Henrik Backe−Hansen
−− Company : NTNU / Aptina Norway
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− D e s c r i p t i o n : t h i s module w i l l take the w_size , e na b l e and data_in
as the primary input s i g n a l s .
−−the e n ab l e s i g n a l w i l l denote that a new value i s ready at the
data_in port .
−−the w_size w i l l determine the s i z e o f the i n t e r n a l data array as
the s i z e i s w_size ∗ w_size −1
−−The v a l u e s are f i r s t inputed i n t o the data array and then s o r t e d
−−the median o f the array i s then put on the median output port and
the done f l a g i s s e t to ' 1 ' ;
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
l i b r a r y IEEE ;
use IEEE . std_logic_1164 . a l l ;
use work . s i z e . a l l ;

e n t i t y median i s
port (
clk : in std_logic ; −− c l o c k
rst : in std_logic ; −− r e s e t s i g n a l from top l e v e l
module
data_in : i n i n t e g e r range 0 to bit_depth ; −− i n t e g e r s from the
s l i d i n g window
e n ab l e : i n std_logic ; −− s i g n a l to e n b l e the
median module
done : out s t d _ l o g i c ; −− s i g n a l denotes the median
v a l u e s i s found
median : out i n t e g e r range 0 to bit_depth −−the c o r r e s p o n d i n g
median value
);
end e n t i t y ;

a r c h i t e c t u r e med_arch o f median i s

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− S i g n a l d e c l a r a t i o n

63
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
type state_type i s ( i d l e , read_values , s t a r t , one , two , three , r e s e t ) ;
s i g n a l cs , ns : state_type ;

type data_format i s array (8 downto 0) o f i n t e g e r range 0 to

bit_depth ; −− input data array s i z e setup
s i g n a l data : data_format := ( o t h e r s => 0) ;

begin
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−This p r o c e s s r e s e t s the module i n c a s e o f the r s t s i g n a l being
e v a l u a t e d to ' 1 ' .
−− I t changes the value o f the ns ( Next S t a t e ) s i g n a l to the c s ( Current
State ) s i g n a l i f r s t i s '0 '
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
sync_proc : p r o c e s s ( clk , r s t )
begin
i f ( r s t = ' 1 ' ) then
c s <= r e s e t ;
e l s i f ( r i s i n g _ e d g e ( c l k ) ) then
c s <= ns ;
end i f ;
end p r o c e s s ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−temp i s a v a r i a b l e used when two v a l u e s changes p l a c e s
−− index i s used to loop through the array
−−median_counter p o i n t s to the p o s i t i o n o f the median i n a s o r t e d
array
−−count counts the number o f i n s t r u c t i o n that can be done on one pass
o f the array
−−packet_counter i s the number o f v a l u e s i n the data array and i f a l l
the p a c k e t s are p r e s e n t
−− i t w i l l s t a r t the median c a l c u l a t i o n by s e t t i n g ns to s t a r t
−−
−− s t a t e i d l e w i l l t r i g g e r on the e na b l e s i g n a l and then s e t the ns
s i g n a l to read_values
−−the read_values s t a t e w i l l s t o r e the input i n the l o c a t i o n , i n the
data array , denoted by packet_counter
−− s t a t e one w i l l loop through a l l the v a l u e s and swap v a l u e s i f the
h i g h e r value i s at the h i g h e r p o s i t i o n
−−when a l l the v a l u e s have been s o r t e d count = w_data ∗ w_size − 1, and
the ns s i g n a l i s t h r e e
−−In the s t a t e t h r e e the median i s s e t on the output , the done f l a g
i s s e t to ' 1 ' and ns i s i d l e ,
−−and the median module i s ready to read o t h e r v a l u e s
−−output s i g n a l s are given d e f a u l t v a l u e s i n the b e g i n i n g o f the
process

64
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
comb_proc : p r o c e s s ( cs , enable , data_in )
v a r i a b l e temp : n a t u r a l range 0 to 255 := 0 ;
v a r i a b l e index : n a t u r a l range 0 to 255 := 1 ;
v a r i a b l e count : n a t u r a l range 0 to 255 := 0 ;
v a r i a b l e packet_counter : n a t u r a l range 0 to 255 := 0 ;

begin
done <= ' 0 ' ;
median <= 0 ;

ns <= i d l e ;
case cs i s

when r e s e t =>
median <= 0 ;
packet_counter := 0 ;
packet_counter :=0;
count := 0 ;
index := 0 ;
ns <= i d l e ;

when i d l e =>
i f ( e n a bl e = ' 1 ' ) then
ns <= read_values ;
else
ns <= c s ;
end i f ;

when read_values =>

data ( packet_counter ) <= data_in ;
packet_counter := packet_counter +1;
i f ( packet_counter = data ' l e n g t h ) then
ns <= s t a r t ;
else
ns <= i d l e ;
end i f ;

when s t a r t =>
packet_counter := 0 ;
count := 0 ;
ns <= one ;
index := 1 ;

when one =>

i f ( data (9 − index ) > data (8 − index ) ) then

65
 temp := data (9 − index ) ;
data (9 − index )<= data (8 − index ) ;
data (8 − index )<= temp ;
count := 0 ;
else
count := count +1;
temp := 0 ;

end i f ;

i f ( index = 8) then
ns <= s t a r t ;
index := 0 ;
else
ns <= two ;
end i f ;

index := index +1;

i f ( count = 8) then
ns <= t h r e e ;
else
ns <= two ;
end i f ;

when two =>

ns <= one ;

when t h r e e =>
ns <= i d l e ;
done <= ' 1 ' ;
median <= data ( 4 ) ;

when o t h e r s =>
ns <= i d l e ;

end c a s e ;

end p r o c e s s ;

end a r c h i t e c t u r e ;

66
Image_core Module

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− T i t l e : image_core
−− Design : defect_pixel_corr
−− Author : Henrik Backe−Hansen
−− Company : NTNU / Aptina Norway
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− F i l e : image_core . vhd
−− Generated : Mon Feb 1 1 4 : 0 9 : 2 3 2010
−− From : interface description f i l e
−− By : I t f 2 V h d l ver . 1 . 2 0
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− D e s c r i p t i o n : This image c o r e i s the top l e v e l u n i t o f the
d e f e c t i v e pixel correction algorithm . It uses
−−the median module i n o r d e r to c a l c u l a t e the median o f the v a l u e s at
i t s input .
−−The image c o r e i s enabled by the mod_en s i g n a l and w i l l then read
i n one p i x e l −value at the time u n t i l l a l l p i x e l s have been read
−−The data array w i l l c o n s i s t o f the read p i x e l − v a l u e s and a two
p i x e l border with the value 1 2 7 . This i s to make i t
−− e a s i e r to read and c o r r e c t edge and c o r n e r p i x e l s .
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

l i b r a r y IEEE ;
use IEEE . STD_LOGIC_1164 . a l l ;
use work . s i z e . a l l ;

e n t i t y image_core is
port (
clk : in std_logic ;
mod_en : in std_logic ;
rst : in std_logic ;
core_in : i n i n t e g e r range 0 to bit_depth ;
di : in std_logic ; −−data i n
do : out s t d _ l o g i c ; −−data out
core_out : out i n t e g e r range 0 to bit_depth
);
end image_core ;

a r c h i t e c t u r e image_core_arch o f image_core i s

−−−−− S i g n a l s to the median_mod−−−−−−−

−−These s i g n a l s are the s i g n a l s that communicates between the median
module and the image c o r e

67
signal e n ab l e : s t d _ l o g i c ;
signal data_in : i n t e g e r range 0 to bit_depth ;
signal done : std_logic ;
signal median : i n t e g e r range 0 to bit_depth ;
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

−−−−−−−−−−−−type d e f i n i t i o n s −−−−−−−−−
type pix_map i s array (0 to size_x +3,0 to size_y +3) o f b i t ;
−− p i x e l map
type img_array i s array (0 to size_x +3,0 to size_y +3) o f i n t e g e r range
0 to bit_depth ; −−image array with 2 p i x e l border
type bye_array i s array (0 to size_x − 1,0 to size_y −1) o f i n t e g e r range
0 to bit_depth ; −−bayer image array data
type median_array i s array (8 downto 0) o f i n t e g e r range 0 to
bit_depth ; −− array with the array to the median mod

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

−−−−−−−−−−−−−−−FSM−−−−−−−−−−−−−−−−−−−
type state_type i s ( i d l e , read_values , c o r r e c t , read_out , padding127 ,
data_mapping , de_mapping , f i n d _ d e f e c t s , r e s e t ) ; −−FSM
states
s i g n a l cs , ns : state_type ; −−FSM s i g n a l s
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− I n s t a n s i a t i o n o f the median module component and mapping s i g n a l s to
the median module s i g n a l s
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
begin
median_mod : e n t i t y work . median ( med_arch )
port map(
clk ,
rst ,
data_in ,
enable ,
done ,
median
);

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− p r o c e s s that i s s e n s i t i v e to the input values , clk , r e s e t , and done
s i g n a l . The p r o c e s s w i l l read the p i x e l s i n t o the
−−bayer array , then add a border and map i t to the data array .

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
sync_proc : p r o c e s s ( clk , r s t , core_in , done )
v a r i a b l e bayer_array : bye_array ;
v a r i a b l e pixel_map : pix_map ;

68
variable data : img_array ;
variable med_array : median_array ;
variable state : i n t e g e r := 1 ;
variable a : i n t e g e r :=0;
variable b : i n t e g e r :=0;
variable high : i n t e g e r range 0 to bit_depth := 0 ;
variable low : i n t e g e r range 0 to bit_depth := bit_depth ;
variable timer : i n t e g e r range 0 to 2 := 0 ;
variable x_cor : i n t e g e r range 0 to size_x −1:= 0 ;
variable y_cor : i n t e g e r range 0 to size_y −1:= 0 ;
variable read_state : i n t e g e r range 0 to 3:= 1 ;
variable testing : i n t e g e r := th ;
begin

i f ( r s t = ' 1 ' ) then

c s <= r e s e t ;
e l s i f ( r i s i n g _ e d g e ( c l k ) ) then
c s <= ns ;

case cs i s

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−The r e s e t s t a t e w i l l s e t d e f a u l t v a l u e s to a l l the v a r i a b l e s used
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
when r e s e t =>
timer := 0 ;
a := 0 ;
b := 0 ;
med_array := ( o t h e r s => 0) ;
data := ( o t h e r s => ( o t h e r s => 0) ) ;
bayer_array := ( o t h e r s => ( o t h e r s => 0) ) ;
pixel_map :=( o t h e r s =>(o t h e r s => ' 0 ' ) ) ;
ns <= i d l e ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−The i d l e s t a t e w i l l wait f o r the mod_en s i g n a l to s t a r t i t s work
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
when i d l e =>
do<= ' 0 ' ;
i f (mod_en = ' 1 ' ) then
core_out <= 0 ;
ns <= read_values ;
else
ns <= c s ;
end i f ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

69
−−The v a l u e s are read i n t o the bayer_array i n t h i s s t a t e . The v a l u e s
come from the input i n t e g e r _ i n .
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
when read_values =>
−−read the image v a l u e s and s t o r e them i n the data array
c a s e read_state i s
when 0 =>
i f ( x_cor = size_x −1) then
x_cor := 0 ;
read_state := 2 ;
else
ns <= read_values ;
x_cor := x_cor +1;
read_state := 1 ;
end i f ;

when 1=>
i f ( d i = ' 1 ' ) then
bayer_array ( x_cor , y_cor ) := core_in ;
i f ( y_cor = size_y −1) then
read_state := 0 ;
y_cor := 0 ;
else
y_cor := y_cor +1;
end i f ;
else
read_state := 1 ;
end i f ;

when 2=>
ns <= padding127 ;
read_state := 1 ;

when o t h e r s =>
read_state := 1 ;
end c a s e ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−The padding127 s t a t e w i l l f i l l the e n t i r e data array with the
v a l u e s o f 1 2 7 . This i s i n o r d e r to make a two p i x e l border
−−when the bayer_array i s mapped to the data array . The data array
hence have the s i z e 4 g r e a t e r than the bayer_array
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
when padding127 => −− f i l l i n g the e n t i r e 2D array with
the value 127
f o r a i n size_x+3 downto 0 loop
f o r b i n size_y+3 downto 0 loop

70
 data ( a , b ) := 1 2 7 ;
end loop ;
end loop ;
ns <= data_mapping ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−Data_mapping i s where the bayer_array i s mapped onto the data array
.
−−The r e s u l t i s when an array with the bayer_array with a two p i x e l
border
−− o f the v a l u e s 127( halv way between 0 and 255)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
when data_mapping =>
f o r a i n size_x −1 downto 0 loop −−mapping the data from
the bayer_array to the data array
f o r b i n size_y −1 downto 0 loop
data ( a+2,b+2):= bayer_array ( a , b ) ;
end loop ;
end loop ;
ns <=f i n d _ d e f e c t s ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−This s t a t e w i l l go through the e n i t i r e image , exept the borders , and
p l a c e a ' 1 ' entry i n t o the pixe_map at that p o s s i s i o n
−− i f the value i s c l a s s e f i e d to be d e f e c t i v e . For every p i x e l i t s
e i g h t p i x e l s o f the same c o l o r are e v a l u a t e d i n o r d e r to
−− determine i f the p i x e l i s d e f e c t i v e . I f the middle p i x e l have l e s s
value than the s m a l l e s t v a l u e s − t h r e s h o l d or h i g h e r than
−−the h i g h e s t value + t h r e s h o l d , the p i x e l i s c l a s s e f i e d as d e f e c t i v e
, denoted by a ' 1 ' entry i n the pixel_map at that p o s i t i o n .
−−The h i g h e s t and l o w e s t o f the e i g h t p i x e l s have to be r e c a l c u l a t e d
f o r every p i x e l . That i s done with two f o r l o o p s .
−−When done going through the image tha next s t a t e w i l l be c o r r e c t .
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
when f i n d _ d e f e c t s =>
f o r j i n size_y+1 downto 2 loop
f o r i i n size_x+1 downto 2 loop
med_array ( 0 ) := data ( i − 2, j −2) ;
med_array ( 1 ) := data ( i , j −2) ;
med_array ( 2 ) := data ( i +2, j −2) ;
med_array ( 3 ) := data ( i − 2, j +2) ;
med_array ( 4 ) := data ( i , j +2) ;
med_array ( 5 ) := data ( i +2, j +2) ;
med_array ( 6 ) := data ( i − 2, j ) ;
med_array ( 7 ) := data ( i +2, j ) ;
med_array ( 8 ) := data ( i , j ) ;

71
 high := 0 ;
low := 2 5 5 ;

f o r count i n 0 to 7 loop −− f i n d i n g h i g h e s t and

l o w e s t value
i f ( med_array ( count )>high ) then
high := med_array ( count ) ;
end i f ;
end loop ;

f o r count i n 0 to 7 loop −− f i n d i n g h i g h e s t and

h i g h e s t value
i f ( med_array ( count )<low ) then
low := med_array ( count ) ;
end i f ;
end loop ;

i f ( data ( i , j ) > high+t e s t i n g ) then −− d e f e c t i v e p i x e l

with h i g h e r value
pixel_map ( i , j ) := ' 1 ' ; −−adding the l o c a t i o n to the
pixel_map
e l s i f ( data ( i , j ) < low− t e s t i n g ) then −− d e f e c t i v e p i x e l
with lower value
pixel_map ( i , j ) := ' 1 ' ; −−adding the l o c a t i o n to the
pixel_map
end i f ;
end loop ;
end loop ;
ns <= c o r r e c t ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−The c o r r e c t s t a t e c o n s i s t o f a s t a t e machine that i s t r i g g e r e d by
the s t a t e v a r i a b l e .
−−The 0 and 1 s t a t e a c t s as a double f o r loop i n o r d e r to go through
the pixel_map to s e a r c h f o r ' 1 ' e n t r i e s .
−− I f t h e r e i s a ' 1 ' entry , d e n o t e i n g a d e f e c t i v e p i x e l , the median
array i f f i l l e d .
−−The value o f the n e i g b o r i n g p i x e l i s added to the median array as
long as that p o s i t i o n does not c o n t a i n a ' 1 ' entry i n
−−the pixel_map .
−− S t a t e 2 −10 w i l l s e t the e n a bl e f l a g , s e t the data_in value
a c c o r d i n g to the v a l u e s i n the median array , then r e s e t the en a b l e
flag
−−When a l l the v a l u e s i n the median array have been s e n t the s t a t e
w i l l be 11 , and w i l l be t h e r e u n t i l the median value
−− i s not z e r o .
−−At that p o i n t the median value w i l l be pl a c ed i n i t s proper
p o s i t i o n i n the data array , and then s e t the s t a t e v a r i a b l e to 1 ;

72
−−Being i n s t a t e 12 i n d i c a t e s that the e n t i r e image have been
c o r r e c t e d a c c o r d i n g to the ' 1 ' e n t r i e s i n the pixel_map
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
when c o r r e c t =>
case state i s

when 0=> −− o u t e r f o r loop

i f ( a=size_x +2) then
s t a t e := 1 2 ;
a :=0;
else
a := a+1;
s t a t e := 1 ;
b :=0;
end i f ;

when 1 => −− i n n e r f o r loop

i f ( b=size_y +3) then
s t a t e := 0 ;
else
i f ( pixel_map ( a , b )= ' 1 ' ) then −−a+2,b+2
i f ( pixel_map ( a+2,b+2) = '1 ') then
med_array ( 0 ) := 1 2 7 ;
else
med_array ( 0 ) := data ( a+2,b+2) ;
end i f ;

i f ( pixel_map ( a+2,b ) = '1 ') then −−a+2,b

med_array ( 1 ) := 1 2 7 ;
else
med_array ( 1 ) := data ( a+2,b ) ;
end i f ;

i f ( pixel_map ( a+2,b −2) = '1 ') then −−a+2,b−2

med_array ( 2 ) := 1 2 7 ;
else
med_array ( 2 ) := data ( a+2,b −2) ;
end i f ;

i f ( pixel_map ( a , b+2) = '1 ') then −−a , b+2

med_array ( 3 ) := 1 2 7 ;
else
med_array ( 3 ) := data ( a , b+2) ;
end i f ;

med_array ( 4 ) := data ( a , b ) ; −−a , b

i f ( pixel_map ( a , b −2) = '1 ') then −−a , b−2

73
 med_array ( 5 ) := 1 2 7 ;
else
med_array ( 5 ) := data ( a , b −2) ;
end i f ;

i f ( pixel_map ( a − 2,b+2) = '1 ') then −−a − 2,b+2

med_array ( 6 ) := 1 2 7 ;
else
med_array ( 6 ) := data ( a − 2,b+2) ;
end i f ;

i f ( pixel_map ( a − 2,b ) = '1 ') then −−a − 2,b

med_array ( 7 ) := 1 2 7 ;
else
med_array ( 7 ) := data ( a − 2,b ) ;
end i f ;

i f ( pixel_map ( a − 2,b −2) = '1 ') then −−a − 2,b−2

med_array ( 8 ) := 1 2 7 ;
else
med_array ( 8 ) := data ( a − 2,b −2) ;
end i f ;

s t a t e := 2 ;
else
s t a t e := 1 ;
end i f ;
b:= b+1;
end i f ;

when 2=> −− s t a r t sending data

e n ab l e <= ' 1 ' ;
data_in <= med_array ( 0 ) ; −−1 s t value
i f ( timer = 2) then
ns <= c o r r e c t ;
s t a t e := 3 ;
e n ab l e <= ' 0 ' ;
timer := 0 ;
else
ns<= c o r r e c t ;
s t a t e := 2 ;
timer := timer +1;
end i f ;

when 3 =>
e n ab l e <= ' 1 ' ;

74
data_in <= med_array ( 1 ) ; −−2nd value
i f ( timer = 2) then
ns <= c o r r e c t ;
s t a t e := 4 ;
e n ab l e <= ' 0 ' ;
timer := 0 ;
else
ns<= c o r r e c t ;
s t a t e := 3 ;
timer := timer +1;
end i f ;

when 4 =>
e n ab l e <= ' 1 ' ;
data_in <= med_array ( 2 ) ; −−3 rd value
i f ( timer = 2) then
ns <= c o r r e c t ;
s t a t e := 5 ;
e n ab l e <= ' 0 ' ;
timer := 0 ;
else
ns<= c o r r e c t ;
s t a t e := 4 ;
timer := timer +1;
end i f ;

when 5 =>
e n ab l e <= ' 1 ' ;
data_in <= med_array ( 3 ) ; −−4 th value
i f ( timer = 2) then
ns <= c o r r e c t ;
s t a t e := 6 ;
e n ab l e <= ' 0 ' ;
timer := 0 ;
else
ns<= c o r r e c t ;
s t a t e := 5 ;
timer := timer +1;
end i f ;

when 6 =>
e n ab l e <= ' 1 ' ;
data_in <= med_array ( 4 ) ; −−5 th value
i f ( timer = 2) then
ns <= c o r r e c t ;
s t a t e := 7 ;
e n ab l e <= ' 0 ' ;
timer := 0 ;
else

75
 ns<= c o r r e c t ;
s t a t e := 6 ;
timer := timer +1;
end i f ;

when 7 =>
e n ab l e <= ' 1 ' ;
data_in <= med_array ( 5 ) ; −−6 th value
i f ( timer = 2) then
ns <= c o r r e c t ;
s t a t e := 8 ;
e n ab l e <= ' 0 ' ;
timer := 0 ;
else
ns<= c o r r e c t ;
s t a t e := 7 ;
timer := timer +1;
end i f ;

when 8=>
e n ab l e <= ' 1 ' ;
data_in <= med_array ( 6 ) ; −−7 th value
i f ( timer = 2) then
ns <= c o r r e c t ;
s t a t e := 9 ;
e n ab l e <= ' 0 ' ;
timer := 0 ;
else
ns<= c o r r e c t ;
s t a t e := 8 ;
timer := timer +1;
end i f ;

when 9 =>
e n ab l e <= ' 1 ' ;
data_in <= med_array ( 7 ) ; −−8 th value
i f ( timer = 2) then
ns <= c o r r e c t ;
s t a t e := 1 0 ;
e n ab l e <= ' 0 ' ;
timer := 0 ;
else
ns<= c o r r e c t ;
s t a t e := 9 ;
timer := timer +1;
end i f ;

when 10 =>
e n ab l e <= ' 1 ' ;

76
 data_in <= med_array ( 8 ) ; −−9 th value
i f ( timer = 2) then
ns <= c o r r e c t ;
s t a t e := 1 1 ;
e n ab l e <= ' 0 ' ;
timer := 0 ;
else
ns<= c o r r e c t ;
s t a t e := 1 0 ;
timer := timer +1;
end i f ;

when 11=>
i f ( done = ' 1 ' ) then −− w a i t i n g f o r the median module to
produce i t s output
data ( a , b −1):= median ; −− r e p l a c i n g the d e f e c t i v e value with
the median o f i t s n e i g b o r i n g p i x e l s
s t a t e := 1 ;
else
s t a t e := 1 1 ;
end i f ;
ns <= c o r r e c t ;

when 12 =>
ns <= de_mapping ;

when o t h e r s =>
s t a t e := 1 ;
end c a s e ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−The two p i x e l border i s removed i n the de_mapping s t a t e .
−−The new bayer_array has s i z e o f the o r i g i n a l array , but with
corrected values .
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
when de_mapping =>
f o r a i n size_x −1 downto 0 loop
f o r b i n size_y −1 downto 0 loop
bayer_array ( a , b ) := data ( a+2,b+2) ;
end loop ;
end loop ;
ns <= read_out ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−Read_out w i l l read out the data array , one value at the time
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
when read_out =>

77
 c a s e read_state i s
when 0=>
i f ( x_cor = size_x −1) then
read_state := 3 ;
x_cor := 0 ;
else
x_cor :=x_cor +1;
read_state := 1 ;
end i f ;

when 1=>
do <= ' 1 ' ; −−x_cor , y_cor
core_out<= bayer_array ( x_cor , y_cor ) ;
read_state := 2 ;

when 2=>

do <= ' 0 ' ;

i f ( y_cor = size_y −1) then
y_cor := 0 ;
read_state := 0 ;
else
read_state := 1 ;
y_cor := y_cor +1;
end i f ;

when 3=>
ns<= i d l e ;

when o t h e r s =>
read_state := 1 ;
end c a s e ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−Required s t a t e as to a v i o i d c s s i g n a l with a wrong value ( not a
defined state )
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
when o t h e r s =>
ns <= i d l e ;

end c a s e ;
end i f ;
end p r o c e s s ;
end image_core_arch ;

78
Ctrl Module

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− T i t l e : ctrl
−− Design : defect_pixel_corr
−− Author : Henrik Backe−Hansen
−− Company : NTNU / Aptina Norway
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− F i l e : c t r l . vhd
−− Generated : F r i Mar 5 1 3 : 5 1 : 1 3 2010
−− From : interface description f i l e
−− By : I t f 2 V h d l ver . 1 . 2 0
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− D e s c r i p t i o n : Top l e v e l u n i t i n the d e f e c t i v e p i x e l c o r r e c t i o n
a l g o r i t h m . Reads
−−data from RAM and i n p u t s them to image_core , and r e a d s the v a l u e s
from image_core
−− back to RAM
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

l i b r a r y IEEE ;
use IEEE . STD_LOGIC_1164 . a l l ;
use work . s i z e . a l l ;
use IEEE . numeric_std . a l l ;

entity ctrl is
port (
clk : in std_logic ;
data_out : out i n t e g e r ;
rst : in std_logic
);
end c t r l ;

architecture ctrl_arch of c t r l i s
−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−The f o l l o w i n g s i g n a l s are used to map to the image_core
−− s i g n a l s to t h e s e s i g n a l s i n o r d e r to communicate with
−−sub−modules
−−−−−−−−−−−−−−−−−−−−−−−−−−−
signal mod_en : std_logic ;
signal core_in : i n t e g e r range 0 to bit_depth ;
signal di : std_logic ;
signal do : std_logic ;
signal core_out : i n t e g e r range 0 to bit_depth ;

79
−− S t a t e machine s i g n a l s f o r the two s t a t e machines .
−−The cs_r and ns_r denotes the read o p e r a t i o n from ram w h i l e
−−cs_w and ns_w denotes a w r i t e o p e r a t i o n from ram
−−−−−−−−−−−−−−−−−−−−−−−−−−−
type state_type i s ( i d l e , one , two , s t a r t , wait1 , wait2 ) ;
s i g n a l cs_r , cs_w , ns_r , ns_w : state_type ;

begin

−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− I n i t i a l i z e the image_core module and mapping s i g n a l s to the module
−−−−−−−−−−−−−−−−−−−−−−−−−−−
image_core_module : e n t i t y work . image_core ( image_core_arch )
port map(
clk ,
mod_en ,
rst ,
core_in ,
di ,
do ,
core_out
);

−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−Synchrounes p r o c e s s that makes the s t a t e t r a n s i s t i o n s on the r i s i n g
edge o f the c l o c k
−−−−−−−−−−−−−−−−−−−−−−−−−−−
sync_proc : p r o c e s s ( c l k )
begin
i f ( r i s i n g _ e d g e ( c l k ) ) then
i f ( r s t = ' 1 ' ) then
cs_r<= i d l e ;
cs_w <= i d l e ;
else
cs_r <= ns_r ;
cs_w<= ns_w ;
end i f ;
end i f ;
end p r o c e s s ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−This p r o c e s s w i l l read a l l the v l a u e s o f an image from ram i n t o the
image_core
−−the ram module i n p u t s and outputs only s t d _ l o g i c _ v e c t o r so the
v a l u e s ( ram_out )
−−needs to be converted from s t d _ l o g i c _ v e c t o r to i n t e g e r b e f o r e
inputting

80
−−them to the image c o r e . The f l a g s data i n ( d i ) a l s o needs to be s e t
i n o r d e r f o r the iamge_core
−− to know that i t s r e c e i v i n g data . The mod_en s i g n a l a l s o needs to be
s e t i n o r d e r to en a b l e the
−−image_core .
−−The s t a t e machine i s n e c e s a r r y i n o r d e r to get the r i g h t timing on
the input s i g n a l s to the image_core
−−Read_adr i s a v a r i a b l e that needs to be converted to
s t d _ l o g i c _ v e c t o r i n o r d e r to get c o r r e c t
−−communication between ram and image_core
−−−−−−−−−−−−−−−−−−−−−−−−−−−
write_to_core_from_ram : p r o c e s s ( cs_r , data_array )
v a r i a b l e sent_count : n a t u r a l := 0 ;

begin

c a s e cs_r i s

when i d l e =>
sent_count := 0 ;
ns_r <= s t a r t ;
mod_en <= ' 1 ' ;

when s t a r t =>
ns_r <= one ;

when one =>

i f ( sent_count = ( ( size_x ∗ size_y ) ) ) then
ns_r <= s t a r t ;
else
ns_r <= two ;
end i f ;
mod_en <= ' 0 ' ;
di <= ' 0 ' ;

when two =>

di <= ' 1 ' ;
core_in <= data_array ( sent_count ) ;
sent_count := sent_count +1;
ns_r <= one ;

when o t h e r s =>
ns_r <= i d l e ;

end c a s e ;
end p r o c e s s ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−

81
−−This p r o c e s s w i l l w r i t e the output v a l u e s from the image_core back
to the ram module .
−−There they w i l l be s t o r e d i n the ram_block array .
−−Data out from the image_core i s denoted by the data out ( do ) f l a g so
cheching the f l a g
−− w i l l ensure that a l l data out v a l u e s are s t o r e d to ram .
−−The ram module only a c c e p t s s t d _ l o g i c _ v e c t o r so the write_adr and
value w i l l be converted from
−− i n t e g e r to e i g h t b i t s t d _ l o g i c _ v e c t o r .
−−The p r o c e s s w i l l s t a r t w r i t i n g v a l u e s at p o s i t i o n 0 and end with
p o s i t i o n size_x ∗ size_y −1
−−−−−−−−−−−−−−−−−−−−−−−−−−−
read_from_core_to_ram : p r o c e s s ( do , cs_w , mod_en , core_out )
v a r i a b l e recv_count : n a t u r a l range 0 to ( ( size_x ∗ size_y ) ) := 0 ;
begin
c a s e cs_w i s
when i d l e =>
i f ( do = ' 1 ' and mod_en = ' 0 ' ) then
data_out <= core_out ;
recv_count := recv_count +1;
end i f ;

when o t h e r s =>
ns_w <= i d l e ;

end c a s e ;

end p r o c e s s ;

end c t r l _ a r c h ;

82
Size Package

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− T i t l e : size_package
−− Design : defect_pixel_corr
−− Author : Henrik Backe−Hansen
−− Company : NTNU / Aptina Norway
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− F i l e : size_package . vhd
−− Generated : F r i Feb 26 1 5 : 0 9 : 2 8 2010
−− From : interface description f i l e
−− By : I t f 2 V h d l ver . 1 . 2 0
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− D e s c r i p t i o n :
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
l i b r a r y IEEE ;
use IEEE . std_logic_1164 . a l l ;
use IEEE . numeric_std . a l l ;
use IEEE . std_logic_unsigned . a l l ;

package s i z e i s

c o n s t a n t size_y : n a t u r a l := 2 5 6 ; −− s i z e o f the image i n

the y d i r e c t i o n
c o n s t a n t size_x : n a t u r a l := 2 5 6 ; −− s i z e o f the image i n
the x d i r e c t i o n
c o n s t a n t th : n a t u r a l := 5 0 ; −− t h r e s h o l d f o r d e t e c t i n g
defective pixels
constant b i t s : n a t u r a l :=8; −−number o f b i t s i n the
p i x e l v a l u e s (8=255)
c o n s t a n t bit_depth : n a t u r a l := 2 ∗∗ b i t s ; −−255 f o r 8 b i t s

type ram_type i s array (0 to 65535) o f i n t e g e r ;

s i g n a l data_array : ram_type ;
end s i z e ;

83
User_logic

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− u s e r _ l o g i c . vhd − e n t i t y / a r c h i t e c t u r e p a i r
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
−− ∗∗ Copyright ( c ) 1995 − 2010 Xilinx , Inc . A l l r i g h t s r e s e r v e d .
∗∗
−− ∗∗

∗∗
−− ∗∗ Xilinx , Inc .
∗∗
−− ∗∗ XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS "
∗∗
−− ∗∗ AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
∗∗
−− ∗∗ SOLUTIONS FOR XILINX DEVICES . BY PROVIDING THIS DESIGN, CODE,
∗∗
−− ∗∗ OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
∗∗
−− ∗∗ APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
∗∗
−− ∗∗ THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF
INFRINGEMENT, ∗∗
−− ∗∗ AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
REQUIRE ∗∗
−− ∗∗ FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
∗∗
−− ∗∗ WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
∗∗
−− ∗∗ IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
∗∗
−− ∗∗ REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
∗∗
−− ∗∗ INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
∗∗
−− ∗∗ FOR A PARTICULAR PURPOSE.
∗∗
−− ∗∗

∗∗
−− ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Filename : u s e r _ l o g i c . vhd
−− Version : 1.00. a
−− D e s c r i p t i o n : User l o g i c .

84
−− Date : F r i May 28 2 3 : 2 1 : 0 9 2010 ( by Create and Import
P e r i p h e r a l Wizard )
−− VHDL Standard : VHDL' 9 3
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Naming Conventions :
−− a c t i v e low s i g n a l s : " ∗_n"
−− clock signals : " c l k " , " clk_div #", " clk_#
x"
−− reset signals : " r s t " , " rst_n "
−− generics : "C_∗ "
−− u s e r d e f i n e d types : " ∗_TYPE"
−− s t a t e machine next s t a t e : " ∗ _ns"
−− s t a t e machine c u r r e n t s t a t e : " ∗ _cs"
−− combinatorial signals : " ∗_com"
−− p i p e l i n e d or r e g i s t e r delay s i g n a l s : " ∗_d#"
−− counter s i g n a l s : " ∗ cnt ∗ "
−− c l o c k en a b l e s i g n a l s : " ∗ _ce"
−− i n t e r n a l v e r s i o n o f output port : " ∗ _i"
−− device pins : " ∗ _pin"
−− ports : "− Names begin with
Uppercase "
−− processes : " ∗_PROCESS"
−− component i n s t a n t i a t i o n s : "<ENTITY_>I_<#|FUNC>"
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

−− DO NOT EDIT BELOW THIS LINE −−−−−−−

library ieee ;
use i e e e . std_logic_1164 . a l l ;
use i e e e . s t d _ l o g i c _ a r i t h . a l l ;
use i e e e . std_logic_unsigned . a l l ;
use IEEE .NUMERIC_STD. a l l ;

l i b r a r y proc_common_v3_00_a ;
use proc_common_v3_00_a . proc_common_pkg . a l l ;

−− DO NOT EDIT ABOVE THIS LINE −−−−−−−

−−USER l i b r a r i e s added here

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Entity s e c t i o n
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− D e f i n i t i o n o f G e n e r i c s :
−− C_SLV_DWIDTH −− Slave i n t e r f a c e data bus width
−− C_NUM_REG −− Number o f s o f t w a r e a c c e s s i b l e
registers
−− C_NUM_INTR −− Number o f i n t e r r u p t event
−−
−− D e f i n i t i o n o f Ports :

85
−− Bus2IP_Clk −− Bus to IP clock
−− Bus2IP_Reset −− Bus to IP reset
−− Bus2IP_Data −− Bus to IP data bus
−− Bus2IP_BE −− Bus to IP byte e n a b l e s
−− Bus2IP_RdCE −− Bus to IP read chip en a b l e
−− Bus2IP_WrCE −− Bus to IP w r i t e chip en a b l e
−− IP2Bus_Data −− IP to Bus data bus
−− IP2Bus_RdAck −− IP to Bus read t r a n s f e r
acknowledgement
−− IP2Bus_WrAck −− IP to Bus w r i t e t r a n s f e r
acknowledgement
−− IP2Bus_Error −− IP to Bus e r r o r r e s p o n s e
−− IP2Bus_IntrEvent −− IP to Bus i n t e r r u p t event
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

entity user_logic i s
generic
(
−− ADD USER GENERICS BELOW THIS LINE −−−−
−−USER g e n e r i c s added here
−− ADD USER GENERICS ABOVE THIS LINE −−−

−− DO NOT EDIT BELOW THIS LINE −−−−−−−−−−−

−− Bus p r o t o c o l parameters , do not add to or d e l e t e
C_SLV_DWIDTH : integer := 3 2 ;
C_NUM_REG : integer := 6 ;
C_NUM_INTR : integer := 1
−− DO NOT EDIT ABOVE THIS LINE −−−−−−−−−
);
port
(
−− ADD USER PORTS BELOW THIS LINE −−−−−−−
−−USER p o r t s added here
−− ADD USER PORTS ABOVE THIS LINE −−−−−−−−−−−−−−−−−−

−− DO NOT EDIT BELOW THIS LINE −−−−−−−−−−−−−−−−−−−−−

−− Bus p r o t o c o l ports , do not add to or d e l e t e
Bus2IP_Clk : in std_logic ;
Bus2IP_Reset : in std_logic ;
Bus2IP_Data : in s t d _ l o g i c _ v e c t o r (0 to
C_SLV_DWIDTH−1) ;
Bus2IP_BE : in s t d _ l o g i c _ v e c t o r (0 to
C_SLV_DWIDTH/8 − 1) ;
Bus2IP_RdCE : in s t d _ l o g i c _ v e c t o r (0 to
C_NUM_REG−1) ;
Bus2IP_WrCE : in s t d _ l o g i c _ v e c t o r (0 to
C_NUM_REG−1) ;
IP2Bus_Data : out s t d _ l o g i c _ v e c t o r (0 to
C_SLV_DWIDTH−1) ;

86
 IP2Bus_RdAck : out std_logic ;
IP2Bus_WrAck : out std_logic ;
IP2Bus_Error : out std_logic ;
IP2Bus_IntrEvent : out s t d _ l o g i c _ v e c t o r (0 to
C_NUM_INTR−1)
−− DO NOT EDIT ABOVE THIS LINE −−−−−−−−−−−−−−−−−−−−−
);

a t t r i b u t e SIGIS : s t r i n g ;
a t t r i b u t e SIGIS o f Bus2IP_Clk : s i g n a l i s "CLK" ;
a t t r i b u t e SIGIS o f Bus2IP_Reset : s i g n a l i s "RST" ;

end e n t i t y u s e r _ l o g i c ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− A r c h i t e c t u r e s e c t i o n
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

a r c h i t e c t u r e IMP o f u s e r _ l o g i c i s

−−USER s i g n a l d e c l a r a t i o n s added here , as needed f o r u s e r l o g i c

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− S i g n a l s f o r u s e r l o g i c s l a v e model s /w a c c e s s i b l e r e g i s t e r
example
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
s i g n a l slv_reg0 : s t d _ l o g i c _ v e c t o r (0 to
C_SLV_DWIDTH−1) ;−− v a l s read by cpu
s i g n a l slv_reg1 : s t d _ l o g i c _ v e c t o r (0 to
C_SLV_DWIDTH−1) ;−− r e s e t w r i t e
s i g n a l slv_reg2 : s t d _ l o g i c _ v e c t o r (0 to
C_SLV_DWIDTH−1) ;−− r e s e t read
s i g n a l slv_reg3 : s t d _ l o g i c _ v e c t o r (0 to
C_SLV_DWIDTH−1) ;−− d i w r i t e
s i g n a l slv_reg4 : s t d _ l o g i c _ v e c t o r (0 to
C_SLV_DWIDTH−1) ;−− d i read
s i g n a l slv_reg5 : s t d _ l o g i c _ v e c t o r (0 to
C_SLV_DWIDTH−1) ;−− value i n
s i g n a l slv_reg_write_sel : s t d _ l o g i c _ v e c t o r (0 to 5) ;
s i g n a l slv_reg_read_sel : s t d _ l o g i c _ v e c t o r (0 to 5) ;
s i g n a l slv_ip2bus_data : s t d _ l o g i c _ v e c t o r (0 to
C_SLV_DWIDTH−1) ;
s i g n a l slv_read_ack : std_logic ;
s i g n a l slv_write_ack : std_logic ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− S i g n a l s f o r u s e r l o g i c i n t e r r u p t example
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
s i g n a l intr_counter : std_logic ;

87
 signal reset_wr : std_logic ;
signal output : s t d _ l o g i c _ v e c t o r (31 downto 0) ;
signal clk : std_logic ;
signal rst : std_logic ;

component c t r l
port (
Bus2IP_Clk : in std_logic ;
output : out s t d _ l o g i c _ v e c t o r (31 downto 0) ;
Bus2IP_Reset : i n s t d _ l o g i c
);
end component ;
begin

reset_wr <= slv_reg0 ( 0 ) ;

−−USER l o g i c implementation added here

read_values : p r o c e s s ( Bus2IP_Clk ) i s
v a r i a b l e i : i n t e g e r := 0 ;
begin
i f ( r i s i n g _ e d g e ( Bus2IP_Clk ) ) then
i f ( Bus2IP_Reset = ' 1 ' ) then
i n t r _ c o u n t e r <= ' 0 ' ;
else
i n t r _ c o u n t e r <= ' 1 ' ;
i f ( reset_wr = ' 1 ' ) then
i n t r _ c o u n t e r <= ' 0 ' ;
end i f ;
end i f ;
end i f ;

end p r o c e s s ;

IP2Bus_IntrEvent ( 0 ) <= i n t r _ c o u n t e r ;

−−−−−−−−−−−−−−−−−−−−−−−−−
−− Example code to read / w r i t e u s e r l o g i c s l a v e model s /w a c c e s s i b l e
registers
−−
−− Note :
−− The example code p r e s e n t e d here i s to show you one way o f
reading / writing
−− s o f t w a r e a c c e s s i b l e r e g i s t e r s implemented i n the u s e r l o g i c
s l a v e model .

88
−− Each b i t o f the Bus2IP_WrCE/Bus2IP_RdCE s i g n a l s i s c o n f i g u r e d to
correspond
−− to one s o f t w a r e a c c e s s i b l e r e g i s t e r by the top l e v e l template .
For example ,
−− i f you have f o u r 32 b i t s o f t w a r e a c c e s s i b l e r e g i s t e r s i n the
user logic ,
−− you are b a s i c a l l y o p e r a t i n g on the f o l l o w i n g memory mapped
registers :
−−
−− Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped R e g i s t e r
−− "1000" C_BASEADDR + 0x0
−− "0100" C_BASEADDR + 0x4
−− "0010" C_BASEADDR + 0x8
−− "0001" C_BASEADDR + 0xC
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
slv_reg_write_sel <= Bus2IP_WrCE(0 to 5) ;
slv_reg_read_sel <= Bus2IP_RdCE(0 to 5) ;
slv_write_ack <= Bus2IP_WrCE( 0 ) or Bus2IP_WrCE( 1 ) or
Bus2IP_WrCE( 2 ) or Bus2IP_WrCE( 3 ) or Bus2IP_WrCE( 4 ) or
Bus2IP_WrCE( 5 ) ;
slv_read_ack <= Bus2IP_RdCE ( 0 ) or Bus2IP_RdCE ( 1 ) or
Bus2IP_RdCE ( 2 ) or Bus2IP_RdCE ( 3 ) or Bus2IP_RdCE ( 4 ) or
Bus2IP_RdCE ( 5 ) ;

−− implement s l a v e model s o f t w a r e a c c e s s i b l e r e g i s t e r ( s )
SLAVE_REG_WRITE_PROC : p r o c e s s ( Bus2IP_Clk ) i s
begin

i f Bus2IP_Clk ' event and Bus2IP_Clk = ' 1 ' then

i f Bus2IP_Reset = ' 1 ' then
slv_reg5 <= ( o t h e r s => ' 0 ' ) ;
else
c a s e slv_reg_write_sel i s
when " 100000 " =>
f o r byte_index i n 0 to (C_SLV_DWIDTH/8) −1 loop
i f ( Bus2IP_BE( byte_index ) = ' 1 ' ) then
slv_reg0 ( byte_index ∗ 8 to byte_index ∗ 8+7) <=
Bus2IP_Data ( byte_index ∗ 8 to byte_index ∗ 8+7) ;
end i f ;
end loop ;
when " 010000 " =>
f o r byte_index i n 0 to (C_SLV_DWIDTH/8) −1 loop
i f ( Bus2IP_BE( byte_index ) = ' 1 ' ) then
slv_reg1 ( byte_index ∗ 8 to byte_index ∗ 8+7) <=
Bus2IP_Data ( byte_index ∗ 8 to byte_index ∗ 8+7) ;
end i f ;
end loop ;
when " 001000 " =>

89
 f o r byte_index i n 0 to (C_SLV_DWIDTH/8) −1 loop
i f ( Bus2IP_BE( byte_index ) = ' 1 ' ) then
slv_reg2 ( byte_index ∗ 8 to byte_index ∗ 8+7) <=
Bus2IP_Data ( byte_index ∗ 8 to byte_index ∗ 8+7) ;
end i f ;
end loop ;
when " 000100 " =>
f o r byte_index i n 0 to (C_SLV_DWIDTH/8) −1 loop
i f ( Bus2IP_BE( byte_index ) = ' 1 ' ) then
slv_reg3 ( byte_index ∗ 8 to byte_index ∗ 8+7) <=
Bus2IP_Data ( byte_index ∗ 8 to byte_index ∗ 8+7) ;
end i f ;
end loop ;
when " 000010 " =>
f o r byte_index i n 0 to (C_SLV_DWIDTH/8) −1 loop
i f ( Bus2IP_BE( byte_index ) = ' 1 ' ) then
slv_reg4 ( byte_index ∗ 8 to byte_index ∗ 8+7) <=
Bus2IP_Data ( byte_index ∗ 8 to byte_index ∗ 8+7) ;
end i f ;
end loop ;
when " 000001 " =>
f o r byte_index i n 0 to (C_SLV_DWIDTH/8) −1 loop
i f ( Bus2IP_BE( byte_index ) = ' 1 ' ) then
slv_reg5 ( byte_index ∗ 8 to byte_index ∗ 8+7) <=
Bus2IP_Data ( byte_index ∗ 8 to byte_index ∗ 8+7) ;
end i f ;
end loop ;
when o t h e r s => n u l l ;
end c a s e ;
end i f ;
end i f ;

end p r o c e s s SLAVE_REG_WRITE_PROC;

−− implement s l a v e model s o f t w a r e a c c e s s i b l e r e g i s t e r ( s ) read mux

SLAVE_REG_READ_PROC : p r o c e s s ( slv_reg_read_sel , slv_reg0 , slv_reg1
, slv_reg2 , output , slv_reg4 , slv_reg5 ) i s
begin

c a s e slv_reg_read_sel i s
when " 100000 " => slv_ip2bus_data <= slv_reg0 ;
when " 010000 " => slv_ip2bus_data <= output ;
when " 001000 " => slv_ip2bus_data <= slv_reg2 ;
when " 000100 " => slv_ip2bus_data <= slv_reg3 ;
when " 000010 " => slv_ip2bus_data <= slv_reg4 ;
when " 000001 " => slv_ip2bus_data <= slv_reg5 ;
when o t h e r s => slv_ip2bus_data <= ( o t h e r s => ' 0 ' ) ;
end c a s e ;

90
 end p r o c e s s SLAVE_REG_READ_PROC;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Example code to d r i v e IP to Bus s i g n a l s
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
IP2Bus_Data <= slv_ip2bus_data ;

IP2Bus_WrAck <= slv_write_ack ;

IP2Bus_RdAck <= slv_read_ack ;
IP2Bus_Error <= ' 0 ' ;

end IMP ;

91
My_custom_ip_register

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− my_custom_ip_register . vhd − e n t i t y / a r c h i t e c t u r e p a i r
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− IMPORTANT:
−− DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS .
−−
−− SEARCH FOR −−USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
−−
−− TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
−− PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
−− OF THE USER_LOGIC ENTITY.
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
−− ∗∗ Copyright ( c ) 1995 − 2010 Xilinx , Inc . A l l r i g h t s r e s e r v e d .
∗∗
−− ∗∗

∗∗
−− ∗∗ Xilinx , Inc .
∗∗
−− ∗∗ XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS "
∗∗
−− ∗∗ AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
∗∗
−− ∗∗ SOLUTIONS FOR XILINX DEVICES . BY PROVIDING THIS DESIGN, CODE,
∗∗
−− ∗∗ OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
∗∗
−− ∗∗ APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
∗∗
−− ∗∗ THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF
INFRINGEMENT, ∗∗
−− ∗∗ AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
REQUIRE ∗∗
−− ∗∗ FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
∗∗
−− ∗∗ WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
∗∗
−− ∗∗ IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
∗∗
−− ∗∗ REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
∗∗
−− ∗∗ INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
∗∗
−− ∗∗ FOR A PARTICULAR PURPOSE.
∗∗

92
−− ∗∗

∗∗
−− ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Filename : my_custom_ip_register . vhd
−− Version : 9.00. a
−− D e s c r i p t i o n : Top l e v e l design , i n s t a n t i a t e s l i b r a r y
components and u s e r l o g i c .
−− Date : Sat May 29 1 2 : 4 8 : 0 0 2010 ( by Create and Import
P e r i p h e r a l Wizard )
−− VHDL Standard : VHDL' 9 3
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Naming Conventions :
−− a c t i v e low s i g n a l s : " ∗_n"
−− clock signals : " c l k " , " clk_div #", " clk_#
x"
−− reset signals : " r s t " , " rst_n "
−− generics : "C_∗ "
−− u s e r d e f i n e d types : " ∗_TYPE"
−− s t a t e machine next s t a t e : " ∗ _ns"
−− s t a t e machine c u r r e n t s t a t e : " ∗ _cs"
−− combinatorial signals : " ∗_com"
−− p i p e l i n e d or r e g i s t e r delay s i g n a l s : " ∗_d#"
−− counter s i g n a l s : " ∗ cnt ∗ "
−− c l o c k en a b l e s i g n a l s : " ∗ _ce"
−− i n t e r n a l v e r s i o n o f output port : " ∗ _i"
−− device pins : " ∗ _pin"
−− ports : "− Names begin with
Uppercase "
−− processes : " ∗_PROCESS"
−− component i n s t a n t i a t i o n s : "<ENTITY_>I_<#|FUNC>"
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

library ieee ;
use i e e e . std_logic_1164 . a l l ;
use i e e e . s t d _ l o g i c _ a r i t h . a l l ;
use i e e e . std_logic_unsigned . a l l ;

l i b r a r y proc_common_v3_00_a ;
use proc_common_v3_00_a . proc_common_pkg . a l l ;
use proc_common_v3_00_a . ipif_pkg . a l l ;

l i b r a r y interrupt_control_v2_01_a ;
use interrupt_control_v2_01_a . i n t e r r u p t _ c o n t r o l ;

l i b r a r y plbv46_slave_single_v1_01_a ;
use plbv46_slave_single_v1_01_a . plbv46_slave_single ;

93
l i b r a r y my_custom_ip_register_v9_00_a ;
use my_custom_ip_register_v9_00_a . u s e r _ l o g i c ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Entity s e c t i o n
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− D e f i n i t i o n o f G e n e r i c s :
−− C_BASEADDR −− PLBv46 slave : base a d d r e s s
−− C_HIGHADDR −− PLBv46 slave : high a d d r e s s
−− C_SPLB_AWIDTH −− PLBv46 slave : a d d r e s s bus width
−− C_SPLB_DWIDTH −− PLBv46 slave : data bus width
−− C_SPLB_NUM_MASTERS −− PLBv46 slave : Number o f masters
−− C_SPLB_MID_WIDTH −− PLBv46 slave : master ID bus
width
−− C_SPLB_NATIVE_DWIDTH −− PLBv46 s l a v e : i n t e r n a l n a t i v e
data bus width
−− C_SPLB_P2P −− PLBv46 s l a v e : p o i n t to p o i n t
i n t e r c o n n e c t scheme
−− C_SPLB_SUPPORT_BURSTS −− PLBv46 s l a v e : support b u r s t s
−− C_SPLB_SMALLEST_MASTER −− PLBv46 s l a v e : width o f the
s m a l l e s t master
−− C_SPLB_CLK_PERIOD_PS −− PLBv46 s l a v e : bus c l o c k i n
picoseconds
−− C_INCLUDE_DPHASE_TIMER −− PLBv46 s l a v e : Data Phase Timer
c o n f i g u r a t i o n ; 0 = e x c l u d e timer , 1 = i n c l u d e timer
−− C_FAMILY −− X i l i n x FPGA f a m i l y
−−
−− D e f i n i t i o n o f Ports :
−− SPLB_Clk −− PLB main bus c l o c k
−− SPLB_Rst −− PLB main bus r e s e t
−− PLB_ABus −− PLB a d d r e s s bus
−− PLB_UABus −− PLB upper a d d r e s s bus
−− PLB_PAValid −− PLB primary a d d r e s s v a l i d
indicator
−− PLB_SAValid −− PLB secondary a d d r e s s v a l i d
indicator
−− PLB_rdPrim −− PLB secondary to primary read
request indicator
−− PLB_wrPrim −− PLB secondary to primary w r i t e
request indicator
−− PLB_masterID −− PLB c u r r e n t master i d e n t i f i e r
−− PLB_abort −− PLB abort r e q u e s t i n d i c a t o r
−− PLB_busLock −− PLB bus l o c k
−− PLB_RNW −− PLB read / not w r i t e
−− PLB_BE −− PLB byte e n a b l e s
−− PLB_MSize −− PLB master data bus s i z e
−− PLB_size −− PLB transfer size
−− PLB_type −− PLB t r a n s f e r type

94
−− PLB_lockErr −− PLB l o c k e r r o r i n d i c a t o r
−− PLB_wrDBus −− PLB w r i t e data bus
−− PLB_wrBurst −− PLB b u r s t w r i t e t r a n s f e r
indicator
−− PLB_rdBurst −− PLB b u r s t read t r a n s f e r
indicator
−− PLB_wrPendReq −− PLB w r i t e pending bus r e q u e s t
indicator
−− PLB_rdPendReq −− PLB read pending bus r e q u e s t
indicator
−− PLB_wrPendPri −− PLB w r i t e pending r e q u e s t
priority
−− PLB_rdPendPri −− PLB read pending r e q u e s t
priority
−− PLB_reqPri −− PLB c u r r e n t r e q u e s t p r i o r i t y
−− PLB_TAttribute −− PLB t r a n s f e r a t t r i b u t e
−− Sl_addrAck −− Slave a d d r e s s acknowledge
−− Sl_SSize −− Slave data bus s i z e
−− Sl_wait −− Slave wait i n d i c a t o r
−− Sl_rearbitrate −− Slave re − a r b i t r a t e bus i n d i c a t o r
−− Sl_wrDAck −− Slave w r i t e data acknowledge
−− Sl_wrComp −− Slave w r i t e t r a n s f e r complete
indicator
−− Sl_wrBTerm −− Slave t e r m i n a t e w r i t e b u r s t
transfer
−− Sl_rdDBus −− Slave read data bus
−− Sl_rdWdAddr −− Slave read word a d d r e s s
−− Sl_rdDAck −− Slave read data acknowledge
−− Sl_rdComp −− Slave read t r a n s f e r complete
indicator
−− Sl_rdBTerm −− Slave t e r m i n a t e read b u r s t
transfer
−− Sl_MBusy −− Slave busy i n d i c a t o r
−− Sl_MWrErr −− Slave w r i t e e r r o r i n d i c a t o r
−− Sl_MRdErr −− Slave read e r r o r i n d i c a t o r
−− Sl_MIRQ −− Slave i n t e r r u p t i n d i c a t o r
−− IP2INTC_Irpt −− I n t e r r u p t output to p r o c e s s o r
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

e n t i t y my_custom_ip_register i s
generic
(
−− ADD USER GENERICS BELOW THIS LINE −−−−−−−−−−−−−−−
−−USER g e n e r i c s added here
−− ADD USER GENERICS ABOVE THIS LINE −−−−−−−−−−−−−−−

−− DO NOT EDIT BELOW THIS LINE −−−−−−−−−−−−−−−−−−−−−

−− Bus p r o t o c o l parameters , do not add to or d e l e t e

95
 C_BASEADDR : std_logic_vector := X"
FFFFFFFF" ;
C_HIGHADDR : std_logic_vector := X"
00000000 " ;
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 1 00 0 0 ;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := " virtex5
"
−− DO NOT EDIT ABOVE THIS LINE −−−−−−−−−−−−−−−−−−−−−
);
port
(
−− ADD USER PORTS BELOW THIS LINE −−−−−−−−−−−−−−−−−−
−−USER p o r t s added here
−− ADD USER PORTS ABOVE THIS LINE −−−−−−−−−−−−−−−−−−

−− DO NOT EDIT BELOW THIS LINE −−−−−−−−−−−−−−−−−−−−−

−− Bus p r o t o c o l ports , do not add to or d e l e t e
SPLB_Clk : in std_logic ;
SPLB_Rst : in std_logic ;
PLB_ABus : in s t d _ l o g i c _ v e c t o r (0 to 31) ;
PLB_UABus : in s t d _ l o g i c _ v e c t o r (0 to 31) ;
PLB_PAValid : in std_logic ;
PLB_SAValid : in std_logic ;
PLB_rdPrim : in std_logic ;
PLB_wrPrim : in std_logic ;
PLB_masterID : in s t d _ l o g i c _ v e c t o r (0 to
C_SPLB_MID_WIDTH−1) ;
PLB_abort : in std_logic ;
PLB_busLock : in std_logic ;
PLB_RNW : in std_logic ;
PLB_BE : in s t d _ l o g i c _ v e c t o r (0 to
C_SPLB_DWIDTH/8 − 1) ;
PLB_MSize : in s t d _ l o g i c _ v e c t o r (0 to 1) ;
PLB_size : in s t d _ l o g i c _ v e c t o r (0 to 3) ;
PLB_type : in s t d _ l o g i c _ v e c t o r (0 to 2) ;
PLB_lockErr : in std_logic ;
PLB_wrDBus : in s t d _ l o g i c _ v e c t o r (0 to
C_SPLB_DWIDTH−1) ;
PLB_wrBurst : in std_logic ;
PLB_rdBurst : in std_logic ;

96
 PLB_wrPendReq : in std_logic ;
PLB_rdPendReq : in std_logic ;
PLB_wrPendPri : in s t d _ l o g i c _ v e c t o r (0 to 1) ;
PLB_rdPendPri : in s t d _ l o g i c _ v e c t o r (0 to 1) ;
PLB_reqPri : in s t d _ l o g i c _ v e c t o r (0 to 1) ;
PLB_TAttribute : in s t d _ l o g i c _ v e c t o r (0 to 15) ;
Sl_addrAck : out std_logic ;
Sl_SSize : out s t d _ l o g i c _ v e c t o r (0 to 1) ;
Sl_wait : out std_logic ;
Sl_rearbitrate : out std_logic ;
Sl_wrDAck : out std_logic ;
Sl_wrComp : out std_logic ;
Sl_wrBTerm : out std_logic ;
Sl_rdDBus : out s t d _ l o g i c _ v e c t o r (0 to
C_SPLB_DWIDTH−1) ;
Sl_rdWdAddr : out s t d _ l o g i c _ v e c t o r (0 to 3) ;
Sl_rdDAck : out std_logic ;
Sl_rdComp : out std_logic ;
Sl_rdBTerm : out std_logic ;
Sl_MBusy : out s t d _ l o g i c _ v e c t o r (0 to
C_SPLB_NUM_MASTERS−1) ;
Sl_MWrErr : out s t d _ l o g i c _ v e c t o r (0 to
C_SPLB_NUM_MASTERS−1) ;
Sl_MRdErr : out s t d _ l o g i c _ v e c t o r (0 to
C_SPLB_NUM_MASTERS−1) ;
Sl_MIRQ : out s t d _ l o g i c _ v e c t o r (0 to
C_SPLB_NUM_MASTERS−1) ;
IP2INTC_Irpt : out s t d _ l o g i c
−− DO NOT EDIT ABOVE THIS LINE −−−−−−−−−−−−−−−−−−−−−
);

attribute SIGIS : string ;

attribute SIGIS o f SPLB_Clk : s i g n a l i s "CLK" ;
attribute SIGIS o f SPLB_Rst : s i g n a l i s "RST" ;
attribute SIGIS o f IP2INTC_Irpt : s i g n a l i s "INTR_LEVEL_HIGH" ;

end e n t i t y my_custom_ip_register ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− A r c h i t e c t u r e s e c t i o n
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

a r c h i t e c t u r e IMP o f my_custom_ip_register i s

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Array o f base / high a d d r e s s p a i r s f o r each a d d r e s s range
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
c o n s t a n t ZERO_ADDR_PAD : s t d _ l o g i c _ v e c t o r (0 to 31)
:= ( o t h e r s => ' 0 ' ) ;

97
c o n s t a n t USER_SLV_BASEADDR : std_logic_vector :=
C_BASEADDR or X" 00000000 " ;
c o n s t a n t USER_SLV_HIGHADDR : std_logic_vector :=
C_BASEADDR or X" 000000FF" ;
c o n s t a n t INTR_BASEADDR : std_logic_vector :=
C_BASEADDR or X" 00000100 " ;
c o n s t a n t INTR_HIGHADDR : std_logic_vector :=
C_BASEADDR or X" 000001FF" ;

c o n s t a n t IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, −− u s e r l o g i c s l a v e space
base a d d r e s s
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, −− u s e r l o g i c s l a v e space
high a d d r e s s
ZERO_ADDR_PAD & INTR_BASEADDR, −− i n t e r r u p t c o n t r o l space
base a d d r e s s
ZERO_ADDR_PAD & INTR_HIGHADDR −− i n t e r r u p t c o n t r o l space
high a d d r e s s
);

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Array o f d e s i r e d number o f chip e n a b l e s f o r each a d d r e s s range
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
c o n s t a n t USER_SLV_NUM_REG : integer :=
6;
c o n s t a n t USER_NUM_REG : integer :=
USER_SLV_NUM_REG;
c o n s t a n t INTR_NUM_CE : integer :=
16;

c o n s t a n t IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2 (USER_SLV_NUM_REG) , −− number o f ce f o r u s e r
l o g i c s l a v e space
1 => INTR_NUM_CE −− number o f ce f o r
i n t e r r u p t c o n t r o l space
);

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Ratio o f bus c l o c k to c o r e c l o c k ( f o r use i n dual c l o c k systems )
−− 1 = r a t i o i s 1 : 1
−− 2 = r a t i o i s 2 : 1
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
c o n s t a n t IPIF_BUS2CORE_CLK_RATIO : integer :=
1;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Width o f the s l a v e data bus (32 only )

98
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
c o n s t a n t USER_SLV_DWIDTH : integer :=
C_SPLB_NATIVE_DWIDTH;

c o n s t a n t IPIF_SLV_DWIDTH : integer :=
C_SPLB_NATIVE_DWIDTH;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Number o f d e v i c e l e v e l i n t e r r u p t s
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
c o n s t a n t INTR_NUM_IPIF_IRPT_SRC : integer :=
4;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Capture mode f o r each IP i n t e r r u p t ( g e n e r a t e d by u s e r l o g i c )
−− 1 = pass through ( non− i n v e r t i n g )
−− 2 = pass through ( i n v e r t i n g )
−− 3 = r e g i s t e r e d l e v e l ( non− i n v e r t i n g )
−− 4 = r e g i s t e r e d l e v e l ( i n v e r t i n g )
−− 5 = p o s i t i v e edge d e t e c t
−− 6 = n e g a t i v e edge d e t e c t
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
c o n s t a n t USER_NUM_INTR : integer :=
1;
c o n s t a n t USER_INTR_CAPTURE_MODE : integer :=
1;

c o n s t a n t INTR_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_INTR_CAPTURE_MODE
);

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Device p r i o r i t y encoder f e a t u r e i n c l u s i o n / o m i s s i o n
−− t r u e = i n c l u d e p r i o r i t y encoder
−− f a l s e = omit p r i o r i t y encoder
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
c o n s t a n t INTR_INCLUDE_DEV_PENCODER : boolean :=
true ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Device ISC f e a t u r e i n c l u s i o n / o m i s s i o n
−− t r u e = i n c l u d e d e v i c e ISC
−− f a l s e = omit d e v i c e ISC
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
c o n s t a n t INTR_INCLUDE_DEV_ISC : boolean :=
true ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

99
−− Index f o r CS/CE
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
c o n s t a n t USER_SLV_CS_INDEX : integer :=
0;
c o n s t a n t USER_SLV_CE_INDEX : integer :=
calc_start_ce_index (IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX) ;
c o n s t a n t INTR_CS_INDEX : integer :=
1;
c o n s t a n t INTR_CE_INDEX : integer :=
calc_start_ce_index (IPIF_ARD_NUM_CE_ARRAY, INTR_CS_INDEX) ;

c o n s t a n t USER_CE_INDEX : integer :=
USER_SLV_CE_INDEX;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− IP I n t e r c o n n e c t ( IPIC ) s i g n a l d e c l a r a t i o n s
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
s i g n a l ipif_Bus2IP_Clk : std_logic ;
s i g n a l ipif_Bus2IP_Reset : std_logic ;
s i g n a l ipif_IP2Bus_Data : s t d _ l o g i c _ v e c t o r (0 to
IPIF_SLV_DWIDTH−1) ;
s i g n a l ipif_IP2Bus_WrAck : std_logic ;
s i g n a l ipif_IP2Bus_RdAck : std_logic ;
s i g n a l ipif_IP2Bus_Error : std_logic ;
s i g n a l ipif_Bus2IP_Addr : s t d _ l o g i c _ v e c t o r (0 to
C_SPLB_AWIDTH−1) ;
s i g n a l ipif_Bus2IP_Data : s t d _ l o g i c _ v e c t o r (0 to
IPIF_SLV_DWIDTH−1) ;
s i g n a l ipif_Bus2IP_RNW : std_logic ;
s i g n a l ipif_Bus2IP_BE : s t d _ l o g i c _ v e c t o r (0 to
IPIF_SLV_DWIDTH/8 − 1) ;
s i g n a l ipif_Bus2IP_CS : s t d _ l o g i c _ v e c t o r (0 to ( (
IPIF_ARD_ADDR_RANGE_ARRAY' l e n g t h ) /2) −1) ;
s i g n a l ipif_Bus2IP_RdCE : s t d _ l o g i c _ v e c t o r (0 to
calc_num_ce (IPIF_ARD_NUM_CE_ARRAY) −1) ;
s i g n a l ipif_Bus2IP_WrCE : s t d _ l o g i c _ v e c t o r (0 to
calc_num_ce (IPIF_ARD_NUM_CE_ARRAY) −1) ;
s i g n a l intr_IPIF_Reg_Interrupts : s t d _ l o g i c _ v e c t o r (0 to 1) ;
s i g n a l intr_IPIF_Lvl_Interrupts : s t d _ l o g i c _ v e c t o r (0 to
INTR_NUM_IPIF_IRPT_SRC−1) ;
s i g n a l intr_IP2Bus_Data : s t d _ l o g i c _ v e c t o r (0 to
IPIF_SLV_DWIDTH−1) ;
s i g n a l intr_IP2Bus_WrAck : std_logic ;
s i g n a l intr_IP2Bus_RdAck : std_logic ;
s i g n a l intr_IP2Bus_Error : std_logic ;
s i g n a l user_Bus2IP_RdCE : s t d _ l o g i c _ v e c t o r (0 to
USER_NUM_REG−1) ;
s i g n a l user_Bus2IP_WrCE : s t d _ l o g i c _ v e c t o r (0 to
USER_NUM_REG−1) ;

100
 s i g n a l user_IP2Bus_Data : s t d _ l o g i c _ v e c t o r (0 to
USER_SLV_DWIDTH−1) ;
s i g n a l user_IP2Bus_RdAck : std_logic ;
s i g n a l user_IP2Bus_WrAck : std_logic ;
s i g n a l user_IP2Bus_Error : std_logic ;
s i g n a l user_IP2Bus_IntrEvent : s t d _ l o g i c _ v e c t o r (0 to
USER_NUM_INTR−1) ;

begin

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− i n s t a n t i a t e plbv46_slave_single
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
PLBV46_SLAVE_SINGLE_I : e n t i t y plbv46_slave_single_v1_01_a .
plbv46_slave_single
g e n e r i c map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk ,
SPLB_Rst => SPLB_Rst ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid ,
PLB_SAValid => PLB_SAValid ,
PLB_rdPrim => PLB_rdPrim ,
PLB_wrPrim => PLB_wrPrim ,
PLB_masterID => PLB_masterID ,
PLB_abort => PLB_abort ,
PLB_busLock => PLB_busLock ,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize ,
PLB_size => PLB_size ,
PLB_type => PLB_type ,
PLB_lockErr => PLB_lockErr ,
PLB_wrDBus => PLB_wrDBus,

101
 PLB_wrBurst => PLB_wrBurst ,
PLB_rdBurst => PLB_rdBurst ,
PLB_wrPendReq => PLB_wrPendReq ,
PLB_rdPendReq => PLB_rdPendReq ,
PLB_wrPendPri => PLB_wrPendPri ,
PLB_rdPendPri => PLB_rdPendPri ,
PLB_reqPri => PLB_reqPri ,
PLB_TAttribute => PLB_TAttribute ,
Sl_addrAck => Sl_addrAck ,
Sl_SSize => Sl_SSize ,
Sl_wait => Sl_wait ,
Sl_rearbitrate => Sl_rearbitrate ,
Sl_wrDAck => Sl_wrDAck ,
Sl_wrComp => Sl_wrComp ,
Sl_wrBTerm => Sl_wrBTerm ,
Sl_rdDBus => Sl_rdDBus ,
Sl_rdWdAddr => Sl_rdWdAddr ,
Sl_rdDAck => Sl_rdDAck ,
Sl_rdComp => Sl_rdComp ,
Sl_rdBTerm => Sl_rdBTerm ,
Sl_MBusy => Sl_MBusy ,
Sl_MWrErr => Sl_MWrErr ,
Sl_MRdErr => Sl_MRdErr ,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk ,
Bus2IP_Reset => ipif_Bus2IP_Reset ,
IP2Bus_Data => ipif_IP2Bus_Data ,
IP2Bus_WrAck => ipif_IP2Bus_WrAck ,
IP2Bus_RdAck => ipif_IP2Bus_RdAck ,
IP2Bus_Error => ipif_IP2Bus_Error ,
Bus2IP_Addr => ipif_Bus2IP_Addr ,
Bus2IP_Data => ipif_Bus2IP_Data ,
Bus2IP_RNW => ipif_Bus2IP_RNW ,
Bus2IP_BE => ipif_Bus2IP_BE ,
Bus2IP_CS => ipif_Bus2IP_CS ,
Bus2IP_RdCE => ipif_Bus2IP_RdCE ,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− i n s t a n t i a t e i n t e r r u p t _ c o n t r o l
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
INTERRUPT_CONTROL_I : e n t i t y interrupt_control_v2_01_a .
interrupt_control
g e n e r i c map
(
C_NUM_CE => INTR_NUM_CE,
C_NUM_IPIF_IRPT_SRC => INTR_NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => INTR_IP_INTR_MODE_ARRAY,

102
 C_INCLUDE_DEV_PENCODER => INTR_INCLUDE_DEV_PENCODER,
C_INCLUDE_DEV_ISC => INTR_INCLUDE_DEV_ISC,
C_IPIF_DWIDTH => IPIF_SLV_DWIDTH
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk ,
Bus2IP_Reset => ipif_Bus2IP_Reset ,
Bus2IP_Data => ipif_Bus2IP_Data ,
Bus2IP_BE => ipif_Bus2IP_BE ,
Interrupt_RdCE => ipif_Bus2IP_RdCE (
INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE−1) ,
Interrupt_WrCE => ipif_Bus2IP_WrCE (
INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE−1) ,
IPIF_Reg_Interrupts => intr_IPIF_Reg_Interrupts ,
IPIF_Lvl_Interrupts => intr_IPIF_Lvl_Interrupts ,
IP2Bus_IntrEvent => user_IP2Bus_IntrEvent ,
Intr2Bus_DevIntr => IP2INTC_Irpt ,
Intr2Bus_DBus => intr_IP2Bus_Data ,
Intr2Bus_WrAck => intr_IP2Bus_WrAck ,
Intr2Bus_RdAck => intr_IP2Bus_RdAck ,
Intr2Bus_Error => intr_IP2Bus_Error ,
Intr2Bus_Retry => open ,
Intr2Bus_ToutSup => open
);

−− f e e d r e g i s t e r e d and l e v e l −pass −through i n t e r r u p t s i n t o Device

ISC i f e x i s t s , o t h e r w i s e ignored
intr_IPIF_Reg_Interrupts ( 0 ) <= ' 0 ' ;
intr_IPIF_Reg_Interrupts ( 1 ) <= ' 0 ' ;
intr_IPIF_Lvl_Interrupts ( 0 ) <= ' 0 ' ;
intr_IPIF_Lvl_Interrupts ( 1 ) <= ' 0 ' ;
intr_IPIF_Lvl_Interrupts ( 2 ) <= ' 0 ' ;
intr_IPIF_Lvl_Interrupts ( 3 ) <= ' 0 ' ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− i n s t a n t i a t e User Logic
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
USER_LOGIC_I : e n t i t y my_custom_ip_register_v9_00_a . u s e r _ l o g i c
g e n e r i c map
(
−− MAP USER GENERICS BELOW THIS LINE −−−−−−−−−−−−−−−
−−USER g e n e r i c s mapped here
−− MAP USER GENERICS ABOVE THIS LINE −−−−−−−−−−−−−−−

C_SLV_DWIDTH => USER_SLV_DWIDTH,

C_NUM_REG => USER_NUM_REG,
C_NUM_INTR => USER_NUM_INTR
)

103
 port map
(
−− MAP USER PORTS BELOW THIS LINE −−−−−−−−−−−−−−−−−−
−−USER p o r t s mapped here
−− MAP USER PORTS ABOVE THIS LINE −−−−−−−−−−−−−−−−−−

Bus2IP_Clk => ipif_Bus2IP_Clk ,

Bus2IP_Reset => ipif_Bus2IP_Reset ,
Bus2IP_Data => ipif_Bus2IP_Data ,
Bus2IP_BE => ipif_Bus2IP_BE ,
Bus2IP_RdCE => user_Bus2IP_RdCE ,
Bus2IP_WrCE => user_Bus2IP_WrCE ,
IP2Bus_Data => user_IP2Bus_Data ,
IP2Bus_RdAck => user_IP2Bus_RdAck ,
IP2Bus_WrAck => user_IP2Bus_WrAck ,
IP2Bus_Error => user_IP2Bus_Error ,
IP2Bus_IntrEvent => user_IP2Bus_IntrEvent
);

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− connect i n t e r n a l s i g n a l s
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
IP2BUS_DATA_MUX_PROC : p r o c e s s ( ipif_Bus2IP_CS , user_IP2Bus_Data ,
intr_IP2Bus_Data ) i s
begin

c a s e ipif_Bus2IP_CS i s
when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data ;
when "01" => ipif_IP2Bus_Data <= intr_IP2Bus_Data ;
when o t h e r s => ipif_IP2Bus_Data <= ( o t h e r s => ' 0 ' ) ;
end c a s e ;

end p r o c e s s IP2BUS_DATA_MUX_PROC;

ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or intr_IP2Bus_WrAck ;

ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck or intr_IP2Bus_RdAck ;
ipif_IP2Bus_Error <= user_IP2Bus_Error or intr_IP2Bus_Error ;

user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE (USER_CE_INDEX to USER_CE_INDEX

+USER_NUM_REG−1) ;
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE (USER_CE_INDEX to USER_CE_INDEX
+USER_NUM_REG−1) ;

end IMP ;

104
.1.2 VHDL Test Benches
Median

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− T i t l e : median_tb
−− Design : defect_pixel_corr
−− Author : Henrik Backe−Hansen
−− Company : NTNU / Aptina Norway
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− F i l e : median_mod_tb . vhd
−− Generated : Tue Jan 26 2 3 : 2 4 : 3 1 2010
−− From : interface description f i l e
−− By : I t f 2 V h d l ver . 1 . 2 0
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− D e s c r i p t i o n :
−−This t e s t b e n c h the input w i l l be e n t e r e d one−by−by and compared
with the data i n a c e r t a i n p o s i t i o n i n the data_golden array
−−The d i s p l a y w i l l show ERROR i f the input value does not match the
data_golden value f o r that p o s i t i o n .
−−A FAILURE message w i l l appear i f the median value i s d i f f e r e n t from
the median c a l c u l a t e d f o r the data_golden array ( 1 2 3 )
−−a FAILURE message w i l l be shown s a y i n g " s i m u l a t i o n completed
c o r r e c t l y without e r r o r " to i n d i c a t e that the s i m u l a t i o n has
completed
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

l i b r a r y IEEE ;
use IEEE . std_logic_1164 . a l l ;
use work . s i z e . a l l ;

e n t i t y median_testbench i s
end e n t i t y ;

a r c h i t e c t u r e s t r u c t o f median_testbench i s
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−Component d e c l a r a t i o n
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
component median_mod
port ( −−component d e c l a r a t i o n
clk : in std_logic ;
rst : in std_logic ;
data_in : in integer ;
e n ab l e : in std_logic ;
done : out s t d _ l o g i c ;

105
 median : out integer
);
end component ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− S i g n a l d e c l a r a t i o n
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
signal clk : std_logic := '0 ';
signal rst : std_logic := '0 ';
signal data_in : integer := 0 ;
signal e n ab l e : std_logic := ' 0 ' ;
signal done : std_logic := ' 0 ' ;
signal median : integer := 0 ;

type data_format i s array (8 downto 0) o f i n t e g e r range 0 to

bit_depth ; −− input data array s i z e setup
s i g n a l data_golden : data_format :=
(127 ,105 ,141 ,127 ,127 ,127 ,127 ,113 ,115) ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−Device under t e s t (DUT) i n s t a n s i a t i o n
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
begin
DUT: median_mod
port map(
clk => clk ,
rst => r s t ,
data_in => data_in ,
e n ab l e => enable ,
done => done ,
median => median
);

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− p r o c e s s to g e n e r a t e the c l o c k f o r 100MHz
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
clk_gen : p r o c e s s
begin
wait f o r 5 ns ;
c l k <= not ( c l k ) ;
end p r o c e s s ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− S t i m u l i
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
test_bench : p r o c e s s
v a r i a b l e t e s t : i n t e g e r := 0 ;
v a r i a b l e t e s t 2 : i n t e g e r := 0 ;
begin

106
 r s t <= ' 1 ' ;
wait f o r 20 ns ;
r s t <= ' 0 ' ;
wait f o r 20 ns ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− l a t c h i n g i n input v a l u e s
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
e n ab l e <= ' 1 ' ; −−data ( 0 ) <= 115
data_in <= 1 1 5 ;
wait f o r 20 ns ;
e n ab l e <= ' 0 ' ;
wait f o r 20 ns ;
a s s e r t data_golden ( 0 ) = data_in
r e p o r t " data_golden ( 0 ) d i f f e r s from input 0"
severity error ;

e n ab l e <= ' 1 ' ; −−data ( 1 ) <= 123

data_in <= 1 1 3 ;
wait f o r 20 ns ;
e n ab l e <= ' 0 ' ;
wait f o r 20 ns ;
a s s e r t data_in = data_golden ( 1 )
r e p o r t " data_golden ( 1 ) d i f f e r s from input 1"
severity error ;

e n ab l e <= ' 1 ' ; −−data ( 2 ) <= 105

data_in <= 1 2 7 ;
wait f o r 20 ns ;
e n ab l e <= ' 0 ' ;
wait f o r 20 ns ;
a s s e r t data_in = data_golden ( 2 )
r e p o r t " data_golden ( 2 ) d i f f e r s from input 2"
severity error ;

e n ab l e <= ' 1 ' ; −−data ( 3 ) <= 129

data_in <= 1 2 7 ;
wait f o r 20 ns ;
e n ab l e <= ' 0 ' ;
wait f o r 20 ns ;
a s s e r t data_in = data_golden ( 3 )
r e p o r t " data_golden ( 3 ) d i f f e r s from input 3"
severity error ;

e n ab l e <= ' 1 ' ; −−data ( 4 ) <= 249

107
 data_in <= 1 2 7 ;
wait f o r 20 ns ;
e n ab l e <= ' 0 ' ;
wait f o r 20 ns ;
a s s e r t data_in = data_golden ( 4 )
r e p o r t " data_golden ( 4 ) d i f f e r s from input 4"
severity error ;

e n ab l e <= ' 1 ' ; −−data ( 5 ) <= 135

data_in <= 1 2 7 ;
wait f o r 20 ns ;
e n ab l e <= ' 0 ' ;
wait f o r 20 ns ;
a s s e r t data_in = data_golden ( 5 )
r e p o r t " data_golden ( 5 ) d i f f e r s from input 5"
severity error ;

e n ab l e <= ' 1 ' ; −−data ( 6 ) <= 102

data_in <= 1 4 1 ;
wait f o r 20 ns ;
e n ab l e <= ' 0 ' ;
wait f o r 20 ns ;
a s s e r t data_in = data_golden ( 6 )
r e p o r t " data_golden ( 6 ) d i f f e r s from input 6"
severity error ;

e n ab l e <= ' 1 ' ; −−data ( 7 ) <= 136

data_in <= 1 0 5 ;
wait f o r 20 ns ;
e n ab l e <= ' 0 ' ;
wait f o r 20 ns ;
a s s e r t data_in = data_golden ( 7 )
r e p o r t " data_golden ( 7 ) d i f f e r s from input 7"
severity error ;

e n ab l e <= ' 1 ' ; −−data ( 8 ) <= 117

data_in <= 1 2 7 ;
wait f o r 20 ns ;
e n ab l e <= ' 0 ' ;
wait f o r 20 ns ;
a s s e r t data_in = data_golden ( 8 )
r e p o r t " data_golden ( 8 ) d i f f e r s from input 8"
severity error ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−Comparing the output with the golden output

108
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
wait on done ;
a s s e r t median = 127
r e p o r t "wrong median value c a l c u l a t e d "
severity failure ;

wait f o r 50 ns ;
assert true ;
r e p o r t " s i m u l a t i o n completed c o r r e c t l y without e r r o r "
severity failure ;

wait ;
end p r o c e s s ;

end a r c h i t e c t u r e ;

109
Image_core

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− T i t l e : image_core_tb
−− Design : defect_pixel_corr
−− Author : Henrik Backe−Hansen
−− Company : NTNU / Aptina Norway
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− F i l e : image_core_tb . vhd
−− Generated : Mon Feb 22 1 7 : 0 1 : 0 1 2010
−− From : interface description f i l e
−− By : I t f 2 V h d l ver . 1 . 2 0
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−Testbench to t e s t the image_core . vhd f i l e . The s t i m u l i i s f e d to
the image_core f i l e
−− value by value , row by row u n t i l a l l v a l u e s are read .
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

l i b r a r y IEEE ;
use IEEE . STD_LOGIC_1164 . a l l ;
use work . s i z e . a l l ;
use IEEE . numeric_std . a l l ;
use std . t e x t i o . a l l ;
use IEEE . std_logic_unsigned . a l l ;

e n t i t y image_core_tb i s
end image_core_tb ;

a r c h i t e c t u r e arch o f image_core_tb i s

type in_array i s array (0 to size_x −1) o f INTEGER;

type out_array i s array (0 to size_y ) o f INTEGER;

component image_core
port ( −−component d e c l a r a t i o n
clk : in std_logic ;
mod_en : in std_logic ;
rst : in std_logic ;
core_in : i n integer ;
di : in std_logic ;
do : out s t d _ l o g i c ;
core_out : out i n t e g e r
);
end component ;

110
signal clk : s t d _ l o g i c := ' 0 ' ;
signal mod_en : s t d _ l o g i c := ' 0 ' ;
signal rst : s t d _ l o g i c := ' 0 ' ;
signal core_in : i n t e g e r := 0 ;
signal core_out : i n t e g e r := 0 ;
signal di : s t d _ l o g i c := ' 0 ' ;
signal do : s t d _ l o g i c := ' 0 ' ;

begin

DUT: image_core −− d e v i c e under t e s t s i g n a l mapping

port map(
clk => clk ,
mod_en => mod_en ,
rst => r s t ,
core_in => core_in ,
di => di ,
do => do ,
core_out => core_out
);

clk_gen : p r o c e s s
begin
wait f o r 5 ns ;
c l k <= not ( c l k ) ;
end p r o c e s s ;

read_values : p r o c e s s
begin

mod_en <= ' 1 ' ;

wait f o r 20 ns ;
mod_en <= ' 0 ' ;
wait f o r 20 ns ;

f o r i i n 0 to ( ( size_y ∗ size_x ) −1) loop

d i <= ' 1 ' ; −− s e t t i n g the data i n ( d i ) f l a g

core_in <= data_array ( i ) ; −− i n p u t i n g the v a l u e s to
integer_in
wait f o r 10 ns ;
di<= ' 0 ' ;
wait f o r 10 ns ;
end loop ;

wait ;
end p r o c e s s ;

111
 write_file : process
FILE f i l e _ o u t :TEXT open WRITE_MODE IS " s r c \data_out_th_50 . pgm" ;
v a r i a b l e line_out : LINE ;
v a r i a b l e output : out_array ;
v a r i a b l e i : i n t e g e r :=0;

begin
wait f o r 10 ns ;
i f ( do = '1 ') then
output ( i ) := core_out ;
w r i t e ( line_out , output ( i ) ) ;
w r i t e ( line_out , s t r i n g ' ( " " ) ) ;

i := i +1;
i f ( i = size_y ) then
i := 0 ;
w r i t e l i n e ( f i l e _ o u t , line_out ) ;

else

end i f ;

end i f ;

end p r o c e s s ;

end arch ;

112
Ctrl

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− T i t l e : ctrl_tb
−− Design : defect_pixel_corr
−− Author : Henrik Backe−Hansen
−− Company : NTNU / Aptina Norway
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−
−− F i l e : c t r l _ t b . vhd
−− Generated : Mon Mar 15 2 1 : 2 1 : 1 1 2010
−− From : interface description f i l e
−− By : I t f 2 V h d l ver . 1 . 2 0
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− D e s c r i p t i o n : Testbench f o r the c t r l module
−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

l i b r a r y IEEE ;
use IEEE . STD_LOGIC_1164 . a l l ;
use IEEE . numeric_std . a l l ;
use std . t e x t i o . a l l ;
use work . s i z e . a l l ;

entity ctrl_tb i s
end c t r l _ t b ;

a r c h i t e c t u r e ctrl_tb_arch o f c t r l _ t b i s

type out_array i s array (0 to size_y ) o f INTEGER;

component c t r l
port (
clk : in std_logic ;
rst : in std_logic ;
data_out : out i n t e g e r
);
end component ;
signal clk : s t d _ l o g i c := ' 0 ' ;
signal rst : s t d _ l o g i c := ' 0 ' ;
s i g n a l data_out : integer := 0 ;

begin

DUT: c t r l
port map(

113
 clk => clk ,
rst => r s t ,
data_out=> data_out
);

clk_gen : p r o c e s s
begin
wait f o r 5 ns ;
c l k <= not ( c l k ) ;
end p r o c e s s ;

write_to_file : process
FILE f i l e _ o u t :TEXT open WRITE_MODE i s " s r c \ o u t _ c t r l . pgm" ;
v a r i a b l e line_out : LINE ;
v a r i a b l e output : out_array ;
v a r i a b l e i : i n t e g e r :=0;

begin
wait f o r 100 ns ;

i f ( data_out /= − 2147483648) then

output ( i ) := data_out ;
t e x t i o . w r i t e ( line_out , output ( i ) ) ;
t e x t i o . w r i t e ( line_out , s t r i n g ' ( " " ) ) ;

i := i +1;
i f ( i = size_y ) then
i := 0 ;
w r i t e l i n e ( f i l e _ o u t , line_out ) ;
end i f ;
end i f ;

end p r o c e s s ;
end ctrl_tb_arch ;

114
.2 Microblaze les
.2.1 mss

PARAMETER VERSION = 2 . 2 . 0

BEGIN OS
PARAMETER OS_NAME = s t a n d a l o n e
PARAMETER OS_VER = 3 . 0 0 . a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER s t d i n = RS232_Uart
PARAMETER std ou t = RS232_Uart
END

BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1 . 1 2 . b
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER xmdstub_peripheral = RS232_Uart
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1 . 0 0 . a
PARAMETER HW_INSTANCE = dlmb_cntlr
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1 . 0 0 . a
PARAMETER HW_INSTANCE = ilmb_cntlr
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = g e n e r i c
PARAMETER DRIVER_VER = 1 . 0 0 . a
PARAMETER HW_INSTANCE = lmb_bram
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = u a r t l i t e
PARAMETER DRIVER_VER = 1 . 1 4 . a
PARAMETER HW_INSTANCE = RS232_Uart
END

115
BEGIN DRIVER
PARAMETER DRIVER_NAME = s y s a c e
PARAMETER DRIVER_VER = 1 . 1 2 . a
PARAMETER HW_INSTANCE = SysACE_CompactFlash
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = g e n e r i c
PARAMETER DRIVER_VER = 1 . 0 0 . a
PARAMETER HW_INSTANCE = clock_generator_0
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = u a r t l i t e
PARAMETER DRIVER_VER = 1 . 1 4 . a
PARAMETER HW_INSTANCE = mdm_0
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = g e n e r i c
PARAMETER DRIVER_VER = 1 . 0 0 . a
PARAMETER HW_INSTANCE = proc_sys_reset_0
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = i n t c
PARAMETER DRIVER_VER = 1 . 1 1 . a
PARAMETER HW_INSTANCE = xps_intc_0
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = g e n e r i c
PARAMETER DRIVER_VER = 1 . 0 0 . a
PARAMETER HW_INSTANCE = mb_plb
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = my_custom_ip_register
PARAMETER DRIVER_VER = 9 . 0 0 . a
PARAMETER HW_INSTANCE = my_custom_ip_register_0
END

BEGIN LIBRARY
PARAMETER LIBRARY_NAME = x i l f a t f s
PARAMETER LIBRARY_VER = 1 . 0 0 . a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER CONFIG_WRITE = t r u e

116
 PARAMETER CONFIG_DIR_SUPPORT = t r u e
PARAMETER CONFIG_FAT12 = t r u e
END

117
.2.2 mhs

#
##############################################################################

# Created by Base System B u i l d e r Wizard f o r X i l i n x EDK 1 1 . 5 Build

EDK_LS5. 7 0
# Sat Apr 17 1 3 : 5 9 : 1 4 2010
# Target Board : X i l i n x V ir t e x 5 ML501 Evaluation Platform Rev 1
# Family : virtex5
# Device : xc5vlx50
# Package : ff676
# Speed Grade : −1
# P r o c e s s o r number : 1
# P r o c e s s o r 1 : microblaze_0
# System c l o c k f r e q u e n c y : 1 2 5 . 0
# Debug I n t e r f a c e : On−Chip HW Debug Module
#
##############################################################################

PARAMETER VERSION = 2 . 1 . 0

PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX_pin , DIR = I

PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX_pin , DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin =
fpga_0_SysACE_CompactFlash_SysACE_MPA_pin , DIR = O, VEC = [ 6 : 0 ]
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin =
fpga_0_SysACE_CompactFlash_SysACE_CLK_pin , DIR = I
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin =
fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin , DIR = I
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin =
fpga_0_SysACE_CompactFlash_SysACE_CEN_pin , DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin =
fpga_0_SysACE_CompactFlash_SysACE_OEN_pin , DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin =
fpga_0_SysACE_CompactFlash_SysACE_WEN_pin , DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin =
fpga_0_SysACE_CompactFlash_SysACE_MPD_pin , DIR = IO , VEC = [ 1 5 : 0 ]
PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s , DIR = I , SIGIS = CLK,
CLK_FREQ = 100000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s , DIR = I , SIGIS = RST,
RST_POLARITY = 0

BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 2 . 0 1 . a

118
 PARAMETER C_BASEADDR = 0 x81800000
PARAMETER C_HIGHADDR = 0 x 8 1 8 0 f f f f
BUS_INTERFACE SPLB = mb_plb
PORT I r q = microblaze_0_INTERRUPT
PORT I n t r = my_custom_ip_register_0_IP2INTC_Irpt
END

BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 2 . 0 0 . a
PORT Slowest_sync_clk = clk_125_0000MHz
PORT Ext_Reset_In = sys_rst_s
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Dcm_locked = Dcm_all_locked
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
END

BEGIN m i c r o b l a z e
PARAMETER INSTANCE = microblaze_0
PARAMETER C_INTERCONNECT = 1
PARAMETER C_USE_FPU = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER HW_VER = 7 . 3 0 . a
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
PORT MB_RESET = mb_reset
PORT INTERRUPT = microblaze_0_INTERRUPT
END

BEGIN mdm
PARAMETER INSTANCE = mdm_0
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER HW_VER = 1 . 0 0 . g
PARAMETER C_BASEADDR = 0 x84400000
PARAMETER C_HIGHADDR = 0 x 8 4 4 0 f f f f
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN plb_v46
PARAMETER INSTANCE = mb_plb

119
 PARAMETER HW_VER = 1 . 0 4 . a
PORT PLB_Clk = clk_125_0000MHz
PORT SYS_Rst = sys_bus_reset
END

BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1 . 0 0 . a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2 . 1 0 . b
PARAMETER C_BASEADDR = 0 x00000000
PARAMETER C_HIGHADDR = 0 x 0 0 0 1 f f f f
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1 . 0 0 . a
PORT LMB_Clk = clk_125_0000MHz
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2 . 1 0 . b
PARAMETER C_BASEADDR = 0 x00000000
PARAMETER C_HIGHADDR = 0 x 0 0 0 1 f f f f
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1 . 0 0 . a
PORT LMB_Clk = clk_125_0000MHz
PORT SYS_Rst = sys_bus_reset
END

BEGIN c l o c k _ g e n e r a t o r
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 125000000

120
 PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER HW_VER = 3 . 0 2 . a
PORT CLKIN = dcm_clk_s
PORT CLKOUT0 = clk_125_0000MHz
PORT RST = sys_rst_s
PORT LOCKED = Dcm_all_locked
END

BEGIN xps_sysace
PARAMETER INSTANCE = SysACE_CompactFlash
PARAMETER C_MEM_WIDTH = 16
PARAMETER HW_VER = 1 . 0 1 . a
PARAMETER C_BASEADDR = 0 x83600000
PARAMETER C_HIGHADDR = 0 x 8 3 6 0 f f f f
BUS_INTERFACE SPLB = mb_plb
PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin
PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin
PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin
END

BEGIN x p s _ u a r t l i t e
PARAMETER INSTANCE = RS232_Uart
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER HW_VER = 1 . 0 1 . a
PARAMETER C_BASEADDR = 0 x84000000
PARAMETER C_HIGHADDR = 0 x 8 4 0 0 f f f f
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_Uart_RX_pin
PORT TX = fpga_0_RS232_Uart_TX_pin
END

BEGIN my_custom_ip_register
PARAMETER INSTANCE = my_custom_ip_register_0
PARAMETER HW_VER = 9 . 0 0 . a
PARAMETER C_BASEADDR = 0 xccc00000
PARAMETER C_HIGHADDR = 0 x c c c 0 f f f f
BUS_INTERFACE SPLB = mb_plb
PORT IP2INTC_Irpt = my_custom_ip_register_0_IP2INTC_Irpt
END

121
.2.3 ucf
# V i r te x 5 ML501 Evaluation Platform
Net fpga_0_RS232_Uart_RX_pin LOC = AC7 | IOSTANDARD=LVCMOS33;
Net fpga_0_RS232_Uart_TX_pin LOC = AD14 | IOSTANDARD=LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=N6 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=E5 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=F5 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=F4 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=J5 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=E7 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=G7 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AB12 | IOSTANDARD
= LVCMOS33 | PERIOD = 30000 ps ;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=G6 | IOSTANDARD
= LVCMOS33 | TIG ;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=F7 | IOSTANDARD =
LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=E6 | IOSTANDARD =
LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=M5 | IOSTANDARD =
LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=M6 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=K5 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=L3 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=L4 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=L7 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=L5 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=H6 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=G5 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=M7 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=H7 |
IOSTANDARD = LVCMOS33;

122
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=J6 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=G4 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=K7 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=J4 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=H4 |
IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=K6 |
IOSTANDARD = LVCMOS33;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin ;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz ;
Net fpga_0_clk_1_sys_clk_pin LOC = AD8 | IOSTANDARD=LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG ;
Net fpga_0_rst_1_sys_rst_pin LOC = T23 | IOSTANDARD=LVCMOS33 |
PULLUP;

123
.2.4 xparameters.h

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
∗
∗ CAUTION: This f i l e i s a u t o m a t i c a l l y g e n e r a t e d by l i b g e n .
∗ Version : X i l i n x EDK 1 2 . 1 EDK_MS1. 5 3 d
∗ DO NOT EDIT .
∗
∗ Copyright ( c ) 1995 − 2010 Xilinx , Inc . All rights reserved .

∗
∗ D e s c r i p t i o n : Driver parameters
∗
∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

#d e f i n e STDIN_BASEADDRESS 0 x84000000
#d e f i n e STDOUT_BASEADDRESS 0 x84000000

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

/ ∗ D e f i n i t i o n s f o r d r i v e r UARTLITE ∗ /
#d e f i n e XPAR_XUARTLITE_NUM_INSTANCES 2

/ ∗ D e f i n i t i o n s f o r p e r i p h e r a l MDM_0 ∗ /
#d e f i n e XPAR_MDM_0_BASEADDR 0 x84400000
#d e f i n e XPAR_MDM_0_HIGHADDR 0x8440FFFF
#d e f i n e XPAR_MDM_0_DEVICE_ID 0
#d e f i n e XPAR_MDM_0_BAUDRATE 0
#d e f i n e XPAR_MDM_0_USE_PARITY 0
#d e f i n e XPAR_MDM_0_ODD_PARITY 0
#d e f i n e XPAR_MDM_0_DATA_BITS 0

/ ∗ D e f i n i t i o n s f o r p e r i p h e r a l RS232_UART ∗ /
#d e f i n e XPAR_RS232_UART_BASEADDR 0 x84000000
#d e f i n e XPAR_RS232_UART_HIGHADDR 0x8400FFFF
#d e f i n e XPAR_RS232_UART_DEVICE_ID 1
#d e f i n e XPAR_RS232_UART_BAUDRATE 9600
#d e f i n e XPAR_RS232_UART_USE_PARITY 0
#d e f i n e XPAR_RS232_UART_ODD_PARITY 0
#d e f i n e XPAR_RS232_UART_DATA_BITS 8

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

/ ∗ Canonical d e f i n i t i o n s f o r p e r i p h e r a l MDM_0 ∗ /
#d e f i n e XPAR_UARTLITE_0_DEVICE_ID XPAR_MDM_0_DEVICE_ID

124
#d e f i n e XPAR_UARTLITE_0_BASEADDR 0 x84400000
#d e f i n e XPAR_UARTLITE_0_HIGHADDR 0x8440FFFF
#d e f i n e XPAR_UARTLITE_0_BAUDRATE 0
#d e f i n e XPAR_UARTLITE_0_USE_PARITY 0
#d e f i n e XPAR_UARTLITE_0_ODD_PARITY 0
#d e f i n e XPAR_UARTLITE_0_DATA_BITS 0
#d e f i n e XPAR_UARTLITE_0_SIO_CHAN −1

/ ∗ Canonical d e f i n i t i o n s f o r p e r i p h e r a l RS232_UART ∗ /
#d e f i n e XPAR_UARTLITE_1_DEVICE_ID XPAR_RS232_UART_DEVICE_ID
#d e f i n e XPAR_UARTLITE_1_BASEADDR 0 x84000000
#d e f i n e XPAR_UARTLITE_1_HIGHADDR 0x8400FFFF
#d e f i n e XPAR_UARTLITE_1_BAUDRATE 9600
#d e f i n e XPAR_UARTLITE_1_USE_PARITY 0
#d e f i n e XPAR_UARTLITE_1_ODD_PARITY 0
#d e f i n e XPAR_UARTLITE_1_DATA_BITS 8
#d e f i n e XPAR_UARTLITE_1_SIO_CHAN −1

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

#d e f i n e XPAR_XSYSACE_MEM_WIDTH 16
/ ∗ D e f i n i t i o n s f o r d r i v e r SYSACE ∗ /
#d e f i n e XPAR_XSYSACE_NUM_INSTANCES 1

/ ∗ D e f i n i t i o n s f o r p e r i p h e r a l SYSACE_COMPACTFLASH ∗ /
#d e f i n e XPAR_SYSACE_COMPACTFLASH_DEVICE_ID 0
#d e f i n e XPAR_SYSACE_COMPACTFLASH_BASEADDR 0 x83600000
#d e f i n e XPAR_SYSACE_COMPACTFLASH_HIGHADDR 0x8360FFFF
#d e f i n e XPAR_SYSACE_COMPACTFLASH_MEM_WIDTH 16

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

/ ∗ Canonical d e f i n i t i o n s f o r p e r i p h e r a l SYSACE_COMPACTFLASH ∗ /
#d e f i n e XPAR_SYSACE_0_DEVICE_ID XPAR_SYSACE_COMPACTFLASH_DEVICE_ID
#d e f i n e XPAR_SYSACE_0_BASEADDR 0 x83600000
#d e f i n e XPAR_SYSACE_0_HIGHADDR 0x8360FFFF
#d e f i n e XPAR_SYSACE_0_MEM_WIDTH 16

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

/ ∗ D e f i n i t i o n s f o r p e r i p h e r a l DLMB_CNTLR ∗ /
#d e f i n e XPAR_DLMB_CNTLR_BASEADDR 0 x00000000
#d e f i n e XPAR_DLMB_CNTLR_HIGHADDR 0x0001FFFF

125
/ ∗ D e f i n i t i o n s f o r p e r i p h e r a l ILMB_CNTLR ∗ /
#d e f i n e XPAR_ILMB_CNTLR_BASEADDR 0 x00000000
#d e f i n e XPAR_ILMB_CNTLR_HIGHADDR 0x0001FFFF

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

/ ∗ D e f i n i t i o n s f o r d r i v e r MY_CUSTOM_IP_REGISTER ∗ /
#d e f i n e XPAR_MY_CUSTOM_IP_REGISTER_NUM_INSTANCES 1

/ ∗ D e f i n i t i o n s f o r p e r i p h e r a l MY_CUSTOM_IP_REGISTER_0 ∗ /
#d e f i n e XPAR_MY_CUSTOM_IP_REGISTER_0_DEVICE_ID 0
#d e f i n e XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR 0xCCC00000
#d e f i n e XPAR_MY_CUSTOM_IP_REGISTER_0_HIGHADDR 0xCCC0FFFF

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

#d e f i n e XPAR_INTC_MAX_NUM_INTR_INPUTS 1
#d e f i n e XPAR_XINTC_HAS_IPR 1
#d e f i n e XPAR_XINTC_USE_DCR 0
/ ∗ D e f i n i t i o n s f o r d r i v e r INTC ∗ /
#d e f i n e XPAR_XINTC_NUM_INSTANCES 1

/ ∗ D e f i n i t i o n s f o r p e r i p h e r a l XPS_INTC_0 ∗ /
#d e f i n e XPAR_XPS_INTC_0_DEVICE_ID 0
#d e f i n e XPAR_XPS_INTC_0_BASEADDR 0 x81800000
#d e f i n e XPAR_XPS_INTC_0_HIGHADDR 0x8180FFFF
#d e f i n e XPAR_XPS_INTC_0_KIND_OF_INTR 0xFFFFFFFE

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

#d e f i n e XPAR_INTC_SINGLE_BASEADDR 0 x81800000
#d e f i n e XPAR_INTC_SINGLE_HIGHADDR 0x8180FFFF
#d e f i n e XPAR_INTC_SINGLE_DEVICE_ID XPAR_XPS_INTC_0_DEVICE_ID
#d e f i n e XPAR_MY_CUSTOM_IP_REGISTER_0_IP2INTC_IRPT_MASK 0X000001
#d e f i n e XPAR_XPS_INTC_0_MY_CUSTOM_IP_REGISTER_0_IP2INTC_IRPT_INTR 0

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

/ ∗ Canonical d e f i n i t i o n s f o r p e r i p h e r a l XPS_INTC_0 ∗ /
#d e f i n e XPAR_INTC_0_DEVICE_ID XPAR_XPS_INTC_0_DEVICE_ID
#d e f i n e XPAR_INTC_0_BASEADDR 0 x81800000
#d e f i n e XPAR_INTC_0_HIGHADDR 0x8180FFFF
#d e f i n e XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFFE

126
#d e f i n e XPAR_INTC_0_MY_CUSTOM_IP_REGISTER_0_VEC_ID
XPAR_XPS_INTC_0_MY_CUSTOM_IP_REGISTER_0_IP2INTC_IRPT_INTR

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

/ ∗ D e f i n i t i o n s f o r bus f r e q u e n c i e s ∗ /
#d e f i n e XPAR_CPU_DPLB_FREQ_HZ 125000000
#d e f i n e XPAR_CPU_IPLB_FREQ_HZ 125000000
/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

/ ∗ Canonical d e f i n i t i o n s f o r bus f r e q u e n c i e s ∗ /
#d e f i n e XPAR_PROC_BUS_0_FREQ_HZ 125000000
/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

#d e f i n e XPAR_CPU_CORE_CLOCK_FREQ_HZ 125000000
#d e f i n e XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ 125000000

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

/ ∗ D e f i n i t i o n s f o r p e r i p h e r a l MICROBLAZE_0 ∗ /
#d e f i n e XPAR_MICROBLAZE_0_SCO 0
#d e f i n e XPAR_MICROBLAZE_0_FREQ 125000000
#d e f i n e XPAR_MICROBLAZE_0_DATA_SIZE 32
#d e f i n e XPAR_MICROBLAZE_0_DYNAMIC_BUS_SIZING 1
#d e f i n e XPAR_MICROBLAZE_0_AREA_OPTIMIZED 0
#d e f i n e XPAR_MICROBLAZE_0_OPTIMIZATION 0
#d e f i n e XPAR_MICROBLAZE_0_INTERCONNECT 1
#d e f i n e XPAR_MICROBLAZE_0_DPLB_DWIDTH 32
#d e f i n e XPAR_MICROBLAZE_0_DPLB_NATIVE_DWIDTH 32
#d e f i n e XPAR_MICROBLAZE_0_DPLB_BURST_EN 0
#d e f i n e XPAR_MICROBLAZE_0_DPLB_P2P 0
#d e f i n e XPAR_MICROBLAZE_0_IPLB_DWIDTH 32
#d e f i n e XPAR_MICROBLAZE_0_IPLB_NATIVE_DWIDTH 32
#d e f i n e XPAR_MICROBLAZE_0_IPLB_BURST_EN 0
#d e f i n e XPAR_MICROBLAZE_0_IPLB_P2P 0
#d e f i n e XPAR_MICROBLAZE_0_D_PLB 1
#d e f i n e XPAR_MICROBLAZE_0_D_LMB 1
#d e f i n e XPAR_MICROBLAZE_0_I_PLB 1
#d e f i n e XPAR_MICROBLAZE_0_I_LMB 1
#d e f i n e XPAR_MICROBLAZE_0_USE_MSR_INSTR 1
#d e f i n e XPAR_MICROBLAZE_0_USE_PCMP_INSTR 1
#d e f i n e XPAR_MICROBLAZE_0_USE_BARREL 0
#d e f i n e XPAR_MICROBLAZE_0_USE_DIV 0
#d e f i n e XPAR_MICROBLAZE_0_USE_HW_MUL 1
#d e f i n e XPAR_MICROBLAZE_0_USE_FPU 1
#d e f i n e XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS 0
#d e f i n e XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION 0
#d e f i n e XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION 0

127
#d e f i n e XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION 0
#d e f i n e XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION 0
#d e f i n e XPAR_MICROBLAZE_0_FPU_EXCEPTION 0
#d e f i n e XPAR_MICROBLAZE_0_FSL_EXCEPTION 0
#d e f i n e XPAR_MICROBLAZE_0_PVR 0
#d e f i n e XPAR_MICROBLAZE_0_PVR_USER1 0 x00
#d e f i n e XPAR_MICROBLAZE_0_PVR_USER2 0 x00000000
#d e f i n e XPAR_MICROBLAZE_0_DEBUG_ENABLED 1
#d e f i n e XPAR_MICROBLAZE_0_NUMBER_OF_PC_BRK 1
#d e f i n e XPAR_MICROBLAZE_0_NUMBER_OF_RD_ADDR_BRK 0
#d e f i n e XPAR_MICROBLAZE_0_NUMBER_OF_WR_ADDR_BRK 0
#d e f i n e XPAR_MICROBLAZE_0_INTERRUPT_IS_EDGE 0
#d e f i n e XPAR_MICROBLAZE_0_EDGE_IS_POSITIVE 1
#d e f i n e XPAR_MICROBLAZE_0_RESET_MSR 0 x00000000
#d e f i n e XPAR_MICROBLAZE_0_OPCODE_0X0_ILLEGAL 0
#d e f i n e XPAR_MICROBLAZE_0_FSL_LINKS 0
#d e f i n e XPAR_MICROBLAZE_0_FSL_DATA_SIZE 32
#d e f i n e XPAR_MICROBLAZE_0_USE_EXTENDED_FSL_INSTR 0
#d e f i n e XPAR_MICROBLAZE_0_ICACHE_BASEADDR 0 x00000000
#d e f i n e XPAR_MICROBLAZE_0_ICACHE_HIGHADDR 0x3FFFFFFF
#d e f i n e XPAR_MICROBLAZE_0_USE_ICACHE 0
#d e f i n e XPAR_MICROBLAZE_0_ALLOW_ICACHE_WR 1
#d e f i n e XPAR_MICROBLAZE_0_ADDR_TAG_BITS 0
#d e f i n e XPAR_MICROBLAZE_0_CACHE_BYTE_SIZE 8192
#d e f i n e XPAR_MICROBLAZE_0_ICACHE_USE_FSL 1
#d e f i n e XPAR_MICROBLAZE_0_ICACHE_LINE_LEN 4
#d e f i n e XPAR_MICROBLAZE_0_ICACHE_ALWAYS_USED 0
#d e f i n e XPAR_MICROBLAZE_0_ICACHE_INTERFACE 0
#d e f i n e XPAR_MICROBLAZE_0_ICACHE_VICTIMS 0
#d e f i n e XPAR_MICROBLAZE_0_ICACHE_STREAMS 0
#d e f i n e XPAR_MICROBLAZE_0_DCACHE_BASEADDR 0 x00000000
#d e f i n e XPAR_MICROBLAZE_0_DCACHE_HIGHADDR 0x3FFFFFFF
#d e f i n e XPAR_MICROBLAZE_0_USE_DCACHE 0
#d e f i n e XPAR_MICROBLAZE_0_ALLOW_DCACHE_WR 1
#d e f i n e XPAR_MICROBLAZE_0_DCACHE_ADDR_TAG 0
#d e f i n e XPAR_MICROBLAZE_0_DCACHE_BYTE_SIZE 8192
#d e f i n e XPAR_MICROBLAZE_0_DCACHE_USE_FSL 1
#d e f i n e XPAR_MICROBLAZE_0_DCACHE_LINE_LEN 4
#d e f i n e XPAR_MICROBLAZE_0_DCACHE_ALWAYS_USED 0
#d e f i n e XPAR_MICROBLAZE_0_DCACHE_INTERFACE 0
#d e f i n e XPAR_MICROBLAZE_0_DCACHE_USE_WRITEBACK 0
#d e f i n e XPAR_MICROBLAZE_0_DCACHE_VICTIMS 0
#d e f i n e XPAR_MICROBLAZE_0_USE_MMU 0
#d e f i n e XPAR_MICROBLAZE_0_MMU_DTLB_SIZE 4
#d e f i n e XPAR_MICROBLAZE_0_MMU_ITLB_SIZE 2
#d e f i n e XPAR_MICROBLAZE_0_MMU_TLB_ACCESS 3
#d e f i n e XPAR_MICROBLAZE_0_MMU_ZONES 16
#d e f i n e XPAR_MICROBLAZE_0_USE_INTERRUPT 1
#d e f i n e XPAR_MICROBLAZE_0_USE_EXT_BRK 1

128
#d e f i n e XPAR_MICROBLAZE_0_USE_EXT_NM_BRK 1
#d e f i n e XPAR_MICROBLAZE_0_USE_BRANCH_TARGET_CACHE 0
#d e f i n e XPAR_MICROBLAZE_0_BRANCH_TARGET_CACHE_SIZE 0

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

#d e f i n e XPAR_CPU_ID 0
#d e f i n e XPAR_MICROBLAZE_ID 0
#d e f i n e XPAR_MICROBLAZE_SCO 0
#d e f i n e XPAR_MICROBLAZE_FREQ 125000000
#d e f i n e XPAR_MICROBLAZE_DATA_SIZE 32
#d e f i n e XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 1
#d e f i n e XPAR_MICROBLAZE_AREA_OPTIMIZED 0
#d e f i n e XPAR_MICROBLAZE_OPTIMIZATION 0
#d e f i n e XPAR_MICROBLAZE_INTERCONNECT 1
#d e f i n e XPAR_MICROBLAZE_DPLB_DWIDTH 32
#d e f i n e XPAR_MICROBLAZE_DPLB_NATIVE_DWIDTH 32
#d e f i n e XPAR_MICROBLAZE_DPLB_BURST_EN 0
#d e f i n e XPAR_MICROBLAZE_DPLB_P2P 0
#d e f i n e XPAR_MICROBLAZE_IPLB_DWIDTH 32
#d e f i n e XPAR_MICROBLAZE_IPLB_NATIVE_DWIDTH 32
#d e f i n e XPAR_MICROBLAZE_IPLB_BURST_EN 0
#d e f i n e XPAR_MICROBLAZE_IPLB_P2P 0
#d e f i n e XPAR_MICROBLAZE_D_PLB 1
#d e f i n e XPAR_MICROBLAZE_D_LMB 1
#d e f i n e XPAR_MICROBLAZE_I_PLB 1
#d e f i n e XPAR_MICROBLAZE_I_LMB 1
#d e f i n e XPAR_MICROBLAZE_USE_MSR_INSTR 1
#d e f i n e XPAR_MICROBLAZE_USE_PCMP_INSTR 1
#d e f i n e XPAR_MICROBLAZE_USE_BARREL 0
#d e f i n e XPAR_MICROBLAZE_USE_DIV 0
#d e f i n e XPAR_MICROBLAZE_USE_HW_MUL 1
#d e f i n e XPAR_MICROBLAZE_USE_FPU 1
#d e f i n e XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 0
#d e f i n e XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 0
#d e f i n e XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION 0
#d e f i n e XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION 0
#d e f i n e XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 0
#d e f i n e XPAR_MICROBLAZE_FPU_EXCEPTION 0
#d e f i n e XPAR_MICROBLAZE_FSL_EXCEPTION 0
#d e f i n e XPAR_MICROBLAZE_PVR 0
#d e f i n e XPAR_MICROBLAZE_PVR_USER1 0 x00
#d e f i n e XPAR_MICROBLAZE_PVR_USER2 0 x00000000
#d e f i n e XPAR_MICROBLAZE_DEBUG_ENABLED 1
#d e f i n e XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 1
#d e f i n e XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 0
#d e f i n e XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 0
#d e f i n e XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0
#d e f i n e XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1

129
#d e f i n e XPAR_MICROBLAZE_RESET_MSR 0 x00000000
#d e f i n e XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 0
#d e f i n e XPAR_MICROBLAZE_FSL_LINKS 0
#d e f i n e XPAR_MICROBLAZE_FSL_DATA_SIZE 32
#d e f i n e XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
#d e f i n e XPAR_MICROBLAZE_ICACHE_BASEADDR 0 x00000000
#d e f i n e XPAR_MICROBLAZE_ICACHE_HIGHADDR 0x3FFFFFFF
#d e f i n e XPAR_MICROBLAZE_USE_ICACHE 0
#d e f i n e XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
#d e f i n e XPAR_MICROBLAZE_ADDR_TAG_BITS 0
#d e f i n e XPAR_MICROBLAZE_CACHE_BYTE_SIZE 8192
#d e f i n e XPAR_MICROBLAZE_ICACHE_USE_FSL 1
#d e f i n e XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
#d e f i n e XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 0
#d e f i n e XPAR_MICROBLAZE_ICACHE_INTERFACE 0
#d e f i n e XPAR_MICROBLAZE_ICACHE_VICTIMS 0
#d e f i n e XPAR_MICROBLAZE_ICACHE_STREAMS 0
#d e f i n e XPAR_MICROBLAZE_DCACHE_BASEADDR 0 x00000000
#d e f i n e XPAR_MICROBLAZE_DCACHE_HIGHADDR 0x3FFFFFFF
#d e f i n e XPAR_MICROBLAZE_USE_DCACHE 0
#d e f i n e XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
#d e f i n e XPAR_MICROBLAZE_DCACHE_ADDR_TAG 0
#d e f i n e XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 8192
#d e f i n e XPAR_MICROBLAZE_DCACHE_USE_FSL 1
#d e f i n e XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
#d e f i n e XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 0
#d e f i n e XPAR_MICROBLAZE_DCACHE_INTERFACE 0
#d e f i n e XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 0
#d e f i n e XPAR_MICROBLAZE_DCACHE_VICTIMS 0
#d e f i n e XPAR_MICROBLAZE_USE_MMU 0
#d e f i n e XPAR_MICROBLAZE_MMU_DTLB_SIZE 4
#d e f i n e XPAR_MICROBLAZE_MMU_ITLB_SIZE 2
#d e f i n e XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
#d e f i n e XPAR_MICROBLAZE_MMU_ZONES 16
#d e f i n e XPAR_MICROBLAZE_USE_INTERRUPT 1
#d e f i n e XPAR_MICROBLAZE_USE_EXT_BRK 1
#d e f i n e XPAR_MICROBLAZE_USE_EXT_NM_BRK 1
#d e f i n e XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 0
#d e f i n e XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0
#d e f i n e XPAR_MICROBLAZE_HW_VER " 7 . 3 0 . a"

/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗ /

#d e f i n e XILFATFS_MAXFILES 5
#d e f i n e XILFATFS_BUFCACHE_SIZE 10240

130
.3 Microblaze Synthesize
R e l e a s e 1 2 . 1 − x s t M. 5 3 d ( nt )
Copyright ( c ) 1995 − 2010 Xilinx , Inc . A l l r i g h t s r e s e r v e d .
−−>
TABLE OF CONTENTS
1) S y n t h e s i s Options Summary
2) HDL Compilation
3) Design Hierarchy A n a l y s i s
4) HDL A n a l y s i s
5) HDL S y n t h e s i s
5 . 1 ) HDL S y n t h e s i s Report
6) Advanced HDL S y n t h e s i s
6 . 1 ) Advanced HDL S y n t h e s i s Report
7) Low Level S y n t h e s i s
8) P a r t i t i o n Report
9) F i n a l Report
9 . 1 ) Device u t i l i z a t i o n summary
9 . 2 ) P a r t i t i o n Resource Summary
9 . 3 ) TIMING REPORT

=========================================================================

∗ S y n t h e s i s Options Summary
∗
=========================================================================

−−−− Source Parameters

Input Format : MIXED
Input F i l e Name : " system_xst . p r j "
Verilog Include Directory : {"C: \ Users \ Magician \ Desktop \
bsb_project \ p c o r e s \" "C: \ X i l i n x \1 2 . 1\ISE_DS\EDK\hw\
X i l i n x P r o c e s s o r I P L i b \ p c o r e s \" }

−−−− Target Parameters

Target Device : x c 5 v l x 5 0 f f 6 7 6 −1
Output F i l e Name : " . . / implementation / system . ngc "

−−−− Source Options

Top Module Name : system

−−−− Target Options

Add IO B u f f e r s : YES
Global Maximum Fanout : 10000

−−−− General Options

Optimization Goal : speed
N e t l i s t Hierarchy : as_optimized

131
Optimization E f f o r t : 1
Hierarchy S e p a r a t o r : /

−−−− Other Options

Cores Search D i r e c t o r i e s : { . . / implementation }

=========================================================================

WARNING: U t i l i t i e s C − The message f i l t e r f i l e " . . / __xps/ i s e / f i l t e r .

filter " specified with the − f i l t e r switch can ' t be found .
WARNING: U t i l i t i e s C − The message f i l t e r f i l e " . . / __xps/ i s e / f i l t e r .
filter " specified with the − f i l t e r switch can ' t be found .

=========================================================================

∗ HDL Compilation
∗
=========================================================================

Compiling vhdl f i l e "C: / Users / Magician / Desktop / bsb_project / hdl / system

. vhd" i n Li br ary work .
Entity <system> compiled .
Entity <system> ( A r c h i t e c t u r e <STRUCTURE>) compiled .

=========================================================================

∗ Design Hierarchy A n a l y s i s
∗
=========================================================================

Analyzing h i e r a r c h y f o r e n t i t y <system> i n l i b r a r y <work> (

a r c h i t e c t u r e <STRUCTURE>) .

=========================================================================

∗ HDL A n a l y s i s
∗
=========================================================================

Analyzing Entity <system> i n l i b r a r y <work> ( A r c h i t e c t u r e <STRUCTURE

>) .
Set property "BUFFER_TYPE = BUFGP" f o r s i g n a l <
fpga_0_SysACE_CompactFlash_SysACE_CLK_pin> i n u n i t <system >.
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 1 9 1 : Unconnected output port ' RstcPPCresetcore_0 ' o f
component ' proc_sys_reset_0_wrapper ' .

132
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 1 9 1 : Unconnected output port ' RstcPPCresetchip_0 ' o f
component ' proc_sys_reset_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 1 9 1 : Unconnected output port ' RstcPPCresetsys_0 ' o f
component ' proc_sys_reset_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 1 9 1 : Unconnected output port ' RstcPPCresetcore_1 ' o f
component ' proc_sys_reset_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 1 9 1 : Unconnected output port ' RstcPPCresetchip_1 ' o f
component ' proc_sys_reset_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 1 9 1 : Unconnected output port ' RstcPPCresetsys_1 ' o f
component ' proc_sys_reset_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 1 9 1 : Unconnected output port ' Peripheral_Reset ' o f
component ' proc_sys_reset_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'MB_Halted ' o f component '
microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' T ra c e_ In s tr u ct i on ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Valid_Instr ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_PC ' o f component '
microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Reg_Write ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Reg_Addr ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'Trace_MSR_Reg ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_PID_Reg ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_New_Reg_Value ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Exception_Taken ' o f
component ' microblaze_0_wrapper ' .

133
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Exception_Kind ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Jump_Taken ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Delay_Slot ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Data_Address ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Data_Access ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Data_Read ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Data_Write ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Data_Write_Value '
o f component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Data_Byte_Enable '
o f component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_DCache_Req ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_DCache_Hit ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_DCache_Rdy ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_DCache_Read ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_ICache_Req ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_ICache_Hit ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_ICache_Rdy ' o f
component ' microblaze_0_wrapper ' .

134
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_OF_PipeRun ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_EX_PipeRun ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'Trace_MEM_PipeRun ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_MB_Halted ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port ' Trace_Jump_Hit ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL0_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL0_S_READ ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL0_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL0_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL0_M_DATA' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL0_M_CONTROL' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL1_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL1_S_READ ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL1_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL1_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL1_M_DATA' o f component
' microblaze_0_wrapper ' .

135
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL1_M_CONTROL' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL2_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL2_S_READ ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL2_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL2_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL2_M_DATA' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL2_M_CONTROL' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL3_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL3_S_READ ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL3_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL3_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL3_M_DATA' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL3_M_CONTROL' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL4_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL4_S_READ ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL4_M_CLK ' o f component
' microblaze_0_wrapper ' .

136
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL4_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL4_M_DATA' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL4_M_CONTROL' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL5_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL5_S_READ ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL5_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL5_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL5_M_DATA' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL5_M_CONTROL' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL6_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL6_S_READ ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL6_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL6_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL6_M_DATA' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL6_M_CONTROL' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL7_S_CLK ' o f component
' microblaze_0_wrapper ' .

137
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL7_S_READ ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL7_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL7_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL7_M_DATA' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL7_M_CONTROL' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL8_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL8_S_READ ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL8_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL8_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL8_M_DATA' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL8_M_CONTROL' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL9_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL9_S_READ ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL9_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL9_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL9_M_DATA' o f component
' microblaze_0_wrapper ' .

138
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL9_M_CONTROL' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL10_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL10_S_READ ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL10_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL10_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL10_M_DATA ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL10_M_CONTROL ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL11_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL11_S_READ ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL11_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL11_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL11_M_DATA ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL11_M_CONTROL ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL12_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL12_S_READ ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL12_M_CLK ' o f component
' microblaze_0_wrapper ' .

139
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL12_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL12_M_DATA ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL12_M_CONTROL ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL13_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL13_S_READ ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL13_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL13_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL13_M_DATA ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL13_M_CONTROL ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL14_S_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL14_S_READ ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL14_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL14_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL14_M_DATA ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL14_M_CONTROL ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL15_S_CLK ' o f component
' microblaze_0_wrapper ' .

140
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL15_S_READ ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL15_M_CLK ' o f component
' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL15_M_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL15_M_DATA ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'FSL15_M_CONTROL ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'ICACHE_FSL_IN_CLK ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'ICACHE_FSL_IN_READ ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'ICACHE_FSL_OUT_CLK ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'ICACHE_FSL_OUT_WRITE ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'ICACHE_FSL_OUT_DATA' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'ICACHE_FSL_OUT_CONTROL'
o f component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'DCACHE_FSL_IN_CLK ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'DCACHE_FSL_IN_READ ' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'DCACHE_FSL_OUT_CLK' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'DCACHE_FSL_OUT_WRITE' o f
component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'DCACHE_FSL_OUT_DATA' o f
component ' microblaze_0_wrapper ' .

141
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 2 1 5 : Unconnected output port 'DCACHE_FSL_OUT_CONTROL'
o f component ' microblaze_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' I n t e r r u p t ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'MDM_DBus' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'MDM_errAck ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'MDM_retry ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'MDM_toutSup ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'MDM_xferAck ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Clk_1 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_TDI_1 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Reg_En_1 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Capture_1 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Shift_1 ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Update_1 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Rst_1 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Clk_2 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_TDI_2 ' o f component '
mdm_0_wrapper ' .

142
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Reg_En_2 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Capture_2 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Shift_2 ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Update_2 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Rst_2 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Clk_3 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_TDI_3 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Reg_En_3 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Capture_3 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Shift_3 ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Update_3 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Rst_3 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Clk_4 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_TDI_4 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Reg_En_4 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Capture_4 ' o f
component 'mdm_0_wrapper ' .

143
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Shift_4 ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Update_4 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Rst_4 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Clk_5 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_TDI_5 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Reg_En_5 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Capture_5 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Shift_5 ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Update_5 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Rst_5 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Clk_6 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_TDI_6 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Reg_En_6 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Capture_6 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Shift_6 ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Update_6 ' o f
component 'mdm_0_wrapper ' .

144
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Rst_6 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Clk_7 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_TDI_7 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Reg_En_7 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Capture_7 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Shift_7 ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' Dbg_Update_7 ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Dbg_Rst_7 ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' bscan_tdi ' o f component '
mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' bscan_reset ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' b s c a n _ s h i f t ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' bscan_update ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' bscan_capture ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' bscan_sel1 ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port ' bscan_drck1 ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'FSL0_S_CLK ' o f component
'mdm_0_wrapper ' .

145
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'FSL0_S_READ ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'FSL0_M_CLK ' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'FSL0_M_WRITE ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'FSL0_M_DATA' o f component
'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'FSL0_M_CONTROL' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Ext_JTAG_DRCK ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Ext_JTAG_RESET ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Ext_JTAG_SEL ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Ext_JTAG_CAPTURE ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Ext_JTAG_SHIFT ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Ext_JTAG_UPDATE ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 5 2 0 : Unconnected output port 'Ext_JTAG_TDI ' o f
component 'mdm_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_Rst ' o f component '
mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'MPLB_Rst ' o f component '
mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_dcrAck ' o f component
' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_dcrDBus ' o f component
' mb_plb_wrapper ' .

146
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port ' PLB_SaddrAck ' o f
component ' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_SMRdErr ' o f component
' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_SMWrErr ' o f component
' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_SMBusy ' o f component
' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_SrdBTerm ' o f
component ' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_SrdComp ' o f component
' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_SrdDAck ' o f component
' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_SrdDBus ' o f component
' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_SrdWdAddr ' o f
component ' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port ' PLB_Srearbitrate ' o f
component ' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port ' PLB_Sssize ' o f component
' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port ' PLB_Swait ' o f component '
mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_SwrBTerm ' o f
component ' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_SwrComp ' o f component
' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port 'PLB_SwrDAck ' o f component
' mb_plb_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 6 7 3 : Unconnected output port ' Bus_Error_Det ' o f
component ' mb_plb_wrapper ' .

147
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT1 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT2 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT3 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT4 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT5 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT6 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT7 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT8 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT9 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT10 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT11 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT12 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT13 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT14 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKOUT15 ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'CLKFBOUT' o f component '
clock_generator_0_wrapper ' .

148
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 8 8 0 : Unconnected output port 'PSDONE ' o f component '
clock_generator_0_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 9 0 9 : Unconnected output port 'SysACE_IRQ ' o f component
' sysace_compactflash_wrapper ' .
WARNING: Xst : 7 5 3 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 1 9 6 5 : Unconnected output port ' I n t e r r u p t ' o f component '
rs232_uart_wrapper ' .
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 0 6 1 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 0 6 9 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 0 7 7 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 0 8 5 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 0 9 3 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 1 0 1 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 1 0 9 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 1 1 7 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 1 2 5 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 1 3 3 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 1 4 1 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 1 4 9 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 1 5 7 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 1 6 5 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 1 7 3 : I n s t a n t i a t i n g black box module <IOBUF>.
WARNING: Xst : 2 2 1 1 − "C: / Users / Magician / Desktop / bsb_project / hdl / system .
vhd" l i n e 2 1 8 1 : I n s t a n t i a t i n g black box module <IOBUF>.
Entity <system> analyzed . Unit <system> g e n e r a t e d .

=========================================================================

∗ HDL S y n t h e s i s
∗

149
=========================================================================

Performing b i d i r e c t i o n a l port r e s o l u t i o n . . .

S y n t h e s i z i n g Unit <system >.

Related s o u r c e f i l e i s "C: / Users / Magician / Desktop / bsb_project / hdl
/ system . vhd" .
Unit <system> s y n t h e s i z e d .

=========================================================================

HDL S y n t h e s i s Report

Found no macro
=========================================================================

=========================================================================

∗ Advanced HDL S y n t h e s i s
∗
=========================================================================

Reading c o r e <../ implementation /xps_intc_0_wrapper . ngc >.

Reading c o r e <../ implementation / proc_sys_reset_0_wrapper . ngc >.
Reading c o r e <../ implementation / microblaze_0_wrapper . ngc >.
Reading c o r e <../ implementation /mdm_0_wrapper . ngc >.
Reading c o r e <../ implementation /mb_plb_wrapper . ngc >.
Reading c o r e <../ implementation /lmb_bram_wrapper . ngc >.
Reading c o r e <../ implementation / ilmb_cntlr_wrapper . ngc >.
Reading c o r e <../ implementation / ilmb_wrapper . ngc >.
Reading c o r e <../ implementation / dlmb_cntlr_wrapper . ngc >.
Reading c o r e <../ implementation /dlmb_wrapper . ngc >.
Reading c o r e <../ implementation / clock_generator_0_wrapper . ngc >.
Reading c o r e <../ implementation / sysace_compactflash_wrapper . ngc >.
Reading c o r e <../ implementation / rs232_uart_wrapper . ngc >.
Reading c o r e <../ implementation /my_custom_ip_register_0_wrapper . ngc >.
Loading c o r e <xps_intc_0_wrapper> f o r timing and area i n f o r m a t i o n f o r
i n s t a n c e <xps_intc_0 >.
Loading c o r e <proc_sys_reset_0_wrapper> f o r timing and area
i n f o r m a t i o n f o r i n s t a n c e <proc_sys_reset_0 >.
Loading c o r e <microblaze_0_wrapper> f o r timing and area i n f o r m a t i o n
f o r i n s t a n c e <microblaze_0 >.
Loading c o r e <mdm_0_wrapper> f o r timing and area i n f o r m a t i o n f o r
i n s t a n c e <mdm_0>.

150
Loading c o r e <mb_plb_wrapper> f o r timing and area i n f o r m a t i o n f o r
i n s t a n c e <mb_plb>.
Loading c o r e <lmb_bram_wrapper> f o r timing and area i n f o r m a t i o n f o r
i n s t a n c e <lmb_bram>.
Loading c o r e <ilmb_cntlr_wrapper> f o r timing and area i n f o r m a t i o n f o r
i n s t a n c e <ilmb_cntlr >.
Loading c o r e <ilmb_wrapper> f o r timing and area i n f o r m a t i o n f o r
i n s t a n c e <ilmb >.
Loading c o r e <dlmb_cntlr_wrapper> f o r timing and area i n f o r m a t i o n f o r
i n s t a n c e <dlmb_cntlr >.
Loading c o r e <dlmb_wrapper> f o r timing and area i n f o r m a t i o n f o r
i n s t a n c e <dlmb>.
Loading c o r e <clock_generator_0_wrapper> f o r timing and area
i n f o r m a t i o n f o r i n s t a n c e <clock_generator_0 >.
Loading c o r e <sysace_compactflash_wrapper> f o r timing and area
i n f o r m a t i o n f o r i n s t a n c e <SysACE_CompactFlash>.
Loading c o r e <rs232_uart_wrapper> f o r timing and area i n f o r m a t i o n f o r
i n s t a n c e <RS232_Uart>.
Loading c o r e <my_custom_ip_register_0_wrapper> f o r timing and area
i n f o r m a t i o n f o r i n s t a n c e <my_custom_ip_register_0 >.

=========================================================================

Advanced HDL S y n t h e s i s Report

Found no macro
=========================================================================

=========================================================================

∗ Low Level S y n t h e s i s
∗
=========================================================================

Optimizing u n i t <system> . . .

Mapping a l l e q u a t i o n s . . .
B u i l d i n g and o p t i m i z i n g f i n a l n e t l i s t . . .
INFO : Xst : 2 2 6 0 − The FF/ Latch <mb_plb/GEN_MPLB_RST[ 1 ] . I_MPLB_RST> i n
Unit <mb_plb> i s e q u i v a l e n t to the f o l l o w i n g 7 FFs/ Latches : <
mb_plb/GEN_MPLB_RST[ 0 ] . I_MPLB_RST> <mb_plb/GEN_SPLB_RST [ 4 ] .
I_SPLB_RST> <mb_plb/GEN_SPLB_RST [ 3 ] . I_SPLB_RST> <mb_plb/
GEN_SPLB_RST [ 2 ] . I_SPLB_RST> <mb_plb/GEN_SPLB_RST [ 1 ] . I_SPLB_RST> <
mb_plb/GEN_SPLB_RST [ 0 ] . I_SPLB_RST> <mb_plb/I_PLB_RST>
INFO : Xst : 2 2 6 0 − The FF/ Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/
I_ARBCONTROL_SM/ arbSecRdInProgReg_i> i n Unit <mb_plb> i s
e q u i v a l e n t to the f o l l o w i n g 2 FFs/ Latches : <mb_plb/GEN_SHARED.

151
 I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbSecRdInProgReg_i_1> <mb_plb
/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/
arbSecRdInProgReg_i_2>
INFO : Xst : 2 2 6 0 − The FF/ Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/
I_ARB_ENCODER/arbAddrSelReg_i_1> i n Unit <mb_plb> i s e q u i v a l e n t to
the f o l l o w i n g FF/ Latch : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/
I_ARB_ENCODER/arbAddrSelReg_i_1_1>
INFO : Xst : 2 2 6 0 − The FF/ Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/
I_ARB_ENCODER/arbAddrSelReg_i_0> i n Unit <mb_plb> i s e q u i v a l e n t to
the f o l l o w i n g FF/ Latch : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/
I_ARB_ENCODER/arbAddrSelReg_i_0_1>
INFO : Xst : 2 2 6 0 − The FF/ Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/
I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd3> i n Unit <mb_plb> i s
e q u i v a l e n t to the f o l l o w i n g FF/ Latch : <mb_plb/GEN_SHARED.
I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd3_1>
INFO : Xst : 2 2 6 0 − The FF/ Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/
I_ARBCONTROL_SM/ arbSecRdInProgReg_i> i n Unit <mb_plb> i s
e q u i v a l e n t to the f o l l o w i n g 2 FFs/ Latches : <mb_plb/GEN_SHARED.
I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbSecRdInProgReg_i_1> <mb_plb
/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/
arbSecRdInProgReg_i_2>
INFO : Xst : 2 2 6 0 − The FF/ Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/
I_ARB_ENCODER/arbAddrSelReg_i_0> i n Unit <mb_plb> i s e q u i v a l e n t to
the f o l l o w i n g FF/ Latch : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/
I_ARB_ENCODER/arbAddrSelReg_i_0_1>
INFO : Xst : 2 2 6 0 − The FF/ Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/
I_ARB_ENCODER/arbAddrSelReg_i_1> i n Unit <mb_plb> i s e q u i v a l e n t to
the f o l l o w i n g FF/ Latch : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/
I_ARB_ENCODER/arbAddrSelReg_i_1_1>
INFO : Xst : 2 2 6 0 − The FF/ Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/
I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd3> i n Unit <mb_plb> i s
e q u i v a l e n t to the f o l l o w i n g FF/ Latch : <mb_plb/GEN_SHARED.
I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd3_1>
INFO : Xst : 2 2 6 0 − The FF/ Latch <mb_plb/GEN_MPLB_RST[ 1 ] . I_MPLB_RST> i n
Unit <mb_plb> i s e q u i v a l e n t to the f o l l o w i n g 7 FFs/ Latches : <
mb_plb/GEN_MPLB_RST[ 0 ] . I_MPLB_RST> <mb_plb/GEN_SPLB_RST [ 4 ] .
I_SPLB_RST> <mb_plb/GEN_SPLB_RST [ 3 ] . I_SPLB_RST> <mb_plb/
GEN_SPLB_RST [ 2 ] . I_SPLB_RST> <mb_plb/GEN_SPLB_RST [ 1 ] . I_SPLB_RST> <
mb_plb/GEN_SPLB_RST [ 0 ] . I_SPLB_RST> <mb_plb/I_PLB_RST>

F i n a l Macro P r o c e s s i n g . . .

=========================================================================

F i n a l R e g i s t e r Report

Found no macro
=========================================================================

152
=========================================================================

∗ P a r t i t i o n Report
∗
=========================================================================

P a r t i t i o n Implementation S tatus
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

No P a r t i t i o n s were found i n t h i s d e s i g n .

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

=========================================================================

∗ F i n a l Report
∗
=========================================================================

Final Results
Top Level Output F i l e Name : . . / implementation / system . ngc
Output Format : ngc
Optimization Goal : speed
Keep Hierarchy : no

Design S t a t i s t i c s
# IOs : 32

C e l l Usage :
# BELS : 3937
# GND : 16
# INV : 54
# LUT1 : 128
# LUT2 : 251
# LUT3 : 519
# LUT4 : 522
# LUT5 : 506
# LUT6 : 948
# LUT6_2 : 31
# MULT_AND : 12
# MUXCY : 266
# MUXCY_L : 196
# MUXF5 : 39
# MUXF7 : 123
# MUXF7_L : 4
# MUXF8_L : 2
# VCC : 12

153
# XORCY : 308
# F l i p F l o p s / Latches : 3042
# FD : 240
# FDC : 63
# FDC_1 : 5
# FDCE : 47
# FDE : 534
# FDE_1 : 5
# FDP : 25
# FDR : 795
# FDRE : 1184
# FDRE_1 : 1
# FDRS : 20
# FDRSE : 6
# FDS : 59
# FDSE : 58
# RAMS : 55
# RAM32M : 21
# RAM32X1D : 2
# RAMB36_EXP : 32
# Shift Registers : 90
# SRL16 : 3
# SRL16E : 32
# SRLC16E : 55
# Clock B u f f e r s : 6
# BUFG : 5
# BUFGP : 1
# IO B u f f e r s : 31
# IBUF : 4
# IOBUF : 16
# OBUF : 11
# DSPs : 5
# DSP48E : 5
# Others : 2
# BSCAN_VIRTEX5 : 1
# PLL_ADV : 1
=========================================================================

Device u t i l i z a t i o n summary :
−−−−−−−−−−−−−−−−−−−−−−−−−−−

S e l e c t e d Device : 5 v l x 5 0 f f 6 7 6 −1

S l i c e Logic U t i l i z a t i o n :
Number o f S l i c e R e g i s t e r s : 2984 out o f 28800 10%
Number o f S l i c e LUTs : 3137 out o f 28800 10%
Number used as Logic : 2959 out o f 28800 10%

154
 Number used as Memory : 178 out o f 7680 2%
Number used as RAM: 88
Number used as SRL : 90

S l i c e Logic D i s t r i b u t i o n :
Number o f LUT F l i p Flop p a i r s used : 4892
Number with an unused F l i p Flop : 1908 out o f 4892 39%
Number with an unused LUT: 1755 out o f 4892 35%
Number o f f u l l y used LUT−FF p a i r s : 1229 out o f 4892 25%
Number o f unique c o n t r o l s e t s : 295

IO U t i l i z a t i o n :
Number o f IOs : 32
Number o f bonded IOBs : 32 out o f 440 7%
IOB F l i p Flops / Latches : 58

S p e c i f i c Feature U t i l i z a t i o n :
Number o f Block RAM/FIFO : 32 out o f 48 66%
Number u s i n g Block RAM only : 32
Number o f BUFG/BUFGCTRLs: 6 out o f 32 18%
Number o f DSP48Es : 5 out o f 48 10%
Number o f PLL_ADVs: 1 out o f 6 16%

−−−−−−−−−−−−−−−−−−−−−−−−−−−
P a r t i t i o n Resource Summary :
−−−−−−−−−−−−−−−−−−−−−−−−−−−

No P a r t i t i o n s were found i n t h i s d e s i g n .

−−−−−−−−−−−−−−−−−−−−−−−−−−−

=========================================================================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE
REPORT
GENERATED AFTER PLACE−and−ROUTE.

Clock I n f o r m a t i o n :
−−−−−−−−−−−−−−−−−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−−−+−−−−

Clock S i g n a l | Clock b u f f e r (FF

name ) | Load |
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−−−+−−−−

155
clock_generator_0 / clock_generator_0 /PLL0_CLK_OUT<0>| BUFG
| 2858 |
mdm_0/mdm_0/ drck_i | BUFG
| 204 |
mdm_0/ bscan_update1 | BUFG
| 35 |
fpga_0_SysACE_CompactFlash_SysACE_CLK_pin | BUFGP
| 95 |
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−+−−−−−−−−−−−−−−−−−−−−−−−−+−−−−

Asynchronous Control S i g n a l s I n f o r m a t i o n :
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Control S i g n a l

| B u f f e r (FF name )

| Load |
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

lmb_bram/lmb_bram/net_gnd0 (lmb_bram/lmb_bram/XST_GND:G)

| NONE(lmb_bram/lmb_bram/ramb36_0 )
|
128 |
mb_plb/SPLB_Rst<2>(mb_plb/mb_plb/GEN_SPLB_RST [ 2 ] . I_SPLB_RST:Q)

| NONE( SysACE_CompactFlash/SysACE_CompactFlash/I_SYSACE_CONTROLLER
/MEM_STATE_MACHINE_I/Done ) | 89 |
mdm_0/mdm_0/MDM_Core_I1/Config_Reg_Acst_inv (mdm_0/mdm_0/MDM_Core_I1/
Config_Reg_Acst_inv1_INV_0 :O)

| NONE(mdm_0/mdm_0/MDM_Core_I1/Config_Reg_0 )
| 23 |
mdm_0/mdm_0/MDM_Core_I1/SEL_inv (mdm_0/mdm_0/MDM_Core_I1/
SEL_inv1_INV_0 :O)

| NONE(mdm_0/mdm_0/MDM_Core_I1/PORT_Selector_0 )
| 12 |
SysACE_CompactFlash/SysACE_CompactFlash/I_SYSACE_CONTROLLER/
SYNC_2_CLOCKS_I/ done3 ( SysACE_CompactFlash/SysACE_CompactFlash/
I_SYSACE_CONTROLLER/SYNC_2_CLOCKS_I/DONE_REG3:Q) | NONE(
SysACE_CompactFlash/SysACE_CompactFlash/I_SYSACE_CONTROLLER/
SYNC_2_CLOCKS_I/RDCE_REG1) | 6 |
microblaze_0 / microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/
Command_Reg_Rst( microblaze_0 / microblaze_0 / Performance .
Use_Debug_Logic . Debug_I1/Command_Reg_Rst :Q) | NONE(

156
 microblaze_0 / microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/
command_reg_0 ) | 2 |
mdm_0/mdm_0/MDM_Core_I1/ PLB_Interconnect .JTAG_CONTROL_I/data_cmd_inv (
mdm_0/mdm_0/MDM_Core_I1/ PLB_Interconnect .JTAG_CONTROL_I/
data_cmd_inv1_INV_0 :O) | NONE(mdm_0/mdm_0/
MDM_Core_I1/ PLB_Interconnect .JTAG_CONTROL_I/ e x e c u t e )
| 1 |
mdm_0/mdm_0/MDM_Core_I1/ PLB_Interconnect .JTAG_CONTROL_I/ local_sel_n3 (
mdm_0/mdm_0/MDM_Core_I1/ PLB_Interconnect .JTAG_CONTROL_I/
Insert_Delays [ 4 ] . LUT_Delay :O) | NONE(mdm_0/mdm_0/
MDM_Core_I1/ PLB_Interconnect .JTAG_CONTROL_I/FDC_I)
| 1 |
mdm_0/mdm_0/MDM_Core_I1/reset_RX_FIFO (mdm_0/mdm_0/MDM_Core_I1/
reset_RX_FIFO :Q)

| NONE(mdm_0/mdm_0/MDM_Core_I1/ PLB_Interconnect .JTAG_CONTROL_I/

Have_UARTs .RX_FIFO_I/ data_Exists_I ) | 1 |
mdm_0/mdm_0/MDM_Core_I1/reset_TX_FIFO (mdm_0/mdm_0/MDM_Core_I1/
reset_TX_FIFO :Q)

| NONE(mdm_0/mdm_0/MDM_Core_I1/ PLB_Interconnect .JTAG_CONTROL_I/

Have_UARTs . TX_FIFO_I/ data_Exists_I ) | 1 |
microblaze_0 / microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/
continue_from_brk ( microblaze_0 / microblaze_0 / Performance .
Use_Debug_Logic . Debug_I1/ continue_from_brk :Q) | NONE(
microblaze_0 / microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/
continue_from_brk_TClk ) | 1 |
microblaze_0 / microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/
force_stop_CMD ( microblaze_0 / microblaze_0 / Performance .
Use_Debug_Logic . Debug_I1/force_stop_CMD :Q) | NONE(
microblaze_0 / microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/
force_stop_TClk ) | 1 |
microblaze_0 / microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/
normal_stop_cmd ( microblaze_0 / microblaze_0 / Performance .
Use_Debug_Logic . Debug_I1/normal_stop_cmd :Q) | NONE(
microblaze_0 / microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/
normal_stop_TClk ) | 1 |
microblaze_0 / microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/
s t a r t _ s i n g l e _ s t e p ( microblaze_0 / microblaze_0 / Performance .
Use_Debug_Logic . Debug_I1/ s t a r t _ s i n g l e _ s t e p :Q) | NONE(
microblaze_0 / microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/
single_Step_TClk ) | 1 |
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Timing Summary :
−−−−−−−−−−−−−−−
Speed Grade : −1

157
 Minimum p e r i o d : 6 . 1 9 8 ns (Maximum Frequency : 161.342MHz)
Minimum input a r r i v a l time b e f o r e c l o c k : 2 . 7 5 0 ns
Maximum output r e q u i r e d time a f t e r c l o c k : 7 . 2 0 6 ns
Maximum combinational path delay : 1 . 3 9 7 ns

Timing D e t a i l :
−−−−−−−−−−−−−−
A l l v a l u e s d i s p l a y e d i n nanoseconds ( ns )

=========================================================================

Timing c o n s t r a i n t : D e f a u l t p e r i o d a n a l y s i s f o r Clock '

clock_generator_0 / clock_generator_0 /PLL0_CLK_OUT<0>'
Clock p e r i o d : 5 . 9 9 7 ns ( f r e q u e n c y : 166.750MHz)
Total number o f paths / d e s t i n a t i o n p o r t s : 763463 / 9782
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Delay : 5 . 9 9 7 ns ( L e v e l s o f Logic = 6)
Source : microblaze_0 / microblaze_0 / Performance .
Data_Flow_I/FPU_I/mem_MantA_2_31 (FF)
Destination : microblaze_0 / microblaze_0 / Performance .
Data_Flow_I/FPU_I/Use_FPU .FPU_ADDSUB_I/mem_MantB_3_34 (FF)
Source Clock : clock_generator_0 / clock_generator_0 /PLL0_CLK_OUT
<0> r i s i n g
D e s t i n a t i o n Clock : clock_generator_0 / clock_generator_0 /PLL0_CLK_OUT
<0> r i s i n g

Data Path : microblaze_0 / microblaze_0 / Performance . Data_Flow_I/FPU_I/

mem_MantA_2_31 to microblaze_0 / microblaze_0 / Performance .
Data_Flow_I/FPU_I/Use_FPU .FPU_ADDSUB_I/mem_MantB_3_34
Gate Net
C e l l : in −>out fanout Delay Delay L o g i c a l Name ( Net Name)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−−−−
FDRE: C−>Q 3 0.471 1 . 0 8 0 microblaze_0 /
Performance . Data_Flow_I/FPU_I/mem_MantA_2_31 ( microblaze_0 /
Performance . Data_Flow_I/FPU_I/mem_MantA_2<31>)
LUT6 : I0 −>O 4 0.094 0 . 7 2 6 microblaze_0 /
Performance . Data_Flow_I/FPU_I/Use_FPU .FPU_ADDSUB_I/
mem_rot_mux1<31>1 ( microblaze_0 / Performance . Data_Flow_I/FPU_I
/Use_FPU .FPU_ADDSUB_I/mem_rot_mux1<31>)
LUT5 : I2 −>O 6 0.094 0 . 8 1 6 microblaze_0 /
Performance . Data_Flow_I/FPU_I/Use_FPU .FPU_ADDSUB_I/
mem_rot_mux2<11>1 ( microblaze_0 / Performance . Data_Flow_I/FPU_I
/Use_FPU .FPU_ADDSUB_I/mem_rot_mux2<11>)
LUT6 : I2 −>O 2 0.094 0 . 7 9 4 microblaze_0 /
Performance . Data_Flow_I/FPU_I/Use_FPU .FPU_ADDSUB_I/
mem_rot_mux3<27>1 ( microblaze_0 / Performance . Data_Flow_I/FPU_I
/Use_FPU .FPU_ADDSUB_I/mem_rot_mux3<27>)

158
 LUT6 : I2 −>O 1 0.094 0 . 0 0 0 microblaze_0 /
Performance . Data_Flow_I/FPU_I/Use_FPU .FPU_ADDSUB_I/
mem_mant_sticky_3_cmb113_F ( N535 )
MUXF7: I0 −>O 1 0.251 0 . 4 8 0 microblaze_0 /
Performance . Data_Flow_I/FPU_I/Use_FPU .FPU_ADDSUB_I/
mem_mant_sticky_3_cmb113 ( microblaze_0 / Performance .
Data_Flow_I/FPU_I/Use_FPU .FPU_ADDSUB_I/
mem_mant_sticky_3_cmb113 )
LUT5 : I4 −>O 1 0.094 0 . 3 3 6 microblaze_0 /
Performance . Data_Flow_I/FPU_I/Use_FPU .FPU_ADDSUB_I/
mem_mant_sticky_3_cmb164 ( microblaze_0 / Performance .
Data_Flow_I/FPU_I/Use_FPU .FPU_ADDSUB_I/
mem_mant_sticky_3_cmb164 )
FDRS: S 0.573 microblaze_0 /
Performance . Data_Flow_I/FPU_I/Use_FPU .FPU_ADDSUB_I/
mem_MantB_3_34
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Total 5 . 9 9 7 ns ( 1 . 7 6 5 ns l o g i c , 4 . 2 3 2 ns r o u t e )
(29.4% l o g i c , 70.6% r o u t e )

=========================================================================

Timing c o n s t r a i n t : D e f a u l t p e r i o d a n a l y s i s f o r Clock 'mdm_0/mdm_0/

drck_i '
Clock p e r i o d : 6 . 1 9 8 ns ( f r e q u e n c y : 161.342MHz)
Total number o f paths / d e s t i n a t i o n p o r t s : 302 / 250
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Delay : 3 . 0 9 9 ns ( L e v e l s o f Logic = 4)
Source : mdm_0/mdm_0/MDM_Core_I1/ PLB_Interconnect .
JTAG_CONTROL_I/SYNC_FDRE (FF)
Destination : microblaze_0 / microblaze_0 / Performance .
Use_Debug_Logic . Debug_I1/ shift_Count_0 (FF)
Source Clock : mdm_0/mdm_0/ drck_i f a l l i n g
D e s t i n a t i o n Clock : mdm_0/mdm_0/ drck_i r i s i n g

Data Path : mdm_0/mdm_0/MDM_Core_I1/ PLB_Interconnect .JTAG_CONTROL_I/

SYNC_FDRE to microblaze_0 / microblaze_0 / Performance .
Use_Debug_Logic . Debug_I1/ shift_Count_0
Gate Net
C e l l : in −>out fanout Delay Delay L o g i c a l Name ( Net Name)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−−−−
FDRE_1: C−>Q 1 0.467 0 . 9 7 3 PLB_Interconnect .
JTAG_CONTROL_I/SYNC_FDRE ( PLB_Interconnect .JTAG_CONTROL_I/
sync )
LUT6 : I1 −>O 9 0.094 0 . 3 8 0 PLB_Interconnect .
JTAG_CONTROL_I/ shifting_Data ( Dbg_Shift_7 )
end scope : 'mdm_0/MDM_Core_I1 '
end scope : 'mdm_0 '

159
 begin scope : ' microblaze_0 '
INV : I −>O 8 0.238 0 . 3 7 4 microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/Shift_inv1_INV_0 (
microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/ S h i f t _ i n v )
FDR:R 0.573 microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/ shift_Count_0
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Total 3 . 0 9 9 ns ( 1 . 3 7 2 ns l o g i c , 1 . 7 2 7 ns r o u t e )
(44.3% l o g i c , 55.7% r o u t e )

=========================================================================

Timing c o n s t r a i n t : D e f a u l t p e r i o d a n a l y s i s f o r Clock 'mdm_0/

bscan_update1 '
Clock p e r i o d : 5 . 7 4 6 ns ( f r e q u e n c y : 174.034MHz)
Total number o f paths / d e s t i n a t i o n p o r t s : 209 / 40
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Delay : 2 . 8 7 3 ns ( L e v e l s o f Logic = 4)
Source : mdm_0/mdm_0/MDM_Core_I1/ PLB_Interconnect .
JTAG_CONTROL_I/FDC_I (FF)
Destination : microblaze_0 / microblaze_0 / Performance .
Use_Debug_Logic . Debug_I1/ force_stop_TClk (FF)
Source Clock : mdm_0/ bscan_update1 f a l l i n g
D e s t i n a t i o n Clock : mdm_0/ bscan_update1 r i s i n g

Data Path : mdm_0/mdm_0/MDM_Core_I1/ PLB_Interconnect .JTAG_CONTROL_I/

FDC_I to microblaze_0 / microblaze_0 / Performance . Use_Debug_Logic .
Debug_I1/ force_stop_TClk
Gate Net
C e l l : in −>out fanout Delay Delay L o g i c a l Name ( Net Name)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−−−−
FDC_1: C−>Q 10 0.467 0 . 6 2 5 PLB_Interconnect .
JTAG_CONTROL_I/FDC_I ( PLB_Interconnect .JTAG_CONTROL_I/
data_cmd )
LUT2 : I0 −>O 6 0.094 1 . 0 0 0 PLB_Interconnect .
JTAG_CONTROL_I/Dbg_Reg_En_I<4>1 (Dbg_Reg_En_0<4>)
end scope : 'mdm_0/MDM_Core_I1 '
end scope : 'mdm_0 '
begin scope : ' microblaze_0 '
LUT5 : I0 −>O 9 0.094 0 . 3 8 0 microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/
Control_Reg_En_cmp_eq00001 ( microblaze_0 / Performance .
Use_Debug_Logic . Debug_I1/Control_Reg_En )
FDCE:CE 0.213 microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/ force_stop_TClk
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Total 2 . 8 7 3 ns ( 0 . 8 6 8 ns l o g i c , 2 . 0 0 5 ns r o u t e )
(30.2% l o g i c , 69.8% r o u t e )

160
=========================================================================

Timing c o n s t r a i n t : D e f a u l t p e r i o d a n a l y s i s f o r Clock '

fpga_0_SysACE_CompactFlash_SysACE_CLK_pin '
Clock p e r i o d : 2 . 2 2 4 ns ( f r e q u e n c y : 449.640MHz)
Total number o f paths / d e s t i n a t i o n p o r t s : 227 / 70
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Delay : 2 . 2 2 4 ns ( L e v e l s o f Logic = 2)
Source : SysACE_CompactFlash/SysACE_CompactFlash/
I_SYSACE_CONTROLLER/MEM_STATE_MACHINE_I/current_State_FSM_FFd4 (
FF)
Destination : SysACE_CompactFlash/SysACE_CompactFlash/
I_SYSACE_CONTROLLER/MEM_STATE_MACHINE_I/SYSACE_WEN_REG (FF)
Source Clock : fpga_0_SysACE_CompactFlash_SysACE_CLK_pin r i s i n g
D e s t i n a t i o n Clock : fpga_0_SysACE_CompactFlash_SysACE_CLK_pin r i s i n g

Data Path : SysACE_CompactFlash/SysACE_CompactFlash/

I_SYSACE_CONTROLLER/MEM_STATE_MACHINE_I/current_State_FSM_FFd4
to SysACE_CompactFlash/SysACE_CompactFlash/I_SYSACE_CONTROLLER/
MEM_STATE_MACHINE_I/SYSACE_WEN_REG
Gate Net
C e l l : in −>out fanout Delay Delay L o g i c a l Name ( Net Name)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−−−−
FDC: C−>Q 3 0.471 1 . 0 8 0 SysACE_CompactFlash/
I_SYSACE_CONTROLLER/MEM_STATE_MACHINE_I/
current_State_FSM_FFd4 ( SysACE_CompactFlash/
I_SYSACE_CONTROLLER/MEM_STATE_MACHINE_I/
current_State_FSM_FFd4 )
LUT6 : I0 −>O 2 0.094 0 . 4 8 5 SysACE_CompactFlash/
I_SYSACE_CONTROLLER/MEM_STATE_MACHINE_I/sysace_wen_cmb21 (
SysACE_CompactFlash/I_SYSACE_CONTROLLER/MEM_STATE_MACHINE_I/
N3)
LUT3 : I2 −>O 1 0.094 0 . 0 0 0 SysACE_CompactFlash/
I_SYSACE_CONTROLLER/MEM_STATE_MACHINE_I/sysace_wen_cmb1 (
SysACE_CompactFlash/I_SYSACE_CONTROLLER/MEM_STATE_MACHINE_I/
sysace_wen_cmb )
FDP:D − 0.018 SysACE_CompactFlash/
I_SYSACE_CONTROLLER/MEM_STATE_MACHINE_I/SYSACE_WEN_REG
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Total 2 . 2 2 4 ns ( 0 . 6 5 9 ns l o g i c , 1 . 5 6 5 ns r o u t e )
(29.6% l o g i c , 70.4% r o u t e )

=========================================================================

Timing c o n s t r a i n t : D e f a u l t OFFSET IN BEFORE f o r Clock '

clock_generator_0 / clock_generator_0 /PLL0_CLK_OUT<0>'
Total number o f paths / d e s t i n a t i o n p o r t s : 3 / 3

161
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Offset : 1 . 7 3 3 ns ( L e v e l s o f Logic = 3)
Source : fpga_0_rst_1_sys_rst_pin (PAD)
Destination : proc_sys_reset_0 / proc_sys_reset_0 /EXT_LPF/exr_d1
(FF)
D e s t i n a t i o n Clock : clock_generator_0 / clock_generator_0 /PLL0_CLK_OUT
<0> r i s i n g

Data Path : fpga_0_rst_1_sys_rst_pin to proc_sys_reset_0 /

proc_sys_reset_0 /EXT_LPF/exr_d1
Gate Net
C e l l : in −>out fanout Delay Delay L o g i c a l Name ( Net Name)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−−−−
IBUF : I −>O 2 0.818 0.341
fpga_0_rst_1_sys_rst_pin_IBUF ( fpga_0_rst_1_sys_rst_pin_IBUF )
begin scope : ' proc_sys_reset_0 '
INV : I −>O 1 0.238 0 . 3 3 6 proc_sys_reset_0 /
EXT_LPF/exr_d1_or000011_INV_0 ( proc_sys_reset_0 /EXT_LPF/
exr_d1_or00001 )
FDS :D − 0.018 proc_sys_reset_0 /
EXT_LPF/exr_d1
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Total 1 . 7 3 3 ns ( 1 . 0 5 6 ns l o g i c , 0 . 6 7 7 ns r o u t e )
(60.9% l o g i c , 39.1% r o u t e )

=========================================================================

Timing c o n s t r a i n t : D e f a u l t OFFSET IN BEFORE f o r Clock 'mdm_0/mdm_0/

drck_i '
Total number o f paths / d e s t i n a t i o n p o r t s : 129 / 96
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Offset : 2 . 7 5 0 ns ( L e v e l s o f Logic = 4)
Source : mdm_0/mdm_0/ Use_Virtex5 .BSCAN_VIRTEX5_I: SHIFT (
PAD)
Destination : microblaze_0 / microblaze_0 / Performance .
Use_Debug_Logic . Debug_I1/ shift_Count_0 (FF)
D e s t i n a t i o n Clock : mdm_0/mdm_0/ drck_i r i s i n g

Data Path : mdm_0/mdm_0/ Use_Virtex5 .BSCAN_VIRTEX5_I: SHIFT to

microblaze_0 / microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/
shift_Count_0
Gate Net
C e l l : in −>out fanout Delay Delay L o g i c a l Name ( Net Name)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−−−−
BSCAN_VIRTEX5: SHIFT 5 0.000 0.000 mdm_0/ Use_Virtex5 .
BSCAN_VIRTEX5_I ( b s c a n _ s h i f t )
begin scope : 'mdm_0/MDM_Core_I1 '

162
 LUT6 : I0 −>O 9 0.094 0 . 3 8 0 PLB_Interconnect .
JTAG_CONTROL_I/ shifting_Data ( Dbg_Shift_7 )
end scope : 'mdm_0/MDM_Core_I1 '
end scope : 'mdm_0 '
begin scope : ' microblaze_0 '
INV : I −>O 8 0.238 0 . 3 7 4 microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/Shift_inv1_INV_0 (
microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/ S h i f t _ i n v )
FDR:R 0.573 microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/ shift_Count_0
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Total 2 . 7 5 0 ns ( 1 . 9 9 6 ns l o g i c , 0 . 7 5 4 ns r o u t e )
(72.6% l o g i c , 27.4% r o u t e )

=========================================================================

Timing c o n s t r a i n t : D e f a u l t OFFSET IN BEFORE f o r Clock 'mdm_0/

bscan_update1 '
Total number o f paths / d e s t i n a t i o n p o r t s : 14 / 14
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Offset : 1 . 6 7 0 ns ( L e v e l s o f Logic = 2)
Source : mdm_0/mdm_0/ Use_Virtex5 .BSCAN_VIRTEX5_I: SEL (PAD
)
Destination : mdm_0/mdm_0/MDM_Core_I1/PORT_Selector_1_0 (FF)
D e s t i n a t i o n Clock : mdm_0/ bscan_update1 r i s i n g

Data Path : mdm_0/mdm_0/ Use_Virtex5 .BSCAN_VIRTEX5_I: SEL to mdm_0/

mdm_0/MDM_Core_I1/PORT_Selector_1_0
Gate Net
C e l l : in −>out fanout Delay Delay L o g i c a l Name ( Net Name)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−−−−
BSCAN_VIRTEX5: SEL 8 0.000 0.000 mdm_0/ Use_Virtex5 .
BSCAN_VIRTEX5_I (mdm_0/ s e l )
begin scope : 'mdm_0/MDM_Core_I1 '
LUT5 : I0 −>O 4 0.094 0.352 MDM_SEL1 (MDM_SEL)
FDCE:CE 0.213 PORT_Selector_1_0
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Total 1 . 6 7 0 ns ( 1 . 3 1 8 ns l o g i c , 0 . 3 5 2 ns r o u t e )
(78.9% l o g i c , 21.1% r o u t e )

=========================================================================

Timing c o n s t r a i n t : D e f a u l t OFFSET IN BEFORE f o r Clock '

fpga_0_SysACE_CompactFlash_SysACE_CLK_pin '
Total number o f paths / d e s t i n a t i o n p o r t s : 16 / 16
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Offset : 1 . 1 5 4 ns ( L e v e l s o f Logic = 2)

163
 Source : fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> (
PAD)
Destination : SysACE_CompactFlash/SysACE_CompactFlash/
I_SYSACE_CONTROLLER/SYNC_2_CLOCKS_I/MEM_DQ_I_GEN[ 7 ] .MEM_DQ_I_1 (
FF)
D e s t i n a t i o n Clock : fpga_0_SysACE_CompactFlash_SysACE_CLK_pin r i s i n g

Data Path : fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> to

SysACE_CompactFlash/SysACE_CompactFlash/I_SYSACE_CONTROLLER/
SYNC_2_CLOCKS_I/MEM_DQ_I_GEN[ 7 ] .MEM_DQ_I_1
Gate Net
C e l l : in −>out fanout Delay Delay L o g i c a l Name ( Net Name)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−−−−
IOBUF : IO−>O 1 0.818 0 . 3 3 6 iobuf_15 (
fpga_0_SysACE_CompactFlash_SysACE_MPD_pin_I<0>)
begin scope : ' SysACE_CompactFlash '
FDCE:D − 0.018 SysACE_CompactFlash/
I_SYSACE_CONTROLLER/SYNC_2_CLOCKS_I/MEM_DQ_I_GEN[ 7 ] .
MEM_DQ_I_1
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Total 1 . 1 5 4 ns ( 0 . 8 1 8 ns l o g i c , 0 . 3 3 6 ns r o u t e )
(70.9% l o g i c , 29.1% r o u t e )

=========================================================================

Timing c o n s t r a i n t : D e f a u l t OFFSET OUT AFTER f o r Clock '

fpga_0_SysACE_CompactFlash_SysACE_CLK_pin '
Total number o f paths / d e s t i n a t i o n p o r t s : 42 / 26
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Offset : 3 . 2 5 9 ns ( L e v e l s o f Logic = 2)
Source : SysACE_CompactFlash/SysACE_CompactFlash/
I_SYSACE_CONTROLLER/MEM_STATE_MACHINE_I/SYSACE_CEN_REG (FF)
Destination : fpga_0_SysACE_CompactFlash_SysACE_CEN_pin (PAD)
Source Clock : fpga_0_SysACE_CompactFlash_SysACE_CLK_pin r i s i n g

Data Path : SysACE_CompactFlash/SysACE_CompactFlash/

I_SYSACE_CONTROLLER/MEM_STATE_MACHINE_I/SYSACE_CEN_REG to
fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
Gate Net
C e l l : in −>out fanout Delay Delay L o g i c a l Name ( Net Name)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−−−−
FDP: C−>Q 1 0.471 0 . 3 3 6 SysACE_CompactFlash/
I_SYSACE_CONTROLLER/MEM_STATE_MACHINE_I/SYSACE_CEN_REG (
SysACE_CEN)
end scope : ' SysACE_CompactFlash '
OBUF: I −>O 2.452
fpga_0_SysACE_CompactFlash_SysACE_CEN_pin_OBUF (
fpga_0_SysACE_CompactFlash_SysACE_CEN_pin)

164
 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Total 3 . 2 5 9 ns ( 2 . 9 2 3 ns l o g i c , 0 . 3 3 6 ns r o u t e )
(89.7% l o g i c , 10.3% r o u t e )

=========================================================================

Timing c o n s t r a i n t : D e f a u l t OFFSET OUT AFTER f o r Clock '

clock_generator_0 / clock_generator_0 /PLL0_CLK_OUT<0>'
Total number o f paths / d e s t i n a t i o n p o r t s : 1 / 1
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Offset : 3 . 2 5 9 ns ( L e v e l s o f Logic = 2)
Source : RS232_Uart/RS232_Uart/UARTLITE_CORE_I/
UARTLITE_TX_I/TX (FF)
Destination : fpga_0_RS232_Uart_TX_pin (PAD)
Source Clock : clock_generator_0 / clock_generator_0 /PLL0_CLK_OUT
<0> r i s i n g

Data Path : RS232_Uart/RS232_Uart/UARTLITE_CORE_I/UARTLITE_TX_I/TX

to fpga_0_RS232_Uart_TX_pin
Gate Net
C e l l : in −>out fanout Delay Delay L o g i c a l Name ( Net Name)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−−−−
FDS : C−>Q 1 0.471 0 . 3 3 6 RS232_Uart/
UARTLITE_CORE_I/UARTLITE_TX_I/TX (TX)
end scope : ' RS232_Uart '
OBUF: I −>O 2.452
fpga_0_RS232_Uart_TX_pin_OBUF ( fpga_0_RS232_Uart_TX_pin )
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Total 3 . 2 5 9 ns ( 2 . 9 2 3 ns l o g i c , 0 . 3 3 6 ns r o u t e )
(89.7% l o g i c , 10.3% r o u t e )

=========================================================================

Timing c o n s t r a i n t : D e f a u l t OFFSET OUT AFTER f o r Clock 'mdm_0/mdm_0/

drck_i '
Total number o f paths / d e s t i n a t i o n p o r t s : 119 / 1
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Offset : 7 . 2 0 6 ns ( L e v e l s o f Logic = 8)
Source : microblaze_0 / microblaze_0 / Performance .
Use_Debug_Logic . Debug_I1/Use_SRL16 . The_Cache_Addresses [ 5 ] .
SRL16E_Cache_I (FF)
Destination : mdm_0/mdm_0/ Use_Virtex5 .BSCAN_VIRTEX5_I:TDO (PAD
)
Source Clock : mdm_0/mdm_0/ drck_i r i s i n g

Data Path : microblaze_0 / microblaze_0 / Performance . Use_Debug_Logic .

Debug_I1/Use_SRL16 . The_Cache_Addresses [ 5 ] . SRL16E_Cache_I to

165
 mdm_0/mdm_0/ Use_Virtex5 .BSCAN_VIRTEX5_I:TDO
Gate Net
C e l l : in −>out fanout Delay Delay L o g i c a l Name ( Net Name)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−−−−
SRL16E :CLK−>Q 1 1.889 0 . 9 7 3 microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/Use_SRL16 .
The_Cache_Addresses [ 5 ] . SRL16E_Cache_I ( microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/ tdo_config_word1 <6>)
LUT6 : I1 −>O 1 0.094 0 . 9 7 3 microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/TDO42 ( microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/TDO42)
LUT6 : I1 −>O 1 0.094 0 . 0 0 0 microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/TDO387_SW01 (
microblaze_0 / Performance . Use_Debug_Logic . Debug_I1/TDO387_SW0)
MUXF7: I1 −>O 1 0.254 0 . 7 8 9 microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/TDO387_SW0_f7 ( N463 )
LUT6 : I2 −>O 1 0.094 1 . 0 6 9 microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/TDO387 (DBG_TDO)
end scope : ' microblaze_0 '
begin scope : 'mdm_0 '
begin scope : 'mdm_0/MDM_Core_I1 '
LUT6 : I0 −>O 1 0.094 0 . 7 8 9 TDO_i79 (TDO_i79)
LUT6 : I2 −>O 0 0.094 0 . 0 0 0 TDO_i225 (TDO)
end scope : 'mdm_0/MDM_Core_I1 '
BSCAN_VIRTEX5:TDO 0.000 mdm_0/ Use_Virtex5 .
BSCAN_VIRTEX5_I
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Total 7 . 2 0 6 ns ( 2 . 6 1 3 ns l o g i c , 4 . 5 9 3 ns r o u t e )
(36.3% l o g i c , 63.7% r o u t e )

=========================================================================

Timing c o n s t r a i n t : D e f a u l t OFFSET OUT AFTER f o r Clock 'mdm_0/

bscan_update1 '
Total number o f paths / d e s t i n a t i o n p o r t s : 36 / 1
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Offset : 4 . 9 9 6 ns ( L e v e l s o f Logic = 9)
Source : mdm_0/mdm_0/MDM_Core_I1/ PLB_Interconnect .
JTAG_CONTROL_I/FDC_I (FF)
Destination : mdm_0/mdm_0/ Use_Virtex5 .BSCAN_VIRTEX5_I:TDO (PAD
)
Source Clock : mdm_0/ bscan_update1 f a l l i n g

Data Path : mdm_0/mdm_0/MDM_Core_I1/ PLB_Interconnect .JTAG_CONTROL_I/

FDC_I to mdm_0/mdm_0/ Use_Virtex5 .BSCAN_VIRTEX5_I:TDO
Gate Net
C e l l : in −>out fanout Delay Delay L o g i c a l Name ( Net Name)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−−−−

166
 FDC_1: C−>Q 10 0.467 0 . 6 2 5 PLB_Interconnect .
JTAG_CONTROL_I/FDC_I ( PLB_Interconnect .JTAG_CONTROL_I/
data_cmd )
LUT2 : I0 −>O 6 0.094 1 . 0 9 6 PLB_Interconnect .
JTAG_CONTROL_I/Dbg_Reg_En_I<4>1 (Dbg_Reg_En_0<4>)
end scope : 'mdm_0/MDM_Core_I1 '
end scope : 'mdm_0 '
begin scope : ' microblaze_0 '
LUT6 : I0 −>O 1 0.094 0 . 4 8 0 microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/TDO351 ( microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/TDO351)
LUT6 : I5 −>O 1 0.094 1 . 0 6 9 microblaze_0 /
Performance . Use_Debug_Logic . Debug_I1/TDO387 (DBG_TDO)
end scope : ' microblaze_0 '
begin scope : 'mdm_0 '
begin scope : 'mdm_0/MDM_Core_I1 '
LUT6 : I0 −>O 1 0.094 0 . 7 8 9 TDO_i79 (TDO_i79)
LUT6 : I2 −>O 0 0.094 0 . 0 0 0 TDO_i225 (TDO)
end scope : 'mdm_0/MDM_Core_I1 '
BSCAN_VIRTEX5:TDO 0.000 mdm_0/ Use_Virtex5 .
BSCAN_VIRTEX5_I
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Total 4 . 9 9 6 ns ( 0 . 9 3 7 ns l o g i c , 4 . 0 5 9 ns r o u t e )
(18.8% l o g i c , 81.2% r o u t e )

=========================================================================

Timing c o n s t r a i n t : D e f a u l t path a n a l y s i s
Total number o f paths / d e s t i n a t i o n p o r t s : 2 / 2
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Delay : 1 . 3 9 7 ns ( L e v e l s o f Logic = 3)
Source : fpga_0_rst_1_sys_rst_pin (PAD)
Destination : clock_generator_0 / clock_generator_0 /Using_PLL0 .
PLL0_INST/PLL_INST/Using_PLL_ADV . PLL_ADV_inst :RST (PAD)

Data Path : fpga_0_rst_1_sys_rst_pin to clock_generator_0 /

clock_generator_0 /Using_PLL0 . PLL0_INST/PLL_INST/Using_PLL_ADV .
PLL_ADV_inst :RST
Gate Net
C e l l : in −>out fanout Delay Delay L o g i c a l Name ( Net Name)
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−−−−
IBUF : I −>O 2 0.818 0.341
fpga_0_rst_1_sys_rst_pin_IBUF ( fpga_0_rst_1_sys_rst_pin_IBUF )
begin scope : ' clock_generator_0 '
INV : I −>O 0 0.238 0 . 0 0 0 clock_generator_0 /
Using_PLL0 . PLL0_INST/PLL_INST/rsti1_INV_0 ( clock_generator_0 /
Using_PLL0 . PLL0_INST/PLL_INST/ r s t i )

167
 PLL_ADV:RST 0.000 clock_generator_0 /
Using_PLL0 . PLL0_INST/PLL_INST/Using_PLL_ADV . PLL_ADV_inst
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Total 1 . 3 9 7 ns ( 1 . 0 5 6 ns l o g i c , 0 . 3 4 1 ns r o u t e )
(75.6% l o g i c , 24.4% r o u t e )

=========================================================================

Total REAL time to Xst completion : 2 5 . 0 0 s e c s

Total CPU time to Xst completion : 2 5 . 7 5 s e c s

−−>

Total memory usage i s 257840 k i l o b y t e s

Number o f e r r o r s : 0 ( 0 filtered )
Number o f warnings : 278 ( 0 filtered )
Number o f i n f o s : 10 ( 0 filtered )

168
.4 Matlab Scripts
.4.1 Read Image
a = imread ( ' canyon . g i f ' ) ;
[ y , x]= s i z e ( a ) ;
size_x = x ;
size_y = y ;

b = imnoise ( a , ' s a l t & pepper ' , 0 . 0 2 ) ;

string = ' ( ' ;

f o r j = 1 : size_x
j
f o r i = 1 : size_y
i f ( j==size_x && i==size_y )
s t r i n g = [ s t r i n g , num2str ( b ( i , j ) ) ] ;
else
s t r i n g = [ s t r i n g , num2str ( b ( i , j ) ) , ' , ' ] ;
end ;

end ;
end ;

string = [ string , ' ) ' ] ;

f i l e _ i n = fopen ( ' image_in_0 . 0 2 . pgm ' , 'w ' ) ;
fprintf ( file_in , string ) ;
fclose ( file_in ) ;
size_x
size_y

169
.4.2 Write Image
a = t e x t r e a d ( ' one . pgm ' ) ;
b = a ';
[ y , x]= s i z e ( b ) ;
img = z e r o s ( x , y −(y−x ) ) ;

f o r i = 1 : y−1
for j = 1:x
img ( i , j ) = b ( i , j ) ;
end ;
end ;

s i z e ( img )
imwrite ( img , ' canyon_noise_0 . 0 1 . pgm ' , ' encoding ' , ' a s c i i ' ) ;

170
.4.3 Measuring Values
img = imread ( ' f i e l d . g i f ' ) ;
noisy = imread ( ' field_output_noise_0 . 0 0 1 . png ' ) ;
img = im2double ( img ) ;
noisy = im2double ( n o i s y ) ;

[ x , y]= s i z e ( img ) ;

max_val = max(max( img ) ) ;

[ x , y ] = s i z e ( img ) ;
mse = 0 ;
mae = 0 ;
f o r i =2:x−1
f o r j =2:y−1
mse = mse + ( img ( i , j )− n o i s y ( i , j ) ) ^2;
mae = mae + abs ( img ( i , j )− n o i s y ( i , j ) ) ;
end
end

mse = mse /(2 ∗ x ∗ y ) ;

mae = mae/(2 ∗ x ∗ y ) ;

psnr = 10 ∗ l o g 1 0 ( ( max_val^2) /mse ) ;

mse = mse ∗ 2 5 6 ;
mae = mae ∗ 2 5 6 ;

mse
mae
psnr

171
.4.4 Median algorithm
%image i s the image to be n o i s e d then d e n o i s e d
%m i s the v i n d o w s i z e
%th i s the t h r e s h o l d i n added value , a value o f 0 ,2 w i l l c l a s s e f y any
pixel
%o f + −0,2 as d e f e c t
%n i s the n o i s e p e r c e n t a g e
f u n c t i o n image_median ( image ,m, th , n )
tic ; %s t a r t time
I = imread ( image ) ; %r e a d i n g image f i l e
[ x , y , z ]= s i z e ( I ) ; %c a l c u l a t i n g the s i z e o f
the input image
pixel_map = z e r o s ( x , y , z ) ; %a matrix which s t o r e s
the p o s i t i o n s o f the p i x e l s that have been c o r r e c t e d
img = im2double ( I ) ; %c o n v e r t i n g from u n i t 8 to
double : s c a l e from 0 . . 1 i n s t e a d o f 0−−256
img_noisy = imnoise ( img , ' s a l t & pepper ' , n ) ; %adding n o i s e to the
input image
n o i s e= img_noisy ; %d u p l i c a t i n g the n o i s t
image i n o r d e r to dispay both o f them
% imwrite ( n o i s e , ' img_two_noisy_salt . jpg ' ) ;% w r i t i n g c o r r e c t e d image to
file
%The c o r n e r s , edges and
mid image w i l l have to
be done s e p a r a t e l y
due to
%how matlab i n d e x e s and m
∗ n ∗ 3 matrix . I t i s
i m p o s s i b l e to a c c e s s a
position
%o u t s i d e the matrix . The
image matrix w i l l have
corners (1 ,1) ,(1 , y) ,(x
, 1 ) and
%( x , y )
%c o r r e c t i n g the c o r n e r s
o f a l l the l a y e r s i n
the image by r e p l a c i n g
a noisy
%p i x e l with the median o f
the t h r e e n e i g b o r i n g
p i x e l s . The z v a r i a b l e
will
%be 3 f o r an RGB image .
%l e f t upper c o r n e r ( 1 , 1 )
o f a l l the l a y e r s (3
l a y e r s f o r an RGB
image )

172
f o r k=1: z
c1 =[ img_noisy ( 2 , 1 , k ) , img_noisy ( 2 , 2 , k ) , img_noisy ( 1 , 2 , k ) ] ;
i f ( img_noisy ( 1 , 1 , k )>th+max( c1 ) | | img_noisy ( 1 , 1 , k )<th+min ( c1 ) )
pixel_map ( 1 , 1 , k ) =1;
img_noisy ( 1 , 1 , k )=median ( c1 ) ; %l e f t upper c o r n e r ( 1 , y )
of a l l layers
end
end

f o r k=1: z
c2 =[ img_noisy ( 1 , y − 1,k ) , img_noisy ( 2 , y , k ) , img_noisy ( 2 , y − 1,k ) ] ;
i f ( img_noisy ( 1 , y , k )>th+max( c2 ) | | img_noisy ( 1 , y , k )<th+min ( c2 ) )
pixel_map ( 1 , y , k ) =1;
img_noisy ( 1 , y , k )=median ( c2 ) ; %r i g h t upper c o r n e r ( 1 , y )
of a l l layers
end
end

f o r k=1: z
c3= [ img_noisy ( x , 2 , k ) , img_noisy ( x − 1 ,1 , k ) , img_noisy ( x − 1 ,2 , k ) ] ;
i f ( img_noisy ( x , 1 , k )>th+max( c3 ) | | img_noisy ( x , 1 , k )<th+min ( c3 ) )
pixel_map ( x , 1 , k ) =1;
img_noisy ( x , 1 , k )=median ( c3 ) ; %l e f t lower c o r n e r ( x , 1 )
of a l l layers
end
end

f o r k=1: z
c4 =[ img_noisy ( x , y , k ) , img_noisy ( x − 1,y − 1,k ) , img_noisy ( x − 1,y , k ) ] ;
i f ( img_noisy ( x , y , k )>th+max( c4 ) | | img_noisy ( x , y , k )<th+min ( c4 ) )
pixel_map ( x , y , k ) =1;
img_noisy ( x , y , k )=median ( c4 ) ; %r i g h t lower c o r n e r ( x , y )
of a l l layers
end
end

%c o r r e c t i n g the edges o f
the image i s done by
s t o r i n g the n e i g b o r i n g
%p i x e l v a l u e s and
a s s i g n i n g the median
o f t h o s e v a l u e s to the
p i s i t i o n of
%the d e f e c t p i x e l . The
windowsize i s m, and
c o r r e c t i n g from ( (m− ((
m+1) /2) ) )
%to ( (m− ((m−1) /2) ) ) w i l l
c o r r e c t the edges that

173
 the mid image
correction
%f u n c t i o n can not reach
with i t s f o r loop .

f o r k=1: z %upper h o r i z o n t a l l i n e
f o r i =2:((m− ((m+1) /2) ) )
f o r j =2:((m− ((m−1) /2) ) )
e1 =[ img_noisy ( i , j − 1,k ) , img_noisy ( i , j +1,k ) ,
img_noisy ( i +1, j − 1,k ) , img_noisy ( i +1, j , k ) ,
img_noisy ( i +1, j +1,k ) ] ;
i f ( img_noisy ( i , j , k )>th+max( e1 ) | | img_noisy
( i , j , k )<th+min ( e1 ) )
pixel_map ( i , j , k ) =1;
img_noisy ( i , j , k )=median ( e1 ) ;

end
end
end
end

f o r k=1: z %lower h o r i z o n t a l l i n e
f o r i =2:(x −(m− ((m+1) /2) ) )
f o r j=y : ( y −(m− ((m−1) /2) ) )
e2 =[ img_noisy ( i , j − 1,k ) , img_noisy ( i , j +1,k ) ,
img_noisy ( i +1, j − 1,k ) , img_noisy ( i +1, j , k ) ,
img_noisy ( i +1, j +1,k ) ] ;
i f ( img_noisy ( i , j , k )>th+max( e2 ) | | img_noisy ( i , j
, k )<th+min ( e2 ) )
pixel_map ( i , j , k ) =1;
img_noisy ( i , j , k )=median ( e2 ) ;
else
end
end
end
end

f o r k=1: z %l e f t v e r t i c a l l i n e
f o r i =2:((m− ((m+1) /2) ) )
f o r j =2:((m− ((m+1) /2) ) )
e3 =[ img_noisy ( i − 1, j , k ) , img_noisy ( i +1, j , k ) ,
img_noisy ( i +1, j +1,k ) , img_noisy ( i , j +1,k ) ,
img_noisy ( i − 1, j +1,k ) ] ;
i f ( img_noisy ( i , j , k )>th+max( e3 ) | | img_noisy ( i , j
, k )<th+min ( e3 ) )
pixel_map ( i , j , k ) =1;
img_noisy ( i , j , k )=median ( e3 ) ;

174
 end
end
end
end

f o r k=1: z %r i g h t v e r t i c a l l i n e
f o r i=y : ( y −(m− ((m+1) /2) ) )
f o r j =2:(x −(m− ((m+1) /2) ) )
e4 =[ img_noisy ( i , j − 1,k ) , img_noisy ( i , j +1,k ) ,
img_noisy ( i +1, j − 1,k ) , img_noisy ( i +1, j , k ) ,
img_noisy ( i +1, j +1,k ) ] ;
i f ( img_noisy ( i , j , k )>th+max( e4 ) | | img_noisy ( i , j
, k )<th+min ( e4 ) )
pixel_map ( i , j , k ) =1;
img_noisy ( i , j , k )=median ( e4 ) ;

end
end
end
end

%C o r r e c t i n g mid image
from (m−(m−1) /2) : x −(m
−(m+1) /2) to
%(m−(m−1) /2) : y −(m−(m+1)/2
w i l l ensure that the
e n i t r e image has been
%c o r r e c t e d when f i r s t
doing the c o r e n e r s ,
then the edges and at
l a s t the
%mid image .
f o r k=1: z
f o r i =(m−(m−1) /2) : x −(m−(m+1) /2)
f o r j =(m−(m−1) /2) : y −(m−(m+1) /2)
val = 1; %counter f o r
the v a l u e s array
count = 1 ;
v a l u e s = z e r o s ( 1 ,m^2) ; %array to
s t o r e the n e i g b o r i n g p i x e l v a l u e s
array = z e r o s ( 1 ,m^1 −1) ;
f o r a=−(m− ((m+1) /2) ) : (m− ((m+1) /2) )
f o r b=−(m−(m+1) /2) : (m− ((m+1) /2) )
i f ( a==0 && b==0)
else
array ( count )=img_noisy ( i+a , j+b ,
k) ;

175
 end
v a l u e s ( v a l )=img_noisy ( i+a , j+b , k
);
v a l = v a l +1;
end
end
i f ( img_noisy ( i , j , k )>th+max( array ) | |
img_noisy ( i , j , k )<th+min ( array ) )
img_noisy ( i , j , k )=median ( v a l u e s ) ; %
r e p l a c i n g the d e f e c t p i x e l with
the median o f the v a l u e s array
pixel_map ( i , j , k ) =1; %
s t o r i n g the p o s i t i o n o f the d e f e c t
pixel
end
end
end
end

toc ; %stop time

imwrite ( img_noisy , ' median_res . jpg ' ) ; % w r i t e the
%r e s t o r e d image to
predetermined f i l e n a m e
%p l o t t i n g the o r i g i n a l ,
n o i s y and
r e c o n s t r u c t e d image
s t r=s p r i n t f ( ' Median f i l t e r e d image with windowsize %d ' , m) ;
s u b p l o t ( 2 , 2 , 1 : 2 ) , imshow ( I )
t i t l e ( ' O r i g i n a l image ' ) ;
s u b p l o t ( 2 , 2 , 3 ) , imshow ( n o i s e )
t i t l e ( ' Noisy image ' ) ;
s u b p l o t ( 2 , 2 , 4 ) , imshow ( img_noisy )
ti tl e ( str ) ;

%When the image has been

c o r r e c t e d i t i s time
to measure the mse ,
mae and
%psnr . This i s done by
l o o p i n g through the
e n t i r e image i n o r d e r
to
%c a l c u l a t e t h e s e v a l u e s .
J = img_noisy ;
max_val = max(max(max( img ) ) ) ;
[x,y, z ] = size ( I ) ;
mse = 0 ;
mae = 0 ;
f o r k=1: z

176
 f o r i =2:x−1
f o r j =2:y−1
mse = mse + ( img ( i , j , k )−J ( i , j , k ) ) ^2;
mae = mae + abs ( img ( i , j , k )−J ( i , j , k ) ) ;
end
end
end
mse = mse /(3 ∗ x ∗ y ) ;
mae = mae/(3 ∗ x ∗ y ) ;
psnr = 10 ∗ l o g 1 0 ( ( max_val^2) /mse ) ;
%d e f e c t s = sum(sum(sum( pixel_map ) ) ) ;

mse = 256 ∗ mse ;

mae = 256 ∗ mae ;
%d i s p l a y i n g the measured v a l u e s .
mse
mae
psnr
end

177
.5 C Code
.5.1 Test Compact ash
#i n c l u d e " s y s a c e _ s t d i o . h"
#i n c l u d e " xparameters . h"
#i n c l u d e " x u t i l . h"
#i n c l u d e " x i o . h"
#i n c l u d e " s t d i o . h"

i n t main ( void ) {

unsigned char b u f f e r [ 3 ] ;

char ∗ f i l e _ o u t = " output . t x t " ; // input and output f i l e s name , type the
char ∗ f i l e _ i n = " input . t x t " ; // d i r e c t o r y
i n t numread ;
char r e a d B u f f e r [ 2 ] ; // the v a r i a b l e that s t o r e d c h a r a c k t e r s read
from the c f card

SYSACE_FILE ∗ o u t f i l e ; // input f i l e handler

SYSACE_FILE ∗ i n f i l e ; // output f i l e handler

o u t f i l e = sysace_fopen ( f i l e _ o u t , "w" ) ; // open the p u t f i l e i n

w r i t e mode
i n f i l e = sysace_fopen ( f i l e _ i n , " r " ) ; // open the input f i l e i n
read mode

numread = s ys ace _f rea d ( r eadB uffe r , 1 , 1 9 , i n f i l e ) ; // r e a d i n g 19

c h a r a c t e r s from the input f i l e i n t o the r e a d B u f f e r

s y s a c e _ f w r i t e ( r eadB uffe r , 1 , 1 9 , o u t f i l e ) ; // w r i t i n g the c h a r a c t e r s

from the r e a d B u f f e r i n t o the f i l e on the c f card

sysace_fclose ( o u t f i l e ) ; // c l o s i n g the output f i l e

sysace_fclose ( i n f i l e ) ; // c l o s i n g the input f i l e

return 0;
}

178
.5.2 Test interrupt
#i n c l u d e " s y s a c e _ s t d i o . h"
#i n c l u d e " xparameters . h"
#i n c l u d e " x u t i l . h"
#i n c l u d e " x i o . h"
#i n c l u d e " s t d i o . h"
#i n c l u d e " my_custom_ip_register . h"
#i n c l u d e " x i n t c . h"
#i n c l u d e " mb_interface . h"

#d e f i n e SLV_REG0 0 x00000000
#d e f i n e SLV_REG1 0 x00000004
#d e f i n e SLV_REG2 0 x00000008
#d e f i n e SLV_REG3 0x0000000C
#d e f i n e SLV_REG4 0 x00000010
#d e f i n e BaseAddress 0xCCC00000
#d e f i n e read 0 x00000001
#d e f i n e reset 0 x00000000

void i n t r _ h a n d l e r ( ) {
char ∗ f i l e _ o u t = " o u t f i l e . t x t " ; // d e c l a r i n g the output f i l e name ,
type and d i r e c t o r y
char readValue ; // v a r i a b l e to s t o r e data
i n t numwrite ;
SYSACE_FILE ∗ o u t f i l e ; // output f i l e handler
unsigned char b u f f e r [4]= " t e s t " ; // data to be w r i t t e n to the f i l e

s t a t u s = MY_CUSTOM_IP_REGISTER_mReadReg(
XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR,
MY_CUSTOM_IP_REGISTER_INTR_IPISR_OFFSET) ; // read the s t a t u s o f
the i n t e r r u p t s e r v i c e r e g i s t e r
MY_CUSTOM_IP_REGISTER_mWriteReg(
XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR,
MY_CUSTOM_IP_REGISTER_INTR_IPISR_OFFSET, 0) ; // Acknowledge
i n t e r r u p t on p e r i p h e r a l
XIntc_mAckIntr (XPAR_XPS_INTC_0_BASEADDR,
XPAR_MY_CUSTOM_IP_REGISTER_0_IP2INTC_IRPT_MASK) ;
// Acknowledge i n t e r r u p t on i n t e r r u p t c o n t r o l l e r

o u t f i l e = sysace_fopen ( f i l e _ o u t , "w" ) ; // open f i l e i n

w r i t e mode
numwrite = s y s a c e _ f w r i t e ( b u f f e r , 1 , s i z e o f ( b u f f e r ) , o u t f i l e ) ; // w r i t e
the data i n b u f f e r to the f i l e
sysace_fclose ( o u t f i l e ) ; // c l o s e f i l e
}

179
void i n i t ( ) {
// R e g i s t e r i n g an I n t e r r u p t handler
XIntc_RegisterHandler (XPAR_XPS_INTC_0_BASEADDR,
XPAR_XPS_INTC_0_MY_CUSTOM_IP_REGISTER_0_IP2INTC_IRPT_INTR,
intr_handler , ( void ∗ )XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR) ;

// e n a b l i n g i n t e r r u p t s on the i n t e r r u p t c o n t r o l l e r , my_custom_ip
and m i c r o b l a z e
XIntc_mMasterEnable (XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR) ;
XIntc_mEnableIntr (XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR,
XPAR_MY_CUSTOM_IP_REGISTER_0_IP2INTC_IRPT_MASK) ;
MY_CUSTOM_IP_REGISTER_EnableInterrupt ( ( void ∗ )
XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR) ;
microblaze_enable_interrupts () ;

i n t main ( void ) {
init () ; // run the f u n c t i o n to s e t up the i n t e r r u p t s
intr_handler () ; // the f u n c t i o n run f o r every i n t e r r u p t

while (1) {

return 0;
}

180
.5.3 Test interrupt with read and write
#i n c l u d e " s y s a c e _ s t d i o . h"
#i n c l u d e " xparameters . h"
#i n c l u d e " x u t i l . h"
#i n c l u d e " x i o . h"
#i n c l u d e " s t d i o . h"
#i n c l u d e " my_custom_ip_register . h"
#i n c l u d e " x i n t c . h"
#i n c l u d e " mb_interface . h"

void i n t r _ h a n d l e r ( ) {

SYSACE_FILE ∗ o u t f i l e ;
char ∗ f i l e _ o u t = " o u t f i l e . t x t " ; // output f i l e name , type and
directory
Xuint32 readValue ; // v a r i a b l e to s t o r e data read from the
register
Xuint32 s t a t u s ; // s t a t u s o f the i n t e r r u p t r e g i s t e r
char t e s t [ 3 ] ; // v a r i a b l e used to s t o r e char r e p r e s e n t a t i o n
o f readValue
char data [ 3 0 ] ; // v a r i a b l e that i s w r i t t e n to the c f card

s t a t u s = MY_CUSTOM_IP_REGISTER_mReadReg(
XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR,
MY_CUSTOM_IP_REGISTER_INTR_IPISR_OFFSET) ; // read the s t a t u s
o f the i n t e r r u p t s e r v i c e r e g i s t e r
MY_CUSTOM_IP_REGISTER_mWriteReg(
XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR,
MY_CUSTOM_IP_REGISTER_INTR_IPISR_OFFSET, 0) ; //
Acknowledge i n t e r r u p t on p e r i p h e r a l
XIntc_mAckIntr (XPAR_XPS_INTC_0_BASEADDR,
XPAR_MY_CUSTOM_IP_REGISTER_0_IP2INTC_IRPT_MASK) ;
// Acknowledge i n t e r r u p t on i n t e r r u p t c o n t r o l l e r

o u t f i l e = sysace_fopen ( f i l e _ o u t , "w" ) ;
// open f i l e i n w r i t e mode
readValue = MY_CUSTOM_IP_REGISTER_mReadReg(
XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR,
MY_CUSTOM_IP_REGISTER_SLV_REG3_OFFSET) ; // read value from
register 3
t e s t [ 0 ] = readValue ;
// s t o r e s value i n the t e s t v a r i a b l e
s t r n c a t ( data , t e s t , 2 ) ; // s t o r e s
the t e s t value i n t o a char array
s y s a c e _ f w r i t e ( ( char ∗ ) data , 1 , s i z e o f ( data ) , o u t f i l e ) ;
// w r i t e s the value o f data to the c f card
sysace_fclose ( o u t f i l e ) ; // c l o s e
the f i l e

181
 }

int init ( i ){
// R e g i s t e r i n g an I n t e r r u p t handler
XIntc_RegisterHandler (XPAR_XPS_INTC_0_BASEADDR,
XPAR_XPS_INTC_0_MY_CUSTOM_IP_REGISTER_0_IP2INTC_IRPT_INTR,
intr_handler , ( void ∗ )XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR) ;

// e n a b l i n g i n t e r r u p t s on the i n t e r r u p t c o n t r o l l e r , my_custom_ip
and m i c r o b l a z e
XIntc_mMasterEnable (XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR) ;
XIntc_mEnableIntr (XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR,
XPAR_MY_CUSTOM_IP_REGISTER_0_IP2INTC_IRPT_MASK) ;
MY_CUSTOM_IP_REGISTER_EnableInterrupt ( ( void ∗ )
XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR) ;
microblaze_enable_interrupts () ;
i =0;
return i ;
}

i n t main ( void ) {
MY_CUSTOM_IP_REGISTER_mWriteReg(XPAR_MY_CUSTOM_IP_REGISTER_0_BASEADDR
,MY_CUSTOM_IP_REGISTER_SLV_REG3_OFFSET, 0 xA2) ; // w r i t i n g a t e s t
value to r e g i s t e r 3

init () ; // f u n c t i o n to s e t up the i n t e r r u p t s

intr_handler () ; // f u n c t i o n that i s invoked when t h e r e i s an

interrupt .

while (1) {
}

return 0;
}

182
.6 Images
.6.1 Original Images

Figure 1: Original noise free Lena image

183
Figure 2: Original noise free Canyon image

184
Figure 3: Original noise free Field image

185
.6.2 Lena Images from dierent noise levels

Figure 4: Lena image with noise level 0.001

Figure 5: Restored Lena image from noise level 0.001

186
 Figure 6: Lena image with noise level 0.002

Figure 7: Restored Lena image from noise level 0.002

187
 Figure 8: Lena image with noise level 0.004

Figure 9: Restored Lena image from noise level 0.004

188
 Figure 10: Lena image with noise level 0.006

Figure 11: Restored image from noise level 0.006

189
 Figure 12: Lena image with noise level 0.008

Figure 13: Restored Lena image from noise level 0.008

190
 Figure 14: Lena image with noise level 0.01

Figure 15: Restored Lena image from noise level 0.01

191
 Figure 16: Lena image with noise level 0.02

Figure 17: Restored Lena image from noise level 0.02

192
 Figure 18: Lena image with noise level 0.04

Figure 19: Restored Lena image from noise level 0.04

193
 Figure 20: Lena image with noise level 0.06

Figure 21: Restored Lena image from noise level 0.06

194
 Figure 22: Lena image with noise level 0.08

Figure 23: Restored Lena image from noise level 0.08

195
 Figure 24: Lena image with noise level 0.1

Figure 25: Restored Lena image from noise level 0.1

196
.6.3 Lena Images from dierent threshold levels

Figure 26: Lena image with noise level 0.02

Figure 27: Restored Lena image from threshold level 1

197
Figure 28: Restored Lena image from threshold level 4

Figure 29: Restored Lena image from threshold level 8

198
Figure 30: Restored Lena image from threshold level 12

Figure 31: Restored image from threshold level 16

199
Figure 32: Restored Lena image from threshold level 20

Figure 33: Restored Lena image from threshold level 22

200
Figure 34: Restored Lena image from threshold level 26

Figure 35: Restored Lena image from threshold level 30

201
Figure 36: Restored Lena image from threshold level 34

Figure 37: Restored Lena image from threshold level 38

202
Figure 38: Restored Lena image from threshold level 42

Figure 39: Restored Lena image from threshold level 46

203
Figure 40: Restored Lena image from threshold level 50

204
.6.4 Field Images from dierent noise levels

Figure 41: Field image with noise level 0.001

Figure 42: Restored Field image from noise level 0.001

205
 Figure 43: Field image with noise level 0.002

Figure 44: Restored Field image from noise level 0.002

206
 Figure 45: Field image with noise level 0.004

Figure 46: Restored Field image from noise level 0.004

207
 Figure 47: Field image with noise level 0.006

Figure 48: Restored Field image from noise level 0.006

208
 Figure 49: Field image with noise level 0.008

Figure 50: Restored Field image from noise level 0.008

209
 Figure 51: Field image with noise level 0.01

Figure 52: Restored Field image from noise level 0.01

210
 Figure 53: Field image with noise level 0.02

Figure 54: Restored Field image from noise level 0.02

211
 Figure 55: Field image with noise level 0.04

Figure 56: Restored Field image from noise level 0.04

212
 Figure 57: Field image with noise level 0.06

Figure 58: Restored Field image from noise level 0.06

213
 Figure 59: Field image with noise level 0.08

Figure 60: Restored Field image from noise level 0.08

214
 Figure 61: Field image with noise level 0.1

Figure 62: Restored Field image from noise level 0.1

215
.6.5 Field Images from dierent threshold levels

Figure 63: Field image with noise level 0.02

Figure 64: Restored Field image from threshold level 1

216
Figure 65: Restored Field image from threshold level 4

Figure 66: Restored Field image from threshold level 8

217
Figure 67: Restored Field image from threshold level 12

Figure 68: Restored Field image from threshold level 16

218
Figure 69: Restored Field image from threshold level 20

Figure 70: Restored Field image from threshold level 22

219
Figure 71: Restored Field image from threshold level 26

Figure 72: Restored Field image from threshold level 30

220
Figure 73: Restored Field image from threshold level 34

Figure 74: Restored Field image from threshold level 38

221
Figure 75: Restored Field image from threshold level 42

Figure 76: Restored Field image from threshold level 46

222
Figure 77: Restored Field image from threshold level 50

223
.6.6 Canyon Images from dierent noise levels

Figure 78: Canyon image with noise level 0.001

Figure 79: Restored Canyon image from noise level 0.001

224
 Figure 80: Canyon image with noise level 0.002

Figure 81: Restored Canyon image from noise level 0.002

225
 Figure 82: Canyon image with noise level 0.004

Figure 83: Restored Canyon image from noise level 0.004

226
 Figure 84: Canyon image with noise level 0.006

Figure 85: Restored Canyon image from noise level 0.006

227
 Figure 86: Canyon image with noise level 0.008

Figure 87: Restored Canyon image from noise level 0.008

228
 Figure 88: Canyon image with noise level 0.01

Figure 89: Restored Canyon image from noise level 0.01

229
 Figure 90: Canyon image with noise level 0.02

Figure 91: Restored Canyon image from noise level 0.02

230
 Figure 92: Canyon image with noise level 0.04

Figure 93: Restored Canyon image from noise level 0.04

231
 Figure 94: Canyon image with noise level 0.06

Figure 95: Restored Field image from noise level 0.06

232
 Figure 96: Canyon image with noise level 0.08

Figure 97: Restored Canyon image from noise level 0.08

233
 Figure 98: Canyon image with noise level 0.1

Figure 99: Restored Canyon image from noise level 0.1

234
.6.7 Canyon Images from dierent threshold levels

Figure 100: Canyon image with noise level 0.02

Figure 101: Restored Canyon image from threshold level 1

235
Figure 102: Restored Canyon image from threshold level 4

Figure 103: Restored Canyon image from threshold level 8

236
Figure 104: Restored Canyon image from threshold level 12

Figure 105: Restored Canyon image from threshold level 16

237
Figure 106: Restored Canyon image from threshold level 20

Figure 107: Restored Canyon image from threshold level 22

238
Figure 108: Restored Canyon image from threshold level 26

Figure 109: Restored Canyon image from threshold level 30

239
Figure 110: Restored Canyon image from threshold level 34

Figure 111: Restored Canyon image from threshold level 38

240
Figure 112: Restored Canyon image from threshold level 42

Figure 113: Restored Canyon image from threshold level 46

241
Figure 114: Restored Canyon image from threshold level 50

242
.6.8 Image from software simulation

Figure 115: Restored Lena image when using the software algorithm designed in the 2009 fall
project

243
Figure 116: Restored eld image when using the software algorithm designed in the 2009 fall
project

244
Figure 117: Restored canyon image when using the software algorithm designed in the 2009
fall project

245