EXP.

NO:1a NAME:BVS PRIYANKA

Realization of Boolean Expression without

AIM: To realize given Boolean expression with and without

m
er as
GIVEN BOOLEAN EXPRESSION:

co
eH w
o.
TRUTH TABLE OF BOOLEAN EXPRESSION:
rs e
ou urc
o
aC s
vi y re
ed d
ar stu
is
Th
sh

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 Implementation of circuit without simplification:

m
er as
co
eH w
o.
rs e
ou urc
OUTPUT OF STIMULATION:
o
aC s
vi y re
ed d
ar stu
is
Th
sh

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https://www.coursehero.com/file/111286930/DLD-lab-1pdf/
 VALIDATION OF A CONDITION FROM TRUTH TABLE:

m
er as
co
eH w
o.
rs e
ou urc
SIMPLIFICATION OF BOOLEAN EXPRESSION:
o
aC s
vi y re
ed d
ar stu
is
Th
sh

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https://www.coursehero.com/file/111286930/DLD-lab-1pdf/
 IMPLEMENTATION OF EXPRESSION BY SIMPLIFICATION:

m
er as
co
eH w
o.
OUTPUT OF STIMULATION: rs e
ou urc
o
aC s
vi y re
ed d
ar stu
is
Th
sh

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https://www.coursehero.com/file/111286930/DLD-lab-1pdf/
 INFERENCE:
For the input values of 1111 in truth table, we get 1 and for 1001 we
get 0,which is same in the stimulation results, for inputs 1111 we get
1 as output and for the input 1001 we get 0 as output. Hence, the
stimulation output is same in both the cases (with and without
simplification).
Hence The stimulation results of the given Boolean expression with
and without simplification matches each other. Hence, the Boolean
expression without and with simplification is realized with the help

m
er as
of LTSpice.

co
eH w
o.
rs e
ou urc
o
aC s
vi y re
ed d
ar stu
is
Th
sh

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 EXP.NO:1b NAME:BVS PRIYANKA
DATE:11-03-2021 REG.NO:20BDS0237
Realization of the following Boolean Expression using only NAND
GATE AND NOR GATE:
AIM:
To relize given Boolean expression using NAND and NOR gates by using
LTSPICE.

GIVEN BOOLEAN EXPRESSION:

m
er as
TRUTH TABLE:

co
eH w
o.
rs e
ou urc
o
aC s
vi y re
ed d

SIMPLIFICATION OF BOOLEAN EXPRESSION:

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https://www.coursehero.com/file/111286930/DLD-lab-1pdf/
 IMPLIMENTATION OF NAND GATE:

m
er as
OUTPUT OF STIMULATION:

co
eH w
o.
rs e
ou urc
o
aC s
vi y re
ed d
ar stu
is
Th

CONCLUSION:
sh

1. For the input values of A=0, B=0, C=0 in truth table we get 0 and for A=0,
B=1, C=0 we get 1.
2. As the same in stimulation results, for inputs 000 we get 0 as output and for
the input 010 we get 1 as output. Hence, our stimulation graph is correct

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 IMPLEMENTAION OF NOR GATE:

m
er as
co
eH w
OUTPUT OF STIMULATION:

o.
rs e
ou urc
o
aC s
vi y re
ed d
ar stu
is
Th
sh

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https://www.coursehero.com/file/111286930/DLD-lab-1pdf/
 CONCLUSION:
1. For the input values of A=0, B=0, C=0 in truth table we get 0 and
for A=0, B=1, C=0 we get 1.
2. As the same in stimulation results, for inputs 000 we get 0 as
output and for the input 010 we get 1 as output. Hence, our
stimulation graph is correct.

INFERENCE:
The stimulation results of the given Boolean expression has been implemented by universal
gates(NAND and NOR) by using LTSPICE.

m
er as
co
eH w
o.
rs e
ou urc
o
aC s
vi y re
ed d
ar stu
is
Th
sh

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https://www.coursehero.com/file/111286930/DLD-lab-1pdf/
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