DATA SHEET

MOS INTEGRATED CIRCUIT

µPD75208
4-BIT SINGLE-CHIP MICROCOMPUTER

DESCRIPTION
The µPD75208 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, a ROM, a RAM,
I/O ports, a fluorescent display tube controller/driver, a watch timer, a timer/pulse generator capable of outputting
14-bit PWM, a serial interface and a vectored interrupt function integrated on a single-chip.
It uses the VCR, ECR and CD fluorescent display tubes as display devices and is most suitable for applications
requiring the timer/watch function and high-speed interrupt servicing. It can help to provide the unit with many
functions and to decrease performance costs.
With the µPD75208, the µPD75P216A, 75P218 one-time PROM products are available for system development ★
evaluation or small production.
The following manual provides detailed description of the functions of the µPD75208. Be sure to read this manual
when you design an application system.
µPD75216A User’s Manual: IEM-988

FEATURES
• Architecture equal to that of an 8-bit microcomputer
• High-speed operation : Minimum instruction execution time : 0.95 µs (when operated at 4.19 MHz)
• Instruction execution time variable function realizing a wide range of operating voltages
• On-chip large-capacity program memory : 8K bytes
• Watch operation with an ultra low current consumption : 5µA TYP. (at the 3 V operation)
• On-chip programmable fluorescent display tube controller/driver
• Timer function : 4 ch
• 14-bit PWM output capability with the voltage synthesizer type electronic tuner
• Buzzer output capability
• Interrupt function with importance attached to applications
• For power-off detection
• For remote controlled reception
• Product with an on-chip PROM : µPD75P216A, µPD75P218 (on-chip EPROM : WQFN package) ★

ORDERING INFORMATION ★

Ordering Code Package Quality Grade

µ PD75208CW-××× 64-pin plastic shrink DIP (750 mil) Standard

µ PD75208GF-×××-3BE 64-pin plastic QFP (14 × 20 mm) Standard

Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

The information in this document is subject to change without notice.

Document No. IC-1884A

(O. D. No. IC-7048C) The mark ★ shows major revised points.
Date Published August 1993 P
Printed in Japan © NEC Corporation 1991
 µPD75208

★ LIST OF FUNCTIONS

Item Function

Instruction execution time • 0.95, 1.91, 15.3 µs (Main system clock : 4.19 MHz operation)
• 122 µs (Subsystem clock : 32.768 kHz operation)

On-chip memory ROM 8064 × 8 bits

RAM 497 × 4 bits

General register • 4-bit manipulation : 8 × 4 banks

• 8-bit manipulation : 4 × 4 banks

Input/output port 33 8 CMOS input pin


 FIP ® dual-function pin  20 CMOS input/output pins • Direct LED drive capability : 8
 included  • On-chip pull-down resistor by mask option capability : 4
 FIP dedicated pin 
 excluded 5 CMOS output pin • Direct LED drive capability : 4
• PWM/pulse output : 1
• On-chip pull-down resistor by mask option capability : 4

FIP controller/driver • No. of segments : 9 to 12 segments

• No. of digits : 9 to 16 digits
• Dimmer function : 8 levels
• On-chip pull-down resistor by mask option capability
• Key scan interrupt generation

Timer 4 channels • Timer/pulse generator : 14-bit PWM output enabled

• Watch timer : Buzzer output enabled
• Timer/event counter
• Basic interval timer : Watchdog timer application capability

Serial interface • MSB start/LSB start switchable

• Serial bus configuration capability

Vectored interrupt External : 3, Internal : 5

Test input External : 1, Internal : 1

System clock oscillator • Ceramic/crystal oscillator for main system clock oscillation : 4.194304 MHz standard
• Crystal oscillator for subsystem clock oscillation : 32.768 kHz standard

Standby function STOP/HALT mode

Mask option • Power-on reset, power-on flag

• High withstand voltage port : Pull-down resistor or open-drain output
• Port 6 : Pull-down resistor

Operating temperature range –40 to +85 °C

Operating voltage 2.7 to 6.0 V (standby data hold : 2.0 to 6.0 V)

Package • 64-pin plastic shrink DIP (750 mil)

• 64-pin plastic QFP (14 × 20 mm)

2
 µPD75208

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) ....................................................................................... 5

2. BLOCK DIAGRAM .................................................................................................................... 6

3. PIN FUNCTIONS ...................................................................................................................... 7

3.1 PORT PINS .................................................................................................................................... 7
3.2 NON-PORT PINS .......................................................................................................................... 8
3.3 PIN INPUT/OUTPUT CIRCUIT LIST ............................................................................................ 9
3.4 UNUSED PINS TREATMENT .................................................................................................... 10
3.5 P00/INT4 PIN AND RESET PIN OPERATING PRECAUTIONS ............................................... 11
3.6 XT1, XT2 AND P50 PIN OPERATING PRECAUTIONS ........................................................... 11

4. ARCHITECTURE AND MEMORY MAP OF THE µPD75208 ............................................... 12

5. PERIPHERAL HARDWARE FUNCTIONS .............................................................................. 14

5.1 PORTS .......................................................................................................................................... 14
5.2 CLOCK GENERATOR .................................................................................................................. 15
5.3 BASIC INTERVAL TIMER ........................................................................................................... 16
5.4 WATCH TIMER .......................................................................................................................... 17
5.5 TIMER/EVENT COUNTER ......................................................................................................... 18
5.6 TIMER/PULSE GENERATOR ..................................................................................................... 19
5.7 SERIAL INTERFACE ................................................................................................................... 20
5.8 FIP CONTROLLER/DRIVER ........................................................................................................ 22
5.9 POWER-ON FLAG (MASK OPTION) ......................................................................................... 23

6. INTERRUPT FUNCTIONS ...................................................................................................... 23

7. STANDBY FUNCTIONS ......................................................................................................... 25

8. RESET FUNCTIONS ............................................................................................................... 25

9. INSTRUCTION SET ................................................................................................................ 26

10. MASK OPTION SELECTION .................................................................................................. 35

11. APPLICATION BLOCK DIAGRAM ......................................................................................... 36

11.1 VCR TIMER TUNER .................................................................................................................... 36
11.2 COMPACT DISK PLAYER .......................................................................................................... 37
11.3 ECR ............................................................................................................................................... 37

3
 µPD75208

12. ELECTRICAL SPECIFICATIONS ............................................................................................ 38

13. CHARACTERISTIC CURVES .................................................................................................. 50

14. PACKAGE INFORMATION .................................................................................................... 54

15. RECOMMENDED SOLDERING CONDITIONS ..................................................................... 57

APPENDIX A DEVELOPMENT TOOLS .................................................................................... 58

APPENDIX B RELATED DOCUMENT ....................................................................................... 59

4
 µPD75208

1. PIN CONFIGURATION (TOP VIEW)

S3 1 64 VDD
S2 2 63 S4
S1 3 62 S5
S0 4 61 S6
P00/INT4 5 60 S7
P01/SCK 6 59 S8
P02/SO 7 58 S9
P03/SI 8 57 VPRE
P10/INT0 9 56 VLOAD
P11/INT1 10 55 T15/S10
P12/INT2 11 54 T14/S11
P13/TI0 12 53 T13/PH0

µ PD75208CW-× × ×
P20 13 52 T12/PH1
P21 14 51 T11/PH2
P22 15 50 T10/PH3
P23/BUZ 16 49 T9
P30 17 48 T8
P31 18 47 T7
P32 19 46 T6
P33 20 45 T5
P60 21 44 T4
P61 22 43 T3
P62 23 42 T2
P63 24 41 T1
P40 25 40 T0
P41 26 39 RESET
P42 27 38 P53
P43 28 37 P52
PPO 29 36 P51
X1 30 35 P50
X2 31 34 XT2
VSS 32 33 XT1
P12/INT2
P11/INT1
P10/INT0
P23/BUZ

P13/TI0

P02/SO
P03/SI
P40
P63
P62
P61
P60
P33
P32
P31
P30

P22
P21
P20

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P41 52 32 P01/SCK
P42 53 31 P00/INT4
P43 54 30 S0
PPO 55 29 S1
X1 56 28 S2
X2 57 27 S3
VSS 58
µ PD75208GF-× × ×-3BE 26 VDD
XT1 59 25 S4
XT2 60 24 S5
P50 61 23 S6
P51 62 22 S7
P52 63 21 S8
P53 64 20 S9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
RESET
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10/PH3
T11/PH2
T12/PH1
T13/PH0
T14/S11
T15/S10
VLOAD
VPRE

5
6

2. BLOCK DIAGRAM
PORT0 4 P00–P03
BASIC
INTERVAL
TIMER PORT1 4 P10–P13

PROGRAM CY SP(8)
INTBT ALU
COUNTER(13)
PORT2 4 P20–P23
TI0/P13 TIMER/EVENT
COUNTER
#0 BANK PORT3 4 P30–P33

INTT0
PORT4 4 P40–P43

TIMER/PULSE
GENERAL REG. PORT5 4 P50–P53
GENERATOR
PPO
ROM PORT6 4 P60–P63
INTTPG
PROGRAM
SI/P03 MEMORY DECODE RAM
SERIAL 8064 × 8 BITS AND DATA MEMORY
SO/P02
INTERFACE CONTROL 497 × 4 BITS
SCK/P01 10 T0–T9

INTSIO T10/PH3–
4 T13/PH0
INT0/P10 FIP
CONTROLLER/ T14/S11,T15/
INT1/P11 2
DRIVER S10
INT2/P12 INTERRUPT
CONTROL
10 S0–S9
INTW fX/2 N
INT4/P00
VPRE
SYSTEM CLOCK CPU CLOCK VLOAD
WATCH CLOCK GENERATOR STAND BY Φ
TIMER DIVIDER CONTROL
SUB MAIN INTKS

µPD75208
PORTH 4 PH0–PH3

BUZ/P23 XT1 XT2 X1 X2 VDD VSS RESET

 µPD75208

3. PIN FUNCTIONS

3.1 PORT PINS

Dual- 8-Bit Input / Output

Pin Name I/O Function Pin Function I/O After Reset Circuit Type *1

P00 Input INT4 4-bit input port (PORT0). × Input B

P01 Input/output SCK F

P02 Input/output SO G

P03 Input SI B
P10 Input INT0 Noise removing function available Input B
P11 INT1 Noise removing function available
P12 INT2 4-bit input port (PORT1).
P13 TI0

P20 Input/ ––– 4-bit input/output port (PORT2). × Input E

output
P21 –––
P22 –––

P23 BUZ

P30–P33 Input/ ––– Programmable 4-bit input/ output port (PORT3). Input E
output Input/output specifiable in 1-bit units.

P40 to P43 Input/ ––– 4-bit input/output port (PORT4). ● Input E

output LED direct drive capability.

P50 to P53 Input/ ––– 4-bit input/output port (PORT5). Input E

output LED direct drive capability.

P60 to P63 Input/ ––– Programmable 4-bit input/output port (PORT6). × Input V
output Input/output specifiable in 1-bit units.
On-chip pull-down resistor available (mask
option). Suitable for key input.

PH0 Output T13 4-bit P-ch open-drain, high-dielectric, high-current × Low level I
output port (PORTH). (with an on-
PH1 T12 chip pull-
LED direct drive capability. On-chip pull-down
PH2 T11 down resistor)
resistor available (mask option). or high
PH3 T10 impedance.

* Schmitt trigger inputs are circled.

7
 µPD75208

3.2 NON-PORT PINS

Dual- Input / Output

Pin Name I/O Function Pin Function After Reset Circuit Type *

T0 to T9 Output ––– FIP controller/ Digit output high-voltage high-current Low level I
driver output output. (with an on-
chip pull-
pins. down
T10 to T13 PH3 to PH0 Digit/segment output dual-function
Pull-down high-voltage high-current output. resistor ) or
resistor can be high
Extra pins can be used as PORTH.
impedance
incorporated in (without a
T14/S11, ––– Digit/segment output dual-function
bit units (mask pull-down
T15/S10 high-voltage high-current output.
option). resistor)
Static output also possible.

S9 Segment output high voltage output.

Static output also possible.

S0 to S8 Segment high-voltage output.

PPO Output ––– Timer/pulse generator pulse output. High D

impedance

TI0 Input P13 External event pulse input for timer/event counter. B

SCK Input/output P01 Serial clock input/output. Input F

SO Input/output P02 Serial data output pin or serial data input/output. Input G

SI Input P03 Serial data input or normal input. Input B

INT4 Input P00 Edge-detected vectored interrupt input (rising and falling B
edge detection).

INT0 Input P10 Edge-detected vectored interrupt input with noise B

eliminate function (detection edge selection possible).
INT1 P11

INT2 Input P12 Edge-detected testable input (rising edge detection). B

BUZ Input/output P23 Fixed frequency output (for buzzer or system clock Input E
trimming).

X1, X2 Input ––– Crystal/ceramic connect pin for main system clock
oscillation.
External clock input to X1 and its inverted clock input to
X2.

XT1 Input ––– Crystal connect pin for subsystem clock oscillation.
External clock input to XT1 and XT2 open.
XT2 –––

RESET Input System reset input (low level active). B

VPRE ––– FIP controller/driver output buffer power supply. I

VLOAD ––– FIP controller/driver pull-down resistor connect pin. I

VDD ––– Positive power supply.

VSS ––– GND potential.

* Schmitt trigger inputs are circled.

8
 µPD75208

3.3 PIN INPUT/OUTPUT CIRCUIT LIST

TYPE A TYPE F

VDD data
IN/OUT
Type D
output
P-ch disable
IN
Type B

N-ch

Input/Output Circuit Consisting of Type D Push-Pull Output

CMOS-Specified Input Buffer and Type B Schmitt Trigger Input

TYPE B TYPE G

VDD
P-ch output
disable P-ch
data IN/OUT

IN N-ch

Type B

Schmitt Trigger Input Having Hysteresis Characteristics

Input/Output Circuit Capable of Switching between Push-Pull
Output and N-ch Open-Drain Output (with P-ch OFF).
TYPE D
TYPE V
VDD

data data
P-ch IN/OUT
Type D
OUT output
disable

output N-ch
disable Type A
Pull-down
Resistor
Push-Pull Output which can be Set to Output High Impedance
(Mask Option)
(with Both P-ch and N-ch Set to OFF)

TYPE E TYPE I

data VDD VDD

IN/OUT
Type D
output data P-ch P-ch
disable OUT

Pull-down Resistor
N-ch
(Mask Option)
Type A VLOAD

VPRE
Input/Output Circuit Consisting of Type D Push-Pull Output
and Type A Input Buffer

9
 µPD75208

3.4 UNUSED PINS TREATMENT

Pin Recommended Connection

P00/INT4 Connect to VSS

P01/SCK Connect to VSS or VDD

P02/SO

P03/SI
P10/INT0 to P12/INT2 Connect to VSS

P13/TI0

P20 to P22 Input state : Connect to VSS or V DD

P23/BUZ Output state : Leave open

P30 to P33

P40 to P43
P50 to P53

P60 to P63

PPO Leave open

S0 to S9

T15/S10 to T14/S11

T0 to T9
T10/PH3 to T13/PH0

XT1 Connect to VSS or VDD

XT2 Leave open

RESET when there is an on- Connect to VDD

chip power-on reset circuit

VLOAD when there is no on- Connect to VSS or VDD

chip load resistor

10
 µPD75208

3.5 P00/INT4 PIN AND RESET PIN OPERATING PRECAUTIONS

P00/INT4 and RESET pins have the function (especially for IC test) to test uPD75208 internal operations in addition
to the functions described in sections 3.1 and 3.2.
The test mode is set when a voltage larger than VDD is applied to one of these pins. If noise larger than VDD is
applied in normal operation, the test mode may be set thereby adversely affecting normal operation.
Since there is a display output pin having a high-voltage amplitude (35 V) next to the P00/INT4 and RESET pins,
if cables for the related signals are routed in parallel, wiring noise larger than VDD may be applied to the P00/INT4
and RESET pins causing errors.
Thus, carry out wiring so that wiring noise can be minimized, If noise still cannot be suppressed, take the measure
against noise using the following external components.

• Connect diode with small VF (0.3 V or less) between • Connect a capacitor between the pins and VDD.
the pins and VDD

VDD VDD

VDD VDD

P00/INT4, RESET P00/INT4, RESET

3.6 XT1, XT2 AND P50 PIN OPERATING PRECAUTIONS

When selecting the 32.768 kHz subsystem clock connected to the XT1 and XT2 pins as the watch timer source
clock, the signal to be input or output to the P50 pin next to the XT2 pin must be a signal required to be switched
between high and low the minimum number of times (once/second or less).
If the P50 pin signal is switched frequently between high and low, a spike is generated in the XT2 pin because
of capacitance coupling of the P50 and XT2 pins and the correct watch functions cannot be achieved (the watch
becomes fast).
If it is necessary to allow the P50 pin signal to switch between high and low, mount an external capacitor to the
P50 pin as shown below.

µ PD75208

P50
XT1 XT2
0.0068 µ F

32.768 kHz

11
 µPD75208

4. ARCHITECTURE AND MEMORY MAP OF THE µPD75208

The µPD75208 has three architectural features:

• Bank configuration of data memory : Static RAM (448 words × 4 bits)
Display data memory (49 words × 4 bits)
Peripheral hardware (128 × 4 bits)
• Bank configuration of general registers: 8 × 4 banks (for operation in 4-bit units)
4 × 4 banks (for operation in 8-bit units)
• Memory mapped I/O

Fig. 4-1 and 4-2 show the memory maps for the µPD75208.

Fig. 4-1 Program Memory Map

Address
7 6 5 0
0000H MBE RBE 0 Internal Reset Start Address (High-Order 5 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
0002H MBE RBE 0 INTBT/INT4 Start Address (High-Order 5 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits) CALLF
0004H MBE RBE 0 INT0 Start Address (High-Order 5 Bits) ! faddr
Instruction
INT0 Start Address (Low-Order 8 Bits) Entry
0006H MBE RBE 0 INT1 Start Address (High-Order 5 Bits) Address

INT1 Start Address (Low-Order 8 Bits)

0008H MBE RBE 0 INTSIO Start Address (High-Order 5 Bits)
BRCB
INTSIO Start Address (Low-Order 8 Bits)
! caddr
000AH MBE RBE 0 INTT0 Start Address (High-Order 5 Bits) Instruction
Branch
INTT0 Start Address (Low-Order 8 Bits)
Address
000CH MBE RBE 0 NTTPG Start Address (High-Order 5 Bits) CALL ! addr
Instruction
INTTPG Start Address (Low-Order 8 Bits) Subroutine Entry
000EH MBE RBE 0 INTKS Start Address (High-Order 5 Bits) Address

INTKS Start Address (Low-Order 8 Bits)

BR ! addr
Instruction Branch
Address

0020H
GETI Instruction Reference Table BR $addr
007FH Instruction
0080H Relative Branch
Address
(–15 to –1,
07FFH +2 to +16) Branch Destination
0800H Address Specified
by GETI Instruction,
Subroutine Entry
Address
0FFFH
1000H
BRCB
! caddr Instruction
Branch Address
1F7FH

Remarks In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC
changed is enabled by BR PCDE and BR PCXA instructions.

12
 µPD75208

Fig. 4-2 Data Memory Map

General 000H
Register (32 × 4)
Area 01FH
020H
Stack Area Bank 0

256 × 4

General
Static RAM 0FFH
(497 × 4) 100H

241 × 4

Bank 1
1BFH
Display Data 1C0H
Memory, (49 × 4)
etc. 1FFH
Not Incorporated
F80H

Peripheral
Hardware 128 × 4 Bank 15
Area

FFFH

13
 µPD75208

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 PORTS
The µPD75208 has the following three types of I/O port:
• 8 CMOS input ports
• 20 CMOS I/O ports
• 4 P-ch open-drain high-voltage, large-current output ports

Total: 32 ports

Table 5-1 Functions of Ports

Port Name Function Operation and Feature Remarks

PORT0 4-bit input Always read or test possible irrespective of the dual-function Shares the pins with SI, SO, SCK
pin operating mode. and INT4.

PORT1 Always read or test possible, P10 and P11 are inputs with the Shares the pins with INT0 to 2
noise eliminate function. and TI0.

PORT2 4-bit Can be set to the input or output mode in 4-bit units. P23 shares the pin with BUZ.
PORT4 input/output Ports 4 and 5 can input/output data in pairs in 8-bit units.
PORT5 Ports 4 and 5 can directly drive LEDs.

PORT3 Can be set bit-wise to the input or output mode. Port 6 can
PORT6 incorporate a pull-down resistor as a mask option.

PORTH 4-bit output P-ch open-drain high-voltage, high-current output port. Can Shares the pins with T10 to T13.
drive an FIP and LED directly. Can incorporate a pull-down
resistor bit-wise as a mask option.

14
 µPD75208

5.2 CLOCK GENERATOR

Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control
register (SCC).
The main system clock or subsystem clock can be selected.
The instruction execution time is variable.
• 0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz)
• 122 µs (subsystem clock: 32.768 kHz)

Fig. 5-1 Clock Generator Block Diagram

XT1 • FIP Controller
• Basic Interval Timer (BT)
Subsystem fXT • Timer/Event Counter
Clock Watch Timer • Serial Interface
XT2 Generator • Watch Timer
Timer/Pulse • INT0 Noise Eliminator
X1 Generator
1/8 to 1/4096
Main System Selector fXX
Clock Frequency Divider
X2 Generator fX

1/2 1/6
SCC Oscillation
Stop
Frequency
SCC3
Divider

Selector
SCC0 1/4 Φ

PCC • CPU
• INT0 Noise Eliminator
• INT1 Noise Eliminator
PCC0
Internal Bus

PCC1
4
HALT F/F
PCC2
HALT* S

PCC3
STOP*
R Q

PCC2 and
PCC3
Clear STOP F/F Wait Release Signal from BT
Q S
RES Signal (Internal Reset)
* Instruction execution
R
Standby Release Signal from
Remarks 1. fX = Main system clock frequency Interrupt Control Circuit
2. fXT = Subsystem clock frequency
3. fXX = System clock frequency
4. Φ = CPU clock
5. PCC: Processor clock control register
6. SCC: System clock control register
7. 1 clock cycle (tCY) of Φ is 1 machine cycle of an instruction. For tCY, see ”AC Characteristics“ in
12. ELECTRICAL SPECIFICATIONS. ★

15
 µPD75208

5.3 BASIC INTERVAL TIMER

The basic interval timer has the following functions:
• Interval timer operation to generate reference time
• Watchdog timer application to detect inadvertent program loop
• Wait time select and count upon standby mode release
• Count contents read

Fig. 5-2 Basic Interval Timer Configuration

From Clock
Generator

5
Clear Clear
fXX/2

7
fXX/2
Basic Interval Timer Set BT Interrupt
MPX (8-Bit Frequency Divider) Request Flag
fXX/2
9 Vectored
Interrupt
Request
12 BT IRQBT Signal
fXX/2

Wait Release
Signal during
BTM3 BTM2 BTM1 BTM0 BTM Standby Release

SET1* 4 8

Internal Bus

* Instruction execution

16
 µPD75208

5.4 WATCH TIMER

The µPD75208 incorporates one channel of watch timer. The watch timer has the following functions:
• Sets the test flag (IRQW) at 0.5 sec intervals.
The standby mode can be released by IRQW.
• 0.5 second interval can be set with the main system clock and subsystem clock.
• The fast mode enables to set 128-time (3.91 ms) interval useful to program debugging and inspection.
• The fixed frequencies (2.048 kHz) can be output to the P23/BUZ pin for use to generate buzzer sound
and trim the system clock oscillator frequency.
• Since the frequency divider can be cleared, the watch can be started from zero second.

Fig. 5-3 Watch Timer Block Diagram

fW
7 (256 Hz : 3.91 ms)
2

INTW
fXX
fW Selector IRQW
128 14 Set Signal
From (32.768 kHz) fW 2
Clock Selector Frequency Divider
(32.768 kHz)
Generator 2Hz
fXT
0.5 sec
(32.768 kHz)
fW
(2.048 kHz) Clear
16 Output Buffer

P23/BUZ

WM PORT2.3 Bit 2 of PMGB

P23 Port 2
WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0 Output Input/Output
Latch Mode

Internal Bus

Remarks Values at fXX = 4.194304 MHz and fXT = 32.768 kHz are indicated in parentheses.

17
 µPD75208

5.5 TIMER/EVENT COUNTER

The µPD75208 incorporates one channel of timer/event counter. The timer/event counter has the following
functions:
• Program interval timer operation
• Event counter operation
• Count state read function

Fig. 5-4 Timer/Event Counter Block Diagram

Internal Bus

SET1 * 8
8 8
TM0 TMOD0

TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0 Modulo Register (8)

8
Match
Comparator (8) INTT0
IRQT0
Input Buffer 8 Set Signal
T0
P13/TI0 Count Register (8)
 MPX CP
From Clock 
Generator  Clear


(Refer to Fig. 5-1) Timer Operation Start

IRQT0
Clear

* Instruction execution

18
 µPD75208

5.6 TIMER/PULSE GENERATOR

The µPD75208 incorporates one channel of timer/pulse generator which can be used as a timer or a pulse
generator. The timer/pulse generator has the following functions:

(a) Functions available in the timer mode

• 8-bit interval timer operation (IRQTPG generation) enabling the clock source to be varied at 5 levels
• Square wave output to PPO pin

(b) Functions available in the PWM pulse generate mode

• 14-bit accuracy PWM pulse output to the PPO pin (Used as a digital-to-analog converter and applicable
to tuning)
215
• Fixed time interval ( = 7.81 ms : at 4.19 MHz operation) interrupt generation
fXX

If pulse output is not necessary, the PPO pin can be used as a 1-bit output port.

Note If the STOP mode is set while the timer/pulse generator is in operation, erroneous operation may result.
To prevent that from occurring, preset the timer/pulse generator to the stop state using its mode
register.

Fig. 5-5 Block Diagram of Timer/Pulse Generator (Timer Mode)

Internal Bus

8 8
MODL MODH

Modulo Register L (8) Modulo Register H (8)

TPGM3
(Set to "1")

INTTPG
Modulo Latch H (8) IRQTPG
Set Signal

8
Match Output Buffer

Comparator (8) T F/F Selector

PPO
Frequency Set
8
Divider CP
fX 1/2
Prescalar Select Latch (5) Count Register (8) TPGM4 TPGM5 TPGM7
TPGM1
Clear Clear

19
 µPD75208

Fig. 5-6 Timer/Pulse Generator Block Diagram (PWM Pulse Generate Mode)

Internal Bus

8 8
MODH MODL

Modulo Register H (8) Modulo Register L (6) (2)

TPGM3

MODH (8) MODL7-2 (6)

Modulo Latch (14)
Output Buffer
TPGM1
PWM Pulse Generator Selector PPO
fx 1/2

Frequency Divider

INTTPG
TPGM5 TPGM7
(IRQTPG Set Signal)
215
( = 7.81 ms : at 4.19 MHz operation)
fX

5.7 SERIAL INTERFACE

The serial interface has the following functions:
• Clock synchronous 8-bit send/receive operation (simultaneous send/receive)
• Clock synchronous 8-bit serial bus operation (data input/output from the SO pin. N-ch open-drain SO output)
• Start LSB/MSB switching

These functions facilitate data communication with another microcomputer of µPD7500 series or 78K series via
a serial bus and coupling with peripheral devices.

20
 Fig 5-7 Serial Interface Block Diagram

Internal Bus

8
8 8 SET1 *2
P03/SI
SIO0 SIO7 SIOM
Selector SIO
Shift Register (8) SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0

*1
SO Output
P02/SO
Latch

INTSIO
Overflow
Serial Clock IRQSIO
Counter (3) Set Signal

IRQSIO
Clear Clear Signal
Serial Start
P01/SCK

Q S Φ
4
fxx/2
MPX
10
fxx/2

* 1. CMOS output and N-ch open-drain output switchable output buffer.

2. Instruction execution

µPD75208
21
 µPD75208

5.8 FIP CONTROLLER/DRIVER

The on-chip FIP controller/driver has the following functions:
• Generates the segment and digit signals by automatically reading the display data memory executing DMA
operation.
• Can select up to a total of 26 display devices in the range of 9 to 12 segments and 9 to 16 digits.
• Can apply the remaining display output as static output.
• Can adjust the brightness at 8 levels using the dimmer function.
• Can apply key scan operations.
• Generates interrupt at the key scan timing (IRQKS)
• Can generate key scan data output from the segment output pin.
• Owns the high-voltage output pin (40 V) which can directly drive the FIP.
• Segment special pins (S0 to S9) : VOD = 40 V, IOD = 3 mA
• Digit output pins (T0 to T15) : VOD = 40 V, IOD = 15 mA
• Can incorporate pull-down resistors bit-wise as mask options.

Fig. 5-8 FIP Controller/Driver Block Diagram

Internal Bus

4 4 4 Key Scan
Flag (KSF)
Display Digit Dimmer
Mode Select Select
Display Data Memory Register Register Register
(48 × 4 Bits)

Key Scan Registers

Port H
(KS0 and KS1)

12

Segment Data Latch (12) Digit Signal Generator IRQKS

Generation
Signal

2 2 4 4
10

Selector

2 4 10

Hige-Voltage Output Buffer

10 2 4 10

S0-S9 T15/S10 and T13/PH0- T0-T9 VLOAD VPRE

T14/S11 T10/PH3

Note The FIP controller/driver can only operate in the high and intermediate-speeds (PCC = 0011B or 0010B) of
the main system clock (SCC.0 = 0). It may cause errors with any other clock or in the standby mode. Thus,
be sure to stop FIP controller operation (DSPM.3 = 0) and then shift the unit to any other clock mode or
the standby mode.

22
 µPD75208

5.9 POWER-ON FLAG (MASK OPTION)

The power-on flag (PONF) is automatically set (1) when the power-on reset circuit is activated and the power-
on reset signal is generated. (See Fig. 8-1 Reset Signal Generator)
The PONF is mapped at bit 0 of address FD1H in the data memory space and can be tested by the memory bit
manipulation instructions (SKT, SKF, SKTCLR) or cleared (CLR1).

Note The PONF cannot be set by SET1 instruction.

6. INTERRUPT FUNCTIONS

The µPD75208 has eight types of interrupt sources and can generate multiple interrupts with priority order.
It is also equipped with two types of test sources. INT2 is an edge detected testable input.
The µPD75208 interrupt control circuit has the following functions:
• Hardware-controller vectored interrupt function which can control interrupt acknowledge with the interrupt
enable flag (IE×××) and the interrupt master enable flag (IME).
• Function of setting any interrupt start address.
• Multiple interrupt function which can specify priority order with the interrupt priority select register (IPS).
• Interrupt request flag (IRQ×××) test function. (Interrupt generation can be checked by software.)
• Standby mode release function. (Interrupt to be released by interrupt enable flag can be selected.)

23
24

Fig. 6-1 Interrupt Control Circuit Block Diagram

Internal Bus

2 2 4 2
(IME) IPS IST
IM1 IM0
Interrupt Enable Flag (IE XXX )

Decoder
INT
BT IRQBT

INT4 Both Edges

Detection IRQ4 VRQn
/P00 Circuit
INT0 Edge
* Detection IRQ0
/P10 Circuit
INT1 Edge
* Detection IRQ1 Vector
/P11 Circuit Table
Priority Control
Address
INTSIO IRQSIO Circuit
Generator
Circuit
INTT0 IRQT0

INTTPG IRQTPG

INTKS IRQKS

INTW IRQW Standby Release

Signal
INT2 Rising Edge
Detection IRQ2
/P12 Circuit

* Noise Eliminator

µPD75208
 µPD75208

7. STANDBY FUNCTIONS

Two standby modes (STOP mode and HALT mode) are available for the µPD75208 to decrease power consump-
tion in the program standby mode.

Table 7-1 Operation Status in Standby Mode

STOP Mode HALT Mode

Set instruction STOP instruction HALT instruction

System clock when set Setting enabled only with main system Setting enabled with either main system
clock. clock or subsystem clock.

Clock oscillator Oscillator stops only with main system Stops only with CPU clock Φ (Oscillation
clock. continued).

Basic interval timer Operation stopped. Operation (IRQBT set at reference time
intervals).

Serial interface Operation enabled only when external Operation enabled when serial clock other
Operating State

SCK input is selected for serial clock. than Φ is specified.

Timer/event counter Operation enabled only when TI0 pin Operation enabled.
input is specified for count clock.

Timer/pulse generator Operation stopped. Operation enabled.

Watch timer Operation enabled only fXT is selected for Operation enabled.
count clock.

FIP controller/driver Operation disabled (display off mode set before disabling).

CPU Operation stopped.

Release signal Interrupt request signal (except INT0, INT1, INT2) or RESET input enabled by
interrupt enable flag.

8. RESET FUNCTIONS

The reset signal (RES) generator has a configuration shown in Fig. 8-1.

Fig. 8-1 Reset Signal Generator

RESET
Internal Reset Signal
(RES)

Mask
Option SWB

Bit
Power-On Manipulation
Internal Bus

Reset SWA
Instruction
Generator Execution
Power-On Flag
(PONF)

The power-on reset generator is a circuit to generate a one-shot pulse upon detection of the start-up of the power
voltage. This pulse is used in three ways according to SWA, SWB mask option specification shown in Fig. 8-1. (See
10. MASK OPTION SELECTION.)

25
 µPD75208

9. INSTRUCTION SET

(1) Operand identifier and description

Enter an operand in the operand column of each instruction using the description method relating to the
operand identifier of the instruction (refer to RA75X Assembler Package User's Manual, Language (EEU-730)
for details). If more than one description method is available, select one. Capital alphabetic letters, plus and
minus signs are keywords. Describe them as they are.
In the case of immediate data, describe appropriate numerical values or labels.

Identifier Description Method

reg X, A, B, C, D, E, H, L
reg1 X, B, C, D, E, H, L

rp XA, BC, DE, HL

rp1 BC, DE, HL
rp2 BC, DE
rp’ XA, BC, DE, HL, XA’, BC’, DE’, HL’
rp’1 BC, DE, HL, XA’, BC’, DE’, HL’

rpa HL, HL+, HL-, DE, DL

rpa1 DE, DL

n4 4-bit immediate data or label

n8 8-bit immediate data or label

mem 8-bit immediate data or label*

bit 2-bit immediate data or label

fmem FB0H to FBFH and FF0H to FFFH immediate data or labels

pmem FC0H to FFFH immediate data or labels

addr 0000H to 1F7FH immediate data or labels

caddr 12-bit immediate data or label
faddr 11-bit immediate data or label

taddr 20H to 7FH immediate data (bit0 = 0) or label

PORTn PORT0 to PORT6

IE××× IEBT, IESIO, IET0, IETPG, IE0, IE1, IEKS, IEW, IE4
RBn RB0 to RB3
MBn MB0, MB1, MB15

* For 8-bit data processing, only even addresses can be specified.

26
 µPD75208

(2) Legend for operation description

A : A register; 4-bit accumulator

B : B register
C : C register
D : D register
E : E register
H : H register
L : L register
X : X register
XA : Register pair (XA); 8-bit accumulator
BC : Register pair (BC)
DE : Register pair (DE)
HL : Register pair (HL)
XA’ : Expanded register pair (XA’)
BC’ : Expanded register pair (BC’)
DE’ : Expanded register pair (DE’)
HL’ : Expanded register pair (HL’)
PC : Program counter
SP : Stack pointer
CY : Carry flag; Bit accumulator
PSW : Program status word
MBE : Memory bank enable flag
RBE : Register bank enable flag
PORTn : Port n (n = 0 to 6)
IME : Interrupt master enable flag
IPS : Interrupt priority select register
IE××× : Interrupt enable flag
RBS : Register bank select register
MBS : Memory bank select register
PCC : Processor clock control register
• : Address and bit delimiter
(××) : Contents addressed by ××
××H : Hexadecimal data

27
 µPD75208

(3) Description of symbols in the addressing area column

*1 MB = MBE • MBS
(MBS = 0, 1, 15)

*2 MB = 0

*3 MBE = 0 : MB = 0 (00H to 7FH)

MB = 15 (80H to FFH)
Data Memory
MBE = 1 : MB = MBS (MBS = 0, 1, 15)
Addressing
*4 MB = 15, fmem = FB0H to FBFH,
FF0H to FFFH

*5 MB = 15, pmem = FC0H to FFFH

*6 addr = 0000H to 1F7FH

*7 addr = (Current PC) – 15 to (Current PC) – 1,

(Current PC) + 2 to (Current PC) + 16
Program Memory
*8 caddr = 0000H to 0FFFH (PC12 = 0) or
Addressing
1000H to 1F7FH (PC12 = 1)

*9 faddr = 0000H to 07FFH

*10 taddr = 0020H to 007FH

Remarks 1. MB indicates accessible memory bank.

2. In *2, MB = 0 irrespective of MBE and MBS.
3. In *4 and *5, MB = 15 irrespective of MBE and MBS.
4. *6 to *10 indicate addressable areas.

(4) Description of the machine cycle column

S indicates the number of machine cycles required for skip operation by an instruction having skip function.
The S value varies as follows:

• When not skipped ................................................................................................... S = 0

• When 1-byte or 2-byte instructions are skipped ................................................. S = 1
• When 3-byte instructions are skipped (BR !addr, CALL !addr instruction) ..... S = 2

Note GETI instruction is skipped in one machine cycle.

One machine cycle is equal to one cycle(=tCY) of CPU clock Φ and three time periods are available according
to PCC setting.

28
 µPD75208

No. of Machine Addressing Skip

Note 1 Mnemonic Operands Operation
Bytes Cycle Area Condition

MOV A, #n4 1 1 A←n4 Stack A

reg1, #n4 2 2 reg1←n4

XA, #n8 2 2 XA←n8 Stack A

HL, #n8 2 2 HL←n8 Stack B

rp2, #n8 2 2 rp2←n8

A, @HL 1 1 A←(HL) *1

A, @HL+ 1 2+S A←(HL), then L←L+1 *1 L=0

A, @HL– 1 2+S A←(HL), then L←L–1 *1 L = FH

A, @rpa1 1 1 A←(rpa1) *2

XA, @HL 2 2 XA←(HL) *1

@HL, A 1 1 (HL)←A *1

@HL, XA 2 2 (HL)←XA *1

A, mem 2 2 A←(mem) *3

XA, mem 2 2 XA←(mem) *3

Transfer

mem, A 2 2 (mem)←A *3

mem, XA 2 2 (mem)←XA *3

A, reg 2 2 A←reg

XA, rp' 2 2 XA←rp'

reg1, A 2 2 reg1←A

rp'1, XA 2 2 rp'1←XA

XCH A, @HL 1 1 A↔(HL) *1

A, @HL+ 1 2+S A↔(HL), then L←L+1 *1 L=0

A, @HL– 1 2+S A↔(HL), then L←L–1 *1 L = FH

A, @rpa1 1 1 A↔(rpa1) *2

XA, @HL 2 2 XA↔(HL) *1

A, mem 2 2 A↔(mem) *3

XA, mem 2 2 XA↔(mem) *3

A, reg1 1 1 A↔reg1

XA, rp' 2 2 XA↔rp'

MOVT XA, @PCDE 1 3 XA←(PC12–8+DE)ROM

Note 2
XA, @PCXA 1 3 XA←(PC12–8+XA)ROM

Note 1. Instruction Group

2. Table reference

29
 µPD75208

No. of Machine Addressing Skip

Note Mnemonic Operand Operation
Bytes Cycle Area Condition

MOV1 CY, fmem.bit 2 2 CY←(fmem.bit) *4

CY, pmem.@L 2 2 CY←(pmem 7–2+L3–2.bit(L 1–0)) *5

Bit transfer

CY, @H+mem.bit 2 2 CY←(H+mem3–0.bit) *1

fmem.bit, CY 2 2 (fmem.bit)←CY *4

pmem.@L, CY 2 2 (pmem7–2+L3–2.bit(L1–0))←CY *5

@H+mem.bit, CY 2 2 (H+mem3–0.bit)←CY *1

ADDS A, #n4 1 1+S A←A+n4 carry

XA, #n8 2 2+S XA←XA+n8 carry

A, @HL 1 1+S A←A+(HL) *1 carry

XA, rp' 2 2+S XA←XA+rp' carry

rp'1, XA 2 2+S rp'1←rp'1+XA carry

ADDC A, @HL 1 1 A, CY←A+(HL)+CY *1

XA, rp' 2 2 XA, CY←XA+rp'+CY

rp'1, XA 2 2 rp'1, CY←rp'1+XA+CY

SUBS A, @HL 1 1+S A←A–(HL) *1 borrow

XA, rp' 2 2+S XA←XA–rp' borrow

rp'1, XA 2 2+S rp'1←rp'1–XA borrow

Operation

SUBC A, @HL 1 1 A, CY←A–(HL)–CY *1

XA, rp' 2 2 XA, CY←XA–rp'–CY

rp'1, XA 2 2 rp'1, CY←rp'1–XA–CY

AND A, #n4 2 2 A←A n4

A, @HL 1 1 A←A (HL) *1

XA, rp' 2 2 XA←XA rp'

rp'1, XA 2 2 rp'1←rp'1 XA

OR A, #n4 2 2 A←A n4

A, @HL 1 1 A←A (HL) *1

XA, rp' 2 2 XA←XA rp'

rp'1, XA 2 2 rp'1←rp'1 XA

XOR A, #n4 2 2 A←A n4

A, @HL 1 1 A←A (HL) *1

XA, rp' 2 2 XA←XA rp'

rp'1, XA 2 2 rp'1←rp'1 XA

Note Instruction Group

30
 µPD75208

No. of Machine Addressing Skip

Note 1 Mnemonic Operands Operation
Bytes Cycle Area Condition

CY←A0, A3←CY, An–1←An

Note 2

RORC A 1 1

NOT A 2 2 A←A

INCS reg 1 1+S reg←reg+1 reg = 0

Increment/decrement

rp1 1 1+S rp1←rp1+1 rp1 = 00H

@HL 2 2+S (HL)←(HL)+1 *1 (HL) = 0

mem 2 2+S (mem)←(mem)+1 *3 (mem) = 0

DECS reg 1 1+S reg←reg–1 reg = FH

rp' 2 2+S rp'←rp'–1 rp = FFH

SKE reg, #n4 2 2+S Skip if reg = n4 reg = n4

@HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4

Compare

A, @HL 1 1+S Skip if A = (HL) *1 A = (HL)

XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL)

A, reg 2 2+S Skip if A = reg A = reg

XA, rp' 2 2+S Skip if XA = rp' XA = rp'

SET1 CY 1 1 CY←1
manipulation
Carry flag

CLR1 CY 1 1 CY←0

SKT CY 1 1+S Skip if CY = 1 CY = 1

NOT1 CY 1 1 CY←CY

Note 1. Instruction Group

2. Accumulator manipulation

31
 µPD75208

No. of Machine Addressing Skip

Note Mnemonic Operands Operation
Bytes Cycle Area Condition
SET1 mem.bit 2 2 (mem.bit)←1 *3

fmem.bit 2 2 (fmem.bit)←1 *4

pmem.@L 2 2 (pmem7–2+L3–2.bit(L 1–0))←1 *5

@H + mem.bit 2 2 (H+mem3–0.bit)←1 *1

CLR1 mem.bit 2 2 (mem.bit)←0 *3

fmem.bit 2 2 (fmem.bit)←0 *4

pmem.@L 2 2 (pmem7–2+L3–2.bit(L 1–0))←0 *5

@H+mem.bit 2 2 (H+mem3–0.bit)←0 *1

SKT mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1

fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1

pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 1 *5 (pmem.@L) = 1

Memory bit manipulation

@H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 1 *1 (@H+mem.bit) = 1

SKF mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0

fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0

pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 0 *5 (pmem.@L) = 0

@H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 0 *1 (@H+mem.bit) = 0

SKTCLR fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1

pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear *5 (pmem.@L) = 1

@H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=1 and clear *1 (@H+mem.bit)=1

AND1 CY, fmem.bit 2 2 CY←CY (fmem.bit) *4

CY, pmem.@L 2 2 CY←CY (pmem7–2+L3–2.bit(L1–0)) *5

CY, @H+mem.bit 2 2 CY←CY (H+mem3–0.bit) *1

OR1 CY, fmem.bit 2 2 CY←CY (fmem.bit) *4

CY, pmem.@L 2 2 CY←CY (pmem7–2+L3–2.bit(L 1–0)) *5

CY, @H+mem.bit 2 2 CY←CY (H+mem3–0.bit) *1

XOR1 CY, fmem.bit 2 2 CY←CY (fmem.bit) *4

CY, pmem.@L 2 2 CY←CY (pmem7–2+L3–2.bit(L 1–0)) *5

CY, @H+mem.bit 2 2 CY←CY (H+mem3–0.bit) *1

BR addr — — PC 12–0←addr *6
(Optimum instruction is
selected from among BR !addr,
BRCB !caddr and BR $addr by an
assembler.)
Branch

!addr 3 3 PC12–0←addr *6

$addr 1 2 PC12–0←addr *7
BRCB !caddr 2 2 PC12–0←PC12+caddr11–0 *8

BR PCDE 2 3 PC12–0←PC12–8+DE

PCXA 2 3 PC12–0←PC12–8+XA

Note Instruction Group

32
 µPD75208

No. of Machine Addressing Skip

Note Mnemonic Operands Operation
Bytes Cycle Area Condition

CALL !addr 3 3 (SP–4) (SP–1) (SP–2)←PC11–0 *6

(SP–3)← MBE, RBE, 0, PC12
PC12–0←addr, SP←SP–4

CALLF !faddr 2 2 (SP–4) (SP–1) (SP–2)←PC11–0 *9

(SP–3)← MBE, RBE, 0, PC12
PC12–0←00, faddr, SP←SP–4

RET 1 3 MBE, RBE, 0, PC12←(SP+1)

PC11–0←(SP) (SP+3) (SP+2)
SP←SP+4
Subroutine stack control

RETS 1 3+S MBE, RBE, 0, PC12←(SP+1) Unconditional

PC11–0←(SP) (SP+3) (SP+2)
SP←SP+4
then skip unconditionally

RETI 1 3 ×, ×, ×, PC12←(SP+1)
PC11–0←(SP) (SP+3) (SP+2)
PSW←(SP+4) (SP+5), SP←SP+6

PUSH rp 1 1 (SP–1) (SP–2)←rp, SP←SP–2

BS 2 2 (SP–1)←MBS, (SP–2)←RBS, SP←SP–2

POP rp 1 1 rp←(SP+1) (SP), SP←SP+2

BS 2 2 MBS←(SP+1), RBS←(SP), SP←SP+2

EI 2 2 IME(IPS.3)←1
Interrupt
control

IE××× 2 2 IE×××←1

DI 2 2 IME(IPS.3)←0

IE××× 2 2 IE×××←0

IN * A, PORTn 2 2 A←PORTn (n = 0 to 6)
Input/output

XA, PORTn 2 2 XA←PORTn+1, PORTn (n = 4)

OUT * PORTn, A 2 2 PORTn←A (n = 2 to 6)

PORTn, XA 2 2 PORTn+1, PORTn←XA (n = 4)

Special CPU control

HALT 2 2 Set HALT Mode (PCC.2←1)

STOP 2 2 Set STOP Mode (PCC.3←1)

NOP 1 1 No Operation

SEL RBn 2 2 RBS←n (n = 0 to 3)

MBn 2 2 MBS←n (n = 0, 1, 15)

* MBE = 0 or MBE = 1 and MBS = 15 must be set for execution of IN/OUT instruction

Note Instruction Group

33
 µPD75208

No. of Machine Addressing Skip

Note Mnemonic Operands Operation
Bytes Cycle Area Condition

GETI * taddr 1 3 • TBR instruction *10

PC12–0←(taddr)4–0+(taddr+1)
---------------------------------------------------- ------------------------
• TCALL instruction
(SP–4)(SP–1)(SP–2)←PC11–0
(SP–3)← MBE, RBE, 0, PC12
Special

PC12–0←(taddr)4–0+(taddr+1)
SP←SP–4
---------------------------------------------------- ------------------------
• (taddr) (taddr+1) instruction Depends on
executed in the case of instructions
instruction other than TBR and referred to.
TCALL instructions

* TBR and TCALL instructions are assembled pseudo-instructions to define the GETI instruction table.

Note Instruction Group

34
 µPD75208

10. MASK OPTION SELECTION

The µPD75208 has the following mask options enabling or disabling on-chip components.

(1) Pin

Pin Mask Option

P60 to P63 Pull-up resistor incorporation enabled bit-wise

T0/T9

T10/PH3 to T13/PH0

T14/S11, T15/S10

S0 to S9

XT1, XT2 Deletion of subsystem clock oscillator feedback resistor

possible

Note 1. In a system not using subsystem clocks, power consumption in the STOP mode can be decreased by
removing the feedback resistor from the oscillator.
2. The feedback resistor must be incorporated when the subsystem clock is used.

(2) Power-on reset generator, power-on flag (PONF)

One of the following three can be selected.

Switch Selection
(See Fig. 8-1) Power-On Reset Generator Power-On Flag (PONF) Internal Reset Signal (RES)

SWA SWB

ON ON Incorporated Incorporated Generate automatically

ON OFF Incorporated Incorporated Not generate automatically

OFF OFF Not incorporated Not incorporated –––––

35
 µPD75208

11. APPLICATION BLOCK DIAGRAM

11.1 VCR TIMER TUNER

Main Power Supply

+
Super Capacitor

Power VDD VSS

Failure INT4 T0–T15 16
Detection

LPF PPO Fluorescent Display Panel (FIP)

Electronic S0–S11 12
µPD75208 12 Segments × 16 Digits
Tuner
 Timer 
 Tuner 
 Remote 
 
Tape Count Pulse INT1  Controlled 
 Reception 
Tape Up/Down  Tape Counter 
PORT6 Key Matrix
(12 × 4)
SCK SCK
System Controller
SO SO
Microcomputer SI

µ PD75104/75106 INT0 Remote Controlled

EEPROM™ Signal
µ PC2800A

µ PD6252 BUZ
BZ Piezoelectric Buzzer
X1 X2 XT1 XT2

36
 µPD75208

11.2 COMPACT DISK PLAYER

T0–T15 16
Servo SIO SCK
Control IC SI/SO

Fluorescent Display Panel (FIP)

S0–S11 12
12 Segments × 16 Digits

Loading
Circuit µPD75208

PORT6 Key Matrix

(12 × 4)
BUZ
BZ
INT0 Remote Controlled
Signal
µ PC2800A
X1 X2

11.3 ECR

Main Power Supply

+

Power VDD VSS

Failure INT4 T0–T15 16
Detection

Fluorescent Display Panel (FIP)

S0–S9 10
10 Segments × 16 Digits
RAM

µPD75208

Key Matrix
(10 × 4)
Printer

PPO
BZ Piezoelectric Buzzer
X1 X2 XT1 XT2

37
 µPD75208

12. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)

PARAMETER SYMBOL TEST CONDITIONS RATING UNIT

VDD –0.3 to +7.0 V

Power supply voltage VLOAD VDD –40 to VDD +0.3 V

VPRE VDD –12 to VDD +0.3 V

Input voltage VI –0.3 to VDD +0.3 V

VO Pins except display output pins –0.3 to VDD +0.3 V

Output voltage
VOD Display output pins VDD –40 to VDD +0.3 V

1 pins except display output pins –15 mA

S0 to S9 1 pin –15 mA

Output current high IOH T0 to T15 1 pin –30 mA

Total of pins except display output pins –20 mA

Total of display output pins –120 mA

1 pin 17 mA
Output current low IOL
Total of pins 60 mA

Plastic QFP 450 mW

Total loss*1 PT
Plastic shrink DIP 600 mW

Operating temperature Topt –40 to +85 °C

Storage temperature Tstg –65 to +150 °C

POWER SUPPLY VOLTAGE RANGE (Ta = –40 to +85 °C)

PARAMETER TEST CONDITIONS MIN. MAX. UNIT

CPU *2 *3 6.0 V

Display controller 4.5 6.0 V

Time/pulse generator 4.5 6.0 V

Other hardware *2 2.7 6.0 V

38
 µPD75208

* 1. Calculation of total loss

Design so that the sum of the following three power consumption values for the µPD75208CW/GF will be less
than the total loss PT (It is recommended to use the system with 80 % or less of the rating).
➀ CPU loss : Given as VDD (MAX.) × IDD1 (MAX.)
➁ Output pin loss : There are normal output pin loss and display output pin loss. It is necessary
to add a loss derived from the flow of maximum current to each output pin.
➂ Pull-down register loss : Power loss due to a pull-down resistor incorporated in the display output pin
by mask option.

Example Suppose 4-LED output with 9SEG × 11DIGIT, V DD = 5 V + 10 % and 4.19 MHz oscillation and let a maximum
of 3 mA, 15 mA and 10 mA flow to the segment pin, timing pin and LED output pin, respectively.
Further, let the voltage of fluorescent display tube (VLOAD voltage) be –30 V and normal voltage be small.
➀ CPU loss : 5.5 V × 9.0 mA = 49.5 mW
➁ Pin loss : Segment pin ..... 2 V × 3 mA × 9 = 54 mW
Timing pin ......... 2 V × 15 mA = 30 mW

10
LED output ........ ×2V × 10 mA × 4 = 53 mW
15

➂ Pull-down resistor loss ........ (30 + 5.5 V)2 × 10 = 315 mW

40 kΩ
PT = ➀ + ➁ + ➂ = 501.5 mW

In this example, the power consumption of 501.5 mW is less than the allowable total loss for the shrink
DIP package (600 mW). However, since the allowable total loss is 450 mW for the QFP package, it is
necessary to decrease power consumption by decreasing the number of on-chip pull-down resistors. In
this example, power consumption can be adjusted to 344 mW by incorporating pull-down resistors in
only 11 digit outputs and 4 segment outputs and externally mounting pull-down resistors to the 5
remaining segment outputs.

2. Except the system clock oscillator, display controller and timer/pulse generator.
3. The operating voltage range varies depending on the cycle time. Refer to the section describing AC
characteristics.

39
 µPD75208

MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)

RESONATOR RECOMMENDED CIRCUIT PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT

Oscillator frequency VDD = Oscillation

2.0 5.0*4 MHz
(fXX) *2 voltage range
X1 X2
Ceramic
resonator*1 After VDD reaches the
Oscillation minimum value in
C1 C2 stabilization time *3 the oscillation
4 ms
voltage range

Oscillator frequency
2.0 4.19 5.0 *4 MHz
(fXX) *2
X1 X2
Crystal
resonator*1 VDD = 4.5 to 6.0 V 10 ms
Oscillation stabilization
C1 C2
time *3
30 ms

X1 input frequency
2.0 5.0*4 MHz
X1 X2 (fX) *2
External
clock
X1 input high and low
100 250 ns
µ PD74HCU04 level widths (tXH, tXL )

* 1. Resonators are shown in the following page.

2. Oscillator characteristics only. Refer to the description of AC characteristics for details of instruction execution
time.
3. Time required for oscillation to become stabilized after VDD application or STOP mode release.
★ 4. When oscillator frequency is " 4.19 < fX ≤ 5.0 MHz ", do not select " PCC = 0011 " as instruction execution time.
If " PCC = 0011 " is selected, 1 machine cycle becomes less than 0.95 µs, with the result that the specified MIN.
value of 0.95 µs cannot be observed.

SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)

RESONATOR RECOMMENDED CIRCUIT PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT

Oscillator frequency
32 32.768 35 kHz
XT1 XT2 (fXT) *2
Crystal
resonator*1 330 kΩ VDD = 4.5 to 6.0 V 1.0 2 s
Oscillation stabilization
C3 C4 time *3
10 s

XT1 input frequency

32 100 kHz
XT1 XT2 (fXT)
External
clock Leave Open
XT1 input high and low
10 32 µs
level widths (tXTH, tXTL)

* 1. Recommended resonators are shown in the following page.

2. Oscillator characteristics only. Refer to the description of AC characteristics for instruction execution time.
3. Oscillation stabilization time is a time required for oscillation to become stabilized after VDD application or
STOP mode release.

40
 µPD75208

CAPACITANCE (Ta = 25 °C, VDD = 0 V)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Input capacitance CIN 15 pF

Except display output f = 1 MHz 15 pF

Output capacitance COUT Unmeasured pin returned
Display output to 0V 35 pF

Input /output capacitance CIO 15 pF

RECOMMENDED OSCILLATOR CONSTANTS

MAIN SYSTEM CLOCK : CERAMIC RESONATOR (Ta = –40 to +85 °C)

EXTERNAL OSCILLATION
MANUFACTURER PRODUCT NAME CAPACITANCE (pF) VOLTAGE RANGE (V)
C1 C2 MIN. MAX.
Murata Mfg. Co., Ltd. CSA 4.19MG 30 30 4.0 6.0
Kyocera Corp. KBR–2.09MS 68 68
KBR–3.58MS 4.0 6.0
KBR–4.19MS 33 33
KBR–4.9M

MAIN SYSTEM CLOCK : CRYSTAL RESONATOR (Ta = –40 to +85 °C)

EXTERNAL OSCILLATION
FREQUENCY CAPACITANCE (pF) VOLTAGE RANGE (V)
MANUFACTURER HOLDER
(MHz) C1 C2 MIN. MAX.
Kinseki 4.19 HC–49/U 15 15 2.7 6.0

Note Carry out fine adjustment of crystal resonator frequency with external capacitance C1 of 10 to 33 pF.

41
 µPD75208

DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

VIH1 Except below 0.7V DD VDD V

VIH2 Ports 0, 1, RESET 0.75VDD VDD V

Input voltage high VIH3 X1, X2, XT1 V DD–0.4 VDD V

VDD = 4.5 to 6.0 V 0.65VDD VDD V

VIH4 Port 6
0.7V DD VDD V

VIL1 Except below 0 0.3VDD V

Input Voltage low VIL2 Ports 0, 1, 6, RESET 0 0.2VDD V

VIL3 X1, X2, XT1 0 0.4 V

VDD = 4.5 to 6.0V, IOH = –1 mA V DD–1.0 V

Output voltage high VOH All output pins
IOH = –100 µA V DD–0.5 V

Ports 4, 5 VDD = 4.5 to 6.0V, IOL = 15 mA 0.4 2.0 V

Output voltage low VOL VDD = 4.5 to 6.0V, IOL = 1.6 mA 0.4 V
All output pins
IOL = 400 µA 0.5 V

Input leakage current ILIH1 Except X1,X2,XT1 3 µA

VIN = VDD
high ILIH2 X1, X2, XT1 µA
20

Input leakage current ILIL1 Except X1,X2,XT1 –3 µA

VIN = 0 V
low ILIL2 X1, X2, XT1 µA
–20

Output leakage current high ILOH All output pins VOUT = VDD 3 µA

Output leakage current ILOL1 Except display output VOUT = 0 V –3 µA

low
ILOL2 Display output VOUT = VLOAD = VDD – 35 V –10 µA
VPRE = VDD – 9 ±1 V*1 –3 –5.5 mA
S0 to S9 VDD =
4.5 to 6.0 V VPRE = 0 V –1.5 –3.5 mA
Display output current IOD
VOD =
VPRE = VDD – 9 ±1 V*1 –15 –22 mA
T0 to T15 VDD – 2 V
VPRE = 0 V –7 –15 mA

VDD = 4.5 to 6.0 V 30 80 200 kΩ

Port 6
Built-in pull-down RP6
VIN = VDD 30 1000 kΩ
resistor (mask option)
RL Display output VOD – VLOAD = 35 V 40 70 120 kΩ

VDD = 5 V ±10 %*3 3.0 9.0 mA

IDD1 4.19 MHz
crystal VDD = 3 V ±10 %*4 0.55 1.5 mA
oscillation
C1 = C2 = VDD = 5 V ±10 % 600 1800 µA
IDD2 HALT mode
15pF
VDD = 3 V ±10 % 200 600 µA
Supply current*2
IDD3 32 kHz crystal VDD = 3 V ±10 % 40 120 µA
oscillation*5 HALT mode VDD = 3 V ±10 %
IDD4 5 15 µA

XT1 = 0 V VDD = 5 V ±10 % 0.5 20 µA

IDD5
STOP mode VDD = 3 V ±10 % 0.1 10 µA

42
 µPD75208

* 1. The following external circuit is recommended.

µ PD75208
+5 V
VDD

RD9. 1EL

VPRE RD9. 1EL : Zener Diode (NEC)

Zener Voltage = 8.29 to 9.30 V
68 kΩ

VLOAD
–30 V
VSS

2. Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included.
3. When the processor clock control register (PCC) is set to 0011 and is operated in the high-speed mode.
4. When the PCC register is set to 0000 and is operated in the low-speed mode.
5. When the system clock control register (SCC) is set to 1001 and is operated with the subsystem clock with
main system clock oscillation stopped.

POWER-ON RESET CIRCUIT CHARACTERISTICS (MASK OPTION) (Ta = -40 to +85 °C)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Power-on reset
VDDH 4.5 6.0 V
operating voltage high

Power-on reset
VDDL 0 0.2 V
operating voltage low

Power supply voltage

tr 10 *1 µs
rise time

Power supply voltage

toff 1 s
off time

Power-on reset circuit*2 VDD = 5 V ±10 % 10 100 µA

IDDPR
current consumption VDD = 2.7 V 2 20 µA

* 1. 2 17/fXX (31.3 ms at fXX = 4.19 MHz)

2. Current with on-chip power-on reset circuit or power-on flag.

VDDH
VDD

VDDL

toff tr

Remarks Start the power supply smoothly.

43
 µPD75208

AC CHARACTERISTICS (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Operation with main VDD = 4.5 to 6.0 V 0.95 32 µs

CPU clock cycle time system clock
(minimum instruction 3.8 32 µs
tCY
execution time = 1
machine cycle) *1 Operation with sub-
system clock 114 122 125 µs

VDD = 4.5 to 6.0 V 0 0.6 MHz

TI0 input frequency fTI
0 165 kHz

tTIH, VDD = 4.5 to 6.0 V 0.83 µs

TI0 input high and low-
level widths tTIL 3 µs

Input 0.8 µs
VDD = 4.5 to 6.0 V
Output 0.95 µs
SCK cycle time tKCY
Input 3.2 µs

Output 3.8 µs

Input 0.4 µs
VDD = 4.5 to 6.0 V
tKH, Output tKCY/2–50 ns
SCK high and low-level
widths tKL Input 1.6 µs

Output t KCY/2–150 ns

SI setup time (to SCK↑) tSIK 100 ns

SI hold time (from SCK↑) tKSI 400 ns

SO output delay time VDD = 4.5 to 6.0 V 300 ns

tKSO
from SCK↓
1000 ns

INT0 *2 µs
Interrupt input high and tINTH,
INT1 2tCY µs
low-level widths
tINTL
INT2, 4 10 µs

RESET low-level width tRSL 10 µs

44
 µPD75208

* 1. CPU clock (Φ) cycle time is determined by the tCY VS VDD

oscillator frequency of the connected resonator, (Main System Clock in Operation)
40
the system clock control register (SCC) and the
32
processor clock control register (PCC). The cycle 30
time tCY characteristics for power supply voltage
VDD when the main system clock is in operation is 6
shown below. 5
Operation Guaranteed
2. 2tCY or 128/fXX is set by interrupt mode register Range
4

Cycle Time tCY [µ s]

(IM0) setting.
3

0.5
0 1 2 3 4 5 6

Power Supply Voltage VDD [V]

45
 µPD75208

AC Timing Measurement Values (Except X1 and XT1 Inputs)

0.75VDD 0.75VDD
Test Points
0.2VDD 0.2VDD

Clock Timing

1/fX

tXL tXH

X1 Input V DD - 0.4 V
0.4 V

1/fXT

tXTL tXTH

XT1 Input
VDD - 0.4 V
0.4 V

TI0 Timing

1/fTI

tTIL tTIH

TI0

46
 µPD75208

Serial Transfer Timing

tKCY

tKL tKH

SCK

tSIK tKSI

SI Input Data

tKSO

SO Output Data

Interrupt Input Timing

tINTL tINTH

INT0,1,2,4

RESET Input Timing

tRSL

RESET

47
 µPD75208

DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40
to +85 °C)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Data retention power

VDDDR 2.0 6.0 V
supply voltage

Data retention power

IDDDR VDDDR = 2.0V 0.1 10 µA
supply current *1

Release signal set time tSREL 0 µs

Release by RESET 217/fX ms

Oscillation stabilization tWAIT
wait time *2 Release by interrupt request *3 ms

* 1. Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included.
2. Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation
start.
3. According to the setting of the basic interval timer mode register (BTM) (see below).

BTM3 BTM2 BTM1 BTM0 Wait Time (Values at fXX = 4.19 MHz in parentheses)

— 0 0 0 220/fX (approx. 250 ms)

— 0 1 1 217/fX (approx. 31.3 ms)

— 1 0 1 215/fX (approx. 7.82 ms)

— 1 1 1 213/fX (approx. 1.95 ms)

Data Retention Timing (STOP Mode Release by RESET)

Internal Reset Operation

HALT Mode

STOP Mode Operating Mode

Data Retention Mode

VDD
VDDDR tSREL

STOP Instruction Execution

RESET

tWAIT

48
 µPD75208

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

HALT Mode

STOP Mode Operating Mode

Data Retention Mode

VDD
VDDDR tSREL

STOP Instruction Execution

Standby Release Signal

(Interrupt Request)
tWAIT

49
 µPD75208

13. CHARACTERISTIC CURVES

IDD vs VDD (Ta = 25 °C)

5000
High-Speed
Mode (0011)
Medium-Speed
Mode (0010)

Low-Speed
Mode (0000)

1000 HALT Mode

(0100)

500
Supply Current IDD [ µ A]

Subsystem
Clock
Operating
Mode
100

Subsystem
50 Clock HALT
Mode

STOP Mode
(1000)
 Power-on 
10  reset 
 
 circuit and 
 power-on flag
 incorporated 
5

X1 X2 XT1 XT2

330 kΩ
4.19 MHz 32.768 kHz
15 pF 15 pF 22 pF 33 pF

1
0 1 2 3 4 5 6
Supply Voltage VDD [V]

Remarks Values of the processor clock control register (PCC) is indicated in parenthesis.

50
 µPD75208

IOL vs VOL (Ports 0, 2, 3, 6)

(Ta = 25 °C)
20

VDD = 5 V
VDD = 6 V VDD = 4 V

15
Output Current Low IOL [mA]

VDD = 3 V

10

VDD = 2.7 V

0
0 1 2 3 4 5

Output Voltage Low VOL [V]

IOH vs (VDD - VOH) (Ports 0, 2, 3, 6)

(Ta = 25 °C)
–20

VDD = 5 V
–15
VDD = 6 V VDD = 4 V
Output Current High IOH [mA]

–10
VDD = 3 V

–5
VDD = 2.7 V

0
0 1 2 3 4 5
VDD - VOH [V]

51
 µPD75208

IOL vs VOL (Ports 4, 5)

(Ta = 25 °C)
20

VDD = 5 V
6V 4V VDD = 3 V

15
Output Current Low IOL [mA]

VDD = 2.7 V

10

0
0 1 2 3 4 5
Output Voltage Low VOL [V]

IOH vs (VDD - VOH) (Ports 4, 5)

(Ta = 25 °C)
–20

VDD = 6 V
–15

VDD = 5 V
Output Current High IOH (mA)

VDD = 4 V

–10

VDD = 3 V
–5

VDD = 2.7 V

0
0 1 2 3 4 5
VDD - VOH [V]
52
 µPD75208

IOD vs (VDD - VOD) (T0 to T15)

(Ta = 25 °C)
–40.0

VDD – VPRE = 8 V
–30.0
VDD – VPRE = 10 V VDD – VPRE = 6 V
Display Output Current IOD [mA]

–20.0

VDD – VPRE = 4 V

–10.0

0
0 1 2 3 4 5
VDD - VOD [V]

IOD vs (VDD - VOD) (S0 to S9)

(Ta = 25 °C)
–10.0
VDD – VPRE = 10 V VDD – VPRE = 8 V
Display Output Current IOD [mA]

VDD – VPRE = 6 V

–5.0

VDD – VPRE = 4 V

0
0 1 2 3 4 5
VDD - VOD [V]

53
 µPD75208

14. PACKAGE INFORMATION

64 PIN PLASTIC SHRINK DIP (750 mil)

64 33

1 32
A
K

L
I
J

F
G

M R
D N M C B

NOTE ITEM MILLIMETERS INCHES

1) Each lead centerline is located within 0.17 mm (0.007 inch) of A 58.68 MAX. 2.311 MAX.
its true position (T.P.) at maximum material condition. B 1.78 MAX. 0.070 MAX.
2) Item "K" to center of leads when formed parallel. C 1.778 (T.P.) 0.070 (T.P.)

D 0.50±0.10 0.020 +0.004

–0.005
F 0.9 MIN. 0.035 MIN.
G 3.2±0.3 0.126±0.012
H 0.51 MIN. 0.020 MIN.
I 4.31 MAX. 0.170 MAX.
J 5.08 MAX. 0.200 MAX.
K 19.05 (T.P.) 0.750 (T.P.)
L 17.0 0.669

M 0.25 +0.10
–0.05 0.010 +0.004
–0.003
N 0.17 0.007
R 0~15° 0~15°
P64C-70-750A,C-1

54
 µPD75208

64 PIN PLASTIC QFP (14×20)

A
B

51 33 detail of lead end

52 32

S
C D
Q R

64 20
1 19
F

G H I M J

K
P M

N L

NOTE ITEM MILLIMETERS INCHES

Each lead centerline is located within 0.20 mm (0.008 inch) of A 23.6±0.4 0.929±0.016
its true position (T.P.) at maximum material condition.
B 20.0±0.2 0.795 +0.008
–0.009

C 14.0±0.2 0.551+0.009
–0.008
D 17.6±0.4 0.693±0.016
F 1.0 0.039
G 1.0 0.039

H 0.40±0.10 0.016 +0.004

–0.005
I 0.20 0.008
J 1.0 (T.P.) 0.039 (T.P)
K 1.8±0.2 0.071 +0.008
–0.009

L 0.8±0.2 0.031 +0.009

–0.008

M 0.15 +0.10
–0.05 0.006 +0.004
–0.003
N 0.10 0.004
P 2.7 0.106
Q 0.1±0.1 0.004±0.004
R 5°±5° 5°±5°
S 3.0 MAX. 0.119 MAX.
P64GF-100-3B8,3BE,3BR-2

55
 µPD75208

64-pin ceramic QFP for ES (reference) (unit : mm)

14.2

12.0

64 52
1 51

18.0

20

19 33
20 32

1.0 0.4 0.15

2.25

Note 1. Care is needed since the metal cap is con-

nected to pin 26 and set to the positive
power supply level.
2. Care is needed since the lead of the base is
formed obliquely.
3. The lead length is not stipulated since the
Bottom
cutting of the lead ends is not progress-
View
controlled.

56
 µPD75208

15. RECOMMENDED SOLDERING CONDITIONS ★

This product should be soldered and mounted under the conditions recommended below.
For details of recommended soldering conditions for the surface mounting type, refer to the document
“Semiconductor Device Mount Technology” (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our salesman.

Table 15-1 Surface Mounting Type Conditions

µPD75208GF-×××-3BE : 64-pin plastic QFP (body 14 × 20 mm)

Recommended
Soldering Method Soldiering Conditions
Condition Symbol

Wave soldering Solder bath temperature: 260 °C or less, Duration: 10 sec. max. WS60-107-1
Number of times: Once, Time limit: 7 days* (thereafter 10 hours prebaking required
at 125 °C)
Preheating temperature : 120 °C max. (package surface temperature)

Infrared reflow Package peak temperature: 230 °C, Duration: 30 sec. max. (at 210 °C or above), IR30-107-1
Number of times: Once, Time limit: 7 days*(thereafter 10 hours prebaking required
at 125 °C)

VPS Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above), VP15-107-1
Number of times: Once, Time limit: 7 days* (thereafter 10 hours prebaking required
at 125 °C)

Pin part heating Pin part temperature: 300 °C or below , Duration: 3 sec. max. (per device side) –––

* For the storage period after dry-pack decompression storage conditions are max. 25 °C, 65 % RH.

Note Use of more than one soldering method should be avoided (except in the case of pin part heating).

Table 15-2 Insertion Type Soldering Conditions

µPD75208CW-××× : 64-pin plastic shrink DIP (750 mil)

Soldering Method Soldering Conditions

Wave soldering
Solder bath temperature: 260 °C or below , Duration: 10 sec. max.
(lead part only)

Pin part heating Pin part temperature: 260 °C or below , Duration: 10 sec. max.

Note Ensure that the application of wave soldering is limited to the lead part and no solder touches the main
unit directly.

57
 µPD75208

★ APPENDIX A DEVELOPMENT TOOLS

The following development tools are provided for developing systems including the µPD75208:

IE-75000-R *1 In-circuit emulator for the 75X series

IE-75001-R

IE-75000-R-EM *2 Emulation board for the IE-75000-R and IE-75001-R

EP-75216ACW-R Emulation probe for the µPD75216ACW

Emulation probe for the µPD75216AGF. A 64-pin conversion socket, the EV-9200G-64, is attached
Hardware

EP-75216AGF-R
EV-9200G-64 to the probe.

PG-1500 PROM programmer

PA-75P216ACW PROM programmer adapter for the µPD75P216ACW and µPD75P218CW. Connected to the
PG-1500.

PA-75P218GF PROM programmer adapter for the µPD75P218GF. Connected to the PG-1500.

PA-75P218KB PROM programmer adapter for the µPD75P218KB. Connected to the PG-1500.

IE control program Host machine

• PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A *3)
Software

PG-1500 controller
• IBM PC series (PC DOSTM Ver. 3.1)
RA75X relocatable
assembler

* 1. Maintenance service only

2. Not contained in the IE-75001-R
3. These software cannot use the task swap function, which is available in MS-DOS Ver. 5.00 and Ver. 5.00A.

58
 µPD75208

APPENDIX B RELATED DOCUMENTS ★

Documents related to the device

Document Name Document No.

User’s manual IEU-1294

Application note IEM-1294

75X series selection guide IF-1027

Documents related to development tools

Document Name Document No.

IE-75000-R User’s Manual EEU-1297

IE-75001-R User’s Manual EEU-1416

Hardware

IE-75000-R-EM User’s Manual EEU-1294

EP-75216ACW-R User’s Manual EEU-1321

EP-75216AGF-R User’s Manual EEU-1309

PG-1500 User’s Manual EEU-1335

RA75X Assembler Package Operation PC-9800 series EEU-1346

User’s Manual (MS-DOS) base
Software

IBM PC series
(PC DOS) base

Language EEU-1363

PG-1500 Controller User’s Manual EEU-1291

Other documents

Document Name Document No.

PACKAGE MANUAL IEI-1213

SMD SURFACE MOUNT TECHNOLOGY MANUAL IEI-1207

QUALITY GRADES ON NEC SEMICONDUCTOR DEVICES IEI-1209

NEC SEMICONDUCTOR DEVICE RELIABILITY/QUALITY CONTROL SYSTEM IEI-1203

ELECTROSTATIC DISCHARGE (ESD) TEST IEI-1201

GUIDE TO QUALITY ASSURANCE FOR SEMICONDUCTOR DEVICES MEI-1202

Note The above documents may be revised without notice. Use the latest versions when you design an
application system.

59
 µPD75208

Cautions on CMOS Devices

1 Countermeasures against static electricity for all MOSs

Caution When handling MOS devices, take care so that they are not electrostatically charged.
Strong static electricity may cause dielectric breakdown in gates. When transporting or
storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal
cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during
assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins.
Also handle boards on which MOS devices are mounted in the same way.

2 CMOS-specific handling of unused input pins

Caution Hold CMOS devices at a fixed input level.
Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an
intermediate-level input may be caused by noise. This allows current to flow in the CMOS
device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input
level. Since unused pins may function as output pins at unexpected times, each unused
pin should be separately connected to the VDD or GND pin through a resistor.
If handling of unused pins is documented, follow the instructions in the document.

3 Statuses of all MOS devices at initialization

Caution The initial status of a MOS device is unpredictable when power is turned on.
Since characteristics of a MOS device are determined by the amount of ions implanted
in molecules, the initial status cannot be determined in the manufacture process. NEC
has no responsibility for the output statuses of pins, input and output settings, and the
contents of registers at power on. However, NEC assures operation after reset and items
for mode setting if they are defined.
When you turn on a device having a reset function, be sure to reset the device first.

60
 µPD75208

[MEMO]

61
 µPD75208

[MEMO]

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M4 92.6
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