A Low-Power Active Switched-Capacitor Loop Filter

for Phase Locked Loops

Yu Song and Zeljko Ignjatovic

Dept. of Electrical and Computer Engineering
University of Rochester
Rochester, NY 14627, USA
{yusong, ignjatov}@ece.rochester.edu

Abstract—We propose a low-power active switched-capacitor In this paper, a novel PLL loop filter using active low
(SC) implementation of the loop filter for PLL applications. power SC circuits is proposed. The use of a sub-threshold
Control voltage ripples caused by current mismatches are class-C inverter as the SC active element can reduce power
eliminated. Sub-threshold inverters are employed as the active consumption to a level lower than the CT filter. The DC pole
components of the filter resulting in very low circuit power required in the Type II loop filter is provided by the SC filter
consumption. Moreover, 1/f noise of the inverter amplifier is in the discrete-time domain. Other advantages like low
suppressed by the SC auto-zeroing. Transistor level simulation reference spurs and small capacitor sizes are still
of a 2.4-GHz frequency synthesizer in a 0.18μm technology is accomplished. Additionally, as opposed to continuous time
carried out to verify the proposed loop filter. With a 10 MHz
filters, 1/f noise of the active inverters can be readily
input reference frequency, the sub-threshold inverter amplifier
consumes about 110uA with a 1.25V power supply.
suppressed by the auto-zero function in the SC circuit.
Section II presents the low power active SC loop filter
I. INTRODUCTION design. Transfer functions, which can be easily used for
practical designs, are provided. The effects of the sample-
Phase-locked loops (PLLs) are widely used components in and-hold output are included. A transistor level 2.4 GHz PLL
modern electronic systems, such as in the fields of wireless is designed with the proposed loop filter in a 0.18um CMOS
communication systems, micro-processing and high-speed environment and simulation results are present in Section III.
data conversion systems. These systems usually impose very Non-idealities of SC circuits and their solutions are also
stringent requirements on PLLs' performance, and make their discussed. Section IV concludes the paper.
integrated implementation a troublesome procedure. One of
the difficulties is the large on-chip capacitor area required in II. ACTIVE SC LOOP FILTER DESIGN
a conventional RC loop filter. Another major problem is the
reference spurs or jitters caused by the mismatch between the A. SC Filters
positive and negative charge pump currents. While SC filters are very popular in CMOS analog signal
Recently, switched-capacitor (SC) loop filters have processing for their high accuracy, conventional SC filters
become popular substitutes for the conventional RC ones. consume more power compared to their continuous-time
While many works have shown their effectiveness on the counterparts, because the amplifier bandwidth must be large
problems mentioned above, some imperfections still exist. In enough for adequate settling accuracy in SC circuits. For a
[1-3], with the use of passive SC loop filters, small on-chip conventional OTA SC integrator, to achieve a settling
capacitors and low reference spur levels are accomplished. accuracy of 0.1%, the unity gain frequency of the amplifier
However, these loop filters do not have a DC pole and the should be at least 2.23/β times the sampling frequency, where
loop dynamics become Type I, resulting in a limited lock-in β is the feedback coefficient. Therefore, for medium frequency
range problem. In order to achieve a Type II SC PLL, operations, the OTA can be power hungry. In the existing type
existing solutions [4-5] employ additional continuous-time II SC loop filter designs, to reduce power consumption,
(CT) active filters to provide the missing DC pole. But continuous-time active filters are used following the passive
operational transconductance amplifiers (OTAs) or Gm cells SC stage to generate the DC pole and the stabilizing zero [4-5].
in these topologies increase power consumption, and more In this work, a low power active SC PLL loop filter is
importantly, additional 1/f and thermal noise are introduced. designed. To achieve a power-efficiency higher than the active
continuous-time filters, sub-threshold inverters are used as the

978-1-4244-5309-2/10/$26.00 ©2010 IEEE 1316

 semiconductor technology.

B. Low Power SC Loop Filter

The proposed low power active SC PLL loop filter is
shown in Fig. 2. Two charge pumps are used to generate
currents with inverse polarities. The buffer in the circuit can
be a simple source follower. When the charge pump current
sources are turned on, Φ1 is on, and Cs1 and Cs2 are charged
or discharged accordingly. Then Φ2 is turned on and the
charge is redistributed among the capacitors and an output
voltage is established at the inverter output. This voltage is
taken as the VCO control voltage when the delayed Φ2 is on.
When Φ2 and Φ2d are off, ΦRST is on and Cs2 are reset to
VREF and the filter is ready for the next update cycle. It is clear
from the schematic that one control voltage update cycle
Figure 1. Relationship of DC gain and bandwidth on an inverter's power consists of different phases. Since the charging phase (Φ1) is
supply volatge isolated from the voltage output phase (Φ2d) and the net
charge injected into the loop filter is zero when the loop is
active components instead of the conventional OTAs. In [6], locked, voltage ripples caused by charge pump current
Sigma-Delta data converters built with class-C inverter SC mismatch are no longer present.
integrators demonstrates both very low power consumption
and high accuracy. Transfer functions of this loop filter are derived below.
Cs1=Cs2=Cs and unity buffer gain are assumed for simplicity.
Low power consumption for the SC circuit is achieved by It can be shown that the discrete-time phase to output voltage
setting the active-element/inverter power supply voltage close transfer function of this loop filter is
to the sum of NMOS and PMOS thresholds; therefore, the
inverter operates in a class-C manner [6]. Since the transistors I IN T ⎛ Cs z -1/ 2 C 2 ⋅ z -1/ 2 ⎞
in the inverter are in the weak-inversion region most of the H ( z) = ⋅ ⋅⎜ ⋅ + ⎟, (1)
2π Cs ⎜ CI (1- z -1 ) CI ⎟
time and the static current is small, power consumption is ⎝ ⎠
reduced significantly. The dependency of DC gain and
bandwidth of a cascode inverter on its power supply is plotted where IIN is the charge pump current as in Fig. 2 and T is the
in a 0.18um CMOS environment is plotted in Fig. 1. The sum update period or the reference period when the loop is locked.
of Vtn and Vtp is approximately 1.2V for a 0.18um channel We assume KCP=IIN/2π, m=C2/Cs and use (2) to derive (3).
length, with high threshold transistors used to increase the ωT
output swing. The figure shows that if the inverter is powered z1/ 2 − z −1/ 2 = 2 j sin (2)
at the boundary of weak and strong inversion, large DC gain 2
and unity gain bandwidth can be obtained simultaneously. Equation (1) can be rearranged as
High slew rate can also be obtained during the short transition
phase when one of the inverter transistors is shifted into the T ⎛ 1 + 2m sin (ωT 2 ) + j ⋅ m sin (ωT ) ⎞
2

strong inversion due to input voltage change. This provides a H ( jω ) = K CP ⎜⎜ ⎟⎟ . (3)

CI ⎝ 2 j ⋅ sin (ωT 2 ) ⎠
promising way to build power-efficient SC circuits, especially
considering the fact that the output voltage swing of
conventional OTAs continues to drop with the advancement of

Figure 2. Proposed SC PLL loop filter

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 Figure 6. The transient response of PLL control voltages

Figure 3. Phase and gain responses of the sinc and single pole filters

In PLLs, low-frequency response of the loop filteris of

more interest because the PLL loop bandwidth should be less
than 1/10 of the reference frequency for stability concerns. For
those frequencies, we assume
sin (ωT / 2 ) ≅ ωT / 2 . (4)

With (4), the SC filter transfer function can be approximated

by the following continuous-time transfer function
K CP (1 + jω ω z1 )(1 + jω ω z 2 )
H ( jω ) ≅ ⋅ , (5)
CI jω
where

ω z1 = 2 ⎡⎢
⎣ ( )
m 2 + 2m + m T ⎤ ,
⎦⎥
(6)
Figure 4. Magnitude and phase responses of the active SC loop filters

ω z 2 = − 2 ⎡⎢
⎣ ( )
m 2 + 2m − m T ⎤ .
⎥⎦
(7) where s = jω.
Equation (8) carries the necessities for a type II PLL loop
In Fig. 2, the Φ2d switch performs a sample and hold filter. Unlike the passive SC filters, the DC pole is preserved
function and it has a sinc response. Assuming the holding time by the active SC integration. The stabilizing zero ωz1 is also
is much larger than the sampling time, the complete phase-to- well defined since T is the reference period. In addition, a
control voltage transfer function approximation should be redundant right half plane (RHP) zero ωz2 exists in this loop
filter. However, this RHP zero has negligible effects on the
K CP (1 + jω ω z1 )(1 + jω ω z 2 ) sin (ωT 2 ) e
− jωT / 2

H ( jω ) ≅ ⋅ . loop stability since it is at a frequency much higher than the

CI jω ωT 2 frequency of the stabilizing zero (m>>1).
(8) The loop phase margin can be found easily from (9), as
The sinc low pass filter has a strong impact on the filter's
magnitude and phase behaviors. In order to simplify the ⎛ ωc ⎞ −1 ⎛ ω c ⎞
⎛
−1 ω c
⎞
φm = tan −1 ⎜ ⎟ + tan ⎜ ⎟ − tan ⎜⎜ ⎟⎟ , (10)
analysis, a single pole ωp = 2/T is used to approximate the sinc ⎝ ω z1 ⎠ ⎝ ωz 2 ⎠ ⎝ ωp ⎠
filter's low frequency behavior. The phase and gain responses
of the sinc and its approximation single pole filters are plotted where ωc is the unity gain frequency of the open loop. Since
in Fig. 3. Their differences at 1/10 sampling frequency are ωz 2 ≅ −ω p , the phase margin reaches its maximum when
also shown and the small deviations verify the validity of this
approximation. With this method, the open loop gain of this
SC loop filter can be further approximated by ωc =
(ω p − 2ω z1 ) ωz1ω p
. (11)
2ω p − ω z1
K CP (1 + s ω z1 )(1 + s ωz 2 )
H ( s) ≅ (9)
CI s ⋅ (1 + s / ω p ) A loop filter is designed using the above analysis. Its
magnitude and phase responses from 10 KHz to 10MHz are

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 Figure 6. Transient response of the PLL’s control voltages

configuration, common mode errors, like leakage current and

Figure 5. The PLL open loop magnitude response the above two, can be effectively reduced.
depicted in Fig. 4. The loop filter is designed for a 2.4GHz Another important factor that affects circuit performance is
PLL with a 10 MHz reference frequency and a 550 KHz loop noise. In this SC loop filter, while the inverter introduces
bandwidth. A 51 degree phase margin is chosen. The active noise, its influence is limited. The inverter 1/f noise is
magnitude response of the target PLL open loop gain is shown suppressed by the offset-canceling or auto-zeroing function of
in Fig. 5. In Fig. 4, it is clear that at frequencies smaller than Cc. In terms of thermal noise, it can be shown that the
1/(10T), equation (9) is a good approximation for the original dominant noise source is the KTC noise. It has a sinc-shape
transfer function and this proves that the series of spectrum and its PSD is inversely proportional to the sampling
simplifications used above is valid. Loop filter circuit frequency. Thus capacitor sizes and input reference frequency
simulation is also carried out in Cadence and the results follow should be selected carefully to meet design specifications.
the theoretical prediction well.
IV. CONCLUSION
III. PLL SIMULATION RESULTS
A new low-power active SC loop filter for PLLs utilizing
A transistor-level PLL is designed with the proposed low sub-threshold inverters as active components is proposed in
power active SC loop filter in a 0.18um CMOS environment. this paper. To simplify design procedure, a low frequency
The loop filter is implemented in a differential configuration approximation for its transfer function is provided. Transistor-
and a differentially tuned VCO is used. For a 10 MHz input level simulation is carried out in a 0.18um CMOS
reference frequency, the sub-threshold inverter amplifier environment and a 2.4 GHz PLL is successfully designed
consumes a static current of about 110uA under a 1.25V using this loop filter. The layout of a 2.4 GHz LC VCO PLL
power supply. The increase of inverter power supply voltage using this loop filter is completed and scheduled for
can give a larger bandwidth, but the current will also rise. The fabrication.
source follower buffer is biased at about 50uA. Figure 6
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