DECODER

• WHAT IS DECODER?
Decoder is a combinational circuit that has ‘n’ input lines and maximum
of 2n output lines. One of these outputs will be active High based on the
combination of inputs present, when the decoder is enabled. That means
decoder detects a particular code.

e.g.1 If a decoder takes 2 inputs the corresponding output will be 22=4

outputs. Such a decoder will be called 2X4 Decoder.

e.g.2 If a decoder takes 10 inputs the corresponding output will be

210=1024 outputs. Such a decoder will be called 10X1024 Decoder.

• CIRCUIT DESIGN OF A DECODER

Suppose the decoder we have got is a 3x8 decoder. So this means, that
there will be 3 inputs and 8 outputs. Each decoder has 2 main gates used
NOT & AND gates.

Consider the inputs to be A,B,C and the corresponding outputs are taken
from
D0, D1, D2, D3, D4, D5, D6, D7,
 FIGURE 1:: A 3x8
Decoder circuit
diagram

• LET US DEFINE THE CIRCUIT

As you can see from the figure, 2 types of inputs are taken. One is normal
input and the other is inverted input (From the NOT gate).
Question is “ when do we take what?”.
When you are beginning to draw the circuit, forget everything and focus on
one thing. The normal input is always HIGH(1) and
the inverted input is always LOW(0).

Good! Now draw the wires from the corresponding inputs to the AND gate.
The inputs are drawn from the input from the Binary representation chart.
i.e. (For a 3x8 decoder, 3 bits are necessary for representation)
 TABLE 1:: BINARY
REPRESENTATION USING 3 BIT

A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Now look closely.

• If you consider 000 or D0. Here is how you draw the inputs:

The Light Green line corresponds to 0 and the dark green refers to 1

• Similarly if we consider 001 or D1,

Notice the difference? Now compare every input to Figure 1 and table 1 and you’ll
get the results
• Now, as you can see in the figures above, you’re seeing a high input next to
D1 while all the others are low. What is up with that? Lets find out.

Recall to the first line you read in this note. It said, a Decoder gives one
High input and all others are low.
So how do we decide which value will be high? Let us see that.

✓ Lets see the example where A,B,C all are 0. i.e. 000 and the output is
from D0.
[Note:: The previous time we considered 000 was for
desiging purpose, donot confuse with output finding ]

Now. We can see that all the inputs taken are inverted inputs

Since the inverted result of 0 is 1. So in all the inputs, 1 is passed to

the AND gate.

i.e. Input given by user:: 000

Input received by AND gate:: 111

Output given by AND gate::: 1(high)

 ✓ Lets see the example where A,B,C are 001 and the output is from D1.

Now. We can see that the inputs taken from A,B are inverted inputs
And the input from C is original output

So from A and B inverted value of 0, i.e. 1 is given to the AND gate

and from C the original value (1) is sent to the AND gate

i.e. Input given by user:: 001

Input received by AND gate:: 111

Output given by AND gate::: 1(high)

Here is how the rest of the circuit looks when the user
input is 001

NOTICE THAT
ONLY D1 IS HIGH
OUTPUT WHILE
THE REST HAS
LOW OUTPUT
 ✓ Lets see the example where A,B,C are 101 and the output is from D5.

Now. We can see that the inputs taken from A,C are original inputs
And the input from B is original value

So from A and C original value i.e. 1 is given to the AND gate and
from B the inverted value of 0 i.e 1 is sent to the AND gate

i.e. Input given by user:: 101

Input received by AND gate:: 111

Output given by AND gate::: 1(high)

Here is how the rest of the circuit looks when the user input is 101

NOTICE THAT
ONLY D5 IS HIGH
OUTPUT WHILE
THE REST HAS
LOW OUTPUT
If we look at the outputs from every input combination of a 3x8
decoder, we can see a pattern

A B C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

• BLOCK DIAGRAM REPRESENTATION OF A

DECODER
Taking the example of the previous 3x8 decoder, we
draw the block representation
• ACTIVE LOW DECODER
There does exist yet another type of decoder called the active low decoder.
The difference between this and the previously discussed decoder is that, it
uses NAND gates instead of AND gates.
Thus, in this case the decoder gives only one low output for any particular
combination and all the other outputs are high.

Lets see the combination 000. Here the D0 is supposed to give low output
and all other are giving high output
 Lets see another example. 010. Here D2 is supposed to give a low output and all
others give high output

If we look at the outputs from every input combination of a 3x8 decoder, we can see a
pattern

A B C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 0 1 1 1 1 1 1 1
0 0 1 1 0 1 1 1 1 1 1
0 1 0 1 1 0 1 1 1 1 1
0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 1 1 1 0 1 1 1
1 0 1 1 1 1 1 1 0 1 1
1 1 0 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 0
• REPRESENTING BOOLEAN FUNCTIONS USING
DECODER
Let us take an example. Suppose a function is described as
F=m(2,3,5,7,9,11)
If we had to design its logic circuit, we had to draw its K-map and reduce it
and then draw accordingly.
However, Using a decoder, we can easily draw the circuit.

First. We check the greatest min-term available in the given equation. Here
it is 11. 11<16. So 4 bits are enough to represent the minterms.
This means that there will be 4 inputs. Accordingly in a decoder, 4 inputs
result in 24=16 outputs.
The decoder therefore required is 4x16 decoder.

Then, the decoder Dn corresponding to the nth minterm is passed to a OR

gate as shown below.
• IMPLEMENTING FULL ADDER USING DECODER
Let us take the previous example.
F=m(2,3,5,7,9,11)
So the sum and carry will be represented as
S=m(1,2,4,7)
And the carry will be represented as
C=m(3,5,6,7)
Using the same technique as before ,.i.e passing the outputs of Dn with the
corresponding min-term to a OR gate gives us the necessary circuit.
• ENABLE LINE IN DECODER
So far, we have seen how to represent and use decoders.
There was one thing that we didn’t discuss. The concept of “Enable lines”.

A standard decoder typically has an additional input called Enable. Output

is only generated when the Enable input has value 1; otherwise, all outputs
are 0. Only a small change in the implementation is required:
the Enable input is fed into the AND gates which produce the outputs.

There are two types of device.

1. Low Enable,
2. High Enable

LOW ENABLE:
Low enable devices are those which work when the input given to the
Enable wire is low. The enable value is passed through a NOT gate, so the
low input is actually converted to high and the decoder is active.
CIRCUIT DIAGRAM:

Notice how
when the
enable
value is 0
(low), the
decoder is
active
 CIRCUIT DIAGRAM:

Notice how
when the
enable
value is 1
(high), the
decoder is
inactive

BLOCK DIAGRAM

Notice the small bubble at the end of the enable line E. This denotes
that it is a low enable device
HIGH ENABLE:
High enable devices are those which work when the input given to the
Enable wire is high.
CIRCUIT DIAGRAM:

Notice how
when the
enable
value is
1(high), the
decoder is
active

Notice how
when the
enable
value is
0(low), the
decoder is
inactive
 BLOCK DIAGRAM

Notice that there is no bubble at E, so it indicates that it is a high

enable device.

• IMPLEMENTING HIGHER ORDER DECODER

USING LOWER ORDER DECODER.

Suppose we are asked to make a 5x32 decoder using some smaller

decoders.
There are 2 types of decoder that we use.
One decoder takes some part of the input and gives output as the enable
lines for the rest of the 2nd type decoder.
The 2nd type decoder finally gives the desired output.
So, for a 5x32 decoder. We can choose the 2nd type decoder as a 3x8
decoder.
Now, we will require (32/8) =4 number of 3x8 decoder to create the
desired 5x32 decoder.
In order to make the 4 nos. Of 3x8 decoder to run, we need 4 enable lines.
Therefore we need another 2x4 decoder to give 4 enable lines which shall
connect to 3x8 decoders.
The following diagram makes it easy to asses.
 Lets say the inputs are P,Q,R,S,T
So,

The blue lines indicate the enable lines.

We can find the number of lower order decoders required for implementing higher
order decoder using the following formula.

Required number of lower order decoders = m2/m1

Where,
m2= total number of outputs of higher order decoder
m1= total number of output of the lower order decoder.

In the previous example, we had 32 outputs for the higher order

decoder and 8 outputs for the lower order. So 32/8=4.

Now since a 4 3x8 decoders need 4 enable lines, so we must choose a

decoder that gives 4 outputs, hence the need of the 2x4 decoder.

Let us take another example to confirm the explanation::

We have to implement a 9X 512 decoder using smaller decoders.

So, m2 = 512.
We can choose m1 as 16,
So, (m2/m1) =(512/16)= 32.
Hence we require 32 nos. of 4x16 decoders.
Now , 32, nos of 4x16 decoders will require 32 nos. of enable lines.
The way we can get 32 enable lines is only by using a 5x32 decoder.

Thus 5 inputs would be passed to the 5X32 decoder and the rest 3 inputs would be
distributed to the 32nos of 4x16 decoders (along with enable lines for each).
So, to summarize,

32 nos. of 4x16 decoders and 1 nos. 5x32 decoder is required for a 9x512 decoder.