CSE1003 - Digital Logic Design

Module 3: Design of Combinational

Logic Circuits
Module 3: Combinational Circuit-I
• Adder
• Subtractor
• Encoder & Decoder
• Multiplexer & Demultiplexer
• Parity Generator & Checker
• Applications of decoders, multiplexers, de
multiplexers
• Modeling of combinational logic circuits using
Verilog HDL
Adder and Subtractor
Binary Addition – Sum & Carry
Binary Addition – Carry In & Carry Out
Half adder
Full Adder
Half Adder
Half Adder
Full Adder – Truth Table
Full Adder using two half adders
Full Adder using two half adders
Full Adder – Truth Table
Full Adder
Full Adder
Binary Subtraction
Half Subtractor
Half Adder and Subtractor
Full Subtractor – Truth Table
Full Subtractor
Full Subtractor
Full Subtractor
Full adder and
full Subtractor
 Parity Generators/Checkers
• When binary data is transmitted and processed ,
data may be subjected to noise so that such noise
can alter 0s (of data bits) to 1s and 1s to 0s.
• The message containing the data bits along with
parity bit is transmitted from transmitter node to
receiver node.
• At the receiving end, the number of 1s in the
message is counted and if it doesn’t match with
the transmitted one, then it means there is an
error in the data.
 Parity Generators/Checkers
• Parity is an error detection method
• Commonly used in digital systems to detect the
single bit errors in the transmitted data
• Uses an extra bit appended to a group of bits
• Parity bit is added to the input data in order to
make number of 1s either even or odd.
• Let s = 1010011.
• S with odd parity = 11010011
• S with even parity =01010011
Odd parity generator/checker
Odd Parity Bit Generator
Odd Parity Bit Generator
 Odd Parity Bit Generator
• P = A ⊕ B Ex-NOR C
Odd Parity bit Checker
Odd Parity Bit Error Checker
 Odd Parity Bit Error Checker
• PEC = (A Ex-NOR B) Ex-NOR (C Ex-NOR D)
Even Parity Bit Generator
Even Parity Bit Error Checker
Even Parity Bit Generator
Even Parity Error Checker
Magnitude Comparator
1-bit Magnitude Comparator
1-bit Magnitude Comparator
A>B: AB'
A<B: A'B
A=B: A'B' + AB
A1 A0 B1 B0 A<B A=B A>B
0 0 0 0 2-bit
0 0 0 1
0 0 1 0 Magnitude
0
0
0
1
1
0
1
0
Comparator
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
2-bit Magnitude Comparator
 2-bit Magnitude Comparator
A1 A0 B1 B0 A<B A=B A>B
0 0 0 0 0 1 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0 For A<B:
0 0 1 1 1 0 0 A1’A0’B0 + A1’B1 + A0’B1B0
0 1 0 0 0 0 1
0 1 0 1 0 1 0 For A=B:
0 1 1 0 1 0 0 (A1 ⊙B1) . (A0 ⊙B0)
0 1 1 1 1 0 0
1 0 0 0 0 0 1 For A>B:
1 0 0 1 0 0 1
A0B1’B0’+ A1A0B0’ + A1B1’
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0
2-bit Magnitude
Comparator
 Encoders & Decoders
• Encoders - Convert 2N lines of input into a
code of N bits.
• Decoders - decode the N bits into 2N lines.
 Applications of Encoders
• Binary code of N digits can be used to store
2N distinct elements of coded information.
 Encoders
• Combinational circuit that converts binary
information in the form of a 2N input lines into
N output lines
• In simple encoders, only one input line is
active at a time.
 Octal to Binary encoder
• An octal-to-binary encoder takes 8 input lines
and generates 3 output lines.
 Octal to Binary encoder
D7 D6 D5 D4 D3 D2 D1 D0 X Y Z
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
X = D4 + D5 + D6 + D7
Y = D2 +D3 + D6 + D7
Z = D1 + D3 + D5 + D7
 Octal to Binary encoder
• As seen from the truth table, the output is 000
when D0 is active; 001 when D1 is active; 010
when D2 is active and so on.
• X = D4 + D5 + D6 + D7
• Y = D2 +D3 + D6 + D7
• Z = D1 + D3 + D5 + D7
Octal to Binary encoder
 Priority Encoder
• Priority encoders output the highest order
input first
• for example, if input lines “D2“, “D3” and “D5”
are applied simultaneously the output code
would be for input “D5” (“101”) as this has the
highest order out of the 3 inputs.
• Once input “D5” had been removed the next
highest output code would be for input “D3”
(“011”), and so on.
 Digital Inputs Binary Output

D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0 Priority
Encoder
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 1 X X X 0 1 1
0 0 0 1 X X X X 1 0 0
0 0 1 X X X X X 1 0 1
0 1 X X X X X X 1 1 0
1 X X X X X X X 1 1 1
 Digital Inputs Binary Output

D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0 Priority Encoder
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 1 X X X 0 1 1
0 0 0 1 X X X X 1 0 0
0 0 1 X X X X X 1 0 1
0 1 X X X X X X 1 1 0
1 X X X X X X X 1 1 1
Priority Encoder
 Priority Encoder Applications
• Keyboard Encoder
– only one key would be pressed either “HIGH” or “LOW” at any
one time
• Positional Encoders
– magnetic positional control as used on ships navigation
– for robotic arm positioning
• Interrupt Requests
– For detecting interrupts in microprocessor applications.
– The microprocessor uses interrupts to allow peripheral devices
such as the disk drive, scanner, mouse, or printer etc, to
communicate with it, but the microprocessor can only “talk” to
one peripheral device at a time.
– The processor does this by assigning priority to all the
peripheral devices to ensure that the most important peripheral
device is serviced first.
 Decoder
• Convert digital signal to an analogue signal
• Allows single input line and produces multiple
output lines.
• Has N input lines and 2N output lines
 3 to 23 Decoder
X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
 3 to 23
X Y Z D0 D1 D2 D3 D4 D5 D6 D7 Decoder
0 0 0 1 0 0 0 0 0 0 0 • D0 = X’ Y’ Z’
0 0 1 0 1 0 0 0 0 0 0 • D1 = X’ Y’ Z
• D2 = X’ Y Z’
0 1 0 0 0 1 0 0 0 0 0
• D3 = X’ Y Z
0 1 1 0 0 0 1 0 0 0 0
• D4 = X Y’ Z’
1 0 0 0 0 0 0 1 0 0 0 • D5 = X Y’ Z
1 0 1 0 0 0 0 0 1 0 0 • D6 = X Y Z’
1 1 0 0 0 0 0 0 0 1 0 • D7 = X Y Z
1 1 1 0 0 0 0 0 0 0 1
 Decoder
• D0 = X’ Y’ Z’
• D1 = X’ Y’ Z
• D2 = X’ Y Z’
• D3 = X’ Y Z
• D4 = X Y’ Z’
• D5 = X Y’ Z
• D6 = X Y Z’
• D7 = X Y Z
 Multiplexer
• MUX - several inputs but provide a single
output.
• multiplexer acts as data selector
Multiplexer
 Applications
Multiplexers are used in various applications wherein multiple-
data need to be transmitted by using single line.
MUX & DEMUX
Telephony Multiplexer System
MUX & DEMUX Applications
MUX & DEMUX Applications
MUX Applications
4-to-1 Channel
Multiplexer
4-to-1 Channel Multiplexer
4-to-1 Channel
Multiplexer
4-to-2 Channel Multiplexer
Adjustable Amplifier Gain
 Applications of Multiplexer
• Multiplexer are used in various fields where multiple data need to be transmitted
using a single line. Following are some of the applications of multiplexers –
• Communication system – Communication system is a set of system that enable
communication like transmission system, relay and tributary station, and
communication network. The efficiency of communication system can be
increased considerably using multiplexer. Multiplexer allow the process of
transmitting different type of data such as audio, video at the same time using a
single transmission line.
• Telephone network – In telephone network, multiple audio signals are integrated
on a single line for transmission with the help of multiplexers. In this way, multiple
audio signals can be isolated and eventually, the desire audio signals reach the
intended recipients.
• Computer memory – Multiplexers are used to implement huge amount of
memory into the computer, at the same time reduces the number of copper lines
required to connect the memory to other parts of the computer circuit.
• Transmission from the computer system of a satellite – Multiplexer can be used
for the transmission of data signals from the computer system of a satellite or
spacecraft to the ground system using the GPS (Global Positioning System)
satellites.
 De Multiplexer
• DEMUX - reverses the operation of MUX.
• Single input but transmits the data to multiple
outputs.
• Demultiplexer acts as a data distributor.
1-to-4 De Multiplexer
1-to-4 De multiplexer

Output Select Data

Output
a b Selected

0 0 A
0 1 B
1 0 C
1 1 D
1-to-4 De
multiplexer
Digitally Adjustable Amplifier Gain
 De Multiplexer and Decoder
• De multiplexer - accepts only one input and
directs it into one of the several outputs.
• Decoder - accept many inputs and generate
the decoded output.
De Multiplexer and Decoder
ADDER USING MUX
IC 74153 - Dual 4-input multiplexer
HALF ADDER USING MUX IC 74153
HALF ADDER USING MUX
FULL ADDER USING MUX IC 74153
FULL ADDER TRUTH TABLE
 Ripple Carry Adder/N-Bit Parallel
Adder
• To add together two n-bit numbers, n number
of 1-bit full adders are “cascaded” together to
produce a Ripple Carry Adder.
• A “ripple carry adder” is simply “n“, 1-bit full
adders cascaded together.
4-bit Ripple Carry Adder
 Disadvantage of Ripple Carry Adder
One main disadvantage of “cascading” together
1-bit binary adders to add large binary numbers
is :
• MSB of the sum has to wait for any changes
from the carry input of the LSB
• This unwanted delay time is
called Propagation delay
 Carry Look Ahead Binary Adder
• Generates the carry-input signals directly
from the A and B inputs rather than using
the ripple arrangement above.
• The speed of the parallel adder can be
greatly improved using carry-look ahead
logic.
Carry look ahead adders - Advantage
• Length of time a carry look ahead adder needs
to produce the SUM is independent of the
number of data bits.
 Carry Look-ahead Adder
• Carry look-ahead adder reduces the
propagation delay by introducing more
complex hardware.
• Ripple carry design is suitably transformed
such that the carry logic over fixed groups of
bits of the adder is reduced to two-level logic.
 4-Bit Carry Look Ahead Adder
• Consider two 4-bit binary numbers
A3A2A1A0 and B3B2B1B0 are to be added.
• Mathematically, the two numbers will be
added as-
 C1 = C0 (A0 ⊕ B0) + A0B0
C2 = C1 (A1 ⊕ B1) + A1B1
C3 = C2 (A2 ⊕ B2) + A2B2
C4 = C3 (A3 ⊕ B3) + A3B3

For simplicity, Let-

Gi = AiBi where G is called carry generator
Pi = Ai ⊕ Bi where P is called carry propagator
Then, re-writing the above equations, we have-
C1 = C0P0 + G0 ………….. (1)
C2 = C1P1 + G1 ………….. (2)
C3 = C2P2 + G2 ………….. (3)
C4 = C3P3 + G3 ………….. (4)
 C1 = C0 (A0 ⊕ B0) + A0B0
C2 = C1 (A1 ⊕ B1) + A1B1
C3 = C2 (A2 ⊕ B2) + A2B2
C4 = C3 (A3 ⊕ B3) + A3B3
Substituting (1) in (2), we get C2 in terms of C0.
Finally, we have the following equations-
• C1 = C0P0 + G0
• C2 = C0P0P1 + G0P1 + G1
• C3 = C0P0P1P2 + G0P1P2 + G1P2 + G2
• C4 =C0P0P1P2P3 + G0P1P2P3 + G1P2P3 + G2P3 + G3
Then, substituting (2) in (3), we get C3 in terms
of C0 and so on.
Implementation Of C1
Implementation Of C2
 Implementation Of C3 & C4
• Similarly, implement C3 and C4.
• Implementation of C3 uses 3 AND gates and 1
OR gate.
• Implementation of C4 uses 4 AND gates and 1
OR gate.
Carry look ahead adder
4 Bit Carry look ahead adder
 Advantages of Carry Look Ahead
Adder
• Generates carry-in for each full adder
simultaneously.
• Reduces propagation delay.
 Disadvantages of Carry Look Ahead
Adder
• Involves complex hardware.
• Costlier since it involves complex hardware.
• More complicated as the number of bits
increases.
 Unsigned Binary Number
• Unsigned binary numbers are, by
definition, positive numbers and thus do not
require an arithmetic sign.
• An m-bit unsigned number represents all
numbers in the range 0 to 2m − 1.
 Unsigned Array Multiplier
• Very popular binary multiplication.
• Resembles pen and paper method of
multiplication process.
• On the contrary to the sequential multiplier,
array multiplier is parallel.
• An array of full adders are used for the
multiplication process.
• For n-bit data width, total n(n-1) full adders
are used in this multiplier.
Array multiplication process for two 4-bit
unsigned numbers a and b is shown below.
 Multiplier Applications
• One of the key hardware blocks in most digital
signal processing (DSP) systems.
• Typical DSP applications where a multiplier
plays an important role include digital
filtering, digital communications and spectral
analysis.
 Booth Multiplier
• Booth's Algorithm is used for binary
multiplication.
• Used for multiplication of 2 signed numbers.
• Booth multiplication algorithm defines a
multiplication algorithm that can multiply
two signed binary numbers in two’s
complement.
• This algorithm helps in the study of
computer architecture.
 Booth Multiplier
• Reduces the power consumption of
multipliers.
• speeds up the performance of the
multiplication process.
• It works on the string bits 0's in the multiplier.
• It doenot require additional bit
• It only shift the right-most string bits and a
string of 1's in a multiplier bit weight 2k to
weight 2m that can be considered as 2k+ 1 - 2m.
Pictorial Representation Of The Booth's
Algorithm:
 Working on the Booth Algorithm
1. Set the Multiplicand and Multiplier binary bits as
M and Q, respectively.
2. Initially, we set the AC and Qn + 1 registers value
to 0.
3. SC represents the number of Multiplier bits (Q),
and it is a sequence counter that is continuously
decremented till equal to the number of bits (n)
or reached to 0.
4. A Qn represents the last bit of the Q, and the
Qn+1 shows the incremented bit of Qn by 1.
 Working on the Booth Algorithm
5. On each cycle of the booth algorithm, Qn and Qn + 1 bits will be
checked on the following parameters as follows:
5. When two bits Qn and Qn + 1 are 00 or 11, we simply perform the
arithmetic shift right operation (ashr) to the partial product AC. And
the bits of Qn and Qn + 1 is incremented by 1 bit.
6. If the bits of Qn and Qn + 1 is shows to 01, the multiplicand bits (M)
will be added to the AC (Accumulator register). After that, we
perform the right shift operation to the AC and QR bits by 1.
7. If the bits of Qn and Qn + 1 is shows to 10, the multiplicand bits (M)
will be subtracted from the AC (Accumulator register). After that, we
perform the right shift operation to the AC and QR bits by 1.
6. The operation continuously works till we reached n - 1 bit in the
booth algorithm.
7. Results of the Multiplication binary bits will be stored in the AC
and QR registers.
 Two methods used in Booth's
Algorithm
1. RSC (Right Shift Circular)
It shifts the right-most bit of the binary number,
and then it is added to the beginning of the
binary bits.
 Two methods used in Booth's
Algorithm
2. RSA (Right Shift Arithmetic)
• It adds the two binary bits and then shift the
result to the right by 1-bit position.
• Example: 0100 + 0110 => 1010, after adding
the binary number shift each bit by 1 to the
right and put the first bit of resultant to the
beginning of the new bit.
Multiply two numbers 7 and 3 by using
Booth's multiplication algorithm.
• Step1: Convert 7 and 3 into binary numbers like 7
= (0111) and 3 = (0011).
• Now set
– 7 (in binary 0111) as multiplicand (M)
– 3 (in binary 0011) as a multiplier (Q).
– SC (Sequence Count) represents the number of bits,
and here we have 4 bits, so set the SC = 4.
• Also, it shows the number of iteration cycles of
the booth's algorithms and then cycles run SC =
SC - 1 time.
 4 Bit Magnitude Comparator
• To compare two binary numbers with each of
four bits
 A>B
In a 4-bit comparator the condition of A>B can be
possible in the following four cases:

• If A3 = 1 and B3 = 0
• If A3 = B3 and A2 = 1 and B2 = 0
• If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
• If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0
 A<B
Similarly the condition for A<B can be possible in
the following four cases:
• If A3 = 0 and B3 = 1
• If A3 = B3 and A2 = 0 and B2 = 1
• If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
• If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1
 A=B
• The condition of A=B is possible only when all
the individual bits of one number exactly
coincide with corresponding bits of another
number.
4 Bit Magnitude Comparator
 Applications of Comparators
• Used in central processing units (CPUs) and
microcontrollers (MCUs).
• These are used in control applications in which
the binary numbers representing physical
variables such as temperature, position, etc. are
compared with a reference value.
• Comparators are also used as process controllers
and for Servo motor control.
• Used in password verification and biometric
applications.
IC7483
• https://www.electronicshub.org/carry-look-
ahead-adder/
• http://www.eng.ucy.ac.cy/theocharides/Cours
es/ECE210/Carrylookahead_supp4.pdf
 Code converter
• Code converter is used to convert one type of
binary code to another.
• There are different types of binary codes like
BCD code, gray code, excess-3 code, etc. ...
• To get the required code from any one type
of code, the simple code conversion process is
done with the help of combinational circuits.
 BCD to Excess-3 code converter

From the truth table, the minterms are obtained for each outputs(E3, E2, E1, E0).
E3 = ∑m(5, 6, 7, 8, 9), E2 = ∑m(1, 2, 3, 4, 9), E1 = ∑m(0, 3, 4, 7, 8), E0 = ∑m(0, 2, 4, 6, 8,)
 BCD to Excess-3 code converter

From the truth table, the minterms are obtained for each outputs(E3, E2, E1, E0).
E3 = ∑m(5, 6, 7, 8, 9), E2 = ∑m(1, 2, 3, 4, 9), E1 = ∑m(0, 3, 4, 7, 8), E0 = ∑m(0, 2, 4, 6, 8,)
 BCD to
Excess-3
code
converter
 BCD to
Excess-3
code
converter
BCD to Gray code converter
Binary to Gray Conversion
BCD to Gray code converter
 BCD to
Gray code
converter
 BCD to
Gray code
converter
BCD to Gray code converter – Using Ex-OR
gates
 Gray
Code to
Binary
Gray Code to Binary
Gray to Binary Conversion
K-map for b0 & b0
K-map for b2 & b3
Gray Code to Binary
Gray Code to Binary
 CAT I Syllabus
Module 1 – Digital Logic:
• Except Logic Families
Module 3 – Design of combinational logic circuits:
• Except Modeling of combinational logic circuits
using verilog HDL
Module 4 – Design of data path circuits:
• Except Booth multiplier and Modeling of data
path circuits using verilog HDL