Realtek: For V4L Confidential

RTL2832U
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DVB-T COFDM DEMODULATOR+USB 2.0
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DATASHEET
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(CONFIDENTIAL: Development Partners Only)
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01 November 2010
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Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL2832U
Datasheet
COPYRIGHT
©2010 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
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and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
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TRADEMARKS
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Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
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are trademarks/registered trademarks of their respective owners.
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USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
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RTL2832U.
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Though every effort has been made to ensure that this document is current and accurate, more information
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may have become available subsequent to the production of this guide.
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REVISION HISTORY
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Revision Release Date Summary
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1.0 2008/06/30 First release.
1.1 2009/02/06 Corrected typing errors.
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Revised ‘Connects a 12k ohm Resistor to ground’ to ‘Connects a 10k ohm
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1.2 2009/02/16 Resistor to ground’, in the ADC section of Table 1 Pin Descriptions, page 5.
Revised Figure 9, page 44.
1.3
1.4
2009/06/29
2010/11/01
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Corrected minor typing errors.
Added Table 38 Crystal Conditions, page 43.
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DVB-T COFDM Demodulator + USB 2.0 ii Track ID: JATR-2265-11 Rev. 1.4
RTL2832U
Datasheet
Table of Contents
1. GENERAL DESCRIPTION ..............................................................................................................................................1
2. FEATURES .........................................................................................................................................................................2
3. SYSTEM APPLICATIONS...............................................................................................................................................2
4. BLOCK DIAGRAM ...........................................................................................................................................................3
5. PIN ASSIGNMENTS .........................................................................................................................................................4
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5.1. GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................4
6. PIN DESCRIPTIONS.........................................................................................................................................................5
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7. FUNCTIONAL DESCRIPTION.......................................................................................................................................7
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7.1. ANALOG-TO-DIGITAL CONVERSION (ADC).................................................................................................................7
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7.2. AUTOMATIC GAIN CONTROL (AGC)............................................................................................................................7
7.3. DIGITAL DOWN CONVERSION ......................................................................................................................................7
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7.4. RESAMPLER .................................................................................................................................................................8
7.5. GUARD INTERVAL REMOVAL .......................................................................................................................................8
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7.6. FAST FOURIER TRANSFORM (FFT)...............................................................................................................................8
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7.7. SYNCHRONIZATION ......................................................................................................................................................8
7.8. CHANNEL ESTIMATION ................................................................................................................................................9
7.9. TRANSMISSION PARAMETER SIGNAL DECODER ...........................................................................................................9
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7.10. EQUALIZATION ............................................................................................................................................................9
7.11. DE-INTERLEAVER, FEC DECODER, AND DESCRAMBLER .............................................................................................9
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8. TUNER INTERFACE......................................................................................................................................................10
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8.1. AUTOMATIC GAIN CONTROL (AGC)..........................................................................................................................11
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8.1.1. Register Name: loop_gain ....................................................................................................................................12
8.1.2. Register Name: if_agc_min/if_agc_max/rf_agc_min/rf_agc_max .......................................................................13
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8.1.3. Register Name: Vtop.............................................................................................................................................13
8.1.4. Register Name: Krf...............................................................................................................................................14
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8.1.5. Register Name: if_agc_val/rf_agc_val .................................................................................................................14
8.2. ADC INPUT (TUNER OUTPUT) ...................................................................................................................................14
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8.3. TWO-WIRE INTERFACE BETWEEN THE TUNER AND THE RTL2832U .........................................................................15
8.4. RTL2832U INTERNAL SWITCHING REGULATOR ........................................................................................................16
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9. REGISTER DESCRIPTIONS (GENERAL)..................................................................................................................17
9.1.
9.2.
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ANALOG TO DIGITAL CONVERTER (ADC) .................................................................................................................17
DC CANCELLATION AND IQ COMPENSATION ............................................................................................................18
9.3.
9.4.
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DIGITAL DOWN CONVERSION (DDC) ........................................................................................................................19
RESAMPLER ...............................................................................................................................................................20
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9.5. CO-CHANNEL INTERFERENCE REJECTION ..................................................................................................................21
9.6. IMPULSE NOISE CANCELLATION ................................................................................................................................21
9.7. DIGITAL AUTOMATIC GAIN CONTROL (DAGC) ........................................................................................................22
9.8. FFT MODE DETECTION ..............................................................................................................................................22
9.9. TIMING RECOVERY/CARRIER RECOVERY ..................................................................................................................23
9.10. CRYSTAL....................................................................................................................................................................24
9.11. PID FILTER ................................................................................................................................................................24
10. REGISTER DESCRIPTIONS (8051 SYSTEM) .......................................................................................................27
10.1. DEMODULATOR CONTROL REGISTER (DEMOD_CTL, 0000H) .................................................................................29
10.2. GPIO RELATED REGISTERS (0001H~0008H) .............................................................................................................29
10.2.1. GPIO Output Value Register (GPO, 0001h) ...................................................................................................30
DVB-T COFDM Demodulator + USB 2.0 iii Track ID: JATR-2265-11 Rev. 1.4
RTL2832U
Datasheet
10.2.2. GPIO Input Value Register (GPI, 0002h)........................................................................................................30
10.2.3. GPIO Output Enable Register (GPOE, 0003h) ...............................................................................................31
10.2.4. GPIO Direction Control Register (GPD, 0004h) ............................................................................................31
10.2.5. PAD Configuration Register for GPIO0~3 (GP_CFG0, 0007h).....................................................................32
10.2.6. PAD Configuration Register for GPIO4 (GP_CFG1, 0008h).........................................................................32
10.3. I2C MASTER CONTROL REGISTERS (0040H-0053H) ...................................................................................................33
10.3.1. I2C Clock Register (I2CCR, 0040h-0043h)......................................................................................................33
10.3.2. I2C Master Control Register (I2CMCR, 0044h-0047h)...................................................................................33
10.3.3. I2C Master SCL Timing Register (I2CMSTR, 0048h-004Bh) ..........................................................................35
10.3.4. I2C Master Status Register (I2CMSR, 004Ch-004Fh) .....................................................................................35
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10.3.5. I2C Master FIFO Register (I2CMFR, 0050h-0053h) ......................................................................................36
11. REGISTER DESCRIPTIONS (USB INTERFACE) ................................................................................................36
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11.1. INTRODUCTION ..........................................................................................................................................................36
11.2. VENDOR COMMANDS .................................................................................................................................................36
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11.3. SIE CONTROL REGISTER ............................................................................................................................................38
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11.4. USB SYSTEM CONTROL REGISTER (USB_SYSCTL, 0000H) ....................................................................................39
11.4.1. Endpoint A Configuration Register (USB_EPA_CFG, 0144h) .......................................................................39
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11.4.2. Endpoint A Control Register (USB_EPA_CTL, 0148h) ..................................................................................40
11.4.3. Endpoint A Max Packet Size Register (USB_EPA_MAXPKT, 0158h) ............................................................40
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11.4.4. Endpoint A FIFO Configuration Register (USB_EPA_FIFO_CFG, 0160h) ..................................................40
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12. CHARACTERISTICS.................................................................................................................................................41
12.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................41
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12.2. DC CHARACTERISTICS ...............................................................................................................................................41
12.3. AC CHARACTERISTICS ...............................................................................................................................................42
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12.4. CRYSTAL CONDITIONS ...............................................................................................................................................43
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13. APPLICATION CIRCUITS .......................................................................................................................................44
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14. MECHANICAL DIMENSIONS.................................................................................................................................45
14.1. MECHANICAL DIMENSIONS NOTES ............................................................................................................................46
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15. ORDERING INFORMATION ...................................................................................................................................47
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RTL2832U
Datasheet
List of Tables
TABLE 1. PIN DESCRIPTIONS ........................................................................................................................................................5
TABLE 2. AAGC REGISTER TABLE ............................................................................................................................................12
TABLE 3. I2C REPEATER REGISTER TABLE .................................................................................................................................15
TABLE 4. ADC REGISTERS .........................................................................................................................................................17
TABLE 5. DC CANCELLATION REGISTERS ..................................................................................................................................18
TABLE 6. DIGITAL DOWN CONVERSION (DDC) .........................................................................................................................20
TABLE 7. RESAMPLER ................................................................................................................................................................20
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TABLE 8. CO-CHANNEL INTERFERENCE REJECTION...................................................................................................................21
TABLE 9. IMPULSE NOISE CANCELLATION .................................................................................................................................21
TABLE 10. DAGC REGISTERS .....................................................................................................................................................22
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TABLE 11. FTT MODE DETECTION..............................................................................................................................................22
TABLE 12. TIMING RECOVERY/CARRIER RECOVERY ..................................................................................................................24
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TABLE 13. PID FILTER ................................................................................................................................................................25
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TABLE 14. SYSTEM REGISTER DESCRIPTIONS .............................................................................................................................27
TABLE 15. DEMODULATOR CONTROL REGISTER (DEMOD_CTL, 0000H) .................................................................................29
TABLE 16. GPIO OUTPUT VALUE REGISTER (GPO, 0001H) .......................................................................................................30
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TABLE 17. GPIO INPUT VALUE REGISTER (GPI, 0002H) ............................................................................................................30
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TABLE 18. GPIO OUTPUT ENABLE REGISTER (GPOE, 0003H) ...................................................................................................31
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TABLE 19. GPIO DIRECTION CONTROL REGISTER (GPD, 0004H)...............................................................................................31
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TABLE 20. PAD CONFIGURATION REGISTER FOR GPIO0~3 (GP_CFG0, 0007H) .......................................................................32
TABLE 21. PAD CONFIGURATION REGISTER FOR GPIO4 (GP_CFG1, 0008H)............................................................................32
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TABLE 22. I2C CLOCK REGISTER (I2CCR, 0040H-0043H)...........................................................................................................33
TABLE 23. I2C MASTER CONTROL REGISTER (I2CMCR, 0044H-0047H) ....................................................................................33
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TABLE 24. I2C MASTER SCL TIMING REGISTER (I2CMSTR, 0048H-004BH) .............................................................................35
TABLE 25. I2C MASTER STATUS REGISTER (I2CMSR, 004CH-004FH) .......................................................................................35
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TABLE 26. I2C MASTER FIFO REGISTER (I2CMFR, 0050H-0053H)............................................................................................36
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TABLE 27. VENDOR COMMANDS .................................................................................................................................................36
TABLE 28. DEFINITION OF ‘WINDEX’...........................................................................................................................................37
TABLE 29. SIE CONTROL REGISTER ............................................................................................................................................38
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TABLE 30. USB SYSTEM CONTROL REGISTER (USB_SYSCTL, 0000H) ....................................................................................39
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TABLE 31. ENDPOINT A CONFIGURATION REGISTER (USB_EPA_CFG, 0144H) ........................................................................39
TABLE 32. ENDPOINT A CONTROL REGISTER (USB_EPA_CTL, 0148H)....................................................................................40
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TABLE 33. ENDPOINT A MAX PACKET SIZE REGISTER (USB_EPA_MAXPKT, 0158H) ............................................................40
TABLE 34. ENDPOINT A FIFO CONFIGURATION REGISTER .........................................................................................................40
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TABLE 35. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................41
TABLE 36. DC CHARACTERISTICS ...............................................................................................................................................41
TABLE 37.
TABLE 38.
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TWO-WIRE INTERFACE TIMING .................................................................................................................................42
CRYSTAL CONDITIONS ...............................................................................................................................................43
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TABLE 39. ORDERING INFORMATION ..........................................................................................................................................47
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DVB-T COFDM Demodulator + USB 2.0 v Track ID: JATR-2265-11 Rev. 1.4
RTL2832U
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM ........................................................................................................................................................3
FIGURE 2. PIN ASSIGNMENTS (48-PIN QFN) ................................................................................................................................4
FIGURE 3. IF OR ZERO-IF TUNER INTERFACE.............................................................................................................................10
FIGURE 4. DELAYED AGC .........................................................................................................................................................11
FIGURE 5. TWO-WIRE INTERFACE BETWEEN THE TUNER AND RTL2832U ................................................................................15
FIGURE 6. INTERNAL SWITCHING REGULATOR LAYOUT ............................................................................................................16
FIGURE 7. PID FILTER FUNCTION OF THE RTL2832U................................................................................................................24
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FIGURE 8. TWO-WIRE INTERFACE TIMING DIAGRAM ................................................................................................................42
FIGURE 9. APPLICATION CIRCUITS .............................................................................................................................................44
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DVB-T COFDM Demodulator + USB 2.0 vi Track ID: JATR-2265-11 Rev. 1.4
RTL2832U
Datasheet
1. General Description
The RTL2832U is a high-performance DVB-T COFDM demodulator that supports a USB 2.0 interface.
The RTL2832U complies with NorDig Unified 1.0.3, D-Book 5.0, and EN300 744 (ETSI Specification).
It supports 2K or 8K mode with 6, 7, and 8MHz bandwidth. Modulation parameters, e.g., code rate, and
guard interval, are automatically detected.
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The RTL2832U supports tuners at IF (Intermediate Frequency, 36.125MHz), low-IF (4.57MHz), or
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Zero-IF output using a 28.8MHz crystal. Embedded with an advanced ADC (Analog-to-Digital
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Converter), the RTL2832U features high stability in portable reception.
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The state-of-the-art RTL2832U features Realtek proprietary algorithms (patent-pending), including
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superior channel estimation, co-channel interface rejection, long echo channel reception, and impulse
noise cancellation, and provides an ideal solution for a wide range of applications for PC-TV, such as
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USB dongle and MiniCard/USB, and embedded system via USB interface.
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DVB-T COFDM Demodulator + USB 2.0 1 Track ID: JATR-2265-11 Rev. 1.4
RTL2832U
Datasheet
2. Features
COFDM complying with Nordig Unified Delayed AGC with programmable

1.0.3, D-book 5.0, and ETSI 300-744 Take-Over Point (TOP)
Supports multiple IF frequencies (4.57MHz 7-bit ADC for RF signals level measurement
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or 36.167MHz) and spectrum inversion
Hardware MPEG-2 PID filters
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Supports Zero-IF input
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Infra-red port for remote control and
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Single low-cost crystal for clock generation wake-up, protocols supported are
(±100ppm) Microsoft RC6 protocol
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Automatic transmission mode and guard NEC, Sony, SIRC, RC-5 protocol
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interval detection
Eight general purpose I/O ports
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Impulse noise cancellation circuits
USB 2.0 Interface
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Automatic carrier recovery over a wide
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Supports USB Full/High speed
range offset (±800KHz)
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Configurable vendor information via
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Superior performance with pre/post/long external EEPROM
echo profiles
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Passes USB-IF certification
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Embedded adjacent and co-channel Signal 3.3V external power is required
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interference rejection circuit
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48-pin QFN (6x6 mm2) Green Package
3. System Applications
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Portable DTV device
USB dongle
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MiniCard
RTL2832U
Datasheet
4. Block Diagram
IF to Baseband
Sampling Clock
Timing Error
28.8 MHz LPF
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ADC 90 Resampler Synchroniza FFT
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-tions
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LPF
RF AGC
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AGC Frequency Error
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IF AGC
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Channel Channel
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MPEG 2 PID MPEG 2
USB Decoding & De-Mapper Estimation/
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Filter
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De-Interleaver Equalizer
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Figure 1. Block Diagram
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RTL2832U
Datasheet
5. Pin Assignments
VDDA33
SEGND
UVDDA
GPIO0
HSDM
GNDA
VDDA
VDDA
HSDP
R12K
VCMI
IRRC
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47
45
43
40
48
46
44
42
41
37
39
38
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13
14
15
16
17
18
19
20
21
22
23
24
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FB
VDD1
I2C_SDA
AGC_RF
I2C_SDAT
GPIO6
AGC_IF
I2C_SCLT
VDD3
I2C_SCL
SW_VOUT1
GPIO7
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Figure 2. Pin Assignments (48-Pin QFN)
5.1. Green Package and Version Identification

Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2. The version number is shown
in the location marked ‘V’.
RTL2832U
Datasheet
6. Pin Descriptions
The following signal type codes are used in the tables:
I: Input I/OD: Bi-Directional, Output Open-Drain
O: Output Tri: Tri-State Output
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OD: Open-Drain Output PS: Power Supply
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I/O: Bi-Directional GND: Ground
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Table 1. Pin Descriptions
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Name Pin number Function Type
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Power and Ground
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VDD1 12, 20, 28, 34 Digital Core Power Supplies PS (1.2V)
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VDD3 14, 33 Digital I/O Power Supplies PS (3.3V)
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VDDA33 43 Analog Front End Power Supply PS (3.3V)
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VDDA 44, 47 Analog Front End Power Supplies PS (1.2V)
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GNDA 3, 45 Analog Front End Ground GND
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Oscillator and PLL
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XI 11 Crystal Oscillator Input I
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XO 10 Crystal Oscillator Output O
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VDDPLL 7 PLL Power Supply PS (1.2V)
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GNDPLL 8 PLL Ground GND
TP_CKO 9 ADC Test Pin for Clock Input I/O
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VIP 1 Differential Analog Input – Positive (I Path) I
VIN 2 Differential Analog Input – Negative (I Path) I
VQP 4 Differential Analog Input – Positive (Q Path) I
VQN 5 Differential Analog Input – negative (Q Path) I
R12K 48 Connects a 10k ohm Resistor to Ground I
VCMI 46 Reference Voltage for ADC AC-Coupling I
RTL2832U
Datasheet
Name Pin number Function Type
VINR 6 Low Speed 7-bit ADC Single-Ended Input I
USB Interface
HSDP 40 USB D+ Signal I/O
HSDM 41 USB D- Signal I/O
UVDDA 42 USB 1.2V Analog Power Supply PS (1.2V)
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SEGND 39 Reference Ground GND
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Host Interface
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I2C_SCL 18 I2C Interface Clock Output Pin (5 Voltage Tolerance) OD
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I2C_SDA 19 I2C Interface Bi-Directional Data Pin (5 Voltage Tolerance) I/OD
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I2C_SCLT 16 Output SCLK Signal (5 Voltage Tolerance) for Tuner Control OD
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I2C_SDAT 17 Output SDAT Signal (5 Voltage Tolerance) for Tuner Control I/OD
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AGC_IF 13 Control Signal for IF AGC (5 Voltage Tolerance) OD
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AGC_RF 15 Control Signal for RF AGC (5 Voltage Tolerance) OD
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M_ERR 35 MPEG Error Output O
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GPIO Interface and IR
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IRRC 38 IR Signal Input I
GPIO[0] 37 General Purpose I/O Pin-0 Tri
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GPIO[5]
GPIO[6]
29
22
General Purpose I/O Pin-5
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4L Tri
Tri
GPIO[7]
ENSWREG
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Internal 3.3V to 1.2V Switching Regulator
0V: Turn off switching regulator

Tri
I
3.3V: Turn on switching regulator (Tie high internally)
SW_VDD3 26, 25 3.3V Power Input PS (3.3V)
REG_OUT 24 1.2V Power Output O
FB 23 Regulated Feedback Voltage I
RTL2832U
Datasheet
7. Functional Description
The block diagram of the RTL2832U DVB-T demodulator is shown in Figure 1, page 3. The RTL2832U
accepts IF or Zero IF input signals with the analog signal sampled by the internal ADC. The sampled data
stream is then processed by OFDM demodulation. After decoding by an on-chip FEC (Viterbi and
Reed-Solomon decoder) the USB 2.0 interface outputs packets with transport stream data.
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A detailed description of each block is given in this section.
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7.1. Analog-to-Digital Conversion (ADC)
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The internal A/D converter can accept tuner output with various bandwidths (6, 7, 8MHz), different IF
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frequencies (4.57M or 36.167M,), Zero IF (I & Q channel) input and can perform spectrum reversion.
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Using a sampling clock generated by the internal PLL with a 28.8MHz clock source, the RTL2832U
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demodulates the received TV signal.
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7.2. Automatic Gain Control (AGC)
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The AGC circuit is used to adjust received signal strength to a moderate level for the ADC. This module
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supports two output paths, and both are sigma-delta modulated signals. The output signals need additional
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RC LPFs (Low-Pass Filters) before feeding to IF and RF VGA in the tuner The delayed AGC algorithm
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is described in section 8.1 Automatic Gain Control (AGC), page 11.
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7.3. Digital Down Conversion
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The RTL2832U uses IF or Zero-IF sampling to process received signals. The Digital Down Conversion
(DDC) circuit converts the sampled IF signal to a complex base-band signal for further processing. The
down conversion frequency and low-pass filter can be programmed according to different IF frequency,
sampling rates, and signal bandwidth.
RTL2832U
Datasheet
7.4. Resampler
The Resampler circuit changes the received signal from a fixed ADC sampling rate to an Orthogonal
Frequency Division Multiplexing (OFDM) sampling rate according to the signal bandwidth. The
conversion ratio can be programmed via a register setting.
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7.5. Guard Interval Removal
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In time domain modulation, there is a guard interval inserted between two Orthogonal Frequency
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Division Multiplexing (OFDM) signals. It is necessary to remove the guard interval before Fast Fourier
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Transform (FFT) processing. This module is used to moderate the OFDM symbol boundary for FFT
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according to the results of synchronization.
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7.6. Fast Fourier Transform (FFT)
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The Fast Fourier Transform (FFT) circuit converts a received time domain signal to a frequency domain
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signal. Based on the ETSI 300-744 definition, FFT output contains continuous pilots, scattered pilots,
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Transmission Parameter Signal (TPS), and data signal. These signals can be used for synchronization,
channel estimation, and data decision in further processing.
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7.7. Synchronization
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The RTL2832U can measure and compensate for a large range of sampling frequency offsets and carrier
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frequency offsets before making a data decision. A moderate symbol boundary is utilized to avoid Inter-
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Symbol Interference (ISI).
RTL2832U
Datasheet
7.8. Channel Estimation

A channel estimation circuit is used to estimate the channel condition of received signals. The estimated
channel response can be used for equalization, and is updated symbol by symbol to support mobile
channel variations.
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7.9. Transmission Parameter Signal Decoder
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This module is used to decode and determine Transmission Parameter Signal (TPS) bits. The TPS carriers
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contain parameters for demodulation. These parameters are protected by Bose, Ray-Chaudhuri,
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Hocquenghem (BCH) encoding. After decoding, the RTL2832U demodulator further processes the
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decoded information. Parameters such as transmission mode, guard interval value, code rate etc, can be
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pre-set by registers to overwrite the result of TPS decoding.
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7.10. Equalization
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To handle various channel conditions, the equalization circuit compensates for the signal degradation
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caused by different multi-path channel profiles. The data bit is detected based on the equalization output.
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7.11. De-Interleaver, FEC Decoder, and Descrambler
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In accordance with ETSI 300-744, the RTL2832U uses a de-interleaver to re-order the decision data bit to
the correct sequence. The Forward Error Correction (FEC) decoder circuit detects and corrects error bits
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Stream (TS) sequence.
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in the received sequence. The descrambler recovers the output of the decoder to a standard Transport
RTL2832U
Datasheet
8. Tuner Interface
There are three interfaces (AGC, ADC input, two-wire serial interface) between the tuner and the
demodulator.
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Figure 3. IF or Zero-IF Tuner Interface
RTL2832U
Datasheet
8.1. Automatic Gain Control (AGC)

In the RTL2832U, the RF_AGC and IF_AGC pins control the Radio Frequency (RF) and Intermediate
Frequency (IF) VGA gain of the tuner. In some applications, the RTL2832U only controls IF VGA, and
the tuner controls RF VGA. In some tuners, only the RF AGC is needed. The RTL2832U uses delayed
AGC to control RF and IF AGC. Gain distribution for RF and IF VGA is adjusted by registers ‘vtop’ and
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‘krf’. The delayed AGC method is shown in Figure 4. RTL2832U has three vtop and four krf register
values to be programmed by user.
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When the input power of the RF tuner is weak, RF VGA gain is kept to the maximum for better tuner
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performance. When the input power is strong enough, RF VGA starts to decrease its gain to avoid the
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non-linearity effect of the following block (IF VGA). The point where RF VGA starts to decrease gain
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value is vtop (the ‘take-over point’). The ratio for RF VGA gain decrease is set by register krf. The
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optimal values of registers vtop and krf depend on the tuner used.
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Pins RF_AGC and IF_AGC are sigma-delta DAC output. An external Resistor/Capacitor (RC) low-pass
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filter and pull-high resister should be placed on the PCB board to generate a quasi-DC control voltage to
the tuner as shown in Figure 3, page 10.
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Figure 4. Delayed AGC
RTL2832U
Datasheet
8.1.1. Register Name: loop_gain

Analog Automatic Gain Control (AAGC) loop gain is set by register loop_gain2<3:0> and
loop_gain2<4>. Register loop_gain2 can be set to 0~26. The value depends on the tuner. The
recommended value is 20 (dec). A larger loop_gain value would get a slower AAGC locking time, but
more stable AAGC control voltage. There are another loop_gain1 and loop_gain3 for special cases: use
loop_gain1 for aagc unlock, and use loop_gain3 for existing interference.
k
Table 2. AAGC Register Table
e
Offset Bits Default
Register Name Page RW Description
t
{LSB, MSB} Used (Hex)
l
Inverse the AGC_RF Sigma-Delta Pin
polar_rf_agc 0 0x0E [1] RW 0
0: Normal 1: Inverse
a L
Inverse the AGC_IF Sigma-Delta Pin
polar_if_agc 0 0x0E [0] RW 0
e IA
0: Normal 1: Inverse
loop_gain2<3:0> 1 0x04 [4:1] RW 0 AGC Loop Gain (Bit0~Bit3) for AAGC Lock
T
R
Hold AAGC Value (Open AAGC Loop)
N
aagc_hold 1 0x04 [5] RW 0
0: Disable 1: Enable
E
Enable RF AGC Loop
ID
en_rf_agc 1 0x04 [6] RW 1
1: Enable 0: Disable
F
Enable IF AGC Loop
en_if_agc 1 0x04 [7] RW 1
N
1: Enable 0: Disable
O
loop_gain2<4> 1 0x05 [7] RW 1 AAGC Loop Gain (Bit4) for AAGC Lock
C
loop_gain1 1 0xC7 [5:1] RW C AAGC Loop Gain for AAGC Unlock
loop_gain3
vtop1
1
1
0xC8
0x06
[4:0]
[5:0]
RW
RW
4 L 1A
10
AAGC Loop Gain for Existing Interference
u(6,5f) Set Take-Over Point1
vtop2 1 0xC9
r [5:0] RW
V 30 u(6,5f) Set Take-Over Point2
vtop3
krf1
krf2
1
1
0xCA
0xCB
0x07
fo [5:0]
[7:0]
[7:0]
RW
RW
RW
28
F
u(6,5f) Set Take-Over Point3
u(8,4f) Set RF AGC Gain Degrade Ratio1
u(8,4f) Set RF AGC Gain Degrade Ratio2
krf3 1 0xCD [7:0] RW 20 u(8,4f) Set RF AGC Gain Degrade Ratio3
krf4 1 0xCE [7:0] RW 30 u(8,4f) Set RF AGC Gain Degrade Ratio4
if_agc_min 1 0x08 [7:0] RW 80 s(8,7f) Set IF AAGC Minimum Gain
RTL2832U
Datasheet
Offset Bits Default

{LSB, MSB} Used (Hex)
if_agc_max 1 0x09 [7:0] RW 7F s(8,7f) Set IF AAGC Maximum Gain
rf_agc_min 1 0x0A [7:0] RW 80 s(8,7f) Set RF AAGC Minimum Gain
rf_agc_max 1 0x0B [7:0] RW 7F s(8,7f) Set RF AAGC Maximum Gain
if_agc_val 3 {59,5A} [13:0] R - s(14, 13f) IF AAGC Value
k
rf_agc_val 3 {5B,5C} [13:0] R - s(14, 13f) RF AAGC Value
e
aagc_lock 3 0x50 [0] R - AAGC Lock
l t
8.1.2. Register Name: if_agc_min/if_agc_max/rf_agc_min/rf_agc_max
a L
Format: s(8,7f)
e IA
These registers limit the minimum and maximum value of RF/IF AGC. They are in 8-bit two’s
complement format. The maximum value 127 (dec) means maximum output voltage.
T
R
For example, if we want to limit RF minimum/maximum, AGC output voltage would be 10%/90% of
N
pull-high voltage.
ID E
rf_agc_min=floor (10%*255-128)=-103 (dec)
rf_agc_max=floor (90%*255-128)=101 (dec)
N F
O
8.1.3. Register Name: Vtop
C
Format: u(6,6f)
4 L
The take-over point of RF VGA is set by register vtop. There are two special cases shown below. The
optimal value depends on the tuner.
r V
fo
vtop=0 (dec) Æ RF gain is always set on maximum value
vtop=63 (dec)Æ RF gain does not delay
For example, if we want to degrade RF VGA gain when IF VGA control voltage is smaller than 0.5*Vdd:
vtop=floor (63*0.5)=31 (dec)
RTL2832U
Datasheet
8.1.4. Register Name: Krf

Format: u(6,2f)
The gain degrade ratio between the RF and IF AGC when input power exceeds the RF take-over point is
set by register Krf. A larger krf means the RF Gain degrade ratio is larger. This means an equal gain
degrade ratio between the RF and the IF AGC. If we want RF gain to degrade quickly when input power
is larger than the take-over point, krf should be set to a larger value. If only IF AGC is controlled by the
k
RTL2832U, registers vtop and krf are not used.
t e
8.1.5. Register Name: if_agc_val/rf_agc_val
l
Format: s(14,13f)
a L
The RF AAGC value and IF AAGC value are read from registers if_agc_val/rf_agc_val. They are in
e IA
14-bit two’s complement format. The minimum value is –8192 and maximum value is 8191. When
rf/if_agc_val is set to the maximum value, it means the RF/IF AGC pin output is at the maximum control
T
R
voltage. The real RF input power can be mapped from if_agc_val/rf_agc_val. The mapping can be to a
N
table or an equation. Note that different vtop and krf settings map different tables and equations.
8.2. ADC Input (Tuner Output)

ID E
N F
Tuner IF or Zero IF output is AC coupled to the RTL2832U differential ADC input. An external AC
O
coupling capacitor is required. The schematic is shown in Figure 3, page 10.
C V 4 L
fo r
RTL2832U
Datasheet
8.3. Two-Wire Interface Between the Tuner and the RTL2832U
t e k
a l L
e IA
Figure 5. Two-Wire Interface between the Tuner and RTL2832U
T
R E N
The RTL2832U supports an I2C repeater to prevent tuner interference from the two-wire interface. In
ID
normal situations the tuner cannot hear any command sent via the two-wire interface. We need to turn on
the I2C repeater (set register IIC_repeat=1) in order to send a command to the tuner. The command will
F
be heard by the tuner and the RTL2832U at the same time. The Tuner and RTL2832U can distinguish the
N
origin of the command by the I2C address. On the PCB, pin I2C_SDAT/I2C_SCLT should be connected
O
to pull-high resisters (10k ohm) to pull-high the two-wire bus.
C
Table 3. I2C Repeater Register Table
4L
Register Name Page Offset{MSB,LSB} Bits Used RW Default (Hex) Description
I2C Repeater for Tuner

IIC_repeat 1 0x01
r V [3] RW 0 1: Enable
fo
Note 1: IIC_repeat should be set to 1 before sending a command to the tuner.
Note2: IIC_repeat is not automatically set to 0 after receiving a ‘STOP’ command.
0: Disable
RTL2832U
Datasheet
8.4. RTL2832U Internal Switching Regulator

The RTL2832U integrates a switching regulator with input voltage 3.3V to output voltage 1.2V. Figure 6
shows the application circuit.
The ENSWREG pin default power is 3.3V. Applying 0V turns off the switching regulator.
t e k
a l L
R e E N T IA
F ID
O N
C L
Figure 6. Internal Switching Regulator Layout
V 4
fo r
RTL2832U
Datasheet
9. Register Descriptions (General)
9.1. Analog to Digital Converter (ADC)

The RTL2832U can receive IF or Zero-IF signals from the tuner. The following registers set IF or
Zero-IF mode.
k
IF signal mode
e
• AD_EN_reg1 set 1
l t
• en_bbin set 0
a L
Zero-IF signal mode
e IA
T
R
N
• en_bbin set 1
E
Table 4. ADC Registers
ID
Offset Default
Register Name Page Bits Used RW Description
F
{MSB,LSB} (Hex)
N
1: Enable ADC_Q
AD_EN_reg1 0 0x08 [6] RW 0
O
0: Disable ADC_Q
C
1: Enable ADC_I
AD_EN_reg 0 0x08 [7] RW 0
4L
0: Disable ADC_I
1: Enable Zero-IF input
V
en_bbin 1 0xB1 [0] RW 1
0: Disable Zero-IF input
opt_adc_iq 0 0x06
fo r
[5:4] RW 0
0: Default ADC_I, ADC_Q datapath
1: Exchange ADC_I, ADC_Q datapath
RTL2832U
Datasheet
9.2. DC Cancellation and IQ Compensation

In Zero-IF mode, the output signal of the tuner often has DC bias and IQ mismatch issues. The
RTL2832U will compensate for these effects. DC cancellation and IQ compensation blocks are default
enabled when en_bbin is set to 1.
Table 5. DC Cancellation Registers
k
Register Offset Default
Page Bits Used RW Description
e
Name {MSB,LSB} (Hex)
t
1: Enable DC estimation and cancellation
en_dc_est 1 0xB1 [1] RW 1
l
0: Disable DC estimation and cancellation
1: Enable IQ compensation
a
en_iq_comp 1 0xB1 [3] RW 1
L
0: Disable IQ compensation
e IA
1: Enable IQ estimation for compensation
en_iq_est 1 0xB1 [4] RW 1
0: Disable IQ estimation for compensation
T
R
Est_kq 1 {0x66,0x67} [11:0] R - Estimated Gain for IQ Gain Mismatch, u(12,11f)
N
Est_sin 1 {0x68,0x69} [11:0] R - Estimated Sin for IQ θ Mismatch, s(12,10f)
ID E
N F
C O 4 L
r V
fo
RTL2832U
Datasheet
9.3. Digital Down Conversion (DDC)

The Analog-to-Digital Converter (ADC) block sub-samples Intermediate Frequency (IF) signals, and a
Digital Down Conversion (DDC) block converts the IF to baseband signals.
In normal cases, the tuner is high-side mixing and the spectrum is inversed. The demodulator requires an
inverse spectrum in the DDC (register spec_inv). In the RTL2832U there is an adjacent channel canceller
k
that is enabled or disabled by register en_aci. The initial IF frequency should be set by register
e
pset_iffreq. This register setting depends on the crystal frequency. The equation of pset_iffreq is shown
below:
l t
f IF _ D
pset _ iffreq = − floor ( × 4194304)
a
f crystal
L
e IA
Where:
fIF_D: Intermediate Frequency (IF) after sub-sampling
T
R
fcrystal: Crystal frequency
N
Examples:
E
•
ID
fIF = 4.57M, fADC = 28.8M,
pset_iffreq = -665554 Æ 2^22–665554 = 3528750 (two’s complement) = 0x35D82E
F
• fIF = 36.167M, fADC = 28.8M, fIF_D = 36.167-28.8 = 7.367,
N
pset_iffreq = -1072897 Æ 2^22–1072897 = 3121407 (two’s complement) = 0x2FA0FF
O
• fIF = 36.125M, fADC = 28.8M, fIF_D = 36.167-28.8 = 7.367,
C
pset_iffreq = -1066780 Æ 2^22–1066780 = 3127524 (two’s complement) = 0x2FB8E4
• fIF = 0M, fADC = 28.8M,
4 L
pset_iffreq = 0x0
r V
fo
• DAB Mode,
pset_iffreq = -1066988 = 3127316 (two’s complement) = 0x2FB814
RTL2832U
Datasheet
Table 6. Digital Down Conversion (DDC)
Register Offset Default

Page Bits Used RW Description
Name {MSB,LSB} (Hex)
1: Spectrum inversion
Spec_inv 1 0x15 [0] RW 0
0: Spectrum non-inversion
1: Enable adjacent channel rejection

En_aci 1 0x15 [1] RW 1
k
0: Disable adjacent channel rejection
pset_iffreq 1 {0x19,0x1B} [21:0] RW - Set IF Frequency
9.4. Resampler
l t e
a L
As the ADC sampling clock is larger than the symbol ratio, there is a re-sampler to convert sampling data
e IA
to symbol ratio. The ratio can be set via register ‘rsamp_ratio’. The rsamp_ratio is related to signal
bandwidth and crystal frequency. The equation of rsamp_ratio is shown below:
T
R N
f crystal
rsamp _ ratio = floor ( × 4194304)
E
f symbol
ID
Where:
F
fcrystal = crystal frequency
N
fsymbol = symbol ratio of different bandwidths
O
• BW: 8MHz Æ fsymbol = 64/7 MHz, fcrystal = 28.8MHz
C
rsamp_ratio = 13212057 (dec) = 0x C99999
• BW: 7MHz Æ fsymbol = 8 MHz, fcrystal = 28.8MHz
4 L
•
rsamp_ratio = 15099494 (dec) = 0x E66666
BW: 6MHz Æ fsymbol = 48/7 MHz, fcrystal = 28.8MHz

r V
•
rsamp_ratio = 17616076 (dec) = 0x 10CCCC
DAB mode
rsamp_ratio = 14745600 (dec) = 0x E10000
fo
Table 7. Resampler
rsamp_ratio 1 {0x9F, 0xA2} [27:2] RW C99999 Resampler Ratio
RTL2832U
Datasheet
9.5. Co-Channel Interference Rejection

Narrow band in-band interference is detected and rejected by Co-Channel Interference (CCI) rejection.
Register en_cci enables or disables Co-Channel Interference Rejection.
Table 8. Co-Channel Interference Rejection
k
1: Enable CCI cancellation
e
En_cci 1 0x40 [1] RW 1
0: Disable CCI cancellation
9.6. Impulse Noise Cancellation
a l t L
e IA
Impulse noise can be cancelled by a unique Realtek patented algorithm. Register inc_det_cnt monitors
how many times impulse noise occur. Register inc_det_cnt_rst resets the counter inc_det_cnt.
T
R
Table 9. Impulse Noise Cancellation
E N
Offset Bits Default
{MSB,LSB} Used (Hex)
ID
1: Enable impulse noise cancellation
F
en_inc 1 0x5D [0] RW 1
0: Disable impulse noise cancellation
N
Reset for inc_det_cnt
O
inc_det_cnt_rst 1 0x5E [6] RW 0 1: Reset
C
0: Normal
inc_det_cnt 3 {0x28, 0x29} [8:0] R
4 L - Number of Impulse Noise Events
r V
fo
RTL2832U
Datasheet
9.7. Digital Automatic Gain Control (DAGC)

The RTL2832U features Digital Automatic Gain Control (DAGC) to adjust optimal signal levels. DAGC
can be enabled or disabled via register en_dagc. The DAGC voltage gain is read from register dagc_val.
Linear voltage gain of DAGC=dagc_val/16.
k
Table 10. DAGC Registers
Offset Bits Default
e
t
en_dagc 1 0x11 [0] RW 1 1: Enable DAGC 0: Disable DAGC
l
dagc_val 3 0x05 [7:0] R - Gain of DAGC
e a IA L
9.8. FFT Mode Detection
T
R
The Fast Fourier Transform (FFT) mode and the Guard Interval are automatically detected by an auto
N
mode detection algorithm. Auto mode detection can also be enabled or disabled by register. When auto
E
mode detection is disabled, the correct FFT mode and Guard Interval can be set manually by register
ID
pset_mode_gi.
F
Table 11. FTT Mode Detection
N
Offset Bits Default
O
0: Enable auto mode detection
C
dis_auto_scan 1 0x5F [0] RW 0
1: Disable auto mode detection
4 L Pre-Set Guard Interval and FFT Mode
pset_mode_gi 1 0x5F
r
[3:1] RW
V 3
0: 2k, 1/32GI
2: 2k, 1/8GI
1: 2k, 1/16GI
3: 2k, ¼
fo 4: 8k, 1/32
6: 8k, 1/8
Mode and GI Index
0: 2k, 1/32GI
5: 8k, 1/16
7: 8k, ¼
1: 2k, 1/16GI
mode_gi_idx 3 0x51 [2:0] R - 2: 2k, 1/8GI 3: 2k, ¼GI
4: 8k, 1/32GI 5: 8k, 1/16GI
6: 8k, 1/8GI 7: 8k, ¼GI
RTL2832U
Datasheet
9.9. Timing Recovery/Carrier Recovery

The unique synchronization algorithm in the RTL2832U is capable of dealing with tough receiving
conditions. The result of sampling frequency offset can be read from the register sfreq_off, which is
denoted in ppm. The estimated carrier frequency offset can be read from register cfreq_off, which is
denoted in carrier spacing. Carrier spacing depends on signal bandwidth and transmission mode. An
k
example of the computation is shown below:
For 8M bandwidth with 8K mode signal, the carrier spacing is approximately 1.116 KHz. If the sfreq_off
e
= 0x200 (two’s complement)=512 (dec), cfreq_off=0xFB2E (two’s complement)=64302 (dec), then:
l t
• Sampling frequency offset = sfreq_off / 224*1000000=512/16777216*1000000=30.5176ppm
• Carrier frequency offset = cfreq_off / 27*carrier spacing=64302/128*1.116KHz=560.63KHz
a L
In addition, to supporting different crystal frequency sources, the register cfreq_off_ratio must be set
e IA
according to the sampling frequency. The cfreq_off_ratio equation is shown below:
T
R
f FFT
cfreq _ off _ ratio = − floor ( × 1048576)
fs
E N
Where:
ID
fFFT: FFT sampling rate
fs: ADC sampling frequency
F
E.g., fS = 28.8M, fFFT = 64/7M,
N
cfrq_off_ratio = -floor (64/7/28.8*1048576) = -332881 (dec) = 0xAEBAF (two’s complement)
O
• 8M mode, fFFT = 64/7M: cfrq_off_ratio = 715695 (dec) = 0xAEBAF
C L
• 7M mode, fFFT = 8M: cfrq_off_ratio = 757305 (dec) = 0xB8E39
•
4
6M mode, fFFT = 48/7M: cfrq_off_ratio = 798916 (dec) = 0xC30C4
V
Carrier Spacing
•
fo r
8M mode, fFFT = 64/7M: carrier spacing (8k) = fFFT / 8192 = 1.116071Hz
carrier spacing (2k) = fFFT / 2048 = 4.464285Hz
RTL2832U
Datasheet
Table 12. Timing Recovery/Carrier Recovery
Register Name Page Offset Bit RW Type Default Description

cfreq_off_ratio 1 {0x9D, 0x9F} [23:4] RW s(20, 31f) AEBAF Set Carrier Frequency Offset Ratio
cfreq_off 3 {0x5F, 0x61} [17:0] R s(18,7f) - Estimated Carrier Frequency Offset
sfreq_off 3 {0x18, 0x19} [13:0] R s(14,24f) - Estimated Sampling Frequency Offset
e k
9.10. Crystal
l t
The RTL2832U has superior timing offset tracking ability, allowing the use of a low-cost crystal as clock
a
source. The timing offset tolerance is ±100 ppm. The RTL2832U also supports an oscillator (oscillator
L
output should be connected to the XI pin).
e IA
Note: For different crystal frequencies, registers such as rsamp_ratio, cfreq_off_ratio, and pset_iffreq
need to be set accordingly.
T
R
9.11. PID Filter
F ID E N
A PID (Packet Identifier) filtering capability allows the reduction of the transport stream at the output of
the demodulator. There are 32 PIDs that can be selected within the received multiplex. The following
N
block diagram shows the PID filter functions, and the default register setting will let all PID transport
O
streams pass through.
C V 4 L
fo r
Figure 7. PID Filter Function of the RTL2832U
RTL2832U
Datasheet
Table 13. PID Filter
Register Name Page Offset Bit RW Default Description

Set 0 to Reject All Error Packets

err_pass 0 0x61 [5] RW 1
Set 1 to Pass All Error Packets
Set 0 to Pass Matched PID

mode_PID 0 0x61 [6] RW 1
k
Set 1 to Reject Matched PID
Set 1 to Enable Output of PID Filter
e
enable_PID 0 0x61 [7] RW 1
Set 0 No Output
l t
Enable (1) and Disable (0) Individual PID
en_PID[7:0] 0 0x62 [7:0] RW 0
Filter 0~7
a
L
en_PID[15:8] 0 0x63 [7:0] RW 0
e
Filter 8~15
IA
en_PID[23:16] 0 0x64 [7:0] RW 0
T
R
Filter 16~23
N
en_PID[31:24] 0 0x65 [7:0] RW 0
E
Filter 24~31
ID
PID0 0 {0x66, 0x67} [12:0] RW 00 PID Value for PID Filter #0
F
PID2 0 {0x6A, 0x6B} [12:0] RW 06 PID Value for PID Filter #2
N
PID3 0 {0x6C, 0x6D} [12:0] RW 11 PID Value for PID Filter #3
O
PID4 0 {0x6E, 0x6F} [12:0] RW 12 PID Value for PID Filter #4
C L
PID6
PID7
0
0
{0x72, 0x73}
{0x74, 0x75}
[12:0]
[12:0]
RW
V
RW 4 14
15
PID Value for PID Filter #6
PID8
PID9
PID10
0
0
{0x76, 0x77}
{0x78, 0x79}
{0x7A, 0x7B}fo r
[12:0]
[12:0]
[12:0]
RW
RW
RW
16
17
18
PID12 0 {0x7E, 0x7F} [12:0] RW 1A PID Value for PID Filter #12
PID13 0 {0x80, 0x81} [12:0] RW 1B PID Value for PID Filter #13
PID14 0 {0x82, 0x83} [12:0] RW 1C PID Value for PID Filter #14
RTL2832U
Datasheet
Register Name Page Offset Bit RW Default Description

PID15 0 {0x84, 0x85} [12:0] RW 1D PID Value for PID Filter #15
PID16 0 {0x86, 0x87} [12:0] RW 1E PID Value for PID Filter #16
PID17 0 {0x88, 0x89} [12:0] RW 1F PID Value for PID Filter #17
k
e
PID20 0 {0x8E, 0x8F} [12:0] RW 22 PID Value for PID Filter #20
t
l
a
L
e IA
T
R
E N
PID28 0 {0x9E, 0x9F} [12:0] RW 2A PID Value for PID Filter #28
ID
PID29 0 {0xA0, 0xA1} [12:0] RW 2B PID Value for PID Filter #29
PID30 0 {0xA2, 0xA3} [12:0] RW 2C PID Value for PID Filter #30
F
PID31 0 {0xA4, 0xA5} [12:0] RW 2D PID Value for PID Filter #31
O N
C V 4 L
fo r
RTL2832U
Datasheet
10. Register Descriptions (8051 System)

The address is defined by offset value with base address 0x3000.
Table 14. System Register Descriptions
Address Offset Access Name Description
0000h RW DEMOD_CTL Control Register for DVB-T Demodulator
k
GPIO Registers
e
0001h RW GPO Output Value of General Purpose I/O
t
0002h R GPI Input Value of General Purpose I/O
l
0003h RW GPOE Output Enable of General Purpose I/O
a
0004h RW GPD Direction Control for General Purpose I/O
L
0005h RW SYSINTE System Interrupt Enable Register
e IA
0006h RW SYSINTS System Interrupt Status Register
T
R
0007h RW GP_CFG0 PAD Configuration for GPIO0-GPIO3
N
0008h RW GP_CFG1 PAD Configuration for GPIO4
E
0009h RW SYSINTE_1 System Interrupt Enable Register GPIO5~GPIO7
ID
000Ah RW SYSINTS_1 System Interrupt Status Register GPIO5~GPIO7
F
000Bh RW DEMOD_CTL_1 Enable IR Remote Wakeup & Low Current XTL Mode
when Suspended
N
000Ch RW IR_SUSPEND IR Sensor Discontinuous Turned ON. Controlled by
O
GPIO3
C
IrDA Registers
FC00~FC7F - IR_RX_BUFF
4 LNormal Mode: The 128-byte buffer is for receiving RLC
r V encoded waveform data

Suspend Mode: Used to save original power key RLC
FD00h
FD01h
-
-
IR_RX_IE
IR_RX_IF
fo encoded data for comparing with received waveform data
Interrupt Enable Register. Not Available in Suspend Mode
Interrupt Flag Register. Not Available in Suspend Mode
FD02h - IR_RX_CTRL IR Receive Control Register
FD03h - IR_RX_CONFIG IR Receive Configure Register
FD04h - IR_MAX_DURATION0 Max Time Duration Configure Register
RTL2832U
Datasheet
Address Offset Access Name Description
FD05h - IR_MAX_DURATION1 Max Time Duration Configuration Register
FD06h - IR_IDLE_LEN0 Idle Length Configuration Register
FD07h - IR_IDLE_LEN1 Idle Length Configuration Register
FD08h - IR_GLITCH_LEN Glitch Length Configuration Register
FD09h - IR_RX_BUFFER_CTRL IR RX Buffer Control Register
k
FD0Ah - IR_RX_BUFFER_DATA IR Buffer Data for MCU Access
e
FD0Bh - IR_RX_BC Frame RX Byte Counter Register
t
FD0Ch - IR_RX_CLK Frame RX Byte Counter Register. Not Available in
l
Suspend
a
FD0Dh - IR_RX_C_COUNT_L IR Received Carrier Count Register
L
FD0Eh - IR_RX_C_COUNT_H IR Received Carrier Count Register
e IA
FD0Fh - - Reserved
FD10h - IR_SUSPEND_CTRL Suspend Control Register
T
R
FD11h - IR_Err_Tolerance_CTRL IR Error Tolerance Control Register
E N
FD12h - IR_UNIT_LEN 1T Unit Length Register
ID
FD13h - IR_ERR_Tolerance_LEN High Level Unit Negative Tolerance Length Register
FD14h - IR_MAX_H_Tolerance_LEN High Level Max Tolerance Length Register
F
FD15h - IR_MAX_L_Tolerance_LEN Low Level Max Tolerance Length Register
N
FD16h - IR_MASK_CTRL Mask Control Register
O
FD17h - IR_MASK_DATA Mask Data Register
C
FD18h - IR_RESUME_MASK_ADDR IR Resume Mask Address Register
FD19h -
4 L
IR_RESUME_MASK_T_LEN IR Resume Mask Length Register
0040h RW I2CCR
r V
I2C Master Registers
I2C Clock Register
0044h
0048h
004Ch
RW
RW
RW
I2CMCR
I2CMSTR
I2CMSR
fo I2C Master Control Register
I2C Master SCL Timing Register
I2C Master Status Register
0050h RW I2CMFR I2C Master FIFO Register.
RTL2832U
Datasheet
10.1. Demodulator Control Register (DEMOD_CTL, 0000h)

Table 15. Demodulator Control Register (DEMOD_CTL, 0000h)
Bits Access Reset Description
7 RW 0 Demodulator PLL Enable. Set to 1 to enable demodulator PLL, and to 0 to disable
6 RW 0 Demodulator ADC_I Enable. Set to 1 to enable ADC operation and to 0 to disable
k
5 RW 1 Demodulator Hardware Reset. Set to 0 to activate hardware reset, and to 1 to release reset
e
4 - - Reserved
t
3 RW 0 Demodulator ADC_Q Enable. Set 1 to enable ADC operation and 0 to disable
l
2:0 - - Reserved
e a IA L
10.2. GPIO Related Registers (0001h~0008h)
T
R
The following registers are used to control GPIO 0~7. The default functions of these 8 pins are:
E N
1. GPIO [0]: Output for VDD1 power control. Default value 1 to turn off power.
ID
2. GPIO [1]: Input for power-on latch to select clock source. Input value depends on the crystal on
F
board; default 0 for 28.8MHz.
N
3. GPIO [2]: Input for external I2C mode, internal pull-down. This pin is used for LED control after
O
8051 firmware runs, and will set to 0 to turn off the LED, or 1 to turn it on.
C L
4. GPIO [3]: Input for USB remote wakeup. Input value 0 is to activate remote wakeup.
4
Output for tuner power control. Default value 1 to turn off power.
V
5. GPIO [4]:
6. GPIO [5]:
fo r
Output for antenna power control. Default value 0 to turn off power.
Input for power-on latch to select clock source, input value depends on the crystal on
board. Default 0 for 28.8MHz.
7. GPIO [6]: Reserved.
8. GPIO [7]: Reserved.
RTL2832U
Datasheet
10.2.1. GPIO Output Value Register (GPO, 0001h)

Table 16. GPIO Output Value Register (GPO, 0001h)
7 RW 0 Output Value of GPIO 7. Valid only when GPIO 7 is defined as output pin.
k
e
t
l
a
L
e IA
10.2.2. GPIO Input Value Register (GPI, 0002h)
T
R N
Table 17. GPIO Input Value Register (GPI, 0002h)
E
ID
7 R - Input Value of GPIO 7. Valid only when GPIO 7 is defined as input pin.
F
N
O
C L
0
R
R
-
V 4
Input Value of GPIO 1. Valid only when GPIO 1 is defined as input pin.
Input Value of GPIO 0. Valid only when GPIO 0 is defined as input pin.
fo r
RTL2832U
Datasheet
10.2.3. GPIO Output Enable Register (GPOE, 0003h)

Table 18. GPIO Output Enable Register (GPOE, 0003h)
Output Enable for GPIO 7. Valid only when GPIO 7 is defined as output pin.
7 RW 0
1: Output enable 0: Output disable (tri-state)
k
6 RW 0
e
5 RW 0
l t
4 RW 1
a
L
3 RW 1
e IA
2 RW 0
T
R
N
1 RW 0
E
ID
0 RW 1
10.2.4.
N F
GPIO Direction Control Register (GPD, 0004h)
C O
Table 19. GPIO Direction Control Register (GPD, 0004h)
Direction Control of GPIO 7
4 L
V
7 RW 0
1: Input 0: Output
5
RW
RW
0
0
1: Input
fo r

0: Output
1: Input 0: Output
4 RW 0
1: Input 0: Output
3 RW 1
1: Input 0: Output
RTL2832U
Datasheet

2 RW 1
1: Input 0: Output
1 RW 1
1: Input 0: Output
0 RW 0
k
1: Input 0: Output
t e
10.2.5. PAD Configuration Register for GPIO0~3 (GP_CFG0, 0007h)
l
Table 20. PAD Configuration Register for GPIO0~3 (GP_CFG0, 0007h)
a
L
7:6 RW 2h GP_PAD3. PAD configuration as internal pull-up or pull-down for GPIO3.
e IA
T
R
N
10.2.6.
ID E
PAD Configuration Register for GPIO4 (GP_CFG1, 0008h)
F
Table 21. PAD Configuration Register for GPIO4 (GP_CFG1, 0008h)
N
O
C
3:2 RW 1h
4 L
GP_PAD5. PAD configuration as internal pull-up or pull-down for GPIO5.
1:0 RW 1h
V
GP_PAD4. PAD configuration as internal pull-up or pull-down for GPIO4.
r
fo
Note: PAD pull-up or pull-down (PU:PD) configuration is:
1. [0:0] – Normal No pull-up or pull-down.
2. [0:1] – 75kΩ resistor pull-down.
3. [1:0] – 75kΩ resistor pull-up.
RTL2832U
Datasheet
10.3. I2C Master Control Registers (0040h-0053h)

10.3.1. I2C Clock Register (I2CCR, 0040h-0043h)
Table 22. I2C Clock Register (I2CCR, 0040h-0043h)
k
31:6 - - Reserved
FD10. Frequency 10M Divisor and 0 are forbidden. 10M=Bus clock/(FD10+1).
e
5:0 RW 13h When powered on, software must write FD10 to let the I2C controller generate a 10MHz
t
clock.
a l
I2C Master Control Register (I2CMCR, 0044h-0047h)
L
10.3.2.
e IA
Table 23. I2C Master Control Register (I2CMCR, 0044h-0047h)
T
R
N
2
IMUR. I C Master Unit Reset
E
0: Normal
31 RW 0
ID
1: Reset the I2C Unit (only resets hardware FSM). This bit will self-clear to Zero after
reset complete
F
CS. Command Start
N
30 RW 0 0: Stop. After completing a whole transaction, it returns to Zero
O
1: Start
C
RWL. Read/Write Data Length for Related Commands
29:25 RW 0 L
Does not include the slave address byte in the FIFO register.
4
When accessed, the controller will parse the byte following the last start (or Sr) byte to
r
find the command type.
V
fo
0: 1 byte ……… 17: 24 bytes
TORE. Time-Out Register Enable

24 RW 1 If TOR is required, the I2C rate must be constrained within 25kbps~400kbps.
This constraint is due to the time-out register bit.
RTL2832U
Datasheet
TOR. Time-Out Register

Time-out = TOR x 2 x ((FD10+1)/Bus clock) (For receive /transmit one bit).
23:16 RW 3Ah
If time-out occurs, it will trigger the Transaction Error Interrupt Flag.
Note: Time-out must > (1 SCL low period + repeat start setup time).
15:11 - - Reserved
k
SBAIFD. Second Byte ACK in FRSIB Data
e
SBAIFD indicates whether the master checks for ACK from slave after emitting second
10 RW 0
data in FRSIB data.
l t
0: Check 1: Do not check
FBAIFD. First Byte ACK in FRSIB Data
a
FBAIFD indicates whether the master checks for ACK from slave after emitting first data
L
9 RW 0
e
in FRSIB data.
IA
0: Check 1: Do not check
T
R
SRSIB. Second Repeat Start Interval Byte
N
After transmitting SRSIB bytes following the first repeat start command, the master will
E
produce a second repeat start command. The slave address or device address byte is
8:7 RW 0
ID
included in this interval. Default interval is one byte. 0=1 byte; 1=2 bytes, etc.
Note: The eighth bit of slave address or device address byte followed by second repeat
F
start command must be 1(means a Read CMD).
N
FRSIB. First Repeat Start Interval Byte
O
After transmitting FRSIB bytes following the original start command, the master will
C
6:5 RW 0
produce the first repeat start command. The original slave address or device address byte
RSC. Repeat Start Count

4 L
is included in this interval. Default interval is one byte. 0=1 byte; 1=2 bytes, etc.
4:3 RW 0
r
00: No repeat start
V 01: One repeat start
fo
10: Two repeat starts 11: Reserved
2 RW 0 TEIE. Transaction Error Interrupt Enable
1 RW 0 MRCIE. Master Receive Complete Interrupt Enable
0 RW 0 MTCIE. Master Transmit Complete Interrupt Enable
RTL2832U
Datasheet
10.3.3. I2C Master SCL Timing Register (I2CMSTR, 0048h-004Bh)

Table 24. I2C Master SCL Timing Register (I2CMSTR, 0048h-004Bh)
31 - - Reserved
I2CMD. I2C Master De-Bounce

0: Sample rate=(bus clk / (FD10+1))
k
30:28 RW 0 1: Sample rate=(bus clk / (FD10+1)) / 2
e
……
t
7: Sample rate= (bus clk / (FD10+1)) / 8
l
STA_SU_PC. STA Setup Time Period Count
27:20 RW 9h
In repeat start, the setup time of SCL must match the I2C spec.
a L
FTPC. Fall Time Period Count
e IA
19:16 RW 3h If the value of (Bus clock/FD10) does not approximate 10MHz, FTPC can make the fall
time of SCL more than 300ns.
T
R
SHPC. SCL High Period Counter (SCL High Period=100ns*SHPC)
N
15:8 RW 9h SHPC must include rising time in the I2C.
E
The I2C specification requires SHPC to include rising time.
ID
SLPC. SCL Low Period Counter (SCL Low Period=100ns*SLPC)
7:0 RW 10h
F
The I2C specification requires SLPC to include falling time.
10.3.4.
O N
I2C Master Status Register (I2CMSR, 004Ch-004Fh)
C L
Table 25. I2C Master Status Register (I2CMSR, 004Ch-004Fh)
Bits
31:3
Access
-
Reset
-
Description
Reserved
V 4
2 RW 0
fo r
TEIF. Transaction Error Interrupt Flag
When a master transmit/receive fault or time-out occurs, the I2C controller will lift the
flag up and return the bus to idle. Write ‘1’ to clear.
1 RW 0 MRCIF. Master Receive Complete Interrupt Flag. Write ‘1’ to clear.
0 RW 0 MTCIF. Master Transmit Complete Interrupt Flag. Write ‘1’ to clear.
RTL2832U
Datasheet
10.3.5. I2C Master FIFO Register (I2CMFR, 0050h-0053h)

Table 26. I2C Master FIFO Register (I2CMFR, 0050h-0053h)
31:8 - - Reserved
7:0 RW 0 TDD. Target Device Data. Read for receive.
e k
11. Register Descriptions (USB Interface)
l t
11.1. Introduction
a L
The RTL2832U transfers transport stream data from the demodulation module to the host via an
e IA
embedded high-speed USB 2.0 interface (compatible with USB 1.1). Two endpoints are supplied. One is
the control pipe and the other is the data pipe for TS transfer. The user controls the device by sending
T
R
standard request commands listed in the USB 2.0 Specification, Chapter 9. The host driver also needs to
N
read and write the device’s registers by sending vendor commands (11.1). The data pipe can be
E
configured to BULK mode or ISO mode.
ID
To reduce power consumption, the RTL2832U can enter a low-power suspend state, and has a remote
F
wakeup capability via IrDA. It can resume from S1, S3, or selective suspend state if the remote wakeup
N
function is permitted on the host.
C O
11.2. Vendor Commands
4 L
bmRequestType
rbRequest
V
Table 27. Vendor Commands
wValue wIndex wLength
fo
Command
(1 Byte) (1 Byte) (2 Bytes) (2 Bytes) (2 Bytes)
GetDemodRegPage0 0x0000~ Length of registers
0xC0 x Reg’s offset in page0~4
~GetDemodRegPage4 0x0004 to access
SetDemodRegPage0 0x0010~ Length of registers
0x40 x Reg’s offset in page0~4
~SetDemodRegPage4 0x0014 to access
Length of registers
GetUSBReg 0xC0 x (BaseAdd)<<8 + OffsetAdd 0x0100
to access
RTL2832U
Datasheet
bmRequestType bRequest wValue wIndex wLength

Command
(1 Byte) (1 Byte) (2 Bytes) (2 Bytes) (2 Bytes)
Length of registers
SetUSBReg 0x40 x (BaseAdd)<<8 + OffsetAdd 0x0110
to access
Length of registers
GetSysReg 0xC0 x (BaseAdd)<<8 + OffsetAdd 0x0200
to access
k
Length of registers
SetSysReg 0x40 x (BaseAdd)<<8 + OffsetAdd 0x0210
to access
e
Length of registers
GetTunReg 0xC0 x (OffsetAdd)<<8+ IICAdd 0x0300
t
to access
l
Length of registers
SetTunReg 0x40 x (OffsetAdd)<<8+ IICAdd 0x0310
to access
a L
GetROMCode 0xC0 x Rom Code Address 0x0400 Size of ROM Code
e
GetSTDI2C 0xC0 x I2C Device Address/ 0x0600 Length of registers
IA
Device register address to access
T
R
SetSTDI2C 0x40 x I2C Device Address/ 0x0610 Length of registers
N
Device register address to access
E
Note1: Demod registers are organized in 5 pages (page0~page4). ‘wIndex’ indicates the page’s number.
ID
Note2: Before accessing the tuner, the 7th bit of the first byte of the demodulator’s page1 should be set to 1 (IIC_repeat
bit).
N F Table 28. Definition of ‘wIndex’
O
Nibble [3] [2] [1] [0]
C
Page (true only as [2]=0,
4L
x Block Access
for demodulator)
0 1 2 3 4 5 0 1 0–4
Description Demodulator USB
o r V
System Tuner
ROM
Code
IR
0
6
Standard I2C
Command
f7
x
8
x
9
x
A
x
B
x
Get Set Page number
Note: To access the tuner, the command is issued within the DATA stage, ignoring the ‘wValue’ field value. The command
depends on the tuner used.
RTL2832U
Datasheet
11.3. SIE Control Register

The registers for USB SIE is defined in Table 29, including SIE control registers, endpoint registers,
debugging registers, and DMA control registers. The address is defined by an offset value with base
address 0x2000.
Table 29. SIE Control Register
k
Address Offset Name Description
e
0000h USB_SYSCTL USB System Control Register
t
0004h~0010h - Reserved
l
0008h - Reserved
a
000Ch - Reserved
L
0010h - Reserved
e IA
0014h - Reserved
T
R
0018h - Reserved
N
001C~0140h - Reserved
E
0144h USB_EPA_CFG Endpoint A Configure Register
ID
0148h USB_EPA_CTL Endpoint A Control Register
014C~0154h - Reserved
F
0158h USB_EPA_MAXPKT Endpoint A Max Packet Size Register
N
015Ch - Reserved
O
0160h USB_EPA_FIFO_CFG Endpoint A FIFO Configure Register
C
0164h~0FFFh - Reserved
4 L
r V
fo
RTL2832U
Datasheet
11.4. USB System Control Register (USB_SYSCTL, 0000h)

Table 30. USB System Control Register (USB_SYSCTL, 0000h)
31:11 - - Reserved
SIE Reset
k
10 RW 0
1: Switch to reset state 0: Switch to normal state
e
9:4 - - Reserved
t
Full Packet Mode
l
3 RW 0 When set to 1, SIE will send maximum packet size packets only. When data in EPA FIFO
a
is less than the maximum packet size, SIE will NAK the IN request.
L
2:1 - - Reserved
e IA
DMA Control
0 RW 1
1: Enable DMA 0: Disable DMA
T
R E N
11.4.1. Endpoint A Configuration Register (USB_EPA_CFG, 0144h)
ID
Table 31. Endpoint A Configuration Register (USB_EPA_CFG, 0144h)
F
N
31:10 - - Reserved
O
Isochronous Mode
C
Specifies the number of additional transaction opportunities per microframe (same
9:8 RW 0
4 L
definition as wMaxPacketSize[12:11] in standard Endpoint Descriptor).
Must be set to 00 (means 1 transaction per microframe).
7 RW 0
Endpoint Enable
r V
fo
0: Disable Endpoint A 1: Enable Endpoint A.
Endpoint Transfer Type

6:5 RW 10b 00: Control (only EP0 can be for control) 01: Isochronous
10: Bulk 11: Interrupt
Endpoint Transfer Direction

4 R -
0: OUT. Host-to-device 1: IN. Device-to-host
3:0 RW 0 Endpoint Number
RTL2832U
Datasheet
11.4.2. Endpoint A Control Register (USB_EPA_CTL, 0148h)

Table 32. Endpoint A Control Register (USB_EPA_CTL, 0148h)
31:10 - - Reserved
9 RW 0 FIFO Reset. Reset EPA FIFO
k
8:6 - - Reserved
5 W 0 FIFO Flush. Write 1 to flush the oldest TS packet (a 188 bytes block)
e
4 RW 0 Stall Endpoint. Write 1 to stall
t
3:1 - - Reserved
l
0 W 0 FIFO Valid. Write 1 to validate the TS packet (a 188 bytes block)
e a IA L
11.4.3. Endpoint A Max Packet Size Register
(USB_EPA_MAXPKT, 0158h)
T
R N
Table 33. Endpoint A Max Packet Size Register (USB_EPA_MAXPKT, 0158h)
E
ID
31:11 - - Reserved
F
EPA Max Packet Size
10:0 RW 40h
N
Defines the max packet size (in bytes) of endpoint A.
11.4.4.
C O Endpoint A FIFO Configuration Register

(USB_EPA_FIFO_CFG, 0160h)
4 L
V
Table 34. Endpoint A FIFO Configuration Register
r
fo
BLK_DROP_COUNTER
31:24 RW 0
Counts blocks dropped (each is 188 bytes) due to full FIFO.
23:4 - - Reserved.
EPA FIFO Size

3:0 RW Ah (10d)
Configures EPA FIFO size, in 188-byte blocks. Valid data range is 1~10.
RTL2832U
Datasheet
12. Characteristics
12.1. Absolute Maximum Ratings

Table 35. Absolute Maximum Ratings
Description Minimum Maximum Unit
k
Supply Voltage (VDD3, VDDA33) -0.5 4 V
e
Supply Voltage (VDD1, VDDA, UVDDA, VDDPLL) -0.5 1.35 V
t
Storage Temperature -55 +125 °C
12.2. DC Characteristics
a l L
e IA
Table 36. DC Characteristics
T
R
Symbol Parameter Conditions Minimum Typical Maximum Unit
N
VDD3, VDDA33 3.3V Supply Voltage - 3.0 3.3 3.6 V
E
VDDPLL, VDDA| 1.2V Supply Voltage - 1.1 1.2 1.35 V
ID
UVDDA
F
VDD1 1.2V Supply Voltage - 1.1 1.2 1.35 V
N
Voh Minimum High Level Ioh=-8mA 0.9*VDD3 - VDD3 V
O
Output Voltage
C
Vol Maximum Low Level Iol=-8mA - - 0.1*VDD3 V
4L
Output Voltage
Icc33 Average Operating Supply - - 7 - mA

(VDDA33, VDD3) Current from 3.3V
r V
fo
Icc12 Average Operating Supply - - 202* - mA
(VDD1, VDDA, Current from 1.2V
VDDPLL, UVDDA)
*: In case of 64QAM, Code rate=2/3, Guard Interval=1/4, Bandwidth=8MHz, bypass internal switching regulator.
RTL2832U
Datasheet
12.3. AC Characteristics
START STOP
SDA
k
tr tf tset_DAT
t e
SCL
a l
th_STR tlow th_DAT thigh tset_STOP
L
e IA
Figure 8. Two-Wire Interface Timing Diagram
T
R E N
Table 37. Two-Wire Interface Timing
ID
Symbol Parameter Min Max Unit
F
- SCL Clock Frequency 50 300 kHz
N
thigh High Period of SCL 600 - ns
O
tlow Low Period of SCL 600 - ns
C
th_STR Hold Time of START 200 - ns
4L
th_DAT Hold Time of DATA 200 - ns
tset_STOP Setup Time of STOP 200 - ns
tset_DAT Setup Time of DATA
r V 200 - ns
fo
tr Rise Time of SCL and SDA (with 4.7k ohm resister pulled high) (See Note) - ns
tf Fall time of SCA and SDA (See Note) - ns
Note: Depends on the external bus pull high resistor.
RTL2832U
Datasheet
12.4. Crystal Conditions

Table 38. Crystal Conditions
Description Minimum Typical Maximum Unit
Crystal Reference Frequency, Fundamental Mode - 28.8 - MHz
Stability -30 - +30 ppm
k
Tolerance -30 - +30 ppm
e
Duty Cycle 40 - 60 %
t
Load Capacitance - 20 - pF
l
C0 (Shunt Capacitance) - - 5pF pF
a
ESR (Equivalent Series Resistance) - - 30 ohm
L
R e E N T IA
F ID
O N
C V 4 L
fo r
RTL2832U
Datasheet
13. Application Circuits

Designers are suggested to contact Realtek to get the latest application circuits. To get the best
compatibility in hardware design and software driver, any modifications of application circuits should be
confirmed by us. Realtek may update the latest application circuits onto our website (www.realtek.com)
without modifying this datasheet.
k
USB Interface
e
DM
DP
t
VDDLV
C1
0.1uF R1
l
VDDA3
R2 10k 1% 0
VDDA1
VDDA1
GNDA
GPIO0
a
49
48
47
46
45
44
43
42
41
40
39
38
37
C2 U3
Q_P
1nF VDDA33
GPIO0
R12K
VDDA
GNDA
VDDA
LV_USB
HSDP
HSDM
GND
VCMI
SEGND
IRRC
L
C3
Q_N
1nF
1 36
2 VIP GPIO3 35 VDD1
e
C4 GNDA 3 VIN M_ERR 34 VDD3
IA
I_N GNDA VDD1
1nF 4 33
C5 5 VQP VDD3 32
I_P VQN GPIO1
1nF 6 31
VINR
VDD_PLL 7
VDDPLL RTL2832U GPIO2
GPIO4
30
8 QFN48 29 VDD1
C6 47pF 9 GNDPLL GPIO5 28 0
T
TP_CK0 VDD1
R
10 27 R5
11 XO ENSWREG 26 VDD3
REG_OUT4
XI HVD1
2
R6 VDD1 12 25
I2C_SDAT
I2C_SCLT
VDD1
I2C_SDA
HVD2
I2C_SCL
AGC_RF
Y2 L4 bead
AGC_IF
GPIO7
GPIO6
N
28.8MHz 1M
VDD3
VDD1
RSET
C7
4
C8 10uF
LT6
13
14
15
16
17
18
19
20
21
22
23
24
E
VDD3
47pF VDD3 L15 VDD1_2
bead 10uH
C9 R7 VDD1_2 VDDA1
IFAGC
VDD1
VDD3
0.1uF R8
ID
1K
R9
L5 bead
R10 C10
0R
C11 C12 C13

4.7K 10uF 2.2uF
4.7K
R11 10K IFAGC 0.1uF 0.1uF

IF_AGC
F
SCLT
C14
VDD1_2 VDD_PLL
10nF SDAT
N
L6 bead
R12 R13 VDD3 C15 C16

U4 VDD3 2.2uF
VDD3 0.1uF
1 8 4.7K VDDA3
4.7K
O
2 E0 VCC 7
E1 MODE VDDA3
3 6 VDD1_2
4 E2 SCL 5 VDD1_2 VDDLV
VSS SDA VDD1_2
C
L7 bead
M24C02-W
C18 C17
2.2uF
0.1uF
4 L
V
Figure 9. Application Circuits
fo r
RTL2832U
Datasheet
14. Mechanical Dimensions
t e k
a l L
R e E N T IA
F ID
O N
C V 4 L
fo r
RTL2832U
Datasheet
14.1. Mechanical Dimensions Notes

Symbol Dimension in mm Dimension in inch
Min Nom Max Min Nom Max
A 0.75 0.85 1.00 0.030 0.034 0.039
A1 0.00 0.02 0.05 0.000 0.001 0.002
k
A2 0.55 0.65 0.80 0.022 0.026 0.032
e
A3 0.20REF 0.008REF
t
b 0.15 0.20 0.25 0.006 0.008 0.010
l
D/E 6.00BSC 0.236BSC
a
D1/E1 5.75BSC 0.226BSC
L
D2/E2 4.05 4.30 4.55 0.159 0.169 0.179
e IA
e 0.40BSC 0.016BSC
L 0.30 0.40 0.50 0.012 0.016 0.020
T
R
θ 0o - 14o 0o - 14o
E N
aaa - - 0.15 - - 0.006
ID
bbb - - 0.10 - - 0.004
ccc - - 0.10 - - 0.004
F
ddd - - 0.05 - - 0.002
N
eee - - 0.08 - - 0.003
O
fff - - 0.10 - - 0.004
C 4 L
Notes 1: DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
V
Notes 2: CONTROLLING DIMENSION: MILLIMETER (mm).
fo r
Notes 3: REFERENCE DOCUMENT: JEDEC MO-220.
RTL2832U
Datasheet
15. Ordering Information

Table 39. Ordering Information
Part Number Description Status
RTL2832U QFN-48 with ‘Green’ Package Mass Production
Note: See page 4 for Green package and version identification.
t e k
a l L
R e E N T IA
F ID
O N
C V 4 L
Realtek Semiconductor Corp. fo r
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com

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fo Track ID: JATR-2265-11

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ADC 90 Resampler Synchroniza FFT

5.1. Green Package and Version Identification

I: Input I/OD: Bi-Directional, Output Open-Drain

O: Output Tri: Tri-State Output

TP_CKO 9 ADC Test Pin for Clock Input I/O

VIN 2 Differential Analog Input – Negative (I Path) I

VQP 4 Differential Analog Input – Positive (Q Path) I

VQN 5 Differential Analog Input – negative (Q Path) I

R12K 48 Connects a 10k ohm Resistor to Ground I

VCMI 46 Reference Voltage for ADC AC-Coupling I

Name Pin number Function Type

VINR 6 Low Speed 7-bit ADC Single-Ended Input I

HSDP 40 USB D+ Signal I/O

HSDM 41 USB D- Signal I/O

UVDDA 42 USB 1.2V Analog Power Supply PS (1.2V)

GPIO[0] 37 General Purpose I/O Pin-0 Tri

Internal 3.3V to 1.2V Switching Regulator

0V: Turn off switching regulator

SW_VDD3 26, 25 3.3V Power Input PS (3.3V)

REG_OUT 24 1.2V Power Output O

FB 23 Regulated Feedback Voltage I

7.8. Channel Estimation

8.1. Automatic Gain Control (AGC)

8.1.1. Register Name: loop_gain

u(6,5f) Set Take-Over Point1

u(8,4f) Set RF AGC Gain Degrade Ratio1

u(8,4f) Set RF AGC Gain Degrade Ratio2

krf3 1 0xCD [7:0] RW 20 u(8,4f) Set RF AGC Gain Degrade Ratio3

krf4 1 0xCE [7:0] RW 30 u(8,4f) Set RF AGC Gain Degrade Ratio4

if_agc_min 1 0x08 [7:0] RW 80 s(8,7f) Set IF AAGC Minimum Gain

Offset Bits Default

if_agc_max 1 0x09 [7:0] RW 7F s(8,7f) Set IF AAGC Maximum Gain

rf_agc_min 1 0x0A [7:0] RW 80 s(8,7f) Set RF AAGC Minimum Gain

rf_agc_max 1 0x0B [7:0] RW 7F s(8,7f) Set RF AAGC Maximum Gain

if_agc_val 3 {59,5A} [13:0] R - s(14, 13f) IF AAGC Value

rf_agc_max=floor (90%*255-128)=101 (dec)

vtop=63 (dec)Æ RF gain does not delay

vtop=floor (63*0.5)=31 (dec)

8.1.4. Register Name: Krf

8.2. ADC Input (Tuner Output)

8.3. Two-Wire Interface Between the Tuner and the RTL2832U

I2C Repeater for Tuner

8.4. RTL2832U Internal Switching Regulator

9. Register Descriptions (General)

9.1. Analog to Digital Converter (ADC)

1: Enable Zero-IF input

9.2. DC Cancellation and IQ Compensation

9.3. Digital Down Conversion (DDC)

• fIF = 0M, fADC = 28.8M,

Table 6. Digital Down Conversion (DDC)

Register Offset Default

1: Enable adjacent channel rejection

pset_iffreq 1 {0x19,0x1B} [21:0] RW - Set IF Frequency

• BW: 7MHz Æ fsymbol = 8 MHz, fcrystal = 28.8MHz

BW: 6MHz Æ fsymbol = 48/7 MHz, fcrystal = 28.8MHz

Register Name Page Offset{MSB,LSB} Bits Used RW Default (Hex) Description

rsamp_ratio 1 {0x9F, 0xA2} [27:2] RW C99999 Resampler Ratio

9.5. Co-Channel Interference Rejection

1: Enable CCI cancellation

9.6. Impulse Noise Cancellation

inc_det_cnt 3 {0x28, 0x29} [8:0] R

4 L - Number of Impulse Noise Events

9.7. Digital Automatic Gain Control (DAGC)

Offset Bits Default

4 L Pre-Set Guard Interval and FFT Mode

9.9. Timing Recovery/Carrier Recovery

Table 12. Timing Recovery/Carrier Recovery

Register Name Page Offset Bit RW Type Default Description

cfreq_off 3 {0x5F, 0x61} [17:0] R s(18,7f) - Estimated Carrier Frequency Offset

sfreq_off 3 {0x18, 0x19} [13:0] R s(14,24f) - Estimated Sampling Frequency Offset

Table 13. PID Filter

Register Name Page Offset Bit RW Default Description

COFDM complying with Nordig Unified Delayed AGC with programmable