Acer All in One - 13045-1

5 4 3 2 1
Title Page Title Page

COVER PAGE 1 USB 3.0 PORT/CHARGER 35
D
BLOCK DIAGRAM
POWER BLOCK DIAGRAM
2
3
USB 2.0 POWER SWITCH
REAR USB/TOUCH/ WEBCAM
36
37
vSuperb_-1 D
SYSTEM POWER SEQUENCE 4 MINI PCIE ( WLAN/BT) 38

POWER SEQUENCE 5 MINI PCIE ( mSATA) 39
CLOCK DIAGRAM
RESET DIAGRAM
6
7
PWRBTN/SIDE KEY/LED
G-SENSOR
40
41 Schematics Document
GPIO TABLE 8 SPI/RTC 42
SMBUS BLOCK DIAGRAM 9 CSOPN/COM PORT 43
TABLE OF CONTENT
CPU uLGA 1150_1
10
11
DEBUG PORT/TPM
DUMMY SYMBOL/EMI CAP
44
45
Haswell LGA1150
CPU uLGA 1150_2 12 RUN POWER/SEQUENCE 46
C
CPU uLGA 1150_3
CPU uLGA 1150_4
13
14
ADAPTOR OCP
DC IN
47
48
Intel Lynx Point C
DDR3-SODIMM1 15 BATTERY CHARGER 49

DDR3-SODIMM2 16 5V/3D3V(TPS51125) 50
PCH (AUDIO/GPIO/SPI) 17 CPU VCORE_ISL95812(1/2) 51
PCH CLOCK 18 CPU VCORE_ISL95812(2/2) 52
PCH (SATA/FAN/DP/VGA) 19 1D5V/0D75V(TPS51116) 53 !"#$%&'()*+,-.)&'
PCH (FDI/PCIE/DMI/USB) 20 PCH 1D05V/1D05_ME 54
PCH (GND/STRAPS) 21 12V 55
<=8####>=?
PCH POWER 22
!"#!$% @#########@
PCIEX1 23 &"#&'#!$% A#########A
B
SIO ITE8732 24 ("#()*+,*'- A#########A B
INTEL LAN CLARKVILLE 1217 25 ."#.$!#)#&',#/0121- A#########@

AUDIO CODEC_ALC269 26 /"#/0121- @#########A
AUDIO_AMP 27 3"#4,5+-,12#6%#7'-#83 @#########@
SCALAR PORT 28
9"#.,:';,5
eDP to LVDS 29
LCD PORT 30
PCB BOARD SIZE
VGA PORT 31 8 Layers
DISPLAY PORT 32 170mm X 170mm
SATA PORT 33
Schematics change
SIDE IO PORT 34 SA
A
SB A
<Core Design>
1A
-1 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size Document Number Rev
Custom
vSuperb -1
Date: Tuesday, October 08, 2013 Sheet 1 of 55
5 4 3 2 1
5 4 3 2 1
BATTERY CHARGER
Project code :91.3KB01.001 BQ24727RGRR 49
Swift Block Diagram PCB No :13045 INPUTS OUTPUTS
Revision : -1 ADP+ DCBATOUT
SYSTEM DC/DC
Project Name :PIH81L/vSuperb TPS51225 50
D
DDRIII 1333/1600 Channel A DDRIII Slot 1 INPUTS OUTPUTS D
LVDS LVDS RTD2136 eDP 1066/1333 5V_AUX_S5
Intel CPU DCBATOUT
3D3V_AUX_S5
5V_A
3D3V_A
DDRIII 1333/1600 Channel B DDRIII Slot 2
DP Haswell 1066/1333 CPU DC/DC
DP 51-52
Intel pGA Core ISL95812HRZ
HDMI IN
i7 4765T 2.0G 8M INPUTS OUTPUTS
i5 4570T 2.9G 4M DCBATOUT VCC_CORE
DP DP i3-4130T 2.9G 3M SYSTEM DC/DC

Pentium Dual-core G3220T eDP Scalar BD LVDS LCD TPS51116 53
2.6G 3M INPUTS OUTPUTS
1D5V_S3
DCBATOUT 0D75V_S0
DDR_VREF_S3
FDIx4x2 DMIx4 LDO

(UMA only) HP APL5611ACI 54
C
INPUTS OUTPUTS C
Combo Jack 12V_S0 PCH_1D05V

26
Mic in LDO
APL5930KAI 54
Intel Amp INPUTS OUTPUTS
VGA RGB CRT
3D3V_A 1D05V_ME
AZALIA
PCH ALC269Q
SYSTEM DC/DC
USB x 1 USB3.0 x 1 Lynx Point NCP1589AMNTWG 55
H81/Q87 INPUTS OUTPUTS
Int Digital MIC IN
USB x 1 DCBATOUT 12V_S0
USB3.0 x 1
Charger function
2 USB 3.0 / 8 USB 2.0/1.1 ports
RJ45
CONN
PCB LAYER
PCIEX1 PCIE x 1 ETHERNET (10/100/1000Mb)
Intel L1:Top L5:VCC
High Definition Audio PCIE x 1 L2:GND L6:Signal
B Clarkvillie I217-V/LM L3:Signal L7:GND B
SATA ports (4)
Webcam USB2.0 L4:Signal L8:Bottom
PCIE ports (6)
LPC I/F
Real side PCIE x 1,USB x 1 Mini-Card
ACPI 1.1
USB X 2 Flash ROM SPI Wireless Lan+ Bluetooth
8MB/16MB
Touch
SATA x 4 mSATA (SATA3_6Gb/s)
LPC Bus
Card Reader
LPC debug port HDD 2.5" (SATA3_6Gb/s)
TPM
HDD 2.5"
A SIO ITE8732-CX Temp Ctrl <Core Design> A
ODD Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
Block Diagram
Fan Scalar Ctrl 25 A3
vSuperb -1
5 4 3 25 2 1
5 4 3 2 1
Adapter 90W/135W
3D3V_DMIC
EUP PWR
19V
N-MOS N-MOS
3D3V_S5 V_3P3_LAN
AO6402A AO3419L
D D
3D3V_AUX_S5 P_3.3V_EDP_VDDIO
P_3.3V_EDP_VDDIOX
LDO 1D05V_ME
SI4128*1 3D3V_PWR 3D3V_A APL5930 Imax=1A
VCC5_CAM
SI4712*1 Imax=5A
1 Phase Design N-MOS

3D3V_S0
AO4468L
PWM
SIR172ADP*1 5V_PWR 5V_A N-MOS
TPS51225C FAN_PWR
SIRA12DP*1 Imax=11A AO4468L 5V_S0
1 Phase Design 5V_ODD

5V_AUX_S5
C C
5V_HDD
UP7534 5V_CHARGER_OUT
EUP PWR
N-MOS
5V_S5 UP7534 USB30_VCCA
AO4468L
SIR172DP*2
PWM
SIRA12DP*2 UP7534 VCC5_USB_018
VCC_CORE
2 Phase Design Tdc=26A Iomax=58A (45W)
ISL95812 Tdc=20A Iomax=48A (35W)
SIR172DP*2(1reserve) 5V_PVDD
SIRA12DP*2
B B
V_5_CODEC
PWM
SIR172DP*1 1D5V_S3 LDO
PCH_1D05V
TPS51116 SIRA12DP*2 Imax=18A APL5611AC
1 Phase Design
DDR_VREF_PWR
0D75V_S0
Imax=1.5A
DDR_VREF_S3
A A
PWM <Core Design>
SIR4214D*1 12V_S0 Wistron Corporation

NCP1589
Imax=4A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
www.vinafix.vn
Title
1 Phase Design
Power Block Diagram
Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
Power Sequence
D D
C C
B B
A <Core Design> A
Wistron Corporation
Title
System Power Sequence

A3
vSuperb -1
5 4 3 2 1
5 4 3 2 1
Power Sequence
D D
C C
B B
<Core Design>
A A
Wistron Corporation
Title
Power Sequence
B
vSuperb -1
5 4 3 2 1
5 4 3 2 1
CPU i7-4765T/i5-4570T
CLK_EXP_N
M_A_DIM0_CLK_DDR0/M_A_DIM0_CLK_DDR#0
BCLK(J3)
BCLK#(H2)
SA_CK0(AU36)
SA_CK#0(AV36) M_A_DIM0_CLK_DDR1/M_A_DIM0_CLK_DDR#1
DIMM1
D CLK_EXP_P SA_CK1(AT40) D
SA_CK#1(AU40)
M_B_DIM0_CLK_DDR0/M_B_DIM0_CLK_DDR#0
SB_CK0(BA34)
SB_CK#0(AY34) M_B_DIM0_CLK_DDR1/M_B_DIM0_CLK_DDR#1 DIMM2
SB_CK1(BA36)
SB_CK#1(BB36)
PCH H81
CLKOUT_DMI_N(AV22)
CLKOUT_DMI_P(AU22)
PCIEX1_CLKN(Y4)
PCIEX1_CLKP(Y2)
100MHz PCIE-X1
C C
CLKOUT_PCIE5N(V45)
CLKOUT_PCIE5P(V46)
100MHz Intel Clarkville 25MHz
1217-V/LM
CLKOUT_PCIE3N(Y37)
100MHz
CLKOUT_PCIE3P(Y36)
Mini PCIE WLAN+BT
SIO IT8732F-CX
48MHz
CLKOUTFLEX1(F47) CLKIN(37)
B 33MHz B
CLKOUT_PCI2(J48) PCICLK(47)
HDA_BCLK(N34) 24MHz
AUDIO ALC269Q
RTCCLK
(for Master) SPI_CLK(T3)

17.86 MHz/31.25 MHz/50 MHz SPI ROM
XTAL25_IN
25MHz XTAL25_OUT
CLKOUT_PCI0(H49)
33MHz LPC Debug Port
(for RTC)
32.768KHz RTCX1
RTCX2
A A
<Core Design>
Wistron Corporation
Title
Clock Diagram
C
vSuperb -1
5 4 3 2 1
5 4 3 2 1
REALTEK
PLTRST_LAN RTL8111E-VC
Rs
RESET#
PCIRST1# PLTRST1# PLTRST_SL_N PCIE X16

PIN33
Rs
RESET#
D D
PCIRST2#
PIN34
PLT_WLAN_RST#
PLTRST3#
Rs Mini-PCIE WLAN+BT
RESET#
SIO ITE8732
PLTRST*_SIO
LRESET# Rs
PIN49
TPS51461
3D3V_S0 Intel PCH
PLT_RST# CPU BGA1155
PLTRST#
Rs C6
H_RCIN#
KBRST# RCIN# ISL95836HR
PIN45 P5
RSMRST#_SIO 6 PM_RSMRST#
C
RSMRST# Rs SYS_RESET# 3D3V_S0 C
PIN85 RSMRST# K3
Rs The signal is active after SLP_SUS C21
GP43 PWRON#
PIN75 PIN72 2 PM_PWRBTN# PWRBTN#
E20
PWROK2 SUSB# PM_SLP_S3#

PIN78 PIN71 8 SLP_S3_PCH_N SLP_S3#
Rs F4 DRAMPWROK H_DRAMPWRGD 13 VDDPWRGOOD SM_DRAMPWROK
PM_SLP_S4# 7 B13 BE45
SUSC# SLP_S4#
PSON# PIN77 H4
PIN76
PWROK3_1 12 S0_PWR_GOOD
PWROK1 Rs PWROK
PIN32 L22
H_CPUPWRGD 14
Rs PROCPWRGD UNCOREPWRGOOD
AY11 B46
Rs
DIMM SM_DRAMRST#
AT30 3D3V_S0
PWROK3_2_R PWRGD_3V
Logic Rs PCH_MEPWROK APWROK
APL5930KAI L10
Rs
B PCH_SLP_A ISL95870 B
EN SLP_A#
G10 10
PGOOD
CPUVTT_PWRGD Pin10
AUDIO CODEC ALC269Q SYS_PWROK SYS_PWROK
P12
HDA_CODEC_RST# HDA_RST# HDA_RST#
Rs K34
RESET#
1
RTCRST#
D20
3D3V_S5
Rs Run POWER
9
2
SIO_PSON_N
PS_ON# PWRBTN#
BTNBD1 Rs
A A
CHIP SOCKET or SLOT <Core Design>
Wistron Corporation
PB_IN_N_1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Reset Diagram
C
vSuperb -1
5 4 3 2 1
5 4 3 2 1
!"#$%&'()*+',-&.$
/$%01234'567896:968
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
GPIO Table
Custom
vSuperb -1
5 4 3 2 1
A B C D E
!"#$%&'()$'*+,-$./01203
!"# SCL SCL SCL CIICSCL
3D3V_S0
SDA DIMM1 SDA DIMM2 SDA PCIEX1 CIICSDA RTD2136
1
$%&' 2.2k 2.2k
1
SMB_CLK (R)
SMBCLK ! ! ! ! ! ! ! ! SCL
SMBDATA SMB_DATA
! ! ! ! ! ! ! ! SDA
G Sensor
SCL
SDA
Wireless SCL
SDA mSATA
(R)
LAN+BT (R)
3D3V_S0 3D3V_S5
SMBUS_ISP
SW PCH GPIO68
EDP_AUX_P
(R) 10k 10k (R)
(S) SCALAR SIO_UART1_TX
(R) 10k 10k (R)
(S)
DDPD_AUXP ! ! ! SCL !
0.1U
DDPD_AUXN EDP_AUX_N SIO_UART1_RX
! ! ! SDA !
(S)
(R) 1.8k 1.8k (R)
2 2
GND GND 0.1U
RTD2136
AUX_N
AUX_P
3D3V_S5
SMLINK0_CLK
499R 499R
LAN 3D3V_S5
SML0CLK ! SMB_CLK
SML0DATA SMLINK0_DATA 10k 10k
! SMB_DATA
SMBUS1 !
! for ITE
3D3V_S5
SIO 3D3V_S0
debug 3D3V_S0
2.2k 2.2k ITE8732 10k 10k 10k 10k

SML1_CLK
SML1CLK ! SMB_CLK
3 3
SML1DATA SML1_DATA SMB_DATA ! CIICSDA ! EEPROM
! SMBUS0 !
(R)
CIICSCL RTD2136 !
for EDID
3D3V_S5
10k 10k
! ! CIICSDA
SMBUS2 ! !
CIICSCL BQ24727R
3D3V_S0
VGA_DDC_CLK
VGA_DDC_DATA VGA_PCH_DDCSCL
2.2k 2.2k SDA
SCL
BATTERY
!
DDCDATA
VGA_PCH_DDCSDA
! DDCCLK VGA
4 DP_AUX_P 4
DDPB_AUXP
AUX_CHP
DDPB_AUXN DP_AUX_N
AUX_CHN DP <Core Design>
Wistron Corporation
DP2_AUX_P
DDPC_AUXP Title
AUX_CHP
DDPC_AUXN DP2_AUX_N SMBUS Block Diagram
(R)
AUX_CHN Internal DP Size
Custom
Document Number Rev
vSuperb -1
A B C D E
A B C D E
4 PCH Strapping Huron River Schematic Checklist Rev.0_7 4

Name Schematics Notes
SPKR Reboot option at power-up
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ
- 10-kΩ weak pull-up resistor.
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile.
GNT2#/GPIO53 Mobile: Used as GPIO only
GNT1#/GPIO51 Pull-up resistors are not required on these signals.
If pull-ups are used, they should be tied to the Vcc3_3power rail.
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

SPI_MOSI
Disable Danbury:Left floating, no pull-down required.
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm

weak pull-up resistor [CRB has it pulled up
with 1-kohm no-stuff resistor]
Processor Strapping Huron River Schematic Checklist Rev.0_7
3 NV_ALE Pin Name Strap Description Configuration (Default value for each bit is Default 3
1 unless specified otherwise) Value
Disable Danbury:Leave floating (internal pull-down)
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low. CFG[2] PCI-Express Static 1: Normal Operation.
Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. Disabled - No Physical Display Port attached to
CFG[4] 1: Embedded DisplayPort.
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. 0
/GPIO[33] Platform design should provide appropriate pull-up or pull-down depending on Enabled - An external Display Port device is
the desired settings. If a jumper option is used to tie this signal to GND as 0: connectd to the EMBEDDED display Port
required by the functional strap, the signal should be pulled low through a weak
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal Port Bifurcation 10 : x8, x8 - Device 1 function 1 enabled ;
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for Straps function 2 disabled
strapping functions. 11
01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. enabled
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
1
GPIO15 confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher 0: PEG Wait for BIOS for training
2 suite with confidentiality 2
Note : This is an un-muxed signal.
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low.
Sampled at rising edge of RSMRST#.
CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
GPIO27 analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
1 <Core Design>
1
Wistron Corporation
Title
Table of Content
A3
vSuperb -1
5 4 3 2 1
$%&$' P_CPU_VCCIO
!"#$%&"'(%)*
18 CK_PE_100M_MCP_DP
18 CK_PE_100M_MCP_DN !"#!$"%$"&'()')*+',-./01'23#'45'#63
R337 1 2 75R2F-2-GP !"#$%"&%"'
MINIMIZE STUB BETWEEN THESE AND RESISTORS AT SINAL PAGE
1D5V_S3 R2223 1 2 1K8R2F-GP H_DRAMPWRGD
1
PLACE IN CRB AREA R353 1 2 110R2F-GP ()**+,0.;.<.,=>5?@A5
CPU1E 5 OF 10 R2224
$#()*$&+, H_VIDSCK_VR R55 1 2 0R0402-PAD H_VIDSCK R351 1 (R) 2 90D9R2F-1-GP CK_PE_100M_MCP_DN V4
BCLK# HASWELL BPM#0
G39 TP_CPU_G39 1 TP105 TPAD28-1-GP-U 3K3R2J-3-GP
51 VCC_SENSE CK_PE_100M_MCP_DP V5 J39 TP_CPU_J39 1 TP169 TPAD28-1-GP-U
H_VIDSOUT_VR R54 1 2 0R0402-PAD H_VIDSOUT BCLK BPM#1 G38 TP_CPU_G38 1 TP103 TPAD28-1-GP-U !"#!$"%$"&'()')*+',-./01'#6%7'45'868
51 VSS_SENSE
2
H_VIDSCK C38 BPM#2 H37 TP_CPU_H37 1 TP107 TPAD28-1-GP-U
H_VIDALERT_N_VR R52 1 2 0R0402-PAD H_VIDALERT_N H_VIDSOUT C37 VIDSCLK BPM#3 H38 TP_CPU_H38 1 TP108 TPAD28-1-GP-U
51 H_VIDSCK_VR VIDSOUT BPM#4
51 H_VIDSOUT_VR H_VIDALERT_N R324 1 2 44D2R2F-GP H_VIDALERT_N_1 B37 J38 TP_CPU_J38 1 TP109 TPAD28-1-GP-U
R323 1 (R) 2 100R2J-2-GP VIDALERT# BPM#5 K39 TP_CPU_K39 1 TP110 TPAD28-1-GP-U
51 H_VIDALERT_N_VR BPM#6
D H_DRAMPWRGD R50 1 2 0R0402-PAD H_DRAMPWRGD_CPU AK21 K37 TP_CPU_K37 1 TP111 TPAD28-1-GP-U D
H_PWRGD AB35 SM_DRAMPWROK BPM#7 T35 TP_CPU_T35 1 TP112 TPAD28-1-GP-U
PLTRST_CPU_N R349 1 2 0R0402-PAD H_CPURST_N M39 PWRGOOD RSVD_T35 M38 TP_CPU_M38 1 TP113 TPAD28-1-GP-U P_CPU_VCCIO
RESET# RSVD_M38
!"#
1
(R) (R) (R) H_PM_SYNC_0 P36 P6 TESTLOW_1 R546 1 2 49D9R2F-GP
PM_SYNC TESTLO_P6
1
R365 R330 C567 H_PECI N37 K9 VCCST R338 1 2 51R2J-2-GP H_PROCHOT_R_N
21 HSW_STRAP_13 PECI RSVD_K9
665R2F-2-GP 43R2J-GP SCD1U16V2ZY-2GP H15 TP_RSVD_H15 1 TP136 TPAD28-1-GP-U
1 TP_H_CATERR_N M36 RSVD_H15 J9 TP_RSVD_J9 1 TP137 TPAD28-1-GP-U R336 1 2 1KR2J-1-GP CPU_THERMTRIP_N
!"#$%&'
2
TP166 H_PROCHOT_R_N K38 CATERR# RSVD_J9 H14 TP_RSVD_H14 1 TP138 TPAD28-1-GP-U
2
TPAD28-1-GP-U CPU_THERMTRIP_N F37 PROCHOT# RSVD_H14 M8
THERMTRIP# VCC_M8 VCC_CORE
H_SKTOCC_N D38 AV2 TP_RSVD_AV2 1
SKTOCC# RSVD_AV2 J16 TP_RSVD_J16 1 TP139 TPAD28-1-GP-U R66 1 2 10KR2J-3-GP H_PWRGD
!"#"$%&'"(!"%&)$ +V_SM_VREF_CNT AB38 RSVD_TP_J16 H16 TP_RSVD_H16 1 TP134 TPAD28-1-GP-U
&-.,+ P_CPU_VCCIO
SM_VREF RSVD_TP_H16
PWR_DEBUG
N40 PWR_DEBUG TP135 TPAD28-1-GP-U C460 2 (R) 1 SCD1U16V2ZY-2GP
2010/12/20 SB
Add EMI Cap
HSW_PCUDEBUG_0 AA37 N39
HSW_PCUDEBUG_1 Y38 CFG0 VSS V7 TP_RSVD_V7 R289 1 2 0R0402-PAD R152 1 2 150R2F-1-GP PWR_DEBUG
CFG1 VSS PCH_1D05V
HSW_PCUDEBUG_2 AA36 AB6 TP_RSVD_AB6 R295 1 2 0R0402-PAD
14 VCCST CFG2 VSS
1
14 PWR_DEBUG HSW_PCUDEBUG_3 W38 K13 TP_RSVD_K13 1 TP130 TPAD28-1-GP-U R717 2 (R) 1 10KR2J-3-GP
R339 HSW_PCUDEBUG_4 V39 CFG3 RSVD_TP_K13 J8 TP_RSVD_J8 1 TP131 TPAD28-1-GP-U
75R2J-1-GP HSW_PCUDEBUG_5 U39 CFG4 RSVD_TP_J8 R1 DDR_RCOMP_0 R519 1 2 100R2F-L1-GP-U
17,51 H_PWRGD CFG5 SM_RCOMP0
20,24,44 PLT_RST# (R) HSW_PCUDEBUG_6 U40 P1 DDR_RCOMP_1 R369 1 2 75R2F-2-GP
HSW_PCUDEBUG_7 V38 CFG6 SM_RCOMP1 R2 DDR_RCOMP_2 R529 1 2 100R2F-L1-GP-U
2
HSW_PCUDEBUG_8 T40 CFG7 SM_RCOMP2 AB36 TP_RSVD_AB36 1 TP126 TPAD28-1-GP-U
17 H_SKTOCC_N PLTRST_CPU_N2 HSW_PCUDEBUG_9 Y35 CFG8 RSVD_AB36 AW2 TP_RSVD_AW2 1 TP127 TPAD28-1-GP-U
17 FP_RST_DBR_N 3D3V_S5 CFG9 RSVD_TP_AW2
17 H_DRAMPWRGD HSW_PCUDEBUG_10 AA34 AV1 TP_RSVD_AV1 1 TP128 TPAD28-1-GP-U
HSW_PCUDEBUG_11 V37 CFG10 RSVD_TP_AV1 AC8 TP_RSVD_AC8 1 TP129 TPAD28-1-GP-U
VR_READY R2229 1 (R) 2 150KR2J-GP HSW_PCUDEBUG_12 Y34 CFG11 RSVD_AC8 P4 3D3V_S5
18 CK_DPNS_R_DN CFG12 VCOMP_OUT V_VCCIOA_LOAD
18 CK_DPNS_R_DP HSW_PCUDEBUG_13 U38 U8 TP_RSVD_U8 1 TP124 TPAD28-1-GP-U
Q38 HSW_PCUDEBUG_14 W34 CFG13 RSVD_U8 AB33 TP_RSVD_AB33 1 TP125 TPAD28-1-GP-U
14,17,46,51 VR_READY CFG14 RSVD_AB33 (R)
1 6 HSW_PCUDEBUG_15 V35 T8 CPU_VSS_T8 R80 1 2 0R2J-2-GP R718 1 2 10KR2J-3-GP H_SKTOCC_PU 1 2 0R2J-2-GP H_SKTOCC_N
PLT_RST# R350 1 (R) 2 1K3R2F-1-GP PLTRST_N_R 2 CFG15 RSVD_T8 Y8 TP_RSVD_Y8 1 TP116 TPAD28-1-GP-U R296
19 H_PM_SYNC_0 RSVD_Y8
19 H_THERMTRIP_N 5 PLTRST_CPU_N1 R31 2 (R) 1 100KR2J-1-GP HSW_PCUSTB_0_DP Y36 M10 TP_RSVD_M10 1 TP117 TPAD28-1-GP-U
(R) 3 4 HSW_PCUSTB_0_DN Y37 CFG17 RSVD_M10 L10 TP_RSVD_L10 1 TP118 TPAD28-1-GP-U
19,24 H_PECI CFG16 RSVD_L10
1
19 PLTRST_CPU_N !"#$%"&%"' C303 HSW_PCUSTB_1_DP V36 M11 TP_RSVD_M11 1 TP119 TPAD28-1-GP-U
SC100P50V2JN-3GP MBT3904DW1T1G-2-GP HSW_PCUSTB_1_DN W36 CFG19 RSVD_M11 L12 TP_RSVD_L12 1 TP120 TPAD28-1-GP-U
C ()**+,-.-)./(0%123 (R) CFG18 RSVD_L12 W8 TP_RSVD_W8 1 TP121 TPAD28-1-GP-U
C
24,49,51 H_PROCHOT_N
2
!"#$%"&%"' H_TCK D39 RSVD_W8 R33 TP_RSVD_R33 1 TP122 TPAD28-1-GP-U !"#$%"&%"'
()**+,-.*.-/.0,1234 H_TDI
H_TDO
H_TMS
F38
F39
E39
TCK
TDI
TDO
RSVD_R33
RSVD_P33
VCC_SENSE
P33
E40
TP_RSVD_P33
VCC_SENSE
1 TP123 TPAD28-1-GP-U
!"#$%&'!()*%(+) 6BC?5DE>FE4G"H#IJ,5%8,-.*.-/.0
TMS N33
47 +V_SM_VREF_CNT
1 H_TRST_N E37
0!&1 VSS J11
TPAD28-1-GP-U TP101 1 H_PRDY_N L39 TRST# VSS M9
TPAD28-1-GP-U TP102 1 H_PREQ_N L37 PRDY# VSS J7 HSW_PCUDEBUG_0 R784 1 (R) 2 1KR2J-1-GP
FP_RST_DBR_N TPAD28-1-GP-U TP104 1 R267 2 0R0402-PAD G40 PREQ# VSS F40 VSS_SENSE
XDP_DBRESET_N DBR# VSS_SENSE HSW_PCUDEBUG_1 R785 1 (R) 2 1KR2J-1-GP
R571 2 1 49D9R2F-GP TESTLOW_2 N5 N35 V_1P05_PECI_VCOM 1 TP170 TPAD28-1-GP-U
1 TP_RSVD_K8 K8 TESTLO_N5 RSVD_N35 W6 CK_DPNS_R_DN HSW_PCUDEBUG_2 R786 1 (R) 2 1KR2J-1-GP
TPAD28-1-GP-U TP140 1 TP_RSVD_J10 J10 RSVD_TP_K8 DPLL_REF_CLK# W5 CK_DPNS_R_DP
TPAD28-1-GP-U TP141 RSVD_TP_J10 DPLL_REF_CLK H40 TPEV_CFG_RCOMP
CFG_RCOMP
HSW_PCUDEBUG_3 R787 1 (R) 2 1KR2J-1-GP
1
HASWE1NFU
(62.10055.761) R543 HSW_PCUDEBUG_4 R788 1 (R) 2 1KR2J-1-GP
49D9R2F-GP
2
THERMAL HSW_PCUDEBUG_8 R792 1 (R) 2 1KR2J-1-GP
H_PROCHOT_N R266 1 2 0R0402-PAD H_PROCHOT_R_N !"#$%"&%"' HSW_PCUDEBUG_10 R795 1 (R) 2 1KR2J-1-GP
H_THERMTRIP_N R88 1 2 0R0402-PAD CPU_THERMTRIP_N ()**+,-.*.-/.0,1234,5%67,5%8,9+: HSW_PCUDEBUG_11 R798 1 (R) 2 1KR2J-1-GP
B HSW_PCUDEBUG_12 R799 1 (R) 2 1KR2J-1-GP B

P_CPU_VCCIO 3D3V_S0 PLace Near XDP CONN
P_CPU_VCCIO R379 1 (R) 2 51R2J-2-GP H_TDI
1
1
R2216 (R) R376 1 (R) 2 51R2J-2-GP H_TMS
51R2F-2-GP R2218 PLace Near CPU
249R2F-GP R395 1 2 51R2J-2-GP H_TCK
2
2
H_TDO H_TCK TERMINATION PLACE
NEAR CPU WITHIN 1.1 INCH HSW_PCUDEBUG_13 R806 1 2 1KR2J-1-GP HSW_STRAP_13 ()"*+,-./
1
1
(R) (R) R364 1 2 51R2J-2-GP H_TRST_N
R2217 R2219
825R2F-GP 100R2F-L1-GP-U PLace Any where VCC_SENSE R544 1 (R) 2 49D9R2F-GP VSS_SENSE
2
!"#$%&'%#(&)*!&+,'' HSW_PCUSTB_0_DP R807 1 (R) 2 1KR2J-1-GP
HSW_PCUSTB_0_DN R808 1 (R) 2 1KR2J-1-GP
HSW_PCUSTB_1_DP R809 1 (R) 2 1KR2J-1-GP
HSW_PCUSTB_1_DN R810 1 (R) 2 1KR2J-1-GP
XDP_DBRESET_N
CLOSE TO CPU
1
C560
SCD1U16V2ZY-2GP
2
A A
<Core Design>
Wistron Corporation
Title
CPU uLGA (VCORE/XDP)

Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
"$# !"#$%"&%"$
'())*+,-.-/-+01234#5+)*678.
20 DMI_IT_MR_DP[0..3] !"#$%"&%"'
CPU1C 3 OF 10
20 DMI_IT_MR_DN[0..3] ()**+,-..,/0,.12131,4/56
CPU1D 4 OF 10
HASWELL A12 V_VCCIOA_LOAD
20 DMI_MT_IR_DP[0..3] PEG_TX0 HASWELL
E15 B12 E17 DDSP_B_TX_DATA0
20 DMI_MT_IR_DN[0..3] PEG_RX0 PEG_TX#0 DDIB_TXB0
F15 F17 DDSP_B_TX_DATA0#
PEG_RX#0 DDIB_TXB#0
1
D B11 FDI_CSYNC D16 F18 DDSP_B_TX_DATA1 D
D14 PEG_TX1 C11 R475 FDI_CSYNC DDIB_TXB1 G18 DDSP_B_TX_DATA1#
PEG_RX1 PEG_TX#1 DDIB_TXB#1
E14
PEG_RX#1
24D9R2F-L-GP FDI_INT D18
FDI_INT DP
C10 G19 DDSP_B_TX_DATA2
!"# E13 PEG_TX2 D10 DDIB_TXB2 H19 DDSP_B_TX_DATA2#
2
F13 PEG_RX2 PEG_TX#2 FDI_COMP R4 DDIB_TXB#2 F20 DDSP_B_TX_DATA3
20 FDI_CSYNC PEG_RX#2 DP_COMP DDIB_TXB3
20 FDI_INT B9 G20 DDSP_B_TX_DATA3#
D12 PEG_TX3 C9 CK_DP_DN U5 DDIB_TXB#3
20 FDI_TX_DN[0..1] PEG_RX3 PEG_TX#3 SSC_DPLL_REF_CLK# #$="&%$#,()**+,>..,/0,9)?,#@
E12 CK_DP_DP U6 D19 DDSP_C_TX_DATA0
20 FDI_TX_DP[0..1] PEG_RX#3 C8 SSC_DPLL_REF_CLK DDIC_TXC0 E19 DDSP_C_TX_DATA0#
E11 PEG_TX4 D8 1 DISP_UTIL_CPU E16 DDIC_TXC#0 C20 DDSP_C_TX_DATA1
18 CK_DP_DP PEG_RX4 PEG_TX#4 EDP_DISP_UTIL DDIC_TXC1
F11 TPAD28-1-GP-U TP72 D20 DDSP_C_TX_DATA1#
18 CK_DP_DN PEG_RX#4 $!# DDIC_TXC#1
PEG_TX5
B7 TP_DISP_K11 K11
RSVD_TP_K11 DP
F10 C7 TP_DISP_J12 J12 D21 DDSP_C_TX_DATA2
G10 PEG_RX5 PEG_TX#5 RSVD_TP_J12 DDIC_TXC2 E21 DDSP_C_TX_DATA2#
E9 PEG_RX#5 A6 DDIC_TXC#2 C22 DDSP_C_TX_DATA3
F9 PEG_RX6 PEG_TX6 B6 FDI_TX_DN0 B14 DDIC_TXC3 D22 DDSP_C_TX_DATA3#
"% F8 PEG_RX#6
PEG_RX7
PEG_TX#6 FDI_TX_DP0 A14 FDI0_TX0#0
FDI0_TX00
DDIC_TXC#3
G8 B5 B15 DDSP_D_TX_DATA0
D3 PEG_RX#7 PEG_TX7 C5 FDI_TX_DN1 C13 DDID_TXD0 C15 DDSP_D_TX_DATA0#
32 DDSP_B_TX_DATA0 D4 PEG_RX8 PEG_TX#7 FDI_TX_DP1 B13 FDI0_TX0#1 DDID_TXD#0 A16 DDSP_D_TX_DATA1
32 DDSP_B_TX_DATA0# E4 PEG_RX#8 E1 FDI0_TX01 DDID_TXD1 B16 DDSP_D_TX_DATA1#
C 32 DDSP_B_TX_DATA1 PEG_RX9 PEG_TX8 DDID_TXD#1 C
32 DDSP_B_TX_DATA1#
E5
PEG_RX#9 PEG_TX#8
E2 eDP
F5 B17 DDSP_D_TX_DATA2
32 DDSP_B_TX_DATA2 F6 PEG_RX10 F2 DDID_TXD2 C17 DDSP_D_TX_DATA2#
32 DDSP_B_TX_DATA2# G4 PEG_RX#10 PEG_TX9 F3 DDID_TXD#2 A18 DDSP_D_TX_DATA3
32 DDSP_B_TX_DATA3 G5 PEG_RX11 PEG_TX#9 DDID_TXD3 B18 DDSP_D_TX_DATA3#
32 DDSP_B_TX_DATA3# H5 PEG_RX#11 G1 DDID_TXD#3
H6 PEG_RX12 PEG_TX10 G2
PEG_RX#12 PEG_TX#10 !"#$%"7%#8
$&1')/'!2 J4 HASWE1NFU
J5 PEG_RX13 H2 ()**+,-..,1/0,9:;<3+);
32 DDSP_C_TX_DATA0 PEG_RX#13 PEG_TX11 (62.10055.761)
K5 H3
32 DDSP_C_TX_DATA0# K6 PEG_RX14 PEG_TX#11
32 DDSP_C_TX_DATA1 L4 PEG_RX#14 J1
32 DDSP_C_TX_DATA1# V_VCCIOA_LOAD L5 PEG_RX15 PEG_TX12 J2
32 DDSP_C_TX_DATA2 PEG_RX#15 PEG_TX#12 K2
32 DDSP_C_TX_DATA2# DMI_IT_MR_DP0 U3 PEG_TX13 K3
32 DDSP_C_TX_DATA3 DMI_IT_MR_DN0 T3 DMI_RX0 PEG_TX#13 M2
32 DDSP_C_TX_DATA3# DMI_IT_MR_DP1 U1 DMI_RX#0 PEG_TX14 M3
DMI_IT_MR_DN1 V1 DMI_RX1 PEG_TX#14 L1
DMI_RX#1 PEG_TX15
1
L2 DDSP_D_TX_DATA0 SCD1U16V2KX-3GP 2 (U)1 C15 DDSP_D_TX_DATA0_N

R297 DMI_IT_MR_DP2 W2 PEG_TX#15 DDSP_D_TX_DATA0# SCD1U16V2KX-3GP 2 (U)1 C16 DDSP_D_TX_DATA0#_N
DMI_IT_MR_DN2 V2 DMI_RX2 AA4 DMI_MT_IR_DP0
24D9R2F-L-GP
DMI_IT_MR_DP3 Y3 DMI_RX#2
!"#
DMI_TX0 AA5 DMI_MT_IR_DN0 !"# DDSP_D_TX_DATA1 SCD1U16V2KX-3GP 2 (U)1 C17 DDSP_D_TX_DATA1_N $%&'()*
B DMI_IT_MR_DN3 W3 DMI_RX3 DMI_TX#0 DDSP_D_TX_DATA1# SCD1U16V2KX-3GP 2 (U)1 C18 DDSP_D_TX_DATA1#_N B
&"%
2
DMI_RX#3 AB3 DMI_MT_IR_DP1

TPAD28-1-GP-U TP35 1 TP_PEG_D1 D1 DMI_TX1 AB4 DMI_MT_IR_DN1
%&',-./.0 TPAD28-1-GP-U TP36 1 TP_PEG_C2 C2 RSVD_TP_D1 DMI_TX#1
28 DDSP_D_TX_DATA0# TPAD28-1-GP-U TP37 1 TP_PEG_B3 B3 RSVD_TP_C2 AC5 DMI_MT_IR_DP2
28 DDSP_D_TX_DATA0 TPAD28-1-GP-U TP39 1 TP_PEG_A4 A4 RSVD_TP_B3 DMI_TX2 AC4 DMI_MT_IR_DN2
28 DDSP_D_TX_DATA1# RSVD_TP_A4 DMI_TX#2
28 DDSP_D_TX_DATA1 PEG_COMP P3 AC1 DMI_MT_IR_DP3
28 DDSP_D_TX_DATA2# PEG_RCOMP DMI_TX3 AC2 DMI_MT_IR_DN3
28 DDSP_D_TX_DATA2 DMI_TX#3
28 DDSP_D_TX_DATA3#
28 DDSP_D_TX_DATA3 HASWE1NFU
%&'()*+ (62.10055.761)
29 DDSP_D_TX_DATA0#_N
29 DDSP_D_TX_DATA0_N
<Core Design>
A Wistron Corporation A
Title
CPU uLGA (DMI/FDI)

Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
!!"#!$%$
15 M_A_DQ[0..63]
16 M_B_DQ[0..63]
15 M_A_DQS[0..7]
15 M_A_DQS#[0..7]
16 M_B_DQS[0..7]
16 M_B_DQS#[0..7]
!"#$%"&%#"
D
!!"#&-!.$!! '())*+,-./01+2344+516+/.71+819181/:1+);*96 D
15 M_A_A[0..15]
16 M_B_A[0..15]
15 M_A_WE#
15 M_A_CAS#
15 M_A_RAS#
15 M_A_BS0 1 OF 10
CPU1A
15 M_A_BS1 2 OF 10
CPU1B
15 M_A_BS2 AD38 HASWELL AU13
M_A_DQ0 M_A_A0
M_A_DQ1 AD39 SA_DQ0 SA_MA0 AV16 M_A_A1 M_B_DQ0 AE34 HASWELL AL19 M_B_A0
16 M_B_WE# SA_DQ1 SA_MA1 SB_DQ0 SB_MA0
M_A_DQ2 AF38 AU16 M_A_A2 M_B_DQ1 AE35 AK23 M_B_A1
16 M_B_CAS# AF39 SA_DQ2 SA_MA2 AW17 AG35 SB_DQ1 SB_MA1 AM22
M_A_DQ3 M_A_A3 M_B_DQ2 M_B_A2
16 M_B_RAS# SA_DQ3 SA_MA3 SB_DQ2 SB_MA2
M_A_DQ4 AD37 AU17 M_A_A4 M_B_DQ3 AH35 AM23 M_B_A3
16 M_B_BS0 AD40 SA_DQ4 SA_MA4 AW18 AD34 SB_DQ3 SB_MA3 AP23
M_A_DQ5 M_A_A5 M_B_DQ4 M_B_A4
16 M_B_BS1 SA_DQ5 SA_MA5 SB_DQ4 SB_MA4
M_A_DQ6 AF37 AV17 M_A_A6 M_B_DQ5 AD35 AL23 M_B_A5
16 M_B_BS2 SA_DQ6 SA_MA6 SB_DQ5 SB_MA5
M_A_DQ7 AF40 AT18 M_A_A7 M_B_DQ6 AG34 AY24 M_B_A6
M_A_DQ9 AH40 SA_DQ7 SA_MA7 AU18 M_A_A8 M_B_DQ7 AH34 SB_DQ6 SB_MA6 AV25 M_B_A7
M_A_DQ13 AH39 SA_DQ8 SA_MA8 AT19 M_A_A9 M_B_DQ8 AL34 SB_DQ7 SB_MA7 AU26 M_B_A8
M_A_DQ10 AK38 SA_DQ9 SA_MA9 AW11 M_A_A10 M_B_DQ9 AL35 SB_DQ8 SB_MA8 AW25 M_B_A9
M_A_DQ11 AK39 SA_DQ10 SA_MA10 AV19 M_A_A11 M_B_DQ10 AK31 SB_DQ9 SB_MA9 AP18 M_B_A10
!!"#&%"' M_A_DQ12 AH37 SA_DQ11
SA_DQ12
SA_MA11
SA_MA12
AU19 M_A_A12 M_B_DQ11 AL31 SB_DQ10
SB_DQ11
SB_MA10
SB_MA11
AY25 M_B_A11
M_A_DQ8 AH38 AY10 M_A_A13 M_B_DQ12 AK34 AV26 M_B_A12
15 M_A_DIM0_CS#0 M_A_DQ14 AK37 SA_DQ13 SA_MA13 AT20 M_A_A14 M_B_DQ13 AK35 SB_DQ12 SB_MA12 AR15 M_B_A13
15 M_A_DIM0_CS#1 M_A_DQ15 AK40 SA_DQ14 SA_MA14 AU21 M_A_A15 M_B_DQ14 AK32 SB_DQ13 SB_MA13 AV27 M_B_A14
M_A_DQ17 AM40 SA_DQ15 SA_MA15 M_B_DQ15 AL32 SB_DQ14 SB_MA14 AY28 M_B_A15
M_A_DQ21 AM39 SA_DQ16 AW10 M_A_DIM0_ODT0 M_B_DQ17 AN34 SB_DQ15 SB_MA15
15 M_A_DIM0_CKE0 AP38 SA_DQ17 SA_ODT0 AY8 AP34 SB_DQ16 AM17
M_A_DQ18 M_A_DIM0_ODT1 M_B_DQ21 M_B_DIM0_ODT0
15 M_A_DIM0_CKE1 SA_DQ18 SA_ODT1 SB_DQ17 SB_ODT0
M_A_DQ19 AP39 AW9 M_B_DQ19 AN31 AL16 M_B_DIM0_ODT1
M_A_DQ20 AM37 SA_DQ19 SA_ODT2 AU8 M_B_DQ23 AP31 SB_DQ18 SB_ODT1 AM16
SA_DQ20 SA_ODT3 !"#$%"&%#" SB_DQ19 SB_ODT2
M_A_DQ16 AM38 M_B_DQ20 AN35 AK15 !"#$%"&%#"
15 M_A_DIM0_ODT0
M_A_DQ22 AP37 SA_DQ21 '())*+,-. M_B_DQ16 AP35 SB_DQ20 SB_ODT3
15 M_A_DIM0_ODT1
M_A_DQ23 AP40 SA_DQ22 AW33 M_B_DQ18 AN32 SB_DQ21 AM26
'())*+,-.
M_A_DQ25 AV37 SA_DQ23 SA_ECC_CB0 AV33 M_B_DQ22 AP32 SB_DQ22 SB_ECC_CB0 AM25
C C
M_A_DQ29 AW37 SA_DQ24 SA_ECC_CB1 AU31 M_B_DQ25 AM29 SB_DQ23 SB_ECC_CB1 AP25
16 M_B_DIM0_CS#0 M_A_DQ26 AU35 SA_DQ25 SA_ECC_CB2 AV31 M_B_DQ28 AM28 SB_DQ24 SB_ECC_CB2 AP26
16 M_B_DIM0_CS#1 M_A_DQ27 AV35 SA_DQ26 SA_ECC_CB3 AT33 M_B_DQ27 AR29 SB_DQ25 SB_ECC_CB3 AL26
M_A_DQ28 AT37 SA_DQ27 SA_ECC_CB4 AU33 M_B_DQ30 AR28 SB_DQ26 SB_ECC_CB4 AL25
M_A_DQ24 AU37 SA_DQ28 SA_ECC_CB5 AT31 M_B_DQ24 AL29 SB_DQ27 SB_ECC_CB5 AR26
16 M_B_DIM0_CKE0 AT35 SA_DQ29 SA_ECC_CB6 AW31 SB_DQ28 SB_ECC_CB6
16 M_B_DIM0_CKE1
M_A_DQ30
SA_DQ30 SA_ECC_CB7
Can be left as no connects M_B_DQ29 AL28
SB_DQ29 SB_ECC_CB7
AR25 Can be left as no connects
M_A_DQ31 AW35 if no support ECC. M_B_DQ26 AP29 if no support ECC.
M_A_DQ33 AY6 SA_DQ31 AV12 M_A_BS0 M_B_DQ31 AP28 SB_DQ30 AK17 M_B_BS0
M_A_DQ37 AU6 SA_DQ32 SA_BS0 AY11 M_A_BS1 M_B_DQ32 AR12 SB_DQ31 SB_BS0 AL18 M_B_BS1
16 M_B_DIM0_ODT0 SA_DQ33 SA_BS1 SB_DQ32 SB_BS1
M_A_DQ34 AV4 AT21 M_A_BS2 M_B_DQ33 AP12 AW28 M_B_BS2
16 M_B_DIM0_ODT1 AU4 SA_DQ34 SA_BS2 AL13 SB_DQ33 SB_BS2
M_A_DQ35 M_B_DQ34
M_A_DQ36 AW6 SA_DQ35 AV22 M_A_DIM0_CKE0 M_B_DQ35 AL12 SB_DQ34 AW29 M_B_DIM0_CKE0
M_A_DQ32 AV6 SA_DQ36 SA_CKE0 AT23 M_A_DIM0_CKE1 M_B_DQ36 AR13 SB_DQ35 SB_CKE0 AY29 M_B_DIM0_CKE1
M_A_DQ38 AW4 SA_DQ37 SA_CKE1 AU22 M_B_DQ37 AP13 SB_DQ36 SB_CKE1 AU28
SA_DQ38 SA_CKE2 !"#$%"&%#" SB_DQ37 SB_CKE2
M_A_DQ39 AY4 AU23 M_B_DQ38 AM13 AU29 !"#$%"&%#"
M_A_DQ41 AR1 SA_DQ39 SA_CKE3 '())*+,-. M_B_DQ39 AM12 SB_DQ38 SB_CKE3
M_A_DQ45 AR4 SA_DQ40 AU14 M_A_DIM0_CS#0 M_B_DQ45 AR9 SB_DQ39 '())*+,-.
M_A_DQ42 AN3 SA_DQ41 SA_CS#0 AV9 M_A_DIM0_CS#1 M_B_DQ41 AP9 SB_DQ40
!!"#&'(&) M_A_DQ43 AN4 SA_DQ42
SA_DQ43
SA_CS#1
SA_CS#2
AU10 !"#$%"&%#" M_B_DQ47 AR6 SB_DQ41
SB_DQ42
M_A_DQ44 AR2 AW8 M_B_DQ43 AP6
15 M_A_DIM0_CLK_DDR0 M_A_DQ40 AR3 SA_DQ44 SA_CS#3 '())*+,-. M_B_DQ44 AR10 SB_DQ43 AP17 M_B_DIM0_CS#0
15 M_A_DIM0_CLK_DDR#0 M_A_DQ46 AN2 SA_DQ45 AY15 M_A_DIM0_CLK_DDR0 M_B_DQ40 AP10 SB_DQ44 SB_CS#0 AN15 M_B_DIM0_CS#1
15 M_A_DIM0_CLK_DDR1 M_A_DQ47 AN1 SA_DQ46 SA_CK0 AY16 M_A_DIM0_CLK_DDR#0 M_B_DQ46 AR7 SB_DQ45 SB_CS#1 AN17
15 M_A_DIM0_CLK_DDR#1 SA_DQ47 SA_CK#0 SB_DQ46 SB_CS#2 !"#$%"&%#"
M_A_DQ49 AL1 AW15 M_A_DIM0_CLK_DDR1 M_B_DQ42 AP7 AL15
M_A_DQ53 AL4 SA_DQ48 SA_CK1 AV15 M_A_DIM0_CLK_DDR#1 M_B_DQ52 AM9 SB_DQ47 SB_CS#3 '())*+,-.
M_A_DQ50 AJ3 SA_DQ49 SA_CK#1 AV14 M_B_DQ53 AL9 SB_DQ48 AM20 M_B_DIM0_CLK_DDR0
16 M_B_DIM0_CLK_DDR0 SA_DQ50 SA_CK2 !"#$%"&%#" SB_DQ49 SB_CK0
M_A_DQ51 AJ4 AW14 M_B_DQ50 AL6 AM21 M_B_DIM0_CLK_DDR#0
16 M_B_DIM0_CLK_DDR#0 M_A_DQ52 AL2 SA_DQ51 SA_CK#2 AW13
'())*+,-. M_B_DQ55 AL7 SB_DQ50 SB_CK#0 AP22 M_B_DIM0_CLK_DDR1
16 M_B_DIM0_CLK_DDR1 M_A_DQ48 AL3 SA_DQ52 SA_CK3 AY13 M_B_DQ48 AM10 SB_DQ51 SB_CK1 AP21 M_B_DIM0_CLK_DDR#1
16 M_B_DIM0_CLK_DDR#1 M_A_DQ54 AJ2 SA_DQ53 SA_CK#3 M_B_DQ49 AL10 SB_DQ52 SB_CK#1
M_A_DQ55 AJ1 SA_DQ54 AW12 TP_RSVD_AW12 1 TP34 TPAD28-1-GP-U M_B_DQ54 AM6 SB_DQ53 AN20
SA_DQ55 RSVD_AW12 SB_DQ54 SB_CK2 !"#$%"&%#"
M_A_DQ57 AG1 M_B_DQ51 AM7 AN21
M_A_DQ61 AG4 SA_DQ56 M_B_DQ61 AH6 SB_DQ55 SB_CK#2 AP19
'())*+,-.
M_A_DQ58 AE3 SA_DQ57 M_B_DQ60 AH7 SB_DQ56 SB_CK3 AP20
M_A_DQ59 AE4 SA_DQ58 M_B_DQ59 AE6 SB_DQ57 SB_CK#3
M_A_DQ60 AG2 SA_DQ59 M_B_DQ63 AE7 SB_DQ58 AP16 M_B_CAS#
B
!!"#(%*+", M_A_DQ56 AG3 SA_DQ60
SA_DQ61
M_B_DQ56 AJ6 SB_DQ59
SB_DQ60
SB_CAS#
RSVD_AL20
AL20
B
M_A_DQ62 AE2 M_B_DQ57 AJ7 AM18 M_B_RAS#
47 SM_DRAMRST# M_A_DQ63 AE1 SA_DQ62 M_B_DQ58 AF6 SB_DQ61 SB_RAS# AK16 M_B_WE#
M_A_DQS0 AE39 SA_DQ63 M_B_DQ62 AF7 SB_DQ62 SB_WE#
47 M_VREF_DQ_DIMM1_C SA_DQS0 SB_DQ63
M_A_DQS1 AJ39 M_B_DQS0 AF35 AB39 M_VREF_DQ_DIMM0_C
47 M_VREF_DQ_DIMM0_C SA_DQS1 SB_DQS0 SA_DIMM_VREFDQ
M_A_DQS2 AN39 M_B_DQS1 AL33 AB40 M_VREF_DQ_DIMM1_C
M_A_DQS3 AV36 SA_DQS2 M_B_DQS2 AP33 SB_DQS1 SB_DIMM_VREFDQ
M_A_DQS4 AV5 SA_DQS3 M_B_DQS3 AN28 SB_DQS2
M_A_DQS5 AP3 SA_DQS4 M_B_DQS4 AN12 SB_DQS3
SA_DQS5 SB_DQS4
1
M_A_DQS6 AK3 AU12 M_A_RAS# M_B_DQS5 AP8 C495 C464
M_A_DQS7 AF3 SA_DQS6 SA_RAS# M_B_DQS6 AL8 SB_DQS5 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
AV32 SA_DQS7 AU11 M_A_WE# M_B_DQS7 AG7 SB_DQS6
2
M_A_DQS#0 AE38 SA_DQS8 SA_WE# AN25 SB_DQS7
M_A_DQS#1 AJ38 SA_DQS#0 AV20 TP_RSVD_AV20 1 TP32 TPAD28-1-GP-U M_B_DQS#0 AF34 SB_DQS8
M_A_DQS#2 AN38 SA_DQS#1 RSVD_AV20 M_B_DQS#1 AK33 SB_DQS#0
M_A_DQS#3 AU36 SA_DQS#2 AW27 TP_RSVD_AW27 1 TP33 TPAD28-1-GP-U M_B_DQS#2 AN33 SB_DQS#1
M_A_DQS#4 AW5 SA_DQS#3 RSVD_AW27 M_B_DQS#3 AN29 SB_DQS#2
M_A_DQS#5 AP2 SA_DQS#4 AU9 M_A_CAS# M_B_DQS#4 AN13 SB_DQS#3
M_A_DQS#6 AK2 SA_DQS#5 SA_CAS# M_B_DQS#5 AR8 SB_DQS#4
M_A_DQS#7 AF2 SA_DQS#6 AK22 SM_DRAMRST# M_B_DQS#6 AM8 SB_DQS#5
AU32 SA_DQS#7 SM_DRAMRST# M_B_DQS#7 AG6 SB_DQS#6
SA_DQS#8 AN26 SB_DQS#7
SB_DQS#8
1
(R)
C474
SCD1U10V2KX-5GP
2
HASWE1NFU
(62.10055.761) HASWE1NFU
(62.10055.761)
A A
<Core Design>
Wistron Corporation
Title
CPU uLGA (DDR)

C
vSuperb -1
5 4 3 2 1
5 4 3 2 1
!"" PCH_1D05V R310 1 2 0R0402-PAD

PCH_1D05V R314 1 (R) 2 0R2J-2-GP
11 VCCST
V_CPU_VCCIO2PCH P_CPU_VCCIO
17,19,24 PWRGD_3V
2
R192 VCC_CORE CPU1F 6 OF 10 VCC_CORE CPU1I 9 OF 10 CPU1G 7 OF 10 CPU1J 10 OF 10
0R0603-PAD-1-GP-U CPU1H 8 OF 10
HASWELL A5 HASWELL AJ5 HASWELL HASWELL
R313 P8 C31 A7 VSS VSS AJ8 AP11 AW32 G3 HASWELL K12 TP_RSVD_K12 1 TP142 TPAD28-1-GP-U
1
1 2 0R0402-PAD V_CPU_VCCIO_OUT L40 VCC VCC C33 A11 VSS VSS AJ34 AP14 VSS VSS AW34 G6 VSS K15 RSVD_TP_K12 J13 TP_RSVD_J13 1 TP143 TPAD28-1-GP-U
VCCST R308 1 (R) 2 0R2J-2-GP VCCIO2PCH AB8 VCCIO_OUT VCC L16 A13 VSS VSS AJ35 AP15 VSS VSS AW36 G7 VSS VSS K16 RSVD_TP_J13
VCCIO2PCH VCC L15 A15 VSS VSS AJ36 AP24 VSS VSS AW7 G12 VSS VSS K32 P37 TP_RSVD_P37 1 TP144 TPAD28-1-GP-U
VCC J35 A17 VSS VSS AJ37 AP27 VSS VSS AY17 G13 VSS VSS L36 TPAD28-1-GP-U TP148 1 TP_RSVD_AY18 AY18 RSVD_TP_P37 N38 TP_RSVD_N38 1 TP145 TPAD28-1-GP-U
VCC VSS VSS VSS VSS VSS VSS RSVD_AY18 RSVD_TP_N38
1
L31 H33 A23 AJ40 AP30 AY23 G14 M4 TPAD28-1-GP-U TP149 1 TP_RSVD_AW24 AW24
C28 VCC_CORE VCC VCC VSS VSS VSS VSS VSS VSS RSVD_AW24
C35 L18 H35 AA3 AK1 AP36 AY26 G15 M5 TPAD28-1-GP-U TP150 1 TP_RSVD_AW23 AW23 R36 TP_RSVD_R36 1 TP146 TPAD28-1-GP-U
SCD1U16V2ZY-2GP SC4D7U6D3V3KX-GP L17 VCC VCC J21 AA6 VSS VSS AK4 AP4 VSS VSS AY27 G16 VSS VSS M6 TPAD28-1-GP-U TP151 1 TP_RSVD_AV29 AV29 RSVD_AW23 RSVD_TP_R36 C39 TP_RSVD_C39 1 TP147 TPAD28-1-GP-U
2
J33 VCC VCC J22 AA7 VSS VSS AK5 AP5 VSS VSS AY30 G17 VSS VSS M7 TPAD28-1-GP-U TP152 1 TP_RSVD_AV24 AV24 RSVD_AV29 RSVD_TP_C39
A24 VCC VCC J23 AA8 VSS VSS AK6 AR11 VSS VSS AY5 G21 VSS VSS TPAD28-1-GP-U TP153 1 TP_RSVD_AU39 AU39 RSVD_AV24 U35
A25 VCC VCC J24 AA33 VSS VSS AK7 AR14 VSS VSS AY7 G36 VSS M35 TPAD28-1-GP-U TP154 1 TP_RSVD_AU27 AU27 RSVD_AU39 VSS P40
D A26 VCC VCC J25 AA35 VSS VSS AK8 AR16 VSS VSS B24 G37 VSS VSS M40 TPAD28-1-GP-U TP155 1 TP_RSVD_AU1 AU1 RSVD_AU27 VSS D
A27 VCC VCC J26 AA38 VSS VSS AK9 AR17 VSS VSS B26 H1 VSS VSS N1 TPAD28-1-GP-U TP164 1 TP_RSVD_AT40 AT40 RSVD_AU1 R38
A28 VCC VCC J27 AB5 VSS VSS AK10 AR18 VSS VSS B28 H4 VSS VSS N2 TPAD28-1-GP-U TP160 1 TP_RSVD_AK20 AK20 RSVD_AT40 VSS T37
A29 VCC VCC J28 AB7 VSS VSS AK11 AR19 VSS VSS B30 H7 VSS VSS N3 VCCST_PWRGD Y7 RSVD_AK20 VSS V34
A30 VCC VCC J29 AB34 VSS VSS AK12 AR20 VSS VSS B34 H8 VSS VSS N4 TPAD28-1-GP-U TP162 1 TP_RSVD_T34 T34 RSVD_Y7 VSS
G33 VCC VCC J30 AB37 VSS VSS AK13 AR21 VSS VSS B36 H9 VSS VSS N6 TPAD28-1-GP-U TP163 1 TP_RSVD_R34 R34 RSVD_T34 R39
B25 VCC VCC J32 AC3 VSS VSS AK14 AR22 VSS VSS B4 H10 VSS VSS N7 TPAD28-1-GP-U TP156 1 TP_RSVD_J40 J40 RSVD_R34 VSS
B27 VCC VCC J34 AC6 VSS VSS AK18 AR23 VSS VSS B8 H11 VSS VSS N8 TPAD28-1-GP-U TP157 1 TP_RSVD_J17 J17 RSVD_J40 T38
B29 VCC VCC K19 AC7 VSS VSS AK19 AR24 VSS VSS C4 H13 VSS VSS TPAD28-1-GP-U TP158 1 TP_RSVD_J15 J15 RSVD_J17 VSS U36
B31 VCC VCC K21 AC33 VSS VSS AK24 AR27 VSS VSS C6 H17 VSS N34 TPAD28-1-GP-U TP159 1 TP_RSVD_H12 H12 RSVD_J15 VSS P39
J31 VCC VCC K23 AC34 VSS VSS AK25 AR30 VSS VSS C12 H18 VSS VSS RSVD_H12 VSS
B33 VCC VCC K25 AC35 VSS VSS AK26 AR31 VSS VSS C14 H20 VSS T36
G31 VCC VCC K27 AC36 VSS VSS AK27 AR32 VSS VSS C16 H21 VSS P2 VSS R37
B35 VCC VCC K29 AC37 VSS VSS AK28 AR33 VSS VSS C18 H22 VSS VSS P5 VSS
C24 VCC VCC K31 AC38 VSS VSS AK29 AR34 VSS VSS C19 H24 VSS VSS P7 J14
C25 VCC VCC M13 AC39 VSS VSS AK30 AR35 VSS VSS C21 H26 VSS VSS P34 VSS N36 TP_CPU_N36 1 TP165 TPAD28-1-GP-U
C26 VCC VCC K33 AC40 VSS VSS AK36 AR36 VSS VSS C23 H28 VSS VSS P35 RSVD_TP_N36
C27 VCC VCC K35 AD1 VSS VSS AL5 AR37 VSS VSS C36 H30 VSS VSS P38
C28 VCC VCC L19 AD2 VSS VSS AL11 AR38 VSS VSS B10 H32 VSS VSS R3
C29 VCC VCC L20 AD3 VSS VSS AL14 AR39 VSS VSS B23 H34 VSS VSS R5 HASWE1NFU
C30 VCC VCC L21 AD4 VSS VSS AL17 AR40 VSS VSS C3 H36 VSS VSS R6
VCC VCC VSS VSS VSS VSS VSS VSS (62.10055.761)
C32 L22 AD5 AL21 AR5 D9 H39 R7
C34 VCC VCC L23 AD6 VSS VSS AL22 AT1 VSS VSS D11 J3 VSS VSS R8
C35 VCC VCC L24 AD7 VSS VSS AL24 AT10 VSS VSS D13 J6 VSS VSS R35
D25 VCC VCC L25 AD8 VSS VSS AL27 AT11 VSS VSS D15 J18 VSS VSS R40
VCCST_PWRGD
D27 VCC VCC L26 AD33 VSS VSS AL30 AT12 VSS VSS D17 J19 VSS VSS T1
D29 VCC VCC L27 AD36 VSS VSS AL36 AT13 VSS VSS D2 J20 VSS VSS T2
D31 VCC VCC L28 AE5 VSS VSS AL37 AT14 VSS VSS D23 J36 VSS VSS T4
E33 VCC VCC L29 AE8 VSS VSS AL38 AT15 VSS VSS D24 J37 VSS VSS T5
D33 VCC VCC L30 AE33 VSS VSS AL39 AT16 VSS VSS D26 K1 VSS VSS T6
E31 VCC VCC L32 AE36 VSS VSS AL40 AT2 VSS VSS D28 K4 VSS VSS T7
D35 VCC VCC L33 AE37 VSS VSS AM1 AT24 VSS VSS D30 K7 VSS VSS T33
VCC VCC VSS VSS VSS VSS VSS VSS R2232 R2230
E24 M17 AE40 AM2 AT25 D34 K10 T39
E25 VCC VCC M15 AF1 VSS VSS AM3 AT26 VSS VSS D36 K14 VSS VSS U2 1 2 1 2 PWRGD_3V
E26 VCC VCC M19 AF4 VSS VSS AM4 AT27 VSS VSS D37 K17 VSS VSS U4
E28 VCC VCC M23 AF8 VSS VSS AM11 AT29 VSS VSS D6 K20 VSS VSS U33 2K67R2F-2-GP 6K04R2F-GP
E30 VCC VCC M27 AF36 VSS VSS AM15 AT30 VSS VSS E7 K24 VSS VSS U37
E32 VCC VCC M29 AG5 VSS VSS AM19 AT32 VSS VSS E8 K26 VSS VSS V3
E34 VCC VCC M33 AG8 VSS VSS AM24 AT34 VSS VSS E10 K28 VSS VSS V6
F23 VCC VCC AG33 VSS VSS AM27 AT36 VSS VSS E18 K30 VSS VSS V8
F25 VCC AJ12 AG36 VSS VSS AM30 AT38 VSS VSS E3 K34 VSS VSS V33
VCC VDDQ 1D5V_S3 VSS VSS VSS VSS VSS VSS
F27 AJ13 AG37 AM31 AT39 E20 K36 V40
F29 VCC VDDQ AJ15 AG38 VSS VSS AM32 AT4 VSS VSS E22 K40 VSS VSS W1
F31 VCC VDDQ AJ17 AG39 VSS VSS AM33 AT5 VSS VSS E23 L3 VSS VSS W4
E35 VCC VDDQ AJ20 AG40 VSS VSS AM34 AT6 VSS VSS E36 L6 VSS VSS W7
F33 VCC VDDQ AJ21 AH1 VSS VSS AM35 AT7 VSS VSS E38 L7 VSS VSS W33
F35 VCC VDDQ AJ24 AH2 VSS VSS AM36 AT8 VSS VSS B32 L8 VSS VSS W35
G22 VCC VDDQ AJ25 AH3 VSS VSS AN5 AT9 VSS VSS E6 L9 VSS VSS W37
C G23 VCC VDDQ AJ28 AH4 VSS VSS AN6 AU2 VSS VSS F1 L11 VSS VSS Y4 C
G24 VCC VDDQ AJ29 AH5 VSS VSS AN7 AU25 VSS VSS F32 L13 VSS VSS Y5
G25 VCC VDDQ AJ9 AH8 VSS VSS AN8 AU3 VSS VSS F12 L14 VSS VSS Y6
AV39,AW38,AY3,B38,B39,C40,D40
G26 VCC VDDQ AT17 AH33 VSS VSS AN9 AU30 VSS VSS F14 L35 VSS VSS Y33
G27 VCC VDDQ AT22 AH36 VSS VSS AN10 AU34 VSS VSS F16 L38 VSS VSS
G28 VCC VDDQ AU15 AJ11 VSS VSS AN11 AU38 VSS VSS F19 M1 VSS
G32 VCC VDDQ AV10 AJ18 VSS VSS AN18 AV21 VSS VSS F24 M16 VSS AU40
NCTF TEST PIN: AU40,

G34 VCC VDDQ AV11 AJ19 VSS VSS AN19 AV28 VSS VSS F26 M18 VSS VSS_NCTF_AU40 AV39
G35 VCC VDDQ AV13 AJ22 VSS VSS AN22 AV3 VSS VSS F28 M20 VSS VSS_NCTF_AV39 AW38
H23 VCC VDDQ AV18 AJ23 VSS VSS AN23 AV30 VSS VSS F30 M22 VSS VSS_NCTF_AW38 AY3
H25 VCC VDDQ AV23 AJ26 VSS VSS AN24 AV34 VSS VSS F34 M24 VSS VSS_NCTF_AY3 B38
H27 VCC VDDQ AV8 AJ27 VSS VSS AN27 AV38 VSS VSS F36 M26 VSS VSS_NCTF_B38 B39
H29 VCC VDDQ AW16 AJ30 VSS VSS AN30 AV7 VSS VSS F4 M28 VSS VSS_NCTF_B39 C40
H31 VCC VDDQ AY12 AJ31 VSS VSS AN36 AW26 VSS VSS D32 M30 VSS VSS_NCTF_C40 D40
L34 VCC VDDQ AY14 AJ32 VSS VSS AN37 AW3 VSS VSS F7 M32 VSS VSS_NCTF_D40
VCC VDDQ AY9 AJ33 VSS VSS AN40 AW30 VSS VSS G9 M34 VSS
VDDQ VSS VSS AP1 VSS VSS G11 M37 VSS
VSS VSS VSS
HASWE1NFU HASWE1NFU
(62.10055.761) (62.10055.761) HASWE1NFU
(62.10055.761)
HASWE1NFU
(62.10055.761)
CPU Power Capacitor Quantity

PLACE ALL 0805 CAPS INSIDE CPU SOCKET CAVITY Net CAP AMOUNT
VCC_CORE
VCC_CORE Vcore 22uf 0805 22
V_SM 22uf 0805 4+5(R)
1
1
C367 C368 C338 C335 C352 C336 C350
1
B C343 C348 C340 C355 SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP B
SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP
2
2
2
1
C353 C337 C369 C349 C342 C351 C339
SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP
2
2
!"#"$%&'"(!"%&)$(*+,-!"./) 3D3V_S0
1D5V_S3
1
R132
(R) (R) (R) (R) (R) 10KR2F-2-GP
1
C366 C371 C370 C379 C341 C356 C372 C381 C365 (R)
SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP
2
2
Q48
PWR_DEBUG 6 1
11 PWR_DEBUG
2
VR_READY R129 1 (R) 2 10KR2F-2-GP PWR_DEBUG_N 5
11,17,46,51 VR_READY 4 3 PWR_DEBUG_1
VCC_CORE R130 1 (R) 2 10KR2F-2-GP MBT3904DW1T1G-2-GP
1
PLACE CAPS AT TOP SOCKET EDGE (R)
1
(R) (R)
R311 C128
0R2J-2-GP SCD1U16V2ZY-2GP
2
2
P_CPU_VCCIO
VCC_CORE
1
C187
SC4D7U6D3V3KX-GP
2
1
C354 C266 C267 C373

A SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP A
2
<Core Design>
Wistron Corporation
Title
CPU uLGA (VCC)

D
vSuperb -1
5 4 3 2 1
5 4 3 2 1
DIMM1
M_A_A0
M_A_A1
98
97 A0 NP1
NP1
NP2
2013/05/02
A1 NP2
M_A_A2
M_A_A3
96
95 A2
A3 RAS#
110
M_A_RAS# 13
Rossi Change DIMM type follow London2
M_A_A4 92 113
13 M_A_A[15:0]
M_A_A5
M_A_A6
91
90
A4
A5
WE#
CAS#
115
M_A_W E# 13
M_A_CAS# 13 Symbol--> 62.10024.B81
M_A_A7 86 A6 114
13 M_A_DQS#[7:0] A7 CS0# M_A_DIM0_CS#0 13
M_A_A8 89 121 Note:
A8 CS1# M_A_DIM0_CS#1 13
M_A_A9 85
13 M_A_DQS[7:0] 107 A9 73 If SA0 DIM0 = 0, SA1_DIM0 = 0
M_A_A10 M_A_DIM0_CKE0 13
M_A_A11 84 A10/AP CKE0 74
M_A_A12 83 A11 CKE1 M_A_DIM0_CKE1 13 SO-DIMMA SPD Address is 0xA0
D A12 D
M_A_A13 119
A13 CK0
101
M_A_DIM0_CLK_DDR0 13 SO-DIMMA TS Address is 0x30
M_A_A14 80 103
A14 CK0# M_A_DIM0_CLK_DDR#0 13
M_A_A15 78
A15
13 M_A_BS2
79
A16/BA2 CK1
102
M_A_DIM0_CLK_DDR1 13 If SA0 DIM0 = 1, SA1_DIM0 = 0
104
CK1# M_A_DIM0_CLK_DDR#1 13 SO-DIMMA SPD Address is 0xA2
109
13 M_A_BS0 108 BA0 11
13 M_A_BS1 BA1 DM0 28
SO-DIMMA TS Address is 0x32
13 M_A_DQ[63:0] 5 DM1 46
M_A_DQ0
M_A_DQ1 7 DQ0 DM2 63
M_A_DQ2 15 DQ1 DM3 136
M_A_DQ3 17 DQ2 DM4 153
M_A_DQ4 4 DQ3 DM5 170
M_A_DQ5 6 DQ4 DM6 187
M_A_DQ6 16 DQ5 DM7
M_A_DQ7 18 DQ6 200
21 DQ7 SDA 202 SMB_DATA 16,17,23,28,29,38,39,41
M_A_DQ8
M_A_DQ9 23 DQ8
DQ9
SCL SMB_CLK 16,17,23,28,29,38,39,41
3D3V_S0
Thermal EVENT
M_A_DQ10 33 198
DQ10 EVENT# TS#_DIMM0_1 16 3D3V_S0
M_A_DQ11 35
M_A_DQ12 22 DQ11 199
M_A_DQ13 24 DQ12 VDDSPD TS#_DIMM0_1 1R1403 2
M_A_DQ14 34 DQ13 197 C1401 10KR2J-3-GP
DQ14 SA0
1
M_A_DQ15 36 201
SCD1U10V2KX-5GP
M_A_DQ16 39 DQ15 SA1
M_A_DQ17 41 DQ16 77
2
M_A_DQ18 51 DQ17 NC#1 122
M_A_DQ19 53 DQ18 NC#2 125 1D5V_S3
M_A_DQ20 40 DQ19 NC#/TEST
M_A_DQ21 42 DQ20 75
M_A_DQ22 50 DQ21 VDD1 76
C DQ22 VDD2 C
M_A_DQ23 52 81
M_A_DQ24 57 DQ23 VDD3 82 1D5V_S3
M_A_DQ25 59 DQ24 VDD4 87
M_A_DQ26 67 DQ25 VDD5 88
M_A_DQ27 69 DQ26 VDD6 93
SODIMM A DECOUPLING
M_A_DQ28 56 DQ27 VDD7 94
M_A_DQ29 58 DQ28 VDD8 99
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
M_A_DQ30 68 DQ29 VDD9 100
C1403
C1404
C1405
C1406
DQ30 VDD10
1
M_A_DQ31 70 105
M_A_DQ32 129 DQ31 VDD11 106
M_A_DQ33 131 DQ32 VDD12 111
2
M_A_DQ34 141 DQ33 VDD13 112 (R)
M_A_DQ35 143 DQ34 VDD14 117
M_A_DQ36 130 DQ35 VDD15 118
M_A_DQ37 132 DQ36 VDD16 123
M_A_DQ38 140 DQ37 VDD17 124
M_A_DQ39 142 DQ38 VDD18
M_A_DQ40 147 DQ39 2
M_A_DQ41 149 DQ40 VSS 3
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_A_DQ42 157 DQ41 VSS 8
C1416
C1417
DQ42 VSS Layout Note:
1
M_A_DQ43 159 9
M_A_DQ44 146 DQ43 VSS 13 Place these Caps near
M_A_DQ45 148 DQ44 VSS 14
SO-DIMMA.
2
M_A_DQ46 158 DQ45 VSS 19
M_A_DQ47 160 DQ46 VSS 20
M_A_DQ48 163 DQ47 VSS 25
M_A_DQ49 165 DQ48 VSS 26
M_A_DQ50 175 DQ49 VSS 31
M_A_DQ51 177 DQ50 VSS 32
M_A_DQ52 164 DQ51 VSS 37
M_A_DQ53 166 DQ52 VSS 38
B DQ53 VSS B
M_A_DQ54 174 43
M_A_DQ55 176 DQ54 VSS 44
M_A_DQ56 181 DQ55 VSS 48
M_A_DQ57 183 DQ56 VSS 49
M_A_DQ58 191 DQ57 VSS 54
SB
M_A_DQ59 193 DQ58 VSS 55
M_A_DQ60 180 DQ59 VSS 60 DDR_VREF_S3 SB M_VREF_DQ_DIMM0
M_A_DQ61 182 DQ60 VSS 61
M_A_DQ62 192 DQ61 VSS 65
M_A_DQ63 194 DQ62 VSS 66 0D75V_S0 R1404 R1405
DQ63 VSS 71
Place these caps 1 2 1 2
M_A_DQS#0 10 VSS 72 close to VTT1 and 0R0603-PAD-1-GP-U 0R0603-PAD-1-GP-U DDR_W R_VREF01_B4 47
M_A_DQS#1 27 DQS0# VSS 127
M_A_DQS#2 45 DQS1# VSS 128 VTT2.
M_A_DQS#3 62 DQS2# VSS 133 Tracew should be at least 20 mils wide
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DQS3# VSS
1
M_A_DQS#4 135 134
C1419
C1421
DQS4# VSS
1
M_A_DQS#5 152 138 C1411 C1413
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
2
2
DQS7# VSS 145
M_A_DQS0 12 VSS 150
M_A_DQS1 29 DQS0 VSS 151
DQS7 VSS 172
116 VSS 173
13 M_A_DIM0_ODT0 120 ODT0 VSS 178
A A
13 M_A_DIM0_ODT1 ODT1 VSS 179
VSS <Core Design>
126 184
DDR_VREF_S3 VREF_CA VSS
1 185
M_VREF_DQ_DIMM0 VREF_DQ VSS 189
16,47 DDR3_DRAMRST#
30
RESET#
VSS
VSS
190 Wistron Corporation
195 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
VSS 196 Taipei Hsien 221, Taiwan, R.O.C.
203 VSS 205
0D75V_S0 VTT1 VSS
204 206 Title
VTT2 VSS
DDR3-DIMM1
H =8mm DDR3-204P-101-GP-U Custom
(62.10017.K01) vSuperb -1
5 4 3 2 1
5 4 3 2 1
DIMM2
M_B_A0 98 NP1
M_B_A1
M_B_A2
97
96
A0
A1
NP1
NP2
NP2 2013/05/02
A2
M_B_A3
M_B_A4
95
92 A3
A4
RAS#
WE#
110
113
M_B_RAS# 13
M_B_W E# 13
Rossi Change DIMM type follow London2
M_B_A5 91 115
13 M_B_A[15:0]
M_B_A6
M_B_A7
90
86
A5
A6
CAS#
114
M_B_CAS# 13
Symbol--> 62.10017.W31
13 M_B_DQS#[7:0] A7 CS0# M_B_DIM0_CS#0 13
M_B_A8 89 121
A8 CS1# M_B_DIM0_CS#1 13
M_B_A9 85
13 M_B_DQS[7:0] 107 A9 73
M_B_A10 M_B_DIM0_CKE0 13
M_B_A11 84 A10/AP CKE0 74
D A11 CKE1 M_B_DIM0_CKE1 13 D
M_B_A12 83
M_B_A13 119 A12 101
A13 CK0 M_B_DIM0_CLK_DDR0 13
M_B_A14 80 103
A14 CK0# M_B_DIM0_CLK_DDR#0 13
M_B_A15 78
79 A15 102
13 M_B_BS2 A16/BA2 CK1 M_B_DIM0_CLK_DDR1 13
104
CK1# M_B_DIM0_CLK_DDR#1 13
109
13 M_B_BS0 108 BA0 11
13 M_B_BS1 BA1 DM0 28
Note:
13 M_B_DQ[63:0] 5 DM1 46 SO-DIMMB SPD Address is 0xA4
M_B_DQ0
M_B_DQ1 7 DQ0 DM2 63
M_B_DQ2 15 DQ1 DM3 136 SO-DIMMB TS Address is 0x34
M_B_DQ3 17 DQ2 DM4 153
M_B_DQ4 4 DQ3 DM5 170
M_B_DQ5 6 DQ4 DM6 187
M_B_DQ6 16 DQ5 DM7 SO-DIMMB is placed farther from
M_B_DQ7 18 DQ6 200 the Processor than SO-DIMMA
21 DQ7 SDA 202 SMB_DATA 15,17,23,28,29,38,39,41
M_B_DQ8
23 DQ8 SCL SMB_CLK 15,17,23,28,29,38,39,41
M_B_DQ9
M_B_DQ10 33 DQ9 198 3D3V_S0
DQ10 EVENT# TS#_DIMM0_1 15
M_B_DQ11 35
M_B_DQ12 22 DQ11 199
M_B_DQ13 24 DQ12 VDDSPD
DQ13
1
M_B_DQ14 34 197 C1501
DQ14 SA0
SCD1U10V2KX-5GP
M_B_DQ15 36 201 SA1_DIM1 2 1
M_B_DQ16 39 DQ15 SA1
2
M_B_DQ17 41 DQ16 77 R1501
M_B_DQ18 51 DQ17 NC#1 122 10KR2J-3-GP
M_B_DQ19 53 DQ18 NC#2 125 1D5V_S3
M_B_DQ20 40 DQ19 NC#/TEST
M_B_DQ21 42 DQ20 75
C DQ21 VDD1 C
M_B_DQ22 50 76
M_B_DQ23 52 DQ22 VDD2 81
M_B_DQ24 57 DQ23 VDD3 82
M_B_DQ25 59 DQ24 VDD4 87
M_B_DQ26 67 DQ25 VDD5 88
M_B_DQ27 69 DQ26 VDD6 93
M_B_DQ28 56 DQ27 VDD7 94
M_B_DQ29 58 DQ28 VDD8 99
M_B_DQ30 68 DQ29 VDD9 100
M_B_DQ31 70 DQ30 VDD10 105
M_B_DQ32 129 DQ31 VDD11 106
M_B_DQ33 131 DQ32 VDD12 111
M_B_DQ34 141 DQ33 VDD13 112
M_B_DQ35 143 DQ34 VDD14 117
M_B_DQ36 130 DQ35 VDD15 118 1D5V_S3
M_B_DQ37 132 DQ36 VDD16 123
SODIMM B DECOUPLING
M_B_DQ38 140 DQ37 VDD17 124
M_B_DQ39 142 DQ38 VDD18
M_B_DQ40 147 DQ39 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
M_B_DQ41 149 DQ40 VSS 3
C1505
C1506
C1507
C1503
SC56P50V2JN-2GP
DQ41 VSS
1
SC5D6P50V2CN-1GP
M_B_DQ42 157 8
C1504
M_B_DQ43 159 DQ42 VSS 9
M_B_DQ44 146 DQ43 VSS 13 (R) (R)
2
M_B_DQ45 148 DQ44 VSS 14
M_B_DQ46 158 DQ45 VSS 19
SB M_B_DQ47 160 DQ46 VSS 20
M_B_DQ48 163 DQ47 VSS 25
M_VREF_DQ_DIMM1 M_B_DQ49 165 DQ48 VSS 26
DDR_VREF_S3 M_B_DQ50 175 DQ49 VSS 31
M_B_DQ51 177 DQ50 VSS 32
R1502 R1503 M_B_DQ52 164 DQ51 VSS 37
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
B DQ52 VSS B
1 2 1 2 M_B_DQ53 166 38
C1513
C1514
DDR_W R_VREF01_D1 47 DQ53 VSS
1
0R0603-PAD-1-GP-U 0R0603-PAD-1-GP-U M_B_DQ54 174 43 Layout Note:
M_B_DQ55 176 DQ54 VSS 44
DQ55 VSS Place these Caps near
1
M_B_DQ56 181 48
2
DQ56 VSS
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1515 C1517 M_B_DQ57 183 49

M_B_DQ58 191 DQ57 VSS 54 SO-DIMMB.
2
M_B_DQ59 193 DQ58 VSS 55

M_B_DQ60 180 DQ59 VSS 60
M_B_DQ61 182 DQ60 VSS 61
M_B_DQ62 192 DQ61 VSS 65
M_B_DQ63 194 DQ62 VSS 66
DQ63 VSS 71
M_B_DQS#0 10 VSS 72
M_B_DQS#1 27 DQS0# VSS 127
-2 M_B_DQS#4 135 DQS3# VSS 134
DQS7# VSS 145
Place these caps M_B_DQS0 12 VSS 150
0D75V_S0 close to VTT1 and M_B_DQS1 29 DQS0 VSS 151
M_B_DQS2 47 DQS1 VSS 155
VTT2. M_B_DQS3 64 DQS2 VSS 156
C1519
C1521
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DQS6 VSS
1
M_B_DQS7 188 168

DQS7 VSS 172
116 VSS 173
A A
2
13 M_B_DIM0_ODT0 120 ODT0 VSS 178

13 M_B_DIM0_ODT1 ODT1 VSS <Core Design>
179
126 VSS 184
DDR_VREF_S3 VREF_CA VSS
1 185
M_VREF_DQ_DIMM1 VREF_DQ VSS
VSS
189 Wistron Corporation
30 190 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
15,47 DDR3_DRAMRST# RESET# VSS 195 Taipei Hsien 221, Taiwan, R.O.C.
VSS 196
203 VSS 205 Title
0D75V_S0 VTT1 VSS
204 206
VTT2 VSS DDR3-DIMM2
DDR3-204P-104-GP Custom
H = 5mm (62.10017.K11) vSuperb -1
5 4 3 2 1
5 4 3 2 1
LPC 24,44 LPC_AD0

24,44 LPC_AD1
24,44 LPC_AD2
24,44 LPC_AD3
24,44 LPC_FRAME#
HD LINK
26 HDA_CODEC_BITCLK !"#$%$&'()$%$*'( RTC_AUX_S5
26,27 HDA_CODEC_RST# PCH1D 4 OF 11
26 AUD_LINK_SDIN RTC_AUX_S5
26 HDA_CODEC_SDOUT TPAD28-1-GP-U TP66 1 LPC_DRQ1_N AK26 G38 PCH_GPIO0 1 TP71 TPAD28-1-GP-U
26 HDA_CODEC_SYNC LPC_AD0 R464 1 2 33R2J-2-GP L_AD0_R AN24 LDRQ1#/GPIO23 BMBUSY#/GPIO0 N32 ADAPTOR_SEL
LPC_AD1 R512 1 2 33R2J-2-GP L_AD1_R AP26 LAD0 CLKRUN#/GPIO32 AV26 SOP_ENABLE_GP33 PCH_INTRUDER_N R482 1 2 1MR2J-1-GP
LPC_AD2 R622 1 2 33R2J-2-GP L_AD2_R AJ24 LAD1 DOCKEN#/GPIO33 N34 PCH_GP34_PU
#$2"F%"3,<66,G)4,<9:)H:1*:+/I
LPC_AD3 R640 1 2 33R2J-2-GP L_AD3_R AN26 LAD2 STPPCI#/GPIO34
TPAD28-1-GP-U TP55 1 LPC_DRQ0_N AK22 LAD3 AC40 IGC_EN_N
SMBUS 25 SMLINK0_CLK
LPC_FRAME# R652 1 2 33R2J-2-GP L_FRAME_N_R AP24 LDRQ0#
LFRAME#
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
AL40 LAN_DISABLE_N !"#$%"3%##
AN22 SPI_WP_R_N
25 SMLINK0_DATA
HDA_CODEC_BITCLK R445 1 2 33R2J-2-GP HDA_BITCLK AV23 HDA_DOCK_RST#/GPIO13 AC32 TLS_EN
A)5+B(;+C=01D=E+;5B5;5:F5+)G*B7
D
12$ HDA_CODEC_RST# R452 1 2 33R2J-2-GP HDA_RST# AU24 HDA_CLK GPIO15 AE34 H_SKTOCC_R_N R734 1 2 0R2J-2-GP H_SKTOCC_N D
HDA_RST# GPIO24
15,16,23,28,29,38,39,41
15,16,23,28,29,38,39,41
SMB_CLK
SMB_DATA
TPAD28-1-GP-U TP50
TPAD28-1-GP-U TP52
1
1
TP_PCH_AV13
TP_PCH_AP18
AT26
AV22 HDA_SDI0 GPIO28
V41
AL39
ILIM_SEL
SLP_WLAN_N
#$L"&%#!+>8,;J5;+F8,:J5+7(+M=0N!4 3D3_A
AUD_LINK_SDIN AT22 HDA_SDI1 SLP_WLAN#/GPIO29 W34 PCH_GP73_PD 3D3V_A
034",% TPAD28-1-GP-U TP56 1 TP_PCH_AN16 AW23 HDA_SDI2 PCIECLKRQ0#/GPIO73 P39 PCH_XDP_GP18
HDA_CODEC_SDOUT R444 1 2 33R2J-2-GP HDA_SDOUT AU22 HDA_SDI3 PCIECLKRQ1#/GPIO18 P37 LANCLK_REQ_N
24 SML1_CLK 1 2 33R2J-2-GP AV24 HDA_SDO PCIECLKRQ2#/GPIO20/SMI# AA39
%&0 HDA_SYNC_R R455 HDA_SYNC PCH_GP25_PD PCH_AUD_MUTE R548 1 (R) 2 10KR2J-3-GP
24 SML1_DATA HDA_SYNC PCIECLKRQ3#/GPIO25 W35 EDID_RDY !"#$%"&%"!
SPI_MOSI P40 PCIECLKRQ4#/GPIO26 AA36 USB_PWR_CRL1
SPI_MOSI_IO0 PCIECLKRQ5#/GPIO44 !"#$%"&%#! /56575+D,P5+=%R+$/$S1T
SPI_MISO R36 W32 PCH_GPIO45
SPI_CS0# R38 SPI_MISO_IO1 PCIECLKRQ6#/GPIO45 AA40 CLK_PCIE_WLAN_REQ#
'())*+,--+./0/1'/2
!"#$%"&%"& SPI_CS0# PCIECLKRQ7#/GPIO46
SPI_CLK U39
>8,:J5+7(+K9,-+;5,-+)(697*(: R35 SPI_CLK AC36 ME_CNTL
R40 SPI_CS1# GPIO57 W31 PCH_SYSPWROK
SPI_IO2 U40 SPI_CS2# SYS_PWROK AE36 PCH_RI
SPI_IO3 U37 SPI_IO2 RI# AK34 PCIE_WAKE#
SPI_IO3 WAKE# AN37 PCH_SLP_A
SLP_A# AU36 SLP_LAN_N_C R683 1 2 0R0402-PAD LAN_EN_PW R
SLP_LAN# AC35
SPI 42 SPI_IO3
42 SPI_IO2
SLP_S0#
SLP_S3#
AK40 PM_SLP_S3#
AT35 PM_SLP_S4#
42 SPI_MOSI AN40 SLP_S4# AA35 1
PCH_RTCX1 SLP_S5_N TP106 TPAD28-1-GP-U
42 SPI_MISO RTCX1 SLP_S5#/GPIO63
42 SPI_CS0#
PCH_RTCX2 AN39
RTCX2 SUS_STAT#/GPIO61
AD37 SUS_STAT_N SIO_SUSACK is for SIO DSW
RTC_RST# AR38 W36 SUSCLK
42 SPI_CLK RTCRST# SUSCLK/GPIO62
42 RTC_RST#
SRTC_RST#
PCH_INTRUDER_N
AR39
AR41 SRTCRST# GPIO72
AJ40
AJ37
USB_WAKE_SLP
SUSACK_N CW+:55-+T--+I=
3D3V_S5 3D3V_S5
PWRGD_3V AT40 INTRUDER# SUSACK# AG41 SUS_WARNB 1 TP176 TPAD28-1-GP-U

42 SRTC_RST# !"#$%"3%!O PCH_PWROK SUSWARN#/PWRDNACK/GPIO30
PM_RSMRST# AM40 AE38 H_DRAMPWRGD USB_PWR_CRL1 R549 1 2 10KR2J-3-GP
42 SPI_WP_R_N '())*+P55Q+)G*B7+'CH'CI+)(697*(: PCH_INTVRMEN AV36 RSMRST# DRAMPWRGD AU34 LANW AKE_N
PM_RSMRST# R682 1 2 0R0402-PAD PCH_SIO_DPWROK_1 AV38 INTVRMEN GPIO27 AM36 PCH_AUD_MUTE R551 1 2 10KR2J-3-GP
PM_RSMRST# used for SIO DSW DPWROK ACPRESENT/GPIO31
(R)
DSWVRMEN AM41 AK38 SLP_SUSB 1 TP175 TPAD28-1-GP-U
DSWODVREN SLP_SUS# AK41 PM_PWRBTN# SUS_STAT_N R594 1 2 10KR2J-3-GP
!"#$%"&%"4 PWRBTN#
=,:56+(:%(BB+9)5+C>0+5:5:7 PANEL_BTN_EVENT# AG31 N36 FP_RST_PCH_N PCH_RI R533 1 2 10KR2J-3-GP
SMB_CLK AG36 SMBALERT#/GPIO11 SYS_RESET# R32 HDA_SPKR
SMB_DATA AG32 SMBCLK SPKR PCH_GPIO45 R663 1 2 10KR2J-3-GP
DRAMRST_CNTRL_PCH AG35 SMBDATA D40 H_PWRGD
(R) C1667 C1668 (R) AE32 SMI0ALERT#/GPIO60 PROCPWRGD
SMLINK0_CLK R599 1 (R) 2 1KR2J-1-GP
SML0CLK
1
SMLINK0_DATA AE35
SC1U10V2ZY-N1-GP
SC1U10V2ZY-N1-GP
SML1ALERT_PCH AJ39 SML0DATA CLK_PCIE_WLAN_REQ# R568 1 2 10KR2J-3-GP
SMI1ALERT#/PCHHOT#/GPIO74
1
(R) (R) SML1_CLK AK36
PWR MANAGER
2
C21 C20 SML1_DATA AK33 SML1CLK/GPIO58/MGPIO11 R325 1 (R) 2 100R2J-2-GP
SML1DATA/GPIO75/MGPIO12
SC100P50V2JN-3GP
SC100P50V2JN-3GP
2
JTAG(SUS)
!"#$%"3%#" W37 PCH_JTAG_RST R562 2 (R) 1 10KR2J-3-GP !"#$%"3%## PANEL_BTN_EVENT# R56 1 2 10KR2J-3-GP
11 FP_RST_DBR_N TP13
1
(R) (R) Y40 PCH_JTAG_TCK 1 TP167 TPAD28-1-GP-U
11,51 H_PWRGD
C23 C22
'())*+,--+/0HH+'CI+>I'? JTAG_TCK W39 PCH_JTAG_TDI 1 TP132 TPAD28-1-GP-U
'())*+,--+I=
11 H_DRAMPWRGD JTAG_TDI
SC100P50V2JN-3GP
SC100P50V2JN-3GP
Y38 PCH_JTAG_TDO 1 TP133 TPAD28-1-GP-U
2
JTAG_TDO W40 PCH_JTAG_TMS 1 TP161 TPAD28-1-GP-U SML1ALERT_PCH R523 1 2 10KR2J-3-GP
11,14,46,51 VR_READY JTAG_TMS
LYNX-POINT-2-GP-U DRAMRST_CNTRL_PCH R516 1 2 2K2R2J-2-GP
24 PM_PWRBTN#
(KI.H8101.002) !"#$%"3%#"
'())*+,--+/0HH+'CI+>I'?
14,19,24 PWRGD_3V
ME_CNTL R596 1 2 10KR2J-3-GP
C 42,54 PCH_SLP_A C
TLS_EN R5 2 14K7R2J-2-GP
24,28,46,47,51,54,55 PM_SLP_S3#
24,36,53 PM_SLP_S4#
25 LAN_EN_PW R
SML1_CLK 4 1 RN8
%&0 SML1_DATA 3 2 SRN2K2J-1-GP
24
46
RSMRST#_SIO
SYS_PWROK
Fast Boot 3D3V_S5
Defensive Design 3D3V_S0 !"#"$%&'"()*+%&'" Flash Descriptor Security Overide 3D3V_S5
Low = Default !"#$%"&%"$
2
24 PWROK3_1_R HDA_SDOUT High = Debug mode 3OO+(8U+V5:-(;+C9JJ5)7
1
1
DEFENSIVE DESIGN R2116 SMLINK0_CLK R42 1 2 499R2F-2-GP
1
R258 C3416 1 2 499R2F-2-GP

R588 1KR2J-1-GP SMLINK0_DATA R43
(R)
22KR2J-GP SCD1U16V2KX-3GP
10KR2J-3-GP MECLR1
12$
2ME_CNTL2
1
(R) (R)
need resume GPIO
2
U86
1
2
2
1 5 HDA_SDOUT 1 R2107 2 HDA_SDOUT_R 2 SUSACK_N 1 4 RN9
GPIO/MISC #$2"'%#",(1*14516,<5)+6,>(?(@A-B,CDE FB_A 2 NC#1
A
VCC SYS_PWROK R748 1 2 0R0402-PAD PCH_SYSPWROK 3D3V_S5
3
R2115
SUS_WARNB 2 3 SRN10KJ-11-GP-U
3 4 FB_Y 1 (R) 2 PCH_SYSPWROK 1KR2J-1-GP
!"#$%&'()
C
Q51 GND Y PMBS3906-GP

(R) R2391 100R2J-2-GP PIN-CON3-S-GP ME_CNTL 2 1 ME_CNTL1 1
11 H_SKTOCC_N Q2102
VR_READY R756 1 2Q51_B B MMBT3904-4-GP SB Ryan add for debug HDA_SDOUT 1KR2J-1-GP 2 (R) 1 R456
1
(R84.03904.L06)74LVC1G14GW -GP 1 (R) 2 PWRGD_3V C3315 (84.T3906.E11)
0R2J-2-GP
3
1KR2J-1-GP
1
C422 R2392 249R2F-GP (R) SCD1U50V5KX-1GP

1
19 BOARD_ID_2
E
(R) (R) EV FOR FUTURE ENGINEERING HDA_SDOUT EDID_RDY R73 1 2 10KR2J-3-GP

R592
2
DEBUG ONLY
SC1U6D3V2KX-GP
19 BOARD_ID_1 10KR2J-3-GP
2
#$L"&%#!+ACW+D,P5+7(+M=0NX! USB_WAKE_SLP R557 1 2 10KR2J-3-GP

(R)
19 PCH_GP34_PU #$L"X%"O+G,P5+F8,:J5+7(+.A=+Q(G5;E+:(7+)9QQ(;7+C&+)7,75
2
21 HDA_SPKR
SLP_WLAN_N R554 1 2 10KR2J-3-GP
21 IGC_EN_N #$L"4%"O+F8,:J5+=%R+7(+$/$S1C&E+65,P,J5
21 DSWVRMEN
21 PCH_INTVRMEN
47 DRAMRST_CNTRL_PCH
3D3V_S0 RSMRST SEQUENCE PWROK
36 USB_WAKE_SLP
!"#$!%&'(
2
28 PANEL_BTN_EVENT# (R)
U87
R49 (R)
(R) 1KR2J-1-GP
1 6 FB_CT
PM_RSMRST# R1912 1 2 0R0402-PAD RSMRST#_SIO
*() 5+)7/ VR_READY 2
0R2J-2-GP
1
R120
PWRGD_3V
'+! 3D3V_S0 3D3V_S0
1
49 ADAPTOR_SEL C472 2 ENABLE CDELAY 5

FB_SENCE 3 GND VCC 4 FB_SEOUT 1 (R) 2 PCH_SYSPWROK
#$2"&%#3,(1*41516,7%8,691,:),7;8,+/:14/<=,7%8
SCD1U16V2KX-3GP
2 1
IN OUT R757 0R2J-2-GP (R)

2
(R) (R) (R) LPC_FRAME# R435 1 2 10KR2J-3-GP

1
1 2 PWRGD_3V
R89 MAX6895AAZT-T-GP !"#$)*)!%&'(
C138 R758 0R2J-2-GP
(R) LPC_DRQ0_N R521 1 (R) 2 10KR2J-3-GP
1KR2J-1-GP
SC3300P50V2KX-1GP
2
2345$+67- PCH_SYSPWROK 1
(R)
2 PWROK3_1_R LPC_DRQ1_N R520 1 (R) 2 10KR2J-3-GP
1
'+! R121 0R2J-2-GP *()

25 LAN_DISABLE_N
FP_RST_PCH_N R45 1 2 2K2R2J-2-GP
25 LANCLK_REQ_N
R1908
43 PCH_RI 2012/06/14 SC Ryan add for Intel MOW 100KR2J-1-GP LPC_AD0 R437 1 (R) 2 10KR2J-3-GP
PM_RSMRST# 1 2
B
38 CLK_PCIE_WLAN_REQ# LPC_AD1 R439 1 (R) 2 10KR2J-3-GP B
(R)
LPC_AD2 R440 1 (R) 2 10KR2J-3-GP
LPC_AD3 R441 1 (R) 2 10KR2J-3-GP

35 ILIM_SEL
ADAPTOR_SEL R442 1 2 10KR2J-3-GP
28 EDID_RDY
PCH_RTCX2
X3
BUZZER 5V_S0
XTAL 1 4 PCH_RTCX1 1
BUZ1
+
3D3V_S0 3D3V_S0
TPM !"#$%"&%"' R1511 BUZZER

Board ID Mission Sawgrass
44 SUS_STAT_N 3D3V_S0 R417 1 (R) 2 1KR2J-1-GP SOP_ENABLE_GP33 BZ_ON 1 2 BZ_ON1 2
-
1
()**+,-)./,*+01 2 3 75R2J-1-GP
C
2
HY-05LF-GP BOARD_ID_0 0 0 R651 R404

R1515
R542 HDA_SPKR 1 2 PCH_SPKR1 B Q119 (23.60031.011) BOARD_ID_1 0 10KR2J-3-GP 10KR2J-3-GP
MMBT3904-4-GP 0
XTAL-32D768KHZ-65-GP 0R0402-PAD 2K2R2J-2-GP
(82.30001.661) (84.T3904.K11) R1514
2
E
1 2 BOARD_ID_2
1
R553 5V_S0 BOARD_ID_1

75R2J-1-GP
1 2
FP_RST_PCH_N R750 1 20R0402-PAD FP_RST_DBR_N
WAKE
1
10MR3J-L1-GP
25 LANW AKE_N
1
38 PCIE_WAKE_N_PCIE C441 C835 R650 R397

1
20 Wake#_PCIE SC15P50V3JN-GP C458 RESERVE R542 FOR CRB SCD1U16V2ZY-2GP 10KR2J-3-GP 10KR2J-3-GP /56575
20 Wake#_PCIE_X1 (78.3R374.1BL) SC15P50V3JN-GP STUFF R542 FOR HSW(DEFAULT) (R) (R)
2
23 PCIE_WAKE_N_X1 (78.3R374.1BL)
2
2
SUSCLK R2215 1 (R) 2 1K5R2J-3-GP
PCH_XDP_GP18 R590 1 2 10KR2J-3-GP
PCH_GP25_PD R567 1 2 10KR2J-3-GP

SPI Michael 2011/01/16 HDA SYNC
!"#$%"3%##
'())*+,--+)G*B7+)(697*(:
3D3V_S5 !"#$%"3%"4
'())*+-56575+789:-5;<(67+=>0.>?@+=%?
WAKE SELECT
1
For EMI R1134 1

R141
2
SMBUS 3D3V_S0 RN2007
SRN2K2J-1-GP
PCH_GP73_PD R598 1 2 10KR2J-3-GP
HDA_CODEC_BITCLK 5V_S0 10KR2J-3-GP 3D3V_S5 1 4

(R) 0R2J-2-GP
2 3
G
2
1
(R) C2922 D HDA_SYNC_R PCIE_WAKE_N_X1 S D

034",%
2
SC10P50V2JN-4GP
2
HDA_CODEC_SYNC S PLL ODVR VOLTAGE R861

'+(/01 Q40 10KR2J-3-GP
Q2101 Low = 1.8V (Default) 2N7002A-7-GP
G
2N7002K-2-GP HDA_SYNC High = 1.5V (84.2N702.J31) SMB_DATA

1
(84.2N702.J31) Wake#_PCIE_X1
3D3V_S5
A A
Wake#_PCIE PCIE_WAKE#
R2111 '+!
SPI_WP_R_N 1 2 Q39
HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used 2N7002A-7-GP
G
HDA_CODEC_BITCLK HDA_CODEC_SDOUT 10KR2J-3-GP to (84.2N702.J31) SMB_CLK

sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required
2
(R) EC2102 (R) EC2103 on this PCIE_WAKE_N_PCIE S D

SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
signal on the board. Signal may have leakage paths via powered off devices
1
(Audio ,-#. R864

10KR2J-3-GP R140
Codec) and hence contend with the external pull-up. A blocking FET is 1 2
<Core Design>
recommended in such a case to isolate HDA_SYNC from the Audio Codec (R) 0R2J-2-GP
1
device
until after the Strap sampling is complete. 3D3V_S5 Wistron Corporation
Title
PCH(Audio/GPIO/SPI)
Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
PCI CLOCK
44 CLK_PCI_LPC
20 CK_PCH_33M_FB
24 CLK_PCI_SIO
D D
PCIE CLOCK
11 CK_DPNS_R_DN
11 CK_DPNS_R_DP
11 CK_PE_100M_MCP_DN
11 CK_PE_100M_MCP_DP
12 CK_DP_DN
12 CK_DP_DP
23 PCIEX1_CLKP
23 PCIEX1_CLKN
25 CK_PCIE_3_GLAN_DN 7 OF 11
PCH1G
25 CK_PCIE_3_GLAN_DP
G16 CK_CSI_PCH_IN_DN R535 1 2 10KR2J-3-GP
38 CLK_PCIE_WLAN CLKIN_GND0# F16 CK_CSI_PCH_IN_DP R532 1 2 10KR2J-3-GP
38 CLK_PCIE_WLAN# Empty when measure the PCI clock CLKIN_GND0_P
R2 CK_PE_100M_MCP_DN
CLK_PCI_LPC R354 1 2 22R2J-2-GP CK_33M_PCI0 AV5 CLKOUT_DMI# T2 CK_PE_100M_MCP_DP
!"#$%&'!%( CLKOUT_33MHZ0 CLKOUT_DMI_P CLK OUT TO CPU for DMI
AV7 T3 CK_DP_DN
48M CLOCK CLKOUT_33MHZ1 CLKOUT_DP#
CLKOUT_DP_P
T5 CK_DP_DP CLK OUT TO CPU
$))%*+&,#&$, CK_PCH_33M_FB R388 1 2 22R2J-2-GP CK_33M_PCI2 AU2
24 CLK_48M_SIO CLKOUT_33MHZ2 W2 CK_DPNS_R_DN
R406 1 2 22R2J-2-GP AN9 CLKOUT_DPNS# U2
!"#-.) CLK_PCI_SIO CK_33M_PCI3
CLKOUT_33MHZ3 CLKOUT_DPNS_P
CK_DPNS_R_DP CLK OUT TO CPU
AU5 U6 !"#$%"&%#?
CLKOUT_33MHZ4 CLKOUT_ITPXDP# U7
CLKOUT_ITPXDP_P ()**+,-./.0.,=@7,8;<
C AA3 !"#$%"&%"$ C
AV8 CLKOUT_PEG_A# AA2
CLK_48M_SIO R399 1 2 22R2J-2-GP CLKOUTFLEX1 AT9 CLKOUTFLEX0/GPIO64 CLKOUT_PEG_A_P ()**+,-./.0.,789:=#>,8;<
!"#-.) AV9 CLKOUTFLEX1/GPIO65 AE6
AU8 CLKOUTFLEX2/GPIO66 CLKOUT_PEG_B# AE7
CLKOUTFLEX3/GPIO67 CLKOUT_PEG_B_P
AE10
R537 1 2 7K5R2F-1-GP XCLK_RCOMP R11 CLKOUT_PCIE_N0 AE11
!"#$%"&%"'
1D5V_S0 DIFFCLK_BIASREF CLKOUT_PCIE_P0
!"##$%&''%(")%*+, ()**+,-./.0.,1234-.56)/0,789:,8;<
R375 2 1 10KR2J-3-GP CK_14M_PCH AR7 AC6
REFCLK14IN CLKOUT_PCIE_N1 AC7
CLKOUT_PCIE_P1
CLK_48M_SIO AC11
CLKOUT_PCIE_N2 AC10
CLKOUT_PCIE_P2
1
(R) C2013 W11 CK_PCIE_3_GLAN_DN

#$C"?%!!,82D4E.,789:,;FG,0),7)50$
SC10P50V2JN-4GP CLKOUT_PCIE_N3 W10 CK_PCIE_3_GLAN_DP CLK OUT TO PCIEX1 for LAN
2
CLKOUT_PCIE_P3
NOTE:The 1Mohm Damping Resistor
Use 0603 and Can't change to 0402! Y4 PCIEX1_CLKN
CLKOUT_PCIE_N4 Y2 PCIEX1_CLKP
CLKOUT_PCIE_P4 CLK OUT TO PCIEX1
W7 CLK_PCIE_WLAN#
CLKOUT_PCIE_N5 W6
CLKOUT_PCIE_P5
CLK_PCIE_WLAN CLK OUT TO MINIPCIEX1
AA7
CLKOUT_PCIE_N6 AA6
XTAL_25M_PCH_IN N7 CLKOUT_PCIE_P6
XTAL25_IN R6
R383 1 2 1MR3F-GP XTAL_25M_PCH_OUT N6 CLKOUT_PCIE_N7 R7
XTAL25_OUT CLKOUT_PCIE_P7
X2
3 2
LYNX-POINT-2-GP-U
(KI.H8101.002)
!"#$%"?%"> 4 1
B
()**+,@)A4,*+B. PCH_1D05V
B
XTAL-25MHZ-181-GP
XTAL_IN should be pulled to
1
C322 C328 GND via a 0-Ω resistor by

SC12P50V2JN-3GP SC12P50V2JN-3GP default.
1
SCD1U16V2ZY-2GP
Intel reliability concerns C439
2
2
When support FCIM need to stuff.
WHEN USING 25MHZ EXTERNAL REFERENCE FROM SINAI CMV:
REMOVE R383, X2, C322
Stitching Capacitors
REPLACE C321 WITH 50OHM RES 0402 PACKAGE for CK_PCIE_5
A A
<Core Design>
Wistron Corporation
Title
PCH Clock
C
vSuperb -1
5 4 3 2 1
5 4 3 2 1
01"
31 VGA_HSYNC_3V '$!"&$@&!%
3D3V_S0
31 VGA_VSYNC_3V /3):I:5)*.(E(*)5I:B5)
31 VGA_RED Pull-up on MB '$!"&$@&!%
D 31 VGA_GREEN D
31 VGA_BLUE
PCH1C 3 OF 11 7399:*)5>5?5*,D;99:9*;B)*/E.E*0<
31 VGA_PCH_DDCSDA
BATT_CTRL_EVENT R81 1 2 10KR2J-3-GP
31 VGA_PCH_DDCSCL 1 U36 B28
TPAD28-1-GP-U TP74 CLINK_CLK_LAN SATA_RXN0
31 VGA_DET 1 U35 CL_CLK SATA_RXN0 A28
TPAD28-1-GP-U TP75 CLINK_DATA_LAN SATA_RXP0
1 CLINK_RST_LAN_N U34 CL_DATA SATA_RXP0 F31 SATA_TXN0 +,-.- OBR 1 2 10KR2J-3-GP
MEPWROKStuff R497 for AMT TPAD28-1-GP-U TP76
CL_RST# SATA_TXN0 H31 SATA_TXP0
R72
R497 1 2 0R0402-PAD AA32 SATA_TXP0 D30 1 2 10KR2J-3-GP

PCH_MEPWROK PCH_MEPWROK_R SATA 6G SATA_RXN1 EC_ASF R71
!"#" APWROK SATA_RXN1
CLINK
C30 SATA_RXP1
PWRGD_3V R481 1 (R) 2 0R2J-2-GP SATA_RXP1 B34 SATA_TXN1 INT_SERIRQ R580 1 2 10KR2J-3-GP
39 SATA_RXN0 SATA_TXN1 C34 SATA_TXP1 &//0
39 SATA_RXP0 SATA_TXP1
SB Stuff R481 for Realtek LAN (None AMT) H_A20GATE R555 1 2 10KR2J-3-GP
39 SATA_TXN0 A31
39 SATA_TXP0 1 AL31 SATA_RXN2 B31
TPAD28-1-GP-U TP62 TP_PCH_PWM0 H_RCIN# R582 1 2 10KR2J-3-GP
TPAD28-1-GP-U TP63 1 TP_PCH_PWM1 AM31 PWM0 SATA_RXP2 B35
33 SATA_RXN1 PWM1 SATA_TXN2 !"#$%&''
TPAD28-1-GP-U TP64 1 TP_PCH_PWM2 AP31 D35 EC_SMI# R96 1 2 10KR2J-3-GP
33 SATA_RXP1
TPAD28-1-GP-U TP65 1 TP_PCH_PWM3 AV30 PWM2 SATA_TXP2 B32 ())*+,-./0*1&2*,345*167
FAN
33 SATA_TXN1 PWM3 SATA_RXN3 C32
33 SATA_TXP1 SATA_RXP3 G33
SATA_TXN3 '$!"&$@&!%
BOARD_ID_2 AP28 F33
33 SATA_RXN4 EC_SMI# AT31 TACH0/GPIO17 SATA_TXP3 7399:*)5>5?5*A43B?*(C):3*<5?
33 SATA_RXP4 AM28 TACH1/GPIO1 A26 1 2 10KR2J-3-GP
'$!"&$@&'" EC_ASF SATA_RXN4 PCH_GP38_PU R74
33 SATA_TXN4 TACH2/GPIO6 SATA_RXN4/PERN1
OBR AV34 B26 SATA_RXP4
33 SATA_TXP4 7399:*;))*GQ7 SMBUS_ISP AT30 TACH3/GPIO7 SATA_RXP4/PERP1 L28 SATA_TXN4 &//1
TACH5 AV35 TACH4/GPIO68 SATA_TXN4/PETN1 K28 SATA_TXP4 PCH_GPIO16 R70 1 2 10KR2J-3-GP
33 SATA_RXN5 TACH5/GP69 SATA_TXP4/PETP1 C27
'$!"&$@&!% SATA_RXN5
33 SATA_RXP5 SATA_RXN5/PERN2 B27 SATA_RXP5
33 SATA_TXN5 7399:*)5>5?5*A43B?*(C):3*<5? SATA_RXP5/PERP2 G28 SATA_TXN5 $//0 VGA_DET R575 1 2 10KR2J-3-GP
33 SATA_TXP5 SATA_TXN5/PETN2
R491 1 (R) 2 0R2J-2-GP SST_CTL_R AJ31 F28 SATA_TXP5
SSTCTL SATA_TXP5/PETP2 H35 CK_SATA_PCH_DN R541 1 2 10KR2J-3-GP R589 1 (R) 2 10KR2J-3-GP
34 SATA_LED# L38 CLKIN_SATA# H36
BOARD_ID_1 CK_SATA_PCH_DP R540 1 2 10KR2J-3-GP GPIO49 CAN BE USE AS PCIE/MSATA MUX SELECT IN LPT
PCH_GP38_PU H41 SCLOCK/GPIO22 CLKIN_SATA_P
PCH_GP39_PU R31 SLOAD/GPIO38 J39 SATA_LED#
PCH_GP48_PU L40 SDATAOUT0/GPIO39 SATALED# D33 SATARBIAS_PCH R545 1 2 7K5R2F-1-GP
!"#$%&'()'* SDATAOUT1/GPIO48 SATA_RCOMP 1D5V_S0
PCH_1D05V
$#%&'! '$!"&$@&!% !"#$%&!%**.,0*+O5B?*?3*.0G*I34*.R;4?*Q(E*,E7J TIE TRACES TOGETHER CLOSE TO PINS,
M37 BATT_CTRL_EVENT WITH LENGTH NO LONGER THAN 450 MILS TO RESISTOR
C
11 H_PM_SYNC_0 7399:*;))*F10G*.:HB;> SATA0GP/GPIO21 J40 SATA1GP H_THERMTRIP_N R340 1 (R) 2 51R2J-2-GP C
11 H_THERMTRIP_N SATA1GP/GPIO19 H40
GPIO
SATA2GP
11,24 H_PECI SATA2GP/GPIO36 N41 SATA3GP
SATA3GP/GPIO37 M39 PCH_GPIO16
SATA4GP/GPIO16 N40 VGA_DET
14,17,24 PWRGD_3V SATA5GP/GPIO49
17 PCH_GP34_PU
24 H_A20GATE
24 H_RCIN# AP2 EDP_BKLTCTL
24,44 INT_SERIRQ EDP_BKLTCTL AT2 EDP_BKLTEN
54 PCH_MEPWROK EDP_BKLTEN AP1 EDP_VDDEN
11 PLTRST_CPU_N !"#$%&'$
34 OBR
()*+,-./012.34.526.()*+,- !"#$ EDP_VDDEN
'$!"&$@&'"
24 EC_SMI# 7399:*45954O5)*1,2*1;B5>*P3B?43>
24 EC_ASF N30
3D3V_S0 3D3V_S0 H_A20GATE
RSVD#N30
HOST
K36 H_RCIN#
17,28 PANEL_BTN_EVENT# RCIN# G39 INT_SERIRQ
SERIRQ C40 H_THERMTRIP_N (R)
THRMTRIP#
2
G40 PECI_PCH R538 1 2 0R2J-2-GP H_PECI

28 SMBUS_ISP PECI F40 H_PM_SYNC_0
R228 R230
PM_SYNCH F41 PLTRST_CPU_N
24 BATT_CTRL_EVENT 10KR2J-3-GP 10KR2J-3-GP PLTRST_PROC#
1
C3313
SC47P50V2JN-3GP
1
GPIO1 GPIO2 (R)
2
PCH_GP39_PU 1 PCH_GP48_PU 1 LYNX-POINT-2-GP-U
()* 2 2
1
(KI.H8101.002)
1
R811 JOWLE-CON2-5-GP JOWLE-CON2-5-GP

17 BOARD_ID_1
1KR2J-1-GP (21.62874.102) R812 (21.62874.102)
17 BOARD_ID_2
(R) 1KR2J-1-GP
(R)
2
!+,-./ 3D3V_S0
21 SATA1GP
B B
PCH_GP34_PU R436 1 2 10KR2J-3-GP
21 SATA2GP
R432 1 (R) 2 10KR2J-3-GP
21 SATA3GP
HDMI_DETECT R552 1 2 10KR2J-3-GP
PCH1E 5 OF 11 R433 1 (R) 2 10KR2J-3-GP
TACH5 R438 1 (R) 2 10KR2J-3-GP

DP_HPD_N AJ2 AH3 VGA_HSYNC_3V
EDP DP2_HPD_N AH5 DDPB_HPD
DDPC_HPD
VGA_HSYNC
VGA_VSYNC
AH2 VGA_VSYNC_3V R550 1 2 47KR2J-2-GP
EDP_HPD_N AJ4
28,29 EDP_HPD_N DDPD_HPD AC2
'$!"&$%&$8 VGA_RED
DP_AUX_N AK6 VGA_RED AE2 VGA_GREEN EDP_HPD_N R5129 1 2 4K7R2J-2-GP
28,29 EDP_AUX_N 7399:*;))*<1*21<=*)5>5?5*2</0 DP_AUX_P AK8 DDPB_AUXN VGA_GREEN AC3 VGA_BLUE
28,29 EDP_AUX_P AG7 DDPB_AUXP VGA_BLUE
!"#$%&"!*7399:*75954O5)*<1*I34*!J DP2_AUX_N
DP2_AUX_P AG6 DDPC_AUXN AG4
DDPC_AUXP VGA_IRTN
1
EDP_AUX_N AG11 AL3 VGA_PCH_DDCSDA
29,30 EDP_BKLTCTL EDP_AUX_P AG10 DDPD_AUXN VGA_DDC_DATA AL2 VGA_PCH_DDCSCL R411 R410 R409
30 EDP_BKLTEN DDPD_AUXP VGA_DDC_CLK AF5 VGA_DACREFSET R373 1 2 649R2F-GP 150R2F-1-GP 150R2F-1-GP 150R2F-1-GP
30 EDP_VDDEN DAC_IREF
AN3 DDPC_CTRL_CLK CLOSE TO PCH : '$!"&$@&!L
2
DDPC_CTRLCLK AM2 DDPC_CTRL_DATA
DDPC_CTRLDATA AM1
<500 MIL TO PIN BALLS 7399:*;))*+<1*(MN*12
DDPB_CTRL_CLK
DDPB_CTRLCLK AJ5 DDPB_CTRL_DATA
'$!"&$@&!8 DDPB_CTRLDATA AN4 DDPD_CTRL_CLK CLOSE TO PCH :<250 MIL TO PIN BALLS
7399:*;))*21<*1&J DDPD_CTRLCLK AN2 DDPD_CTRL_DATA 3D3V_S0
*2 32
32
DP_HPD_N
DP2_HPD_N
DDPD_CTRLDATA
DP2_HPD_N RN1
DP_HPD_N EDP_AUX_P 1 4
32 DP_AUX_N 2 3
EDP_HPD_N EDP_AUX_N
32 DP_AUX_P
'$!"&$@&!%
LYNX-POINT-2-GP-U SRN10KJ-11-GP-U
32 DP2_AUX_N 7399:*<5>5?5*2</0*,E7J-,JK
1
(R) (KI.H8101.002) (R)

32 DP2_AUX_P
1
R10 R11 R18 R35 R32
32 DDPB_CTRL_DATA
100KR2J-1-GP
100KR2J-1-GP 100KR2J-1-GP 1K8R2-GP 1K8R2-GP

32 DDPB_CTRL_CLK 3D3V_S0
A (R) (R) (R) (R) A
2
32 DDPC_CTRL_DATA
2
32 DDPC_CTRL_CLK
R33 1 2 2K2R2J-2-GP DDPD_CTRL_CLK
2012/10/4 David <Core Design>
Follow design guide(Dallas) R34 1 2 2K2R2J-2-GP DDPD_CTRL_DATA 2012/11/09 David
vendor suggest(Dallas)
R46 1 2 2K2R2J-2-GP DDPB_CTRL_CLK
Wistron Corporation
R47 1 2 2K2R2J-2-GP DDPB_CTRL_DATA 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
R104 1 2 2K2R2J-2-GP DDPC_CTRL_CLK
Title
R105 1 2 2K2R2J-2-GP DDPC_CTRL_DATA
PCH(SATA/FAN/DP/VGA)
!"#$S&'T*7399:*;))*I34*!J Size Document Number Rev
Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
!"#$%&'()*+',-../01
DMI
12 DMI_MT_IR_DN[0..3]
12 DMI_MT_IR_DP[0..3] 3D3V_S0 !"#$)56 "+,-'",--.
12 DMI_IT_MR_DN[0..3] "/01234 "/01234
12 DMI_IT_MR_DP[0..3]
USB30_RN1
2
!"#$%&'( USB_PN0 USB30_PN1 3D3V_S0
C468 !"#$%"&%#'
* USB_PP0 USB30_TN1
PCIE SCD1U16V2ZY-2GP ()**+,-%.,/0!1,2)33)4,56*+78,79+56
1
USB30_TP1
25 HSI_DN3
25 HSI_DP3 USB30_RN2 GPIO2 R75 1 2 8K2R2J-3-GP
D 25 HSO_C_DN3 !"#$%&'( USB_PN1 USB30_PN2 GPIO3 R76 1 2 8K2R2J-3-GP
D
25 HSO_C_DP3 Stitching Capacitor for DMI USB_PP1 GPIO4 R77 1 2 8K2R2J-3-GP
) USB30_TN2 PCH_NMI#_PU R78 1 2 8K2R2J-3-GP
USB30_TP2
23 PCIE_RXN4
2012/06/25 SC Ryan
23 PCIE_RXP4
SWAP FORCE PWR & TBGPIO6
23 PCIE_TXN4
23 PCIE_TXP4 3D3V_S0
DMI_MT_IR_DN0 L24
PCH1B 2 OF 11
AV10 USB_PN0
!"#$%&'() P_INTA_N 1
RN3
8
DMI_MT_IR_DP0 K24 DMI_RXN0 USB2N0 AU10 USB_PP0 P_INTC_N 2 7
38 PCIE_RXN5 DMI_RXP0 USB2P0
DMI_IT_MR_DN0 C20 AV11 USB_PN1 Pair Device P_INTD_N 3 6
38 PCIE_RXP5 DMI_TXN0 USB2N1
2
DMI_IT_MR_DP0 B20 AW11 USB_PP1 P_INTB_N 4 5
38 PCIE_TXN5 DMI_TXP0 USB2P1
C449 DMI_MT_IR_DN1 G24 AN14 USB_PN2 0
38 PCIE_TXP5
DMI_MT_IR_DP1 H24 DMI_RXN1 USB2N2 AP14 USB_PP2
!"#>56$9:(5$,&'($*$;"/.-=
SCD1U16V2ZY-2GP
1
D21 DMI_RXP1 USB2P2 AJ16
DMI_IT_MR_DN1
DMI_TXN1 USB2N3
USB_PN3 1 !"#>56$9:(5$,&'($)$;8-2'= SRN8K2J-4-GP
DMI
DMI_IT_MR_DP1 B21 AK16 USB_PP3
F26 DMI_TXP1 USB2P3 AU15 R556 2 1 10KR2J-3-GP
DMI_MT_IR_DN2
DMI_RXN2 USB2N4
USB_PN4
!"#$%&'!()*++,()2+2392:(;*3("< 2 78 PCH_GPIO71
DMI_MT_IR_DP2 G26 AV15 USB_PP4
Stitching Capacitor for USB3.0 B22 DMI_RXP2 USB2P4 AU12
DMI_IT_MR_DN2
DMI_TXN2 USB2N5
USB_PN5 3 9:(5$!"#)56$;<+23=
DMI_IT_MR_DP2 C22 AT12 USB_PP5
K26 DMI_TXP2 USB2P5 AV14
DMI_MT_IR_DN3
DMI_RXN3 USB2N6 4 I1(-'123$!"#$;8-4-'J-.=
DMI_MT_IR_DP3 L26 AW14 !"#$%"'%#&
A24 DMI_RXP3 USB2P6 AU17
DMI_IT_MR_DN3
DMI_TXN3 USB2N7 ()**+,C636@6,8)@,*9DD)=@ 5 I1(-'123$!"#$;8-4-'J-.=
DMI_IT_MR_DP3 B24 AT17
DMI_TXP3 USB2P7 AW16
USB2.0 USB2N8
USB_PN8 6 X
R474 1 2 7K5R2F-1-GP DMIRCOMP B19 AV16 USB_PP8
R472 1 2 7K5R2F-1-GP C13 DMI_RCOMP USB2P8 AN16
35 USB_PN0 1D5V_S0 DMICOMP
PCIE_RCOMP USB2N9
USB_PN9 7 X
AP16 USB_PP9
35 USB_PP0 USB2P9 3D3V_S5
R405 2 1 10KR2J-3-GP 100M_DMI_PCH_DN G22 AJ18 USB_PN10 8 9:(5$!"#)56$;<+23=
35 USB_PN1 CLKIN_DMI# USB2N10
R396 2 1 10KR2J-3-GP 100M_DMI_PCH_DP F22 AK18 USB_PP10
35 USB_PP1
USB
CLKIN_DMI_P USB2P10 AP18
34 USB_PN2 USB2N11
USB_PN11 9 D&+EF RN5
L14 AN18 USB_PP11 SRN10KJ-6-GP
34 USB_PP2 PERN1/USB3RN2 USB2P11
K14 AW18 10 GPIO43 1 8
37 USB_PN3
B12 PERP1/USB3RP2 USB2N12 AV18
?/'-3-44$@ABC#D Wake#_PCIE 2 7
37 USB_PP3 PETN1/USB3TN2 USB2P12 !"#$%"'%#& !"#$%"'%#&
B11 AP20 11 3 6
37 USB_PN4
F14 PETP1/USB3TP2 USB2N13 AN20 ()**+,C636@6,8)@,*9DD)=@ ?EF,298G@+)8,2)33)4,H4+2@ ?-GE2H Wake#_PCIE_X1 4 5
37 USB_PP4 ,-./%&'(%0*+%12$34%5%#-6%)%#$"%"-#7."6 PERN2/USB3RN3 USB2P13
!"#$%"'%#& G14 12 X
37 USB_PN5 PERP2/USB3RP3
C
37 USB_PP5 close to CONN ()**+,C636@6,8)@,*9DD)=@
D11
PETN2/USB3TN3 GPIO59
AE40 USB_OC_01 !"#$%&'(%)*+% C
C11 AF37 USB_OC_02 '86"%&'(%9:#$;"$ 13 X
37 USB_PN8 PETP2/USB3TP3 GPIO40
HSI_DN3 F11 AD39 W3_DISABLE_N <=>?@(A%B84#7."
37 USB_PP8 PERN3 GPIO41
HSI_DP3 H11 AD40 W1_DISABLE_N <=>?@(A%B84#7." !"#$%"'%#&
37 USB_PN9 PERP3 GPIO42
FOR LAN HSO_C_DN3 C205 1 2 SCD1U10V2KX-5GP HSO_DN3 B9 AF39 GPIO43 OC[0..3] for Ports 0-7
37 USB_PP9 PETN3 GPIO43 ()**+,:55,2)=,?EF,298G@+)8
PCI-E
HSO_C_DP3 C206 1 2 SCD1U10V2KX-5GP HSO_DP3 A9 AC41 Wake#_PCIE <=>?@(A%<#C"%DE-F382-
38 USB_PN10 PETP3 GPIO9
close to CONN PCIE_RXN4 J11 AF40 mSATA_DET# G'>A>%B"3"F382- OC[4..7] for Ports 8-13
38 USB_PP10 PERN4 GPIO10
PCIE_RXP4 L11 AG40 Wake#_PCIE_X1 H9IJK5%<#C"%DE-F382-
37 USB_PN11 PERP4 GPIO14
PCIE_TXN4 C208 1 2 SCD1U10V2KX-5GP PCIE_C_TXN4 B8
37 USB_PP11 PETN4
FOR PCIEX1 PCIE_TXP4 C207 1 2 SCD1U10V2KX-5GP PCIE_C_TXP4 C8 AV20
PCIE_RXN5 G9 PETP4 USBRBIAS# AU20 USBRBIAS_PCH R465 2 1 22D6R2F-L1-GP USBRBIAS_PHY (R465): TIE TRACES TOGETHER CLOSE TO PINS,
PCIE_RXP5 F9 PERN5 USBRBIAS
PERP5 WITH LENGTH NO LONGER THAN 1 INCHE TO RESISTOR
PCIE_TXN5 C209 1 2 SCD1U10V2KX-5GP PCIE_C_TXN5 B7 AP11 CK_96M_DREF_DN R477 1 2 10KR2J-3-GP
C210 1 2 SCD1U10V2KX-5GP A7 PETN5 CLKIN_DOT96# AM11 CK_96M_DREF_DP R480 1 2 10KR2J-3-GP
FOR WLAN PCIE_TXP5 PCIE_C_TXP5
PETP5 CLKIN_DOT96_P
F7
789:=,>)5,?@AB H7 PERN6
E1 PERP6
D2 PETN6
K6 PETP6
!"#$%"&%"' K8 PERN7
()**+,-./.0.,1234-.56)/0,789:,*+;4</ G3 PERP7
G5 PETN7
J2 PETP7
J3 PERN8
H2 PERP8
H1 PETN8
PETP8
3D3V_S0
USB3.0 LYNX-POINT-2-GP-U
34 USB30_RN1 (KI.H8101.002)
PCH1F 6 OF 11
34 USB30_RP1 !"#$%&'!()*++,(-./012()2/3(456(7*(8*37$ PLACE NEAR PCH
34 USB30_TN1 1D5V_S0
34 USB30_TP1
1
35 USB30_RN0 USB30_RN0 F20 N1 FDI_TX_DN0 C164
USB3RN0 FDI_RXN0 C166
USB30_RP0 G20 N2 FDI_TX_DP0 SC4D7U10V5ZY-3GP
35 USB30_RP0 3D3V_S5 USB3RP0 FDI_RXP0 SCD1U10V2KX-5GP
!"#$%&'(0*+ USB30_TN0 B18 P2 FDI_TX_DN1
35 USB30_TP0
2
USB3TN0 FDI_RXN1
1
B 1 OF 11 C18 P3 B
35 USB30_TN0 PCH1A USB30_TP0 FDI_TX_DP1
USB3TP0 FDI_RXP1 R476
USB30_RN1 G18 L2 FDI_CSYNC 7K5R2F-1-GP
R493 1 (R) 2 10KR2J-3-GP P_PME# AA31 USB30_RP1 H18 USB3RN1 FDI_CSYNC
CK_PCH_33M_FB AM22 PME# AA37 PLT_RST# USB30_TN1 B15 USB3RP1 L3 FDI_INT
!"#$%"'%"/ '86"%&'(0*+
2
CLKIN_33MHZLOOPBACK PLTRST# USB30_TP1 B16 USB3TN1 FDI_INT
M40 PCH_NMI#_PU
()**+,5636@6,@A9856=B)3@,;->? USB3TP1 USB3 K2 FDI_RCOMP
TPAD28-1-GP-U TP44 1 TP_PCH_A2 A2 GPIO35_NMI# AH26 PCH_GPIO50 1 TP45 TPAD28-1-GP-U K20 FDI_RCOMP
TPAD28-1-GP-U TP43 1 TP_PCH_A3 A3 TP16 GPIO50 AU31 P_GNT_N1 L20 USB3RN4
TP17 GPIO51 P_GNT_N1 21 USB3RP4
TPAD28-1-GP-U TP42 1 TP_PCH_B2 B2 AJ26 PCH_GPIO52 1 TP67 TPAD28-1-GP-U D15
TPAD28-1-GP-U TP38 1 TP_PCH_B1 B1 TP18 GPIO52 AV31 P_GNT_N2 C15 USB3TN4
TP19 GPIO53 P_GNT_N2 21 USB3TP4
TD_IREF C3 AW33 PCH_GPIO54 1 TP68 TPAD28-1-GP-U !"#$%"'%#& FDILINK
TD_IREF GPIO54 R30 P_GNT_N3 L18
P_GNT_N3 21 ()**+,C636@6,8)@,*9DD)=@
1
GPIO55 K18 USB3RN5

R118 P_INTA_N AU29 B14 USB3RP5
8K2R2F-1-GP P_INTB_N AU27 PIRQA# A14 USB3TN5
P_INTC_N AW28 PIRQB# USB3TP5
P_INTD_N AV27 PIRQC#
2
GPIO2 AR30 PIRQD# KEY0_TEST AK28

GPIO3 AV29 GPIO2 TPAD28-1-GP-U TP172 1 PCH_GPIO71 AT34 TACH6/GPIO70
GPIO4 AV28 GPIO3 TACH7/GPIO71
1 R27 2 AT27 GPIO4
FDI 12 FDI_TX_DN[0..1]
GS_INT2# GS_INT2#_N
GPIO5 LYNX-POINT-2-GP-U
100R2F-L1-GP-U (KI.H8101.002)
12 FDI_TX_DP[0..1]
!"#$%"'%!$
()**+,:55,;<*68*)=,;->?
12
12 FDI_INT
FDI_CSYNC !"#$%"&%
3D3V_S0
OTHERS
1
37 USB_OC_01
R454
35 USB_OC_02 10KR2J-3-GP
38 W3_DISABLE_N
(63.10234.1DL)
38 W1_DISABLE_N
2
KEY0_TEST
17 Wake#_PCIE
A A
39 mSATA_DET#
Q2202
D
17 Wake#_PCIE_X1
2N7002-11-GP
(84.2N702.J31)
18 CK_PCH_33M_FB <Core Design>
PANEL_SW G
11,24,44 PLT_RST# PCI
Wistron Corporation
S
LYNX-POINT-2-GP-U
(KI.H8101.002) 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
24,34 PANEL_SW
Title
41 GS_INT2#
PCH(FDI/PCIE/DMI/USB)
FOR LPT: GP70 STRAP - USB3 PORT4 Size Document Number Rev
GP71 - USB3 PORT5 Custom
SOFT STRAP TO DETERMINE NATIVE FUNCTION vSuperb -1
5 4 3 2 1
5 4 3 2 1
STRAP
11 HSW_STRAP_13
Straping Pin define
19 SATA1GP
19 SATA2GP
3D3V_S0 R630 1 (R) 2 1KR2J-1-GP HDA_SPKR
19 SATA3GP
PCH1I 9 OF 11 PCH1K 11 OF 11
D9 A12
17 DSWVRMEN E12 VSS_121 VSS_1 A16 D12 AN28
17 IGC_EN_N VSS_122 VSS_2 VSS_100 VSS_62
E3 A21 D13 AP4
17 PCH_INTVRMEN VSS_123 VSS_3 VSS_101 VSS_63
E31 A35 D14 AP9
E35 VSS_124 VSS_4 AA10 D16 VSS_102 VSS_64 AR11 P_GNT_N3 R840 1 (R) 2 1KR2J-1-GP
E38 VSS_125 VSS_5 AA11 D18 VSS_103 VSS_65 AR35
17 HDA_SPKR E4 VSS_126 VSS_6 AA12 D19 VSS_104 VSS_66 AR37
E5 VSS_127 VSS_7 AA14 D20 VSS_105 VSS_67 AT10
20 P_GNT_N1 E7 VSS_128 VSS_8 AA17 D22 VSS_106 VSS_68 AT11
RTC_AUX_S5 R485 1 2 390KR2J-GP PCH_INTVRMEN
20 P_GNT_N2 VSS_129 VSS_9 VSS_107 VSS_69
F18 AA22 D24 AT14
20 P_GNT_N3 F24 VSS_130 VSS_10 AA28 D25 VSS_108 VSS_70 AT15 R484 1 (R) 2 1KR2J-1-GP
F35 VSS_131 VSS_11 AA30 D26 VSS_109 VSS_71 AT16
D F37 VSS_132 VSS_12 AA34 D27 VSS_110 VSS_72 AT18 D
F38 VSS_133 VSS_13 AA5 D28 VSS_111 VSS_73 AT20
G2 VSS_134 VSS_14 AA8 D31 VSS_112 VSS_74 AT21
H14 VSS_135 VSS_15 AB14 D32 VSS_113 VSS_75 AT23
H16 VSS_136 VSS_16 AB28 U4 VSS_114 VSS_76 AT24
H20
H22
VSS_137
VSS_138
VSS_17
VSS_18
AB4
AC30
U8
V26
VSS_182
VSS_183
VSS_77
VSS_78
AT28
AT29
BOOT SELECT STRAPS
H26 VSS_139 VSS_19 AC34 V28 VSS_184 VSS_79 AT33
H28 VSS_140 VSS_20 AC38 V38 VSS_185 VSS_80 AT36 R407 1 2 1KR2J-1-GP
VSS_141 VSS_21 VSS_186 VSS_81
P_GNT_N1 (R) GNT1/ SATA1GP
H33
VSS_142 VSS_22
AC5 V40
VSS_187 VSS_82
AT38 BOOT DEVICE GPIO51 /GPIO19
H34 AC8 W12 AT7
H38 VSS_143 VSS_23 AD14 W20 VSS_188 VSS_83 AT8 R609 1 2 10KR2J-3-GP SATA1GP
VSS_144 VSS_24 VSS_189 VSS_84 3D3V_S0
H4
VSS_145 VSS_25
AD26 W22
VSS_190 VSS_85
AU3 LPC 0 0
H6 AD28 W28 AU39 R564 2 (R) 1 1KR2J-1-GP
H8 VSS_146 VSS_26 AE12 W3 VSS_191 VSS_86 AV12
H9
VSS_148 VSS_28
AE31 W5
VSS_193 VSS_88
AV17 SATA1GP/GPIO19 SPI 1 1
J31 AE4 W8 AV33
J37 VSS_149 VSS_29 AE41 Y1 VSS_194 VSS_89 AW30
J5 VSS_150 VSS_30 AE8 Y41 VSS_195 VSS_90 AW7
DESIGN NOTE:
K31 AF14 B25 WEAK INTERNAL PULLUPS ON GP51. DEFAULT SPI BOOT DEVICE.
K4 VSS_152 VSS_32 AF16 VSS_92 B3
K9 VSS_153 VSS_33 AF17 VSS_93 B30
L37 VSS_154 VSS_34 AF28 VSS_94 B33
L41 VSS_155 VSS_35 AG2 VSS_95 B38
M16 VSS_156 VSS_36 AG30 VSS_96 C25 P_GNT_N2 R841 1 (R) 2 1KR2J-1-GP
M18 VSS_157 VSS_37 AG34 VSS_97 C37
M20 VSS_158 VSS_38 AG38 VSS_98 C6
M22 VSS_159 VSS_39 AG8 VSS_99 D34
M24 VSS_160 VSS_40 AH14 VSS_115 D37
M26 VSS_161 VSS_41 AH16 VSS_116 D4
M28 VSS_162 VSS_42 AJ1 VSS_117 D6
N31 VSS_163 VSS_43 AJ28 VSS_118 D7
N35 VSS_164 VSS_44 AK24 VSS_119 D8
N38 VSS_165 VSS_45 AK37 VSS_120
N4 VSS_166 VSS_46 AK9 LYNX-POINT-2-GP-U
N8 VSS_167 VSS_47 AL11
R1 VSS_168 VSS_48 AL37
VSS_169 VSS_49 (KI.H8101.002) DESIGN NOTE:
R10 AL5 R576 1 (R) 2 1KR2J-1-GP SATA2GP DMI RX TERMINATION
VSS_170 VSS_50 3D3V_S0
R34 AM14 SATA2GP/GPIO36
R8 VSS_171 VSS_51 AM16 R579 1 (R) 2 10KR2J-3-GP
T17 VSS_172 VSS_52 AM18
T22 VSS_173 VSS_53 AM20
T23 VSS_174 VSS_54 AM24
VSS_175 VSS_55
DESIGN NOTE:
T25 AM26 R565 1 2 1KR2J-1-GP SATA3GP LOW:TLS CIPHER SUITE WITH NO CONFIDENTIALITY.
T26 VSS_176 VSS_56 AM35
VSS_177 VSS_57
SATA3GP/GPIO37 HIGH:TLS CIPHER SUITE WITH CONFIDENTIALITY.
T28 AM38 R597 2 (R) 1 10KR2J-3-GP
U1 VSS_178 VSS_58 AM4
VSS_181 VSS_61
C C
LYNX-POINT-2-GP-U
(KI.H8101.002)
DSWODVREN - On Die DSW VR Enable
HIGH Enabled (DEFAULT)
LOW Disabled
PCH1J 10 OF 11 RTC_AUX_S5
AT1 U11 TP_PCH_U11 1 TP46 TPAD28-1-GP-U

AT41 VSS_NCTF_1 TP22 U10 TP_PCH_U10 1 TP47 TPAD28-1-GP-U R486 1 2 390KR2J-GP DSWVRMEN
AU1 VSS_NCTF_2 TP23 AJ14 TP_PCH_AJ14 1 TP48 TPAD28-1-GP-U
AV1 VSS_NCTF_3 TP21 AK14 TP_PCH_AK14 1 TP49 TPAD28-1-GP-U
AV2 VSS_NCTF_4 TP20 K34 TP_PCH_K34 1 TP51 TPAD28-1-GP-U R487 1 2 390KR2J-GP
AV40 VSS_NCTF_5 TP14 K33 TP_PCH_K33 1 TP53 TPAD28-1-GP-U
AV41 VSS_NCTF_6 TP15 AH24 TP_PCH_AH24 1 TP69 TPAD28-1-GP-U
VSS_NCTF_7 TP12 (R)
AW2
AW40 VSS_NCTF_8 L16 TP_PCH_L16 1 TP54 TPAD28-1-GP-U
B40 VSS_NCTF_9 TP10 K16 TP_PCH_K16 1 TP57 TPAD28-1-GP-U
B41 VSS_NCTF_10 TP11 AM34 TP_PCH_AM34 1 TP70 TPAD28-1-GP-U
C41 VSS_NCTF_11 TP9
D1 VSS_NCTF_12
D41 VSS_NCTF_13
VSS_NCTF_14 R12 TP_PCH_R12 1 TP58 TPAD28-1-GP-U
TP3 N12 TP_PCH_N12 1 TP59 TPAD28-1-GP-U
TP4 L22 TP_PCH_L22 1 TP60 TPAD28-1-GP-U
TP1 K22 TP_PCH_K22 1 TP61 TPAD28-1-GP-U
TP2
!"#$%&&'#()*+
R4
TP5 K5 3D3V_S5
TP6 P5
TP7 L5
TP8
AC31
VSS
1
3D3V_S5
R604
10KR2J-3-GP
2
R457 QF2_2
B AF3 1KR2J-1-GP B
VSS AV21
VSS QF2
2
1 6
LYNX-POINT-2-GP-U IGC_EN_N R67 1 2 0R0402-PAD PCH_GP8 R601 1 2 10KR2J-3-GP QF2_1 2
5
1
HSW_STRAP_13 3 4
(KI.H8101.002)
R293
1KR2J-1-GP
MBT3904DW1T1G-2-GP
2
A A
<Core Design>
Wistron Corporation
Title
PCH(GND/STRAPS)
D
vSuperb -1
5 4 3 2 1
5 4 3 2 1
3D3V_S0
%&'"(&)*+&,- C446 1 2 SC1U6D3V2KX-GP
C392 1 2 SC1U6D3V2KX-GP
1D5V_S0 V_1P5_DAC_FB C406 1 2 SC1U6D3V2KX-GP
L31
D D
1 2 V_1P5_DAC_FB_N R68 1 2 0R0402-PAD
3D3V_S0
FCM1608KFG-301T05-GP
1
(68.00909.131) C46 C313 (R)
PCH CORE POWER DECOUPLING SC2D2U6D3V2MX-GP SC1U6D3V2KX-GP C447 1 2 SCD1U16V2ZY-2GP
V_1P05-FILTER CAPS: PLACE NEAR
2
PCH_1D05V
ENDS OF POWER CORRIDOR
DEFENSIVE DESIGN FOR
PCH_1D05V
VCCASEFLEX0_3P3 POWER
!"#$%&$'()*++,(-..(/#/0(1*2(3*,+4
C469 1 2 SC10U10V5KX-2GP
3D3V_S0
C470 1 2 SC10U10V5KX-2GP
PCH1H 8 OF 11 C307 1 2 SCD1U16V2ZY-2GP
PCH_1D05V AA19 A19 1D5V_S0 C315 1 2 SCD1U16V2ZY-2GP
VCC_1 DMI_IREF
1
AA20 N11
C479 1 2 SC1U6D3V2KX-GP AB16 VCC_2 FDI_IREF N10 C540 (R)
AB17 VCC_3 CLK_IREF B13 SCD1U16V2ZY-2GP C382 1 2 SC1U6D3V2KX-GP
2
AB19 VCC_4 PCIE_IREF A33
C553 1 2 SCD1U16V2ZY-2GP AB20 VCC_5 SATA_IREF
AD16 VCC_6 B37 C390 1 2 SC1U6D3V2KX-GP
VCC_7 VCCVRM_1 1D5V_S0
V17 A38
C554 1 2 SCD1U16V2ZY-2GP V19 VCC_8 VCCVRM_2 K1
V20 B39
V22 A39
C555 1 2 SCD1U16V2ZY-2GP V23 VCC_11 VCCVRM_5 A40
V25 VCC_12 VCCVRM_6 T14
VCC_13 VCCVRM 1D5V_S0
1
W17 C2
VCC_14 VCCVRM 1D5V_S0
W19 C1 C541
VCC_15 VCCVRM
W23 B4 1D5V_S0 SCD1U16V2ZY-2GP
PLACE C2 OF PCH EAST CORNER
2
W25 VCC_16 VCCVRM_7 A4
VCC_17 VCCVRM_8 AF2
VCCADAC V_1P5_DAC_FB
AC12
VCCIO_16 AE1 V_3P3_BG R12 1 2 0R0603-PAD-1-GP-U
VCC3_3_0 3D3V_S0 V_CPU_VCCIO2PCH
C PCH_1D05V R772 1 2 0R0805-PAD-1-GP-U V_1P05_XCK_DCB_FB_R AB1 B6 C
VCC VCC3_3_5
1
U12 AW21 C395 C1673
PCH_1D05V VCCCLK_1 VCC3_3_4
V14 SCD1U16V2ZY-2GP SC1U10V2KX-1GP
VCCCLK_2
1
(R) W14 AM7

3D3V_S0
2
C545 C544 AB2 VCCCLK VCCCLK3_3_1 AM9
PCH_1D05V SC1U6D3V2KX-GP SC10U10V5KX-2GP AA16 VCCCLK VCCCLK3_3_2 AP5
2
VCCCLK VCCCLK3_3_3
1
W16 AP7 C2 C126 C127
T16 VCCCLK VCCCLK3_3_4 AR4 SC1U6D3V2KX-GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C565 1 2 SC1U6D3V2KX-GP V16 VCCCLK VCCCLK3_3_5 AT5
2
VCCSSC VCCCLK3_3_6 AV4
P14 VCCCLK3_3_7 AW4
C556 1 2 SC1U6D3V2KX-GP P16 VCCIO_1 VCCCLK3_3_8 AW9
P17 VCCIO_2 VCCCLK3_3_9 AG12
P22 VCCIO_3 VCCCLK3_3_10 AK11
C557 1 2 SC1U6D3V2KX-GP P23 VCCIO_4 VCCCLK3_3_11 AV3
P25 VCCIO_5 VCCCLK3_3_12 AW3
P26 VCCIO_6 VCCCLK3_3_13 3D3V_S5
C566 1 2 SC1U6D3V2KX-GP P28 VCCIO_7 U30
1D5V_S0 VCCIO_8 VCC3_3_1 3D3V_S0
T19 W30
T20 VCCIO_9 VCC3_3_2
(R) AF19 VCCIO_10 AF26 C572 1 2 SC1U6D3V2KX-GP
C568 1 2 SCD1U16V2ZY-2GP AF20 VCCIO_11 VCC3_3_3
PCH_1D05V AF22 VCCIO_12 AG1 C443 1 2 SC1U6D3V2KX-GP
AF23 VCCIO_13 VCCSUS3_3
AP22 VCCIO_14 R41 C440 1 2 SC1U6D3V2KX-GP
VCCUSBPLL VCCPSPI V_3P3_A_EPW
C448 1 2 SC1U6D3V2KX-GP M14
VCCIO_15 AW26
PCH_1D05V VCCSUS3_3 3D3V_S5
1D05V_ME AA23
VCCASW_1
1
C444 1 2 SC1U6D3V2KX-GP AA25 AM33 C404 C515
AA26 VCCASW_2 VCCPSUS3_3 AN33 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C442 1 2 SCD1U16V2ZY-2GP AB22 VCCASW_3 VCCPSUS3_3
2
C445 1 2 SC1U6D3V2KX-GP AB23 VCCASW_4 AH18 V_3P3_A_EPW
AB25 VCCASW_5 VCCSUS3_3 AH20
VCCASW_6 VCCSUS3_3
STITCH CAP FOR GEN2 B AB26
VCCASW_7 VCCSUS3_3
AH22
ACKUP CLOCK ROUTE AD17 AJ20 C37 1 2 SC1U6D3V2KX-GP
AD19 VCCASW_8 VCCSUS3_3 AK20
AD20 VCCASW_9 VCCSUS3_3 P20
AD22 VCCASW_10 VCCSUS3_3 AP35 RTC_AUX_S5
B
AD23 VCCASW_11 VCCRTC B
W26 VCCASW_12 AV39
VCCASW_13 VCCDSW3_3 3D3V_S5
AD25 AW38 C569 1 2 SCD1U16V2ZY-2GP
VCCASW VCCDSW3_3
1
AF25 AW39 C521
1D05V_ME VCCASW VCCDSW3_3 AP33 SCD1U16V2ZY-2GP
VCCRTC RTC_AUX_S5
2
C39
V_PROC_IO V_CPU_VCCIO2PCH
C163 1 2 SC10U6D3V5MX-3GP
AU40 V_1P05_DSW_INT_R R2233 1 2 5D11R3F-1-GP V_1P05_DSW_INT_C C517 1 2 SC1U6D3V2KX-GP
DCPSUSBYP AU41
C571 1 2 SC1U6D3V2KX-GP DCPSUSBYP
AJ22 1
0402
TP_V_1P05_USBSUS_INT TP26 TPAD28-1-GP-U
DCPSUS
AW35 V_1P5_RTC_INT
DCPRTC
AH28 V_1P5_STBY_INT
DCPSST
1
C413
1
AE30 TP_PCH_AE30 1 TP22 TPAD28-1-GP-U C415 SCD1U16V2ZY-2GP
DCPSUS SCD1U16V2ZY-2GP
2
P19 TP_PCH_P19 1 TP28 TPAD28-1-GP-U
2
DCPSUS
LYNX-POINT-2-GP-U
(KI.H8101.002)
A A
<Core Design>
Wistron Corporation
Title
PCH Power
C
vSuperb -1
5 4 3 2 1
5 4 3 2 1
!"#$
!"#$%&'"())
D 15,16,17,28,29,38,39,41 SMB_CLK 3D3V_S5 3D3V_S0 12V_S0 12V_S0 3D3V_S0 D
PCIES1
15,16,17,28,29,38,39,41 SMB_DATA TOP BOTTOM
B1 A1
20 PCIE_TXP4 B1 A1
B2 A2 !"#$%&'%()$%&'*+,-./0'&('1-!'2(33(4'-5!65'7879
20 PCIE_TXN4 B3 B2 A2 A3
B4 B3 A3 A4
18 PCIEX1_CLKP B5 B4 A4 A5
SMB_CLK
18 PCIEX1_CLKN B6 B5 A5 A6
SMB_DATA
02 Do not mirror
B7 B6 A6 A7
20 PCIE_RXP4 B8 B7 A7 A8
20 PCIE_RXN4 B9 B8 A8 A9
B10 B9 A9 A10
17 PCIE_WAKE_N_X1 PCIE_WAKE_N_X1 B11 B10 A10 A11 PCIE_RST_X1 R1903 1 2 0R0402-PAD PLTRST_X1
B12 B11 A11 A12
24 PLTRST_X1 B13 B12 A12 A13 PCIEX1_CLKP
PCIE_TXP4 B14 B13 A13 A14 PCIEX1_CLKN
PCIE_TXN4 B15 B14 A14 A15 Follow Nadia
B15 A15
2
B16 A16 PCIE_RXP4 C1904 Add to prevent noise
B17 B16 A16 A17 PCIE_RXN4 SCD1U16V2ZY-2GP 02/22
B18 B17 A17 A18
1
B18 A18
PCISLT36-33-GP
C C
!"#$%&&'()*+),((*)-.
Add 0.1uF x 3
02/22
3D3V_S0 3D3V_S5
C1905
1
SCD1U16V2ZY-2GP
2
2
C1906 C1907 C1908
2
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
1
1
B B
Add 0.1uF x 6
12V_S0 02/22
2
2
C1909 C1910 C1911 C1912 C1913 C1901
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
1
1
<Core Design>
A A
Wistron Corporation
Title
PCIEX1
B
vSuperb -1
5 4 3 2 1
5 4 3 2 1
3D3V_S5
!"#$%"&'()*+, VRD PCH
Michael 2011/12/15 SIO_VREF SIO_VREF
2
For 5VSB Monitor !"#!$##$#!
R7954 1 2 0R0402-PAD
HDMI IN R7968 5V_S5
R7997
10KR2F-2-GP
R7996
10KR2F-2-GP
%&'()*+,-+#.+/-0+1**2+30454()+5-6,')*
28 DET_HDMI
HW Monitor 17K8R2F-GP
IT8732 Power On Strapping Options
1
SIO_VIN3 1 2 SIO_AGND REMOTE1+ DIMM_TMPIN2 Symbol value Description R8005
1
SIO_VDD_EN 1 2 1KR2J-1-GP
JP1 1 EUP
1
C7914 R7969 RT7901 RT7902
SCD1U16V2ZY-2GP C7925 NTC-10K-19-GP C7926 NTC-10K-19-GP
DSW_EUP_SEL R92
10KR2F-2-GP Pin 60 0 DSW
H_PECI R7932 1 2 0R0402-PAD PECI_SIO_R BAT_CTRL_PROCHOT 1 2 10KR2J-3-GP
2
#$;"&%!#
2
If without use these pins, Please pull-up to 3.3V.
VCC_CORE 100KR2J-1-GP 2 1 R7933 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP Don't let it floating +<==>*3))*@%C*65=
Layout Note: place it Layout Note: place it Pin19/24/25/30/48/57/71/75/77/80~83/96/95
LPC 17,44 LPC_AD0
SIO_AGND
near CPU VORE MOS near PCH EC_SMI#
SIO_AGND
17,44 LPC_AD1 3D3V_S0
R7958 R7906 1 2 1KR2J-1-GP
17,44 LPC_AD2
1
17,44 LPC_AD3 6K49R2F-1-GP
44 LPC_FRAME# G7901 (R)
D COPPER-CLOSE-GP-U SIO_VIN4 1 2 D
SIO_PSON_N R7919 2 1 4K7R2J-2-GP
1
Reset signals
1
C7912 R7959
SCD1U16V2ZY-2GP 10KR2F-2-GP
2 1 33R2J-2-GP RN7905
HM_VCCP PLT_RST# R7939 PLTRST*_SIO
!"#
2
RSMRST#_SIO 1 4
Power Manager
2
!"#!$"%$!& SP1_RTS_N PWROK3_2_R 2 3
1
PCIRST2# SP1_DSR_N
R7946 R7963 5V_S0 '())*+,-.-/-+01234'56+7(8+69+/:;-8 SP1_TXD
SIO_AGND 17K8R2F-GP SP1_RXD SRN10KJ-11-GP-U
17 PWROK3_1_R 10KR2F-2-GP RN7902
PLT_WLAN_RST# R7941 2 1 33R2J-2-GP SP1_DTR_N
SIO_VIN5 1 2 !"#<$"=$#% SP1_DCD_N SIO_DAT_DB 1 4
14,17,19 PWRGD_3V 2 SP1_RI_N SIO_CLK_DB 2 3
17 RSMRST#_SIO '())*+>??+0@6'56+7(8+A#
1
HM_VCCP_R
1
C7913 R7964 PLTRST_X1 R7927 1 2 33R2J-2-GP PCIRST1#
17,24,28,46,47,51,54,55 PM_SLP_S3# SRN10KJ-11-GP-U
17,36,53 PM_SLP_S4# SCD1U16V2ZY-2GP 10KR2F-2-GP
PLTRST_LAN R7924 1 2 33R2J-2-GP R133
2
1
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
C7908 HP_MUTE 1 2 1KR2J-1-GP
2
40 PWRBTN_IN SCD1U16V2ZY-2GP U7901
17 PM_PWRBTN#
#>?";$"!+0*@*05*3+A$B (R)
RI1#
DCD1#
DTR1#
SIN1/D_RX1
SOUT1/D_TX1
DSR1#
RTS1#
FAN_CTL4
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
STB#
AFD#
ERR#
INIT#
SLIN#
ACK#
SLCT
BUSY
PE
HSCK
2
R7952 12V_S0
SIO_AGND 56KR2F-GP
SIO_AGND SIO_VIN2 1 2
3D3V_A
1
SP1_CTS_N 1 102 SIO_AVCC3
CTS1# HMOSI
1
2 101
CLOCK C7911
SCD1U16V2ZY-2GP
R7953
10KR2F-2-GP SIO_PCIRSTIN# 3 5VSB_CTRL#/CIRRX2/GP16
PCIRSTIN#/CIRTX2/GP15/CPU_PG
HMISO
HSCE#
100 L7901
R8003
4 99 1 2 MHC1608S181NBP-GP 2 1 0R3J-0-U-GP SCALAR_SIO_PU
18 CLK_48M_SIO 3D3V_A 3VSB A3VSB 3D3V_A
2
LDRQ# 5 98 HM_VCCP_R (R)
18 CLK_PCI_SIO
2
LDRQ# VIN0/VCORE_0D8V
1
C7906 SCALAR_VDD_EN 6 97 For Power monitor function RN7904
SCD1U16V2ZY-2GP 7 SLP_SUS#/VLDT_EN/GP63 VIN1/VDIMMSTR_1D2V 96 SIO_VIN2 Note: SRN10KJ-6-GP
GNDD VIN2
1
CPU_FANTACH1 8 95 SIO_VIN3 C7907 C7905 Place C887,C884 close SIO_PCIRSTIN# 1 8
2
SIO_AGND CPU_FANCTL1 9 FAN_TAC1 VIN3 94 SIO_VIN4 SC1U10V2KX-1GP SC22U6D3V5MX-2GP 2 7
to IT8731
EC_SMI# 10 FAN_CTL1 VIN4/VLDT_12 93 SIO_VIN5 R7950 1 2 1KR2J-1-GP SIO_UART1_TX 3 6
!"#$! 3D3V_S0
2
(R) AC_IN# 11 FAN_TAC2/GP52 VIN5/5VDUAL 92 SIO_MAIN_VCC3 SIO_UART1_RX 4 5
PWR_CHG_ACOK R90 1 2 0R2J-2-GP PWR_CHG_ACOK_N 12 FAN_CTL2/GP51 VCC3 91 SIO_VREF C7901 1 2 SC1U10V2KX-1GP
FAN_TAC3/GP37 VREF SIO_AGND
BAT_CTRL_PROCHOT 13 90 REMOTE1+
17 SML1_CLK FAN_CTL3/GP36 TMPIN1
#$;"&%#& USB_CHARGER_CTL1 14 89 DIMM_TMPIN2
$%& 17 SML1_DATA
USB_CHARGER_CTL3 15 FAN_TAC4/GP35 TMPIN2 88
+<==>*3))*1344567*?@ABCTRL0 16 SUSWARN#/GP34 TMPIN3 87 RN7903
29 SIO_SMCLK0 SUSACK#/GP33 TSD- SIO_AGND
BLON_EN# 17 86 SIO_BL_EN 1 4
'()*+,- 29 SIO_SMDAT0
SIO_BKLT_CTRL 18 DPWROK/GP32 GNDA 85 ICH_RSMRST_N_R R7978 1 2 0R0402-PAD RSMRST#_SIO SIO_PANEL_ON 2 3
SIO_ATXPG 19 PWMOUT/GP31 RSMRST#/CIRRX1/GP55 84 SIO_VDD_EN
./((
48,49
48,49
BAT_SCL
BAT_SDA For AC OFF SEQUENCE SIO_UART1_RX
SIO_UART1_TX
20
21
ATXPG/GP30
SIN2/GP27
PCIRST3#/GP10
MCLK/GP56
83
82
LAN_LED3_CTRL
EC_ASF SRN10KJ-11-GP-U
SHDN_MUTE_AP_CTL 22 SOUT2/GP26 MDAT/GP57 81 SIO_AUDIO_MUTE
3D3V_S0 DSR2#/GP25 KCLK/GP60 RN7901
DCBATOUT SIO_BL_EN 23 80 ISO_DET
3D3V_S5 R7951 SIO_SI 24 RTS2#/GP24 KDAT/GP61 79 PM_SLP_S3#_3 1 TP168 TPAD28-1-GP-U SIO_AUDIO_MUTE 1 4
R7993 1 2 2 1 25 SI/GP23 3VSBSW#/GP40 78 R526 1 2 0R0402-PAD 2 3
PECI 4K7R2F-GP PWRGD_PS_L1 SIO_SCK SIO_SCK_R
SCK/GP22 PWROK2/GP41
PWROK3_2 PWROK3_2_R ISO_DET
1
2
33R2J-2-GP PANEL_SW 26 77 PM_SLP_S4_N R527 1 2 0R0402-PAD PM_SLP_S4#
R7992 R7995 SUSLED_R_N 27 DCD2#/GP21 SUSC#/GP53 76 SIO_PSON_N
(63.47234.1DL)
100KR2J-1-GP Q7905 RTD2136_LCD_VDD_EN 28 CTS2#/GP20 PSON#/GP42 75 PB_IN_N_1 SRN10KJ-11-GP-U
11,19 H_PECI 10KR2F-2-GP
RI2#/GP17 PANSWH#/GP43
6
29 74
C (63.10334.1DL) DTR2# GNDD RN6 C
R7994 SIO_CE_N 30 73 HP_MUTE
2
1
PWRGD_PS_L PWRGD_PS_L2 1 2 SIO_ATXPG R7922 SML1_CLK 31 CE_N/CIRTX1 PME#/GP54 72 SW_ON_N_SIO C7902 1 2 SC1U10V2KX-1GP BAT_SDA 1 4
2N7002KDW-GP 0R0402-PAD PWROK3_1_R 1 2 PWROK3_1 32 PCH_C1/GP14/VCORE_EN PWRON#/GP44 71 PM_SLP_S3# BAT_SCL 2 3
PWROK1/GP13 SUSB#
1
(75.27002.F7C) 33R2J-2-GP PCIRST1# 33 70 SYS_3VSB 1 R389 2 3D3V_S5

1
R7991 C7924 PCIRST2# 34 PCIRST1#/GP12 SYS_3VSB 69 VBAT_SIO 100R2F-L1-GP-U R7925 1 2 0R0402-PAD

PCIRST2#/GP11 VBAT RTC_AUX_S5 SRN10KJ-11-GP-U
20KR2J-L2-GP SCD1U16V2ZY-2GP 35 68 SIO_COPEN#
3D3V_A
1
SIO_VCORE 36 3VSB COPEN# 67

OTHERS (R)
CLK_48M_SIO R7926 1 2 0R0402-PAD CK_SIO 37 VCORE 3VSB 66 BAT_SCL
3D3V_A Case Open Detection (R)
2
CLKIN D_RX0/SMCLK2/GP46
1
26,27 SIO_AUDIO_MUTE C7916 38 65 BAT_SDA C7917 Note: COPEN# should be connected to GND
GNDD D_TX0/SMDAT2/GP47
1
SCD1U16V2ZY-2GP C7919 C7918 SC22U6D3V5MX-2GP
19 H_A20GATE SCD1U16V2ZY-2GP C7915
when this function is not be used.
SC2D2U6D3V2MX-GP 1344567*8936:56*/012/
PCH_D1/SST/AMDTSI_D
19 H_RCIN#
SCD1U16V2ZY-2GP
IO_SCI#/GP85/SMDAT0
2
2
19 EC_SMI# Note: Note:
19,44 INT_SERIRQ *Place C866, C898,C890 close to IT8731 *Place C869,C883 close to IT8731
3D3V_A
PECI/AMDTSI_C
GP72/KSO0/JP1
*Recommended net "V_3P3_A" minimum trace width 12mils.
GP86/SMCLK0
KRST#/GP62
34 LAN_LED3_CTRL RN7909
GP77/KSO5
GP76/KSO4
GP75/KSO3
GP74/KSO2
GP73/KSO1
GP71/KSI1
GP70/KSI0
LFRAME#
LRESET#
SO/GP50
1 4
SMDAT1
SMCLK1
PCIRST2#
SERIRQ
PCICLK
WRST#
PCIRST1# 2 3
SPI Interface !"#$%"&%#'
GA20
LAD0
LAD1
LAD2
LAD3
27,28 SHDN_MUTE_AP_CTL
46 SIO_PSON_N ()*+,-./0.12$!34(5 (R)
28 SIO_UART1_RX SRN10KJ-11-GP-U
IT8732F-CX-GP
28 SIO_UART1_TX
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
(R)
46 CTRL0_EUP 3D3V_A R8013
!"#$%"&%"' LAN_LED3_CTRL 1 2 10KR2J-3-GP
11,20,44 PLT_RST#
INT_SERIRQ
LPC_FRAME#
())*+,-!#$.*/012/
25 PLTRST_LAN LPC_AD0 SIO_SMDAT0 R61
38 PLT_WLAN_RST# LPC_AD1 SIO_SMCLK0 KSO0 1 2 10KR2J-3-GP
23 PLTRST_X1
2
LPC_AD2 DET_HDMI
R7965 R7966 R7967 R7947 R7948 R7949
LPC I/F LPC_AD3 BRIGHTNESS_N
40 SUSLED_N 1026 3D3V_A H_RCIN# KSO0
28 SIO_PANEL_ON 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP
H_A20GATE SIO_PANEL_ON
R7938 1 2 SIO_WRST# CLK_PCI_SIO BATT_CTRL_EVENT
20,34 PANEL_SW
1
U7902 SIO_SO LVDS_BL_EN_1

30 SIO_BKLT_CTRL
100KR2J-1-GP PLTRST*_SIO PLTRST*_SIO_R
1
SIO_CE_N 1 8 C7903 SIO_WRST# PECI_SIO_R
19 EC_ASF SIO_SO 2 CE# VCC 7 SIO_HOLD# SC1U16V3KX-2GP SIO_CLK_DB PLT_WLAN_RST#_A
SIO_WP# 3 SO HOLD# 6 SIO_SCK SIO_DAT_DB SML1_DATA
WP# SCK For EC domain,
2
4 5 SIO_SI 3D3V_S0
43 SIO_COPEN# GND SIO reset after power up
34 BRIGHTNESS_N
PM25LD010C-SCE-GP LDRQ# R8000 1 2
10KR2J-3-GP
1
28 BLON_EN# (72.25010.R01) C7909

R8001 1 2
29,30 RTD2136_LCD_VDD_EN change to 1Mbit SCD1U16V2ZY-2GP (R) PANEL_SW 10KR2J-3-GP
29,30 RTD2136_BKLT_EN
2
1. layout trace is as far as possible short contract issue, BRIGHTNESS_N R8004 1 2

10KR2J-3-GP
30 SIO_BL_EN
28 SCALAR_VDD_EN and change P/N
30 SIO_VDD_EN
2. Pull-up resistor 1Kohm near SPI Flash
28 ISO_DET
B B
17,28 PANEL_BTN_EVENT#
FAN_PWR
27 HP_MUTE 5V_S0 12V_S0
3D3V_A
+"&,-&)./&01!&2"34%"5 !"#$%&'()*+, 6$7879$ -744$%:&,;7%4&<+=6
FAN CTRL
1
(R) !"#!###$%&'()&%*#+%,-&./0)
2
R7984 2 10R5J-5-GP C7923 SUSLED_R_N R7910 1 2 0R0402-PAD SUSLED_N

+11%23425%67%8.090:6%/0&;&<0 H_PROCHOT_N 11,49,51
2
R8007 R7989 SC10U16V5ZY-GP
2
0R0402-PAD 0R2J-2-GP FAN_PWR R7961 =5,>'?@AB'@ACD@C%EF=',G>%'?@AB'@ACD%%

CHARGER CTRL (R) F1
!"#!$##$!" 10KR2J-3-GP
D
FAN_PWR_N 1 2 5V_S0 12V_S0 PB_IN_N_1 C7921 2 1 SCD1U16V2ZY-2GP
To SIO
1
D4
78+9&'()*+:;"";+'(3+:<=;"
1
R7974 (83.00355.F1F)
35 USB_CHARGER_CTL1
1
POLYSW-1D5A8V-3-GP (R) CTRL0 1 2 CTRL0_EUP 1 R7976 2 PWRBTN_IN BAT_CTRL_PROCHOT G (84.2N702.J31)

35 USB_CHARGER_CTL3 R8008 R7979 0R0402-PAD 0R0402-PAD PM_SLP_S3#A K PM_SLP_S3#_3
17,24,28,46,47,51,54,55 PM_SLP_S3#
2
1KR2J-1-GP 4K7R2J-2-GP Q20
S
3D3V_S0 2N7002-7F-GP
SDMK0340L-7-F-GP
2
R7977
2
R7980 1 (R) 0R2J-2-GP (R) R91

CPU_FANTACH1_1 2 1 CPU_FANTACH1 C7920 R7975
To PCH 10KR2J-3-GP
1
1
SCD1U16V2ZY-2GP SW_ON_N_SIO 1 2 PM_PWRBTN#

2
K
R7982 D7901 FAN1 100R2J-2-GP C7910 0R0402-PAD
1
2K2R2J-2-GP 1N4148WS-7-F-GP FAN_PWR 5 SC100P50V2JN-3GP
!"#$%&'( (R) 1
!"#$%&'$(()*++*,(-*./*.'
2
2
2
A
R7983 100R2J-2-GP 3
CPU_FANCTL1 1 2 CPU_FANCTL1_CONN 4
43 SP1_RTS_N 6
43 SP1_DTR_N
43 SP1_DSR_N
1
C7922 CLX-CON4-9-GP 0.8VCC3-> S0_PWR_GOOD

43
43
SP1_RXD
SP1_DCD_N
SC1U25V5ZY-4GP 3D3V_S0 !"#$%&'""(&)*
43 SP1_TXD (R) SIO delay:
2
43 SP1_CTS_N
1
3D3V_A
43 SP1_RI_N 23h<3:2>
1KR2J-1-GP
00b 01b 10b
1
R7928
400ms / 15ms / 200ms R7998
2
10KR2F-2-GP
PWROK3_1_R R7929 1 2 0R0402-PAD PWRGD_3V_LL PWRGD_3V
2
3D3V_A
3D3V_S5 LVDS_BL_EN*
#%&&'()*+,-.*/&(0 michael 2012/2/16 SB

1
3D3V_A
3D3V_A R7944
6
reserve for iRST circuit 1KR2J-1-GP
2
1
19 BATT_CTRL_EVENT (R) R7999 Q9505
R7971 10KR2F-2-GP
according to customer's request 2N7002KDW-GP
2
49 PWR_CHG_ACOK
2
1
10KR2J-3-GP PWRGD_3V_B_1 C7904 R7943 (75.27002.F7C)
49 AC_IN#
R7962 SC100P50V2JN-3GP 20KR2J-L2-GP
1
A A
10KR2J-3-GP (R)
1
2
(R)
6
PLTRST*_SIO_PU PLT_WLAN_RST#_PU
1
Q7906 LVDS_BL_EN_1
PWROK3_2_R R7942 1 2 1KR2J-1-GP RSMRST*_R (R)
2N7002KDW-GP
6
3D3V_A (R)
1
3
6
Q7907 3D3V_A 3D3V_S0 RTD2136_BKLT_EN

(R) Q7908
2
2N7002KDW-GP (R)
2
2N7002KDW-GP R7985
1
R7970 R7986 10KR2J-3-GP

1
10KR2J-3-GP 10KR2J-3-GP (R)

<Core Design>
(R) (R)
1
1
R7955 (R) R7945 (R)

PLTRST*_SIO PLTRST*_SIO_C 2 1 PLTRST*_SIO_R PLT_WLAN_RST#_A PLT_WLAN_RST#_C 2 1 PLT_WLAN_RST# Wistron Corporation
33R2J-2-GP 33R2J-2-GP Taipei Hsien 221, Taiwan, R.O.C.
Title
SIO ITE8732
Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
If CLK_REQ_N is connected
(R)
to PCIECLKRQ[1:2]#,the
C31
CLK_REQ_N pull-up resistor XF1
PCIE should be connected to +V3.3S. !"#$%&'$()*)!"#$%&'$# 2 1 24 Michael 2011/12/17 V_3P3_LAN
MDI3- 23 1:1 2 MDI3-_C
18
18
CK_PCIE_3_GLAN_DP
CK_PCIE_3_GLAN_DN
+,-./01)1-/23)4/035)6)7/48),0 SCD1U16V2ZY-2GP The connector will be replaced
9:)7/48)8;<=/01 ;<=>*?C> 1
20 HSI_DP3 MCT4 Pin1 TX_D1+ RJ1
20 HSI_DN3
V_3P3_LAN (</+).,);</+)8>,-42)?33;)<@<A (%D%(@%4&>=;E&$#B&F'.%"&D-AA%D. 14
20 HSO_C_DP3 Pin2 TX_D1- 9 SPEED_100*_L1
@/.>)BC)7/48
ORANGE GREEN
20 HSO_C_DN3
1
(R) Pin3 RX_D2+ 10 LAN_SPEED
RA961 MDI3+ 22 3 MDI3+_C
C32
10KR2J-3-GP Pin4 B1_D3+ 11 SPEED_1000*_L1
2 1 21 1 MDI0+_R
U72 MDI2- 20 1:1 5 MDI2-_C Pin5 B1_D3-
2
2 MDI0-_R
LANCLK_REQ_N R714 1 (R) 2 0R2J-2-GP LANCLK_REQ_N_R 48 13 MDI0+ SCD1U16V2ZY-2GP Pin6 RX_D2- 3 MDI1+_R
PLTRST_LAN 36 CLK_REQ_N MDI_PLUS0 14 MDI0- 4 MDI2+_R
D OTHERS PE_RST_N MDI_MINUS0 4 MCT3 Pin7 B1_D4+ 5 MDI2-_R D
CK_PCIE_3_GLAN_DP 44 17 MDI1+ 6 MDI1-_R
PE_CLKP MDI_PLUS1
CK_PCIE_3_GLAN_DN 45 18 MDI1- Pin8 B1_D4- 7 MDI3+_R
PCIE
PE_CLKN MDI_MINUS1 8 MDI3-_R
34 LINK*_ACTIVITY_L
HSI_DP3 C431 1 2 SCD1U16V2KX-3GP HSI_LAN_DP3_I 38
PETP MDI_PLUS2
20 MDI2+ (R) Pin10 Pin9 12 LAN_LED_ACT
HSI_DN3 C432 1 2 SCD1U16V2KX-3GP HSI_LAN_DN3_I 39 21 MDI2- MDI2+ 19 6 MDI2+_C + - GREEN
GREEN
17 LAN_DISABLE_N PETN MDI_MINUS2 C33
MDI
13 LINK*_ACTIVITY_L
3D3V_S5 HSO_C_DP3 41 23 MDI3+ V_3P3_LAN 2 1 18 Pin10 Pin11 ORANGE 15
17 SMLINK0_CLK 42 PERP MDI_PLUS3 24 17 1:1 8
17 SMLINK0_DATA
HSO_C_DN3
PERN MDI_MINUS3
MDI3- MDI1- MDI1-_C + -
RA866 2 (R) 1 4K7R2J-2-GP
V_3P3_LAN RJ45-13P-26-GP
1
24 PLTRST_LAN SCD1U16V2ZY-2GP Pin12 Pin13 Green (22.10285.051)
SMLINK0_CLK 28 6 SVR_EN R698 1 2 0R0402-PAD + -
SMBUS
RA862 SMLINK0_DATA 31 SMB_CLK SVR_EN_N 7 MCT2 V_3P3_LAN
XRF_TDC1
XRF_TDC2
17 LANW AKE_N SMB_DATA
1
4K7R2J-2-GP 1 VCC3P3_L_1 RA863 2 1 4K7R2J-2-GP CA628 CA575
-12131,4%56,4%7,89,:/312,;)<<1/3 RSVD1_VCC3P3 V_3P3_LAN
SC22U6D3V5MX-2GP SCD1U16V2ZY-2GP
17 LANCLK_REQ_N
2
LANW AKE_N 2 5
2
LANWAKE_N VDD3P3_IN
17 LAN_EN_PW R
2
LAN_DISABLE_N R697 1 2 0R0402-PAD LAN_DISABLE_N_I 3 4 VDD3P3 R39 1 2 0R0603-PAD-1-GP-U
V_3P3_LAN MDI1+ 16 9 MDI1+_C
LAN_DISABLE_N VDD3P3_4 15 C34
D3102
VDD3P3_15
2
19 CA574 2 1 15 AZ5125-01H-R7G-GP
LINK*_ACTIVITY_L 26 VDD3P3_19 29 SC1U10V3ZY-6GP MDI0- 14 1:1 11 MDI0-_C R3110 R3109 C3127
LED0 VDD3P3_29
1
SPEED_1000*_L 27
LED
!"#$%&'%#(&!)'* (R) (R) (R) (R)
330R2J-3-GP
330R2J-3-GP
2
LED1
SCD1U16V2ZY-2GP
SPEED_100*_L 25 SCD1U16V2ZY-2GP
LED2
2
8 1D05V_ME C36 10 MCT1 2010/09/20
VDD0P9_8 11 LAN surage solution
SC1U6D3V2KX-GP
1
TPAD28-1-GP-U TP115 1 TP_LAN_JTDI 32 VDD0P9_11 16 (R)
JTAG_TDI VDD0P9_16 R3153
1 34
JTAG
TPAD28-1-GP-U TP114 TP_LAN_JTDO
1 2 10KR2J-3-GP 33 JTAG_TDO 22 LAN_LED_ACT 2 1
V_3P3_LAN RA959 (R) TPEV_LAN_JTMS
JTAG_TMS VDD0P9_22 0.9Vdc
RA859 1 (R) 2 10KR2J-3-GP TPEV_LAN_JTCK 35 MDI0+ 13 12 MDI0+_C
VDD0P9
JTAG_TCK
1
37 330R2J-3-GP R3107
VDD0P9_37 2 1
Keep short and wide (R) XFORM-24P-27-GP SPEED_1000*_L1 SPEED_1000*_L
LAN_XTALO 9 40 RA1020 (68.IH601.301) 330R2J-3-GP
LAN_XTALI 10 XTAL_OUT VDD0P9_40 43 0R5J-5-GP
XTAL_IN VDD0P9_43 R3108
46 SPEED_100*_L1 2 1 SPEED_100*_L
2
VDD0P9_46
2
VDD0P9_47
47 Michael 2012/2/15 330R2J-3-GP
RA857 LAN_TEST_EN 30
TEST_EN
0R0402-PAD LA26 2011/06/26
LAN_RBIAS 12 7 CTRL_0P9 1 2 SB XF1 horizontal and swap
RBIAS CTRL_0P9
pair for layout routing
1
49 COIL-4D7UH-29-GP
XA5 GND_EPAD
1
CA319 CA577 CA569 CA570
3 2 WG1217LM-GP SC22U6D3V5MX-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
(71.01217.C03)
2
!"#$%"&%"' 4 1
1
MCT3
MCT4
MCT1
MCT2
()**+,-)./,*+01
RA960 RA856
MDI0+
MDI1+
MDI2+
MDI3+
MDI0-
MDI1-
MDI2-
MDI3-
XTAL-25MHZ-145-GP
1LAN_XTALO_1
1KR2J-1-GP 3K01R2F-3-GP
C
(82.30020.H71) !"#$%#&#'()%((*'#+,#&#'+-,. 0.9Vdc POWER OPTIONS Link Act
+- 30ppm CL:18P C
2
R95 1 2 1MR3F-GP
/"'$%#&#'(01%((*'#+,#&#'+2,.
1
1
Internal SRV Shared with PCH's 1.05V SVR Giga 100 10
75R3J-L-GP
75R3J-L-GP
75R3J-L-GP
75R3J-L-GP
R3147 R3154 R3155 R3156
CA571 CA573
SC22P50V2JN-4GP SC22P50V2JN-4GP EC3116 EC3109 EC3110 EC3111 EC3112 EC3113 EC3114 EC3115
X
2
1
Orange Green
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
(78.27034.1FL) (78.27034.1FL) Link
LA36 : STUFF LA36 : NO STUFF
2
RA1020 : NO STUFF RA1020 : STUFF PCB Act Blink Blink Blink
R968 : STUFF R968 : NO STUFF MCT_R
RA886 : NO STUFF RA886 : STUFF
1
C3131
SC1KP2KV6KX-GP
2
*NOTE: Clarkville has 0.9V internal SVR. However it is also
possible to disable this 0.9V iSVR and Clarkville can support the
!"#$%&'())*& external 1.05V supply (example sharing from PCH's 1.05V SVR). When
sharing, make sure the 1.05V_SHARED is controlled by the SLP_LAN
!""#$%&'())*& signal. Both +3.3V_LAN and 1.05V_SHARED rails are remained powered
on during ALL Sx states, as required to support WOL.
!'$%&+(,*-)&
./012)%&3)4456&71-80&94,:8
'()*#+,-. !"#
MCT1
MCT2
MCT3
MCT4
U3111
U3110 5
5V_S5
5
5V_S5
1
GDT5 GDT7 GDT6 GDT8
!"#$%"&%!$ 2
2
GT1206-200ASMD-GP
GT1206-200ASMD-GP
GT1206-200ASMD-GP
GT1206-200ASMD-GP
'()*+,(-./.-0123-4(51(4-"-637 TVLST2304AD0-1-GP
6
(R) (R) (R) (R) TVLST2304AD0-1-GP (75.09904.07C)
6
(75.09904.07C)
2
B MDI0- B
L3106 L3107 L3108 L3109 MDI2- MDI0+
MDI3-_C 1 2 MDI3-_R MDI2-_C 1 2 MDI2-_R MDI1-_C 1 2 MDI1-_R MDI0-_C 1 2 MDI0-_R MDI2+ MDI1-
MDI3- MDI1+
MDI3+_C 4 3 MDI3+_R MDI2+_C 4 3 MDI2+_R MDI1+_C 4 3 MDI1+_R MDI0+_C 4 3 MDI0+_R MDI3+
MCM1012B900FBP-GP-U MCM1012B900FBP-GP-U MCM1012B900FBP-GP-U MCM1012B900FBP-GP-U

(66.R0036.04L) (66.R0036.04L) (66.R0036.04L) (66.R0036.04L)
!"#!$##$!%
&'(()*+,*-..*#""/*01/
$%& DCBATOUT V_3P3_LAN
1
1
1
C3139 C3138 C3136 C3135 C3134 C3133
C9654 C9655 C9656 C9657 C9658 C9659 C9660 SCD1U16V2ZY-2GP
2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
'()*/01.,
3D3V_S5 AO3419 PMOS 3.5A
DCBATOUT
+,-'.&/01&!23&4%"#5&$)($-).&667&8%()95&:0
3D3V_S5
GH+&$I#'A%&9,(&$,'.(,"&4%"#5667&>J>< 3D3V_S5
2
R3159
2010/05/06 R3162 100KR2J-1-GP
1
(R) 10KR2J-3-GP
R3163 (R)
1
390KR2J-GP
S
Q3103
2
R3161
2
LAN_EN_2 2 1 LAN_EN_3 G AO3419L-GP R3164

0R5J-5-GP
C
1KR2J-1-GP
1
R3160 C3141
1
LAN_EN_PW R 1 2 LAN_EN_1 B Q3104 SCD1U10V2KX-4GP R3158 (84.02130.031) (R)

1
D
MMBT3904-3-GP (78.10423.2FL) 47KR2J-2-GP

10KR2J-3-GP
2
E
1
C3140
2
SC4D7U10V3KX-GP (84.T3904.K11)
A (R) A
2
2010/05/10 V_3P3_LAN
For NMOS solution
84.03418.031
84.00359.C31
2
R79
10KR2J-3-GP ;<=>*?;*&#44&9,(&"%@%#A%&B(%@%'.
<Core Design>
1
Wistron Corporation
Title
INTEL LAN CLARKVILLE 1217

D
vSuperb -1
5 4 3 2 1
5 4 3 2 1
!"#$%"'%!L
F_HPO_R ,-./012,8),D)=G),IF6JK
F_HPO_L
1+23+&8(&+,-
MIC_VREFL
MIC_VREFR1 TP7906 TPAD28-1-GP-U

!"#$%&' AGND MIC2_VREFO
Analog Moat Digital Moat
SC2D2U10V3KX-1GP
17 AUD_LINK_SDIN
17 HDA_CODEC_SDOUT
17,27 HDA_CODEC_RST# closed to codec
17 HDA_CODEC_SYNC C2912
17 HDA_CODEC_BITCLK ADU_LDO_CAP 1 2 AGND
SC10U16V5KX-GP-U
1
C2913 C2911
AUD_VREF 1 2SCD1U10V2KX-5GP
AGND
2
D D
C2936 1 2
SC2D2U10V3KX-1GP V_5_CODEC V_5_CODEC

5V_S5
AUD_CPVEE
"(%) V_5_CODEC
L2904
1 2
1
AGND
SC100P50V2JN-3GP
37 DMIC_DATA C2904
37 DMIC_CLK SC2D2U10V3KX-1GP C2902 C2928 MHC1608S601LBP-GP
2
2 1AUD_CBN SC10U16V5KX-GP-U SCD1U10V2KX-5GP
2
C2906 C2903 C2933 D8202
SC10U16V5KX-GP-U SCD1U10V2KX-5GP AUD_CBP
Analog Moat (R) AZ5125-01H-R7G-GP
2
(R)
36
35
34
33
32
31
30
29
28
27
26
25
U2901 AGND !"#$%"&%"'
AGND
CBP
CPVEE
HP-OUT-L
MIC1-VREFO-L
MIC2-VREFO
LDO-CAP
AVSS1
AVDD1
CBN
HP-OUT-R
MIC1-VREFO-R
VREF
5V_S0 AGND 9+02#,-./012,8),*+@2,IF6JK
!/01.&("#$%&'#&(#)%(&*+,20 !467&8(&+,-
!*+(%)+),(-,
1
AGND
L2913 SC10U10V5ZY-1GP 37 24 LINE1_R 20110113EMI
1 2 AVSS2 LINE1-R
1
1
27 SPEAKER1_L1 C2905 FCM1608KFG-301T05-GP C2916 C2915 38 23 LINE1_L
SC10U10V5ZY-1GP C2917 AVDD2 LINE1-L
27 SPEAKER1_R1 SCD1U16V2ZY-2GP (68.00335.141) (R) D)=G),H+-,:0,=)@+>+2@,8),H:D#
AUD_PVDD_1 39 22 FM_R_CODEC 1+23+&04"&)5
2
2
PVDD1 MIC1-R
27 FM_R_CODEC SPKR_L+ 40 21 FM_L_CODEC
SCD1U16V2ZY-2GP SPK-L+ MIC1-L
27 FM_L_CODEC
SPKR_L- 41 20
SPK-L- MONO-OUT R2906 20KR2F-L-GP
42 19 JDREF_1 1 2
!"#$#%&'()* SCALAR_AUDIO_JD
27 MIC2_R PVSS1 JDREF AGND
27 MIC2_L
43 18 R2901 1 2 20KR2F-L-GP MIC_IN_JD
27 MIC2_VREFO PVSS2 SENSE_B
SPKR_R- 44 17 MIC2_R
27 LINE1_R SPK-R- MIC2-R
27 LINE1_L !"#$%&'#&(#)%(&*+,-. SPKR_R+ 45 16 MIC2_L
!467&04"&)5 !"#$%"&%"'
27 COMBO JACK SPK-R+ MIC2-L ()**+,-./012,3-/4/5,678,8),9:;<!
AUD_PVDD_2 46 15 LINE2_R
34 MIC_IN_JD PVDD2 LINE2-R =748+,*242-8,>70-8+)0
27 JD_HP_R
1
(R) C2918 !"#$%"&%!! COMBO JACK 47 14 LINE2_L

27 JD_LOT_R
C2923 EAPD/COMBO_JACK LINE2-L !"#$#%&+,-&.&/0(
C SC10U10V5ZY-1GP '())*+,-./01+2(+,(34(+5.67 48 13 SENSE_A R2903 1 2 39K2R2F-L-GP JD_LOT_R C
2
SPDIFO SENSE_A
GPIO0/DMIC-DATA
27 F_HPO_R
GPIO1/DMIC-CLK
49 R282 1 2 10KR2F-2-GP JD_HP_R
27 F_HPO_L SCD1U16V2ZY-2GP GND
27 MIC_VREFL
SDATA-OUT
SDATA-IN
DVDD-IO
PCBEEP
RESET#
BIT-CLK
DVDD1
DVSS2
Digital Moat
SYNC
PD#
1
10
11
12
ALC269Q-VC-GR-GP
!"#!%#"%"#
L2912
?20@)5,*7112*8,A24282,/44
1 2 +AUD_DVDD_1
./0102 3D3V_S0
1
1
MHC1608S601LBP-GP C2930 C2914 +DVDD-IO 3D3V_S0
SCD1U16V2ZY-2GP
1
C2919
2
28 SCALAR_SENSE_B SC10U10V5ZY-1GP SCD1U16V2ZY-2GP

28 SCALAR_OUT_R
2
28 SCALAR_OUT_L
DMIC_DATA
HDA_SDIN0_C
20110113EMI
C2935 1 2 SC100P50V2JN-3GP
1 2 SC100P50V2JN-3GP HDA_CODEC_RST# !7$7"-&+9&:)5;<
C2934
DMIC_CLK HDA_CODEC_SYNC
(R)
.*'3 LINE2_L R518 1 2 SPEAKER1_L1
2 R2912 1 AUD_LINK_SDIN 0R2J-2-GP
33R2J-2-GP /0(
27 SPKR_L+
27 SPKR_L-
HDA_CODEC_BITCLK
20101229 LINE2_R R517 1
(R)
2 SPEAKER1_R1
27 SPKR_R-
PD#_C Remove 33 ohm 0R2J-2-GP
HDA_CODEC_SDOUT
27 SPKR_R+
B (S) B
LINE2_L R530 1 2 SCALAR_OUT_L
0R2J-2-GP
,45627 (S)
!"#$#%
LINE2_R R531 1 2 SCALAR_OUT_R
0R2J-2-GP
24,27 SIO_AUDIO_MUTE
!"#$#%&'()* 80.)0+3$9+:(22(;+'0,2/0<+85=>
SCALAR_AUDIO_JD2 R2904 1 2 39K2R2F-L-GP SCALAR_AUDIO_JD !"#!$"%$!&
'())*+,--+*./01,2+345+67/0
!"#$%&'%#(&)*+%$
D
3D3V_S5
SCALAR_SENSE_B G (84.2N702.J31)
Q3010
S
2
2N7002-7F-GP
R1106 R1107
1KR2J-1-GP 1KR2J-1-GP
(N) (N)
PD#_C
1
AGND 3 1
2
PD 1 Q295
PMBS3904-1-GP R525
(N84.T3904.K11) 0R2J-2-GP
2
3
(R)
HDA_CODEC_RST# 2 R1109 1 AUD_LINK_RST_N1 1 Q297
1
PMBS3904-1-GP
#$B"C%#!,()**+,-./012,8),DEF 10KR2J-3-GP
(N84.T3904.K11)
2
(N)
A C10 2 1 SCD1U16V2ZY-2GP C30 2 1 SCD1U16V2ZY-2GP A
PD_N1
3#45'&67&%86$'&93*
C11 2 1 SCD1U16V2ZY-2GP AGND C25 2 1 SCD1U16V2ZY-2GP AGND
3
SIO_AUDIO_MUTE 2 R1110 1 SIO_AUDIO_MUTE# 1 Q298

C19 2 1 SCD1U16V2ZY-2GP AGND C27 2 1 SCD1U16V2ZY-2GP AGND PMBS3904-1-GP
10KR2J-3-GP <Core Design>
(N84.T3904.K11)
2
(N)
C12 2 1 SCD1U16V2ZY-2GP AGND C26 2 1 SCD1U16V2ZY-2GP AGND
Wistron Corporation
C24 2 1 SCD1U16V2ZY-2GP AGND C29 2 1 SCD1U16V2ZY-2GP AGND /:12;:-;/2 Taipei Hsien 221, Taiwan, R.O.C.
!<=5>%&'#&?+@&!#5'A#" Title
AGND AGND
Audio Codec ALC269
Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
!"#
,-) MIC2_VREFO
For 33Mhz TPM EMI issue (19V)
!"#$%"&%!$ ESD D8204
1 R3044
DCBATOUT
3
SPEAKER1_L1 C3054 2 1 SC1U10V2KX-1GPSPEAKER1_L1_R 2 AMP_L
26 MIC2_VREFO
D14 '())*+,-.+/*(/0+)0123240+5'.6 JD_LOT 1 75R2J-1-GP
1
BAT54AH-1-GP (A) (A)
(75.00054.R7D) 3 (A) R86
26 MIC2_L
26 MIC2_R SPEAKER1_R1 C3056 2 1 SC1U10V2KX-1GPSPEAKER1_R1_R 1 R3043 2 AMP_R 15KR2F-GP
COMBO 2
75R2J-1-GP
2
R85
MIC2_R_C
MIC2_L_C
(A)
2
(A) UVP 1 2 UVP*
AZ5125-02S-R7G-GP
1
(R) 90K9R2F-GP (A)
(A) R87 5V_PVDD
2
D3002 1KR2F-3-GP
#$%&$'()#* R3040 R3038 !%&34)*5!
1
2K2R2J-2-GP 2K2R2J-2-GP F_HPO_R 1 (A) R3045 (A) R3046 (A)
2
R82
26 F_HPO_R 3 1KR2J-1-GP 1KR2J-1-GP 3K16R2F-GP
26 F_HPO_L
1
D
26 JD_LOT_R
R3039 F_HPO_L 2 !"#$%&'()*+' D
L3010
2
26 COMBO JACK 1KR2J-1-GP AGC
MIC2_L C3039 1 2 FM_L_CODEC_1 1 2 FM_L_CODEC_I 1 2 MIC_IN_L_JK MIC_IN_L_JK 34
1
26 FM_L_CODEC MHC1608S601LBP-GP AZ5125-02S-R7G-GP (A)
1
26 FM_R_CODEC SC2D2U10V3KX-1GP MIC_IN_R_JK MIC_IN_R_JK 34 (R) AGND AGND (A) R83
L3009
MIC_IN_JD C438 1K24R2F-GP
MIC_IN_JD 26,34
MIC2_R C3040 1 2 FM_R_CODEC_1 1 2 FM_R_CODEC_I 1 2 SC1U10V2KX-1GP
26 MIC_VREFL
2
SC2D2U10V3KX-1GP R3037 MHC1608S601LBP-GP
1KR2J-1-GP D/23)'E)F,003=.,+
1
C3036 C3038
SC100P50V2JN-3GP SC100P50V2JN-3GP
<()4+/(=8 (78.10224.2FL) (78.10224.2FL) ,-.$%&'()*+'
2
+,
5V_PVDD
26 JD_HP_R
AGND
26 LINE1_R
26 LINE1_L
2
5V_S5 5V_PVDD
R586
L3016
1KR2J-1-GP
1 2 (A) 5V_PVDD
MIC_VREFL (A)
,-.,.--/012341#56178*4
1
)*./*&0#$1 !"#$%"&%!! 9:8;#'<5.#=%:#(4*#=%>?%#@(:=)3%:# MHC1608S181NBP-GP
2
PD#
'()*(+,-./+0(11(2+345-
2
R23 C399 (A) (A)
2K2R2J-2-GP SC10U25V5KX-GP C437 C400
-,*. L2 (63.00000.00L) (A) SCD1U16V2KX-3GP
#$6"N%!7+QC=+.9-:;<+?(+'<:?@-1+G+&6L)) U3002
1
MIC_IN_JACK 1 2 SC1U10V2KX-1GP
1
FM_L_CODEC C9663 1 2 FCM1608KFG-301T05-GP
R21 3D3V_S5
SC2D2U10V3KX-1GP L3011 13 14
26 SPKR_L+ VDD HP_LOUT
FM_R_CODEC C9664 1 2 MIC1 1 2MIC1* 1 2 MIC_IN_JACK C13 16 2
26 SPKR_L- VDD HP_ROUT
1
SC2D2U10V3KX-1GP FCM1608KFG-301T05-GP SC100P50V2JN-3GP 20
AUDR1 VDD 17
(68.00335.091) !"#!###!$%&'(%$)#*$+,%-./( (78.10224.2FL) SPKR_OUT_L+
26 SPKR_R- 1KR2J-1-GP LOUT+
2
15 SPKR_OUT_L-
26 SPKR_R+ $$
2
LOUT-
1
NP2 R3076 SCD1U16V2KX-3GP AGC 11
R20 NP1 10KR2J-3-GP 5V_PVDD AMP_R C386 (A) 1 2 PORTC_SPK_R_C AGC 19 SPKR_OUT_R+
22KR2J-GP COMBO AGND 3D3V_S5 AMP_L C388 (A) 1 2 PORTC_SPK_L_C PD# 3 ROUT+ 1 SPKR_OUT_R-
7 SCD1U16V2KX-3GP 5 SD# ROUT-
1
RIN
1
R28 JD_LOT L3 9 JD_LOT_2 (A) 7
2
F_HPO_R 1 2 F_HPO_R* 1 2 (63.00000.00L) 8 R626 A2603A_VOL_CONTROL 8 LIN 6
VOLUME AGND AGND
2
75R2J-1-GP FCM1608KFG-301T05-GP F_HPO_R_C 3 3K4R2F-GP AMP_MUTE 9
R3075 UVP 12 MUTE 18
!/01 AGND R29 L4 10KR2J-3-GP Q3013 AGND UVP PGND
2
6
1
F_HPO_L 1 2 F_HPO_L* 1 2 (63.00000.00L) F_HPO_L_C 2 A2603A_VOL_CONTROL (A) A2603A_BYPASS 4 21
75R2J-1-GP FCM1608KFG-301T05-GP 1
!"#$%&'()*+,! C387 BTL* 10 BYPASS GND
1
SE/BTL#
1
-%./()0*+12
24 HP_MUTE
FE&GF
1
JD_LOT 2N7002KDW-GP R618 SC1U10V2KX-1GP (A) (A)
R22
1
(75.27002.F7C) 2KR2F-3-GP C385 R84 APA2603AQAI-TRG-GP-U
3
PHONE-JK516-GP
1
COMBO JACK 1 2 COMBO C14 (78.10224.2FL) C9661 (78.10224.2FL) (A) SC1U10V2KX-1GP 100KR2J-1-GP (A)
SC100P50V2JN-3GP SC100P50V2JN-3GP (22.10270.Y61)
24,26 SIO_AUDIO_MUTE
2
C C
2
22KR2J-GP
1
JD_LOT_R
17,26 HDA_CODEC_RST#
C9662 AGND (A)
SC10U6D3V5KX-1GP AMP_MUTE# R504 1 2 AMP_MUTE
2
0R2J-2-GP !"#$%&'()*
(R)
+"#'()*
1
AMP_MUTE#_R R500 1 2
)!, AGND 0R2J-2-GP (A)
AGND R617
26 SPEAKER1_L1 100KR2J-1-GP
26 SPEAKER1_R1
2
2! (R)
<(>?2@(94+&A,%#"",+B21
C39 1 2 SC47U6D3V5MX-1-GP
3D3V_S5
L3007 R3054
SPKR_OUT_L+ 1 2
LINE1_L TC1 1 2 ST100U6D3VBM-15GP LINE1_L_C R3041 1 2 75R2J-1-GP LINE1_L_N 1 2 HP_OUT_L_CON HP_OUT_L_CON 34 (R) 0R5J-5-GP
(77.C1071.081) MHC1608S601LBP-GP L9510 (N68.00335.091)
D/23)'E)F,003=.,+
2
SPKR_L+ 1 2 SPKR_OUT_L+_C
1
R3071 C3075 MCB1608S301HBP-GP C3049
LINE1_R TC2 1 2 ST100U6D3VBM-15GP LINE1_R_C R3042 1 2 75R2J-1-GP LINE1_R_N 1 2 HP_OUT_R_CON HP_OUT_R_CON 34
10KR2J-3-GP SC4700P50V3J-1-GP SC4700P50V3J-1-GP SPK1
(77.C1071.081) L3008 JD_HP 3D3V_S5 (78.33124.2BL) (78.33124.2BL)
JD_HP 34 R3055
5
SPKR_OUT_L- 1 2
1
C40 1 2 SC47U6D3V5MX-1-GP MHC1608S601LBP-GP JD_HP_2 (R)
L9511 0R5J-5-GP (N68.00335.091) 1
2
(R) SPKR_L- 1 2 SPKR_OUT_L-_C
2
1
R3072 C3076 MCB1608S301HBP-GP C3073 2
R115 R116 C3037 C3041 10KR2J-3-GP Q3012 AGND SC4700P50V3J-1-GP R3056 SC4700P50V3J-1-GP 3
4
22KR2J-GP 22KR2J-GP (78.33124.2BL) SPKR_OUT_R+ 1 2 (78.33124.2BL) 4
2
(R) (R) SC100P50V2JN-3GP SC100P50V2JN-3GP 2N7002KDW-GP (R)
1
(75.27002.F7C) L9512 0R5J-5-GP (N68.00335.091)
1
2
JD_HP SPKR_R+ 1 2 SPKR_OUT_R+_C
6
1
1
C3077 MCB1608S301HBP-GP C3050 ACES-CON4-35-GP-U
#$6"K%"L+8(554+-FF+#""I+'-M !"#$%"&%!7
3
SC4700P50V3J-1-GP SC4700P50V3J-1-GP
#$6"K%"L+8(554+8<5<@P<F+!N(9) 508/(3+)9::0)4+#""; (78.33124.2BL) R3057 (78.33124.2BL)
2
#$6"K%"N+'9-:;<+?(+"N"L+&KI+'-M SPKR_OUT_R- 1 2
#$6"N%"!+8(554+.9-:;<+-0?<@+KL(9) (R)
0R5J-5-GP
(20.F1819.004)
#$6"K%"O+'9-:;<+?(+#""I+'-M AGND AGND
JD_HP_R
SPKR_R-
L9513
1 2
(N68.00335.091)
SPKR_OUT_R-_C
1
AGND C3078 MCB1608S301HBP-GP C3074
SC4700P50V3J-1-GP SC4700P50V3J-1-GP
(78.33124.2BL) (78.33124.2BL)
2
B B
%+2.*34,5+42 6"5"0)3 )2)345 3D3V_S5 5V_S5

#$6"N%"!+8(554+.9-:;<+:<?+-0?<@+#""I Control by software driver and CODEC GPIO.
+2#%() GPIO driving low at:
2
POP Circuit R3047 R3073 1).Initial state
1KR2J-1-GP 1KR2J-1-GP Q3024
2).Suspend to S1
Control by software driver and CODEC GPIO. (R) (R) 3).Resume from S1.
LINE1_R_C 6 1 SHDN_MUTE_AP_CTL
GPIO driving low at: C1 E1 AGND
1
3D3V_S0 R9953 R3069
1).Initial state MUTE 2 1 MUTE_1 1 2 LINE1_L_2* 5 B2 B1 2
1
2).Suspend to S1 1KR2J-1-GP
2
3).Resume from S1. R3050 !"#)*+$%&' 0R3J-0-U-GP 4 3 LINE1_L_C R9555

AGND C2
10KR2J-3-GP
R3049 MUTE_RR 1 2 MUTE_R 1 Q3025 PMBS3906-GP (R) E2
10KR2J-3-GP 10KR2J-3-GP
("#$%&' R3068 SHDN_MUTE_AP_CTL
SCD1U16V2ZY-2GP
(84.T3906.E11) 1 2 LINE1_R_2* HBN2444S6R-GP

Michael 2011/12/28
2
2
2
Q3021 C3044
R3051 When the PC mode and Monitor
1
SC22U6D3V5MX-2GP
3.3_POP 1 1KR2J-1-GP
PMBS3906-GP
C3045
1 2 mode are being switched Pull down to 10 for depop when AC ON
2
(84.T3906.E11) 220KR2J-L2-GP
3
(78.47593.41L) C3046 (63.10434.1DL) MUTE_AP_CTL should be low

2
R3035 Q3016 Q3017 1 2

HDA_CODEC_RST# 1 2 AZRST 1 1
5%>?% in order to avoid the
Q3023
PMBS3906-GP PMBS3906-GP SCD1U16V2ZY-2GP noise
1KR2J-1-GP (84.T3906.E11) (R) 3D3V_S5 F_HPO_R 6 C1 E1 1 AGND
3
!"#$%&' R59 R3052

2 1 MUTE_2 1 2 LINE2_L_2* 5 B2 B1 2 MUTE_AP_CTL also control when
("#)*+$%&' 1KR2J-1-GP
0R3J-0-U-GP 4 3 F_HPO_L select MUTE in the PC mode or
AGND C2
(R) E2 Monitor mode
(R)
SIO_AUDIO_MUTE 1 2 SIO_AUDIO_MUTE_R R3053 HBN2444S6R-GP
R3048 1KR2J-1-GP 1 2 LINE2_R_2*
#$6"7%"7+8(554+'9-:;<+=>?<+'4@.>4? MUTE_AP_CTL also control when
1KR2J-1-GP
Control line Control circuit system wake from S3 to S0 C3013 2 1 SCD1U16V2ZY-2GP (R) C3005 2 1 SCD1U16V2ZY-2GP (R)
3D3V_S5 C3004 1 2 0R0402-PAD C3006 2 1 SCD1U16V2ZY-2GP (R)
C3017 2 1 SC2200P50V2KX-2GP (R) R3058 1 2 0R0402-PAD

2
R3034
A'2 5V_S5
A A
1KR2J-1-GP
AGND AGND
2
1
R3033
HP_MUTE_R 100KR2J-1-GP !"#$%&'
(A) ("#)*+$%&'
1
Q3009 R3036 1 2 0R0402-PAD

6
AGND AMP_MUTE#_R
R3063 1 2 0R0402-PAD
2N7002KDW-GP 5V_S5
#$6"7%#"+=>?<+ABC+'D8E (75.27002.F7C)
Q3011 #$6"7%##+8(554+-FF+3%G+0(@+H=3+=IDJ <Core Design>
1
AGND AGND
2
2N7002KDW-GP R93
(A75.27002.F7C) 10KR2J-3-GP Wistron Corporation
!"#)*+$%&' (A) 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1
1
HP_MUTE ("#$%&'
R9954 Title
2 1 SHDN_MUTE_AP_CTL AMP_MUTE#
!"#)*+$%&' 3D3V_S5 Audio AMP
0R3J-0-U-GP Size Document Number Rev
("#$%&' (R) Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
!"#!$"%$#& LCD ON/OFF

Michael 2011/12/02
CONRTOL '())*+,--+../+0(11203(4+3(+50,6,4 Need check the Panel power later
#?C"D$#@+E,.0#$+E,.0?+);,F
SCABD1
31 3D3V_S5
1 EDP_HPD_N
24 BLON_EN#
2
DDSP_D_TX_DATA0_S 2
3 DDSP_D_TX_DATA0#_S R9545
4 10KR2J-3-GP
D D
5 DDSP_D_TX_DATA1_S
DDSP_D_TX_DATA1#_S 6
1
7
DDSP_D_TX_DATA2_S 8
9 DDSP_D_TX_DATA2#_S LCDVDD_EN1
SCALAR_VDD_EN 24
eDP 10
11 DDSP_D_TX_DATA3_S
DDSP_D_TX_DATA3#_S 12 Pin55
13
SIO_UART1_RX 14
15 SIO_UART1_TX
12 DDSP_D_TX_DATA0 PM_SLP_S3# 16
12 DDSP_D_TX_DATA0# 17 EDID_RDY
EDP_AUX_P_C 18
12 DDSP_D_TX_DATA1 19 EDP_AUX_N_C
12 DDSP_D_TX_DATA1# 20
SCALAR_SENSE_B
21 SCALAR_OUT_L
Michael 2012/3/15 1A
SCALAR_OUT_R 22
23
24
VCC5_PANEL for leakage
12 DDSP_D_TX_DATA2 VCC5_PANEL
25
12 DDSP_D_TX_DATA2# 26
3D3V_S5
27 BLON_EN#
12 DDSP_D_TX_DATA3 LCDVDD_EN1 28
12 DDSP_D_TX_DATA3# 29 DET_HDMI
ISO_DET 30
DPD_HPD
19,29 EDP_AUX_N
32
19,29 EDP_AUX_P
ACES-CONN30D-5-GP 5V_S0
19,29 EDP_HPD_N
4
(S)
Q9504
1
2N7002KDW-GP
(75.27002.F7C) R9558
10KR2J-3-GP
3
FW
2
C C
DPD_HPD_R
15,16,17,23,29,38,39,41 SMB_CLK
!"# *08619,&+,:: R9556
PANEL_ON3 1 2 PANEL_BTN_EVENT# 5V_S0_PU_SCALAR
PANEL_ON1 0R0402-PAD
15,16,17,23,29,38,39,41 SMB_DATA
DDSP_D_TX_DATA0 C9529 1(S) 2 SCD1U10V2KX-5GP DDSP_D_TX_DATA0_S
19 SMBUS_ISP DDSP_D_TX_DATA0# C9534 1(S) 2 SCD1U10V2KX-5GP DDSP_D_TX_DATA0#_S
R9552
24 ISO_DET DDSP_D_TX_DATA1 C9532 1(S) 2 SCD1U10V2KX-5GP DDSP_D_TX_DATA1_S SIO_PANEL_ON 1 2
3
DDSP_D_TX_DATA1# C9530 1(S) 2 SCD1U10V2KX-5GP DDSP_D_TX_DATA1#_S
OSD DDSP_D_TX_DATA2 C9531 1(S) 2 SCD1U10V2KX-5GP DDSP_D_TX_DATA2_S

10KR2J-3-GP
2N7002KDW-GP
DDSP_D_TX_DATA2# C9528 1(S) 2 SCD1U10V2KX-5GP DDSP_D_TX_DATA2#_S Q9503
(75.27002.F7C)
4
DDSP_D_TX_DATA3 C9533 1(S) 2 SCD1U10V2KX-5GP DDSP_D_TX_DATA3_S 3D3V_S0
DDSP_D_TX_DATA3# C9527 1(S) 2 SCD1U10V2KX-5GP DDSP_D_TX_DATA3#_S
R9543
1 2 PANEL_ON2
24 SIO_UART1_RX 3D3V_S5
24 SIO_UART1_TX
10KR2J-3-GP
26 SCALAR_SENSE_B
3%4*(1&)56758)59:6&;<&=%(;<>&?$#"#(&<@'$A;*'
R9528 2 1 4K7R2J-2-GP BLON_EN#
!"#?$"@$#% R9517 2 1 4K7R2J-2-GP SHDN_MUTE_AP_CTL

(R)
A020/0+10-7.-,./+5$B
(S)
EDP_AUX_N C9643 1 2 SCD1U10V2KX-5GP EDP_AUX_N_C
EDP_AUX_P C9645 1 2 SCD1U10V2KX-5GP EDP_AUX_P_C
(S)
B B
Panel On Off CTRL
17 PANEL_BTN_EVENT#
24 SIO_PANEL_ON
+,-./0-1&234051&67&!89:!
,45627
17,24,46,47,51,54,55 PM_SLP_S3# SMBUS_ISP SMBUS_ISP
ISP_CLK1 SMB_DATA ISP_CLK1 PCH_DVI_DATA
6
4
3D3V_S5 3D3V_S5
Q9501 Q9502
17 EDID_RDY 2N7002KDW-GP 2N7002KDW-GP
1
#$8"9%#:+'())*+;<=+6-./01+>(?+)6.@.? (S75.27002.F7C) (S75.27002.F7C)

1
R9532
1
3
10KR2J-3-GP R9533
24 DET_HDMI (R) 10KR2J-3-GP (R)
SMB_CLK ISP_DAT1 PCH_DVI_CLK ISP_DAT1
2
(S) SMBUS_ISP SMBUS_ISP

2
A SIO_UART1_RX 47R2J-2-GP 2 1 R9534 PCH_DVI_CLK A

26 SCALAR_OUT_R
26 SCALAR_OUT_L (S)
SIO_UART1_TX 47R2J-2-GP 2 1 R9535 PCH_DVI_DATA
3D3V_S0 3D3V_S0 3D3V_S0
<Core Design>
(S)
1
R9560
1
R9557 R9541
SMBUS_ISP H !
!Simutaneous Mode SMBUS_ISP 1 2 (R) 10KR2J-3-GP R9540 4K7R2J-2-GP Wistron Corporation
4K7R2J-2-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SMBUS_ISP L !
!Isolate Mode Taipei Hsien 221, Taiwan, R.O.C.
2
10KR2J-3-GP
2
SMBUS_ISP ISP_CLK1 ISP_DAT1 Title
Scalar Port
Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
eDP to dual channel LVDS 3D3V_S0 3D3V_S5

EDP 01234500$6"7"%("#$89:$;'<"%
1
19,28 EDP_AUX_N
2012/11/07 R65 R69
6")7'=>$?)@"$A%'&$.1$;)="B$CB)D@$7D%""=$)+$E/FF/.
19,28 EDP_AUX_P
0R3J-0-U-GP 0R3J-0-U-GP
Change from PS8625 to RTD2136R Kenyon (R) (U)
L50 AVCC
Copy from ROSA PBAIO
2
MHC1608S600QBP-GP P_3.3V_EDP_VDDIO
(U63.00000.00L)
12
12
DDSP_D_TX_DATA1_N
DDSP_D_TX_DATA1#_N RTK RTD2136R/71.02136.B03 3D3V_EDP_PWR 1 2
1
C643 C607 C418
1
SC10U6D3V3MX-GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP
30 RTD2136_BKLT_PWM
24,30 RTD2136_LCD_VDD_EN C417 (U78.47520.5BL) (U78.10491.4FL) (U78.10491.4FL)
2
SCD1U16V2ZY-2GP
19,30 EDP_BKLTCTL
2
RTD2136_INI_SDA_R
(U)
RTD2136_INI_SCL_R
30 EDP_LVDS_L0_N
RTD2136_BKLT_EN
30 EDP_LVDS_L0_P Closed to
EDP_LVDS_L0_N
EDP_LVDS_L1_N
EDP_LVDS_L2_N
EDP_LVDS_L0_P
EDP_LVDS_L1_P
EDP_LVDS_L2_P
D D
30 EDP_LVDS_L1_N RTD2136 DVCC
MODE_CFG1
MODE_CFG0
30 EDP_LVDS_L1_P
P_1.2V_EDP
L51 pin 5
30 EDP_LVDS_L2_N
30 EDP_LVDS_L2_P
!;'::B&C5B&7D&(%?%(=%+&EFB&!G,B&6HIHJJ&A*&)HK3 MHC1608S600QBP-GP P_3.3V_EDP_VDDIOX
30 EDP_LVDS_L3_N (U63.00000.00L)
30 EDP_LVDS_L3_P 1 2
30 EDP_LVDS_LC_N
1
30 EDP_LVDS_LC_P C424 C425 C423 C421 C419
30 EDP_LVDS_U0_N SC10U6D3V3MX-GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP C420
(U) (U78.47520.5BL) (U78.10491.4FL) (U78.10491.4FL) (U78.10491.4FL) (U78.10491.4FL) SC22U6D3V3MX-1-GP
49
48
47
46
45
44
43
42
41
40
39
38
37
30 EDP_LVDS_U0_P
2
30 EDP_LVDS_U1_N U27 (U78.10610.5BL)
MODE_CFG1
MODE_CFG0
MIICSCL
MIICSDA
VCCK
TXO0-
TXO1-
TXO2-
TXO0+
TXO1+
TXO2+
GND
BL_EN
30 EDP_LVDS_U1_P
30 EDP_LVDS_U2_N Closed to Closed to
30 EDP_LVDS_U2_P RTD2136 RTD2136
30 EDP_LVDS_U3_N
!"#$%&'()*+
0123G501$6'77,$H014$D'7+$#'<=K$LMN$DO)=J"$+'$PQR$)=#$7O'%+$;)# pin 22 pin 18
30 EDP_LVDS_U3_P
30 EDP_LVDS_UC_N (U)
30 EDP_LVDS_UC_P RTD2136_HPD R51 2 1 1KR2J-1-GP RTD2136_HPD_N 1 36 EDP_LVDS_LC_N
R898 2 1 100KR2J-1-GP TEST_MODE 2 HPD TXOC- 35 EDP_LVDS_LC_P
24,30 RTD2136_BKLT_EN TEST TXOC+ P_1.2V_EDP
(U) DP0_AUXN_RTD2136 3 34 EDP_LVDS_L3_N
DP0_AUXP_RTD2136 4 AUX_N TXO3- 33 EDP_LVDS_L3_P
5 AUX_P TXO3+ 32 EDP_LVDS_U0_N
P_3.3V_EDP_VDDIO DP_V33 TXE0-
6 31 EDP_LVDS_U0_P
DP_GND TXE0+
1
DDSP_D_TX_DATA0_N 7 30 EDP_LVDS_U1_N C427 C428 C429 C430
DDSP_D_TX_DATA0#_N 8 LANE0_P TXE1- 29 EDP_LVDS_U1_P SCD1U16V2KX-3GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP
SC10U6D3V3MX-GP
DDSP_D_TX_DATA1_N 9 LANE0_N TXE1+ 28 EDP_LVDS_U2_N (U78.47520.5BL) (U78.10491.4FL) (U) (U)
2
DDSP_D_TX_DATA1#_N 10 LANE1_P TXE2- 27 EDP_LVDS_U2_P
11 LANE1_N TXE2+ 26
GPIO P_1.2V_EDP
DP_REXT 12 DP_V12 TXEC- 25
EDP_LVDS_UC_N
EDP_LVDS_UC_P Closed to Closed to Closed to Closed to
DP_REXT TXEC+
19,28 EDP_HPD_N RTD2136 RTD2136 RTD2136 RTD2136
PANEL_VCC
SWR_VCCK
SWR_GND
PWM_OUT
pin 15 pin 11 pin 15 pin 43
SWR_VDD
CIICSDA
SWR_LX
PWM_IN
CIICSCL
R1092 (U)
TXE3+
TXE3-
PVCC
12KR2F-L-GP
2
RTD2136R-CGT-GP
13
14
15
16
17
P_3.3V_EDP_VDDIOX 18
RTD2136_BKLT_PWM 19
RTD2136_LCD_VDD_EN 20
21
P_3.3V_EDP_VDDIOX 22
23
24
RTD2136_ROM2_DAT
RTD2136_ROM2_CLK
2012/10/14 David =+&(18&#>6&1?=@
EDP_LVDS_U3_N
EDP_LVDS_U3_P
DP_VARY_BL_R
Follow design guide
C C
RTD2136_SW
(U78.10421.2FL)
EDP_AUX_N C450 1 2 SCD1U10V2MX-3GP DP0_AUXN_RTD2136 (U)
EDP_AUX_P C426 1 2 SCD1U10V2MX-3GP DP0_AUXP_RTD2136 EDP_BKLTCTL R636 1 2 0R2J-2-GP DP_VARY_BL_R
(U78.10421.2FL)
,-.#/0'1"#$%'!23456!2347
2
L93
COIL-4D7UH-21-GP R144
(R68.4R71G.10M) 0R0603-PAD-1-GP-U
(U)
1
P_1.2V_EDP
P_3.3V_EDP_VDDIO 2012/10/14 David

RTD2136_INI_SDA_R R899 1 2 4K7R2J-2-GP
reserved slave address 0x94 & 0x6A
1
R649 R657
4K7R2J-2-GP 4K7R2J-2-GP
P_3.3V_EDP_VDDIO
From PCH
2
MODE_CFG0 R642 1 (U) 2 4K7R2J-2-GP R653 1 (R) 2 0R2J-2-GP
SMB_CLK 15,16,17,23,28,38,39,41
R654 1 (R) 2 0R2J-2-GP
SMB_DATA 15,16,17,23,28,38,39,41
R643 1 (R) 2 4K7R2J-2-GP
From EC
RTD2136_ROM2_CLK R656 1 (U) 2 0R2J-2-GP SIO_SMCLK0_R
RTD2136_ROM2_DAT R655 1 (U) 2 0R2J-2-GP SIO_SMDAT0_R
B B
*;<7&=;1&(05>&0<<=/
2012/10/24 David
P_3.3V_EDP_VDDIO P_3.3V_EDP_VDDIO
Reserve the EEPROM (72.24C64.E01) for SA usage.
Once the panel is work normally, can remove EEPROM, and transfer the initial job to EC
MODE_CFG1 R645 1 (R) 2 4K7R2J-2-GP
P_3.3V_EDP_VDDIO
1
R646 1 (U) 2 4K7R2J-2-GP

R659 R658
4K7R2J-2-GP 4K7R2J-2-GP
(U) (R) U42
2
8 1
7 VCC E0 2
RTD2136_INI_SCL_R R871 1 (R) 2 0R2J-2-GP RTD2136_INI_SCL 6 WC# E1 3
RTD2136_INI_SDA_R R872 1 (R) 2 0R2J-2-GP RTD2136_INI_SDA 5 SCL E2 4
5V_S0 SDA VSS
RTD2136_BKLT_PWM 1 R641 2 0123G53H$)##$I:E$B")@)J"
100KR2J-L-GP M24C64-WMN6TP-1GP
2
(R63.10434.1DL) (U72.24C64.R01)
R134
2K2R2J-2-GP
(U)
RTD2136_LCD_VDD_EN 1 R644 2
1
100KR2J-L-GP RTD2136_HPD_C
5V_S0
(63.10434.1DL) FDI,IFAM 12B:C;:D&E#$$6&=))&?3FG?&"%=H=>%
9M,70NO47112@ !89:!&$10?0@1
G
(R) C642
1 2 IM,O47112@ R131
RTD2136_HPD D S EDP_HPD_N 2K2R2J-2-GP
SC4D7U6D3V2MX-GP-U (U)
1
SMBUS_PU
Q54
DP_VARY_BL_R 1 R647 2 2N7002-7F-GP
100KR2J-L-GP (U84.2N702.J31)
(R63.10434.1DL) SIO_SMDAT0 6 1 SIO_SMDAT0_R
24 SIO_SMDAT0
1
5 2
A A
High active R639 Q11
K(#'?.;AA%(
RTD2136_BKLT_EN 1 R648 2 100KR2J-L-GP 2N7002KDW-GP 4 3
100KR2J-L-GP (R63.10434.1DL) !""#$%"&'("$)*+"%$("%,*-$)+$./ (U75.27002.F7C)
(R63.10434.1DL)
2
SIO_SMCLK0_R
<Core Design>
24 SIO_SMCLK0 SIO_SMCLK0
Wistron Corporation
Title
eDP to LVDS
Custom
vSuperb -1
5 4 3 2 1
!"#$%&'(%)#* !"#$%"&%!$
2"3%456 !"#$%"&%!& '())*+',-./0,+12),+34+5(.4)6*708
!"#$%&'()*+, (R)
',),9:,;+<=+>9(?+5@A
-'./$%01)*+, R24
29 EDP_LVDS_LC_N
29 EDP_LVDS_LC_P
EDP_BKLTEN 1
22R2J-2-GP
2
+19V_S5_INV Power
29 EDP_LVDS_L0_N
29
29
EDP_LVDS_L0_P
EDP_LVDS_L1_N
!"#$%&' (R)
R62
68.00216.191
Z=80 ohm,Rdc=0.02 ohm
22R2J-2-GP DCBATOUT LVDS1
29 EDP_LVDS_L1_P
RTD2136_BKLT_EN 1 2 3D3V_S5 I=5A ,0805 1A 1B EDP_LVDS_L0_N
29 EDP_LVDS_L2_N
29 EDP_LVDS_L2_P !"#$%"D%"E F4
1 2 DCBATOUT_CON 2A 2B EDP_LVDS_L0_P
29 EDP_LVDS_L3_N ',),9:,;+<=+>9(?+'FG!#$H
1
3A 3B EDP_LVDS_L1_N
29 EDP_LVDS_L3_P 4A 4B
R4906 POLYSW-1D5A24V-GP EDP_LVDS_L1_P
1
20KR2J-L2-GP F3 C280 C281 5A 5B EDP_LVDS_L2_N
1 2 (R) 6A 6B EDP_LVDS_L2_P
29 EDP_LVDS_UC_N
SC1U10V2KX-1GP
SCD1U16V2ZY-2GP
7A 7B
29 EDP_LVDS_UC_P
2
3D3V_S5 POLYSW-1D5A24V-GP 8A 8B EDP_LVDS_LC_N
29 EDP_LVDS_U0_N 9A 9B
BKLT_EN (R) EDP_LVDS_LC_P
29 EDP_LVDS_U0_P
10A 10B EDP_LVDS_L3_N
29 EDP_LVDS_U1_N 11A 11B EDP_LVDS_L3_P
29 EDP_LVDS_U1_P
1
12A 12B EDP_LVDS_U0_N
29 EDP_LVDS_U2_N DCBATOUT_CON
R4915 13A 13B EDP_LVDS_U0_P
29 EDP_LVDS_U2_P
1
!"#!$#"$"% 20KR2J-L2-GP Q4905 C4909 14A 14B
29 EDP_LVDS_U3_N
D
2N7002A-7-GP (84.2N702.J31) (R) 15A 15B EDP_LVDS_U1_N
29 EDP_LVDS_U3_P &'()*+,-.,/012,345 SC100P50V2JN-3GP 16A 16B EDP_LVDS_U1_P
2
17A 17B
SIO_BL_EN R615 2 1 BLON_EN G 18A 18B EDP_LVDS_U2_N
22R2J-2-GP CONV1 19A 19B EDP_LVDS_U2_P
2"3%789 9 20A 20B EDP_LVDS_UC_N
BKLT_EN 1 21A 21B EDP_LVDS_UC_P
S
!"#$%01)*+, 22A 22B EDP_LVDS_U3_N
BKLT_ADJ 2 23A 23B EDP_LVDS_U3_P
-'./$%&'()*+, 3 24A 24B
4 25A 25B
5 26A 26B
6 27A 27B
3D3V_S5 7 28A 28B
VCC5_PANEL
8 29A 29B
10 30A 30B
2
(R)
1
R4904 C4911 C4910
ACES-CON8-8-GP-U
1KR2J-1-GP ACES-CONN60G-GP-U (R)
SC1U10V2KX-1GP
SCD1U16V2ZY-2GP
(U)
()*
2
R4903 (20.F1819.008)
1
SIO_BKLT_CTRL 2 1 100R2J-2-GP
+,!-%.'/0('1
(R)
R25
EDP_BKLTCTL 2 1 100R2J-2-GP
24 SIO_BL_EN
19 EDP_BKLTEN !"#$%"&%!&
(R)
24,29 RTD2136_BKLT_EN ',),9:,;+5BC+>9(?+5@A R63
RTD2136_BKLT_PWM 2 1 100R2J-2-GP
24 SIO_BKLT_CTRL !"#$%"D%"E
19,29 EDP_BKLTCTL ',),9:,;+5BC+>9(?+'FG!#$H
29 RTD2136_BKLT_PWM
!"#!$#"$##
19 EDP_VDDEN
24 SIO_VDD_EN
!"# 6+7+08+9,-:4,71;<=>1)
24,29 RTD2136_LCD_VDD_EN
EDP_LVDS_L0_N EDP_LVDS_L0_P
C9607 1 2
SC10P50V2JN-4GP C9617 1 2
SC10P50V2JN-4GP
(R) (R)
C9608 1 2
SC10P50V2JN-4GP C9618 1 2
SC10P50V2JN-4GP
(R) (R)
C9609 1 2
SC10P50V2JN-4GP C9619 1 2
SC10P50V2JN-4GP
5V_A VCC5_PANEL (R) (R)
!"#$%&'()*+, EDP_LVDS_LC_N EDP_LVDS_LC_P
-'./$%01)*+,
U4902 C9610 1 2
SC10P50V2JN-4GP C9620 1 2
SC10P50V2JN-4GP
1 D D 6 (R) (R)
L4901
+,,%&' 2 D D 5 EDP_LVDS_L3_N EDP_LVDS_L3_P
1
3 G S 4 V_5_LCD1 1 2 V_5_LCD2
C4907 C9611 1 2
SC10P50V2JN-4GP C9621 1 2
SC10P50V2JN-4GP
DCBATOUT SC1U10V2KX-1GP AO6402A-GP MHC1608S800QBP-GP (R) (R)
1
Q6107 Main: 84.06402.B3D EDP_LVDS_U0_N EDP_LVDS_U0_P
PMBS3906-GP Alt: 84.00655.B3D R4912
1 2 LCD_5V_EN1 2 3 (84.T3906.E11) LCD_5V_EN 510R2J-1-GP C9612 1 2
SC10P50V2JN-4GP C9622 1 2
SC10P50V2JN-4GP
R4901 47KR2J-2-GP High: Enable (R) (R)
1
EDP_LVDS_U1_N EDP_LVDS_U1_P
Low: Disable
2
2
R4910 R4911 C4912
5V_S5_LCD_DOWN
1
1 2 LCD_5V_EN2 47KR2J-2-GP 1KR2J-1-GP SCD1U50V3KX-GP C9613 1 2

SC10P50V2JN-4GP C9623 1 2
SC10P50V2JN-4GP
R4902 330KR2J-L1-GP (R) (R)
!"#!$#!$!%
1
EDP_LVDS_U2_N EDP_LVDS_U2_P
2
#&'())'#*'+,-')./-(0123
1
C9614 1 2
SC10P50V2JN-4GP C9624 1 2
SC10P50V2JN-4GP
R4909 (R) (R)
LCD_5V_EN4
100KR2J-1-GP 4#"',56'+,-'7869 Q4906 EDP_LVDS_UC_N EDP_LVDS_UC_P
D
2N7002A-7-GP
C9615 1 2
SC10P50V2JN-4GP C9625 1 2
SC10P50V2JN-4GP
2
(R) (R)
LCD_5V_EN3 G EDP_LVDS_U3_N EDP_LVDS_U3_P
(84.2N702.J31) C9616 1 2
SC10P50V2JN-4GP C9626 1 2
SC10P50V2JN-4GP
(R) (R)
S
1
R4914 R4907 R573
6
SIO_VDD_EN 1 2 VDD_EN_C 1 2SCALAR_VDD_EN1 1MR2J-1-GP

Q4901
4K7R2J-2-GP 4K7R2J-2-GP 2N7002KDW-GP
(75.27002.F7C) 2
1
R26
EDP_VDDEN 1 2
!"#?$"@$!?
4K7R2J-2-GP
6+7+08+9,A&B,CDD-.,E1)=01;
(R)
R64
RTD2136_LCD_VDD_EN1 2
4K7R2J-2-GP
!"#?$"F$"% (R)
6+7+08+9,FCGCDD,/012,6HD!#?I
2
R4908
10KR2J-3-GP
1
<Core Design>
Wistron Corporation
Title
LCD Port
C
vSuperb -1
5 4 3 2 1
!"#
D 3D3V_S0 D
&'(
19 VGA_RED
D3
19 VGA_GREEN
19 VGA_BLUE L9
VGA_DDC_PU K A
5V_S0
VGA_BLUE 1 2 BLUE_CRT
1
BLM15BA750SN1D-GP 1N4148WS-7-F-GP
!"#$ R261 R260 (83.00355.F1F)
2K2R2J-2-GP 2K2R2J-2-GP L11
19 VGA_HSYNC_3V
VGA_GREEN 1 2 GREEN_CRT
19 VGA_VSYNC_3V
1
BLM15BA750SN1D-GP
2
R263 R262
3D3V_S0 2K2R2J-2-GP 2K2R2J-2-GP
%%$ L13
VGA_RED 1 2 RED_CRT
19 VGA_PCH_DDCSDA
2
BLM15BA750SN1D-GP
19 VGA_PCH_DDCSCL
G
3D3V_S0
R321
VGA_PCH_DDCSDA S D 5VDDCDA_R 1 2 5VDDCDA
%)*)+*
Q43 33R2J-2-GP
19 VGA_DET
2N7002-11-GP
G
(84.2N702.J31)
R322
VGA_PCH_DDCSCL S D 5VDDCCL_R 1 2 5VDDCCL
Q58 33R2J-2-GP
2N7002-11-GP
(84.2N702.J31)
L10
BUF_HSYNC_A 1 2 HSYNC_3P3V
0R0603-PAD-1-GP-U
C C
L12
BUF_VSYNC_A 1 2 VSYNC_3P3V
0R0603-PAD-1-GP-U
2
C318 C321 C324 C331 C333 C325 C326
1
R316 R317 R318 C317 C320 C323 SC3D3P50V3N-GP SC3D3P50V3N-GP SC3D3P50V3N-GP SC100P50V2JN-3GP SC100P50V2JN-3GP SC10P50V2JN-4GP SC10P50V2JN-4GP
150R2F-1-GP 150R2F-1-GP 150R2F-1-GP SC3D3P50V3N-GP SC3D3P50V3N-GP SC3D3P50V3N-GP (78.33034.1BL) (78.33034.1BL) (78.33034.1BL)
(78.3R374.1BL) (78.3R374.1BL) (78.3R374.1BL)
2
1
33R2J-2-GP 1 2 R319 1
3D3V_S0
VGA_HSYNC_3V
C327
!"#
1
SCD1U16V2ZY-2GP
!"#$%&!'()*++,(-./.0.().+.12.-(345 5V_S0 5V_S0
2
B U6 BAV99-13-GP BAV99-13-GP B
VGA_VSYNC_3V RED_CRT 5 4 HSYNC_3P3V
CH_4 CH_3 2 2
GREEN_CRT 6 3
CH_5 VN 5VDDCDA 3 5VDDCCL 3
7 2
33R2J-2-GP 1 2 R320 VP CH_2 (R) 1 (R) 1
BLUE_CRT 8 1 VSYNC_3P3V
CH_6 CH_1
PACDN006MR-1-GP D12 D13
Edit Path on 2011.08.25
5V_S0
+5V_VGA
VGAS1
F5 L15
1 2 +5V_VGA_POLY 1 2 9 4 VGA_DET
VCC_CRT NC#4 11
0R0805-PAD-1-GP-U NC#11
POLYSW-1D5A8V-3-GP
1
C344 5VDDCDA 12
SCD1U16V2ZY-2GP 5VDDCCL 15 DDCDATA_ID1
A A
DDCCLK_ID3 5
2
RED_CRT 1 GND 6
GREEN_CRT 2 CRT_RED GND 7
BLUE_CRT 3 CRT_GREEN GND 8
CRT_BLUE GND <Core Design>
10
VSYNC_3P3V 14 GND 16
HSYNC_3P3V 13 VSYNC GND 17
HSYNC GND Wistron Corporation
D-SUB-15-183-GP Taipei Hsien 221, Taiwan, R.O.C.
!"#$$%&'()'*(++)(*,&-./0&')1,22 Title
VGA Port
C
vSuperb -1
5 4 3 2 1
5 4 3 2 1
12V_S0
12V_S0
!"#$%&#""&'(!&)%#*&+!&',))%$-,* !"#$%&$'()*++,(-..(/*0123(4,546,7
1
!" 5V_S0 R103
20KR2J-L2-GP
1
3D3V_S0
12 DDSP_B_TX_DATA0
12 DDSP_B_TX_DATA0# DDSP_B_TX_DATA0 C240 1 2 SCD1U16V2ZY-2GP DDSP_B_TX_DP_0_C
2
10KR2J-3-GP
12 DDSP_B_TX_DATA1
1
R271 2 (R) 1 100KR2J-1-GP DDSP_B_TX_DATA0# C69 1 2 SCD1U16V2ZY-2GP DDSP_B_TX_DN_0_C R102
12 DDSP_B_TX_DATA1#
1
12 DDSP_B_TX_DATA2 DDSP_B_TX_DATA1 C212 1 2 SCD1U16V2ZY-2GP DDSP_B_TX_DP_1_C R101
2
12 DDSP_B_TX_DATA2# (R)
12 DDSP_B_TX_DATA3 DDSP_B_TX_DATA1# C67 1 2 SCD1U16V2ZY-2GP DDSP_B_TX_DN_1_C 1KR2J-1-GP R99
G
12 DDSP_B_TX_DATA3# DDSP_B_TX_DATA2 C68 1 2 SCD1U16V2ZY-2GP DDSP_B_TX_DP_2_C 15KR2F-GP
2
Q7
2
DDSP_B_TX_DATA2# C65 1 2 SCD1U16V2ZY-2GP DDSP_B_TX_DN_2_C HDMI_DEVICE_DETECT 6 1
19 DP_HPD_N
DP_HPD_N S D DDSP_B_HPD_CONN DDSP_B_TX_DATA3 C66 1 2 SCD1U16V2ZY-2GP DDSP_B_TX_DP_3_C 2 DONGLE_DET_C_1
D D
19 DP_AUX_N DP_DONGLE_DET R98 1 2 DONGLE_DET_C 5
1
19 DP_AUX_P Q22 DDSP_B_TX_DATA3# C215 1 2 SCD1U16V2ZY-2GP DDSP_B_TX_DN_3_C 4 3 DP_DEVICE_DETECT
1
2N7002BK-GP 4K7R2J-2-GP
(84.2N702.J31) R270 DP_AUX_N C41 1 2 SCD1U16V2ZY-2GP DDSP_AUX_DN_C MBT3904DW1T1G-2-GP R100
19 DDPB_CTRL_DATA
1
DP_AUX_P C64 1 2 SCD1U16V2ZY-2GP DDSP_AUX_DP_C R9 C60 4K99R2F-L-GP
19 DDPB_CTRL_CLK
100KR2J-1-GP 1MR2J-1-GP SC470P50V2KX-3GP
2
(R)
2
!"#$%&'%#(&$)''%$*)(&!+'
!"#$%
/0!
U69 (R)
!"#$%&&'$(%) 3D3V_S0
23$.1&+).(45(*63
2
12 DDSP_C_TX_DATA0 DDSP_B_TX_DN_2_C 1 8 DDSP_B_TX_DN_2_C DP1 R97
12
12
DDSP_C_TX_DATA0#
DDSP_C_TX_DATA1
DDSP_B_TX_DP_2_C
DDSP_B_HPD_CONN
2
G1
3
L1#1L1#8
L2#2L2#7
GNDGND
7
G2
6
DDSP_B_TX_DP_2_C
DDSP_B_HPD_CONN
DDSP_B_TX_DP_0_C 1
2 ML_LANE0P SHELL1
X1
X2
100KR2J-1-GP
*12
12 DDSP_C_TX_DATA1#
1
DP_DONGLE_DET 4 L3#3L3#6 5 DP_DONGLE_DET DDSP_B_TX_DN_0_C 3 GND SHELL2 Q5 Q6
12 DDSP_C_TX_DATA2 L4#4L4#5 3D3V_S0 ML_LANE0N
12 DDSP_C_TX_DATA2# DDSP_B_TX_DP_1_C 4 DDSP_1_AUX_DN_C 3 4 DDSP_AUX_DN_C DDSP_1_AUX_DN_C 3 4 DDPB_CTRL_DATA
5 ML_LANE1P
12 DDSP_C_TX_DATA3 GND
12 DDSP_C_TX_DATA3# RCLAMP0524PATCT-GP DDSP_B_TX_DN_1_C 6 DP_DEVICE_DETECT 2 5 DP_DEVICE_DETECT HDMI_DEVICE_DETECT 2 5 HDMI_DEVICE_DETECT
DDSP_B_TX_DP_2_C 7 ML_LANE1N
U70 (R) 8 ML_LANE2P DDSP_AUX_DP_C 1 6 DDSP_1_AUX_DP_C DDSP_1_AUX_DP_C 1 6 DDPB_CTRL_CLK
19 DP2_HPD_N 30mil DDSP_B_TX_DN_2_C 9 GND
500mA (Max.) ML_LANE2N
1
19 DP2_AUX_N DDSP_1_AUX_DN_C 1 8 DDSP_1_AUX_DN_C DDSP_B_TX_DP_3_C 10
L1#1L1#8 ML_LANE3P
1
19 DP2_AUX_P DDSP_1_AUX_DP_C 2 7 DDSP_1_AUX_DP_C 11 2N7002KDW-1-GP R94 2N7002KDW-1-GP
G1 L2#2L2#7 G2 F6309 DDSP_B_TX_DN_3_C 12 GND
DDSP_B_TX_DN_3_C 3 GNDGND 6 DDSP_B_TX_DN_3_C POLYSW-1D5A8V-3-GP DP_DONGLE_DET 13 ML_LANE3N 100KR2J-1-GP
19 DDPC_CTRL_DATA L3#3L3#6 GND
DDSP_B_TX_DP_3_C 4 5 DDSP_B_TX_DP_3_C R9955 2 1 1MR2J-1-GP DP1_14 14
19 DDPC_CTRL_CLK
2
L4#4L4#5 DDSP_1_AUX_DP_C 15 GND
2
16 AUX_CHP
RCLAMP0524PATCT-GP DDSP_1_AUX_DN_C 17 GND
DDSP_B_HPD_CONN 18 AUX_CHN
U71 (R) 19 HP_DETECT X3
DP_PWR 20 RETURN SHELL3 X4
C C
DDSP_B_TX_DN_1_C 1 8 DDSP_B_TX_DN_1_C DP_PWR SHELL4
DDSP_B_TX_DP_1_C 2 L1#1L1#8 7 DDSP_B_TX_DP_1_C
L2#2L2#7
1
G1 G2 C202 C56 DISPLAYPORT-1-GP
DDSP_B_TX_DN_0_C 3 GNDGND 6 DDSP_B_TX_DN_0_C SC470P50V2KX-3GP SCD1U16V2ZY-2GP (22.10329.081)
DDSP_B_TX_DP_0_C 4 L3#3L3#6 5 DDSP_B_TX_DP_0_C
2
L4#4L4#5
RCLAMP0524PATCT-GP
!"#$%&'()*+,-*%(%"+.(/0!(!"*1.#
12V_S0
!"#$%&#""&'(!&)%#*&+!&',))%$-,* !"#$%"&'()*(+,""$+#,%(-(.,%(/0 !"#$%&$'()*++,(-..(/*0123(4,546,7

12V_S0
1
(L) R114
DDSP_C_TX_DATA0 C241 1 2 SCD1U16V2ZY-2GP DDSP_C_TX_DP_0_C 20KR2J-L2-GP
1
DDSP_C_TX_DATA0# C75 1 2 SCD1U16V2ZY-2GP DDSP_C_TX_DN_0_C 3D3V_S0 (L)
(L)
!"#$A&"!()*++,(8..(,07350-2(/B(C*5(!D 10KR2J-3-GP
2
1
DDSP_C_TX_DATA1 C213 1(L) 2 SCD1U16V2ZY-2GP DDSP_C_TX_DP_1_C R113
!"#$%&$@(EF-013(7*('$#?'!"@#$'$
1
DDSP_C_TX_DATA1# C74 1 2 SCD1U16V2ZY-2GP DDSP_C_TX_DN_1_C R112 (L)
2
(L) (R)
DP2 1KR2J-1-GP R110
DDSP_C_TX_DATA2 C73 1(L) 2 SCD1U16V2ZY-2GP DDSP_C_TX_DP_2_C 21 15KR2F-GP
2
DDSP_C_TX_DATA2# C72 1 2 SCD1U16V2ZY-2GP DDSP_C_TX_DN_2_C Q10 (L)
2
(L) DDSP_C_TX_DP_0_C 1 HDMI2_DEVICE_DETECT 6 1
3D3V_S0 (L) 2 DP2_DONGLE_DET_C_2
DDSP_C_TX_DATA3 C71 1(L) 2 SCD1U16V2ZY-2GP DDSP_C_TX_DP_3_C 2 DP2_DONGLE_DET R1091 2 DP2_DONGLE_DET_C 5
1
B B
DDSP_C_TX_DATA3# C216 1 2 SCD1U16V2ZY-2GP DDSP_C_TX_DN_3_C DDSP_C_TX_DN_0_C 3 25 4 3 DP2_DEVICE_DETECT
1
(L) DDSP_C_TX_DP_1_C 4 4K7R2J-2-GP
5 MBT3904DW1T1G-2-GP R111
1
DP2_AUX_N C42 1(L) 2 SCD1U16V2ZY-2GP DDSP2_AUX_DN_C DDSP_C_TX_DN_1_C 6 R108 C61 (L) 4K99R2F-L-GP
DP2_AUX_P C70 1 2 SCD1U16V2ZY-2GP DDSP2_AUX_DP_C DDSP_C_TX_DP_2_C 7 1MR2J-1-GP SC470P50V2KX-3GP (L)
2
(L) 30mil 8 (L) (R)
2
500mA (Max.) DDSP_C_TX_DN_2_C 9
DDSP_C_TX_DP_3_C 10
1
11 24
F2 DDSP_C_TX_DN_3_C 12
POLYSW-1D5A8V-3-GP (L) DP2_DONGLE_DET 13
(L) R57 2 1 1MR2J-1-GP DP2_14 14
/0! U73 (R) DDSP_2_AUX_DP_C 15
2
16 3D3V_S0
DDSP_C_TX_DN_2_C 1 8 DDSP_C_TX_DN_2_C DDSP_2_AUX_DN_C 17
DDSP_C_TX_DP_2_C 2 L1#1L1#8 7 DDSP_C_TX_DP_2_C DDSP_C_HPD_CONN 18
L2#2L2#7
2
G1 G2 19 23
DDSP_C_HPD_CONN 3 GNDGND 6 DDSP_C_HPD_CONN DP2_PWR 20 R107
DP2_DONGLE_DET 4 L3#3L3#6
L4#4L4#5
5 DP2_DONGLE_DET
22
100KR2J-1-GP
(L) *12
1
1
RCLAMP0524PATCT-GP C57 C58 ARG-CON20-GP Q8 Q9

SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP DDSP_2_AUX_DN_C 3 4 DDSP2_AUX_DN_C DDSP_2_AUX_DN_C 3 4 DDPC_CTRL_DATA
U74 (R) (L78.47124.2FL) (L) (L)
2
DP2_DEVICE_DETECT 2 5 DP2_DEVICE_DETECT HDMI2_DEVICE_DETECT 2 5 HDMI2_DEVICE_DETECT

DDSP_2_AUX_DN_C 1 8 DDSP_2_AUX_DN_C
DDSP_2_AUX_DP_C 2 L1#1L1#8 7 DDSP_2_AUX_DP_C DDSP2_AUX_DP_C 1 6 DDSP_2_AUX_DP_C DDSP_2_AUX_DP_C 1 6 DDPC_CTRL_CLK
G1 L2#2L2#7 G2
GNDGND
1
DDSP_C_TX_DN_3_C 3 6 DDSP_C_TX_DN_3_C
DDSP_C_TX_DP_3_C 4 L3#3L3#6
L4#4L4#5
5 DDSP_C_TX_DP_3_C
5V_S0
8)9:;<==>'$#?'!"@#$'$ 2N7002KDW-1-GP R106 2N7002KDW-1-GP
(L) (L) (L)
100KR2J-1-GP
RCLAMP0524PATCT-GP
2
U75 (R)
R272 2 (R) 1 100KR2J-1-GP
DDSP_C_TX_DN_1_C 1 8 DDSP_C_TX_DN_1_C
DDSP_C_TX_DP_1_C 2 L1#1L1#8 7 DDSP_C_TX_DP_1_C
G1 L2#2L2#7 G2
G
A DDSP_C_TX_DN_0_C 3 GNDGND 6 DDSP_C_TX_DN_0_C A

DDSP_C_TX_DP_0_C 4 L3#3L3#6 5 DDSP_C_TX_DP_0_C
L4#4L4#5
DP2_HPD_N S D DDSP_C_HPD_CONN
RCLAMP0524PATCT-GP
Q23
<Core Design>
1
2N7002BK-GP
(L84.2N702.J31) R273
(L)
!"#$%&'()*+,-*%(%"+.(/0!(!"*1.# 100KR2J-1-GP Wistron Corporation
2

!"#$%&'%#(&$)''%$*)(&!+'
Title
Display Port
Custom
vSuperb -1
5 4 3 2 1
HDD Connector
HDD1
9
HDD1 19 SATA_TXP1 SCD01U16V2KX-3GP 2
2
1 C5614
1 C5613
SATA_TXP1_C
7
6
5
19 SATA_TXN1 SCD01U16V2KX-3GP SATA_TXN1_C
4
19 SATA_RXN1 SCD01U16V2KX-3GP 1 2 C5616 SATA_RXN1_C 3
SCD01U16V2KX-3GP 1 2 C5615 SATA_RXP1_C 2
19 SATA_RXP1 Layout: Put them together
1
8 5V_S0 2012/02/13 5V_HDD
Change Fuse from 3A to 2A 5V_ODD
F5601 (69.50014.001)
(20.81593.007)
1 2
SKT-SATA7P-19-GP-U
C5611
1
Black color POLYSW-2A6V-GP 5V_HDD (R)
F5602 C5612 SC10U10V5ZY-1GP
!"#"$%&'$()** 1 2
HDDPW1
2
SCD1U10V2KX-5GP
5V_HDD 1 POLYSW-2A6V-GP
(69.50014.001)
2
1
(R)
C5618 C5617 JWT-CON2-S14-GP
SC10U10V5ZY-1GP SCD1U10V2KX-5GP
2
(21.61783.102)
HDD2 !"#$%&$"'()**+',-./01'2)'3451'6)4)7
9
7
HDD2 19
19
SATA_TXP4
SATA_TXN4
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
2
2
1 C5622
1 C5621
SATA_TXP4_C
SATA_TXN4_C
6
5
4
19 SATA_RXN4 SCD01U16V2KX-3GP 1 2 C5623 SATA_RXN4_C 3
19 SATA_RXP4 SCD01U16V2KX-3GP 1 2 C5624 SATA_RXP4_C 2
1
8
(20.81595.007)
SKT-SATA7P-19-GP-U
Blue color
HDDPW2 !"#"$+&'$()**
5V_HDD 1
2
1
(R)
C5620 C5619 JWT-CON2-S14-GP
SC10U10V5ZY-1GP SCD1U10V2KX-5GP
2
(21.61783.102)
ODD Connector
ODD1 ODDPW1
8 5V_ODD 1
1
2
SCD01U16V2KX-3GP 2 1C5608 SATA_RXP5_C 2
19 SATA_RXP5
1
SCD01U16V2KX-3GP 2 1C5607 SATA_RXN5_C 3 (R)

19 SATA_RXN5 JWT-CON2-S14-GP
4 C5605 C5606
19 SATA_TXN5 SCD01U16V2KX-3GP 2 1 C5610 SATA_TXN5_C 5 SC10U10V5ZY-1GP SCD1U10V2KX-5GP
2
19 SATA_TXP5 SCD01U16V2KX-3GP 2 1 C5609 SATA_TXP5_C 6 (21.61783.102)

7
9
SKT-SATA7P-19-GP-U
(20.81593.007)
<Core Design>
Wistron Corporation
Title
SATA Port
Custom
vSuperb -1
5 4 3 2 1
!"#$%&'()*+) !"#$%&'%()
20 USB30_RN1
(*++,-%()
20 USB30_RP1
20 USB30_TN1 !"#!$"%$"&'
D
20 USB30_TP1
(()#'*)+,'-./&,'012345'!6738
!"#$%$"&'$()*+,- 11
BTNBD1
D
35 USB_PP0_R
35 USB_PN0_R R1020
FIOBD1 OBR 1 2 OBR_R 1
33R2J-2-GP
27 BRIGHTNESS 2
1
C893 PWRBTN# 3
3
HP_OUT_L_CON 1 SCD1U16V2ZY-2GP PWRLED_CON 4
D38 SUSLED_CON 5
2
JD_HP 2 BAV99-13-GP LAN_LED*_EMI 6
HP_OUT_R_CON 3 HD_LED_PWR_EMI 7
4 (75.00099.O7D) SATA_LED_OUT_EMI 8
MIC_IN_L_JK 5 PANEL_SW_N 9
2
MIC_IN_JD 6 3D3V_S0 10
MIC_IN_R_JK 7
AGND 8 12
9
&(),%-+(,+) USB30_TP1 1
C6235
2 USB30_TP1_RI
SCD1U16V2KX-3GP
USB30_TP1_RI
USB30_TN1_RI
10
11
ACES-CON10-14-GP
12 (20.F1819.010)
USB30_TN1 1 2 USB30_TN1_RI USB_PP0_R 13
20 USB_PP2
C6234 SCD1U16V2KX-3GP USB_PN0_R 14
20 USB_PN2 !"#$%&'()*+,* 15
USB30_RP1 1 2 USB30_RP1_R* USB30_RN1_R* 16
C6231 0R0402-PAD USB30_RP1_R* 17
18
21%=&5
USB30_RN1 1 2 USB30_RN1_R* USB_PN2 19
R1022
C6230 0R0402-PAD USB_PP2 20 PANEL_SW 1 2 PANEL_SW_N
!" 21 33R2J-2-GP
22
5V_CHARGER_OUT
1
23 C896
./,01 <"#<$"=$#> !"#!$#!$!% 24
25
D39
BAV99-13-GP
SCD1U16V2ZY-2GP
)*+?-.?(@*+,-.(A7B.?(87C?@. #3(45(67(89:.(';
2
3D3V_S5 26 (75.00099.O7D)
28
27 HP_OUT_R_CON
2
3D3V_S0
27 HP_OUT_L_CON
27 JD_HP
C PTWO-CON26-8-GP C
27 MIC_IN_L_JK
27 MIC_IN_R_JK
26 MIC_IN_JD
R1021
BRIGHTNESS_N 1 2 BRIGHTNESS
33R2J-2-GP
1
C895
3
SCD1U16V2ZY-2GP
D40
2
BAV99-13-GP
(75.00099.O7D)
#23#4
2
3D3V_S0
19 OBR !"#<$"=$!#
40 PWRBTN# 17889(:.D.6.(EE)!
40 PWRLED_CON
40 SUSLED_CON
54486.3%674
V_3P3_LAN V_3P3_LAN
19 SATA_LED#
544%674 !"#!$##$!% 6.3%674
24 LAN_LED3_CTRL &'()*+,-.(&/&()012 !"#$%&$'()*+,-.()/,01/2(34(567(8/9.1:(;<(=.2+4
1
3D3V_S0 5V_S0
25 LINK*_ACTIVITY_L
R274 R7981
10KR2J-3-GP
!"#!$##$!% 100KR2J-1-GP
B B
&'()**(+,(*-.)/
2
1
LAN_LED3_CTRL_R
R738 5V_S5 5V_S5 D5 (R)
10KR2J-3-GP R8010
G
LAN_LED3_CTRL_C K A 1 2 LAN_LED3_CTRL
L48
1
2
1
SATA_LED# S D SATA_LED_OUT 1 2 SATA_LED_OUT_EMI (R) R742 1N4148WS-7-F-GP 0R2J-2-GP
22KR2J-GP R233
9389:: (83.00355.F1F)
1
C38 1MR2J-1-GP
Q47 BLM15BA750SN1D-GP SC1U6D3V2KX-GP (R)
2
2N7002-11-GP
20,24 PANEL_SW
2
(84.2N702.J31)
G
2
R744 Q50
PMBS3906-GP 1LAN_LEDC1 2 1 LAN_LEDC111 D S 2N7002-11-GP LINK*_ACTIVITY_L
Q49 (84.2N702.J31)
5V_S0 (84.T3906.E11) 4K7R2J-2-GP
LAN_LEDC03
#-;<5237"" !"#$%&'!()*++,(-./012(3*(!$$*.4(562(3*(-677203(3*(+4/88
1
R733 5V_S0
200R5J-GP
(63.10133.16L)
1
24 BRIGHTNESS_N L47
2
R745
HD_LED_PWR 1 2 HD_LED_PWR_EMI 200R5J-GP R746
(R63.10133.16L) 220R5J-GP
(63.10133.16L)
L57
2
2
BLM15BA750SN1D-GP
LAN_LED*_EMI1 2 LAN_LED*
!"#$%&'!()*++,(-./012(3*(!$$*.4(562(3*(-677203(3*(+4/88
BLM15BA750SN1D-GP
A A
<Core Design>
Wistron Corporation
Title
Side IO Port
C
vSuperb -1
5 4 3 2 1
5 4 3 2 1
$%&'(%)(&*
+,,-./01231-4514657-89::9;-<3:50
usb3.0
20 USB30_TN0
Truth Table for TPS2540A/TPS2543/TPS2546 C3002
1
SCD1U16V2ZY-2GP
2
20 USB30_TP0 5V_CHARGER_OUT
20 USB30_RN0
20 USB30_RP0 ACPI Control CTL1 CTL2 CTL3 ILIM_SEL PWR Control Mode
5V_A
U3001
20 USB_PP1
(R)
20 USB_PN1 S0 1 1 1 1 5V_A CDP R3002 2 110KR2J-3-GP 1 12
IN OUT
20 USB_OC_02
USB_OC_02 13 11 USB_PN0_R
D S1 1 1 1 1 5V_A CDP FAULT# DM_IN D
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
10 USB_PP0_R
DP_IN
1
TC3001
C3003
C3007
ILIM_SEL 4 2 USB_PN0 ST220U6D3VDM-20GP
S3 0 1 1 1 5V_A DCP ILIM_SEL DM_OUT 3 USB_PP0 (R)
2
9 DP_OUT (64.22125.6DL)
NC#9 16 TPS2540_ILIM0 R3003 1 2 20KR2F-L-GP
S4 0 1 1 1 5V_A DCP R3004 1 210KR2J-3-GP ENABLE_2540 5 ILIM0 15 TPS2540_ILIM1 R3005 1 2 46K4R2F-2-GP
5V_A EN ILIM1
CHARGER_CTL1_R 6 (64.22125.6DL)
USB_CHARGER_CTL2 7 CTL1 14
S5 0 1 1 1 5V_A DCP USB_CHARGER_CTL3 8 CTL2 GND 17
CTL3 GND
S5_EuP 0 1 1 1 5V_A DCP TPS2540ARTER-GP

(74.02544.073)
9/5 R_ILIM_LO = R_ILIM_HI = 22.1K
G3->S5 0 1 1 1 5V_A DCP Current limit = 2120 ~ 2430 mA
3D3V_A 5V_A 3D3V_A 3D3V_A 3D3V_A

CHARGER
1
17 ILIM_SEL
R3006 R3007 R3008 R3009 R3010
24 USB_CHARGER_CTL1
24 USB_CHARGER_CTL3 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
2
20 USB_PN0 2 R3011 1 CHARGER_CTL1_R ILIM_SEL USB_CHARGER_CTL2 USB_CHARGER_CTL3
20 USB_PP0
34 USB_PN0_R Change on 2011.08.31
(R)
34 USB_PP0_R
#$8"9%"!-':441-;(*(2(-<:0(5-4012,3 0R2J-2-GP 01/10 Revise
2
D
R3012 R3013 R3014
0R2J-2-GP 0R2J-2-GP 0R2J-2-GP
C (R) (R) (R) C
USB_CHARGER_CTL1 G
1
Q3001
S
2N7002BK-GP !"#"$%"&'()&*+,&-./$0"$&#1223$4
(84.2N702.J31)
01/18 G3->S5 has charger USB_PN0 R3015 1 (R) 2 0R2J-2-GP USB_PN0_R
USB_PP0 R3016 1 (R) 2 0R2J-2-GP USB_PP0_R
R3017 1 (R) 2 0R3J-0-U-GP

5V_A R3018 1 (R) 2 0R3J-0-U-GP
5V_CHARGER_OUT
2011/10/8 Hign ACTIVE TYPE!! USB30_VCCA

!"#$%"&%!& 5V_S5 U6201 USB30_TP0 1 2 USB30_TP0_C
100 mil C6209 SCD1U16V2KX-3GP
'()*+,(-./.-0123-4(51(4-"-637 1
2 GND VOUT#8
8
7
USB30_TN0 1
C6208
2 USB30_TN0_C
SCD1U16V2KX-3GP
3 VIN VOUT#7 6
VIN VOUT#6
1
4 5 C6201 C6203
EN OC#
1
C6202
SC10U10V5ZY-1GP
SC1U10V3ZY-6GP
SCD1U16V2KX-3GP
2
2
B B
UP7534PRA8-20-GP
2
3D3V_S5 (74.02820.B79)
R6221
1 2
10KR2J-3-GP
USB_OC_02
C6204 !"#$%&'$()**+,-).
TR6205 36,37 USB_EN
1
SCD1U16V2ZY-2GP
USB30_RN0_R 1 2 USB30_RN0
$/0*$1+20*0-0)*
2
USB30_RP0_R 4 3 USB30_RP0 1 POWER
FILTER-4P-123-GP 2 USB 2.0 D-
3 USB 2.0 D+
(66.R0036.04L)
4 GND
USB30_VCCA 5 StdA_SSRX- SuperSpeed RX
TR6206 2012/11/09
6 StdA_SSRX+
1
USB30_TN0_R 1 2 USB30_TN0_C
R6206 USB3.0 Tape up 7 GND
USB30_TP0_R 4 3 USB30_TP0_C 0R0805-PAD-1-GP-U
AUSB2_PWR
USBR2 8 StdA_SSTX- SuperSpeed TX
10
2
FILTER-4P-123-GP USB30_TP0_R 9
1
9 StdA_SSTX+
AUSB2_PWR
(66.R0036.04L)
USB30_TN0_R 8
1
USB_PN1_R 2
7 TC6203
USB_PP1_R 3 ST100U6D3VBM-7GP
2
USB30_RP0_R 6 (77.C1071.081)
TR6208 4
USB_PP1_R 1 2 USB_PP1 USB30_RN0_R 5
11
A USB_PN1_R 4 3 USB_PN1 !"#$>&?!(;/@@A()*+,-.(;.+1(BCD(0/(E/10$ A
SKT-USB11-40-GP
MCM1012B900FBP-GP-U (22.10339.G21)
(66.R0036.04L)
<Core Design>
Wistron Corporation
Title
USB 3.0 Port/Charger

C
vSuperb -1
5 4 3 2 1
5 4 3 2 1
USB EN CTRL
D D
17 USB_WAKE_SLP
17,24,53 PM_SLP_S4#
R1337
1 2 19V_USB_EN
DCBATOUT
0R0402-PAD
1
R1340
47KR2J-2-GP
R1341
2
USB_EN2 1 2 USB_EN USB_EN 35,37
1
C 10KR2J-3-GP C
1
R1343 C1090
D
100KR2J-1-GP R1345 SCD1U50V3KX-GP
Q326 15KR2F-GP
2
USB_EN1 G (84.2N702.J31)
2
2N7002A-7-GP
1
R1347
D
S
100KR2J-1-GP
Q328 !"#$%"#%"!
#&'()*+,+-*'.)'#/01'2$'3)4.'*-5+6-'+447-
2
PM_SLP_S4# G
2N7002A-7-GP
(84.2N702.J31)
S
2009/11/04
D
Q344
USB_WAKE_SLP G (84.2N702.J31)
B 2N7002A-7-GP B
S
!"#$%"8%!$
S5 S4 S3-S0 S5 S4 S3-S0 !"#$!%$&&'$()*+(,$-.$/!0123451!67$

!8&!9$$&&'$()*+(,$-.$!671!":
SLP_S4# L L H
L L H
USB_WAKE_SLP L L L USB_EN
USB_WAKE_SLP H H H H H H
<Core Design>
A
Wistron Corporation A

Title
USB Power SW
Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
!"#$%&
!"#$%&'(44$,-$5/#$607 !"#$%&'(?*@$,-$.=A='BC$D&'$)E
20 USB_PP11
20 USB_PN11 !"#!$"%$#&
'()('*(+,-.
VCC5_USB_018 VCC5_CAM
F6303
1 2 L6301
USB_PP11 1 2 USB_PP11_11+
D D
POLYSW-2A6V-2-GP
'()$*
1
3D3V_S5 (R69.50014.001) C6303 C6304 USB_PN11 4 3 USB_PN11_11-
#$8"?%!#-'@441-+AA-BC2(5C+*-D;<-,@CC(,2@5
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP
MCM1012B900FBP-GP-U
20 USB_PP9
2
20 USB_PN9 1
F6304
2
(66.R0036.04L) ------------------)@0(5-E4(-5(+5-D;<$8"-)@0(5-
POLYSW-2A6V-2-GP USB2H1
11
(69.50014.001) 1
USB30_VCCA
2
)+#,-. USB_PN4_4- 3
USB_PP4_4+ 4
20 USB_OC_01 5
USB_PN5_5- 6
USB_PP5_5+ 7
20 USB_PP8 8
20 USB_PN8 9
10
20 USB_PP3
20 USB_PN3 !"#$%&'($8$,-$93!6: ACES-CON9-5-GP
!"#$%"&%!$ (L)
!"#$%&#'()*+$',-
'()*+,(-./.-0123-4(51(4-"-637 ./01234!0//!
/01023045672589 VCC5_USB_018 VCC5_TOU
20 USB_PP4
L6303
20 USB_PN4 USB_PN9 4 3 USB_PN9_9-
20 USB_PP5
1
C6307 C6308 USB_PP9 1 2 USB_PP9_9+
20 USB_PN5
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP
MCM1012B900FBP-GP-U L14 L16
2
(66.R0036.04L) USB_PP4 4 3 USB_PP4_4+ USB_PP5 4 3 USB_PP5_5+
C C
USB_PN4 1 2 USB_PN4_4- USB_PN5 1 2 USB_PN5_5-
MCM1012B900FBP-GP-U MCM1012B900FBP-GP-U
(L66.R0036.04L) (L66.R0036.04L)
!"#$%&'($)*+,-$./0.$123 5/#607293!6:2;716$6&<<=>(&'
VCC5_USB_018
B B
D8201
U6301 DMIC_CLK 1 WTD1

13
1 8 3
2 GND VOUT#8 7 1
5V_S5 VIN VOUT#7 3D3V_DMIC
3 6 DMIC_DATA 2
USB_EN 4 VIN VOUT#6 5 DMIC_DATA 2
35,36 USB_EN EN OC# 26 DMIC_DATA DMIC_CLK 3
TC6301 C6309
26 DMIC_CLK
1
C6301 (R) C6302 (R) AZ5125-02S-R7G-GP 4

UP7534PRA8-20-GP (77.C1071.081) USB_PN11_11- 5
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
(R)
1
ST100U6D3VBM-7GP
1 2 (74.02820.B79) (R) USB_PP11_11+ 6

3D3V_S5
2
7
R6317 3D3V_S5 USB_PN9_9- 8
2
10KR2J-3-GP USB_PP9_9+ 9
USB_OC_01 10
3D3V_DMIC 11
VCC5_TOU
1
2011/10/8 VCC5_CAM
12
C6314 USB2R1
SCD1U16V2ZY-2GP 11 10 14
2
VCC5_USB_018 5 1 VCC5_USB_018
ACES-CON12-25-GP
1
USB_PN3_3- 6 2 USB_PN8_8- F6308 C6311 C6310 (20.F1637.012)
USB_PP3_3+ 7 3 USB_PP8_8+ 1 2
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP
8 4
2
12 9 POLYSW-2A6V-2-GP
#$8"9%#:-;<-5()*+,(-=>-./. (69.50014.001)
SKT-USB12-34-GP
L6305 L6307
USB_PP8 4 3 USB_PP8_8+ USB_PP3 4 3 USB_PP3_3+
A A
USB_PN8 1 2 USB_PN8_8- USB_PN3 1 2 USB_PN3_3-
MCM1012B900FBP-GP-U MCM1012B900FBP-GP-U
(68.01012.20B) (68.01012.20B)
<Core Design>
Wistron Corporation
Title
Rear USB/Touch/Web Cam
Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
D
Mini Card Connector(Wireless LAN+BT) D
Michael 2011/12/05
Michael 2011/11/29
Change the MINI PCIE CONN P/N
Change 1D5V_MEM to 1D5V_S0
1D5V_S0_WLAN
Michael 2011/11/29 3D3V_S5 PCIE2
Change 3D3V_S0 to 3D3V_EUP 6 11 CLK_PCIE_WLAN#
1_5V REFCLK- CLK_PCIE_WLAN# 18
13 CLK_PCIE_WLAN CLK_PCIE_WLAN 18
1D5V_S0 1D5V_S0_WLAN 2 REFCLK+
R6513 3_3VAUX 23
(R) PCIE_RXN1 PCIE_RXN5 20
2 1 0R2J-2-GP 28 PERN0 25 PCIE_RXP1
+1_5V PERP0 PCIE_RXP5 20
48
+1_5V 31 PCIE_TXN1
PETN0 PCIE_TXN5 20
24 33 PCIE_TXP1 PCIE_TXP5 20
3D3V_S5 R6514 +3_3VAUX PETP0
(R) 39
2 1 0R2J-2-GP 3D3V_S5_RSV 41 +3_3VAUX 36 USB_PN10
3D3V_S5 +3_3VAUX USB_D- USB_PN10 20
52 38 USB_PP10
+3_3VAUX USB_D+ USB_PP10 20
8
UIM_PWR 1 W1_WAKE_N R6508 1 2 0R0402-PAD PCIE_WAKE_N_PCIE
C WAKE# PCIE_WAKE_N_PCIE 17 C
16 7 CLK_PCIE_WLAN_REQ# 17
UIM_VPP CLKREQ# 22
PERST# PLT_WLAN_RST# 24
1
10
R6509 3D3V_S5 12 UIM_DATA 53
10KR2J-3-GP 14 UIM_CLK 53 54
UIM_RESET 54
17 NP1
2
19 RESERVED#17/UIM_C8 NP1 NP2

45 RESERVED#19/UIM_C4 NP2
47 RESERVED#45
20 W3_DISABLE_N RESERVED#47
1
49 4
R6506 W3_DISABLE_N 51 RESERVED#49 GND 9
10KR2J-3-GP RESERVED#51 GND 15 1D5V_S0_WLAN
3 GND 18
5 COEX1 GND 21 Please close to PCIE2
2
COEX2 GND 26
GND
1
W1_DISABLE_N 20 27 C6504 C6505 C6503
20 W1_DISABLE_N W_DISABLE# GND 29 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC10U10V5ZY-1GP
R6501 1 (R) 210KR2J-3-GP 42 GND 34 (R) (R) (R)
2
44 LED_WWAN# GND 35
46 LED_WLAN# GND 37
LED_WPAN# GND 40
SMB_CLK R6504 1 (R) 2 0R2J-2-GP M1_SMB_CLK 30 GND 43
15,16,17,23,28,29,39,41 SMB_CLK SMB_CLK GND
15,16,17,23,28,29,39,41 SMB_DATA SMB_DATA R6503 1 2 0R2J-2-GP M1_SMB_DATA 32 50
(R) SMB_DATA GND
B B
SKT-MINI52P-93-GP
(62.10043.I21)
3D3V_S5
Please close to PCIE2
1
C6506 C6507 C6502
PLT_WLAN_RST# SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC10U10V5ZY-1GP
2
1
(R) C6508
SB
SC10P50V2JN-4GP
2
<Core Design>
A A
Wistron Corporation
Title
Mini PCIE WLAN/BT

Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
mSATA
3D3V_S0
D
13.05/15 delete reserved PCIE function D
MSATA1
!"#" 19 SATA_RXP0
6
1.5V REFCLK+
13
11
19 SATA_RXN0 2 REFCLK-
19 SATA_TXN0 3.3V 23 SATA_RXP0_C SCD01U16V2KX-3GP 2 1 C6605 SATA_RXP0
19 SATA_TXP0 PERN0
28 25 SATA_RXN0_C SCD01U16V2KX-3GP 2 1 C6604 SATA_RXN0
48 +1.5V PERP0
+1.5V 31 SATA_TXN0_C SCD01U16V2KX-3GP 2 1 C6612 SATA_TXN0
52 PETN0 33 SATA_TXP0_C SCD01U16V2KX-3GP 2 1 C6611 SATA_TXP0
+3.3V PETP0
24 36
+3.3VAUX USB_D- 38
USB_D+
$%&'() 3
RESERVED#3 SMB_CLK
30 SMB_CLK_MAIN_C 0R2J-2-GP 2 (R) 1 R6609 SMB_CLK
C 5 32 SMB_DATA_MAIN_C 0R2J-2-GP 2 1 R6610 SMB_DATA C
8 RESERVED#5 SMB_DATA (R)
15,16,17,23,28,29,38,41 SMB_CLK RESERVED#8
15,16,17,23,28,29,38,41 SMB_DATA 10
3D3V_S5 12 RESERVED#10 1
14 RESERVED#12 WAKE# 7
20 mSATA_DET# 16 RESERVED#14 CLKREQ# 22
17 RESERVED#16 PERST#
(R) 19 RESERVED#17
R6612 2 1 10KR2J-3-GP W_DISABLE_M# 20 RESERVED#19 4
37 RESERVED#20 GND 9
R6614 1 (R) 2 10KR2J-3-GP 39 RESERVED#37 GND 15
41 RESERVED#39 GND 18
R6607 2 1 33KR2J-3-GP 43 RESERVED#41 GND 21
3D3V_S5 RESERVED#43 GND
45 26
47 RESERVED#45 GND 27 3D3V_S0
(R) 49 RESERVED#47 GND 29
mSATA_DET# R6613 2 1 0R2J-2-GP mSATA_DET#_C 51 RESERVED#49 GND 34
RESERVED#51 GND 35
B GND 40 C6626 C6618 C6619
B
GND
1
SC10U6D3V3MX-GP
42 50
LED_WWAN# GND
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
44 53
46 LED_WLAN# GND 54
2
LED_WPAN# GND
NP1
NP2
NP1
NP2
SKT-MINI52P-32-GP-U
<Core Design>
Wistron Corporation
A Taipei Hsien 221, Taiwan, R.O.C. A
Title
Mini PCIE mSATA

Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
G8202
USB30_VCCA 1 2 V_5_LED
2
COPPER-CLOSE-GP-U
5V_S0 R8011
0R0402-PAD USB30_VCCA 3D3V_S5
!"#!$##$!% SUSPEND LED
1
L8201 R8218 SUSLED_DELAY
1
PWRLED_CON 1 2 V_5_PWR1 1 2 (R) R8222 R8223
D
34 PWRLED_CON &'()**(+,(*-.)/ C7928 10KR2J-3-GP 4K7R2J-2-GP D
MHC1608S601LBP-GP 130R5J-GP SCD1U16V2ZY-2GP (R)
2
(63.10133.16L)
2
20110626
!"#$%&'!()*++,(-./012(3*(!$$*.4(562(3*(-677203(3*(+4/88
2
Q8201 R8221
1 SUSLED_1 1 2 SUSLED_N
PMBS3906-GP SUSLED_N 24
(84.T3906.E11) 2K2R2J-2-GP
1
2010/11/15
SUSLED_CON_P1
(63.10334.1DL)
add as vendor R8224
suggestion 10KR2J-3-GP
(R)
2
1
R8220 2009/12/01
200R5J-GP
20100115
2
3D3V_A
C V_5_SUS1 C
2
2
R8212
330KR2J-L1-GP 10mW L8202
MHC1608S601LBP-GP
1
PWRBTN# 2 1 PWRBTN_IN
34 PWRBTN# PWRBTN_IN 24
1
1
R8213 C8209
SCD01U16V2KX-3GP
470R2J-2-GP 34 SUSLED_CON SUSLED_CON
1
2
R8219
10KR2J-3-GP
3
(R)
U8202
2
BAV99-13-GP
(78.10321.2FL) (R)
2
3D3V_S5
B B
<Core Design>
A Wistron Corporation A
Title
PWR BT/Side Key/LED

Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
!"#$%&'(
D D
3D3V_S0 3D3V_S0
!""#$%&&'$()*+,$-.&,.&/$01,.201,.)*,$345&+5)/
2
1
1
C434 C433 R669
SCD1U16V2ZY-2GP SC1U10V3ZY-6GP 4K7R2J-2-GP
C (G) (G) C
2
1
U1
9 7 GS_SDA R284 1 2 0R0402-PAD

DVDD SDA SMB_DATA 15,16,17,23,28,29,38,39
6 GS_SCL R285 1 2 0R0402-PAD
SCL SMB_CLK 15,16,17,23,28,29,38,39
3
AVDD 5
INT# GS_INT2# 20
12
GS_GND 1 GND 11
RESERVED#1 GND
8
DVSS
2
10
R286 2 NC#10 4
0R0402-PAD NC#2 AVSS
B B
MMA7660FC-GP
1
(G)
<Core Design>
A
Title
G-Sensor
A4
vSuperb -1
5 4 3 2 1
5 4 3 2 1
V_3P3_A_EPW
SPI
17 SPI_CS0#
SPI ROM Equal length need to less than 500mil
17 SPI_MISO
17 SPI_IO2
1
17 SPI_IO3
SC10U6D3V5KX-1GP
C6001 C6002
17 SPI_CLK
SCD1U10V2KX-5GP
(R)
17 SPI_MOSI
2
17 SPI_WP_R_N
V_3P3_A_EPW V_3P3_A_EPW
D D
17,54 PCH_SLP_A
!"#$%&'()*+'$*,$'+)$,&--+.)/0$12/'
1
V_3P3_A_EPW
1
R48
R37
3"4$567$*,$&,/0$+'$0/,(.*-)+.$8+0/9 1KR2J-1-GP
1KR2J-1-GP !"#$%"&%"'
U6001
2
()**+,-./.0.,1234,56,7.89.:
2
SPI_CS0# R38 1 2 15R2F-2-GP SPI_CS0#_R 1 8

SPI_MISO R30 1 2 15R2F-2-GP SPI_MISO_R 2 CS# VCC 7 SPI_IO3_R R40 1 2 15R2F-2-GP SPI_IO3
SPI_IO2 R36 1 2 15R2F-2-GP SPI_IO2_R 3 DO/IO1 HOLD#/IO3 6 SPI_CLK_R R41 1 2 15R2F-2-GP SPI_CLK
4 WP#/IO2 CLK 5 SPI_MOSI_R R44 1 2 15R2F-2-GP SPI_MOSI
GND DI/IO0
W25Q64FVSSIG-GP
(72.25Q64.F01) <K9GBL<E$5+,,*$(2M'N/$)+$<B+28
%+OO+1$0/,*N'$N&*0/
:;<$==>$;7?$@A9ABCDE9FG<
C;@$==>$<D7?$@A9AB<A;9GH<
SPI1
1 8
2 7
3 6 2N7002-11-GP Q6002
4 5 (R84.07002.I31)
D S
SKT-G6179-GP-U I463$!"$./,/.J/0
SPI_WP#_R
(R62.10089.001)
G
SPI_WP_R_N
C C
2
R6009
0R2J-2-GP
(R)
1
SPI_IO2_R
V_3P3_LAN
!"#$%&$'()*++,(-..(/*00(1,213,4 !"#$%&$5(67"8"797:8;(<("="67>'
!"#$#"%"&$'
1
R117
0R5J-5-GP V_3P3_A_EPW 3D3V_S5
!"#$$%&'()%#*(%+)"(,%+-./%0,12345,,( (S)
2
(S)
R298 1 2 0R5J-5-GP
(S)
C76 1 2
R119
EPW_CTRL_S S D 1 2
(S) SCD1U16V2ZY-2GP
EPW_CTRL_R R352 1 2 499R2F-2-GP U29
(S) AO3413L-GP 0R5J-5-GP
G
RN76
3
1 4
V_3P3_LAN
1
PCH_SLP_A 2 3 SLPM_BR 1 Q67 C211 EPW_CTRL

PMBS3904-1-GP SCD1U16V2ZY-2GP
B For AMT M0-M3 support SRN10KJ-5-GP (S) (S) B
2
2
1
(S) C242
S0 S3 S5 SC1U10V2KX-1GP
(S)
2
H H H
+RTC_VCC !"#$%&'()*+,,-)./0123)4+)5364-708)49:3 RTC_RST# RTC_RST# 17

R6002 RTC1
RTC_AUX_S5 Q6001 3
1KR2J-1-GP SRTC_RST# SRTC_RST# 17
2 RTC_PWR 1 2 1
2
3 Width=20mils C6005 2
SCD1U16V2KX-3GP
(R) 4
13D3V_AUX_S5_C
1
2
C6003 3D3V_A ACES-CON2-36-GP-U

SC1U6D3V2KX-GP (R) BAS40C-GP
1
(75.00040.07D) !"#$%"#&'$##"(
R6006 1 2 0R0402-PAD
2011/9/30 Clear CMOS CMOS1

Add CLR CMOS circuit 1
RTC_AUX_S5 R6007 1 2 20KR2F-L-GP RTC_RST# 2

PCH_RTCRST_DOWN 3
1
PIN-CON3-S-GP
1
A C6004 R6008 A
1 NC SC1U6D3V2KX-GP 4K7R2J-2-GP
2
2 RTC_RST
2
<Core Design>
3 GND
R2106 1 2 20KR2F-L-GP SRTC_RST#
RTC_AUX_S5
Wistron Corporation
1
C2103 Taipei Hsien 221, Taiwan, R.O.C.
SC1U6D3V2KX-GP Title
2
SPI/RTC
Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
.3,))*)+56217)*(6 !"#!$##$!%
&'()*+,(-.,/(0-11-2(&34(+566,+7
D 3D3V_A D
SPI +RTC_VCC
1
R232
200R2F-L-GP
1
24 SP1_RTS_N
R231
24 SP1_DTR_N
2 COPEN#_C
24 SP1_DSR_N 1MR2J-1-GP
24 SP1_RXD
!"#!$#!$#!
2
24 SP1_DCD_N
24 SP1_TXD
A
24 SP1_CTS_N
#%&'()*+,
D19
24 SP1_RI_N
17 PCH_RI 1N4148WS-7-F-GP
(83.00355.F1F) CSOPN1
R528 3
K
SIO_COPEN# 1 2 SIO_COPEN#_N 1
0R0402-PAD CASE_OPEN_R 2
1
C942
SC1U6D3V2KX-GP
4
R7907 (R)
1KR2J-1-GP
2
(R) ACES-CON2-36-GP-U
CASE OPEN
1
!"#$%"#&'$##"(
24 SIO_COPEN# !"#$%&'()*+,,-)./0123)4+)567)4893
C C
!"#!$"%$#&
#-."/$"0&1()*+,&'234256&62&!."&476'(&684,
'())*+,--+.(/+0(12+34,-41
COM1
SP1_R_DCD_N 10 9 SP1_R_RXD
SP1_R_TXD 8 7 SP1_R_DTR_N
6 5 SP1_R_DSR_N
SP1_R_RTS_N 4 3 SP1_R_CTS_N
SP1_R_RI_N 2 1
SERIAL PORT
X
5V_S0 PIN-CONN10A-SFP7-GP
B U4101 B
C616
SCD1U16V2KX-3GP 1 2COM_C1+ 28 26 C621 1 2 SC1U10V3ZY-6GP
COM_C1- 24 C1+ VCC
C619 C1- 27 COM_V+ C618 1 2 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP 1 2COM_C2+ 1 V+ 3 COM_V- C620 1 2 SCD1U16V2KX-3GP
COM_C2- 2 C2+ V- PCH_RI
C2-
22 4 SP1_R_CTS_N
R4104
C
23 FORCEOFF# RIN1 5 SP1_R_DSR_N
5V_S0 FORCEON RIN2 6 SP1_R_RXD SP1_R_RI_N 1 2 SP1_R_RI_C B Q4107
21 RIN3 7 SP1_R_DCD_N MMBT3904-4-GP
INVALID# RIN4
1
20 8 SP1_R_RI_N (84.T3904.K11)
E
ROUT2B RIN5 10KR2J-3-GP R4105
SP1_CTS_N 19 9 SP1_R_DTR_N 10KR2J-3-GP
SP1_DSR_N 18 ROUT1 DOUT1 10 SP1_R_RTS_N
SP1_RXD 17 ROUT2 DOUT2 11 SP1_R_TXD
2
SP1_DCD_N 16 ROUT3 DOUT3
SP1_RI_N 15 ROUT4 14 SP1_DTR_N
ROUT5 DIN1 13 SP1_RTS_N
25 DIN2 12 SP1_TXD Add RI# function for com port
GND DIN3 2011.05.24
8
7
6
5
8
7
6
5
MAX3243CDBR-GP-U RC4105 RC4106
SRC100P50V-2-GP SRC100P50V-2-GP
1
2
3
4
1
2
3
4
A A
<Core Design>
Wistron Corporation
Title
CSOPN/COM Port
Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
3D3V_S0
D D
1
R7101
10KR2J-3-GP
DBH1
2 1
2
17,24 LPC_AD3 LPC_FRAME# 24
4 3 V_3P3_DBP
17,24 LPC_AD2 6 5
8 7 CLK_PCI_LPC 18
17,24 LPC_AD1 10 9
17,24 LPC_AD0 12 11 PLT_RST# 11,20,24
14 13 3D3V_S0
JWT-CONN14D-4-GP
(R21.D1009.207)
C C
!"#$%&'(&)$*$+$#,--$.
3D3V_S5 3D3V_S0
TPM1
3D3V_S0 1 2 INT_SERIRQ
3 4 LPCPD_N_1 2 1 SUS_STAT_N
1
B 5 6 LPC_AD0 B
19,24 INT_SERIRQ R1155 7 8 LPC_AD1 33R2J-2-GP
10KR2J-3-GP 9 10 LPC_FRAME# R1154
11 12 CLK_PCI_LPC
17 SUS_STAT_N PLT_RST# 13 14 LPC_AD2
2
CLK_RUN_N 15 16 LPC_AD3
FOX-CONN16D-1-GP
<Core Design>
A
Title
Debug connector / TPM

A4
vSuperb -1
5 4 3 2 1
5 4 3 2 1
()$*+,-. !"# !"#$%&'

H4
2
H1 H2 H3 STF296R207H152-GP STF296R207H152-GP STF296R207H152-GP STF296R207H152-GP STF296R207H504-GP STF296R207H504-GP
3
2
4 HS1 HS2 HS3 HS4 HS5 HS6
4 4 4 1
1 1 1
5 8
5 8 5 8 5 8
1
D D
6
7
GENS315R158-8-F-A-GP
GENS315R158-8-F-A-GP GENS315R158-8-F-A-GP GENS315R158-8-F-A-GP
!"#$"456- /*&0&123%3
SKT1 SKT2 SKT3
HS8 HS10
STFT256B126R113H62-GP STF256R113-UH258-GP
1
1
C C
Load Plate Back Plate ILM COVER

(22.78006.001) (22.78006.011) (22.78005.161)
9(3
1D5V_S3
5V_S0 1D5V_S3
3D3V_S5
1
SC33P50V2JN-3GP
(R) (R) FC9713 FC9706

1
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
EC9706 EC9705 FC9705 (R)

1
SCD01U25V2KX-3GP
(R) FC9704
2
SC56P50V2JN-2GP
2
B B
2
SC33P50V2JN-3GP
)566-,7 8&)98
BAT1 LBL1
BATTERY CR2032_30MM LABEL
(23.21221.024) !"#$%&$' (40.3KP03.001)
Wire Length:30mm ()*(+,*-./0"
!"#$%& 1234"&5673)8936#$31:;36$$&"44
A <Core Design> A
'()* 0<-0../.-//.3=>3,<3?3.<@@
+,-+.++.-/+0 0<-0../A-/..3=>3A/3?3B@@
+,-+.+.+-/,. 0<-0...<-//.3=>3,03?3.,-<@@ Wistron Corporation
Title
Dummy Symbol/EMI CAP

A3
vSuperb -1
5 4 3 2 1
5 4 3 2 1
Power Sequence
11,14,17,51 VR_READY R3617 1 2 0R0402-PAD SYS_PWROK 17
BAS16-1-GP
1
1
C3605
R3614
CRB : 1K
SCD01U50V2KX-1GP
(R)
2
D 3 D
17,24,28,46,47,51,54,55 PM_SLP_S3#
2
D3601
(83.00016.K11)
ANNIE Run Power 5V_A 5V_S0 5V_A
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
DCBATOUT U3601 EC3601 EC3602
Q3602 C3603 1 S D 8
2
PMBS3906-GP SCD1U25V3KX-GP 2 S D 7 (R) (R)
1 2 RUNPWR_R1 2 3 (84.T3906.E11) RUNPWR_R3 1 2 3 S D 6 5V_S0
R3603 47KR2J-2-GP 1 4 G D 5
1
(R)
R3606 R3607 R3618 AO4468L-GP 3D3V_S5
1
1 2 RUNPWR_R2 47KR2J-2-GP 1KR2J-1-GP C3601 1 2

C R3620 C
2
R3604 330KR2J-L1-GP 0R0402-PAD
SCD1U50V3KX-GP
1 2 SB:must to be
2
2
3D3V_A
closed U3604
1
1
1 R3616 2 PS_S3CNTRL 47
R3605 1KR2J-1-GP 100KR2J-1-GP
RUNPWR_R5 U3603
100KR2J-1-GP 1 S D 8
2 S D 7
D
3 S D 6
2
4 G D 5 Q3611
3D3V_S0
RUNPWR_R4
2N7002K-2-GP
AO4468L-GP (84.2N702.J31)
Add R3620 and R3621 for
RUN_EN
discharge S5->S0
R3621
S
G
R3601 1 2
17,24,28,46,47,51,54,55 PM_SLP_S3# 1 2 RUNPWR_R6 1D5V_S3
4K7R2J-2-GP 1KR2J-1-GP 17,24,28,46,47,51,54,55 PM_SLP_S3#

D
U3602
Q3603 1 S D 8
Q3601 2N7002KDW-GP 2 S D 7
G 2N7002-11-GP (75.27002.F7C) 3 S D 6
24 SIO_PSON_N
(R84.2N702.J31) 4 G D 5
1D5V_S0 SB modify part number
1
3
S
AO4468L-GP 1D5V_S0
1
MAX Current 3000 mA
C3604
SCD01U50V2KX-1GP 2 Design Current 2100 mA
Total= 11.39A
B B
EUP Power 5V_A
U3604
C3607 1 S D 8
SCD1U25V3KX-GP 2 S D 7
1 2 3 S D 6
(R) 4 G D 5
DCBATOUT
Q3604 AO4468L-GP
PMBS3906-GP R3619 5V_S5
1 2 EUP_R1 2 3(84.T3906.E11) EUP_R3 1 2
R3608 47KR2J-2-GP 0R0402-PAD
1
R3611 R3612
1
1 2 EUP_R2 47KR2J-2-GP 1KR2J-1-GP C3602

2
R3609 330KR2J-L1-GP 3D3V_A

SCD1U50V3KX-GP
2
EUP_EN
1
1
R3610 U3605 ID=7A

100KR2J-1-GP 1 D D 6
2 D D 5
3 G S 4
EUP_R5
2 EUP_R4
AO6402A-GP
3D3V_S5
R3602
24 CTRL0_EUP 1 2 EUP_R6
1
A A
4K7R2J-2-GP C3606
6
SCD01U50V2KX-1GP <Core Design>

2
Q3605
2N7002KDW-GP
(75.27002.F7C)
Wistron Corporation
1

Title
Run Power / Sequence

Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
Close to CPU
S3 Power Reduction Circuit Processor VREF_DQ Implementation
R3707
0R2J-2-GP 3D3V_S0
1 2
DDR_VREF_S3 (R)
1
R3712
S (R) 10KR2J-3-GP
+V_SM_VREF_CNT 11
D D
2
D R3711
2
R3705 0D75V_EN_C 1 2 0D75V_EN 53
G 100KR2J-1-GP 0R0402-PAD
Q3708 2 1
1
2N7002K-2-GP 17,24,28,46,47,51,54,55 PM_SLP_S3#
1
(84.2N702.J31) R3716 (R) C3705
0R2J-2-GP (R) SCD1U10V2KX-5GP
2
PM_SLP_S3# 17,24,28,46,47,51,54,55
5 S3 Power Reduction X01 20091111 JE40 HR modify !"R3710#

#$
C
Close to DIMM C
S3 Power Reduction Circuit SM_DRAMPWROK
0D75V_S0 DRAMRST_CNTRL_PCH 17,47
16 DDR_W R_VREF01_D1 M_VREF_DQ_DIMM0_C 13

1
1
R3703
22R2J-2-GP R3714 Q3709 R3708
0R2J-2-GP
2N7002KDW-GP
0R2J-2-GP
0D75V_S0_C (R) (R)
2
2
DDR_W R_VREF01_B4 15
D
13 M_VREF_DQ_DIMM1_C
Q3701
17,47 DRAMRST_CNTRL_PCH (75.27002.F7C)
2N7002K-2-GP
(84.2N702.J31)
Close to CPU
G
S3 Power Reduction Circuit SM_DRAMPWROK

1D5V_S3
46 PS_S3CNTRL
1
B R3706 B
R3709 1KR2J-1-GP
0R2J-2-GP
(R)
2
1 2
S3 Power Reduction Circuit

SM_DRAMRST#
13 SM_DRAMRST# S
R3718
D SM_DRAMRST#_D 1 2 DDR3_DRAMRST# 15,16
1KR2J-1-GP
1
G
(R) C3702
Q3703 SC100P50V2JN-3GP
2
2N7002K-2-GP SB to -1
(84.2N702.J31)
DRAMRST_CNTRL_PCH 17,47
C3703
2 1DRAMRST_CNTRL_PCH
SCD047U16V2KX-1-GP
A <Core Design> A
Wistron Corporation
Title
ADAPTER OCP
SM_DRAMPWROK must have a maximum of 15ns rise or fall time Size Document Number Rev
A3
over VDDQ * 0.55± 200mV and the edge must be monotonic vSuperb -1
5 4 3 2 1
5 4 3 2 1
ANNIE solution
D
!"##$%&'()** D
DCIN1 AD_JK_S
4 BT+
1 !"#$%&$%'()**+',-./01'2)//'3)'4,56
2 UPS1
3 11
2
PC3803 1
K
SCD1U50V3KX-GP
5
CHASSIS
6 D3803 2
CHASSIS
1
P6SBMJ24APT-GP 3
NP1 (83.P6SMB.HAG) RN7 4
1 4 BAT_SCL_N 5
24,49 BAT_SCL
1
DC-JACK200-GP-U C50 C51 2 3 BAT_SDA_N 6
24,49 BAT_SDA
SCD1U25V2KX-GP
SCD1U25V2KX-GP
7
(22.10261.211) 8
2
SRN33J-5-GP-U 9
10
12
ACES-CON10-51-GP
C C
!"#$%&!'(#$)*+&,-
B B
AD_JK_S ADP+
PU3802
1 S D 8
2 S D 7
3 S D 6
PWR_AD+_2 4 G D 5
1
AO4407AL-GP (R) PR3809

2
20KR2J-L2-GP
PR3807
1
200KR2F-L-GP
2
PC3805
SC1U50V5ZY-1-GP-U
1
2
1
PR3808
<Core Design>
100KR2J-1-GP
A A
Wistron Corporation
2

Title
DCIN JACK
B
vSuperb -1
5 4 3 2 1
5 4 3 2 1
BATTERY CHARGER
ADP+ DCBATOUT
ADP_SYS_R PR34
D01R3721F-GP-U
PQ8
8 D S 1 1 2
D D
7 D S 2
1
6 D S 3
1
5 D G 4 PR277
R255 100KR2F-L1-GP
1
2R2F-GP
1
PR4423 SI7121DN-T1-GE3-GP
2
10KR2F-2-GP AD+_G_1 PG12 PG11 ADP+
2
AD+_IN_R GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
2
1
1
DC_IN_D
C9667
2
SC2D2U25V5KX-1GP PR278 PQ13
PQ4401
2
10KR2F-2-GP PR95 SI7121DN-T1-GE3-GP

3 4 ADP+ PC45 0R0402-PAD
2
1 2
PWR_CHG_ACOK 2 5 1 S D 8
24 PWR_CHG_ACOK
1
SCD1U25V2KX-GP 2 S D 7
SCD1U25V2KX-GP
1
1 6 AD+_G_2 PC47 3 S D 6
PC46 PWR_ADP_CTRL 4 G D 5
2
2N7002KDW-GP
1
PR266 R218 SCD1U25V2KX-GP
(75.27002.F7C) 430KR2F-GP 10R6F-1-GP PR4411
470KR2J-2-GP
PWR_CHG_ACN
PWR_CHG_ACP
+,-./011#2"334#5%6%7%
2
1
1
1
PC344 PC343
PC341
SC10U25V6KX-1GP
SC10U25V6KX-1GP
2
2
1
SC1U25V5KX-1GP
2
1
PR267 PR39
5
6
7
8
66K5R2F-GP PC4410 1 2
D
D
D
D
SCD01U50V2KX-1GP PU14 0R3J-0-U-GP PWR_CHG_BTST_R
2
PQ11
ACP
ACN
2
PWR_CHG_VCC 20 SI4128DY-T1-GE3-GP
VCC A K
PD3
CYNTEC. 6.8uH , 7*7*3 Pre-Charger Current =0.2A
1
6 17 DCR: 43.9~50mOhm
G
S
S
S
PWR_CHG_ACDET PWR_CHG_BTST SD103AWS-1-GP
ACDET BTST
Charger Current= 1A
1
C PC320 C
4
3
2
1
PWR_CHG_CMPOUT PC229 Idc : 4.5 A , Isat : 6A
2
16 PWR_CHG_REGN SC1U25V5KX-1GP SCD1U50V5KX-1GP
2
1
1
PR4402 REGN
PR270 3 BT+
10KR2F-2-GP 3D3MR2J-GP CMPOUT 18 PWR_CHG_HIDRV PL4105
HIDRV PR38
4 1 2 1 2
2
2
PWR_CHG_CMPIN CMPIN 19 PWR_CHG_PHASE
PHASE D01R3721F-GP-U
COIL-6D8UH-10-GP
1
2 1 PWR_CHG_SCL
24,48 BAT_SCL
PG4408 GAP-CLOSE-PWR-3-GP 9 15 PWR_CHG_LODRV C9668 C9665
SCL LODRV
5
6
7
8
SC10U25V6KX-1GP
SC10U25V6KX-1GP
2
2
D
D
D
D
2 1 PWR_CHG_SDA
24,48 BAT_SDA
1
PG4409 GAP-CLOSE-PWR-3-GP 8 PQ12 PR47
SDA 2D2R6J-3-GP PG10 PG9
SI4128DY-T1-GE3-GP (R) GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
2
1
13 PWR_CHG_SRP
PWR_CHG_SNB
2
10 SRP
G
S
S
S
PR273 PR272 PWR_CHG_ILIM
10KR2F-2-GP 10KR2F-2-GP ILIM 12 PWR_CHG_SRN
4
3
2
1
SRN
11 PC43
2
NC#11 1 2
Battery spec (3S1P)
1
!"#$%%&#'()*() PC48 SCD1U25V2KX-GP PC44
3D3V_AUX_S5 SCD1U25V2KX-GP SCD1U25V2KX-GP
5 7 PWR_CHG_IOUT Voltage of Max charge : 12.6V
2
ACOK# IOUT
1
3D3V_AUX_S5
Normal Capacity:2150mA/h
GND
GND
PC49
1
SC1KP50V3KX-GP Max continue charge current : 1.075A
2
1
BQ24727RGRR-1-GP PC345 (R)
21
14
1
PR269 SC100P50V2JN-3GP
2
316KR2F-GP PR274
10KR2F-2-GP
2
Idc=[(Vin-Vo) Vo] / L*Fsw*Vin

2
PWR_CHG_SRP 1 2 SRP_1
1
PR7943
B
PR271
100KR2F-L1-GP 24 AC_IN#
10R2F-L-GP
=[(19-12.6) 12.6]/ 6.8*750*19 B
PWR_CHG_SRN 1 2 SRN_1
AC adapter detect current : PR7942 =0.833A
2
7D5R2F-GP
PWR_CHG_IOUT
Ac input current = 20 x ( Vacp - Vacn ) / 10mohm
R1 = PR279 // PR275
!"!#$%&'()*)+$'+$&* R3
1
PR279 PR275
64K9R2F-1-GP 97K6R2F-GP
R1 AD+ total power R1 R2 R3 GPIO
!"#$%&$'()*++,(-..(-.-/0*1(+23240(4*501*3(
D
2
PQ4408 ADAPTOR_SEL_4 90W 39.2K 100K 64.9K High
2N7002K-2-GP
84.2N702.J31
D
DCBATOUT 135W 97.6K 100K Low
2ND = 84.2N702.031 Q21
R128 (84.2N702.J31)
PMBS3906-GP
1 2 SEL_DCBATOUT 2 3 ADAPTOR_SEL_2 2 1ADAPTOR_SEL_CTRL G 2N7002-11-GP
S
R122 47KR2J-2-GP Q53

1
(84.T3906.E11) 0R0402-PAD
adapter 90W
S
AC_Protect 1 2 PWR_CHG_CMPOUT R124 R125
1
PR4414 1 2 SEL_DCBATOUT_C 47KR2J-2-GP 1KR2J-1-GP C45 PWR_CHG_CMPIN AC mode (default:120% ):

2
0R0402-PAD R123 330KR2J-L1-GP (63.10334.1DL) SCD1U50V3KX-GP

set up the value by PR275 and PR276
1
2
PR276
1
1
3D3V_AUX_S5 R126 R2 100KR2F-L1-GP
100KR2J-1-GP
2
1
ADAPTOR_SEL_3
2
PR4430
100KR2J-1-GP
ADAPTOR_SEL_1
2
R127
17 ADAPTOR_SEL ADAPTOR_SEL 1 2 ADAPTOR_SEL_C !"#$%&
A PWR_CHG_ACOK A
4K7R2J-2-GP '()*++,*-.*/0-123/4'5167*-1/.((6
6
!"# Q24 !"#$%&14

D
2N7002KDW-GP
PQ4406
2N7002K-2-GP
(75.27002.F7C)
.43)++,*-./'2586*9%*4'516*:;9<:$*&=*>0?@ <Core Design>
1
84.2N702.J31
2ND = 84.2N702.031 Wistron Corporation
S
Title
BATTERY CHARGER
AC_IN# Size Document Number Rev
Custom
vSuperb -1
5 4 3 2 1
A B C D E
DCBATOUT PWR_3_5V_DCBATOUT 3D3V_PWR 3D3V_A
0R0805-PAD 2 1 PR2229
PR2227 1 2 0R0805-PAD
0R0805-PAD 2 1 PR2230
PR2228 1 2 0R0805-PAD
0R0805-PAD 2 1 PR2231
4
3D3V_PWR / 5V_PWR DCBATOUT
PR2233 1
PWR_3_5V_DCBATOUT
2 0R0805-PAD
4
PR2234 1 2 0R0805-PAD
PR2235 1 2 0R0805-PAD
84.04128.037 SI4128
Vgs @ 4.5V, 84.00172.A37 SIR172ADP
PWR_3_5V_DCBATOUT
VIN RIPPLE CURRENT Imax=1.6A Id = 9.7A, Vgs @ 4.5V, VIN RIPPLE CURRENT Imax=4.9A PWR_3_5V_DCBATOUT
Rds(on) = 24.0~30.0mohm, Id = 24A, 5V_PWR 5V_A

PWR_3_5V_DCBATOUT
Qg = 3.8~6.0nC Rds(on) = 8.5~10.5mohm, PR2236 1 2 0R0805-PAD
1
PC4146 PC4147 PC4140 PC4142 PC4138 PC4157 PC4143 PC4158 PC4145 PC4144 PR2237 1 2 0R0805-PAD
1
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U25V3KX-GP
84.SRA12.037 SIRA12DP PR2238 1 2 0R0805-PAD
8
7
6
5
5
6
7
8
SCD1U25V3KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
84.04712.A37 SI4712 PR4130
Vgs @ 4.5V,
2
D
D
D
D
D
D
D
D
PU4103 PU4108 PR2239 1 2 0R0805-PAD
SI4128DY-T1-GE3-GP
Vgs @ 4.5V, 2D2R5F-2-GP Id = 20A,
Id = 12.9A,
SIR172ADP-T1-GE3-GP
PR2240 1 2 0R0805-PAD
Rds(on) = 4.4~6.0mohm,
Rds(on) = 13.0~16.5mohm,
2
3_5_VIN PC4114 4 PR2241 1 2 0R0805-PAD
G
Qg = 8.3~12.5nC
SCD01U50V2KX-1GP
S
S
S
S
S
S
G
1
PR2242 1 2 0R0805-PAD
1
2
3
4
3
2
1
12
!"#$%&!"'()**+',--')./'*0)12'3,-
2
RIPPLE CURRENT=2.4A PWR_3D3V_UGATE2_R 1
PR2174
2 PWR_3D3V_UGATE2
PU5303
PWR_5V_UGATE1 1
PR2175
2PWR_5V_UGATE1_R
VIN
Iomax=5A
2D2R5J-1-GP 2D2R5J-1-GP
RIPPLE CURRENT=8.2A Iomax=11A
PR2177 PR2176
OCP>8.75A 2 1 PWR_3D3V_BOOT1 1 2PWR_3D3V_BOOT2 9
VBST2 VBST1
17 PWR_5V_BOOT1 1 2PWR_5V_BOOT1_1 1 2 OCP>18.7A
3D3V_PWR
3.3uH, DCR=10.8mohm, Idc=10.0A 2D2R5J-1-GP 2D2R5J-1-GP PC4154 1.5uH, DCR=3.8mohm, Idc=16A
PC4116 SCD1U25V3KX-GP PWR_3D3V_UGATE2 10 16 PWR_5V_UGATE1 SCD1U25V3KX-GP 5V_PWR
DRVH2 DRVH1 PL4103
1 2PL4104 PWR_3D3V_PHASE2 8 18 PWR_5V_PHASE1 1 2
SW2 SW1 IND-1D5UH-52-GP
3 PT4106 (R) IND-3D3UH-135-GP PWR_3D3V_LGATE2 11 15 PWR_5V_LGATE1 3
DRVL2 DRVL1
1
(77.22271.27L) PC4139 PC4150 PG4127 PT4104 PT4105
1
SC10U6D3V5KX-1GP
SCD1U50V3KX-GP
(R) (77.22271.27L) (77.22271.27L)
5
6
7
8
1
ST220U6D3VDM-23-GP
GAP-CLOSE-PWR-3-GP
14 PWR_5V_VOUT1 PG4126 PC4149 PC4141

VO1
2
8
7
6
5
1
D
D
D
D
ST220U6D3VDM-23-GP
ST220U6D3VDM-23-GP
GAP-CLOSE-PWR-3-GP
SCD1U50V3KX-GP
SC10U6D3V5KX-1GP
2
D
D
D
D
PU4110 PWR_3D3V_FB2 4 2 PWR_5V_FB1 PQ18
VFB2 VFB1
2
SIRA12DP-T1-GE3-GP
2
2
SI4712DY-T1-GE3-GP PR7911 PR7912 4
G
1 2 6 20 1 2
S
S
S
3D3V_AUX_S5 PWR_3D3V_ENC PWR_5V_ENC 3D3V_AUX_S5
EN2 EN1
S
S
S
G
3
2
1
0R0402-PAD 0R0402-PAD
1
2
3
4
220uF/6.3V, ESR=25mohm PWR_3D3V_CS2 5 1 PWR_5V_CS1
CS2 CS1
PWR_3D3V_FB2_O
19 220uF/6.3V, ESR=25mohm
3D3V_PWR VCLK
3V_5V_POK 7 21
PGOOD GND Vo Pin trace need in
PWR_5V_FB2
VREG3
VREG5
PR4134
100KR2J-1-GP
(R)
depend to connect with
(R) TPS51225CRUKR-GP
Vout by layout
13
1
PR4139
PR4120 0R2J-2-GP 3D3V_AUX_S5 5V_AUX_S5
PWR_5V3D3V_VREG3
PWR_5V3D3V_VREG5
6K65R2F-GP PG4128 PG4125
1 2 1 2
!"#$%&!%'()**+',-.-/-'012'134
1
(R)
2
1 2
PWR_3D3V_FB2_R GAP-CLOSE-PWR GAP-CLOSE-PWR PR4137
1
PC4152 (R) 0R2J-2-GP
SC18P50V2JN-1-GP PR4144
30K9R2F-GP
2
1 2
PWR_5V_FB1_R
(R)
2
1
PC4148
1
PR4135 PC4153 SC18P50V2JN-1-GP
2
10KR2F-2-GP PC4156 Frequency 300k/CH1
SC10U6D3V3MX-GP
SC4D7U25V5KX-GP 350k/CH2
1
2
2 2
PR4121
20KR2F-L-GP
2
3.3V(TPS51225)
L=3.3uH
∆I={(Vin-Vout)*Vout}/(Vin*L*Fsw)
OCP !"#!$"%$#&
'()*+,-./-0!1 5V(TPS51225)
∆I={(19 - 3)*3}/(19*3u*350K)=2.36A PR7922
L=1.5uH
PWR_5V_CS1 1 2
∆I={(Vin-Vout)*Vout}/(Vin*L*Fsw)
(R) 59KR2F-GP ∆I={(19 - 5)*5}/(19*1.5u*300K)=8.2A
1
PC4151
SC18P50V2JN-1-GP
2
Remove EUP CTRL
PR4117
PWR_3D3V_CS2 1 2
1
(R)
PC4110 80K6R2F-GP
TONSEL CH1 CH2
SC18P50V2JN-1-GP
(64.11035.6DL)
2
GND 200kHz 250kHz
VREF 300kHz 375kHz
VREG3 or VREG5 400kHz 500kHz
SKIPSEL VREG3 or VREG5 VREF(2V) GND

1 1
Operating OOA Auto Skip Auto Skip
Mode PWM only PWM only
<Core Design>
Wistron Corporation
Title
5V/3D3V(TPS51125)
Custom
vSuperb -1
A B C D E
5 4 3 2 1
VCORE_SW2 VCORE_SW2 52
VCORE_SW1 VCORE_SW1 52
VCORE_BT1 VCORE_BT1 52
VCORE_BT2 VCORE_BT2 52
VCORE_LG1 VCORE_LG1 52
VCORE_HG1 VCORE_HG1 52
VCORE_LG2 VCORE_LG2 52
VCORE_HG2 VCORE_HG2 52
VCORE_ISEN1 VCORE_ISEN1 52
VCORE_ISUMP VCORE_ISUMP 52
VCORE_ISUMN_2 VCORE_ISUMN_2 52
D D
DCBATOUT 5V_S0
!"#$%&'"(%")*
1
P_CPU_VCCIO
PR9 PR25
2D2R5J-1-GP 2D2R5J-1-GP
1
PC144
1
SCD1U16V2KX-3GP R728 R727 PC139
2 1 VCORE_ISUMN_2 130R2F-1-GP 54D9R2F-L1-GP SCD01U50V2KX-1GP
1
1 PC145
2
PC146 SC1U25V3KX-1-GP
2
2 SCD22U25V3KX-GP
2
1 PC141 1 PC17 1 PC16 U39
SCD22U25V3KX-GP
SCD22U25V3KX-GP
SCD22U25V3KX-GP
(R)
2 2 2 VCORE_VDD 16 1 VCORE_SCLK PR31 2 1 0R0402-PAD
VDD SCLK H_VIDSCK_VR 11
31 VCORE_SDIO PR29 2 1 0R0402-PAD H_VIDSOUT_VR 11
23 SDA
VDDP 21 VCORE_LG1
VCORE_VIN 17 LGATE1 19 VCORE_HG1
!"#$%&'"(%"#+, VIN UGATE1 3D3V_S0
P_CPU_VCCIO 24 VCORE_LG2
VCORE_ISEN1 12 LGATE2 26 VCORE_HG2
ISEN1 UGATE2
1
PR14 VCORE_ISEN2 11
NTC-10K-27-GP VCORE_ISEN3 10 ISEN2 30 VCORE_PROG1 PR16 1 2 16K9R2F-GP PR35
ISEN3 PROG1
1
28 VCORE_PROG2 PR17 1 2 49K9R2F-L-GP 10KR2F-2-GP

R729 1 2 PR12 1 2 634R2F-1-GP VCORE_ISUMN 14 PROG2 29 VCORE_PROG3 PR18 1 2 3K24R2F-GP
VCORE_ISUMP 15 ISUMN PROG3
75R2F-2-GP
2
ISUMP
1
3 VCORE_PWRGD
PGOOD VR_READY 11,14,17,46,51
1
1
C 1 2VCORE_ISUMN_1
1 2 VCORE_BT1 18 4 VCORE_IMON C
2
VCORE_ISUMP_1 PC143 PC142 PR11 VCORE_BT2 27 BOOT1 IMON 6 VCORE_NTC

BOOT2 NTC
2
SCD22U16V2KX-GP
SCD1U16V2KX-3GP
1K5R2F-2-GP PC8 7 VCORE_COMP PR3

2
SC2200P50V2KX-2GP COMP
1
PR37 PR13 VCORE_SW1 20 8 VCORE_FP 107KR2F-GP
2
PHASE1 FB
1
2K61R2F-1-GP 11KR2F-L-GP VCORE_SW2 25 9 VCORE_FB2 PR15 1 2 6K04R2F-GP PC1
PHASE2 SLOPE
SC1KP50V2KX-1GP
1 2 13 VSS_SENSE PR1 PR2
2
VCORE_EN_N PR28 1 2 0R0402-PAD VCORE_EN 2 RTN 22 VCORE_PWM3 PR7 1 2 0R0402-PAD PR6 PR5 PR36 PR4 PC2 NTC-470K-9-GP 27K4R2F-GP
5V_S0
1
VR_ON PWM3
SC56P50V2JN-2GP
5 1KR2F-3-GP 1K87R2F-GP 2KR2F-3-GP 4K02R2F-GP
2
VR_HOT#
1
PC140
VCORE_FB_2
2
11 H_VIDALERT_N_VR PR30 1 2 0R0402-PAD VCORE_ALERT# 32 33 2 1VCORE_FB2 SC1U25V3KX-1-GP
2
ALERT# GND PR10 (R) VCORE_NTC_1
2
1
0R2J-2-GP
1
1
VCORE_COMP_12
VCORE_FB_1
C775 PR67 ISL95812HRZ-T-GP (R)
SC47P50V2JN-3GP 1KR2F-3-GP
1
(R) PR8
2
PC5 3K83R2F-GP
2
!"#$%&'$(%$))*+
SC390P50V2KX-GP
2
2
1
1
PC4 PC3
SC3300P50V2KX-1GP
SC330P50V2KX-3GP
2
2
VCC_SENSE
B VCC_CORE !"#$%&'"(%"#+, B
3D3V_S5 3D3V_S0
!"#$%&!"'()**+',--'.(/'01,234'5+657+8
1
R53
2
R722
100R2F-L1-GP-U R14 1 2 VCORE_EN_N
10KR2J-3-GP
2
22KR2J-GP
1
11 VCC_SENSE VCC_SENSE
11 VSS_SENSE VSS_SENSE Q35
1 6
1
R13 1 210KR2J-3-GP VRM_EN_1 2

17,24,28,46,47,54,55 PM_SLP_S3#
1
R739 PC6 (R) PC7 (R) 5 VRM_EN_3 R15 1 2 10KR2J-3-GP

100R2F-L1-GP-U SCD01U50V2KX-1GP SCD01U50V2KX-1GP VCORE_EN_N 3 4
2
MBT3904DW1T1G-2-GP
2
(75.03904.A7C)
VRM_EN_2
Q36 (R)
1 6 VRM_EN_6 R58 1 2 100R2J-2-GP
H_PWRGD 11,17
R16 1 2 VRM_EN_4 2
10KR2J-3-GP 5 VRM_EN_7 R17 1 2 10KR2J-3-GP
R19 1 2 VRM_EN_5 3 4
11,14,17,46,51 VR_READY
100R2J-2-GP
MBT3904DW1T1G-2-GP
(75.03904.A7C)
A A
<Core Design>
Wistron Corporation
Title
CPU VCORE_ISL95812(1/2)
C -1
Tuesday, October 08, 2013
vSuperb
Date: Sheet 51 of 55
5 4 3 2 1
5 4 3 2 1
P_DCBATOUT_VCORE DCBATOUT
D D
AB'""8C&'=!C11D:68C&=4E
)0?1F1B'()>1 PR40 1 2 0R0805-PAD
PR41 1 2 0R0805-PAD
:;171&B=>1
1
PC149 PC150 PC19 PC20 PC21 PC22 PR42 1 2 0R0805-PAD
6;?G+HI171A'(98"'(-+,->1 SCD1U50V3KX-GP SC10U25V5KX-GP SCD1U50V3KX-GP SC10U25V5KX-GP SC10U25V5KX-GP SC10U25V5KX-GP PR43 1 2 0R0805-PAD
(R) (R)
2
AB'D6=8&'"!C111D:6=8&4E
5
6
7
8
5
6
7
8
D
D
D
D
D
D
D
D
)0?1F1B'()>1 Q76 Q77
:;171&(=>1 SIR172ADP-T1-GE3-GP SIR172ADP-T1-GE3-GP
6;?G+HI171B'B92'"-+,->1 ./0'1"'!2#31
4 4
G
45678'"(98'&-+,-
S
S
S
S
S
S
:;<7!"=>1:?/@72"=
3
2
1
3
2
1
PR44 PL1 VCC_CORE
0R0805-PAD IND-D36UH-19-GP
1 2 VCORE_HG1_1 VCORE_HG1_1
51 VCORE_HG1
1 2
!!"#$%&'()%*+,-
PR57
1
2D2R5J-1-GP
51 VCORE_BT1 VCORE_BT1 1 2VCORE_BT_1 PR45
2
22KR2J-GP TC6 TC3 TC4 TC5
1
PG1 PG2
5
6
7
8
5
6
7
8
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
ST330U2D5VDM-9GP
ST330U2D5VDM-9GP
ST330U2D5VDM-9GP
ST330U2D5VDM-9GP
1 PC148 Q78 Q79
D
D
D
D
D
D
D
D
SCD22U25V3KX-GP PR46
2
2 SIRA12DP-T1-GE3-GP SIRA12DP-T1-GE3-GP 2D2R6J-3-GP
2 VCORE_SNB1
VCORE_ISUMN1
4 4
G
S
S
S
S
S
S
51 VCORE_SW1
51 VCORE_LG1
3
2
1
3
2
1
1
PC30
SC1500P50V3KX-GP
C PR19 1 2 10R2F-L-GP VCORE_ISUMN_2 VCORE_ISUMN_2 51,52 C
2
PR20 1 2 10KR2F-2-GP VCORE_ISEN2
VCORE_ISUMP1
VCORE_ISEN2 51,52
PR21 1 2 10KR2F-2-GP VCORE_ISEN3 VCORE_ISEN3 51,52
(R)
PR22 1 2 3K65R5F-GP VCORE_ISUMP VCORE_ISUMP 51,52

AB'""8C&'=!C11D:68C&=4E
)0?1F1B'()>1
P_DCBATOUT_VCORE !""#"$%&
:;171&B=>1
'()*+,-../0123*45-.67489
1
6;?G+HI171A'(98"'(-+,->1 PC151 PC152 PC158 PC23 PC24 PC25 PC26
SCD1U50V3KX-GP SC10U25V5KX-GP SC10U25V5KX-GP SCD1U50V3KX-GP SC10U25V5KX-GP SC10U25V5KX-GP SC10U25V5KX-GP
AB'D6=8&'"!C111D:6=8&4E (R) (R) (R)
'()*+:-../0123*75-.6;489
2
5
6
7
8
5
6
7
8
D
D
D
D
D
D
D
D
)0?1F1B'()>1 Q80
:;171&(=>1 SIR172ADP-T1-GE3-GP Q81
6;?G+HI171B'B92'"-+,->1
4 4 SIR172ADP-T1-GE3-GP
G
G
./0'1"'!2#31
S
S
S
S
S
S
45678'"(98'&-+,- VCC_CORE
3
2
1
3
2
1
:;<7!"=>1:?/@72"=
PR48 PL2
1R5J-2-GP IND-D36UH-19-GP
51 VCORE_HG2 1 2 VCORE_HG2_1 VCORE_HG2_1
PR55 1 2
2D2R5J-1-GP
1
VCORE_BT2 1 2VCORE_BT2_1
51 VCORE_BT2
2
PR49
22KR2J-GP PG4 PG5
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 PC147
5
6
7
8
5
6
7
8
B B
SCD22U25V3KX-GP Q82 Q83
2
1
D
D
D
D
D
D
D
D
2 PR50
SIRA12DP-T1-GE3-GP SIRA12DP-T1-GE3-GP 2D2R6J-3-GP
2 VCORE_SNB2
VCORE_ISUMN2
51 VCORE_SW2
4 4
G
51 VCORE_LG2
S
S
S
S
S
S
3
2
1
3
2
1
PC32 PR24 1 2 10R2F-L-GP VCORE_ISUMN_2 VCORE_ISUMN_2 51,52

SC1500P50V3KX-GP PR26 1 2 10KR2F-2-GP VCORE_ISEN1
VCORE_ISEN1 51,52
PR27 1 2 10KR2F-2-GP VCORE_ISEN3
VCORE_ISUMP2
VCORE_ISEN3 51,52
2
(R)
PR32 1 2 3K65R5F-GP VCORE_ISUMP VCORE_ISUMP 51,52

A A
<Core Design>
Wistron Corporation
Title
CPU VCORE_ISL95812(2/2)
C -1
Tuesday, October 08, 2013
vSuperb
Date: Sheet 52 of 55
5 4 3 2 1
5 4 3 2 1
DCBATOUT PWR_DCBATOUT_1D5V 1D5V_DDR 1D5V_S3
PR4344 1 2 0R0805-PAD PR4347 1 2 0R0805-PAD
PR4345 1 2 0R0805-PAD PR4348 1 2 0R0805-PAD
PR4346 1 2 0R0805-PAD PR4349 1 2 0R0805-PAD
PR4350 1 2 0R0805-PAD
TPS51116 for 1D5V PR4351 1
PR4352 1
2 0R0805-PAD
2 0R0805-PAD
84.00172.A37 SIR172ADP
Vgs @ 4.5V, PR4353 1 2 0R0805-PAD
D Id = 24A, D
PR4604 PR4354 1 2 0R0805-PAD
PWR_1D5V_VCC5 2 1 Rds(on) = 8.5~10.5mohm,
5V_S5
5D1R2F-GP PR4355 1 2 0R0805-PAD
1
PC4606 PR7931 1 2 0R0805-PAD
SC1U10V2KX-1GP 84.SRA12.037 SIRA12DP
Vgs @ 4.5V,
2
PWR_DCBATOUT_1D5V
(R)
VIN RIPPLE CURRENT Imax=4.9A
1
PC4602
SC1KP50V2KX-1GP
PR4603 Id = 20A,
Rds(on) = 4.4~6.0mohm,
7K15R2F-L-GP
2
PWR_1D5V_VDDP 1 PR4605 2
5V_S5
1
0R0603-PAD PC4623 PC4618 PC4616 PC4617 PC4615
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U25V3KX-GP
PC4620
2
SC1U10V2KX-1GP
5
6
7
8
PWR_1D5V_CS
D
D
D
D
PU4602
SIR172ADP-T1-GE3-GP
4
S
S
S
16
14
15
PU4601
3
2
1
PC4609
VDDP
VDDP
ILIM
PR4633
22 PWR_1D5V_BOOT 1 2 1
PWR_1D5V_BOOT_1 2
13 BST
PGD 2D2R5J-1-GP SCD1U25V3KX-GP
PR4617 Vout RIPPLE CURRENT Imax=4A Iomax=18A
12
NC#12 DH
21 PWR_1D5V_UGATE PWR_1D5V_UGATE 1 2PWR_1D5V_UGATE_R OCP>30.6A
PWR_1D5V_EN 11 2D2R5J-1-GP 0.88uH, DCR=2.7~3.0mohm, Idc=20A 1D5V_DDR
EN/PSV
PWR_0D75V_EN 10 20 PWR_1D5V_PHASE PL7 1 2 IND-D88UH-10-GP
VTTEN LX
1
C 1D5V_S3 PR4341 1 2 0R0805-PAD PWR_1D5V_VTTIN 23 C
VTTIN
Close to pin23
1
19 PWR_1D5V_LGATE PR4616
DL
1
PC4603 7 2D2R5J-1-GP PC4613 PTC13 PTC12
NC#7
5
6
7
8
5
6
7
8
SC1U16V3KX-5GP
ST330U2D5VDM-9GP
ST330U2D5VDM-9GP
SC10U6D3V5KX-1GP (R)
2
2
1PWR_1D5V_SNB
D
D
D
D
D
D
D
D
2
PR4342 1 18 PQ16 PQ17
PGND2 PGND1
SIRA12DP-T1-GE3-GP
17 SIRA12DP-T1-GE3-GP
1 2 PWR_1D5V_TON 4 PGND1
1D5V_DDR TON 8 PWR_1D5V_TON 4 4
G
VDDQS
S
S
S
S
S
S
GAP-CLOSE-PWR
24 9 PWR_1D5V_FB
DDR_VREF_PWR
3
2
1
3
2
1
VTT FB
1
PC4619
1
2 PR4608 (R) SC1500P50V3KX-GP
VTTS 5V_S5
6 31K6R2F-GP PC4610
2
VCCA SC18P50V2JN-1-GP
Iomax=1.5A VSSA R1 330uF/2.5V, ESR=9.0mohm
GND
2
REF
2
TPS51116RGER-GP-U1
25
Close to output cap pin1, not 5
1
inside of the output cap R2 PR4609
30KR2F-GP
Close to PIN9
1PWR_1D5V_VTTREF
2
DDR_VREF_S3
Vout=0.75*(1+R1/R2)
1 PR4607 2
0R0402-PAD
+0.75VS
Iomax: 1.5A PC4608
SCD033U16V2KX-GP
!"#$%!&'()"#%
2
B
1 2 PWR_1D5V_EN B
17,24,36 PM_SLP_S4# PR4612 0R0402-PAD
1 PR4615 2 PWR_0D75V_EN
47 0D75V_EN
1
0R0402-PAD PC4612
(R) SCD1U10V2KX-5GP
2
0D75V_S0 PR46321 2 0R0805-PAD
DDR_VREF_PWR
!"#$%&'$()*++,(-..(/0-123(+,40-2
R1475 1 2 10KR2J-3-GP PWR_0D75V_EN
56*7(!#$%8(9:;(9<) 3D3V_S5
5V_S5 R1484 1 2 10KR2J-3-GP

1
PC4604 PC4605
(R)
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
R1463
2
6
1 2 0D75V_EN_R 5 2 0D75V_EN_R_C
PCH_1D05V
C1073
Q73
1
10KR2J-3-GP SC1U6D3V2KX-GP
MMDT3904-7-F-1-GP
1
(R)
(75.03904.A7C)
S0 S3 S5 DS
2
H L L L
A A
<Core Design>
Wistron Corporation
Title
1D5V/0D75V(TPS51116)
Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
PCH_VIN_1D5V 1D5V_S3
PCH_1D05V PR7939 1
PR7940 1
2 0R0805-PAD
2 0R0805-PAD
PCH_VIN_1D5V
PR7941 1 2 0R0805-PAD
12V_S0
84.00172.037 SIR172DP
Vgs @ 4.5V,
1
3D3V_S0 PC4626 PC4624
Id = 13.6A, SC10U6D3V3MX-GP SCD1U25V2KX-GP
Rds(on) = 10.3~12.4mohm,
2
1
PR7932
1
100KR2F-L1-GP
PC4629
5
6
7
8
!"#$%&'$()*++,(-../(012%3!!(+*456,*7 SC1U16V3KX-2GP 5A(Imax)
D
D
D
D
PU5304
High Enable PU36
SIR172ADP-T1-GE3-GP
PCH_1D05V_EN 1 6 PR7925
D EN VCC 100R5J-4-GP
D
2 5 PCH_1D05V_DRV 2 1 PCH_1D05V_DRV_1 4 PD=(1.5-1.05)*5=2.25(W)
G
GND DRV
1
PC4625
S
S
S
SCD1U10V2KX-5GP 3 4 PCH_1D05V_SS
FB SS
3
2
1
1
PC4628
1
APL5611ACI-TRG-GP SCD01U25V2KX-3GP
(78.10324.2FL)
2
1
PC4627 PR7927
SCD047U16V2KX-1-GP 10KR2F-2-GP
1D05V_PWR PCH_1D05V
2
PR7926
PCH_1D05V_FB_1 1 2 PR4821 1 2 0R0805-PAD
1 PR149_2
0R0402-PAD
1
PR4822 1 2 0R0805-PAD
1
PC9
1
SC1KP50V2KX-1GP PC10 PR7929 PR7928 PR7930 1 2 0R0805-PAD
(R) 10R2F-L-GP
1 PC73_1
1
7K5R2F-1-GP
PC11 (77.23371.13L)
!"#$%!&'()*+, R1
2
SCD1U25V2KX-GP PT4 PC12
!"##"$%&"'("')
ST330U2D5VDM-9GP
SC150P50V2KX-GP SC4D7U6D3V3KX-GP
2
3D3V_S0
PC13
SCD047U16V2KX-1-GP
2
1
PCH_1D05V_FB
PR4646
100KR2F-L1-GP
1
From SLP_S4 change to SLP_S3--Kai 0327 (R)
2
PR7924
17,24,28,46,47,51,55 PM_SLP_S3#
PR4653 1 2 0R0402-PAD PCH_1D05V_EN R2 24KR2F-GP Vout = 0.8*(1+R1/R2)=0.951V
2
1
PC4637
SCD1U10V2KX-5GP
(R)
2
Add PR4646--Kai 0328
C 1D05V_ME C
(APL5930)
!"#$%"&%$"
'(()*+,-+./+)0123)456657)8794:
5V_A 5V_A 5V_A ME_VIN_3D3V 3D3V_A

1
PC4631
SC1U10V2KX-1GP
1
R9951 2 1
1
R9949 10KR2F-2-GP 0R0805-PAD

10KR2F-2-GP PR7937 PR7938
1
10KR2F-2-GP PC4633 1D05VME_PWR 1D05V_ME
2
SC10U6D3V3MX-GP
Iomax=1A
2
2
PU5305 PD=(3.3-1.05)*1=2.25(W)
PR7933
5 0R0603-PAD
6 VIN#5 4 1 2
R60 1D05V_ME_GD 7 VCNTL VOUT#4 3
PCH_ME5 1 2 PCH_ME5_R 8 POK VOUT#3 2 PWR_5930_FB_M 2 1
9 EN FB 1 PR7936 PC4632 PC4634
C
VIN#9 GND
1
10KR2F-2-GP 3K16R2F-GP SC10U6D3V3MX-GP SC1U10V3ZY-6GP
PCH_ME4 B Q9506
MMBT3904-3-GP
R1
APL5930KAI-TRG-GP
2
1
(84.T3904.K11) (74.05930.B3D) 1 2
PC4630
E
R9950 SC100P50V2JN-3GP
10KR2F-2-GP R2 1
(R)
2
PR7934
2
R9952 10KR2F-2-GP
1KR2J-1-GP
2
Vo(cal.)=1.0528V
Vo=0.8*(1+(R1/R2))
1
B B
PCH_SLP_A
17,42 PCH_SLP_A
3D3V_S5
2
R303
19 PCH_MEPWROK 0R0402-PAD
1
PCH_ME1
3D3V_S5
1
1
1
1D05V_ME R291 R294

R290 SCD1U10V2KX-4GP 5K6R2J-1-GP 33KR2J-3-GP
10KR2F-2-GP (78.10423.2FL)
1
R279
2
Q34 30K1R2F-L-GP 2 1 C226 PCH_MEPWROK

1 6
PCH_SLP_A R287 2 1 10KR2F-2-GP MEPOK1 2 Q33
2
5 MEPOK2 1 6 PCH_ME2
C238 PCH_MEPWROK 3 4 PCH_ME3 2
1
SCD1U10V2KX-4GP 5
1
(78.10423.2FL) MBT3904DW1T1G-2-GP 3 4
1
R280
2
(75.03904.A7C) 301KR2F-1-GP C220 MBT3904DW1T1G-2-GP C225

1
SCD22U6D3V2KX-1GP SC100P50V2JN-3GP
2
(75.03904.A7C)
2
A A
<Core Design>
Wistron Corporation
Title
PCH 1D05V/1D05_ME
Custom
vSuperb -1
5 4 3 2 1
5 4 3 2 1
D D
5V_S5 VIN RIPPLE CURRENT Imax=1.93A DCBATOUT_12V DCBATOUT
PR4335 1 2 0R0805-PAD
PR4334 1 2 0R0805-PAD
A
1
1
PC5313 PC5303 PC5306
PR5303 PD4 SCD1U50V3KX-GP SC10U25V5KX-GP SC10U25V5KX-GP
2D2R5J-1-GP RB551V30-GP
2
(83.R5003.H8H)
K
2
1
PC5312
84.04214.037 SI4214DDY
12V_PWR_VCC
SC1U10V3KX-4GP-U
Vgs @ 4.5V,
2
Id = 5.9A, Iomax=4A
PU5302 Rds(on) = 19.0~23.0mohm, OCP>6A
Qg = 7.1~11nC
12V_PWR_FB 8 6
9 FB VCC 12V_PWR
12V_PWR_VOS
VOS
PR5304 PC5307 10.0uH, DCR=27.5mohm, Idc=6.0A
10 2D2R5J-1-GP SCD1U50V3KX-GP
PGOOD 1 2
12V_PWR_BOOT 1 12V_PWR_BT1 1 2 PL4 IND-10UH-209-GP
BOOT
1
2 12V_PWR_LX 1 2
PR5306 PR5307 LX 3 12V_PWR_UG !"#$%&$'()*++,(-./012(3*(!$$4(*+-*0
UG
1
C 2K61R2F-1-GP 187R2F-GP PC5308 5 4 12V_PWR_LG C

SCD01U16V2KX-3GP 11 GND LG 7 12V_PWR_COMP
GND COMP/EN#
1
(R) PC5302 PC5305
2
D2
D2
D1
D1
1
PU5301 SC10U25V5KX-GP SE100U16VM-20-GP
1
LOW-->Disable
NCP1589AMNTWG-GP-U1 PR5317 SI4214DDY-GP PR5308
2
10KR2F-2-GP PR5305 (75.04214.A71) 2D2R5J-1-GP
112V_PWR_LX1_SNB
HIGH-->Enable 10KR2J-3-GP
2
2
1
2
G2
S2
G1
S1
PC53111 2 SCD22U16V3KX-2-GP PR53091
12V_PWR_CP1 2 3K3R2F-2-GP
PR5319 PR5310
1
2D2R5J-1-GP 10R2F-L-GP
PC53101 2 SC1KP50V2KX-1GP 2 1 12V_PWR_UG12 100uF/16V, ESR=50mohm
!"#!$##$#%
2
&'()*+,-.,#"/ PC5304
12V_PWR_LX SC1500P50V3KX-GP 12V_PWR 12V_S0
2
PR4336 1 2 0R0805-PAD
PC5309 1 2 SCD01U16V2KX-3GP
12V_PWR_FB1 PR53111 2 75R2F-2-GP
PR4337 1 2 0R0805-PAD
R1
PR5313 1 2 2K61R2F-1-GP 12V_PWR_SENSE PR4338 1 2 0R0805-PAD
1
PR5314
187R2F-GP
R2 Vout=0.8*(R1+R2)/R2
!"#!$#!$#0 5V_S5
2
B
#1,2'()*+,3+45(-6)* B
1
PR5320
10KR2J-3-GP Q5301
12V_EN G
2
2N7002A-7-GP
(84.2N702.J31)
S
D
Q5302
PM_SLP_S3# G
17,24,28,46,47,51,54 PM_SLP_S3#
2N7002A-7-GP
(84.2N702.J31)
S
!!"#$%&'%"(%$)"*+,-$%".(%./
A <Core Design> A
Wistron Corporation
Title
12V
Custom
vSuperb -1
5 4 3 2 1

Acer All in One - 13045-1

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5 4 3 2 1

Title Page Title Page

SYSTEM POWER SEQUENCE 4 MINI PCIE ( WLAN/BT) 38

DDR3-SODIMM1 15 BATTERY CHARGER 49

INTEL LAN CLARKVILLE 1217 25 ."#.$!#)#&',#/0121- A#########@

Swift Block Diagram PCB No :13045 INPUTS OUTPUTS

Revision : -1 ADP+ DCBATOUT

DP DP i3-4130T 2.9G 3M SYSTEM DC/DC

FDIx4x2 DMIx4 LDO

Combo Jack 12V_S0 PCH_1D05V

ODD Wistron Corporation

1 Phase Design N-MOS

1 Phase Design 5V_ODD

PWM <Core Design>

SIR4214D*1 12V_S0 Wistron Corporation

System Power Sequence

(for Master) SPI_CLK(T3)

PCIRST1# PLTRST1# PLTRST_SL_N PCIE X16

PWROK2 SUSB# PM_SLP_S3#

CHIP SOCKET or SLOT <Core Design>

2.2k 2.2k ITE8732 10k 10k 10k 10k

4 PCH Strapping Huron River Schematic Checklist Rev.0_7 4

Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm

HSW_PCUDEBUG_7 R791 1 (R) 2 1KR2J-1-GP

THERMAL HSW_PCUDEBUG_8 R792 1 (R) 2 1KR2J-1-GP

HSW_PCUDEBUG_9 R794 1 (R) 2 1KR2J-1-GP

H_PROCHOT_N R266 1 2 0R0402-PAD H_PROCHOT_R_N !"#$%"&%"' HSW_PCUDEBUG_10 R795 1 (R) 2 1KR2J-1-GP

H_THERMTRIP_N R88 1 2 0R0402-PAD CPU_THERMTRIP_N ()**+,-.*.-/.0,1234,5%67,5%8,9+: HSW_PCUDEBUG_11 R798 1 (R) 2 1KR2J-1-GP

B HSW_PCUDEBUG_12 R799 1 (R) 2 1KR2J-1-GP B

!"#$%&'%#(&)*!&+,'' HSW_PCUSTB_0_DP R807 1 (R) 2 1KR2J-1-GP

HSW_PCUSTB_0_DN R808 1 (R) 2 1KR2J-1-GP

HSW_PCUSTB_1_DP R809 1 (R) 2 1KR2J-1-GP

HSW_PCUSTB_1_DN R810 1 (R) 2 1KR2J-1-GP

CPU uLGA (VCORE/XDP)

L2 DDSP_D_TX_DATA0 SCD1U16V2KX-3GP 2 (U)1 C15 DDSP_D_TX_DATA0_N

DMI_RX#3 AB3 DMI_MT_IR_DP1

CPU uLGA (DMI/FDI)

CPU uLGA (DDR)

!"" PCH_1D05V R310 1 2 0R0402-PAD

NCTF TEST PIN: AU40,

CPU Power Capacitor Quantity

VCC_CORE R130 1 (R) 2 10KR2F-2-GP MBT3904DW1T1G-2-GP

C354 C266 C267 C373

CPU uLGA (VCC)

C1515 C1517 M_B_DQ57 183 49

M_B_DQ59 193 DQ58 VSS 55

M_B_DQS7 188 168

13 M_B_DIM0_ODT0 120 ODT0 VSS 178

LPC 24,44 LPC_AD0

PWRGD_3V AT40 INTRUDER# SUSACK# AG41 SUS_WARNB 1 TP176 TPAD28-1-GP-U

Low = Default !"#$%"&%"$

R258 C3416 1 2 499R2F-2-GP

Q51 GND Y PMBS3906-GP

C422 R2392 249R2F-GP (R) SCD1U50V5KX-1GP

(R) (R) EV FOR FUTURE ENGINEERING HDA_SDOUT EDID_RDY R73 1 2 10KR2J-3-GP

#$L"&%#!+ACW+D,P5+7(+M=0NX! USB_WAKE_SLP R557 1 2 10KR2J-3-GP

49 ADAPTOR_SEL C472 2 ENABLE CDELAY 5

#%&&'()+,-./&(0 michael 2012/2/16 SB