TTL-Transistor - Transistor Logic Transistor-Transistor Logic, or TTL, Refers To The Technology For Designing and Fabricating
TTL-Transistor - Transistor Logic Transistor-Transistor Logic, or TTL, Refers To The Technology For Designing and Fabricating
TTL-Transistor - Transistor Logic Transistor-Transistor Logic, or TTL, Refers To The Technology For Designing and Fabricating
Transistor-Transistor Logic, or TTL, refers to the technology for designing and fabricating
digital integrated circuits that employ logic gates consisting primarily of bipolar transistors. It
overcomes the main problem associated with DTL, i.e., lack of speed.
The input to a TTL circuit is always through the emitter(s) of the input transistor, which
exhibits a low input resistance. The base of the input transistor, on the other hand, is connected
to the Vcc line, which causes the input transistor to pass a current of about 1.6 mA when the
input voltage to the emitter(s) is logic '0', i.e., near ground. Letting a TTL input 'float' (left
unconnected) will usually make it go to logic '1', but such a state is vulnerable to stray signals,
which is why it is good practice to connect TTL inputs to Vcc using 1 kohm pull-up resistors.
The most basic TTL circuit has a single output transistor configured as an inverter with its
emitter grounded and its collector tied to Vcc with a pull-up resistor, and with the output taken
from its collector. Most TTL circuits, however, use a totem pole output circuit, which replaces
the pull-up resistor with a Vcc-side transistor sitting on top of the GND-side output transistor.
The emitter of the Vcc-side transistor (whose collector is tied to Vcc) is connected to the
collector of the GND-side transistor (whose emitter is grounded) by a diode. The output is taken
from the collector of the GND-side transistor. Figure 1 shows a basic 2-input TTL NAND gate
with a totem-pole output.
n the TTL NAND gate of Figure 1, applying a logic '1' input voltage to both emitter inputs of T1
reverse-biases both base-emitter junctions, causing current to flow through R1 into the base of
T2, which is driven into saturation. When T2 starts conducting, the stored base charge of T3
dissipates through the T2 collector, driving T3 into cut-off. On the other hand, current flows
into the base of T4, causing it to saturate and pull down the output voltage Vo to logic '0', or
near ground. Also, since T3 is in cut-off, no current will flow from Vcc to the output, keeping it
at logic '0'. Note that T2 always provides complementary inputs to the bases of T3 and T4, such
that T3 and T4 always operate in opposite regions, except during momentary transition between
regions.
On the other hand, applying a logic '0' input voltage to at least one emitter input of T1 will
forward-bias the corresponding base-emitter junction, causing current to flow out of that
emitter. This causes the stored base charge of T2 to discharge through T1, driving T2 into-cut-
off. Now that T2 is in cut-off, current from Vcc will be diverted to the base of T3 through R3,
causing T3 to saturate. On the other hand, the base of T4 will be deprived of current, causing T
to go into cut-off. With T4 in cut-off and T3 in saturation, the output Vo is pulled up to logic '1',
or closer to Vcc.
TTL PARAMETERS-
Characterstics of digital ICs Compare to their performance:-
Input and output voltage wave forms to define propagation delay time- the delay time are
measure between the 50% voltages levels of input and output goes from the stack to the low state
and toLH corresponding to the output making transmission from the low state to the high state.
The propagation delay time of the logic gate is taken as the average of these two delay times.
2. Power dissipation: - this is the amount of power dissipate is an IC. This power is
specified in
milli watts.
3. Figure of merits – the figure of merits of a digital ICs is defined as the product of
speed and power. The speed is specified in terms of propagation delay times
expressed in nano second.
A low value of speed power production is desirable. In a digital circuit if it is desired to high
speed i.e. low propagation delay, then there is a corresponding increase in the power dissipation
Vice versa.