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Digital Experiment File With Logisim

The document describes the operation of multiplexers, demultiplexers, encoders, and decoders through circuit diagrams and truth tables. It examines a 2-to-1 and 4-to-1 multiplexer, 1-to-2 and 1-to-4 demultiplexer, 4-to-2 encoder, and 2-to-4 decoder. The truth tables define the output patterns for each device based on their input and select lines.

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Nandini Seervi
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0% found this document useful (0 votes)
123 views4 pages

Digital Experiment File With Logisim

The document describes the operation of multiplexers, demultiplexers, encoders, and decoders through circuit diagrams and truth tables. It examines a 2-to-1 and 4-to-1 multiplexer, 1-to-2 and 1-to-4 demultiplexer, 4-to-2 encoder, and 2-to-4 decoder. The truth tables define the output patterns for each device based on their input and select lines.

Uploaded by

Nandini Seervi
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
Download as docx, pdf, or txt
Download as docx, pdf, or txt
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NAME KUSUM SEERVI

ROLL NO 216PH016
DATE 23 DECEMBER 2021
NAME OF THE EXPERIMENT MULTIPLEXERS, DEMULTIPLEXERS,
ENCODERS AND DECODERS

AIM: To simulate ad study the operation of a multiplexer, demultiplexer, encoder and decoders used in
digital electronics.

1. Multiplexer:

(a) 2-to-1 multiplexer:

Circuit Diagram:

Truth table:

S I0 I1 Y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

(b) 4-to-1 multiplexer:

Circuit Diagram:

Truth table:

S0 S1 Y
0 0 I0

0 1 I1

1 0 I2

1 1 I3

2.Demultiplexer:

(a) 1-to-2 Demux:

Circuit diagram:

Truth table:

S I D0 D1

0 0 0 0

0 1 1 0

1 0 0 0

1 1 0 1

(b) 1-to-4 Demux:

Circuit diagram:

Truth Table:

I S1 S0 D0 D1 D2 D3

0 0 0 0 0 0 0

0 0 1 0 0 0 0

0 1 0 0 0 0 0

0 1 1 0 0 0 0

1 0 0 1 0 0 0
1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

3. Encoder:

(a) 4-to-2 Encoder:

Circuit Diagram:

Truth table:

Y3 Y2 Y1 A0 A1

0 0 0 0 0

0 0 1 1 0

0 1 0 0 1

1 0 0 1 1

4. DECODER:

(a) 2-to-4 Decoder:

Circuit Diagram:

Truth Table:

I0 I1 D3 D2 D1 D0

0 0 0 0 0 0

1 0 0 0 1 0

0 1 0 1 0 0

1 1 1 0 0 0

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