LT3045

20V, 500mA, Ultralow Noise,

Ultrahigh PSRR Linear Regulator
FEATURES DESCRIPTION
n Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz) The LT®3045 is a high performance low dropout linear
n Ultralow Spot Noise: 2nV/√Hz at 10kHz regulator featuring LTC’s ultralow noise and ultrahigh
n Ultrahigh PSRR: 76dB at 1MHz PSRR architecture for powering noise sensitive applica-
n Output Current: 500mA tions. Designed as a precision current reference followed
n Wide Input Voltage Range: 1.8V to 20V by a high performance voltage buffer, the LT3045 can be
n Single Capacitor Improves Noise and PSRR easily paralleled to further reduce noise, increase output
n 100µA SET Pin Current: ±1% Initial Accuracy
current and spread heat on the PCB.
n Single Resistor Programs Output Voltage
n High Bandwidth: 1MHz The device supplies 500mA at a typical 260mV dropout
n Programmable Current Limit voltage. Operating quiescent current is nominally 2.2mA
n Low Dropout Voltage: 260mV and drops to <<1µA in shutdown. The LT3045’s wide
n Output Voltage Range: 0V to 15V output voltage range (0V to 15V) while maintaining unity-
n Programmable Power Good gain operation provides virtually constant output noise,
n Fast Start-Up Capability PSRR, bandwidth and load regulation, independent of the
n Precision Enable/UVLO programmed output voltage. Additionally, the regulator
n Parallelable for Lower Noise and Higher Current features programmable current limit, fast start-up capa-
n Internal Current Limit with Foldback bility and programmable power good to indicate output
n Minimum Output Capacitor: 10µF Ceramic voltage regulation.
n Reverse-Battery and Reverse-Current Protection
The LT3045 is stable with a minimum 10µF ceramic output
n 12-Lead MSOP and 10-Lead 3mm × 3mm DFN Packages
capacitor. Built-in protection includes reverse-battery
n AEC-Q100 Qualified for Automotive Applications
protection, reverse-current protection, internal current
limit with foldback and thermal limit with hysteresis. The
APPLICATIONS LT3045 is available in thermally enhanced 12-Lead MSOP
n RF Power Supplies: PLLs, VCOs, Mixers, LNAs, PAs and 10-Lead 3mm × 3mm DFN packages.
n Very Low Noise Instrumentation All registered trademarks and trademarks are the property of their respective owners.
n High Speed/High Precision Data Converters
n Medical Applications: Imaging, Diagnostics
n Precision Power Supplies
n Post-Regulator for Switching Supplies

TYPICAL APPLICATION Power Supply Ripple Rejection

120

VIN IN LT3045 110

5V ±5% 100
4.7µF* 100µA
EN/UV – 90

+ VOUT 80
PSRR (dB)

200k OUT 3V 70
PG IOUT(MAX)
OUTS 500mA 60
SET GND ILIM PGFB 10µF 50 VIN = 5V
402k RSET = 30.1k
40 CSET = 4.7µF
30 COUT = 10µF
249Ω IL = 500mA
4.7µF 30.1k 49.9k
*OPTIONAL, SEE 20
APPLICATIONS 10 100 1k 10k 100k 1M 10M
3045 TA01a
INFORMATION FREQUENCY (Hz)
3045 TA01b
Rev. C

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LT3045
ABSOLUTE MAXIMUM RATINGS (Note 1)

IN Pin Voltage..........................................................±22V OUT-to-OUTS Differential (Note 14)........................ ±1.2V

EN/UV Pin Voltage...................................................±22V IN-to-OUT Differential..............................................±22V
IN-to-EN/UV Differential..........................................±22V IN-to-OUTS Differential............................................±22V
PG Pin Voltage (Note 10)................................–0.3V, 22V Output Short-Circuit Duration........................... Indefinite
ILIM Pin Voltage (Note 10)................................–0.3V, 1V Operating Junction Temperature Range (Note 9)
PGFB Pin Voltage (Note 10)............................–0.3V, 22V E-Grade, I-Grade................................ –40°C to 125°C
SET Pin Voltage (Note 10)...............................–0.3V, 16V H-Grade,............................................ –40°C to 150°C
SET Pin Current (Note 7)..................................... ±20mA MP-Grade (Note 15)............................ –55°C to 150°C
OUTS Pin Voltage (Note 10)............................–0.3V, 16V Storage Temperature Range............... –65°C to 150°C
OUTS Pin Current (Note 7).................................. ±20mA Lead Temperature (Soldering, 10 Sec)
OUT Pin Voltage (Note 10)..............................–0.3V, 16V MSE Package .................................................... 300°C

PIN CONFIGURATION
TOP VIEW
TOP VIEW

IN 1 10 OUT IN 1 12 OUT
IN 2 9 OUTS IN 2 11 OUT
11 IN 3 13 10 OUTS
EN/UV 3 GND 8 GND GND
EN/UV 4 9 GND
PG 4 7 SET PG 5 8 SET
ILIM 5 6 PGFB ILIM 6 7 PGFB

MSE PACKAGE
DD PACKAGE
12-LEAD PLASTIC MSOP
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 33°C/W, θJC = 8°C/W
TJMAX = 150°C, θJA = 34°C/W, θJC = 5.5°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3045EDD#PBF LT3045EDD#TRPBF LGYP 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT3045IDD#PBF LT3045IDD#TRPBF LGYP 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT3045HDD#PBF LT3045HDD#TRPBF LGYP 10-Lead (3mm × 3mm) Plastic DFN –40°C to 150°C
LT3045MPDD#PBF LT3045MPDD#TRPBF LYGP 10-Lead (3mm × 3mm) Plastic DFN –55°C to 150°C
LT3045EMSE#PBF LT3045EMSE#TRPBF 3045 12-Lead Plastic MSOP –40°C to 125°C
LT3045IMSE#PBF LT3045IMSE#TRPBF 3045 12-Lead Plastic MSOP –40°C to 125°C
LT3045HMSE#PBF LT3045HMSE#TRPBF 3045 12-Lead Plastic MSOP –40°C to 150°C
AUTOMOTIVE PRODUCTS**
LT3045EMSE#WPBF LT3045EMSE#WTRPBF 3045 12-Lead Plastic MSOP –40°C to 125°C
LT3045IMSE#WPBF LT3045IMSE#WTRPBF 3045 12-Lead Plastic MSOP –40°C to 125°C
LT3045HMSE#WPBF LT3045HMSE#WTRPBF 3045 12-Lead Plastic MSOP –40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. C

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 LT3045
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Voltage Range l 2 20 V
Minimum IN Pin Voltage ILOAD = 500mA, VIN UVLO Rising l 1.78 2 V
(Note 2) VIN UVLO Hysteresis 75 mV
Output Voltage Range VIN > VOUT l 0 15 V
SET Pin Current (ISET) VIN = 2V, ILOAD = 1mA, VOUT = 1.3V 99 100 101 µA
2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 500mA (Note 3) l 98 100 102 µA
Fast Start-Up Set Pin VPGFB = 289mV, VIN = 2.8V, VSET = 1.3V 2 mA
Current
Output Offset Voltage VIN = 2V, ILOAD = 1mA, VOUT = 1.3V –1 1 mV
VOS (VOUT – VSET) 2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 500mA (Note 3) l –2 2 mV
(Note 4)
Line Regulation: ∆ISET VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V l 0.5 ±2 nA/V
Line Regulation: ∆VOS VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V (Note 4) l 0.5 ±3 µV/V
Load Regulation: ∆ISET ILOAD = 1mA to 500mA, VIN = 2V, VOUT = 1.3V 3 nA
Load Regulation: ∆VOS ILOAD = 1mA to 500mA, VIN = 2V, VOUT = 1.3V (Note 4) l 0.1 0.5 mV
Change in ISET with VSET VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA l 30 400 nA
Change in VOS with VSET VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA (Note 4) l 0.03 0.6 mV
Change in ISET with VSET VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA l 150 600 nA
Change in VOS with VSET VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA (Note 4) l 0.3 2 mV
Dropout Voltage ILOAD = 1mA, 50mA 220 275 mV
l 330 mV
ILOAD = 300mA (Note 5) 220 280 mV
l 350 mV
ILOAD = 500mA (Note 5) 260 350 mV
l 450 mV
GND Pin Current ILOAD = 10µA 2.2 mA
VIN = VOUT(NOMINAL) ILOAD = 1mA l 2.4 4 mA
(Note 6) ILOAD = 50mA l 3.5 5.5 mA
ILOAD = 100mA l 4.3 7 mA
ILOAD = 500mA l 15 25 mA
Output Noise Spectral ILOAD = 500mA, Frequency = 10Hz, COUT = 10µF, CSET = 0.47µF, VOUT = 3.3V 500 nV/√Hz
Density (Notes 4, 8) ILOAD = 500mA, Frequency = 10Hz, COUT = 10µF, CSET = 4.7µF, 1.3V ≤ VOUT ≤ 15V 70 nV/√Hz
ILOAD = 500mA, Frequency = 10kHz, COUT = 10µF, CSET = 0.47µF, 1.3V ≤ VOUT ≤ 15V 2 nV/√Hz
ILOAD = 500mA, Frequency = 10kHz, COUT = 10µF, CSET = 0.47µF, 0V ≤ VOUT < 1.3V 5 nV/√Hz
Output RMS Noise ILOAD = 500mA, BW = 10Hz to 100kHz, COUT = 10µF, CSET = 0.47µF, VOUT = 3.3V 2.5 µVRMS
(Notes 4, 8) ILOAD = 500mA, BW = 10Hz to 100kHz, COUT = 10µF, CSET = 4.7µF, 1.3V ≤ VOUT ≤ 15V 0.8 µVRMS
ILOAD = 500mA, BW = 10Hz to 100kHz, COUT = 10µF, CSET = 4.7µF, 0V ≤ VOUT < 1.3V 1.8 µVRMS
Reference Current RMS BW = 10Hz to 100kHz 6 nARMS
Output Noise (Notes 4, 8)
Ripple Rejection VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = 500mA, COUT = 10µF, CSET = 4.7µF 117 dB
1.3V ≤ VOUT ≤ 15V VRIPPLE = 150mVP-P, fRIPPLE = 10kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF 90 dB
VIN – VOUT = 2V (Avg) VRIPPLE = 150mVP-P, fRIPPLE = 100kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF 77 dB
(Notes 4, 8) VRIPPLE = 150mVP-P, fRIPPLE = 1MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF 76 dB
VRIPPLE = 80mVP-P, fRIPPLE = 10MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF 53 dB
Ripple Rejection VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF 104 dB
0V ≤ VOUT < 1.3V VRIPPLE = 50mVP-P, fRIPPLE = 10kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF 85 dB
VIN – VOUT = 2V (Avg) VRIPPLE = 50mVP-P, fRIPPLE = 100kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF 72 dB
(Notes 4, 8) VRIPPLE = 50mVP-P, fRIPPLE = 1MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF 64 dB
VRIPPLE = 50mVP-P, fRIPPLE = 10MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF 54 dB
EN/UV Pin Threshold EN/UV Trip Point Rising (Turn-On), VIN = 2V l 1.18 1.24 1.32 V
EN/UV Pin Hysteresis EN/UV Trip Point Hysteresis, VIN = 2V 130 mV

Rev. C

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LT3045
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER CONDITIONS MIN TYP MAX UNITS
EN/UV Pin Current VEN/UV = 0V, VIN = 20V l ±1 µA
VEN/UV = 1.24V, VIN = 20V 0.03 µA
VEN/UV = 20V, VIN = 0V l 8 15 µA
Quiescent Current in VIN = 6V 0.3 1 µA
Shutdown (VEN/UV = 0V) TJ ≤ 125°C (E/I-Grade) l 10 µA
TJ ≤ 150°C (H-/MP-Grade) l 20 µA
Internal Current Limit VIN = 2V, VOUT = 0V l 570 710 850 mA
(Note 12) VIN = 12V, VOUT = 0V 700 mA
VIN = 20V, VOUT = 0V l 230 330 430 mA
Programmable Programming Scale Factor: 2V < VIN < 20V (Note 11) 150 mA • kΩ
Current Limit VIN = 2V, VOUT = 0V, RILIM = 300Ω l 450 500 550 mA
VIN = 2V, VOUT = 0V, RILIM = 1.5kΩ l 90 100 110 mA
PGFB Trip Point PGFB Trip Point Rising l 291 300 309 mV
PGFB Hysteresis PGFB Trip Point Hysteresis 7 mV
PGFB Pin Current VIN = 2V, VPGFB = 300mV 25 nA
PG Output Low Voltage IPG = 100µA l 30 100 mV
PG Leakage Current VPG = 20V l 1 µA
Reverse Input Current VIN = –20V, VEN/UV = 0V, VOUT = 0V, VSET = 0V l 100 µA
Reverse Output Current VIN = 0, VOUT = 5V, SET = Open 14 25 µA
Minimum Load Required VOUT < 1V l 10 µA
(Note 13)
Thermal Shutdown TJ Rising 165 °C
Hysteresis 8 °C
Start-Up Time VOUT(NOM) = 5V, ILOAD = 500mA, CSET = 0.47µF, VIN = 6V, VPGFB = 6V 55 ms
VOUT(NOM) = 5V, ILOAD = 500mA, CSET = 4.7µF, VIN = 6V, VPGFB = 6V 550 ms
VOUT(NOM) = 5V, ILOAD = 500mA, CSET = 4.7µF, VIN = 6V, RPG1 = 50kΩ, 10 ms
RPG2 = 700kΩ (with Fast Start-Up to 90% of VOUT)
Thermal Regulation 10ms Pulse –0.01 %/W

Note 1: Stresses beyond those listed under Absolute Maximum Ratings guarantee maximum dropout voltage specifications at high currents
may cause permanent damage to the device. Exposure to any Absolute due to production test limitations with Kelvin-sensing the package
Maximum Rating condition for extended periods may affect device pins. Please consult the Typical Performance Characteristics for curves
reliability and lifetime. of dropout voltage as a function of output load current and temperature
Note 2: The EN/UV pin threshold must be met to ensure device operation. measured in a typical application circuit.
Note 3: Maximum junction temperature limits operating conditions. The Note 6: GND pin current is tested with VIN = VOUT(NOMINAL) and a current
regulated output voltage specification does not apply for all possible source load. Therefore, the device is tested while operating in dropout. This
combinations of input voltage and output current, especially due to the is the worst-case GND pin current. GND pin current decreases at higher
internal current limit foldback which starts to decrease current limit at input voltages. Note that GND pin current does not include SET pin or ILIM
VIN – VOUT > 12V. If operating at maximum output current, limit the input pin current but Quiescent current does include them.
voltage range. If operating at the maximum input voltage, limit the output Note 7: SET and OUTS pins are clamped using diodes and two 25Ω series
current range. resistors. For less than 5ms transients, this clamp circuitry can carry
Note 4: OUTS ties directly to OUT. more than the rated current. Refer to Applications Information for more
Note 5: Dropout voltage is the minimum input-to-output differential information.
voltage needed to maintain regulation at a specified output current. The Note 8: Adding a capacitor across the SET pin resistor decreases output
dropout voltage is measured when output is 1% out of regulation. This voltage noise. Adding this capacitor bypasses the SET pin resistor’s
definition results in a higher dropout voltage compared to hard dropout thermal noise as well as the reference current’s noise. The output noise
— which is measured when VIN = VOUT(NOMINAL). For lower output then equals the error amplifier noise. Use of a SET pin bypass capacitor
voltages, below 1.5V, dropout voltage is limited by the minimum input also increases start-up time.
voltage specification. For DFN package: Linear Technology is unable to

Rev. C

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 LT3045
ELECTRICAL CHARACTERISTICS
Note 9: The LT3045 is tested and specified under pulsed load conditions Note 11: The current limit programming scale factor is specified while the
such that TJ ≈ TA. The LT3045E is 100% tested at 25°C and performance internal backup current limit is not active. Note that the internal current
is guaranteed from 0°C to 125°C. Specifications over the –40°C to 125°C limit has foldback protection for VIN – VOUT differentials greater than 12V.
operating temperature range are assured by design, characterization, and Note 12: The internal back-up current limit circuitry incorporates foldback
correlation with statistical process controls. The LT3045I is guaranteed protection that decreases current limit for VIN – VOUT > 12V. Some level of
over the full –40°C to 125°C operating temperature range. LT3045H is output current is provided at all VIN – VOUT differential voltages. Consult the
100% tested at the 150°C operating junction temperature. LT3045MP Typical Performance Characteristics graph for current limit vs VIN – VOUT.
is 100% tested and guaranteed over the full −55°C to 150°C operating Note 13: For output voltages less than 1V, the LT3045 requires a 10µA
temperature range. High junction temperatures degrade operating lifetimes. minimum load current for stability.
Operating lifetime is derated at junction temperatures greater than 125°C.
Note 14: Maximum OUT-to-OUTS differential is guaranteed by design.
Note 10: Parasitic diodes exist internally between the ILIM, PG, PGFB, SET,
Note 15: MP-Grade is only offered in the DFN package.
OUTS, and OUT pins and the GND pin. Do not drive these pins more than
0.3V below the GND pin during a fault condition. These pins must remain at
a voltage more positive than GND during normal operation.

TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.

SET Pin Current SET Pin Current Offset Voltage (VOUT – VSET)
101.0 2.0
VIN = 2V N = 3250 VIN = 2V
100.8 IL = 1mA IL = 1mA
1.5
VOUT = 1.3V VOUT = 1.3V
100.6
1.0
SET PIN CURRENT (µA)

OFFSET VOLTAGE (mV)

100.4
100.2 0.5

100.0 0
99.8
–0.5
99.6
–1.0
99.4
99.2 –1.5

99.0 –2.0
–75 –50 –25 0 25 50 75 100 125 150 98 99 100 101 102 –75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) ISET DISTRIBUTION (µA) TEMPERATURE (°C)
3045 G01 3045 G02 3045 G03

Offset Voltage SET Pin Current Offset Voltage (VOUT – VSET)

101.0 2.0
N = 3250 IL = 1mA 150°C IL = 1mA 150°C
100.8 V VOUT = 1.3V
OUT = 1.3V 125°C 1.5 125°C
100.6 25°C 25°C
–55°C 1.0 –55°C
SET PIN CURRENT (µA)

OFFSET VOLTAGE (mV)

100.4
0.5
100.2
100.0 0
99.8 –0.5
99.6
–1.0
99.4
–1.5
99.2
99.0 –2.0
–2 –1 0 1 2 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
VOS DISTRIBUTION (mV) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
3045 G04 3045 G05 3045 G06

Rev. C

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LT3045
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.

SET Pin Current Offset Voltage (VOUT – VSET) Load Regulation

101.0 2.0 20 0.20
IL = 1mA 150°C IL = 1mA 150°C V = 2.5V
100.8
VIN = 20V 125°C 1.5 VIN = 20V 125°C 18 ∆IIN= 1mA to 500mA 0.18
L
100.6 25°C 25°C 16 VOUT = 1.3V 0.16
–55°C 1.0 –55°C
SET PIN CURRENT (µA)

OFFSET VOLTAGE (mV)

100.4 14 0.14
100.2 0.5
12 0.12

∆ VOS (mV)
∆ISET (nA)
100.0 0 10 0.10
VOS
99.8 –0.5 8 0.08
99.6 6 0.06
–1.0
99.4 4 ISET 0.04
99.2 –1.5
2 0.02
99.0 –2.0 0 0
0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 –75 –50 –25 0 25 50 75 100 125 150
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) TEMPERATURE (°C)
3045 G07 3045 G08 3045 G09

Quiescent Current Quiescent Current Quiescent Current

4.0 50 3.0
VIN = 2V VEN/UV = 0V VEN/UV = VIN
VEN/UV = VIN 45 IL = 10µA
3.5
IL = 10µA 2.5 RSET = 33.2k
RSET = 13k 40

QUIESCENT CURRENT (mA)

QUIESCENT CURRENT (mA)

QUIESCENT CURRENT (µA)

3.0
35
2.0
2.5 30
2.0 25 VIN = 20V 1.5
20
1.5
VIN = 2V 1.0
15
1.0
10
0.5
0.5 5
0 0 0
–75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 0 2 4 6 8 10 12 14 16 18 20
TEMPERATURE (°C) TEMPERATURE (°C) INPUT VOLTAGE (V)
3045 G10 3045 G11 3045 G12

Quiescent Current Typical Dropout Voltage Dropout Voltage

4.0 500 500
VIN = 20V RSET = 33.2k RSET = 33.2k
3.5 VEN/UV = VIN 450 450
IL = 10µA
400 400
QUIESCENT CURRENT (mA)

3.0 IL = 400mA
DROPOUT VOLTAGE (mV)

DROPOUT VOLTAGE (mV)

350 350
2.5
300 300 IL = 500mA
2.0 250 250
IL = 1mA
1.5 200 200
150 150
1.0 150°C 150°C
125°C 100 125°C 100
0.5 25°C 25°C
50 50
–55°C –55°C
0 0 0
0 2 4 6 8 10 12 14 16 0 50 100 150 200 250 300 350 400 450 500 –75 –50 –25 0 25 50 75 100 125 150
OUTPUT VOLTAGE (V) OUTPUT CURRENT (mA) TEMPERATURE (°C)
3045 G13 3045 G14 3045 G15

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 LT3045
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.

GND Pin Current GND Pin Current GND Pin Current

20 22 18
VIN = 5V VIN = 4.3V RSET = 33.2k
18 RSET = 33.2k 20
RSET = 33.2k 16
16 18
14

GND PIN CURRENT (mA)

16
GND PIN CURRENT (mA)

GND PIN CURRENT (mA)

14 RL = 6.6Ω
IL = 500mA
14 12
12
12 10
10
10 8 RL = 11Ω
IL = 300mA
8
8
6
6 6
IL = 100mA 150°C RL = 33Ω
4 4
4 125°C RL = 330Ω
25°C 2
2 2 RL = 3.3kΩ
IL = 1mA –55°C
0 0 0
–75 –50 –25 0 25 50 75 100 125 150 0 50 100 150 200 250 300 350 400 450 500 0 1 2 3 4 5 6 7 8 9 10
TEMPERATURE (°C) OUTPUT CURRENT (mA) INPUT VOLTAGE (V)
3045 G16 3045 G17 3045 G18

Minimum Input Voltage EN/UV Turn-On Threshold EN/UV Pin Hysteresis

2.00 1.32 200
185
1.75 1.30
170

EN/UV PIN HYSTERESIS (mV)

INPUT UVLO THRESHOLD (V)

TURN-ON THRESHOLD (V)

1.50
1.28 155
1.25 140 VIN = 10V
1.26
1.00 125
1.24 110
VIN = 2V
0.75 VIN = 2V
1.22 95
0.50 VIN = 10V
80
0.25 RISING UVLO 1.20
65
FALLING UVLO
0 1.18 50
–75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3045 G19 3045 G20 3045 G21

EN/UV Pin Current EN/UV Pin Current Negative Enable Pin Current
5.5 10 0
VIN = 20V VIN = 2V
5.0 9 VIN = 2V –10
4.5 8 –20
EN/UV PIN CURRENT (µA)

EN/UV PIN CURRENT (µA)

EN/UV PIN CURRENT (µA)

4.0 7 –30
3.5
6 –40
3.0
5 VIN = 20V –50
2.5
4 –60
2.0
3 –70
1.5 150°C
150°C
1.0 2 –80 125°C
125°C
25°C 1 –90 25°C
0.5 –55°C
–55°C
0 0 –100
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0
ENABLE PIN VOLTAGE (V) ENABLE PIN VOLTAGE (V) ENABLE PIN VOLTAGE (V)
3045 G22 3045 G23 3045 G24

Rev. C

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LT3045
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.

Input Pin Current Internal Current Limit Internal Current Limit

0.3 1000 600
VIN = 2V 150°C RILIM = 0Ω VIN = 20V
900 VOUT = 0V
125°C RILIM = 0Ω
500 VOUT = 0V
25°C 800
–55°C
INPUT CURRENT (µA)

CURRENT LIMIT (mA)

CURRENT LIMIT (mA)

700
0.2 400
600
500 300
400
0.1 200
300
200
100
VIN = 2.5V
100
VIN = 12V
0 0 0
–20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150
ENABLE PIN VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C)
3045 G25 3045 G26 3045 G27

Internal Current Limit Programmable Current Limit Programmable Current Limit

1000 1000 200
RILIM = 0Ω RILIM = 300Ω RILIM = 1.5k
900 900 180
VOUT = 0V VOUT = 0V
800 800 160
CURRENT LIMIT (mA)

CURRENT LIMIT (mA)

CURRENT LIMIT (mA)

700 700 140

600 600 120
VIN = 2.5V
500 500 100
VIN = 12V
400 400 80
300 300 60
150°C
200 125°C 200 40
25°C VIN = 2.5V
100 100 20
–55°C VIN = 12V
0 0 0
0 2 4 6 8 10 12 14 16 18 20 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150
INPUT-TO-OUTPUT DIFFERENTIAL (V) TEMPERATURE (°C) TEMPERATURE (°C)
3045 G28 3045 G29 3045 G30

ILIM Pin Current PGFB Rising Threshold PGFB Hysteresis

1000 310 8
VILIM = 0V VIN = 2V VIN = 2V
900 RSET = 13k 308 7
PGFB RISING THRESHOLD (mV)

800 306
6
PGFB HYSTERESIS (mV)
ILIM PIN CURRENT (uA)

700 304
5
600 302
500 300 4

400 298 3
300 296
2
200 2.5VIN 294
5VIN 1
100 292
10VIN
0 290 0
0 50 100 150 200 250 300 350 400 450 500 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150
OUTPUT CURRENT (mA) TEMPERATURE (°C) TEMPERATURE (°C)
3045 G31 3045 G32 3045 G33

Rev. C

8 For more information www.analog.com

 LT3045
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.

ISET During Start-Up with Fast

PG Output Low Voltage PG Pin Leakage Current Start-Up Enabled
50 100 3.0
VIN = 2V VPG = 2V VIN = 2.5V
45 90
VPGFB = 290mV VPGFB = 310mV VPGFB = 290mV
2.5 VSET = 1.3V
40 IPG = 100µA 80

35 70
2.0
30 60

ISET (mA)
VPG (mV)

IPG (nA)
25 50 1.5
20 40
1.0
15 30

10 20
0.5
5 10

0 0 0
–75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3045 G34 3045 G35 3045 G36

ISET During Start-Up with Fast Output Overshoot Recovery Output Overshoot Recovery
Start-Up Enabled Current Sink Current Sink
3.5 12 7
VPGFB = 290mV VIN = 5V 150°C VIN = 5V
VSET = 1.3V RSET = 33.2k 125°C RSET = 33.2k
3.0 10 6
25°C VOUT – VSET > 5mV

OUTPUT SINK CURRENT (mA)

OUTPUT SINK CURRENT (mA)

–55°C
2.5 5
8
2.0 4
ISET (mA)

6
1.5 3
4
1.0 2

0.5 2 1

0 0 0
0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 –75 –50 –25 0 25 50 75 100 125 150
VIN-TO-VSET DIFFERENTIAL (V) VOUT – VSET (mV) TEMPERATURE (°C)
3045 G37 3045 G38 3045 G39

VOUT Forced Above VOUT(NOMINAL) Power Supply Ripple Rejection Power Supply Ripple Rejection
8 120 120
VIN = 5V IIN when VEN = 0V COUT = 10µF
CSET = 4.7µF
RSET = 33.2k IOUT when VEN = 0V 110 110 COUT = 22µF
CSET = 0.47µF
IIN when VEN = VIN
100 100
6 IOUT when VEN = VIN
90 90
CURRENT (mA)

80 80
PSRR (dB)

PSRR (dB)

4 70 70
60 60
50 50
2 VIN = 5V VIN = 5V
40 RSET = 30.1k 40
RSET = 30.1k
30 COUT = 10µF 30 CSET = 0.47µF
IL = 500mA IL = 500mA
0 20 20
4 5 6 7 8 9 10 11 12 13 14 15 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
OUTPUT VOLTAGE (V) FREQUENCY (Hz) FREQUENCY (Hz)
3045 G40 3045 G41 3045 G42

Rev. C

For more information www.analog.com 9

 LT3045
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.

Power Supply Ripple Rejection

as a Function of Error Amplifier
Power Supply Ripple Rejection Input Pair Power Supply Ripple Rejection
140 120 100
VIN = VOUT + 2V
110 IL = 500mA 90
120 COUT = 10µF
100 80
CSET = 0.47µF
90 70
100
80 60
PSRR (dB)

PSRR (dB)

PSRR (dB)
80 70 50
60 40
60
IL = 500mA 50 30
IL = 300mA VIN = 5V 100kHz IL = 500mA
40 VOUT ≥ 1.3V 20 RSET = 30.1k
40 IL = 100mA RSET = 30.1k 500kHz
IL = 50mA COUT = 10µF 30 0.6V < VOUT < 1.3V 10 1MHz COUT = 10µF
IL = 1mA CSET = 0.47µF VOUT ≤ 0.6V 2MHz CSET = 0.47µF
20 20 0
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M 0 1 2 3 4 5
FREQUENCY (Hz) FREQUENCY (Hz) INPUT–TO–OUTPUT DIFFERENTIAL (V)
3045 G43 3045 G44 3045 G45

Integrated RMS Output Noise Integrated RMS Output Noise Integrated RMS Output Noise
(10Hz to 100kHz) (10Hz to 100kHz) (10Hz to 100kHz)
2.0 9 2.0
VIN = 5V VIN = 5V VIN = VOUT + 2V
1.8 8 1.8
RSET = 33.2k COUT = 10µF COUT = 10µF
1.6 COUT = 10µF RSET = 33.2k 1.6 CSET = 4.7µF

RMS OUTPUT NOISE (µVRMS)

RMS OUTPUT NOISE (µVRMS)

RMS OUTPUT NOISE (µVRMS)

CSET = 4.7µF 7
ILOAD = 500mA ILOAD = 500mA
1.4 1.4
6
1.2 1.2
5
1.0 1.0
4
0.8 0.8
3
0.6 0.6
0.4 2 0.4
0.2 1 0.2
0 0 0
0 50 100 150 200 250 300 350 400 450 500 0.01 0.1 1 10 100 0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15
LOAD CURRENT (mA) SET PIN CAPACITANCE (µF) OUTPUT VOLTAGE (V)
3045 G46 3045 G47 3045 G48

Noise Spectral Density Noise Spectral Density Noise Spectral Density

1000 1000 1000
CSET = 0.047µF IL = 500mA
CSET = 0.47µF IL = 300mA
CSET = 1µF IL = 100mA
100 CSET = 4.7µF 100 100 IL = 10mA
OUTPUT NOISE (nV/√Hz)

OUTPUT NOISE (nV/√Hz)

OUTPUT NOISE (nV/√Hz)

CSET = 22µF IL = 1mA

10 10 COUT = 10µF 10

1 V = 5V 1 V = 5V 1 V = 5V
IN IN IN
RSET = 33.2k RSET = 33.2k COUT = 22µF RSET = 33.2k
COUT = 10µF CSET = 4.7µF CSET = 4.7µF
ILOAD = 500mA ILOAD = 500mA COUT = 10µF
0.1 0.1 0.1
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
3045 G49 3045 G50 3045 G51

Rev. C

10 For more information www.analog.com

 LT3045
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.

Noise Spectral Density as

a Function of Error Amplifier
Input Pair Output Noise: 10Hz to 100kHz Load Transient Response
1000
VOUT ≥ 1.3V
0.6V < VOUT < 1.3V
VOUT ≤ 0.6V
100 OUTPUT
OUTPUT NOISE (nV/√Hz)

CURRENT
5µV/DIV 500mA/DIV

10 VIN = 5V
RSET = 33.2k OUTPUT
COUT = 10µF VOLTAGE
CSET = 4.7µF 20mV/DIV
1 V =V IL = 500mA
IN OUT + 2V 3042 G53 3042 G54
IL = 500mA 1ms/DIV 20µs/DIV
COUT = 10µF VIN = 5V
CSET = 4.7µF RSET = 33.2k
0.1 COUT = 10µF
10 100 1k 10k 100k 1M 10M
CSET = 0.47µF
FREQUENCY (Hz) LOAD STEP = 10mA TO 500mA
3045 G52

Start-Up Time with and

without Fast Start-Up Circuitry for Input Supply Ramp-Up and
Line Transient Response Large CSET Ramp-Down

500mV/DIV INPUT VOLTAGE

INPUT OUTPUT WITH
FAST START–UP
VOLTAGE
(SET AT 90%)
500mV/DIV
2V/DIV 2V/DIV
OUTPUT VOLTAGE
PULSE EN/UV
OUTPUT OUTPUT WITHOUT
VOLTAGE FAST START–UP
1mV/DIV

3042 G55 3042 G56 3042 G57

5µs/DIV 100ms/DIV 50ms/DIV
VIN = 5V
VIN = 4.5V TO 5V VIN = 0V TO 5V
RSET = 33.2k
RSET = 33.2k VEN/UV = VIN
COUT = 10µF
COUT = 10µF RSET = 33.2k
CSET = 4.7µF
CSET = 0.47µF COUT = 10µF
RL = 6.6Ω
IL = 500mA CSET = 0.47µF
RL = 6.6Ω

Rev. C

For more information www.analog.com 11

LT3045
PIN FUNCTIONS (DFN/MSOP)

IN (Pins 1, 2/Pins 1, 2, 3): Input. These pins supply power therefore, it also serves as a current monitoring pin with
to the regulator. The LT3045 requires a bypass capacitor a 0V to 300mV range. If the programmable current limit
at the IN pin. In general, a battery’s output impedance functionality is not needed, tie ILIM to GND. A parasitic
rises with frequency, so include a bypass capacitor in substrate diode exists between ILIM and GND pins of the
battery-powered applications. While a 4.7µF input bypass LT3045; do not drive ILIM more than 0.3V below GND
capacitor generally suffices, applications with large load during normal operation or during a fault condition.
transients may require higher input capacitance to prevent
PGFB (Pin 6/Pin 7): Power Good Feedback. The PG pin
input supply droop. Consult the Applications Information
pulls high if PGFB increases beyond 300mV on its rising
section on the proper use of an input capacitor and its effect
edge, with 7mV hysteresis on its falling edge. Connect-
on circuit performance, in particular PSRR. The LT3045
ing an external resistor divider between OUT, PGFB and
withstands reverse voltages on IN with respect to GND,
GND sets the programmable power good threshold with
OUTS and OUT. In the case of a reversed input, which oc-
curs if a battery is plugged-in backwards, the LT3045 acts the following transfer function: 0.3V • (1 + RPG2/RPG1).
as if a diode is in series with its input. Hence, no reverse As discussed in the Applications Information section,
current flows into the LT3045 and no negative voltage PGFB also activates the fast start-up circuitry. Tie PGFB
appears at the load. The device protects itself and the load. to IN if power good and fast start-up functionalities are
not needed, and if reverse input protection is additionally
EN/UV (Pin 3/Pin 4): Enable/UVLO. Pulling the LT3045’s required, tie the anode of a 1N4148 diode to IN and its
EN/UV pin low places the part in shutdown. Quiescent cathode to PGFB. See the Typical Applications section for
current in shutdown drops to less than 1µA and the out- details. A parasitic substrate diode exists between PGFB
put voltage turns off. Alternatively, the EN/UV pin can set and GND pins of the LT3045; do not drive PGFB more
an input supply undervoltage lockout (UVLO) threshold than 0.3V below GND during normal operation or during
using a resistor divider between IN, EN/UV and GND. The
a fault condition.
LT3045 typically turns on when the EN/UV voltage exceeds
1.24V on its rising edge, with a 130mV hysteresis on its SET (Pin 7/Pin 8): SET. This pin is the inverting input of
falling edge. The EN/UV pin can be driven above the input the error amplifier and the regulation set-point for the
voltage and maintain proper functionality. If unused, tie LT3045. SET sources a precision 100µA current that
EN/UV to IN. Do not float the EN/UV pin. flows through an external resistor connected between SET
and GND. The LT3045’s output voltage is determined by
PG (Pin 4/Pin 5): Power Good. PG is an open-collector
VSET = ISET • RSET. Output voltage range is from zero to
flag that indicates output voltage regulation. PG pulls low
15V. Adding a capacitor from SET to GND improves noise,
if PGFB is below 300mV. If the power good functional-
PSRR and transient response at the expense of increased
ity is not needed, float the PG pin. A parasitic substrate
start-up time. For optimum load regulation, Kelvin connect
diode exists between PG and GND pins of the LT3045; do
the ground side of the SET pin resistor directly to the load.
not drive PG more than 0.3V below GND during normal
A parasitic substrate diode exists between SET and GND
operation or during a fault condition.
pins of the LT3045; do not drive SET more than 0.3V below
ILIM (Pin 5/Pin 6): Current Limit Programming Pin. GND during normal operation or during a fault condition.
Connecting a resistor between ILIM and GND programs
GND (Pin 8, Exposed Pad Pin 11/Pin 9, Exposed Pad
the current limit. For best accuracy, Kelvin connect this
Pin 13): Ground. The exposed backside is an electrical
resistor directly to the LT3045’s GND pin. The program-
connection to GND. To ensure proper electrical and ther-
ming scale factor is nominally 150mA•kΩ. The ILIM pin
mal performance, solder the exposed backside to the PCB
sources current proportional (1:500) to output current;
ground and tie it directly to the GND pin.

Rev. C

12 For more information www.analog.com

 LT3045
PIN FUNCTIONS
OUTS (Pin 9/Pin 10): Output Sense. This pin is the non- OUT (Pin 10/Pins 11, 12): Output. This pin supplies
inverting input to the error amplifier. For optimal transient power to the load. For stability, use a minimum 10µF
performance and load regulation, Kelvin connect OUTS output capacitor with an ESR below 20mΩ and an ESL
directly to the output capacitor and the load. Also, tie the below 2nH. Large load transients require larger output
GND connections of the output capacitor and the SET pin capacitance to limit peak voltage transients. Refer to the
capacitor directly together. A parasitic substrate diode ex- Applications Information section for more information
ists between OUTS and GND pins of the LT3045; do not on output capacitance. A parasitic substrate diode exists
drive OUTS more than 0.3V below GND during normal between OUT and GND pins of the LT3045; do not drive
operation or during a fault condition. OUT more than 0.3V below GND during normal operation
or during a fault condition.

Rev. C

For more information www.analog.com 13

LT3045
BLOCK DIAGRAM

VIN
EN/UV CIN

IN

CURRENT
100µA ERROR
2mA REFERENCE
– AMPLIFIER
QC QP
+ DRIVER QPWR
ENABLE
COMPARATOR
OUTPUT OVERSHOOT
+ RECOVERY
BIAS +
– THERMAL
+ FAST START-UP
SHDN –
V 1.24V OUT
VOUT
+
– INPUT
V 1.5V RL
UVLO
PROGRAMMABLE – COUT
POWER GOOD INTERNAL CURRENT
LIMIT
+
+ +
V 300mV – – 215Ω
– +
INPUT UVLO V 300mV
FAST START-UP CURRENT LIMIT –
DISABLE LOGIC THERMAL SHDN
DROPOUT PROGRAMMABLE
CURRENT LIMIT
SET-TO-OUTS
+
PROTECTION –
CLAMP
+
V 300mV
–
GND
PGFB PG SET OUTS ILIM

RPG RILIM
RPG2
RSET CSET

RPG1
3045 BD

Rev. C

14 For more information www.analog.com

 LT3045
APPLICATIONS INFORMATION
The LT3045 is a high performance low dropout linear NPN-based input pair is active for output voltages greater
regulator featuring LTC’s ultralow noise (2nV/√Hz at than 1.3V, with a smooth transition between the two input
10kHz) and ultrahigh PSRR (76dB at 1MHz) architecture pairs from 0.6V to 1.3V output. While the NPN-based input
for powering noise sensitive applications. Designed as a pair is designed to offer the best overall performance, refer
precision current source followed by a high performance to the Electrical Characteristics Table for details on offset
rail-to-rail voltage buffer, the LT3045 can be easily paral- voltage, SET pin current, output noise and PSRR variation
leled to further reduce noise, increase output current and with the error amp input pair. Table 1 lists many common
spread heat on the PCB. The device additionally features output voltages and their corresponding 1% RSET resistors.
programmable current limit, fast start-up capability and
Table 1. 1% Resistor for Common Output Voltages
programmable power good.
VOUT (V) RSET (kΩ)
The LT3045 is easy to use and incorporates all of the pro- 2.5 24.9
tection features expected in high performance regulators. 3.3 33.2
Included are short-circuit protection, safe operating area 5 49.9
protection, reverse battery protection, reverse current 12 121
protection, and thermal shutdown with hysteresis. 15 150

Output Voltage The benefit of using a current reference compared with

The LT3045 incorporates a precision 100µA current source a voltage reference as used in conventional regulators is
flowing out of the SET pin, which also ties to the error that the regulator always operates in unity gain configura-
amplifier’s inverting input. Figure 1 illustrates that connect- tion, independent of the programmed output voltage. This
ing a resistor from SET to ground generates a reference allows the LT3045 to have loop gain, frequency response
voltage for the error amplifier. This reference voltage is and bandwidth independent of the output voltage. As a
simply the product of the SET pin current and the SET result, noise, PSRR and transient performance do not
pin resistor. The error amplifier’s unity-gain configuration change with output voltage. Moreover, since none of the
produces a low impedance version of this voltage on its error amp gain is needed to amplify the SET pin voltage
noninverting input, i.e. the OUTS pin, which is externally to a higher output voltage, output load regulation is more
tied to the OUT pin. tightly specified in the hundreds of microvolts range and
not as a fixed percentage of the output voltage.
The LT3045’s rail-to-rail error amplifier and current refer-
ence allows for a wide output voltage range from 0V (us- Since the zero TC current source is highly accurate, the
ing a 0Ω resistor) to VIN minus dropout — up to 15V. A SET pin resistor can become the limiting factor in achiev-
PNP-based input pair is active for 0V to 0.6V output and an ing high accuracy. Hence, it should be a precision resistor.
Additionally, any leakage paths to or from the SET pin
IN LT3045
create errors in the output voltage. If necessary, use high
VIN
5V ±5% quality insulation (e.g., Teflon, Kel-F); moreover, clean-
100µA
4.7µF
EN/UV – ing of all insulating surfaces to remove fluxes and other
+ residues may be required. High humidity environments
OUT VOUT, 3.3V
PGFB IOUT(MAX), 500mA may require a surface coating at the SET pin to provide
OUTS
10µF a moisture barrier.
SET GND ILIM PG
3045 F01
Minimize board leakage by encircling the SET pin with a
guard ring operated at a potential close to itself — ideally
0.47µF 33.2k
tied to the OUT pin. Guarding both sides of the circuit
board is recommended. Bulk leakage reduction depends
Figure 1. Basic Adjustable Regulator
Rev. C

For more information www.analog.com 15

LT3045
APPLICATIONS INFORMATION
on the guard ring width. Leakages of 100nA into or out of DEMO BOARD
IN LT3045
the SET pin creates a 0.1% error in the reference voltage. VIN PCB LAYOUT
ILLUSTRATES
Leakages of this magnitude, coupled with other sources 100µA
4-TERMINAL
CIN CONNECTION
of leakage, can cause significant errors in the output volt- TO COUT
age, especially over wide operating temperature range. EN/UV

Figure 2 illustrates a typical guard ring layout technique. PGFB

VOUT
IOUT(MAX): 500mA
OUT

PG
OUTS
1 10
SET GND ILIM COUT
2 9 OUT
3 11 8
4 7 SET
5 6 RSET CSET

3045 F02
3045 F03

Figure 2. DFN Guard Ring Layout Figure 3. COUT and CSET Connections for Best Performance

Since the SET pin is a high impedance node, unwanted the GND side of CSET directly to the GND side of COUT,
signals may couple into the SET pin and cause erratic as well as keep the GND sides of CIN and COUT reason-
behavior. This is most noticeable when operating with a ably close. Refer to the LT3045 demo board manual for
minimum output capacitor at heavy load currents. By- more information on the recommended layout that meets
passing the SET pin with a small capacitance to ground these requirements. While the LT3045 is robust enough
resolves this issue — 10nF is sufficient. not to oscillate if the recommended layout is not followed,
For applications requiring higher accuracy or an adjust- depending on the actual layout, phase/gain margin, noise
able output voltage, the SET pin may be actively driven and PSRR performance may degrade.
by an external voltage source capable of sinking 100µA.
Stability and Output Capacitance
Connecting a precision voltage reference to the SET pin
eliminates any errors present in the output voltage due The LT3045 requires an output capacitor for stability.
to the reference current and SET pin resistor tolerances. Given its high bandwidth, LTC recommends low ESR and
ESL ceramic capacitors. A minimum 10µF output capaci-
Output Sensing and Stability tance with an ESR below 20mΩ and an ESL below 2nH is
required for stability.
The LT3045’s OUTS pin provides a Kelvin sense connection
to the output. The SET pin resistor’s GND side provides a Given the high PSRR and low noise performance attained
Kelvin sense connection to the load’s GND side. using a single 10µF ceramic output capacitor, larger values
of output capacitor only marginally improves the perfor-
Additionally, for ultrahigh PSRR, the LT3045 bandwidth
mance because the regulator bandwidth decreases with
is made quite high (~1MHz), making it very close to a
increasing output capacitance — hence, there is little to
typical 10µF (1206 case size) ceramic output capacitor’s
be gained by using larger than the minimum 10µF output
self-resonance frequency (~1.6MHz). Therefore, it is very
capacitor. Nonetheless, larger values of output capacitance
important to avoid adding extra impedance (ESR and
do decrease peak output deviations during a load transient.
ESL) outside the feedback loop. To that end, as shown in
Figure 3, minimize the effects of PCB trace and solder Note that bypass capacitors used to decouple individual
inductance by tying the OUTS pin directly to COUT and components powered by the LT3045 increase the effective
output capacitance.

Rev. C

16 For more information www.analog.com

 LT3045
APPLICATIONS INFORMATION
Give extra consideration to the type of ceramic capacitors 20
BOTH CAPACITORS ARE 16V,
used. They are manufactured with a variety of dielectrics, 0
1210 CASE SIZE, 10µF

each with different behavior across temperature and applied X5R

CHANGE IN VALUE (%)

voltage. The most common dielectrics used are specified –20

with EIA temperature characteristic codes of Z5U, Y5V,

–40
X5R and X7R. The Z5U and Y5V dielectrics are good for
providing high capacitance in the small packages, but they –60
tend to have stronger voltage and temperature coefficients Y5V
–80
as shown in Figure 4 and Figure 5. When used with a 5V
regulator, a 16V 10µF Y5V capacitor can exhibit an effective –100
value as low as 1µF to 2µF for the DC bias voltage applied 0 2 4 6 8 10
DC BIAS VOLTAGE (V)
12 14 16

over the operating temperature range. 3045 F04

X5R and X7R dielectrics result in more stable character- Figure 4. Ceramic Capacitor DC Bias Characteristics
istics and are thus more suitable for LT3045. The X7R
dielectric has better stability across temperature, while 40
BOTH CAPACITORS ARE 16V,
the X5R is less expensive and is available in higher values. 20
1210 CASE SIZE, 10µF

Nonetheless, care must still be exercised when using CHANGE IN VALUE (%) 0 X5R
X5R and X7R capacitors. The X5R and X7R codes only
specify operating temperature range and the maximum –20

capacitance change over temperature. While capacitance –40 Y5V

change due to DC bias for X5R and X7R is better than –60
Y5V and Z5U dielectrics, it can still be significant enough
to drop capacitance below sufficient levels. As shown in –80

Figure 6, capacitor DC bias characteristics tend to improve –100

–50 –25 0 25 50 75 100 125
as component case size increases, but verification of TEMPERATURE (°C)
expected capacitance at the operating voltage is highly 3045 F05

recommended. Due to its good voltage coefficient in small Figure 5. Ceramic Capacitor Temperature Characteristics
case sizes, LTC recommends using Murata’s GJ8 series
ceramic capacitors. 20

0
High Vibration Environments
CHANGE IN VALUE (%)

–20
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a –40
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress upon –60

it, similar to how a piezoelectric microphone works. For a –80

ceramic capacitor, this stress can be induced by mechanical MURATA: 25V,10%,
X7R/X5R, 10µF CERAMIC
vibrations within the system or due to thermal transients. –100
1 5 10 15 20 25
DC BIAS (V)
LT3045 applications in high vibration environments have 3045 F06

three distinct piezoelectric noise generators: ceramic GRM SERIES, 0805, 1.45mm THICK
output, input, and SET pin capacitors. However, due to GRM SERIES, 1206, 1.8mm THICK
GRM SERIES, 1210, 2.2mm THICK
LT3045’s very low output impedance over a wide fre- GJ8 SERIES, 1206, 1.9mm THICK

quency range, negligible output noise is generated using Figure 6. Capacitor Voltage Coefficient for Different Case Sizes
Rev. C

For more information www.analog.com 17

LT3045
APPLICATIONS INFORMATION
a ceramic output capacitor. Similarly, due to LT3045’s If a battery mounted in close proximity powers the LT3045,
ultrahigh PSRR, negligible output noise is generated a 4.7µF input capacitor suffices for stability. However, if a
using a ceramic input capacitor. Nonetheless, given the distantly located supply powers the LT3045, use a larger
high SET pin impedance, any piezoelectric response value input capacitor. Use a rough guideline of 1µF (in
from a ceramic SET pin capacitor generates significant addition to the 4.7µF minimum) per 6" of wire length.
output noise – peak-to-peak excursions of hundreds of The minimum input capacitance needed to stabilize the
µVs. However, due to the SET pin capacitor’s high ESR application also varies with the output capacitance as well
and ESL tolerance, any non-piezoelectrically responsive as the load current. Placing additional capacitance on the
(tantalum, electrolytic, or film) capacitor can be used at LT3045’s output helps. However, this requires significantly
the SET pin – although electrolytic capacitors tend to more capacitance compared to additional input bypassing.
have high 1/f noise. In any case, use of a surface mount Series resistance between the supply and the LT3045 input
capacitor is highly recommended. also helps stabilize the application; as little as 0.1Ω to 0.5Ω
suffices. This impedance dampens the LC tank circuit at
Stability and Input Capacitance the expense of dropout voltage. A better alternative is to
The LT3045 is stable with a minimum 4.7µF IN pin capacitor. use a higher ESR tantalum or electrolytic capacitor at the
LTC recommends using low ESR ceramic capacitors. In LT3045 input in parallel with a 4.7µF ceramic capacitor.
cases where long wires connect the power supply to the
LT3045’s input and ground terminals, the use of low value PSRR and Input Capacitance
input capacitors combined with a large load current can For applications utilizing the LT3045 for post-regulating
result in instability. The resonant LC tank circuit formed by switching converters, placing a capacitor directly at
the wire inductance and the input capacitor is the cause the LT3045 input results in ac current (at the switching
and not because of LT3045’s instability. frequency) to flow near the LT3045. This relatively high-
The self-inductance, or isolated inductance, of a wire frequency switching current generates a magnetic field
is directly proportional to its length. The wire diameter, that couples to the LT3045 output, thereby degrading its
however, has less influence on its self-inductance. For effective PSRR. While highly dependent on the PCB, the
example, the self-inductance of a 2-AWG isolated wire switching pre-regulator, the input capacitance, amongst
with a diameter of 0.26" is about half the inductance of a other factors, the PSRR degradation can be easily over
30-AWG wire with a diameter of 0.01". One foot of 30-AWG 30dB at 1MHz. This degradation is present even if the
wire has 465nH of self-inductance. LT3045 is de-soldered from the board, because it ef-
fectively degrades the PSRR of the PC board itself. While
Several methods exist to reduce a wire’s self-inductance. negligible for conventional low PSRR LDOs, LT3045’s
One method divides the current flowing towards the LT3045 ultrahigh PSRR requires careful attention to higher order
between two parallel conductors. In this case, placing the parasitics in order to extract the full performance offered
wires further apart reduces the inductance; up to a 50% by the regulator.
reduction when placed only a few inches apart. Splitting
To mitigate the flow of high-frequency switching current
the wires connect two equal inductors in parallel. However,
near the LT3045, the LT3045 input capacitor can be entirely
when placed in close proximity to each other, their mu-
tual inductance adds to the overall self inductance of the removed -- as long as the switching converter’s output
wires — therefore a 50% reduction is not possible in such capacitor is located more than an inch away from the
cases. The second and more effective technique to reduce LT3045. Magnetic coupling rapidly decreases with increas-
ing distance. Nonetheless, if the switching pre-regulator
the overall inductance is to place the forward and return
is placed too far away (conservatively more than a couple
current conductors (the input and ground wires) in close
inches) from the LT3045, with no input capacitor present,
proximity. Two 30-AWG wires separated by 0.02" reduce
as with any regulator, the LT3045 input will oscillate at the
the overall inductance to about one-fifth of a single wire.
Rev. C

18 For more information www.analog.com

 LT3045
APPLICATIONS INFORMATION
parasitic LC resonance frequency. Besides, it is generally a own noise of √4kTR — whereby k = Boltzmann’s constant
very common (and a preferred) practice to bypass regula- 1.38 • 10–23J/K and T is the absolute temperature.
tor input with some capacitance. So this option is fairly One problem that conventional linear regulators face is
limited in its scope and not the most palatable solution. that the resistor divider setting the output voltage gains up
To that end, LTC recommends using the LT3045 demo the reference noise. In contrast, the LT3045’s unity-gain
board layout for achieving the best possible PSRR perfor- follower architecture presents no gain from the SET pin
mance. The LT3045 demo board layout utilizes magnetic to the output. Therefore, if a capacitor bypasses the SET
field cancellation techniques to prevent PSRR degradation pin resistor, then the output noise is independent of the
caused by this high-frequency current flow—while utilizing programmed output voltage. The resultant output noise
the input capacitor. is then set just by the error amplifier’s noise — typically
2nV/√Hz from 10kHz to 1MHz and 0.8µVRMS in a 10Hz to
Filtering High Frequency Spikes 100kHz bandwidth using a 4.7µF SET pin capacitor. Paral-
For applications where the LT3045 is used to post-regulate leling multiple LT3045s further reduces noise by √N, for
a switching converter, its high PSRR effectively sup- N parallel regulators.
presses any “noise” present at the switcher’s switching Refer to the Typical Performance Characteristics section
frequency — typically 100kHz to 4MHz. However, the very for noise spectral density and RMS integrated noise over
high frequency (hundreds of MHz) “spikes” — beyond the various load currents and SET pin capacitances.
LT3045’s bandwidth — associated with the switcher’s
power switch transition times will almost directly pass Set Pin (Bypass) Capacitance: Noise, PSRR, Transient
through the LT3045. While the output capacitor is partly Response and Soft-Start
intended to absorb these spikes, its ESL will limit its ability
In addition to reducing output noise, using a SET pin bypass
at these frequencies. A ferrite bead or even the inductance
capacitor also improves PSRR and transient performance.
associated with a short (e.g. 0.5”) PCB trace between the
Note that any bypass capacitor leakage deteriorates the
switcher’s output and the LT3045’s input can serve as an
LT3045’s DC regulation. Capacitor leakage of even 100nA
LC-filter to suppress these very high frequency spikes.
is a 0.1% DC error. Therefore, LTC recommends the use
Output Noise of a good quality low leakage ceramic capacitor.

The LT3045 offers many advantages with respect to noise Using a SET pin bypass capacitor also soft-starts the output
performance. Traditional linear regulators have several and limits inrush current. The RC time constant, formed
sources of noise. The most critical noise sources for a by the SET pin resistor and capacitor, controls soft-start
traditional regulator are its voltage reference, error amplifier, time. Ramp-up rate from 0 to 90% of nominal VOUT is:
noise from the resistor divider network used for setting tSS ≈ 2.3 • RSET • CSET (Fast Start-Up Disabled)
output voltage and the noise gain created by this resistor
divider. Many low noise regulators pin out their voltage Fast Start-Up
reference to allow for noise reduction by bypassing the For ultralow noise applications that require low 1/f noise
reference voltage. (i.e. at frequencies below 100Hz), a larger value SET pin
Unlike most linear regulators, the LT3045 does not use a capacitor is required, up to 22µF. While this would normally
voltage reference; instead, it uses a 100µA current refer- significantly increase the regulator’s start-up time, the
ence. The current reference operates with typical noise LT3045 incorporates fast start-up circuitry that increases
current level of 20pA/√Hz (6nARMS over a 10Hz to 100kHz the SET pin current to about 2mA during start-up.
bandwidth). The resultant voltage noise equals the current As shown in the Block Diagram, the 2mA current source
noise multiplied by the resistor value, which in turn is RMS remains engaged while PGFB is below 300mV, unless the
summed with the error amplifier’s noise and the resistor’s
Rev. C

For more information www.analog.com 19

LT3045
APPLICATIONS INFORMATION
regulator is in current limit, dropout, thermal shutdown is desired in shutdown, tie the power good resistor (i.e.
or input voltage is below minimum VIN. RPG in the Block Diagram) between the PG pin and either
If fast start-up capability is not used, tie PGFB to IN or to the EN/UV or OUT pins.
OUT for output voltages above 300mV. Note that doing
Externally Programmable Current Limit
so also disables power good functionality.
The ILIM pin’s current limit threshold is 300mV. Connecting
ENABLE/UVLO a resistor from ILIM to GND sets the maximum current
The EN/UV pin is used to put the regulator into a mi- flowing out of the ILIM pin, which in turn programs the
cropower shutdown state. The LT3045 has an accurate LT3045’s current limit. With a 150mA • kΩ programming
1.24V turn-on threshold on the EN/UV pin with 130mV scale factor, the current limit can be calculated as follows:
of hysteresis. This threshold can be used in conjunction 150mA •kΩ
with a resistor divider from the input supply to define an Current Limit =
RILIM
accurate undervoltage lockout (UVLO) threshold for the
regulator. The EN/UV pin current (IEN) at the threshold from For example, a 1kΩ resistor programs the current limit
the Electrical Characteristics table needs to be considered to 150mA and a 2kΩ resistor programs the current limit
when calculating the resistor divider network: to 75mA. For good accuracy, Kelvin connect this resistor
to the LT3045’s GND pin.
⎛ R ⎞
VIN(UVLO) = 1.24V • ⎜ 1+ EN2 ⎟ +IEN •REN2 In cases where IN-to-OUT differential is greater than 12V,
⎝ REN1 ⎠
the LT3045’s foldback circuitry decreases the internal
The EN/UV pin current (IEN) can be ignored if REN1 is less current limit. As a result, internal current limit may over-
than 100k. If unused, tie EN/UV pin to IN. ride the externally programmed current limit level to keep
the LT3045 within its safe-operating-area (SOA). See the
Programmable Power Good Internal Current Limit vs Input-to-Output Differential graph
in the Typical Performance Characteristics section.
As illustrated in the Block Diagram, power good thresh-
old is user programmable using the ratio of two external As shown in the Block Diagram, the ILIM pin sources current
resistors, RPG2 and RPG1: proportional (1:500) to output current; therefore, it also
serves as a current monitoring pin with a 0V to 300mV
⎛ R ⎞ range. If external current limit or current monitoring is
VOUT(PG_ THRESHOLD) = 0.3V • ⎜ 1+ PG2 ⎟ –IPGFB •RPG2
⎝ RPG1 ⎠ not used, tie ILIM to GND.

If the PGFB pin increases above 300mV, the open-collector Output Overshoot Recovery
PG pin de-asserts and becomes high impedance. The
During a load step from full load to no load (or light
power good comparator has 7mV hysteresis and 5µs of
load), the output voltage overshoots before the regulator
deglitching. The PGFB pin current (IPGFB) from the Electrical
responds to turn the power transistor OFF. Given that there
Characteristics table must be considered when determining
is no load (or very light load) present at the output, it takes
the resistor divider network. The PGFB pin current (IPGFB)
a long time to discharge the output capacitor.
can be ignored if RPG1 is less than 30k. If power good
functionality is not used, float the PG pin. Please note that As illustrated in the Block Diagram, the LT3045 incorporates
programmable power good and fast start-up capabilities an overshoot recovery circuitry that turns on a current
are disabled for output voltages below 300mV. sink to discharge the output capacitor in the event OUTS
is higher than SET. This current is typically about 4mA.
The power good functionality is disabled in shutdown,
No load recovery is disabled for input voltages less than
i.e. when EN/UV is set to 0V. If power good functionality
2.5V or output voltages less than 1.5V.
Rev. C

20 For more information www.analog.com

 LT3045
APPLICATIONS INFORMATION
VIN IN LT3045 If OUTS is externally held above SET, the current sink
5V ±5%
100µA
turns ON in an attempt to restore OUTS to its programmed
10µF
EN/UV – voltage. The current sink remains ON until the external
+
OUT 20mΩ circuitry releases OUTS.
PGFB
OUTS
10µF
Direct Paralleling for Higher Current
SET GND ILIM PG
Higher output current is obtained by paralleling multiple
VOUT
3.3V
LT3045s. Tie all SET pins together and all IN pins together.
IN LT3045 IOUT(MAX) Connect the OUT pins together using small pieces of PCB
1A
100µA trace (used as a ballast resistor) to equalize currents in
EN/UV – the LT3045s. PCB trace resistance in milliohms/inch is
+
OUT 20mΩ shown in Table 2.
PGFB OUTS
Table 2. PC Board Trace Resistance
SET GND ILIM PG 10µF
WEIGHT (oz) 10mil WIDTH 20mil WIDTH
1 54.3 27.1
3045 F07

2 27.1 13.6
16.5k 0.47µF Trace resistance is measured in mΩ/in.
The small worst-case offset of 2mV for each paralleled
Figure 7. Parallel Devices LT3045 minimizes the required ballast resistor value.
Figure 7 illustrates that two LT3045s, each using a 20mΩ
PCB trace ballast resistor, provide better than 20% accurate
output current sharing at full load. The two 20mΩ external
resistors only add 10mV of output regulation drop with a
1A maximum current. With a 3.3V output, this only adds
0.3% to the regulation accuracy. As has been discussed
previously, tie the OUTS pin directly to the output capacitor.
More than two LT3045s can also be paralleled for even
higher output current and lower output noise. Paralleling
multiple LT3045s is also useful for distributing heat on the
PCB. For applications with high input-to-output voltage
differential, an input series resistor or resistor in parallel
with the LT3045 can also be used to spread heat.

PCB Layout Considerations

Given the LT3045’s high bandwidth and ultrahigh PSRR,
careful PCB layout must be employed to achieve full device
performance. Figure 8 shows a recommended layout that
delivers full performance of the regulator. Refer to the
LT3045’s DC2491A demo board manual for further details.
Figure 8. Recommended DFN Layout

Rev. C

For more information www.analog.com 21

LT3045
APPLICATIONS INFORMATION
Thermal Considerations Table 3. Measured Thermal Resistance for DFN Package
COPPER AREA
The LT3045 has internal power and thermal limiting circuits THERMAL
TOP SIDE* BOTTOM SIDE BOARD AREA RESISTANCE
that protect the device under overload conditions. The ther-
2500mm2 2500mm2 2500mm2 34°C/W
mal shutdown temperature is nominally 165°C with about
1000mm2 2500mm2 2500mm2 34°C/W
8°C of hysteresis. For continuous normal load conditions,
do not exceed the maximum junction temperature (125°C 225mm2 2500mm2 2500mm2 35°C/W

for E- and I-grades and 150°C for H- and MP-Grades). It 100mm2 2500mm2 2500mm2 36°C/W
is important to consider all sources of thermal resistance *Device is mounted on topside
from junction to ambient. This includes junction-to-case, Table 4. Measured Thermal Resistance for MSOP Package
case-to-heat sink interface, heat sink resistance or circuit COPPER AREA THERMAL
board-to-ambient as the application dictates. Additionally, TOP SIDE* BOTTOM SIDE BOARD AREA RESISTANCE
consider all heat sources in close proximity to the LT3045. 2500mm2 2500mm2 2500mm2 33°C/W
1000mm2 2500mm2 2500mm2 33°C/W
The undersides of the DFN and MSOP packages have
225mm2 2500mm2 2500mm2 34°C/W
exposed metal from the lead frame to the die attachment.
100mm2 2500mm2 2500mm2 35°C/W
Both packages allow heat to directly transfer from the die
*Device is mounted on topside
junction to the PCB metal to limit maximum operating
junction temperature. The dual-in-line pin arrangement Calculating Junction Temperature
allows metal to extend beyond the ends of the package
on the topside (component side) of the PCB. Example: Given an output voltage of 3.3V and input voltage
of 5V ± 5%, output current range from 1mA to 500mA,
For surface mount devices, heat sinking is accomplished and a maximum ambient temperature of 85°C, what is the
by using the heat spreading capabilities of the PCB and its maximum junction temperature?
copper traces. Copper board stiffeners and plated through-
holes can also be used to spread the heat generated by The LT3045’s power dissipation is:
the regulator. IOUT(MAX) • (VIN(MAX) – VOUT) + IGND • VIN(MAX)
Table 3 and Table 4 list thermal resistance as a function where:
of copper area on a fixed board size. All measurements
were taken in still air on a 4 layer FR-4 board with 1oz IOUT(MAX) = 500mA
solid internal planes and 2oz top/bottom planes with a total VIN(MAX) = 5.25V
board thickness of 1.6mm. The four layers were electrically
IGND (at IOUT = 500mA and VIN = 5.25V) = 12.5mA
isolated with no thermal vias present. PCB layers, copper
weight, board layout and thermal vias affect the resultant thus:
thermal resistance. For more information on thermal PDISS = 0.5A • (5.25V – 3.3V) + 12.5mA • 5.25V = 1W
resistance and high thermal conductivity test boards,
refer to JEDEC standard JESD51, notably JESD51-7 and Using a DFN package, the thermal resistance is in the
JESD51-12. Achieving low thermal resistance necessitates range of 34°C/W to 36°C/W depending on the copper area.
attention to detail and careful PCB layout. Therefore, the junction temperature rise above ambient
approximately equals:
1W • 35°C/W = 35°C
The maximum junction temperature equals the maxi-
mum ambient temperature plus the maximum junction
temperature rise above ambient:
TJMAX = 85°C + 35°C = 120°C
Rev. C

22 For more information www.analog.com

 LT3045
TYPICAL APPLICATIONS
Overload Recovery Protection Features
Like many IC power regulators, the LT3045 incorporates The LT3045 incorporates several protection features for
safe-operating-area (SOA) protection. The SOA protection battery-powered applications. Precision current limit and
activates at input-to-output differential voltages greater thermal overload protection protect the LT3045 against
than 12V. The SOA protection decreases the current limit overload and fault conditions at the device’s output. For
as the input-to-output differential increases and keeps normal operation, do not allow the junction temperature
the power transistor inside a safe operating region for to exceed 125°C (E-grade, I-grade) or 150°C (H-grade,
all values of input-to-output voltages up to the LT3045’s MP-Grade).
absolute maximum ratings. The LT3045 provides some
To protect the LT3045’s low noise error amplifier, the SET-
level of output current for all values of input-to-output dif-
to-OUTS protection clamp limits the maximum voltage
ferentials. Refer to the Current Limit curves in the Typical
between SET and OUTS with a maximum DC current of
Performance Characteristics section. When power is first
20mA through the clamp. So for applications where SET
applied and input voltage rises, the output follows the input
is actively driven by a voltage source, the voltage source
and keeps the input-to-output differential low to allow the
must be current limited to 20mA or less. Moreover, to limit
regulator to supply large output current and start-up into
the transient current flowing through these clamps during
high current loads.
a transient fault condition, limit the maximum value of the
Due to current limit foldback, however, at high input volt- SET pin capacitor (CSET) to 22µF.
ages a problem can occur if the output voltage is low and The LT3045 also incorporates reverse input protection
the load current is high. Such situations occur after the whereby the IN pin withstands reverse voltages of up to
removal of a short-circuit or if the EN/UV pin is pulled high
–20V without causing any input current flow and without
after the input voltage has already turned ON. The load
developing negative voltages at the OUT pin. The regulator
line in such cases intersects the output current profile at
protects both itself and the load against batteries that are
two points. The regulator now has two stable operating
plugged-in backwards.
points. With this double intersection, the input power
supply may need to be cycled down to zero and brought In circuits where a backup battery is required, several
back up again to make the output recover. Other linear different input/output conditions can occur. The output
regulators with foldback current limit protection (such as voltage may be held up while the input is either pulled to
the LT1965 and LT1963A) also exhibit this phenomenon, GND, pulled to some intermediate voltage, or left open-
so it is not unique to the LT3045. circuit. In all of these cases, the reverse current protection
circuitry prevents current flow from output to the input.
Nonetheless, due to the OUTS-to-SET clamp, unless the
SET pin is floating, current can flow to GND through the
SET pin resistor as well as up to 15mA to GND through
the output overshoot recovery circuitry. This current flow
through the output overshoot recovery circuitry can be
significantly reduced by placing a Schottky diode between
OUTS and SET pins, with its anode at the OUTS pin.

Rev. C

For more information www.analog.com 23

LT3045
TYPICAL APPLICATIONS
12VIN to 3.3VOUT with 0.8µVRMS Integrated Noise

LT3045
VIN IN
12V ±5%
4.7µF 100µA

EN/UV –
200k + VOUT
OUT 3.3V
PG IOUT
OUTS 200mA
10µF
SET GND ILIM PGFB
453k

750Ω
4.7µF 33.2k 49.9k

3045 TA02

Low Noise CC/CV Lab Power Supply Ultralow Noise Current Source for RF Biasing Applications

IN LT3045 LT3045
VIN IN
VIN
1.8V to 20V
4.7µF 100µA 100µA
4.7µF ROUT = R1 + RLOAD
EN/UV
–
EN/UV
+ R1
VOUT(MAX): 15V
PGFB I : 200mA
OUT 1Ω OUT
OUT PGFB
VOUT
PG OUTS
OUTS
PG 10µF
SET GND ILIM 10µF SET GND ILIM
RLOAD

RIOUT 4.7µF
0.47µF RSET
3045 TA03 RSET
2k
3045 TA04

VOUT(MAX) = 100μA • RSET OUTPUT CURRENT NOISE = 0.8µVRMS/ROUT

INCREASE R1 (AND RSET) TO REDUCE CURRENT NOISE
150mA • kΩ
IOUT(MAX) = 
RIOUT

Rev. C

24 For more information www.analog.com

 LT3045
TYPICAL APPLICATIONS
Programming Undervoltage Lockout

VIN IN LT3045
4V Turn-ON
3.4V Turn-OFF
4.7µF 100µA
PGFB –
REN2 PG +
110k VOUT
⎛ 110k ⎞ OUT 3.3V
VIN(UVLO)RISING =1.24V • ⎜1+ ⎟ IOUT(MAX)
⎝ 49.9k ⎠
EN/UV OUTS 500mA
REN1
49.9k SET GND ILIM 10µF

3045 TA05

0.47µF 33.2k

Ratiometric Tracking

IN LT3045

100µA

EN/UV
–
+
PGFB
OUT
VOUT
IN LT3045 PG 5V
VIN OUTS
5.5V TO 20V 10µF
SET GND ILIM
100µA
10µF
EN/UV 3045 TA06
0.1µF 16.9k
PGFB
OUT
VOUT
PG OUTS 3.3V
10µF MIN LOAD 200µA
SET GND ILIM

0.1µF 33.2k

Rev. C

For more information www.analog.com 25

LT3045
TYPICAL APPLICATIONS
Ultralow 1/f Noise Reference Buffer

VIN IN LT3045
6V ±5%

4.7µF 100µA

EN/UV
–
+
PGFB VOUT = 5V
OUT
IOUT(MAX)
1,2 6,7 PG 500mA
OUTS
LTC6655-5 SET GND ILIM 10µF
3,4,5
1k
3045 TA07

10µF 49.9k 4.7µF

Paralleling Multiple Devices Using ILIM (Current Monitor) to Cancel Ballast Resistor Drop

VIN IN LT3045 LT3045 IN

5V ±5%
10µF 100µA 100µA

EN/UV
– VOUT = 3.3V – EN/UV
IOUT(MAX) = 1A
+ +
PGFB PGFB
OUT OUT
PG 20mΩ 20mΩ PG
OUTS OUTS
SET GND ILIM 10µF 10µF ILIM GND SET

RILIM
287Ω
287Ω
3045 TA08

1µF 16.5k

N = NUMBER OF DEVICES IN PARALLEL RCDC RILIM = 150mA • kΩ/ILIM – RCDC • N

RCDC = CABLE (BALLAST RESISTOR) DROP CANCELLATION RESISTOR 5Ω = 287Ω (FOR 500mA ILIM PER REGULATOR)
RILIM = CURRENT LIMIT PROGRAMMING RESISTOR RCDC = RBALLAST • 500/N
RBALLAST = BALLAST RESISTOR = 5Ω
ILIM = OUTPUT CURRENT LIMIT

Rev. C

26 For more information www.analog.com

 LT3045
TYPICAL APPLICATIONS
Paralleling Multiple LT3045s for 2A Output Current

IN LT3045 LT3045 IN
VIN
5V ±5%
22µF 100µA 100µA

EN/UV
– – EN/UV
+ +
200k PGFB
OUT OUT
PG 20mΩ 20mΩ PG
OUTS OUTS
SET ILIM GND PGFB 10µF 10µF ILIM GND SET
453k

49.9k VOUT = 3.3V

IOUT(MAX) = 2A
DROPOUT = 300mV

0.8µVRMS
OUTPUT NOISE = 
4
= 0.4µVRMS

IN LT3045 LT3045 IN

100µA 100µA

EN/UV
– – EN/UV
+ +
PGFB PGFB
OUT OUT
PG 20mΩ 20mΩ PG
OUTS OUTS
SET GND ILIM 10µF 10µF ILIM GND SET

4.7µF 8.25k

3045 TA09

Rev. C

For more information www.analog.com 27

LT3045
TYPICAL APPLICATIONS
Low Noise Wheatstone Bridge Power Supply

LT1763 NOISE: 20µVRMS (10Hz TO 100kHz)

LT3045 NOISE: 0.8µVRMS (10Hz TO 100kHz)
RESISTOR NOISE AT VBRIDGE NOISE AT VBRIDGE
BRIDGE PSRR
TOLERANCE USING LT1763 USING LT3045
PERFECT
LT3045 INFINITE – –
VIN IN MATCHING
5V ±5%
1% 40dB 200nVRMS 8nVRMS
4.7µF 100µA

EN/UV
– 5% 26dB 1000nVRMS 42.5nVRMS
+
200k
OUT VOUT: 3.3V AND IOUT(MAX): 500mA
PG
R1 R3
OUTS
VBRIDGE
SET GND ILIM PGFB 10µF 453k
+ –

R2 R4
4.7µF 33.2k 49.9k

3045 TA10

PGFB Disabled without Reverse Input Protection PGFB Disabled with Reverse Input Protection

IN LT3045 IN LT3045
VIN VIN

4.7µF 100µA 4.7µF 100µA

EN/UV
– EN/UV
–
+ +
PGFB 1N4148
OUT OUT
VOUT VOUT
PG PGFB
OUTS OUTS
SET GND ILIM 10µF PG SET GND ILIM 10µF

0.47µF RSET 0.47µF RSET

3045 TA11 3045 TA12

Rev. C

28 For more information www.analog.com

 LT3045
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)

0.70 ±0.05

3.55 ±0.05 1.65 ±0.05

2.15 ±0.05 (2 SIDES)

PACKAGE
OUTLINE

0.25 ±0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.125 0.40 ±0.10
TYP
6 10

3.00 ±0.10 1.65 ±0.10

(4 SIDES) (2 SIDES) PIN 1 NOTCH
PIN 1 R = 0.20 OR
TOP MARK 0.35 × 45°
(SEE NOTE 6) CHAMFER
(DD) DFN REV C 0310

5 1
0.200 REF 0.75 ±0.05 0.25 ±0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

Rev. C

For more information www.analog.com 29

LT3045
PACKAGE DESCRIPTION
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev G)

BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
2.845 ±0.102 (.112 ±.004)
(.112 ±.004) 0.889 ±0.127
(.035 ±.005) 1 6 0.35
REF

5.10 1.651 ±0.102

1.651 ±0.102 3.20 – 3.45 0.12 REF
(.201) (.065 ±.004)
MIN (.065 ±.004) (.126 – .136) DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
12 7 FOR REFERENCE ONLY
0.65 NO MEASUREMENT PURPOSE
0.42 ±0.038 4.039 ±0.102
(.0165 ±.0015) (.0256) (.159 ±.004)
TYP BSC (NOTE 3) 0.406 ±0.076
RECOMMENDED SOLDER PAD LAYOUT
12 11 10 9 8 7 (.016 ±.003)
REF
DETAIL “A”
0.254
(.010) 3.00 ±0.102
0° – 6° TYP 4.90 ±0.152
(.118 ±.004)
(.193 ±.006) (NOTE 4)
GAUGE PLANE

0.53 ±0.152
(.021 ±.006)
1 2 3 4 5 6
DETAIL “A” 1.10 0.86
0.18 (.043) (.034)
(.007) MAX REF

SEATING
PLANE 0.22 – 0.38 0.1016 ±0.0508
(.009 – .015) (.004 ±.002)
0.650
TYP MSOP (MSE12) 0213 REV G
NOTE: (.0256)
1. DIMENSIONS IN MILLIMETER/(INCH) BSC
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.

Rev. C

30 For more information www.analog.com

 LT3045
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 10/17 Added H-grade options. 2, 23
Modified Quiescent Current in Shutdown specs. 4
Modified Note 9. 5
Modified PGFB description. 12
B 10/19 Added MP-Grade option. 2, 3, 4, 5, 22, 23
C 03/21 Added AEC-Q100 Qualified for Automotive Applications to features table. 1
Added AUTOMOTIVE PRODUCTS** table and supplemental text. 2
Added information to Programmable Power Good. 20
Updated VOUT(PG_THRESHOLD) formula. 20

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For more by
is granted information www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices. 31
LT3045
TYPICAL APPLICATION
Parallel Devices

VIN IN LT3045
5V ±5%
10µF 100µA
EN/UV –
+ 20mΩ
OUT
PGFB
OUTS

SET GND ILIM PG 10µF

VOUT
3.3V
IN LT3045 IOUT(MAX)
1A
100µA
EN/UV –
+ 20mΩ
OUT
PGFB OUTS

SET GND ILIM PG 10µF

3045 TA13

16.5k 0.47µF

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LT3085 500mA, Parallelable, Low Noise, Low Dropout Linear 275mV Dropout (2-Supply Operation), Low Noise: 40μVRMS, VIN: 1.2V
Regulator to 36V, VOUT: 0V to 35.7V, Current-Based Reference with 1-Resistor
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Rev. C

32
03/21
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