LT3083

Adjustable 3A
Single Resistor Low
Dropout Regulator
FEATURES DESCRIPTION
n Outputs May be Paralleled for Higher Current and The LT®3083 is a 3A low dropout linear regulator that can
Heat Spreading be paralleled to increase output current or spread heat on
n Output Current: 3A surface mounted boards. Architected as a precision current
n Single Resistor Programs Output Voltage source and voltage follower, this new regulator finds use
n 50μA Set Pin Current: 1% Initial Accuracy in many applications requiring high current, adjustability
n Output Adjustable to 0V to zero, and no heat sink. The device also brings out the
n Low Output Noise: 40μVRMS (10Hz to 100kHz) collector of the pass transistor to allow low dropout opera-
n Wide Input Voltage Range: 1.2V to 23V tion—down to 310mV—when used with multiple supplies.
(DD-Pak and TO-220 Packages)
n Low Dropout Voltage: 310mV A key feature of the LT3083 is the capability to supply a
n <1mV Load Regulation wide output voltage range. By using a reference current
n <0.001%/V Line Regulation through a single resistor, the output voltage is programmed
n Minimum Load Current: 1mA to any level between zero and 23V (DD-PAK and TO-220
n Stable with Minimum 10μF Ceramic Capacitor packages). The LT3083 is stable with 10μF of capacitance
n Current Limit with Foldback and Overtemperature on the output, and the IC is stable with small ceramic ca-
Protection pacitors that do not require additional ESR as is common
n Available in 16-Lead TSSOP, 12-Lead 4mm × 4mm with other regulators.
DFN, 5-Lead TO-220 and 5-Lead Surface Mount Internal protection circuitry includes current limiting and
DD-PAK Packages thermal limiting. The LT3083 is offered in the 16-lead
TSSOP (with an exposed pad for better thermal character-
APPLICATIONS istics), 12-lead 4mm × 4mm DFN (also with an exposed
n High Current All Surface Mount Supply pad), 5-lead TO-220, and 5-lead surface mount DD-PAK
n High Efficiency Linear Regulator packages.
n Post Regulator for Switching Supplies L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
n Low Parts Count Variable Voltage Supply Technology Corporation. All other trademarks are the property of their respective owners.

n Low Output Voltage Power Supplies

TYPICAL APPLICATION Set Pin Current Distribution

1.5V to 0.9V at 3A Supply (Using 3.3V VCONTROL) N = 1052

VCONTROL
3.3V
4.7μF
VCONTROL

VIN LT3083 VOUT = 0.9V

IN OUT IMAX = 3A
1.5V
10μF SET 10μF *RMIN
3083 TA01a 909Ω
*OPTIONAL FOR
MINIMUM 1mA LOAD
RSET REQUIREMENT
0.1μF
18.2k
1%
49 49.5 50 50.5 51
SET PIN CURRENT DISTRIBUTION (μA)
3083 TA01b
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LT3083
ABSOLUTE MAXIMUM RATINGS
(Note 1) All Voltages Relative to VOUT
CONTROL Pin Voltage.............................................±28V Output Short-Circuit Duration .......................... Indefinite
IN Pin Voltage (T5, Q Packages) ....................18V, –0.3V Operating Junction Temperature Range (Notes 2, 10)
No Overload or Short-Circuit .....................23V, –0.3V E-, I-grades ........................................ –40°C to 125°C
IN Pin Voltage (DF, FE Packages) .....................8V, –0.3V MP-grade ........................................... –55°C to 125°C
No Overload or Short-Circuit .....................14V, –0.3V Storage Temperature Range .................. –65°C to 150°C
SET Pin Current (Note 7) .....................................±25mA Lead Temperature (Soldering, 10 sec)
SET Pin Voltage (Relative to OUT) .......................... ±10V T, Q, FE Packages Only ..................................... 300°C

PIN CONFIGURATION
TOP VIEW

OUT 1 16 OUT
TOP VIEW
OUT 2 15 IN
OUT 1 12 IN
OUT 3 14 IN
OUT 2 11 IN
OUT 3 13 10 IN OUT 4 17 13 IN
OUT 4 OUT 9 IN OUT 5 OUT 12 IN
OUT 5 8 VCONTROL OUT 6 11 VCONTROL
SET 6 7 VCONTROL
SET 7 10 VCONTROL
DF PACKAGE OUT 8 9 OUT
12-LEAD (4mm s 4mm) PLASTIC DFN
TJMAX = 125°C, θJA = 37°C/W, θJC = 8°C/W FE PACKAGE
EXPOSED PAD (PIN 13) IS OUT, MUST BE SOLDERED TO PCB 16-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 25°C/W, θJC = 8°C/W
EXPOSED PAD (PIN 17) IS OUT, MUST BE SOLDERED TO PCB

FRONT VIEW FRONT VIEW

5 IN 5 IN
4 VCONTROL 4 VCONTROL
TAB IS TAB IS
3 OUT OUT 3 OUT
OUT
2 SET 2 SET
1 NC 1 NC

Q PACKAGE T PACKAGE
5-LEAD PLASTIC DD-PAK 5-LEAD PLASTIC TO-220
TJMAX = 125°C, θJA = 15°C/W, θJC = 3°C/W TJMAX = 125°C, θJA = 40°C/W, θJC = 3°C/W

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3083EDF#PBF LT3083EDF#TRPBF 3083 12-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C
LT3083EFE#PBF LT3083EFE#TRPBF 3083FE 16-Lead Plastic TSSOP –40°C to 125°C
LT3083EQ#PBF LT3083EQ#TRPBF LT3083Q 5-Lead Plastic DD-PAK –40°C to 125°C
LT3083ET#PBF LT3083ET#TRPBF LT3083T 5-Lead Plastic TO-220 –40°C to 125°C
LT3083IDF#PBF LT3083IDF#TRPBF 3083 12-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C
LT3083IFE#PBF LT3083IFE#TRPBF 3083FE 16-Lead Plastic TSSOP –40°C to 125°C
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 LT3083
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3083IQ#PBF LT3083IQ#TRPBF LT3083Q 5-Lead Plastic DD-PAK –40°C to 125°C
LT3083IT#PBF LT3083IT#TRPBF LT3083T 5-Lead Plastic TO-220 –40°C to 125°C
LT3083MPDF#PBF LT3083MPDF#TRPBF 083MP 12-Lead (4mm × 4mm) Plastic DFN –55°C to 125°C
LT3083MPFE#PBF LT3083MPFE#TRPBF 3083MPFE 16-Lead Plastic TSSOP –55°C to 125°C
LT3083MPQ#PBF LT3083MPQ#TRPBF LT3083MPQ 5-Lead Plastic DD-PAK –55°C to 125°C
LT3083MPT#PBF LT3083MPT#TRPBF LT3083MPT 5-Lead Plastic TO-220 –55°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3083EDF LT3083EDF#TR 3083 12-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C
LT3083EFE LT3083EFE#TR 3083FE 16-Lead Plastic TSSOP –40°C to 125°C
LT3083EQ LT3083EQ#TR LT3083Q 5-Lead Plastic DD-PAK –40°C to 125°C
LT3083ET LT3083ET#TR LT3083T 5-Lead Plastic TO-220 –40°C to 125°C
LT3083IDF LT3083IDF#TR 3083 12-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C
LT3083IFE LT3083IFE#TR 3083FE 16-Lead Plastic TSSOP –40°C to 125°C
LT3083IQ LT3083IQ#TR LT3083Q 5-Lead Plastic DD-PAK –40°C to 125°C
LT3083IT LT3083IT#TR LT3083T 5-Lead Plastic TO-220 –40°C to 125°C
LT3083MPDF LT3083MPDF#TR 083MP 12-Lead (4mm × 4mm) Plastic DFN –55°C to 125°C
LT3083MPFE LT3083MPFE#TR 3083MPFE 16-Lead Plastic TSSOP –55°C to 125°C
LT3083MPQ LT3083MPQ#TR LT3083MPQ 5-Lead Plastic DD-PAK –55°C to 125°C
LT3083MPT LT3083MPT#TR LT3083MPT 5-Lead Plastic TO-220 –55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2).
PARAMETER CONDITIONS MIN TYP MAX UNITS
SET Pin Current ISET VIN = 1V, VCONTROL = 2V, ILOAD = 1mA, TJ = 25°C 49.5 50 50.5 μA
VIN ≥ 1V, VCONTROL ≥ 2V, 5mA ≤ ILOAD ≤ 3A (Note 9) l 49 50 51 μA
Output Offset Voltage (VOUT – VSET) VOS DF, FE Packages –3 0 3 mV
VIN = 1V, VCONTROL = 2V, ILOAD = 1mA l –4 0 4 mV
T, Q Packages –4 0 4 mV
l –6 0 6 mV
Load Regulation (DF, FE Packages) ΔISET ΔILOAD = 1mA to 3A –10 nA
ΔVOS ΔILOAD = 5mA to 3A (Note 8) l –0.4 –1 mV
Load Regulation (T, Q Packages) ΔISET ΔILOAD = 1mA to 3A –10 nA
ΔVOS ΔILOAD = 5mA to 3A (Note 8) l –0.7 –4 mV
Line Regulation (DF, FE Packages) ΔISET ΔVIN = 1V to 14V, ΔVCONTROL = 2V to 25V, ILOAD = 1mA 0.1 nA/V
ΔVOS ΔVIN = 1V to 14V, ΔVCONTROL = 2V to 25V, ILOAD = 1mA 0.002 0.01 mV/V
Line Regulation (T, Q Packages) ΔISET ΔVIN = 1V to 23V, ΔVCONTROL = 2V to 25V, ILOAD = 1mA 0.1 nA/V
ΔVOS ΔVIN = 1V to 23V, ΔVCONTROL = 2V to 25V, ILOAD = 1mA 0.002 0.01 mV/V
Minimum Load Current (Notes 3, 9) VIN = 1V, VCONTROL = 2V l 350 500 μA
VIN = 14V (DF/FE) or 23V (T/Q), VCONTROL = 25V l 1 mA

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LT3083
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2).
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCONTROL Dropout Voltage (Note 4) ILOAD = 100mA 1.2 V
ILOAD = 1A l 1.22 1.55 V
ILOAD = 3A l 1.25 1.6 V
VIN Dropout Voltage (Note 4) ILOAD = 100mA l 10 25 mV
ILOAD = 1A, Q, T Packages l 120 190 mV
ILOAD = 1A, DF, FE Packages l 90 160 mV
ILOAD = 3A, Q, T Packages l 310 510 mV
ILOAD = 3A, DF, FE Packages l 240 420 mV
VCONTROL Pin Current (Note 5) ILOAD = 100mA l 5.5 10 mA
ILOAD = 1A l 18 35 mA
ILOAD = 3A l 40 80 mA
Current Limit VIN = 5V, VCONTROL = 5V, VSET = 0V, VOUT = –0.1V l 3 3.7 A
Error Amplifier RMS Output Noise (Note 6) ILOAD = 500mA, 10Hz ≤ f ≤ 100kHz, COUT = 10μF, CSET = 0.1μF 40 μVRMS
Reference Current RMS Output Noise (Note 6) 10Hz ≤ f ≤ 100kHz 1 nARMS
Ripple Rejection f = 120Hz 85 dB
VRIPPLE = 0.5VP-P, IL = 0.1A, CSET = 0.1μF, f = 10kHz 75 dB
COUT = 10μF f = 1MHz 20 dB
Thermal Regulation, ISET 10ms Pulse 0.003 %/W

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: The VCONTROL pin current is the drive current required for the
may cause permanent damage to the device. Exposure to any Absolute output transistor. This current will track output current with roughly a 1:60
Maximum Rating condition for extended periods may affect device ratio. The minimum value is equal to the quiescent current of the device.
reliability and lifetime. Note 6: Output noise is lowered by adding a small capacitor across the
Note 2: Unless otherwise specified, all voltages are with respect to VOUT. voltage setting resistor. Adding this capacitor bypasses the voltage setting
The LT3083 is tested and specified under pulse load conditions such that resistor shot noise and reference current noise; output noise is then equal
TJ ≅ TA. The LT3083E is 100% tested at TA = 25°C. Performance of the to error amplifier noise (see the Applications Information section).
LT3083E over the full –40°C to 125°C operating junction temperature Note 7: The SET pin is clamped to the output with diodes through 1k
range is assured by design, characterization, and correlation with resistors. These resistors and diodes will only carry current under
statistical process controls. The LT3083I regulators are guaranteed transient overloads.
over the full –40°C to 125°C operating junction temperature range. The Note 8: Load regulation is Kelvin sensed at the package.
LT3083MP is 100% tested and guaranteed over the –55°C to 125°C
Note 9: Current limit includes foldback protection circuitry. Current limit
operating junction temperature range.
decreases at higher input-to-output differential voltages.
Note 3: Minimum load current is equivalent to the quiescent current of
Note 10: This IC includes overtemperature protection that is intended
the part. Since all quiescent and drive current is delivered to the output
to protect the device during momentary overload conditions. Junction
of the part, the minimum load current is the minimum current required to
temperature will exceed the maximum operating junction temperature
maintain regulation.
when overtemperature protection is active. Overtemperature protection
Note 4: For the LT3083, dropout is caused by either minimum control (thermal limit) is typically active at junction temperatures of 165°C.
voltage (VCONTROL) or minimum input voltage (VIN). Both parameters are Continuous operation above the specified maximum operating junction
specified with respect to the output voltage. The specifications represent temperature may impair device reliability.
the minimum input-to-output differential voltage required to maintain
regulation.

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 LT3083
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

SET Pin Current Set Pin Current Distribution Offset Voltage (VOUT – VSET)
50.5 1.0
N = 1052 ILOAD = 5mA
50.4 0.8
50.3 0.6

OFFSET VOLTAGE (mV)

SET PIN CURRENT (μA)

50.2 0.4
50.1 0.2
50.0 0
49.9 –0.2
49.8 –0.4
49.7 –0.6
49.6 –0.8
49.5 –1.0
–50 –25 0 25 50 75 100 125 150 49 49.5 50 50.5 51 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) SET PIN CURRENT DISTRIBUTION (μA) TEMPERATURE (°C)
3083 G01 3083 G02 3083 G03

Offset Voltage Distribution Offset Voltage (VOUT – VSET) Offset Voltage (VOUT – VSET)
1.00 0.25
N = 1052 ILOAD = 5mA
0.75 0 TJ = 25°C
0.50 –0.25
OFFSET VOLTAGE (mV)

0.25 OFFSET VOLTAGE (mV) –0.50 TJ = 125°C

0 –0.75

–0.25 –1.00

–0.50 –1.25

–0.75 –1.50

–1.00 –1.75
–3 –2 –1 0 1 2 3 0 5 10 15 20 25 0 0.5 1 1.5 2 2.5 3
VOS DISTRIBUTION (mV) INPUT-TO-OUTPUT VOLTAGE (V) LOAD CURRENT (A)
3083 G04 3083 G05 3083 G06

Dropout Voltage, T/Q Packages

Load Regulation Minimum Load Current (Minimum IN Voltage)
CHANGE IN REFERENCE CURRENT WITH LOAD (nA)

0 100 1.4 400

CHANGE IN OFFSET VOLTAGE WITH LOAD (mV)

VIN = VCONTROL
CHANGE IN OFFSET VOLTAGE (VOUT – VSET)
MINIMUM VOLTAGE (VIN – VOUT) (mV)

–0.2 50 1.2 350

MINIMUM LOAD CURRENT (mA)

TJ = 125°C
–0.4 0 300
1.0
CHANGE IN REFERENCE CURRENT VIN,CONTROL – VOUT = 23V 250
–0.6 –50 TJ = 25°C
0.8
–0.8 –100 200
0.6 TJ = –50°C
–1.0 –150 VIN, CONTROL – VOUT = 1.5V 150
0.4
–1.2 –200 100

–1.4 ΔILOAD = 5mA TO 3A –250 0.2 50

VIN = VCONTROL = VOUT + 2V
–1.6 –300 0 0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 0 0.5 1 1.5 2 2.5 3
TEMPERATURE (°C) TEMPERATURE (°C) LOAD CURRENT (A)
3083 G07 3083 G08 3083 G09

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LT3083
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Dropout Voltage, T/Q Packages Dropout Voltage, FE/DF Packages

Dropout Voltage, FE/DF Packages (Minimum IN Voltage) (Minimum IN Voltage)
400 500 500

MINIMUM IN VOLTAGE (VIN – VOUT) (mV)

MINIMUM IN VOLTAGE (VIN – VOUT) (mV)
450 450
MINIMUM VOLTAGE (VIN – VOUT) (mV)

350
TJ = 125°C 400 400
300
350 ILOAD = 3A 350 ILOAD = 3A
250 TJ = 25°C 300 300
200 250 250
ILOAD = 1.5A
ILOAD = 1.5A
150 200 200
TJ = –50°C
150 150
100
100 ILOAD = 500mA 100 ILOAD = 500mA
50 50 50
ILOAD = 100mA ILOAD = 100mA
0 0 0
0 0.5 1 1.5 2 2.5 3 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
LOAD CURRENT (A) TEMPERATURE (°C) TEMPERATURE (°C)
3083 G10 3083 G11 3083 G12

Dropout Voltage (Minimum Dropout Voltage (Minimum

VCONTROL Pin Voltage) VCONTROL Pin Voltage)
1.6 1.6

1.4 1.4 ILOAD = 3A

MINIMUM VCONTROL PIN VOLTAGE

MINIMUM VCONTROL PIN VOLTAGE

TJ = –50°C
1.2 TJ = 25°C 1.2
(VCONTROL – VOUT) (V)

(VCONTROL – VOUT) (V)

1.0 1.0
TJ = 125°C
0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0 0
0 0.5 1 1.5 2 2.5 3 –50 –25 0 25 50 75 100 125 150
LOAD CURRENT (A) TEMPERATURE (°C)
3083 G13 3083 G14

Current Limit Current Limit

5.0 4.0
TJ = 25°C
4.5 3.5
4.0
3.0
3.5
CURRENT LIMIT (A)

CURRENT LIMIT (A)

3.0 2.5

2.5 2.0
2.0 1.5
1.5
1.0
1.0
0.5 VIN = VCONTROL = 7V 0.5
VOUT = 0V
0 0
–50 –25 0 25 50 75 100 125 150 0 5 10 15 20
TEMPERATURE (°C) IN-TO-OUT DIFFERENTIAL (VIN – VOUT) (V)
3083 G15 3083 G16

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 LT3083
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Load Transient Response Load Transient Response

150 250
VIN = 2V
OUTPUT VOLTAGE

VIN = 2V
DEVIATION (mV)

150 VCONTROL = 3V

LOAD CURRENT (A) OUTPUT VOLTAGE

100 VCONTROL = 3V

DEVIATION (mV)
VOUT = 1V VOUT = 1V
COUT = 22μF CERAMIC 50 CSET = 0.1μF
50 CSET = 0.1μF

–50 COUT = 22μF CERAMIC

0

–50 –150
COUT = 10μF CERAMIC
LOAD CURRENT (A)

–100 4

1.0 2
ΔILOAD = 500mA TO 3A

0.5 0
ΔILOAD = 100mA TO 1A

0
0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200
TIME (μs) TIME (μs)
3083 G18
3083 G17

Line Transient Response Turn-On Response Turn-On Response

7 6 4
VOUT = 1V
6 ILOAD = 10mA 5
3
IN/ VCONTROL
VOLTAGE (V)

COUT = 10μF CERAMIC

IN/ VCONTROL
VOLTAGE (V)

IN/ VCONTROL
VOLTAGE (V)
4
5 CSET = 0.1μF 2
3
4 1
2
3 1 0
OUTPUT VOLTAGE
DEVIATION (mV)

10 0
1.0
1.0
VOLTAGE (V)

VOLTAGE (V)

0 0.5
OUTPUT

OUTPUT

RSET = 20k RSET = 20k

0.5
CSET = 0 CSET = 0.1μF
–10 0 RLOAD = 0.33Ω 0 RLOAD = 1Ω
COUT = 10μF CERAMIC COUT = 10μF CERAMIC
–20 –0.5 –0.5
0 20 40 60 80 100 120 140 160 180 200 0 5 10 15 20 25 30 35 40 45 50 0 2 4 6 8 10 12 14 16 18 20
TIME (μs) TIME (μs) TIME (ms)
3083 G19 3083 G20 3083 G21

Residual Output Voltage with

VCONTROL Pin Current VCONTROL Pin Current Less Than Minimum Load
80 70 600
VCONTROL – VOUT = 2V
70 VIN – VOUT = 1V VIN = 20V
60
500
VCONTROL PIN CURRENT (mA)
VCONTROL PIN CURRENT (mA)

60 VIN = 10V
OUTPUT VOLTAGE (mV)

50
TJ = –50°C 400
50
40 VIN = 5V
40 300 ADD 1N4148 FOR
ILOAD = 3A 30 RTEST < 1k
TJ = 25°C
30
200 SET PIN = 0V
DEVICE IN 20
20 CURRENT LIMIT VIN VOUT
TJ = 125°C
ILOAD = 1.5A 100 RTEST
10 10

0 0 0
0 2 4 6 8 10 12 14 16 18 0 0.5 1 1.5 2 2.5 3 0 500 1000 1500 2000
IN-TO-OUT DIFFERENTIAL (VIN – VOUT) (V) LOAD CURRENT (A) RSET (Ω)
3083 G22 3083 G23 3083 G24

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LT3083
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Ripple Rejection, Dual Supply, Ripple Rejection, Dual Supply,

Ripple Rejection, Single Supply VCONTROL Pin IN Pin
100 120 120
ILOAD = 0.1A ILOAD = 0.1A
90 105 105
80 ILOAD = 0.5A
90 ILOAD = 0.1A 90
RIPPLE REJECTION (dB)

RIPPLE REJECTION (dB)

RIPPLE REJECTION (dB)

70
60 75 75
ILOAD = 1.5A
50 ILOAD = 0.5A 60 I 60
LOAD = 1.5A
40 ILOAD = 1.5A
45 45
30
COUT = 10μF CERAMIC 30 COUT = 10μF CERAMIC 30 COUT = 10μF CERAMIC
20 CSET = 0.1μF CERAMIC CSET = 0.1μF CSET = 0.1μF
10 RIPPLE = 50mVP-P 15 VIN = VOUT(NOMINAL) + 1V 15 VIN = VOUT(NOMINAL) + 1V
VIN – VCONTROL = VOUT(NOMINAL) + 2V VCONTROL = VOUT(NOMINAL) + 2V VCONTROL = VOUT(NOMINAL) + 2V
0 0 0
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
3083 G25 3083 G26 3083 G27

Ripple Rejection (120Hz) Noise Spectral Density

80 1000 100
79
SPECTRAL DENSITY (nV/√Hz)

SPECTRAL DENSITY (pA/√Hz)

78

REFERENCE CURRENT NOISE

ERROR AMPLIFIER NOISE
RIPPLE REJECTOIN (dB)

77
76
75 100 10
74
73
VIN = VCONTROL = VOUT(NOMINAL) + 2V
72 RIPPLE = 500mVP-P, ƒ = 120Hz
ILOAD = 0.5A
71
CSET = 0.1μF, COUT = 10μF
70 10 1
–50 –25 0 25 50 75 100 125 150 10 100 1k 10k 100k
TEMPERATURE (°C) FREQUENCY (Hz)
3083 G28 3083 G29

Output Voltage Noise Error Amplifier Gain and Phase

21 36
18 0
PHASE
15 –36
12 –72
9 –108
GAIN (dB)

6 –144
VOUT
100μV/DIV 3 –180
0 –216
GAIN
–3 –252
–6 –288
–9 ILOAD = 0.5A –324
ILOAD = 1.5A
–12 ILOAD = 3A –360
3083 G30 –15 –396
TIME 1ms/DIV 10 100 1k 10k 100k 1M
VOUT = 1V, RSET = 20k FREQUENCY (Hz)
CSET = 0.1μF, COUT = 10μF
3083 G31
ILOAD = 3A

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 LT3083
PIN FUNCTIONS (DF/FE/Q/T Packages)

OUT (Pins 1-5,13/Pins 1-6,8,9,16,17/ Pin 3, Tab/Pin 3, VCONTROL (Pins 7,8/Pins 10,11/Pin 4/Pin 4): Bias Sup-
Tab): Output. The exposed pad of the DF package (Pin 13) ply. This is the supply pin for the control circuitry of the
and the FE package (Pin 17) and the Tab of the DD-PAK device. Minimum input capacitance is 2.2μF (see Input
and TO-220 packages is an electrical connection to OUT. Capacitance and Stability in the Applications Information
Connect the exposed pad of the DF and FE packages and section). The current flow into this pin is about 1.7% of
the Tab of the DD-PAK package directly to OUT on the the output current. For the device to regulate, this voltage
PCB and the respective OUT pins for each package. There must be more than 1.2V to 1.4V greater than the output
must be a minimum load current of 1mA or the output voltage (see dropout specifications in the Electrical Char-
may not regulate. acteristics section).
SET (Pin 6/Pin 7/Pin 2/Pin 2): Set Point. This pin is the IN (Pins 9-12/Pins 12-15/Pin 5/Pin 5): Power Input. This
non-inverting input to the error amplifier and the regula- is the collector to the power device of the LT3083. The
tion set point. A fixed current of 50μA flows out of this output load current is supplied through this pin. Minimum
pin through a single external resistor, which programs IN capacitance is 10μF (see Input Capacitance and Stabil-
the output voltage of the device. Output voltage range is ity in Applications Information section). For the device to
zero to the VIN(MAX) – VDROPOUT. Transient performance regulate, the voltage at this pin must be more than 0.1V
can be improved by adding a small capacitor from the to 0.5V greater than the output voltage (see dropout
SET pin to ground. specifications in the Electrical Characteristics section).
NC (NA/NA/Pin 1/Pin 1): No Connection. No Connect pins
have no connection to internal circuitry and may be tied
to VIN, VCONTROL, VOUT, GND, or floated.

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LT3083
BLOCK DIAGRAM

IN

VCONTROL

50μA

3083 BD

SET OUT

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 LT3083
APPLICATIONS INFORMATION
The LT3083 regulator is easy to use and has all the protection The LT3083 has the collector of the output transistor con-
features expected in high performance regulators. Included nected to a separate pin from the control input. Since the
are short-circuit protection and safe operating area protec- dropout on the collector (IN pin) is typically only 310mV,
tion, as well as thermal shutdown with hysteresis. two supplies can be used to power the LT3083 to reduce
dissipation: a higher voltage supply for the control circuitry
The LT3083 fits well in applications needing multiple rails.
and a lower voltage supply for the collector. This increases
This new architecture adjusts down to zero with a single
efficiency and reduces dissipation. To further spread the
resistor, handling modern low voltage digital IC’s as well as
heat, a resistor inserted in series with the collector moves
allowing easy parallel operation and thermal management
some of the heat out of the IC to spread it on the PC board
without heat sinks. Adjusting to zero output allows shutting
(see the section Reducing Power Dissipation).
off the powered circuitry. When the input is pre-regulated,
such as with a 5V or 3.3V input supply, external resistors The LT3083 can be operated in two modes. Three termi-
can help spread the heat. nal mode has the VCONTROL pin connected to the IN pin
and gives a limitation of 1.25V dropout. Alternatively, the
A precision “0” TC 50μA reference current source connects
VCONTROL pin is separately tied to a higher voltage and the
to the noninverting input of a power operational amplifier.
IN pin to a lower voltage giving 310mV dropout on the IN
The power operational amplifier provides a low impedance
pin, minimizing total power dissipation. This allows for a
buffered output to the voltage on the noninverting input.
3A supply regulating from 2.5VIN to 1.8VOUT or 1.8VIN to
A single resistor from the noninverting input to ground
1.2VOUT with low power dissipation.
sets the output voltage. If this resistor is set to 0Ω, zero
output voltage results. Therefore, any output voltage can Programming Output Voltage
be obtained between zero and the maximum defined by
the input power supply. The LT3083 sources a 50μA reference current that flows
out of the SET pin. Connecting a resistor from SET to
The benefit of using a true internal current source as the ground generates a voltage that becomes the reference
reference, as opposed to a bootstrapped reference in older point for the error amplifier (see Figure 1). The refer-
regulators, is not so obvious in this architecture. A true ence voltage equals 50μA multiplied by the value of
reference current source allows the regulator to have gain the SET pin resistor. Any voltage can be generated and
and frequency response independent of the impedance on there is no minimum output voltage for the regulator.
the positive input. On older adjustable regulators, such as
the LT1086, loop gain changes with output voltage and
IN LT3083
bandwidth changes if the adjustment pin is bypassed to VCONTROL
ground. For the LT3083, the loop gain is unchanged with 50μA
output voltage changes or bypassing. Output regulation
+ + +
is not a fixed percentage of output voltage, but is a fixed VIN VCONTROL –
fraction of millivolts. Use of a true current source allows OUT
VOUT
all of the gain in the buffer amplifier to provide regulation, SET
and none of that gain is needed to amplify up the reference COUT
RSET CSET
to a higher output voltage.
3083 F01

VOUT = 50μA • RSET

Figure 1. Basic Adjustable Regulator

3083f

11
LT3083
APPLICATIONS INFORMATION
Table 1 lists many common output voltages and the clos-
est standard 1% resistor values used to generate that
output voltage. OUT

Regulation of the output voltage requires a minimum

load current of 1mA. For a true zero voltage output
operation, return this 1mA load current to a negative
supply voltage.
Table 1. 1% Resistors for Common Output Voltages
VOUT (V) RSET (k) GND
SET PIN 3083 F02
1 20
1.2 24.3 Figure 2. Guard Ring Layout Example
1.5 30.1 for DF Package
1.8 35.7
2.5 49.9 to remedy this is to bypass the SET pin with a small
3.3 66.5 amount of capacitance from SET to ground, 10pF to
5 100 20pF is sufficient.
With the lower level current used to generate the refer-
ence voltage, leakage paths to or from the SET pin can Stability and Input Capacitance
create errors in the reference and output voltages. High Typical minimum input capacitance is 10μF for IN and
quality insulation should be used (e.g., Teflon, Kel-F); 2.2μF for VCONTROL. These amounts of capacitance work
cleaning of all insulating surfaces to remove fluxes and well using low ESR ceramic capacitors when placed close
other residues will probably be required. Surface coating to the LT3083 and the circuit is located in close proximity
may be necessary to provide a moisture barrier in high to the power source. Higher values of input capacitance
humidity environments. may be necessary to maintain stability depending on the
Minimize board leakage by encircling the SET pin and application.
circuitry with a guard ring operated at a potential close Oscillating regulator circuits are often viewed as a problem
to itself. Tie the guard ring to the OUT pin. Guard rings of phase margin and inadequate stability with the output
on both sides of the circuit board are required. Bulk leak- capacitor used. More and more frequently, the problem
age reduction depends on the guard ring width. 50nA is not the regulator operating without sufficient output
of leakage into or out of the SET pin and its associated capacitance, but instead with too little input capacitance.
circuitry creates a 0.1% reference voltage error. Leakages The entire circuit must be analyzed and debugged as a
of this magnitude, coupled with other sources of leakage, whole; conditions relating to the input of the regulator
can cause significant offset voltage and reference drift, cannot be ignored.
especially over the possible operating temperature range.
The LT3083 input presents a high impedance to its power
Figure 2 depicts an example of a guard ring layout.
source: the output voltage and load current are independent
If guard ring techniques are used, this bootstraps any of input voltage variations. To maintain stability of the
stray capacitance at the SET pin. Since the SET pin is regulator circuit as a whole, the LT3083 must be powered
a high impedance node, unwanted signals may couple from a low impedance supply. When using short supply
into the SET pin and cause erratic behavior. This will lines or powering directly from a large switching supply,
be most noticeable when operating with minimum there is no issue—hundreds or thousands of microfarads
output capacitors at full load current. The easiest way of capacitance are available through a low impedance.

3083f

12
 LT3083
APPLICATIONS INFORMATION
When longer supply lines, filters, current sense resistors, to reduce overall inductance is to place both forward and
or other impedances exist between the supply and the return current conductors (the input and GND wires) in
input to the LT3083, input bypassing should be reviewed very close proximity. Two 30-AWG wires separated by only
if stability concerns are seen. Just as output capacitance 0.02", used as forward- and return- current conductors,
supplies the instantaneous changes in load current for reduce the overall self-inductance to approximately one-
output transients until the regulator is able to respond, fifth that of a single isolated wire.
input capacitance supplies local power to the regulator until
If wiring modifications are not permissible for the applica-
the main supply responds. When impedance separates the
tions, including series resistance between the power supply
LT3083 from its main supply, the local input can droop
and the input of the LT3083 also stabilizes the application.
so that the output follows. The entire circuit may break
As little as 0.1Ω to 0.5Ω, often less, is effective in damping
into oscillations, usually characterized by larger amplitude
the LC resonance. If the added impedance between the
oscillations on the input and coupling to the output.
power supply and the input is unacceptable, adding ESR to
Low ESR, ceramic input bypass capacitors are acceptable the input capacitor also provides the necessary damping of
for applications without long input leads. However, applica- the LC resonance. However, the required ESR is generally
tions connecting a power supply to an LT3083 circuit’s IN higher than the series impedance required.
and GND pins with long input wires combined with low
ESR, ceramic input capacitors are prone to voltage spikes, Stability and Output Capacitance
reliability concerns and application-specific board oscil- The LT3083 requires an output capacitor for stability. It
lations. The input wire inductance found in many battery is designed to be stable with most low ESR capacitors
powered applications, combined with the low ESR ceramic (typically ceramic, tantalum or low ESR electrolytic). A
input capacitor, forms a high-Q LC resonant tank circuit. In minimum output capacitor of 10μF with an ESR of 0.5Ω
some instances this resonant frequency beats against the or less is recommended to prevent oscillations. Larger
output current dependent LDO bandwidth and interferes values of output capacitance decrease peak deviations
with proper operation. Simple circuit modifications/solu- and provide improved transient response for larger load
tions are then required. This behavior is not indicative of current changes. Bypass capacitors, used to decouple
LT3083 instability, but is a common ceramic input bypass individual components powered by the LT3083, increase
capacitor application issue. the effective output capacitor value. For improvement in
The self-inductance, or isolated inductance, of a wire is transient performance, place a capacitor across the volt-
directly proportional to its length. Wire diameter is not a age setting resistor. Capacitors up to 1μF can be used.
major factor on its self-inductance. For example, the self- This bypass capacitor reduces system noise as well, but
inductance of a 2-AWG isolated wire (diameter = 0.26") is start-up time is proportional to the time constant of the
about half the self-inductance of a 30-AWG wire (diameter voltage setting resistor (RSET in Figure 1) and SET pin
= 0.01"). One foot of 30-AWG wire has about 465nH of bypass capacitor.
self-inductance. Give extra consideration to the use of ceramic capacitors.
One of two ways reduces a wire’s self-inductance. One Ceramic capacitors are manufactured with a variety of di-
method divides the current flowing towards the LT3083 electrics, each with different behavior across temperature
between two parallel conductors. In this case, the farther and applied voltage. The most common dielectrics used
apart the wires are from each other, the more the self-in- are specified with EIA temperature characteristic codes of
ductance is reduced; up to a 50% reduction when placed Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are
a few inches apart. Splitting the wires basically connects good for providing high capacitances in a small package,
two equal inductors in parallel, but placing them in close but they tend to have strong voltage and temperature
proximity gives the wires mutual inductance adding to coefficients as shown in Figures 3 and 4. When used with
the self-inductance. The second and most effective way a 5V regulator, a 16V 10μF Y5V capacitor can exhibit an
3083f

13
LT3083
APPLICATIONS INFORMATION
20
BOTH CAPACITORS ARE 16V, effective value as low as 1μF to 2μF for the DC bias voltage
0
1210 CASE SIZE, 10μF
applied and over the operating temperature range. The X5R
X5R
and X7R dielectrics result in more stable characteristics
CHANGE IN VALUE (%)

–20 and are more suitable for use as the output capacitor.
The X7R type has better stability across temperature,
–40
while the X5R is less expensive and is available in higher
–60 values. Care still must be exercised when using X5R and
Y5V
X7R capacitors. The X5R and X7R codes only specify
–80
operating temperature range and maximum capacitance
–100
change over temperature. Capacitance change due to DC
0 2 4 6 8 10 12 14 16
DC BIAS VOLTAGE (V)
bias with X5R and X7R capacitors is better than Y5V and
3083 F03
Z5U capacitors, but can still be significant enough to drop
Figure 3. Ceramic Capacitor DC Bias Characteristics capacitor values below appropriate levels. Capacitor DC
40 bias characteristics tend to improve as component case
size increases, but expected capacitance at operating
20
voltage should be verified.
CHANGE IN VALUE (%)

0 X5R
Voltage and temperature coefficients are not the only
–20
sources of problems. Some ceramic capacitors have a
–40
Y5V
piezoelectric response. A piezoelectric device generates
–60
voltage across its terminals due to mechanical stress. In a
ceramic capacitor, the stress can be induced by vibrations
–80
BOTH CAPACITORS ARE 16V, in the system or thermal transients.
1210 CASE SIZE, 10μF
–100
–50 –25 0 25 50 75 100 125
Paralleling Devices
TEMPERATURE (°C)
3083 F04
Higher output current is obtained by paralleling multiple
Figure 4. Ceramic Capacitor Temperature Characteristics LT3083s together. Tie the individual SET pins together and
VIN LT3083
tie the individual IN pins together. Connect the outputs in
common using small pieces of PC trace as ballast resistors
VCONTROL to promote equal current sharing. PC trace resistance in
+
mΩ/inch is shown in Table 2. Ballasting requires only a
–
tiny area on the PCB.
OUT 10mΩ
Table 2. PC Board Trace Resistance
SET
WEIGHT (oz) 10mil WIDTH 20mil WIDTH
VIN VIN LT3083
4.8V 1 54.3 27.1
TO 20V
VCONTROL 2 27.1 13.6
Trace resistance is measured in mΩ/in
+
10μF
– The worst-case room temperature offset, only ±4mV
OUT 10mΩ VOUT
(DD-PAK, T Packages) between the SET pin and the OUT
3.3V
SET
6A pin, allows the use of very small ballast resistors.
10μF
33k As shown in Figure 5, each LT3083 has a small 10mΩ
3083 F05
ballast resistor, which at full output current gives better
than 80% equalized sharing of the current. The external
Figure 5. Parallel Devices
3083f

14
 LT3083
APPLICATIONS INFORMATION
resistance of 10mΩ (5mΩ for the two devices in paral- The LT3083’s noise advantage is that the unity gain follower
lel) only adds about 30mV of output regulation drop at presents no noise gain whatsoever from the SET pin to the
an output of 6A. With an output voltage of 3.3V, this only output. Thus, noise figures do not increase accordingly.
adds 1% to the regulation. Of course, paralleling more Error amplifier noise is typically 126.5nV/√Hz (40μVRMS)
than two LT3083s yields even higher output current. over the 10Hz to 100kHz bandwidth). The error amplifier’s
Spreading the devices on the PC board also spreads the noise is RMS summed with the other noise terms to give
heat. Series input resistors can further spread the heat if a final noise figure for the regulator.
the input-to-output difference is high. Curves in the Typical Performance Characteristics sec-
tion show noise spectral density and peak-to-peak noise
Quieting the Noise
characteristics for both the reference current and error
The LT3083 offers numerous noise performance advan- amplifier over the 10Hz to 100kHz bandwidth.
tages. Every linear regulator has its sources of noise. In
general, a linear regulator’s critical noise source is the Load Regulation
reference. In addition, consider the error amplifier’s noise The LT3083 is a floating device. No ground pin exists on
contribution along with the resistor divider’s noise gain. the packages. Thus, the IC delivers all quiescent current
Many traditional low noise regulators bond out the voltage and drive current to the load. Therefore, it is not possible
reference to an external pin (usually through a large value to provide true remote load sensing. The connection resis-
resistor) to allow for bypassing and noise reduction. The tance between the regulator and the load determines load
LT3083 does not use a traditional voltage reference like regulation performance. The data sheet’s load regulation
other linear regulators. Instead, it uses a 50μA reference specification is Kelvin sensed at the package’s pins. Nega-
current. The 50μA current source generates noise current tive-side sensing is a true Kelvin connection by returning
levels of 3.16pA/√Hz (1nARMS) over the 10Hz to 100kHz the bottom of the voltage setting resistor to the negative
bandwidth). The equivalent voltage noise equals the RMS side of the load (see Figure 6).
noise current multiplied by the resistor value.
Connected as shown, system load regulation is the sum
The SET pin resistor generates spot noise equal to √4kTR of the LT3083’s load regulation and the parasitic line
(k = Boltzmann’s constant, 1.38 • 10–23J/°K, and T is abso- resistance multiplied by the output current. To minimize
lute temperature) which is RMS summed with the voltage load regulation, keep the positive connection between the
noise. If the application requires lower noise performance, regulator and load as short as possible. If possible, use
bypass the voltage setting resistor with a capacitor to GND. large diameter wire or wide PC board traces.
Note that this noise-reduction capacitor increases start-up
time as a factor of the RC time constant. IN LT3083
VCONTROL
The LT3083 uses a unity-gain follower from the SET pin
to the OUT pin. Therefore, multiple possibilities exist PARASITIC
+
(besides a SET pin resistor) to set output voltage. For RESISTANCE
–
example, using a high accuracy voltage reference from OUT RP

SET to GND removes the errors in output voltage due to SET RSET RP LOAD
reference current tolerance and resistor tolerance. Active
driving of the SET pin is acceptable. RP

3080 F06
The typical noise scenario for a linear regulator is that the
output voltage setting resistor divider gains up the noise Figure 6. Connections for Best Load Regulation
reference, especially if VOUT is much greater than VREF.

3083f

15
LT3083
APPLICATIONS INFORMATION
Thermal Considerations Table 4. FE Package, 16-Lead TSSOP
COPPER AREA
The LT3083’s internal power and thermal limiting circuitry THERMAL RESISTANCE
TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
protects itself under overload conditions. For continuous
2500mm2 2500mm2 2500mm2 16°C/W
normal load conditions, do not exceed the 125°C maximum
1000mm2 2500mm2 2500mm2 20°C/W
junction temperature. Carefully consider all sources of
thermal resistance from junction-to-ambient. This includes 225mm2 2500mm2 2500mm2 26°C/W

(but is not limited to) junction-to-case, case-to-heat sink 100mm2 2500mm2 2500mm2 32°C/W

interface, heat sink resistance or circuit board-to-ambient *Device is mounted on topside.

as the application dictates. Consider all additional, adjacent
Table 5. Q Package, 5-Lead DD-PAK
heat generating sources in proximity on the PCB.
COPPER AREA THERMAL RESISTANCE
Surface mount packages provide the necessary heat TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
sinking by using the heat spreading capabilities of the 2500mm2 2500mm2 2500mm2 13°C/W
PC board, copper traces, and planes. Surface mount heat 1000mm2 2500mm2 2500mm2 14°C/W
sinks, plated through-holes and solder-filled vias can also 125mm2 2500mm2 2500mm2 16°C/W
spread the heat generated by power devices. *Device is mounted on topside.
Junction-to-case thermal resistance is specified from the
IC junction to the bottom of the case directly, or the bottom T Package, 5-Lead TO-220
of the pin most directly in the heat path. This is the lowest Thermal Resistance (Junction-to-Case) = 3°C/W
thermal resistance path for heat flow. Only proper device
mounting ensures the best possible thermal flow from this For further information on thermal resistance and using
area of the packages to the heat sinking material. thermal information, refer to JEDEC standard JESD51,
notably JESD51-12.
Note that the exposed pad of the DFN and TSSOP pack-
ages and the tab of the DD-PAK and TO-220 packages PCB layers, copper weight, board layout and thermal vias
are electrically connected to the output (VOUT). affect the resultant thermal resistance. Tables 3 through 5
provide thermal resistance numbers for best-case 4-layer
Tables 3 through 5 list thermal resistance as a function boards with 1oz internal and 2oz external copper. Modern,
of copper areas on a fixed board size. All measurements multilayer PCBs may not be able to achieve quite the same
were taken in still air on a 4-layer FR-4 board with 1oz level performance as found in these tables.
solid internal planes and 2oz external trace planes with a
total finished board thickness of 1.6mm. Layers are not Calculating Junction Temperature
connected electrically or thermally.
Example: Given an output voltage of 0.9V, a VCONTROL
Table 3. DF Package, 12-Lead DFN voltage of 3.3V ±10%, an IN voltage of 1.5V ±5%, output
COPPER AREA THERMAL RESISTANCE
current range from 10mA to 3A and a maximum ambient
TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT) temperature of 50°C, what will the maximum junction
2500mm2 2500mm2 2500mm2 18°C/W temperature be for the DD-PAK on a 2500mm2 board with
1000mm2 2500mm2 2500mm2 22°C/W topside copper of 1000mm2?
225mm2 2500mm2 2500mm2 29°C/W
100mm2 2500mm2 2500mm2 35°C/W
*Device is mounted on topside.

3083f

16
 LT3083
APPLICATIONS INFORMATION
The power in the drive circuit equals: As an example, assume: VIN = VCONTROL = 5V, VOUT = 3.3V
and IOUT(MAX) = 2A. Use the formulas from the Calculating
PDRIVE = (VCONTROL – VOUT)(ICONTROL)
Junction Temperature section previously discussed.
where ICONTROL is equal to IOUT/60. ICONTROL is a function
Without series resistor RS, power dissipation in the LT3083
of output current. A curve of ICONTROL vs IOUT can be found
equals:
in the Typical Performance Characteristics curves.
The total power equals: ⎛ 2A ⎞
PTOTAL = (5V − 3.3V ) • ⎜ ⎟ + (5V − 3.3V ) • 2A
PTOTAL = PDRIVE + POUTPUT ⎝ 60 ⎠
= 3.46W
The current delivered to the SET pin is negligible and can
be ignored. If the voltage differential (VDIFF) across the NPN pass
transistor is chosen as 0.5V, then RS equals:
VCONTROL(MAX_CONTINUOUS) = 3.630V (3.3V + 10%)
5V − 3.3V − 0.5V
VIN(MAX_CONTINUOUS) = 1.575V (1.5V + 5%) RS = = 0.6Ω
2A
VOUT = 0.9V, IOUT = 3A, TA = 50°C
Power dissipation in the LT3083 now equals:
Power dissipation under these conditions is equal to:
⎛ 2A ⎞
PDRIVE = (VCONTROL – VOUT)(ICONTROL) PTOTAL = (5V − 3.3V ) • ⎜ ⎟ + 0.5V • 2A = 1.06W
⎝ 60 ⎠
IOUT 3A
ICONTROL = = = 50mA The LT3083’s power dissipation is now only 30% compared
60 60
to no series resistor. RS dissipates 2.4W of power. Choose
PDRIVE = (3.630V – 0.9V)(50mA) = 137mW appropriate wattage resistors or use multiple resistors in
POUTPUT = (VIN – VOUT)(IOUT) parallel to handle and dissipate the power properly.
POUTPUT = (1.575V – 0.9V)(3A) = 2.03W VIN
C1 VCONTROL
RS
Total Power Dissipation = 2.16W LT3083 IN
VINa
Junction Temperature will be equal to:
TJ = TA + PTOTAL • θJA (using tables)
+
TJ = 50°C + 2.16W • 16°C/W = 84.6°C –
OUT
VOUT
In this case, the junction temperature is below the maxi- SET 3083 F07 C2
mum rating, ensuring reliable operation. RSET

Reducing Power Dissipation

In some applications it may be necessary to reduce the Figure 7. Reducing Power Dissipation Using a Series Resistor
power dissipation in the LT3083 package without sacrific-
ing output current capability. Two techniques are available.
The first technique, illustrated in Figure 7, employs a
resistor in series with the regulator’s input. The voltage
drop across RS decreases the LT3083’s input-to-output
differential voltage and correspondingly decreases the
LT3083’s power dissipation.
3083f

17
LT3083
APPLICATIONS INFORMATION
The second technique for reducing power dissipation, As an example, assume: VIN = VCONTROL = 5V, VIN(MAX) =
shown in Figure 8, uses a resistor in parallel with the 5.5V, VOUT = 3.3V, VOUT(MIN) = 3.2V, IOUT(MAX) = 2A and
LT3083. This resistor provides a parallel path for current IOUT(MIN) = 0.7A. Also, assuming that RP carries no more
flow, reducing the current flowing through the LT3083. than 90% of IOUT(MIN) = 630mA.
This technique works well if input voltage is reasonably Calculating RP yields:
constant and output load current changes are small. This
technique also increases the maximum available output 5.5V − 3.2V
RP = = 3.65Ω
current at the expense of minimum load requirements. 0.63A
(5% Standard Value = 3.6Ω)
VIN
C1 VCONTROL
LT3083 IN
The maximum total power dissipation is (5.5V – 3.2V) •
2A = 4.6W. However, the LT3083 supplies only:
5.5V − 3.2V
RP 2A − = 1.36A
+ 3.6Ω
–
OUT
VOUT Therefore, the LT3083’s power dissipation is only:
SET 3083 F08 C2
RSET
PDISS = (5.5V – 3.2V) • 1.36A = 3.13W
RP dissipates 1.47W of power. As with the first technique,
Figure 8. Reducing Power Dissipation Using a Parallel Resistor
choose appropriate wattage resistors to handle and dis-
sipate the power properly. With this configuration, the
LT3083 supplies only 1.36A. Therefore, load current can
increase by 1.64A to a total output current of 3.64A while
keeping the LT3083 in its normal operating range.

3083f

18
 LT3083
TYPICAL APPLICATIONS
Adding Shutdown Current Source

IN LT3083 VIN IN LT3083

VIN
10V
VCONTROL VCONTROL

+ +
– 10μF –
OUT OUT 0.33Ω IOUT
VOUT
0A TO 3A
SET SET
10μF
Q1 Q2*
ON OFF R1 20k
VN2222LL VN2222LL

SHUTDOWN 3083 TA02

3083 TA03

*Q2 INSURES ZERO OUTPUT

IN THE ABSENCE OF ANY
OUTPUT LOAD.

Low Dropout Voltage LED Driver

VIN
C1 VCONTROL
D1 1A
LT3083 IN

+
–
OUT

SET
R1 R2
20k 1Ω
3083 TA04

DAC-Controlled Regulator

IN LT3083
VIN

VCONTROL

+
–
150k 450k OUT
VOUT

– SET 10μF

SPI
LTC2641
150k + 3083 TA05

LT1991

GAIN = 4

3083f

19
LT3083
TYPICAL APPLICATIONS
Coincident Tracking

IN LT3083

VCONTROL

IN LT3083
+
VCONTROL
–
OUT VOUT3
VIN IN LT3083 5V
+ SET 10μF
7V TO 20V
VCONTROL
– 34k 3083 TA06
OUT VOUT2
3.3V
+ SET C3
– R2 10μF
C1 16.2k
10μF OUT VOUT1
2.5V
SET C2
R1 10μF
49.9k

Adding Soft-Start

VIN IN LT3083
4.8V to 20V
VCONTROL

D1 +
1N4148
– VOUT
C1 OUT
10μF 3.3V
3A
SET
C2 R1 COUT
0.01μF 66.5k 10μF
3083 TA07

Lab Supply

VIN IN LT3083 IN LT3083

12V TO 18V
VCONTROL VCONTROL

+ + +
15μF – –
OUT 0.33Ω OUT VOUT
0V TO 10V
SET + SET +
15μF 10μF 100μF
20k R4
0A TO 3A 200k
3083 TA08

3083f

20
 LT3083
TYPICAL APPLICATIONS
High Voltage Regulator

6.1V
VIN 10k
50V
1N4148
IN LT3083
BUZ11
VCONTROL

+ +
10μF
–
OUT VOUT
3A
SET VOUT = 20V
+ 10μF VOUT = 50μA • RSET
15μF RSET
402k

3083 TA09

Ramp Generator Reference Buffer

VIN IN LT3083 IN LT3083

VIN
5V
VCONTROL VCONTROL

10μF + +
– –
OUT OUT
VOUT INPUT VOUT*
SET OUTPUT SET C2
LT1019 10μF
10μF C1 3083 TA11
VN2222LL 10nF VN2222LL
GND 1μF
*MIN LOAD 0.5mA
3083 TA10

Boosting Fixed Output Regulators

IN LT3083

VCONTROL

+
–
OUT
10mΩ
SET
20mΩ
3.3VOUT
5V LT1963-3.3
4.5A
10μF 42Ω* 47μF

3083 TA12

33k
*4mV DROP ENSURES LT3083 IS
OFF WITH NO LOAD
MULTIPLE LT3083’S CAN BE USED

3083f

21
LT3083
TYPICAL APPLICATIONS
Low Voltage, High Current Adjustable High Efficiency Regulator*

0.47μH 10k
PVIN SW
+ 2×
2.7V TO 5.5V† SVIN ITH 100μF IN LT3083
2× + LTC3610
12.1k
470pF
2.2MEG 100k RT 2N3906
100μF
VCONTROL
PGOOD 294k
RUN/SS
+
1000pF VFB
–
OUT
78.7k
10mΩ
SYNC/MODE SET
SGND PGND 124k
IN LT3083

VCONTROL

+
*DIFFERENTIAL VOLTAGE ON LT3083
IS 0.6V SET BY THE VBE OF THE 2N3906 PNP. –
OUT
†MAXIMUM OUTPUT VOLTAGE IS 1.5V 0V TO 4V†
BELOW INPUT VOLTAGE 10mΩ 12A
SET

IN LT3083

VCONTROL

+
–
OUT

10mΩ
SET

IN LT3083

VCONTROL

+
–
OUT

3083 TA13
10mΩ
SET
+
100μF
100k

3083f

22
 LT3083
TYPICAL APPLICATIONS
Adjustable High Efficiency Regulator*

4.5V TO 25V† VIN BOOST

BD 0.47μF
10μF 1μF
100k LT3680 4.7μH
IN LT3083
RUN/SS SW
0.1μF 68μF
B340A VCONTROL

VCONTROL TP0610L
+
15.4k RT FB
GND 200k –
63.4k 10k OUT 0V TO 10V†
680pF 3A
3083 TA14
SET 4.7μF
600kHz
200k
*DIFFERENTIAL VOLTAGE ON LT3083
≈ 1.4V SET BY THE TPO610L P-CHANNEL THRESHOLD. 10k
†MAXIMUM OUTPUT VOLTAGE IS 2V
BELOW INPUT VOLTAGE

2 Terminal Current Source

CCOMP*

IN LT3083

VCONTROL

+
– R1

SET
20k

3083 TA15
1V
*CCOMP IOUT =
R1
R1 ≤ 10Ω 10μF
R1 ≥ 10Ω 2.2μF

3083f

23
LT3083
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev H)

Exposed Pad Variation BB

4.90 – 5.10*
3.58 (.193 – .201)
(.141)
3.58
(.141)
16 1514 13 12 1110 9

6.60 p0.10
2.94
4.50 p0.10 (.116)
SEE NOTE 4 2.94 6.40
(.116) (.252)
0.45 p0.05 BSC

1.05 p0.10

0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8
1.10
4.30 – 4.50* (.0433)
(.169 – .177) 0.25 MAX
REF
0o – 8o

0.65
0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.195 – 0.30
FE16 (BB) TSSOP REV G 0910
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
MILLIMETERS FOR EXPOSED PAD ATTACHMENT
2. DIMENSIONS ARE IN
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3083f

24
 LT3083
PACKAGE DESCRIPTION
DF Package
12-Lead Plastic DFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1733 Rev Ø)

2.50 REF

0.70 p0.05

3.38 p0.05
4.50 p 0.05
2.65 p 0.05
3.10 p 0.05

PACKAGE OUTLINE

0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

4.00 p 0.10 2.50 REF

(4 SIDES) 7 12

0.40 p 0.10

3.38 p0.10
2.65 p 0.10

PIN 1 NOTCH
PIN 1 R = 0.20 TYP OR
TOP MARK 0.35 s 45o
(NOTE 6) CHAMFER
(DF12) DFN 0806 REV Ø

6 1
R = 0.115 0.25 p 0.05
0.200 REF TYP 0.50 BSC
0.75 p 0.05
BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

3083f

25
LT3083
PACKAGE DESCRIPTION
Q Package
5-Lead Plastic DD-PAK
(Reference LTC DWG # 05-08-1461 Rev E)

.060
(1.524) .390 – .415
.060 TYP (9.906 – 10.541) .165 – .180
.256
(6.502) (1.524) (4.191 – 4.572) .045 – .055
15o TYP (1.143 – 1.397)

+.008
.004 –.004
.060 .183 .059
.330 – .370
(1.524) (4.648) (8.382 – 9.398)
(1.499)
TYP  +0.203
0.102 –0.102
.095 – .115
(2.413 – 2.921)
.075
(1.905)
.300
.067 .050 p .012
+.012 (1.702) .013 – .023
(7.620) .143 –.020 (1.270 p 0.305)
(0.330 – 0.584)
.028 – .038 BSC
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
 +0.305
3.632 –0.508 (0.711 – 0.965)
TYP
COPPER HEAT SINK

.420
.080
.420 .276

.350 .325
.205
.585 .585

.320

.090 .090

.067 .042 .067 .042

RECOMMENDED SOLDER PAD LAYOUT RECOMMENDED SOLDER PAD LAYOUT

FOR THICKER SOLDER PASTE APPLICATIONS
NOTE:
1. DIMENSIONS IN INCH/(MILLIMETER) Q(DD5) 0610 REV E

2. DRAWING NOT TO SCALE

3083f

26
 LT3083
PACKAGE DESCRIPTION
T Package
5-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1421)

.147 – .155 .165 – .180

.390 – .415 (3.734 – 3.937) (4.191 – 4.572) .045 – .055
(9.906 – 10.541) DIA (1.143 – 1.397)

.230 – .270
(5.842 – 6.858)

.570 – .620
.620
.460 – .500 (14.478 – 15.748)
(15.75)
(11.684 – 12.700) TYP
.330 – .370
.700 – .728
(8.382 – 9.398)
(17.78 – 18.491)

.095 – .115
SEATING PLANE
(2.413 – 2.921)
.152 – .202
.260 – .320 (3.861 – 5.131) .155 – .195*
(6.60 – 8.13) (3.937 – 4.953)

.013 – .023
(0.330 – 0.584)
.067
BSC .028 – .038 .135 – .165
(1.70)
(0.711 – 0.965) (3.429 – 4.191) * MEASURED AT THE SEATING PLANE
T5 (TO-220) 0801

3083f

27
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT3083
TYPICAL APPLICATION
Paralleling Regulators
IN LT3083

VCONTROL

+
–
OUT 10mΩ

SET

VIN IN LT3083
4.8V TO 28V
VCONTROL

+
– 10mΩ VOUT
10μF OUT
3.3V
6A
SET
22μF
33.2k
3083 TA16

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PART NUMBER DESCRIPTION COMMENTS
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Linear Regulator Stable with 10μF Ceramic Capacitors, 10-Lead MSOP-E and DFN-10 Packages
3083f

LT 0111 • PRINTED IN USA

28 Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417
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