1 General Description: Automotive LCD Driver For Low Multiplex Rates Including A 6 Channel PWM Generator
1 General Description: Automotive LCD Driver For Low Multiplex Rates Including A 6 Channel PWM Generator
1 General Description: Automotive LCD Driver For Low Multiplex Rates Including A 6 Channel PWM Generator
1 General description
The PCA8536 is a peripheral device which interfaces to almost any Liquid Crystal
1
Display (LCD) with low multiplex rates. It generates the drive signals for any multiplexed
LCD containing up to eight backplanes, up to 44 segments, and up to 320 elements. The
PCA8536 is compatible with most microcontrollers and communicates via the two-line
2
bidirectional I C-bus (PCA8536AT) or a three line unidirectional SPI-bus (PCA8536BT).
Communication overheads are minimized using a display RAM with auto-incremented
addressing.
The PCA8536 features an on-chip PWM controller for LED illumination. Up to six
independent channels can be configured. Each channel has 128 levels allowing the
possibility for two RGB controllers. Each of them provides over 2 million colors. Each
channel can also be used for static drive.
1 The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.
NXP Semiconductors
PCA8536
Automotive LCD driver for low multiplex rates including a 6 channel PWM generator
3 Applications
• Car Radio
• Climate Control
• Dash board display
4 Ordering information
Table 1. Ordering information
Type number Interface Topside Package
type mark Name Description Version
2
PCA8536AT/ I C-bus PCA8536AT/ TSSOP56 plastic thin shrink small outline package; 56 SOT364-1
Q900/1 Q900 leads; body width 6.1 mm
PCA8536BT/ SPI-bus PCA8536BT/ TSSOP56 plastic thin shrink small outline package; 56 SOT364-1
Q900/1 Q900 leads; body width 6.1 mm
[1] Standard packing quantities and other packaging data are available at www.nxp.com/packages/.
[2] Discontinuation Notice 202107021DN - drop in replacement is PCA8536AT/Q900/1Y - this is documented in PCN202102010F01.
[3] Discontinuation Notice 202107021DN - drop in replacement is PCA8536BT/Q900/1Y - this is documented in PCN202102010F01.
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5 Block diagram
BP4 to BP7/ S0/GP0 to
VDD BP0 to BP3 S40 to S43 S6 to S39 S5/GP5
VLCD
DISPLAY REGISTER
LCD BIAS
GENERATOR
VSS
DISPLAY RAM
AND
OSCILLATOR PCA8536AT PWM REGISTERS
PRESCALER
OSCCLK AND CLOCK
AND TIMING
SELECTION
013aaa495
A0
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VLCD
DISPLAY REGISTER
LCD BIAS
GENERATOR
VSS
DISPLAY RAM
AND
OSCILLATOR PCA8536BT PWM REGISTERS
PRESCALER
OSCCLK AND CLOCK
AND TIMING
SELECTION
SCL SPI-BUS
SDI CONTROLLER
013aaa496
CE
6 Pinning information
6.1 Pinning
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S9 1 56 S8 S9 1 56 S8
S10 2 55 S7 S10 2 55 S7
S11 3 54 S6 S11 3 54 S6
S12 4 53 S5/GP5 S12 4 53 S5/GP5
S13 5 52 S4/GP4 S13 5 52 S4/GP4
S14 6 51 S3/GP3 S14 6 51 S3/GP3
S15 7 50 S2/GP2 S15 7 50 S2/GP2
S16 8 49 S1/GP1 S16 8 49 S1/GP1
S17 9 48 S0/GP0 S17 9 48 S0/GP0
S18 10 47 VLCD S18 10 47 VLCD
S19 11 46 OSCCLK S19 11 46 OSCCLK
BP0/S32 12 45 VDD BP0/S32 12 45 VDD
BP1/S33 13 44 VSS BP1/S33 13 44 VSS
BP2/S34 14 43 RESET BP2/S34 14 43 RESET
PCA8536AT PCA8536BT
BP3/S35 15 42 SDA BP3/S35 15 42 SDI
BP4/S43/S36 16 41 SCL BP4/S43/S36 16 41 SCL
BP5/S42/S37 17 40 A0 BP5/S42/S37 17 40 CE
BP6/S41/S38 18 39 S39/BP0 BP6/S41/S38 18 39 S39/BP0
BP7/S40/S39 19 38 S38/BP1 BP7/S40/S39 19 38 S38/BP1
S20 20 37 S37/BP2 S20 20 37 S37/BP2
S21 21 36 S36/BP3 S21 21 36 S36/BP3
S22 22 35 S35/BP4/S43 S22 22 35 S35/BP4/S43
S23 23 34 S34/BP5/S42 S23 23 34 S34/BP5/S42
S24 24 33 S33/BP6/S41 S24 24 33 S33/BP6/S41
S25 25 32 S32/BP7/S40 S25 25 32 S32/BP7/S40
S26 26 31 S31 S26 26 31 S31
S27 27 30 S30 S27 27 30 S30
S28 28 29 S29 S28 28 29 S29
013aaa497 013aaa498
Top view. For mechanical details, see Figure 51. Top view. For mechanical details, see Figure 51.
Figure 3. Pin configuration for TSSOP56 (PCA8536AT) Figure 4. Pin configuration for TSSOP56 (PCA8536BT)
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7 Functional description
The PCA8536 is a versatile peripheral device designed to interface any microcontroller
to a wide variety of LCDs and 6 backlight LEDs. It can directly drive any multiplexed LCD
containing up to eight backplanes and up to 44 segments.
[1] Information about control byte and register selection see Section 8.1.
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Backplane swapping can be configured with the BPS bit (see Table 8). It moves the
location of the backplane and the associated segment outputs from one side of the
PCA8536 to the other. Backplane swapping is sometimes desirable to aid with the routing
of PCBs that do not use multiple layers.
The BPS bit has to be set to the required value before enabling the display. Failure to do
so does not damage the PCA8536 or the display, however unexpected display content
may appear.
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BP0 12 S32 12
BP1 13 S33 13
BP2 14 S34 14
BP3 15 S35 15
BP4/S43 16 S36 16
BP5/S42 17 S37 17
BP6/S41 18 39 S39 S38 18 39 BP0
BP7/S40 19 38 S38 S39 19 38 BP1
S20 20 37 S37 S20 20 37 BP2
S21 21 36 S36 S21 21 36 BP3
S22 22 35 S35 S22 22 35 BP4/S43
S23 23 34 S34 S23 23 34 BP5/S42
S24 24 33 S33 S24 24 33 BP6/S41
S25 25 32 S32 S25 25 32 BP7/S40
S26 26 31 S31 S26 26 31 S31
S27 27 30 S30 S27 27 30 S30
S28 28 29 S29 S28 28 29 S29
BPS = 0 BPS = 1
013aaa432
7.1.4.2 Line inversion (driving scheme A) and frame inversion (driving scheme B)
The DC offset of the voltage across the LCD is compensated over a certain period: line-
wise in line inversion mode (driving scheme A) or frame-wise in frame inversion mode
(driving scheme B). With the INV bit (see Table 8), the compensation mode can be
switched.
In frame inversion mode, the DC value is compensated across two frames and not
within one frame. Changing the inversion mode to frame inversion reduces the power
consumption; therefore it is useful when power consumption is a key point in the
application.
Frame inversion may not be suitable for all applications. The RMS voltage across a
segment is better defined; however, since the switching frequency is reduced, there is
possibility for flicker to occur.
The waveforms of Figure 15 to Figure 18 are showing line inversion mode. Figure 19
shows an example of frame inversion.
The power-down bit (PD) allows the PCA8536 to be put in a minimum power
configuration. In order to avoid display artefacts, it is recommended to enter power-down
only after the display has been switched off by setting bit E to logic 0.
During power-down, the internal oscillator is switched off and any selected PWM output
is revert to the static value stored in bits GPO0 to GPO5. These bits may be programmed
to give a static logic 0 or static logic 1 on selected GP0 to GP5 pins.
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With the following sequence, the PCA8536 can be set to a state of minimum power
consumption, called power-down mode.
START
Disable display
by setting bit E
logic 0
External clock
can be
removed now
Enable power-
down mode
with PD = 1
STOP
013aaa447
Remarks:
• It is necessary to run the power-down sequence before removing the supplies.
Depending on the application, care must be taken that no other signals are present at
the chip input or output pins when removing the supplies (see Section 9). Otherwise
it may cause unwanted display artifacts. In case of an uncontrolled removal of supply
voltages, the PCA8536 will not be damaged.
• Static voltages across the liquid crystal display can build up when the external LCD
supply voltage (VLCD) is on while the IC supply voltage is off, or vice versa. This may
cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be
applied or removed together.
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• A clock signal must always be supplied to the device when the display is active.
Removing the clock may freeze the LCD in a DC state, which is not suitable for the
liquid crystal. It is recommended to disable the display first and afterwards to remove
the clock signal.
The display enable bit (E) is used to enable and disable the display. When the display
is disabled, all LCD outputs go to VSS. This function is implemented to ensure that no
voltage can be induced on the LCD outputs as it may lead to unwanted displays of
segments.
Recommended start-up sequences are found in Section 7.2.3
Remarks:
• The state of display enable has no effect on the GPO outputs.
• Display enable is not synchronized to an LCD frame boundary. Therefore using this
function to flash a display for prolonged periods is not recommended due to the
possible build-up of DC voltages on the display.
The bits OSC, COE, and EFR control the source and frequency of the clock used to
generate the LCD and PWM signals (see Figure 7). Valid combinations are shown in
Table 11.
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COE (1)
EFR (2)
OSCCLK 0
LCD waveform
pin 1 generator
Programmable
1
Internal oscillator divider
0
230 kHz
9.6 kHz (3)
LCD frame frequency
OSC selection, q
0
Programmable PWM waveform
divider generator
1
7.1.5.1 Oscillator
The internal logic and LCD drive signals of the PCA8536 are timed either by the built-in
oscillator or from an external clock.
Internal clock
When the internal oscillator is used, all LCD and PWM signals are generated from it. The
oscillator runs at nominal 230 kHz. The relationship between this frequency and the LCD
frame frequency is detailed in Section 7.1.9. The relationship between this frequency and
the PWM frame frequency is detailed in Section 7.1.10.
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Control over the internal oscillator is made with the OSC bit (see Section 7.1.5). The
internal oscillator is also switched on or off under certain combinations of modes which
are described in Table 13.
It is possible to make the internal oscillator signal available on pin OSCCLK by using the
oscillator-control command (see Table 10) and configuring the clock output enable (COE)
bit. If not required, the pin OSCCLK should be left open or connected to VSS. At power-on
the signal at pin OSCCLK is disabled and pin OSCCLK is in 3-state.
Clock output is only valid when using the internal oscillator. The signal will appear on the
OSCCLK pin.
An intermediate clock frequency is available at the OSCCLK pin. The duty cycle of this
clock varies with the chosen divide ratio.
External clock
In applications where an external clock must be applied to the PCA8536, bit OSC (see
Table 10) has to be set logic 1. In this case pin OSCCLK becomes an input.
The OSCCLK signal must switch between the VSS and the VDD voltage supplied to the
chip.
The system is designed for a 230 kHz clock or alternatively for using a 9.6 kHz clock.
The EFR bit determines the external clock frequency. The clock frequency (fclk(ext)) in turn
determines the LCD frame frequency, see Table 15.
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The PWM generator requires a 230 kHz clock to operate. If PWM is enabled and an
external clock of 9.6 kHz is selected, then the internal oscillator will automatically start
and be used for the PWM signal generation.
Remark: If an external clock is used, then this clock signal must always be supplied to
the device when the display is on. Removing the clock may freeze the LCD in a DC state
which will damage the LCD material.
The timing of the PCA8536 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. The
timing also generates the LCD frame frequency which it derives as an integer division of
the clock frequency (see Table 15). The frame frequency is a fixed division of the internal
clock or of the frequency applied to pin OSCCLK when an external clock is used.
230 000 200 1 24
[1] Other values of the frame frequency prescaler see Table 21.
When the internal clock is used, or an external clock with EFR = 1, the LCD frame
frequency can be programmed by software in steps of approximately 10 Hz in the
range of 60 Hz to 300 Hz (see Table 21). Furthermore the internal oscillator is factory
calibrated, see Table 44.
Each output can be individually configured to be either an LCD segment output, a PWM
output or a static general-purpose output (GPO), see Table 17.
Remark: Even if using GPO only, VLCD must still be applied to the device.
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Table 20. Frame-frequency-LCD - frame frequency and output clock frequency command bit
description
Bit Symbol Value Description
7 to 5 - 001 fixed value
4 to 0 FD[4:0] see Table 21 frequency prescaler
The system is designed for a 230 kHz clock. It is either internally generated or externally
provided. Alternatively a 9.6 kHz clock signal can be provided as well. The EFR bit (see
Table 10) has to be set according to the external clock frequency.
When EFR is set to 9.6 kHz, then the LCD frame frequency is calculated with Equation 1:
(1)
When EFR is set to 230 kHz, then the LCD frame frequency is calculated with Equation
2:
(2)
Table 21. Frame frequency prescaler values for 230 kHz clock operation
FD[4:0] Nominal LCD frame Divide factor, q Intermediate clock
[1]
frequency (Hz) frequency (Hz)
0 0000 59.9 80 2 875
0 0001 70.5 68 3 382
0 0010 79.9 60 3 833
0 0011 90.4 53 4 340
0 0100 99.8 48 4 792
0 0101 108.9 44 5 227
0 0110 119.8 40 5 750
0 0111 129.5 37 6 216
0 1000 140.9 34 6 765
0 1001 149.7 32 7 188
0 1010 159.7 30 7 667
0 1011 171.1 28 8 214
0 1100 177.5 27 8 519
0 1101 191.7 25 9 200
[2]
0 1110 199.7 24 9 583
0 1111 208.3 23 10 000
1 0000 217.8 22 10 455
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Table 21. Frame frequency prescaler values for 230 kHz clock operation...continued
FD[4:0] Nominal LCD frame Divide factor, q Intermediate clock
[1]
frequency (Hz) frequency (Hz)
1 0001 228.3 21 10 952
1 0010 239.6 20 11 500
1 0011 252.2 19 12 105
1 0100 266.2 18 12 778
1 0101 281.9 17 13 529
1 0110 299.5 16 14 375
1 0111 to 1 1111 not used
[1] Nominal frame frequency calculated for the default clock frequency of 230 kHz.
[2] Default value.
(3)
Table 23. PWM frame frequency prescaler values for 230 kHz clock operation
[1]
FP[3:0] Nominal PWM frame frequency (Hz) Divide factor, p
0000 59.9 30
0001 69.1 26
0010 81.7 22
0011 89.8 20
0100 99.8 18
0101 112.3 16
0110 119.8 15
[2]
0111 128.3 14
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Table 23. PWM frame frequency prescaler values for 230 kHz clock operation...continued
[1]
FP[3:0] Nominal PWM frame frequency (Hz) Divide factor, p
1000 138.2 13
1001 149.7 12
1010 163.4 11
1011 179.7 10
1100 199.7 9
1101 224.6 8
1110 256.7 7
1111 299.5 6
[1] Nominal frame frequency calculated for the default clock frequency of 230 kHz.
[2] Default value.
In order to avoid flickering caused by the interaction of the backlight LED and the LCD
frame frequency, the PWM frame frequency should be programmed to be more than 50
Hz different from LCD frame frequency or multiples of the LCD frame frequency (see
Figure 8 and Table 49 on page 68).
f1 2f1 f0
This will repeat for 3f1, 4f1, etc.
013aaa449
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Table 24. GPO-static-data - write GPO data for GP0 to GP5 command bit
description
Bit Symbol Value Description
GPO0 to GPO2
7 to 3 - 0110 0 fixed value
[1]
2 GPO2 0 0 level output on pin GP2
1 1 level output on pin GP2
[1]
1 GPO1 0 0 level output on pin GP1
1 1 level output on pin GP1
[1]
0 GPO0 0 0 level output on pin GP0
1 1 level output on pin GP0
GPO3 to GPO5
7 to 3 - 0110 1 fixed value
[1]
2 GPO5 0 0 level output on pin GP5
1 1 level output on pin GP5
[1]
1 GPO4 0 0 level output on pin GP4
1 1 level output on pin GP4
[1]
0 GPO3 0 0 level output on pin GP3
1 1 level output on pin GP3
Remark: Data pointer values outside of the valid range will be ignored and no RAM
content will be transferred until a valid data pointer value is set.
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Remark: Data pointer values outside of the valid range will be ignored and no PWM
content will be transferred until a valid data pointer value is set.
[1] For this command to be effective bit RS[1:0] of the control byte has to be set logic 01, see Table 36page 46.
[2] After Power-On Reset (POR), the RAM content is random and should be brought to a defined status by writing meaningful
content otherwise unexpected display content may appear.
[1] For this command to be effective bit RS[1:0] of the control byte has to be set logic 10, see Table 36page 46.
[2] Default value. After Power-On Reset (POR) the PWM content is set to 0.
The first command sent to the device after the power-on event must be the initialize
command (see Section 7.1.1).
After Power-On Reset (POR) and before enabling the display, the RAM content should
be brought to a defined state by writing meaningful content (e.g. a graphic) otherwise
unwanted display artifacts may appear on the display.
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START
Power-on VDD
and VLCD
together
Send display
Wait minimum content
1 ms
Enable
Send the display
OTP-refresh
STOP
Set:
- mode settings: BPS and INV
- LCD/GPO output mode
- multiplex driver mode 013aaa452
- bias mode
- LCD frame frequency
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START
Power-on VDD
and VLCD
together
Send display
Wait minimum content
1 ms
External clock
External clock must be
can be applied applied by now
now
Enable
Send
the display
OTP-refresh
Set: STOP
- Mode settings: BPS and INV
- Select external clock
013aaa453
- GPO output mode
- Multiplex driver mode
- Bias mode
- LCD frame frequency
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dot matrix
013aaa312
All of the display configurations in Table 30 can be implemented in the typical systems
shown in Figure 12 and Figure 13.
VDD
tr
R=
2Cb
40 to 44 segment
VDD drives
SDA
HOST
LCD PANEL
PROCESSOR/ SCL
PCA8536AT (up to 320
MICRO-
4 to 8 backplanes elements)
CONTROLLER
A0 VSS 013aaa499
VSS
2
Figure 12. Typical system configuration for the I C-bus
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VDD
40 to 44 segment
VDD drives
SDI
HOST LCD PANEL
PROCESSOR/ SCL (up to 320
PCA8536BT
MICRO- 4 to 8 backplanes elements)
CONTROLLER CE
VSS
013aaa500
VSS
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A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast.
(4)
where VLCD is the resultant voltage at the LCD segment and where the values for n are
n = 4 for 1:4 multiplex drive
n = 6 for 1:6 multiplex drive
n = 8 for 1:8 multiplex drive
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 5:
(5)
(6)
It should be noted that VLCD is sometimes referred to as the LCD operating voltage.
(8)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the
selection of a, n (see Equation 4 to Equation 6) and the VLCD voltage.
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Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes just named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
100 %
90 %
Relative Transmission
10 %
OFF GREY ON
SEGMENT SEGMENT SEGMENT
013aaa494
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Tfr
VLCD LCD segments
2VLCD/3
BP0 VLCD/3
VSS
state 1
VLCD
state 2
2VLCD/3
BP1 VLCD/3
VSS
VLCD
2VLCD/3
BP2 VLCD/3
VSS
VLCD
2VLCD/3
BP3 VLCD/3
VSS
VLCD
Sn 2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
Sn+1
VLCD/3
VSS
VLCD
2VLCD/3
Sn+2
VLCD/3
VSS
VLCD
2VLCD/3
Sn+3 VLCD/3
VSS
(a) Waveforms at driver.
VLCD
2VLCD/3
VLCD/3
state 1 0V
-VLCD/3
-2VLCD/3
-VLCD
VLCD
2VLCD/3
VLCD/3
state 2 0V
-VLCD/3
-2VLCD/3
-VLCD
(b) Resultant waveforms
013aaa211
at LCD segment.
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VLCD
2VLCD / 3
BP1
VLCD / 3
VSS
VLCD
2VLCD / 3
BP2
VLCD / 3
VSS
VLCD
2VLCD / 3
BP3
VLCD / 3
VSS
VLCD
2VLCD / 3
BP4
VLCD / 3
VSS
VLCD
2VLCD / 3
BP5
VLCD / 3
VSS
VLCD
2VLCD / 3
Sn
VLCD / 3
VSS
VLCD
2VLCD / 3
Sn + 1
VLCD / 3
VSS
(a) Waveforms at driver
VLCD
2VLCD / 3
state 1
VLCD / 3
VSS
-VLCD / 3
-2VLCD / 3
-VLCD
VLCD
2VLCD / 3
state 2
VLCD / 3
VSS
-VLCD / 3
-2VLCD / 3
-VLCD (b) Resultant waveforms at LCD segment 001aal399
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn +1 (t) - VBP0(t). Von(RMS)(t) = 0.509VLCD. Voff(RMS)(t) = 0.333VLCD.
1
Figure 16. Waveforms for 1:6 multiplex drive mode with bias ⁄3 and line inversion
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Tfr
VLCD LCD segments
3VLCD / 4 state 1 state 2
BP0
VLCD / 4
VSS
VLCD
3VLCD / 4
BP1
VLCD / 4
VSS
VLCD
3VLCD / 4
BP2
VLCD / 4
VSS
VLCD
3VLCD / 4
BP3
VLCD / 4
VSS
VLCD
3VLCD / 4
BP4
VLCD / 4
VSS
VLCD
3VLCD / 4
BP5
VLCD / 4
VSS
VLCD
Sn VLCD / 2
VSS
VLCD
Sn + 1 VLCD / 2
VSS
(a) Waveforms at driver
VLCD
3VLCD / 4
VLCD / 4
state 1 VSS
-VLCD / 4
-3VLCD / 4
-VLCD
VLCD
3VLCD / 4
VLCD / 2
VLCD / 4
state 2 VSS
-VLCD / 4
-VLCD / 2
-3VLCD / 4
(b) Resultant waveforms at LCD segment
-VLCD 001aal400
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Tfr
VLCD LCD segments
3VLCD / 4 state 1 state 2
BP0
VLCD / 4
VSS
VLCD
3VLCD / 4
BP1
VLCD / 4
VSS
VLCD
3VLCD / 4
BP2
VLCD / 4
VSS
VLCD
3VLCD / 4
BP3
VLCD / 4
VSS
VLCD
3VLCD / 4
BP4
3LCD / 4
VSS
VLCD
3VLCD / 4
BP5
VLCD / 4
VSS
VLCD
3VLCD / 4
BP6
VLCD / 4
VSS
VLCD
3VLCD / 4
BP7
VLCD / 4
VSS
VLCD
Sn VLCD / 2
VSS
VLCD
Sn + 1 VLCD / 2
VSS
(a) Waveforms at driver
VLCD
3VLCD / 4
VLCD / 4
state 1 VSS
-VLCD / 4
-3VLCD / 4
-VLCD
VLCD
3VLCD / 4
VLCD / 2
VLCD / 4
state 2 VSS
-VLCD / 4
-VLCD / 2
-3VLCD / 4 (b) Resultant waveforms at LCD segment
-VLCD 001aal398
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn + 1(t) - VBP0(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD.
1
Figure 18. Waveforms for 1:8 multiplex drive mode with bias ⁄4 and line inversion
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Tfr Tfr
VLCD frame n frame n+1
LCD segments
3/4 VLCD
BP0 state 1 state 2
1/4 VLCD
VSS
VLCD
3/4 VLCD
BP1
1/4 VLCD
VSS
VLCD
3/4 VLCD
BP2
1/4 VLCD
VSS
VLCD
3/4 VLCD
BP3
1/4 VLCD
VSS
VLCD
3/4 VLCD
BP4
1/4 VLCD
VSS
VLCD
3/4 VLCD
BP5
1/4 VLCD
VSS
VLCD
3/4 VLCD
BP6
1/4 VLCD
VSS
VLCD
3/4 VLCD
BP7
1/4 VLCD
VSS
VLCD
Sn 1/2 VLCD
VSS
VLCD
Sn + 1 1/2 VLCD
VSS
(a) Waveforms at driver
VLCD
3/4 VLCD
1/2 VLCD
1/4 VLCD
state 1 VSS
1/4 VLCD
1/2 VLCD
3/4 VLCD
VLCD
VLCD
3/4 VLCD
1/2 VLCD
1/4 VLCD
state 2 VSS
1/4 VLCD
1/2 VLCD
3/4 VLCD
VLCD (b) Resultant waveforms at LCD segment 001aam359
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn + 1(t) - VBP0(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD.
1
Figure 19. Waveforms for 1:8 multiplex drive mode with bias ⁄4 and frame inversion
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BP0
BP1
BP2
BP3
BP4
BP5
BP6
Display RAM bits (rows)/backplane outputs (BP)
BP7
Multiplex 1:6 drive mode S0 S1 S2 S3 S4 S35 S36 S37 S38 S39 S40 S41
BP0
BP1
BP2
BP3
BP4
BP5
Multiplex 1:4 drive mode S0 S1 S2 S3 S4 S35 S36 S37 S38 S39 S40 S41 S42 S43
BP0
BP1
BP2
BP3
013aaa454
The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs and between the bits in a RAM row and the backplane outputs.
Figure 20. Display RAM bitmap
Logic 1 in the RAM bit map indicates the on-state (Von(RMS)) of the corresponding LCD
element; similarly, logic 0 indicates the off-state (Voff(RMS)). For more information on
Von(RMS) and Voff(RMS), see Section 7.4.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD elements,
• the RAM columns and the segment outputs,
• the RAM rows and the backplane outputs.
The display RAM bit map, Figure 20, shows row 0 to row 7 which correspond with the
backplane outputs BP0 to BP7, and column 0 to column 43 which correspond with the
segment outputs S0 to S43. In multiplexed LCD applications, the data of each row of the
display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row
1 with BP1, and so on).
When display data is transmitted to the PCA8536, the display bytes received are stored
in the display RAM in accordance with the selected LCD multiplex drive mode. The data
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is stored as it arrives and depending on the current multiplex drive mode, data is stored
in quadruples, sextuples or bytes.
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Columns
Display RAM addresses (columns)/segment outputs (S)
0 1 2 3 4 5 6 7 39 40 41 42 43
0 b7 b3
1 b6 b2
Rows
2 b5 b1
Display RAM
3 b4 b0
bits (rows)/
backplane outputs
(BP)
b7 b6 b5 b4 b3 b2 b1 b0
MSB LSB
Transmitted data byte
013aaa455
Depending on the start address of the data pointer, there is the possibility for a boundary
condition. This will occur when more data bits are sent than fit into the remaining RAM.
The additional data bits are discarded. See Figure 22.
Columns
Display RAM addresses (columns)/segment outputs (S)
0 1 2 3 4 5 6 7 39 40 41 42 43
0 b7
Rows 1 b6
2 b5
Display RAM
bits (rows)/ 3 b4
backplane outputs
(BP)
Discarded
b7 b6 b5 b4 b3 b2 b1 b0
MSB LSB
Transmitted data byte
013aaa456
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Columns
Display RAM addresses (columns)/segment outputs (S)
0 1 2 3 4 5 6 7 37 38 39 40 41
0 a7 a1 b3 c5
1 a6 a0 b2 c4
Rows
2 a5 b7 b1 c3
Display RAM 3 a4 b6 b0 c2
bits (rows)/ 4 a3 b5 c7 c1
backplane outputs 5 a2 b4 c6 c0
(BP)
MSB LSB
a7 a6 a5 a4 a3 a2 a1 a0
b7 b6 b5 b4 b3 b2 b1 b0
c7 c6 c5 c4 c3 c2 c1 c0
The remaining bits are wrapped over into the next column. In order to fill the whole
RAM, 31 and a half bytes need to be sent to the PCA8536. After the last byte sent, the
data pointer must be reset before the next RAM content update. Additional data bytes
sent and any data bits that spill over the RAM will be discarded. Depending on the start
address of the data pointer, there are three possible boundary conditions. See Figure 24.
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Columns
Display RAM addresses (columns)/segment outputs (S)
0 1 2 3 4 5 6 7 37 38 39 40 41
0 b7
1 b6
2 b5
3 b4
4 b3
5 b2
Discarded
b7 b6 b5 b4 b3 b2 b1 b0
Display RAM bits (rows)/backplane outputs (BP)
MSB LSB
Transmitted data byte
0 1 2 3 4 5 6 7 37 38 39 40 41
0
1
2 b7
Rows
3 b6
4 b5
5 b4
Discarded
b7 b6 b5 b4 b3 b2 b1 b0
MSB LSB
Transmitted data byte
0 1 2 3 4 5 6 7 37 38 39 40 41
0
1
2
3
4 b7
5 b6
Discarded
b7 b6 b5 b4 b3 b2 b1 b0
MSB LSB
Transmitted data byte
013aaa458
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Columns
Display RAM columns/segment outputs (S)
0 1 2 3 4 5 6 7 35 36 37 38 39
0 b7
1 b6
2 b5
Rows
3 b4
Display RAM rows/
backplane outputs 4 b3
(BP) 5 b2
6 b1
7 b0
b7 b6 b5 b4 b3 b2 b1 b0
MSB LSB
Transmitted data byte
013aaa459
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Columns
Display RAM columns/segment outputs (S)
0 1 2 3 4 5 6 7 35 36 37 38 39
0 b7
1 b6
Rows
2 b5
Display RAM rows/ 3 b4
backplane outputs
(BP) 4 b3
5 b2
6 b1
7 b0
b7 b6 b5 b4 b3 b2 b1 b0
MSB LSB
Transmitted data byte
013aaa460
(9)
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PWMI
PWM generator
230 kHz 0
channel 0 GP0 1 0
1 1
S0/GP0
0 1
1 segment 0
0 0
PWM value 0 LCD data
GP0M[1:0]
PWM generator
230 kHz 0
channel 1 GP1 1 0
1 1
S1/GP1
0 1
1 segment 1
0 0
PWM value 1 LCD data
GP1M[1:0]
PWM generator
230 kHz 0
channel 2 GP2 1 0
1 1
S2/GP2
0 1
1 segment 2
0 0
PWM value 2 LCD data
GP2M[1:0]
PWM generator
230 kHz 0
channel 3 GP3 1 0
1 1
S3/GP3
0 1
1 segment 3
0 0
PWM value 3 LCD data
GP3M[1:0]
PWM generator
230 kHz 0
channel 4 GP4 1 0
1 1
S4/GP4
0 1
1 segment 4
0 0
PWM value 4 LCD data
GP4M[1:0]
PWM generator
230 kHz 0
channel 5 GP5 1 0
1 1
S5/GP5
0 1
1 segment 5
0 0
PWM value 5 LCD data
GP5M[1:0]
001aan567
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fPWM
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R G B R G B
cluster 0 cluster 1
S0/GP0
S1/GP1
S2/GP2
S3/GP3
S4/GP4
S5/GP5
001aan568
Table 35 gives some examples of programming values for the PWM channels in order to
achieve the given colors. By using three PWM channels for one RGB cluster it is possible
to generate two million colors.
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fPWM
When PWM inversion mode is used, the PWM duty cycle can be calculated with:
(10)
8 Bus interfaces
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MSB LSB
7 6 5 4 3 2 1 0
CO RS[1:0] not relevant
013aaa461
2
8.2 I C-bus interface
2
The I C-bus is for bidirectional, two-line communication between different ICs or
modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor when connected to the
output stages of a device. Data transfer may be initiated only when the bus is not busy.
SDA
SCL
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P).
The START and STOP conditions are shown in Figure 33.
SDA SDA
SCL SCL
S P
SDA
SCL
mga807
8.2.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A target receiver which is addressed must generate an acknowledge after the reception
of each byte.
• Also a controller receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the target transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A controller receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the target. In this event, the
transmitter must leave the data line HIGH to enable the controller to generate a STOP
condition.
2
Acknowledgement on the I C-bus is shown in Figure 35.
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data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL
1 2 8 9
from controller
S
clock pulse for
START
acknowledgement
condition
mbc602
2
Figure 35. Acknowledgement on the I C-bus
2
8.2.5 I C-bus controller
2 2
The PCA8536 acts as an I C-bus target receiver. It does not initiate I C-bus transfers or
2 2
transmit data to an I C-bus controller receiver. Device selection depends on the I C-bus
target address.
2
8.2.7 I C-bus target address
2 2
Device selection depends on the I C-bus target address. Two different I C-bus target
addresses can be used to address the PCA8536 (see Table 37).
2
Table 37. I C target address
target address
Bit 7 6 5 4 3 2 1 0
MSB LSB
0 1 1 1 0 0 A0 R/W
The least significant bit of the target address byte is bit R/W. Bit 1 of the target address is
defined by connecting the input A0 to either VSS (logic 0) or VDD (logic 1). Therefore, two
2
instances of PCA8536 can be distinguished on the same I C-bus.
2
8.2.8 I C-bus protocol
2
The I C-bus protocol is shown in Figure 36. The sequence is initiated with a START
2
condition (S) from the I C-bus controller which is followed by one of the two PCA8536
target addresses available. All PCA8536 with the corresponding A0 level acknowledge in
parallel to the target address, but any PCA8536 with the alternative A0 level ignore the
2
whole I C-bus transfer.
After acknowledgement, a control byte follows (see Section 8.1).
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The display bytes are stored in the display RAM at the address specified by the RAM
data pointer and PWM data is stored at the address pointed to by the PWM data pointer.
The acknowledgement after each byte is made only by the addressed PCA8536. After
2
the last data byte, the I C-bus controller issues a STOP condition (P). Alternatively a
2
START may be issued to RESTART an I C-bus access.
R/W = 0
target address control byte RAM/command byte
R R M L
S 0 1 1 1 0 0 A 0 AC S S A S S P
0 O1 0 B B
EXAMPLES
a) transmit two byte of RAM data
S 0 1 1 1 0 0 A 0 A 1 0 0 A COMMAND A 0 0 0 A COMMAND A P
0
S 0 1 1 1 0 A A
1 0 0 A 1 0 0 A COMMAND A 0 0 1 A RAM DATA A RAM DATA A P
013aaa462
2
Figure 36. I C-bus protocol write mode
If a readout is made, the R/W bit must be logic 1 and then the next data byte following is
provided by the PCA8536 as shown in Figure 37.
R/W = 1
target address readout byte
S 0 1 1 1 0 0 A 1 A 0 1 0 1 0 1 0 A A P
0 0
1. From PCA8536.
2
Figure 37. I C-bus protocol read mode
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In the unlikely case that the chip has entered the internal test mode, detection of this
state is possible by using the modified status read out detailed in Table 39. The read out
value is modified to indicate that the chip has entered an internal test mode.
EMC detection
CE
013aaa464
The subaddress byte opens the communication with a read/write bit and a subaddress.
The subaddress is used to identify multiple devices on one SPI-BUS.
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After the subaddress byte, a control byte follows (see Section 8.1).
R/W = 0
subaddress control byte RAM/command byte
R R M L
0 0 1 C S S S S
O1 0 B B
EXAMPLES
a) transmit two bytes of display RAM data
0 0 1 1 0 0 COMMAND 0 0 0 COMMAND
c) transmit one command byte and two display RAM date bytes
013aaa465
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
SCL
SDI
CE
013aaa466
1
In this example, the bias system is set to ⁄3. The transfer is terminated by CE returning to logic 1. After the last bit is
transmitted, the state of the SDI line is not important.
Figure 40. SPI-bus example
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9 Internal circuitry
VDD
A0, RESET,
OSCCLK
VLCD, VDD,
SCL, SDA
VSS
VLCD
VSS
BP0 to BP7,
S0/GP0 to S5/GP5
S6 to S39
VSS
013aaa472
CE, RESET,
OSCCLK SDI, SCL
VLCD,VDD
VSS
VLCD
VSS
BP0 to BP7,
S0/GP0 to S5/GP5
S6 to S39
VSS 013aaa473
10 Limiting values
CAUTION
Static voltages across the liquid crystal display can build up when the LCD
supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice
versa. This may cause unwanted display artifacts. To avoid such artifacts,
VLCD and VDD must be applied or removed together.
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11 Static characteristics
Table 43. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = -40 °C to +95 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDD supply voltage 1.8 - 5.5 V
VLCD LCD supply voltage VLCD ≥ VDD 2.5 - 9.0 V
[1]
IDD(pd) power-down mode supply current - 0.5 2 μA
IDD supply current see Figure 43
[2]
external 9.6 kHz clock - 10 25 μA
[3]
external 230 kHz - 20 40 μA
clock with PWM
[2]
internal oscillator - 30 60 μA
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2
[1] Power-down mode is enabled; I C-bus or SPI-bus inactive.
1
[2] 1:8 multiplex drive mode; ⁄4 bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; default display
2
prescale factor; I C-bus or SPI-bus inactive.
1
[3] 1:8 multiplex drive mode; ⁄4 bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; default display
2
prescale factor; I C-bus or SPI-bus inactive; six PWM channels active at 50 % duty.
[4] Strongly linked to VLCD voltage. See Figure 44.
1
[5] 1:8 multiplex drive mode; ⁄4 bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; default display prescale factor.
2
[6] The I C-bus interface of PCA8536 is 5 V tolerant.
[7] Variation between any two backplanes on a given voltage level; static measured.
[8] Variation between any two segments on a given voltage level; static measured.
[9] Outputs measured one at a time.
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013aaa502
60
IDD
(µA)
40
20
0
-45 -10 25 60 95
Tamb (ºC)
1
1:8 multiplex drive mode; ⁄4 bias; internal oscillator; display enabled; LCD outputs are open
2
circuit; RAM is all written with logic 1; inputs at VSS or VDD; default display prescale factor; I C-
bus or SPI-bus inactive. Typical is defined at VDD = 3.3 V, 25 °C.
Figure 43. Typical IDD with respect to temperature
013aaa504
15
IDD(LCD)
(µA)
VLCD = 9.0 V
10
VLCD = 5.5 V
5
0
-45 -10 25 60 95
Tamb (ºC)
2
Power-down mode is enabled; I C-bus or SPI-bus inactive. Typical is defined at 25 °C.
Figure 44. Typical IDD(LCD) in power-down mode with respect to temperature
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013aaa506
120
IDD(LCD)
(µA)
VLCD = 9.0 V
80
40 VLCD = 5.5 V
0
-45 -10 25 60 95
Tamb (ºC)
1
1:8 multiplex drive mode; ⁄4 bias; display enabled; LCD outputs are open circuit; RAM is all
written with logic 1; default display prescale factor. Typical is defined at 25 °C.
Figure 45. Typical IDD(LCD) when display is active with respect to temperature
12 Dynamic characteristics
Table 44. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = -40 °C to +95 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
[1]
fclk clock frequency output on pin 7 800 9 600 11 040 Hz
OSCCLK; VDD = 3.3 V
fclk(ext) external clock frequency EFR = 0 - - 250 000 Hz
t(RESET_N) RESET_N pulse width LOW time 400 - - ns
External clock source used on pin OSCCLK
tclk(H) clock HIGH time 33 - - μs
tclk(L) clock LOW time 33 - - μs
[1] Frequency present on OSCCLK with default display frequency division factor.
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013aaa501
15
fclk
(kHz)
(3) (2)
10
(1)
0
1 3 5 7
VDD (V)
1. -40 °C.
2. 25 °C.
3. 95 °C.
Figure 46. Typical clock frequency with respect to VDD and temperature
1/fclk(ext)
tclk(H) tclk(L)
0.7VDD
OSCCLK 0.3VDD
013aaa474
tRESET(L)
RESET
0.3VDD
013aaa475
2
Table 45. Timing characteristics: I C-bus
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = -40 °C to +95 °C; unless otherwise specified. All timing values
are valid within the operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage
swing of VSS to VDD. Timing waveforms see Figure 49.
Symbol Parameter Conditions Min Typ Max Unit
Pin SCL
[1]
fSCL SCL clock frequency - - 400 kHz
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2
Table 45. Timing characteristics: I C-bus...continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = -40 °C to +95 °C; unless otherwise specified. All timing values
are valid within the operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage
swing of VSS to VDD. Timing waveforms see Figure 49.
Symbol Parameter Conditions Min Typ Max Unit
tLOW LOW period of the SCL clock 1.3 - - μs
tHIGH HIGH period of the SCL clock 0.6 - - μs
Pin SDA
tSU;DAT data set-up time 100 - - ns
tHD;DAT data hold time 0 - - ns
Pins SCL and SDA
tBUF bus free time between a STOP 1.3 - - μs
and START condition
tSU;STO set-up time for STOP condition 0.6 - - μs
tHD;STA hold time (repeated) START 0.6 - - μs
condition
tSU;STA set-up time for a repeated START 0.6 - - μs
condition
tr rise time of both SDA and SCL fSCL = 400 kHz - - 0.3 μs
signals
fSCL = 100 kHz - - 1.0 μs
tf fall time of both SDA and SCL - - 0.3 μs
signals
[2]
tVD;ACK data valid acknowledge time 0.6 - - μs
[3]
tVD;DAT data valid time 0.6 - - μs
Cb capacitive load for each bus line - - 400 pF
[4]
tSP pulse width of spikes that must - - 50 ns
be suppressed by the input filter
[1] The minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either the SDA or SCL is held LOW for a
minimum of 25 ms. The bus time-out feature must be disabled for DC operation.
[2] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.
[3] tVD;DAT = minimum time for valid SDA output following SCL LOW.
[4] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
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SCL
tBUF tf
tr
SDA
013aaa417
2
Figure 49. I C-bus timing waveforms
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CE
SDI b7 b6 b0
013aaa476
13 Test information
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14 Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1
D E A
X
y HE v M A
56 29
Q
A2 (A 3 ) A
A1
pin 1 index
θ
Lp
L
1 28 detail X
w M
e bp
0 2.5 5 mm
scale
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
99-12-27
SOT364-1 MO-153
03-02-19
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15 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
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• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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peak
temperature
time
001aac844
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Hx
Gx
P2
(0.125) (0.125)
Hy Gy By Ay
D2 (4x) P1 D1
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ay By C D1 D2 Gx Gy Hx Hy
0.500 0.560 8.900 6.100 1.400 0.280 0.400 14.270 7.000 16.600 9.150
sot364-1_fr
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PCA8536 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
PCA8536 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
[1] The table shows the smallest distance (Δf) from one frequency to the next or multiples of the next. Δf = MIN(f1 - n × f2); the values for n are 1 to 6; f1 and f2 can be either fPWM or ffr(LCD); both relationships have to be considered.
A PWM frame frequency (fPWM) of less than 60 Hz may show flicker purely from the LCD.
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19 Abbreviations
Table 50. Abbreviations
Acronym Description
AEC Automotive Electronics Council
CDM Charged-Device Model
CMOS Complementary Metal-Oxide Semiconductor
DC Direct Current
EMC ElectroMagnetic Compatibility
EPROM Erasable Programmable Read-Only Memory
ESD ElectroStatic Discharge
HBM Human Body Model
2
I C Inter-Integrated Circuit bus
IC Integrated Circuit
LCD Liquid Crystal Display
LED Light-Emitting Diode
LSB Least Significant Bit
MSB Most Significant Bit
MSL Moisture Sensitivity Level
MUX Multiplexer
OTP One Time Programmable
PCB Printed-Circuit Board
POR Power-On Reset
PWM Pulse-Width Modulation
RC Resistance-Capacitance
RAM Random Access Memory
RGB Red Green Blue
RMS Root Mean Square
SCL Serial CLock line
SDA Serial DAta line
SPI Serial Peripheral Interface
20 References
[1] JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model
(HBM)
[2] JESD22-C101 Field-Induced Charged-Device Model Test Method for Electrostatic-
Discharge-Withstand Thresholds of Microelectronic Components
[3] JESD78 IC Latch-Up Test
[4] NX3-00092 NXP store and transport requirements
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21 Revision history
Table 51. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCA8536 v.3 20211006 Product data sheet PCN202102010F01 PCA8536 v.2
Modifications: • Updated Ordering information, including addition of Ordering options. See Change notice
column in this table.
• Removed Marking section (formerly Section 5).
• The terms "master" and "slave" changed to "controller" and "target" to comply with NXP
inclusive language policy.
PCA8536 v.2 20120221 Product data sheet - PCA8536 v.1
Modifications: • Fixed typos
PCA8536 v.1 20111006 Product data sheet - -
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22 Legal information
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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is deemed to offer functions and qualities beyond those described in the
Product data sheet. Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
22.3 Disclaimers given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
Limited warranty and liability — Information in this document is believed the quality and reliability of the device.
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22.4 Trademarks
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Notice: All referenced brands, product names, service names and
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trademarks are the property of their respective owners.
Export control — This document as well as the item(s) described herein 2
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Tables
Tab. 1. Ordering information ..........................................2 Tab. 24. GPO-static-data - write GPO data for GP0
Tab. 2. Ordering options ................................................2 to GP5 command bit description ..................... 20
Tab. 3. Pin description of PCA8536AT and Tab. 25. Load-data-pointer-LCD - load data pointer
PCA8536BT .......................................................6 command bit description ................................. 20
Tab. 4. Commands of PCA8536 ................................... 7 Tab. 26. Load-data-pointer-PWM - load data pointer
Tab. 5. Initialize - initialize command bit description ......8 command bit description ................................. 21
Tab. 6. OTP-refresh - OTP-refresh command bit Tab. 27. Write-RAM-data - write RAM data
description ......................................................... 8 command bit description ................................. 21
Tab. 7. PWM-inversion - PWM inversion command Tab. 28. Write-PWM-data - write PWM data
bit description .................................................... 8 command bit description ................................. 21
Tab. 8. Mode-settings - mode settings command Tab. 29. Reset state ...................................................... 22
bit description .................................................... 8 Tab. 30. Selection of display configurations .................. 25
Tab. 9. Effect of the power-down bit (PD) ................... 11 Tab. 31. Preferred LCD drive modes: summary of
Tab. 10. Oscillator-control - oscillator control characteristics ..................................................26
command bit description ................................. 12 Tab. 32. Backplane and active segment
Tab. 11. Valid combinations of bits OSC, EFR, and combinations ................................................... 34
COE .................................................................13 Tab. 33. PWM generator ............................................... 41
Tab. 12. Typical use of bits OSC, EFR, and COE ......... 13 Tab. 34. Combining PWM channels for RGB ................ 43
Tab. 13. Internal oscillator on/off table .......................... 14 Tab. 35. Example PWM values ..................................... 44
Tab. 14. OSCCLK table .................................................14 Tab. 36. Control byte description .................................. 46
Tab. 15. LCD frame frequencies ................................... 15 Tab. 37. I2C target address .......................................... 48
Tab. 16. GPO-output-config - output mode config Tab. 38. Status read out value ......................................49
command for S5/GP5 to S0/GP0 .................... 15 Tab. 39. Modified status read out value ........................ 50
Tab. 17. GPMO mode definition ....................................16 Tab. 40. Serial interface ................................................ 50
Tab. 18. Set-MUX-mode - set multiplex drive mode Tab. 41. Subaddress byte definition .............................. 51
command bit description ................................. 16 Tab. 42. Limiting values ................................................ 52
Tab. 19. Set-bias-mode - set bias mode command Tab. 43. Static characteristics ....................................... 53
bit description .................................................. 16 Tab. 44. Dynamic characteristics .................................. 57
Tab. 20. Frame-frequency-LCD - frame frequency Tab. 45. Timing characteristics: I2C-bus ....................... 58
and output clock frequency command bit Tab. 46. Timing characteristics: SPI-bus ....................... 60
description ....................................................... 17 Tab. 47. SnPb eutectic process (from J-STD-020D) ..... 64
Tab. 21. Frame frequency prescaler values for 230 Tab. 48. Lead-free process (from J-STD-020D) ............ 64
kHz clock operation .........................................17 Tab. 49. LCD and PWM frame frequency
Tab. 22. Frame-frequency-PWM - PWM frame combinations to avoid flicker ........................... 68
frequency command bit description .................18 Tab. 50. Abbreviations ...................................................70
Tab. 23. PWM frame frequency prescaler values for Tab. 51. Revision history ...............................................71
230 kHz clock operation ..................................18
Figures
Fig. 1. Block diagram of PCA8536AT ...........................3 Fig. 12. Typical system configuration for the I2C-
Fig. 2. Block diagram of PCA8536BT .......................... 4 bus ...................................................................25
Fig. 3. Pin configuration for TSSOP56 Fig. 13. Typical system configuration for the SPI-
(PCA8536AT) .................................................... 5 bus ...................................................................26
Fig. 4. Pin configuration for TSSOP56 Fig. 14. Electro-optical characteristic: relative
(PCA8536BT) .................................................... 5 transmission curve of the liquid .......................28
Fig. 5. Effect of backplane swapping ......................... 10 Fig. 15. Waveforms for the 1:4 multiplex drive mode
Fig. 6. Recommended power-down sequence ........... 11 with 1⁄3 bias and line inversion ....................... 29
Fig. 7. Oscillator selection .......................................... 13 Fig. 16. Waveforms for 1:6 multiplex drive mode
Fig. 8. Flicker avoidance for LED backlighting ........... 19 with bias 1⁄3 and line inversion ....................... 30
Fig. 9. Recommended start-up sequence when Fig. 17. Waveforms for 1:6 multiplex drive mode
using the internal oscillator ............................. 23 with bias 1⁄4 and line inversion ....................... 31
Fig. 10. Recommended start-up sequence when Fig. 18. Waveforms for 1:8 multiplex drive mode
using an external clock signal ......................... 24 with bias 1⁄4 and line inversion ....................... 32
Fig. 11. Example of displays suitable for PCA8536 ......25
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Fig. 19. Waveforms for 1:8 multiplex drive mode Fig. 36. I2C-bus protocol write mode ........................... 49
with bias 1⁄4 and frame inversion .................... 33 Fig. 37. I2C-bus protocol read mode ............................49
Fig. 20. Display RAM bitmap ....................................... 35 Fig. 38. Data transfer overview .................................... 50
Fig. 21. Display RAM filling order in 1:4 multiplex Fig. 39. SPI-bus write example .................................... 51
drive mode ...................................................... 37 Fig. 40. SPI-bus example ............................................. 51
Fig. 22. Boundary condition in 1:4 multiplex drive Fig. 41. Device protection diagram for PCA8536AT ..... 52
mode ............................................................... 37 Fig. 42. Device protection diagram for PCA8536BT .....52
Fig. 23. Display RAM filling order in 1:6 multiplex Fig. 43. Typical IDD with respect to temperature ..........56
drive mode ...................................................... 38 Fig. 44. Typical IDD(LCD) in power-down mode
Fig. 24. Boundary condition in 1:6 multiplex drive with respect to temperature .............................56
mode ............................................................... 39 Fig. 45. Typical IDD(LCD) when display is active
Fig. 25. Display RAM filling order in 1:8 multiplex with respect to temperature .............................57
drive mode ...................................................... 40 Fig. 46. Typical clock frequency with respect to
Fig. 26. PWM register filling ......................................... 41 VDD and temperature ..................................... 58
Fig. 27. General-purpose output block diagram ........... 42 Fig. 47. Driver timing waveforms ..................................58
Fig. 28. PWM example waveforms for PWMI = 0 .........43 Fig. 48. RESET timing ..................................................58
Fig. 29. Configuration for two RGB clusters ................. 44 Fig. 49. I2C-bus timing waveforms ...............................60
Fig. 30. PWM example waveforms for PWMI = 1 .........45 Fig. 50. SPI-bus timing .................................................61
Fig. 31. Control byte format ......................................... 46 Fig. 51. Package outline SOT364-1 (TSSOP56) ..........62
Fig. 32. Bit transfer .......................................................46 Fig. 52. Temperature profiles for large and small
Fig. 33. Definition of START and STOP conditions ...... 47 components ..................................................... 65
Fig. 34. System configuration .......................................47 Fig. 53. Footprint information for reflow soldering of
Fig. 35. Acknowledgement on the I2C-bus .................. 48 SOT364-1 (TSSOP56) package ......................66
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Contents
1 General description ............................................ 1 7.10 PWM registers and data pointer (PWM
2 Features and benefits .........................................1 part) ..................................................................40
3 Applications .........................................................2 7.11 GPO output ......................................................41
4 Ordering information .......................................... 2 7.11.1 RGB color driving ............................................ 43
4.1 Ordering options ................................................ 2 7.11.2 PWM inversion mode ...................................... 45
5 Block diagram ..................................................... 3 8 Bus interfaces ................................................... 45
6 Pinning information ............................................ 4 8.1 Control byte and register selection .................. 45
6.1 Pinning ............................................................... 4 8.2 I2C-bus interface ............................................. 46
6.2 Pin description ................................................... 6 8.2.1 Bit transfer ....................................................... 46
7 Functional description ........................................7 8.2.2 START and STOP conditions .......................... 46
7.1 Commands of PCA8536 ....................................7 8.2.3 System configuration ....................................... 47
7.1.1 Command: initialize ........................................... 8 8.2.4 Acknowledge ....................................................47
7.1.2 Command: OTP-refresh .................................... 8 8.2.5 I2C-bus controller ............................................ 48
7.1.3 Command: PWM-inversion ................................ 8 8.2.6 Input filters ....................................................... 48
7.1.4 Command: mode-settings ..................................8 8.2.7 I2C-bus target address .................................... 48
7.1.4.1 Backplane swapping ..........................................9 8.2.8 I2C-bus protocol .............................................. 48
7.1.4.2 Line inversion (driving scheme A) and 8.2.8.1 Status read out ................................................ 49
frame inversion (driving scheme B) ................. 10 8.3 SPI-bus interface ............................................. 50
7.1.4.3 Power-down mode ...........................................10 8.3.1 Data transmission ............................................ 50
7.1.4.4 Display enable ................................................. 12 9 Internal circuitry ................................................ 52
7.1.5 Command: oscillator-control ............................ 12 10 Limiting values .................................................. 52
7.1.5.1 Oscillator .......................................................... 13 11 Static characteristics ........................................ 53
7.1.5.2 Timing and frame frequency ............................ 15 12 Dynamic characteristics ...................................57
7.1.6 Command: GPO-output-config ........................ 15 13 Test information ................................................ 61
7.1.7 Command: set-MUX-mode .............................. 16 13.1 Quality information ...........................................61
7.1.8 Command: set-bias-mode ............................... 16 14 Package outline .................................................62
7.1.9 Command: frame-frequency-LCD ....................16 15 Handling information ........................................ 63
7.1.10 Command: frame-frequency-PWM .................. 18 16 Soldering of SMD packages .............................63
7.1.11 Command: GPO-static-data .............................19 16.1 Introduction to soldering .................................. 63
7.1.12 Command: load-data-pointer-LCD ...................20 16.2 Wave and reflow soldering .............................. 63
7.1.13 Command: load-data-pointer-PWM ................. 21 16.3 Wave soldering ................................................ 63
7.1.14 Command: write-RAM-data ............................. 21 16.4 Reflow soldering .............................................. 64
7.1.15 Command: write-PWM-data .............................21 17 Footprint information for reflow soldering ..... 66
7.2 Start-up and shut-down ................................... 21 18 Appendix: possible PWM and LCD frame
7.2.1 Reset and Power-On Reset (POR) ..................21 frequency combinations to avoid flicker .........67
7.2.2 RESET pin function ......................................... 22 19 Abbreviations .................................................... 70
7.2.3 Recommended start-up sequences ................. 23 20 References ......................................................... 70
7.3 Possible display configurations ........................24 21 Revision history ................................................ 71
7.4 LCD voltage selector ....................................... 26 22 Legal information .............................................. 72
7.4.1 Electro-optical performance ............................. 27
7.5 LCD drive mode waveforms ............................ 28
7.5.1 1:4 Multiplex drive mode ................................. 28
7.5.2 1:6 Multiplex drive mode ................................. 29
7.5.3 1:8 Multiplex drive mode ................................. 32
7.6 Display register ................................................ 34
7.7 Backplane outputs ........................................... 34
7.8 Segment outputs ............................................. 34
7.9 Display RAM ....................................................34
7.9.1 Data pointer (LCD part) ................................... 36
7.9.2 RAM filling in 1:4 multiplex drive mode ............36
7.9.3 RAM filling in 1:6 multiplex drive mode ............37
7.9.4 RAM filling in 1:8 multiplex drive mode ............39
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