A8293 Datasheet
A8293 Datasheet
A8293 Datasheet
Pre-End-of-Life
This device is in production, however, a currently available next
generation replacement part is available.
Allegro MicroSystems, LLC reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A8293
28 contact, 5 5 mm
MLP/QFN (suffix ET) Continued on the next page
C2 C4
100 F C6 100 nF
C5
100 F 1 F
C1
100 nF VIN LX GNDLX BOOST VCP
VREG
Charge D3
Pump A
C3
220 nF
Regulator Boost
Converter
TMode
EXTM
fsw
VDD
LNB
Wave VOUT
R1 R2 R3 R4 DAC Voltage Linear
Control Shape Stage
LNB
TCAP D4
D2 C8 C10 C9 A
TGate 100 nF 220 nF 10 nF
EXTM fsw
Fault Monitor
SDA
I 2 C- OCP Clock
Compatible PNG Divider 22 kHz TCAP
SCL Interface TSD Oscillator C7
VUV 10 nF (or 22 nF)
ADD
PAD GND
Description (continued)
A comprehensive set of fault registers are provided, which comply The A8293 is supplied in two lead (Pb) free MLP/QFN packages:
with all the common standards, including: overcurrent, thermal ES, 20-contact, 4 mm 4 mm, 0.75 nominal overall height, and
shutdown, undervoltage, and power not good. ET, 28-contact, 5 mm 5 mm, 0.90 nominal overall height.
The device uses a 2-wire bidirectional serial interface, compatible
with the I2C standard, that operates up to 400kHz.
Selection Guide
Part Number Packing 1 Description
7 in. reel, 1500 pieces/reel ES package, MLP/QFN surface mount
A8293SESTR-T 2 12 mm carrier tape 4 mm 4 mm 0.75 mm nominal height
7 in. reel, 1500 pieces/reel ET package, MLP/QFN surface mount
A8293SETTR-T 2 12 mm carrier tape 5 mm 5 mm 0.90 mm nominal height
1 Contact Allegro for additional packing options.
2 Leadframe plating 100% matte tin.
27 GNDLX
22 FLOAT
19 GND
20 LNB
28 LNB
17 VIN
25 VIN
16 NC
24 NC
23 NC
18 LX
26 LX
BOOST 1 15 FLOAT BOOST 1 21 NC
VCP 2 14 GND VCP 2 20 NC
TCAP 3 PAD 13 NC TCAP 3 19 GND
FLOAT 4 12 SCL NC 4 PAD 18 NC
EXTM 5 11 IRQ FLOAT 5 17 NC
EXTM 6 16 NC
ADD 10
6
7
8
SDA 9
NC 7 15 NC
NC
GND
VREG
SDA 10
SCL 12
NC 13
IRQ 14
ADD 11
8
9
GND
VREG
(Top View)
ES Package ET Package
SDA
SCL
tLOW tHIGH
Functional Description
Protection and fall times can be set by the value of the capacitor connected
from the TCAP pin to GND (CTCAP or C7 in the Applications
The A8293 has a wide range of protection features and fault diag- Schematic). Note that during start-up, the BOOST pin is pre-
nostics which are detailed in the Status Register section. charged to the input voltage minus a voltage drop. As a result,
the slew rate control for the BOOST pin occurs from this voltage.
Boost Converter/Linear Regulator The value of CTCAP can be calculated using the following for-
mula:
The A8293 solution contains a tracking current-mode boost
CTCAP = (ITCAP 6) / SR ,
converter and linear regulator. The boost converter tracks the
requested LNB voltage to within 800 mV, to minimize power where SR is the required slew rate of the LNB output voltage,
dissipation. Under conditions where the input voltage, VBOOST, in V/s, and ITCAP is the TCAP pin current specified in the data
is greater than the output voltage, VLNB, the linear regulator must sheet. The recommended value for CTCAP, 10 nF, should provide
drop the differential voltage. When operating in these conditions, satisfactory operation for most applications. However, in some
care must be taken to ensure that the safe operating temperature cases, it may be necessary to increase the value of CTCAP to avoid
range of the A8293 is not exceeded. activating the current limit of the LNB output. One such situa-
The boost converter operates at 352 kHz typical: 16 times tion is when two set-top boxes are connected in parallel. If this is
the internal 22 kHz tone frequency. All the loop compensation, the case, the following formula can be used to calculate CTCAP:
current sensing, and slope compensation functions are provided
internally. CTCAP (ITCAP 6)(2 CBOOST) / ILIMLNB ,
The A8293 has internal pulse-by-pulse current limiting on
the boost converter and DC current limiting on the LNB output CTCAP (10 A 6)(2 100 F) / 500 mA = 24 nF .
to protect the IC against short circuits. When the LNB output is
shorted, the LNB output current is limited to 700 mA typical, The minimum value of CTCAP is 2.2 nF. There is no theoretical
and the IC will be shut down if the overcurrent condition lasts maximum value of CTCAP however too large a value will prob-
for more than 48 ms. If this occurs, the A8293 must be reenabled ably cause the voltage transition specification to be exceeded.
for normal operation. The system should provide sufficient time Tone generation is unaffected by the value of CTCAP .
between successive restarts to limit internal power dissipation; a Pull-Down Rate Control. In applications that have to operate at
minimum of 2 s is recommended. very light loads and that require large load capacitances (in the
At extremely light loads, the boost converter operates in a order of tens to hundreds of microfarads), the output linear stage
pulse-skipping mode. Pulse skipping occurs when the BOOST provides approximately 40 mA of pull-down capability. This
voltage rises to approximately 450 mV above the BOOST target ensures that the output volts are ramped from 18 V to 13 V in a
output voltage. Pulse skipping stops when the BOOST voltage reasonable amount of time.
drops 200 mV below the pulse skipping level.
In the case that two or more set top box LNB outputs are con- ODT (Overcurrent Disable Time)
nected together by the customer (e.g., with a splitter), it is pos- If the LNB output current exceeds 700 mA, typical, for more than
sible that one output could be programmed at a higher voltage 48 ms, then the LNB output will be disabled and the OCP bit will
than the other. This would cause a voltage on one output that is be set.
higher than its programmed voltage (e.g., 19 V on the output of a
Short Circuit Handling
13 V programmed voltage). The output with the highest voltage
will effectively turn off the other outputs. As soon as this voltage If the LNB output is shorted to ground, the LNB output current
is reduced below the value of the other outputs, the A8293 output will be clamped to 700 mA, typical. If the short circuit condition
will auto-recover to their programmed levels. lasts for more than 48 ms, the A8293 will be disabled and the
OCP bit will be set.
Charge Pump. Generates a supply voltage above the internal
tracking regulator output to drive the linear regulator control. Auto-Restart
Slew Rate Control. During either start-up, or when the output After a short circuit condition occurs, the host controller should
voltage at the LNB pin is transitioning, the output voltage rise periodically reenable the A8293 to check if the short circuit has
been removed. Consecutive startup attempts should allow at least EXTM pin (external modulation), in conjunction with the I2C
2s of delay between restarts. control bits: TMODE (tone modulation) and TGATE (tone gate),
provide the necessary control. The TMODE bit controls whether
In-Rush Current
the tone source is either internal or external (via the EXTM pin).
At start-up or during an LNB reconfiguration event, a tran- Both the EXTM pin and TGATE bit determine the 22kHz con-
sient surge current above the normal DC operating level can be trol, whether gated or clocked.
provided by the A8293. This current increase can be as high as Four options for tone generation are shown in figure 1. Note
700mA, typical, for as long as required, up to a maximum of that when using option 4, when EXTM stops clocking, the LNB
48ms. volts park at the LNB voltage, either plus or minus half the tone
Tone Generation signal amplitude, depending on the state of EXTM. For example,
The A8293 solution offers four options for tone generation, if the EXTM is held low, the LNB DC voltage is the LNB pro-
providing maximum flexibility to cover every application. The grammed voltage minus 325 mV (typical).
EXTM
TMODE
TGATE
Tone
LNB (V)
(LNB Ref)
EXTM
TMODE
TGATE
Tone
LNB (V)
(LNB Ref)
Option 2 Use internal tone, gated by the EXTM pin.
EXTM
TMODE
TGATE
Tone
LNB (V)
(LNB Ref)
Option 3 Use external tone, gated by the TGATE bit.
EXTM
TMODE
TGATE
Tone
LNB (V)
(LNB Ref)
Option 4 Use external tone.
Figure 1. Options for tone generation
I2C-Compatible Interface fined by the remaining two bits, are selected by the ADD input.
The address is transmitted MSB first.
This is a serial interface that uses two bus lines, SCL and SDA, 3. Data Cycles.
to access the internal Control and Status registers of the A8293. Write 6 bits of data and 2 bits for addressing four internal
Data is exchanged between a microcontroller (master) and the control registers, followed by an acknowledge bit. See Control
A8293 (slave). The clock input to SCL is generated by the master, Register section for more information.
while SDA functions as either an input or an open drain output, Read Two status registers, where register 1 is read first,
depending on the direction of the data. followed by register 2, then register 1, and so on. At the start
of any read sequence, register 1 is always read first. Data is
Timing Considerations transmitted MSB first.
4. Stop Condition. Defined by a positive edge on the SDA line,
The control sequence of the communication through the I2C- while SCL is high. Except to indicate a Start or Stop condi-
compatible interface is composed of several steps in sequence: tion, SDA must be stable while the clock is high. SDA can
1. Start Condition. Defined by a negative edge on the SDA line, only be changed while SCL is low. It is possible for the Start or
while SCL is high. Stop condition to occur at any time during a data transfer. The
2. Address Cycle. 7 bits of address, plus 1 bit to indicate read (1) A8293 always responds by resetting the data transfer sequence.
or write (0), and an acknowledge bit. The first five bits of the The Read/Write bit is used to determine the data transfer direc-
address are fixed as: 00010. The four optional addresses, de- tion. If the Read/Write bit is high, the master reads the contents of
acknowledge acknowledge
from LNBR from LNBR
Start Address W Control Data Stop
SDA 0 0 0 1 0 A1 A0 0 AK I1 I0 D5 D4 D3 D2 D1 D0 AK
SCL 1 2 3 4 5 6 7 8 9
Write to Register
acknowledge no acknowledge
from LNBR from master
Start Address R Status Register 1 Stop
SDA 0 0 0 1 0 A1 A0 1 AK D7 D6 D5 D4 D3 D2 D1 D0 NAK
SCL 1 2 3 4 5 6 7 8 9
SDA 0 0 0 1 0 A1 A0 1 AK D7 D6 D5 D4 D3 D2 D1 D0 AK - - - - D3 D2 D1 D0 NAK
SCL 1 2 3 4 5 6 7 8 9
register 1, followed by register 2 if a further read is performed. If be used with other I2C-compatible devices to request attention
the Read/Write bit is low, the master writes data to one of the two from the master controller.
Control registers. Note that multiple writes are not permitted. All The IRQ output becomes active when either the A8293 first
write operations must be preceded with the address. recognizes a fault condition, or at power-on, when the main sup-
The Acknowledge bit has two functions. It is used by the mas-
ply, VIN, and the internal logic supply, VREG, reach the correct
ter to determine if the slave device is responding to its address
operating conditions. It is only reset to inactive when the I2C
and data, and it is used by the slave when the master is reading
data back from the slave. When the A8293 decodes the 7-bit ad- master addresses the A8293 with the Read/Write bit set (caus-
dress field as a valid address, it responds by pulling SDA low ing a read). Fault conditions are indicated by the TSD, VUV, and
during the ninth clock cycle. OCP bits, and are latched in the Status register. See the Status
During a data write from the master, the A8293 also pulls SDA register section for full description.
low during the clock cycle that follows the data byte, in order to The DIS and PNG status bits do not cause an interrupt. The
indicate that the data has been successfully received. In both cas- PNG bit is continually updated, apart from the DIS bit, which
es, the master device must release the SDA line before the ninth changes when the LNB is either disabled, faulted, or is enabled.
clock cycle, in order to allow this handshaking to occur.
When the master recognizes an interrupt, it addresses all
During a data read, the A8293 acknowledges the address in the
slaves connected to the interrupt line in sequence, and then reads
same way as in the data write sequence, and then retains control
of the SDA line and send the data from register 1 to the master. the status register to determine which device is requesting atten-
On completion of the eight data bits, the A8293 releases the SDA tion. The A8293 latches all conditions in the Status register until
line before the ninth clock cycle, in order to allow the master to the completion of the data read. The action at the resampling
acknowledge the data. If the master holds the SDA line low dur- point is further defined in the Status Register section. The bits in
ing this Acknowledge bit, the A8293 responds by sending the the Status register are defined such that the all-zero condition in-
data from register 2 to the master. Data bytes continue to be sent dicates that the A8293 is fully active with no fault conditions.
to the master until the master releases the SDA line during the When VIN is initially applied, the I2C-compatible interface
Acknowledge bit. When this is detected, the A8293 stops sending
does not respond to any requests until the internal logic supply
data and waits for a stop signal.
VREG has reached its operating level. Once VREG has reached this
Interrupt Request point, the IRQ output goes active, and the VUV bit is set. After
The A8293 also provides an interrupt request pin, IRQ, which the A8293 acknowledges the address, the IRQ flag is reset. After
is an open-drain, active-low output. This output may be connect- the master reads the status registers, the registers are updated with
ed to a common IRQ line with a suitable external pull-up and can the VUV reset.
SDA 0 0 0 1 0 A1 A0 1 AK D7 D6 D5 D4 D3 D2 D1 D0 NAK
SCL 1 2 3 4 5 6 7 8 9
IRQ
Fault Reload
Event Status Register
Read after Interrupt
Control Registers (I2C-Compatible Write Register) control registers. Each register contains up to 6 bits of data (bit
0 to bit5), followed by 2 bits for the register address (bit 6 and
All main functions of the A8293 are controlled through the I2C- bit7). The power-up states for the control functions are all 0s.
compatible interface via the 8-bit Control registers. As the A8293 The following tables define the control bits for each address
contains numerous control options, it is necessary to have two and the settings for output voltage:
Bit 0 VSEL0 These three bits provide incremental control over the voltage on the LNB output.
Bit 1 VSEL1 The available voltages provide the necessary levels for all the common standards
Bit 2 VSEL2 plus the ability to add line compensation in increments of 333 mV. The voltage
levels are defined in table 3, Output Voltage Amplitude Selection.
Bit 3 VSEL3 Switches between the low level and high level output voltages on the LNB output.
0selects the low level voltage and 1 selects the high level. The low-level center voltage
is 12.709 V nominal and the high level is 18.042 V nominal. These may be increased
in steps of 333mV using the VSEL2, VSEL1 and VSEL0 control register bits.
Bit 4 ODT The overcurrent disable timer is always enabled.
Bit 5 ENB Enables the LNB output. When set to 1 the LNB output is switched on. When set to
0, the LNB output is disabled.
Bit 6 I0 Address
Bit 7 I1 Address
Bit 0 TMODE Tone Mode. Selects between the use of an external 22 kHz logic signal or the use of
the internal 22 kHz oscillator to control the tone generation on the LNB output. A 0
selects the external tone and a 1 selects the internal tone. See the Tone Generation
section for more information
Bit 1 TGATE Tone Gate. Allows either the internal or external 22 kHz tone signals to be gated,
unless the EXTM is selected for gating. When set to 0, the selected tone (via
TMODE) is off. When set to 1, the selected tone is on. See Tone Generation Section
for more information.
Bit 2 Not Used.
Bit 3 Not Used.
Bit 4 Not Used.
Bit 5 Not Used.
Bit 6 I0 Address.
Bit 7 I1 Address.
Status Registers (I2C-Compatible Read Register) As the A8293 has a comprehensive set of status reporting bits,
it is necessary to have two Status registers. When performing a
The main fault conditions: overcurrent (OCP), undervoltage multiple read function, register 1 is read followed by register 2,
(VUV) and overtemperature (TSD), are all indicated by setting
then register 1 again and so on. Whenever a new read function is
the relevant bits in the Status registers. In all fault cases, once the
performed, register 1 is always read first.
bit is set, it remains latched until the A8293 is read by the I2C
The normal sequence of the master in a fault condition will be
master, assuming the fault has been resolved.
to detect the fault by reading the Status registers, then rereading
The current status of the LNB output is indicated by the dis-
the Status registers until the status bit is reset indicating the fault
able bit, DIS. The DIS bit is set when either a fault occurs or if
the LNB is disabled intentionally. This bit is latched, and is reset condition is reset. The fault may be detected either by continuously
when the LNB is commanded on again. The power not good polling, by responding to an interrupt request (IRQ), or by detect-
(PNG) is the only bit which may be reset without an I2C read ing a fault condition externally and performing a diagnostic poll of
sequence. Table4 summarizes the condition of each bit when set all slave devices. Note that the fully-operational condition of the
and how it is reset. Status registers is all 0s, to simplify checking of the Status bit.
Bit 0 DIS LNB Output Disabled. DIS is used to indicate the current condition of the LNB
output. At power-on, or if a fault condition occurs, DIS will be set. This bit changing
to 1 does not cause the IRQ to activate because the LNB output may be disabled in-
tentionally by the I2C master. This bit will be reset at the end of a write sequence
if the LNB output is enabled.
Bit 1 Not used.
Bit 2 OCP Overcurrent. If the LNB output detects an overcurrent condition, for greater than
48ms, the LNB output will be disabled. The OCP bit will be set to indicate that an
overcurrent has occurred and the disable bit, DIS, will be set. The Status register is
updated on the rising edge of the 9th clock pulse in the data read sequence, where the
OCP bit is reset in all cases, allowing the master to reenable the LNB output.
If the overcurrent timer is not enabled, the device operate in current limit indefinitely
and the OCP bit will be set. If the overcurrent condition is removed, the OCP bit will
automatically be reset. Note that if the overcurrent operates long enough, and a ther-
mal shutdown occurs, the LNB output will be disabled and the TSD bit will be set.
Bit 3 Not used.
Bit 4 PNG Power Not Good. Set to 1 when the LNB output is enabled and the LNB voltage is
below 85% of the programmed voltage. The PNG is reset when the LNB volts are
within 90% of the programmed LNB voltage.
Bit 5 Not used.
Bit 6 TSD Thermal Shutdown. 1 indicates that the A8293 has detected an overtemperature
condition and has disabled the LNB output. The disable bit, DIS, will also be set.
The status of the overtemperature condition is sampled on the rising edge of the 9th
clock pulse in the data read sequence. If the condition is no longer present, then the
TSD bit will be reset, allowing the master to reenable the LNB output if required. If
the condition is still present, then the TSD bit will remain at 1.
Bit 7 VUV Undervoltage Lockout. 1 indicates that the A8293 has detected that the input sup-
ply, VIN is, or has been, below the minimum level and an undervoltage lockout has
occurred disabling the LNB outputs. The disable bit, DIS, will also be set and the
A8293 will not reenable the output until so instructed by writing the relevant bit into
the control registers. The status of the undervoltage condition is sampled on the rising
edge of the 9th clock pulse in the data read sequence. If the condition is no longer
present, then the VUV bit will be reset allowing the master to reenable the LNB out-
put if required. If the condition is still present, then the VUV bit will remain at 1.
0.30
4.00 0.10
20 0.50
20
0.95
1
A 1
2
2
4.00 0.10 2.45 4.10
2.45
4.10
+0.05
0.25 0.07 0.75 0.05 For Reference Only, not for tooling use (reference DWG-2864, JEDEC MO-220 WGGD)
Dimensions in millimeters
0.50 Exact case and lead configuration at supplier discretion within limits shown
0.30
5.00 0.15
1.15 28 0.50
28
1
2 A 1
3.15
29X D C
SEATING 4.80
0.08 C PLANE
+0.05 C PCB Layout Reference View
0.25 0.07 0.90 0.10
0.50
Revision History
Number Date Description
4 March 12, 2012 Update Output Voltage Amplitude
5 December 5, 2016 Updated product status to Not for New Design
6 June 5, 2017 Updated product status to Pre-EOL