Aduc845 847 848
Aduc845 847 848
Aduc845 847 848
04741-001
WAKE-UP/ 4 × PARALLEL UART, SPI, AND I 2C
OSC
Dual 16-bit Σ-Δ DACs RTC TIMER PORTS SERIAL I/O
Dual excitation current sources (200 µA) Figure 1. ADuC845 Functional Block Diagram
Time interval counter (wake-up/RTC timer)
UART, SPI®, and I2C® serial I/O
High speed dedicated baud rate generator (incl. 115,200)
Watchdog timer (WDT)
Power supply monitor (PSM)
TABLE OF CONTENTS
Specifications..................................................................................... 4 ADC SFR Interface..................................................................... 39
Pin Configurations and Function Descriptions ......................... 11 ADC0CON1 (Primary ADC Control Register) ..................... 43
General Description ....................................................................... 15 ADC0CON2 (Primary ADC Channel Select Register) ........ 44
8052 Instruction Set ................................................................... 18 SF (ADC Sinc Filter Control Register) .................................... 46
Timer Operation ......................................................................... 18 ICON (Excitation Current Sources Control Register) .......... 47
REVISION HISTORY
12/12—Rev. B to Rev. C
Changes to Figure 3 and Table 3 ...................................................11 Changes to Table 25 ........................................................................ 43
Changes to Burnout Current Sources Section.............................32 Changes to Table 26 ........................................................................ 44
Change to ADCMODE (ADC Mode Register) Section.............42 Changes to Table 27 ........................................................................ 45
Changes to Mode 4 (Dual NRZ 16-Bit Σ-∆ DAC) Section ............58 Changes to User Download Mode Section .................................. 50
Change to Hardware Slave Mode Section ....................................63 Added Figure 51 and Renumbered Subsequent Figures ............ 50
Updated Outline Dimensions ......................................................104 Edits to the DACH/DACL Data Registers Section ..................... 53
Changes to Ordering Guide .........................................................105 Changes to Table 34 ........................................................................ 56
Added SPIDAT: SPI Data Register Section ................................. 65
2/05—Rev. A to Rev. B Changes to Table 42 ........................................................................ 67
Changes to Figure 1........................................................................... 1 Changes to Table 43 ........................................................................ 68
Changes to the Burnout Current Sources Section ......................32 Changes to Table 44 ........................................................................ 69
Changes to the Excitation Currents Section ................................36 Changes to Table 45 ........................................................................ 71
Changes to Table 30 ........................................................................47 Changes to Table 50 ........................................................................ 75
Changes to the Flash/EE Memory on the ADuC845, ADuC847, Changes to Timer/Counter 0 and 1 Data Registers Section...... 76
ADuC848 Section......................................................................48 Changes to Table 54 ........................................................................ 80
Changes to Figure 39 ......................................................................57 Added the SBUF—UART Serial Port Data Register Section..... 80
Changes to On-Chip PLL (PLLCON) Section ............................60 Addition to the Timer 3 Generated Baud Rates Section ........... 83
Added 3 V Part Section Heading ..................................................88 Added Table 57 and Renumbered Subsequent Tables ............... 84
Added 5 V Part Section ..................................................................88 Changes to Table 61 ........................................................................ 86
Changes to Figure 70 ......................................................................91
Changes to Figure 71 ......................................................................93 4/04—Revision 0: Initial Version
6/04—Rev. 0 to Rev. A
Changes to Figure 5.........................................................................17
Changes to Figure 6.........................................................................18
Changes to Figure 7.........................................................................19
Changes to Table 5 ..........................................................................24
Changes to Table 24 ........................................................................41
SPECIFICATIONS1
AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V, REFIN(–) = AGND; AGND =
DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz crystal; all specifications TMIN to TMAX, unless otherwise noted. Input buffer on for primary
ADC, unless otherwise noted. Core speed = 1.57 MHz (default CD = 3), unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Conditions
PRIMARY ADC
Conversion Rate 5.4 105 Hz Chop on (ADCMODE.3 = 0)
16.06 1365 Hz Chop off (ADCMODE.3 = 1)
No Missing Codes2 24 Bits ≤26.7 Hz update rate with chop enabled
24 Bits ≤80.3 Hz update rate with chop disabled
Resolution (ADuC845/ADuC847) See Table 11 and Table 15
Resolution (ADuC848) See Table 13 and Table 17
Output Noise (ADuC845/ADuC847) See Table 10 and Table 14 μV (rms) Output noise varies with selected update rates,
gain range, and chop status.
Output Noise (ADuC848) See Table 12 and Table 16 μV (rms) Output noise varies with selected update rates,
gain range, and chop status.
Integral Nonlinearity ±15 ppm of FSR 1 LSB16
Offset Error3 ±3 μV Chop on
Chop off, offset error is in the order of the noise
for the programmed gain and update rate
following a calibration.
Offset Error Drift vs. Temperature2 ±10 nV/°C Chop on (ADCMODE.3 = 0)
±200 nV/°C Chop off (ADCMODE.3 = 1)
Full-Scale Error4
ADuC845/ADuC847 ±10 μV ±20 mV to ±2.56 V
ADuC848 ±10 μV ±20 mV to ±640 mV
±0.5 LSB16 ±1.28 V to ±2.56 V
Gain Error Drift vs. Temperature4 ±0.5 ppm/°C
Power Supply Rejection
80 dB AIN = 1 V, ±2.56 V, chop enabled
113 dB AIN = 7.8 mV, ±20 mV, chop enabled
80 dB AIN = 1 V, ±2.56 V, chop disabled2
PRIMARY ADC ANALOG INPUTS
Differential Input Voltage Ranges 5, 6 Gain = 1 to 128
Bipolar Mode (ADC0CON1.5 = 0) ±1.024 × V VREF = REFIN(+) − REFIN(−) or
VREF/GAIN REFIN2(+) − REFIN2(−) (or Int 1.25 VREF)
Unipolar Mode (ADC0CON1.5 = 1) 0 – 1.024 × V VREF = REFIN(+) − REFIN(−) or
VREF/GAIN REFIN2(+) − REFIN2(−) (or Int 1.25 VREF)
ADC Range Matching ±2 μV AIN = 18 mV, chop enabled
Common-Mode Rejection DC Chop enabled, chop disabled
On AIN 95 dB AIN = 7.8 mV, range = ±20 mV
113 dB AIN = 1 V, range = ±2.56 V
Common-Mode Rejection 50 Hz/60 Hz ± 1 Hz, 16.6 Hz and 50 Hz update
50 Hz/60 Hz2 rate, chop enabled, REJ60 enabled
On AIN 95 dB AIN = 7.8 mV, range = ±20 mV
90 dB AIN = 1 V, range = ±2.56 V
Footnotes at end of table.
• The ADuC845BCP, ADuC847BCP, and ADuC848BCP (LFCSP package) have been qualified and tested with the base of the LFCSP
package floating. The base of the LFCSP package should be soldered to the board, but left floating electrically, to ensure good
mechanical stability.
• Flash/EE memory reliability characteristics apply to both the Flash/EE program memory and Flash/EE data memory.
1
AGND and DGND are shorted internally on the ADuC845, ADuC847, and ADuC848.
2
Applies to the P1.0 to P1.7 pins operating in analog or digital input modes.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
P1.0/AIN1
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
DGND
PSEN
DGND
DVDD
PSEN
DVDD
ALE
ALE
EA
EA
52 51 50 49 48 47 46 45 44 43 42 41 40
51
56
55
54
53
52
50
49
48
47
46
45
44
43
P1.0/AIN1 1 39 P2.7/PWMCLK P1.1/AIN2 1 42 P2.7/PWMCLK
PIN 1
P1.1/AIN2 2 IDENTIFIER 38 P2.6/PWM1 P1.2/AIN3/REFIN2+ 2 41 P2.6/PWM1
P1.2/AIN3/REFIN2+ 3 37 P2.5/PWM0 P1.3/AIN4/REFIN2– 3 40 P2.5/PWM0
P1.3/AIN4/REFIN2– 4 36 P2.4/T2EX AVDD 4 39 P2.4/T2EX
AVDD 5 35 DGND AGND 5 38 DGND
AGND 6
ADuC845/ADuC847/ADuC848 34 DVDD AGND 6 ADuC845/ADuC847/ 37 DGND
REFIN– 7 33 XTAL2 REFIN– 7 ADuC848 36 DVDD
REFIN+ 8 TOP VIEW 32 XTAL1
REFIN+ 8 TOP VIEW 35 XTAL2
(Not to Scale) P1.4/AIN5 (Not to Scale)
P1.4/AIN5 9 31 P2.3/SS/T2 9 34 XTAL1
P1.5/AIN6 10 33 P2.3/SS/T2
P1.5/AIN6 10 30 P2.2/MISO
P1.6/AIN7/IEXC1 11 32 P2.2/MISO
P1.6/AIN7/IEXC1 11 29 P2.1/MOSI
P1.7/AIN8/IEXC2 12 31 P2.1/MOSI
P1.7/AIN8/IEXC2 12 28 P2.0/SCLOCK (SPI)
AINCOM/DAC 13 30 P2.0/SCLOCK (SPI)
AINCOM/DAC 13 27 SDATA
DAC 14 29 SDATA
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14 15 16 17 18 19 20 21 22 23 24 25 26
DVDD
DAC
RESET
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
DGND
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
SCLOCK (I2C)
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.1/TxD
AIN9
RESET
DGND
P3.7/RD
SCLK (I2C)
DVDD
AIN10
P3.0/RxD
04741-002
04741-003
NOTES
1. THE EXPOSED PADDLE MUST BE LEFT UNCONNECTED.
Figure 2. 52-Lead MQFP Pin Configuration
Figure 3. 56-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No: Pin No:
52-MQFP 56-LFCSP Mnemonic Type 1 Description
1 56 P1.0/AIN1 I By power-on default, P1.0/AIN1 is configured as the AIN1 analog input.
AIN1 can be used as a pseudo differential input when used with AINCOM or as
the positive input of a fully differential pair when used with AIN2.
P1.0 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high
or low externally.
2 1 P1.1/AIN2 I On power-on default, P1.1/AIN2 is configured as the AIN2 analog input.
AIN2 can be used as a pseudo differential input when used with AINCOM or as
the negative input of a fully differential pair when used with AIN1.
P1.1 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high
or low externally.
3 2 P1.2/AIN3/REFIN2+ I On power-on default, P1.2/AIN3 is configured as the AIN3 analog input.
AIN3 can be used as a pseudo differential input when used with AINCOM or as
the positive input of a fully differential pair when used with AIN4.
P1.2 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high
or low externally. This pin also functions as a second external differential
reference input, positive terminal.
4 3 P1.3/AIN4/REFIN2− I On power-on default, P1.3/AIN4 is configured as the AIN4 analog input.
AIN4 can be used as a pseudo differential input when used with AINCOM or as
the negative input of a fully differential pair when used with AIN3.
P1.3 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high
or low externally. This pin also functions as a second external differential
reference input, negative terminal.
5 4 AVDD S Analog Supply Voltage.
6 5 AGND S Analog Ground.
--- 6 AGND S A second analog ground is provided with the LFCSP version only.
7 7 REFIN− I External Differential Reference Input, Negative Terminal.
8 8 REFIN+ I External Differential Reference Input, Positive Terminal.
Footnotes at end of table.
GENERAL DESCRIPTION
The ADuC845, ADuC847, and ADuC848 are single-cycle, The devices operate from a 32 kHz crystal with an on-chip PLL
12.58 MIPs, 8052 core upgrades to the ADuC834 and generating a high frequency clock of 12.58 MHz. This clock is
ADuC836. They include additional analog inputs for routed through a programmable clock divider from which the
applications requiring more ADC channels. MCU core clock operating frequency is generated. The micro-
controller core is an optimized single-cycle 8052 offering up to
The ADuC845, ADuC847, and ADuC848 are complete smart 12.58 MIPs performance while maintaining 8051 instruction set
transducer front ends. The family integrates high resolution compatibility.
Σ-Δ ADCs with flexible, up to 10-channel, input multiplexing, a
fast 8-bit MCU, and program and data Flash/EE memory on a The available nonvolatile Flash/EE program memory options
single chip. are 62 kbytes, 32 kbytes, and 8 kbytes. 4 kbytes of nonvolatile
Flash/EE data memory and 2304 bytes of data RAM are also
The ADuC845 includes two (primary and auxiliary) 24-bit Σ-Δ provided on-chip. The program memory can be configured as
ADCs with internal buffering and PGA on the primary ADC. data memory to give up to 60 kbytes of NV data memory in
The ADuC847 includes the same primary ADC as the ADuC845 data logging applications.
(auxiliary ADC removed). The ADuC848 is a 16-bit ADC
version of the ADuC847. On-chip factory firmware supports in-circuit serial download
and debug modes (via UART), as well as single-pin emulation
The ADCs incorporate flexible input multiplexing, a temperature mode via the EA pin. The ADuC845, ADuC847, and ADuC848
sensor (ADuC845 only), and a PGA (primary ADC only)
are supported by the QuickStart™ development system featuring
allowing direct measurement of low-level signals. The ADCs
low cost software and hardware development tools.
include on-chip digital filtering and programmable output data
rates that are intended for measuring wide dynamic range and
low frequency signals, such as those in weigh scale, strain gage,
pressure transducer, or temperature measurement applications.
P2.7/PWMCLK (A15/A23)
P2.5/PWM0 (A13/A21)
P2.6/PWM1 (A14/A22)
P2.3/SS/T2 (A11/A19)
P2.2/MISO (A10/A18)
P2.4/T2EX (A12/A20)
P2.0/SCLK (A8/A16)
P2.1/MOSI (A9/A17)
P1.2/AIN3/REFIN2+
P1.3/AIN4/REFIN2–
P1.6/AIN7/IEXC1
P1.7/AIN8/IEXC2
P3.2 (INT0)
P3.3 (INT1)
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
P3.0 (RxD)
P3.1 (TxD)
P3.6 (WR)
P1.0/AIN1
P1.1/AIN2
P1.4/AIN5
P1.5/AIN6
P3.7 (RD)
P3.4 (T0)
P3.5 (T1)
46 47 48 49 52 53 54 55 56 1 2 3 9 10 11 12 30 31 32 33 39 40 41 42 18 19 20 21 24 25 26 27
AIN1 56 ADuC845
AIN2 1
AIN3 2 12-BIT
ADC DAC
PRIMARY ADC CONTROL VOLTAGE BUF 14 DAC
AIN4 3 BUF PGA CONTROL
24-BIT AND OUTPUT DAC
AIN5 9 - ADC CALIBRATION
AIN
AIN6 10 MUX
DUAL
AIN7 11 ADC 16-BIT 40 PWM0
AUXILIARY ADC
CONTROL PWM - DAC
AIN8 12 24-BIT CONTROL MUX
AND
AIN9 15 - ADC CALIBRATION
DUAL 41 PWM1
16-BIT
AIN10 16 PWM
42 PWMCLK
AINCOM/DAC 13
BAND GAP 62 kBYTES PROGRAM/ 2304 BYTES
FLASH/EE 24 T0
REFERENCE USER RAM
SINGLE- 16-BIT 25 T1
TEMP
COUNTER
SENSOR 4 kBYTES DATA/ CYCLE WATCHDOG TIMERS 33 T2
FLASH/EE 8052 TIMER
REFIN+ 8 VREF 39 T2EX
REFIN– 7 DETECT MCU POWER SUPPLY
2 DATA POINTERS CORE MONITOR
11-BIT STACK POINTER 20 INT0
PLL WITH PROG.
200A 200A CLOCK DIVIDER 21 INT1
DOWNLOADER
DEBUGGER WAKE-UP/
IEXC1 11 CURRENT
SOURCE RTC TIMER
IEXC2 12
SINGLE-PIN
EMULATOR
MIX
UART UART SPI SERIAL I2C SERIAL
POR SERIAL PORT TIMER INTERFACE INTERFACE
OSC
4 5 6 22 36 51 23 37 38 50 17 18 19 44 43 45 30 31 32 33 28 29 34 35
XTAL1
MOSI
SCLK
SCLK
SDATA
MISO
RESET
XTAL2
PSEN
RxD
TxD
EA
ALE
SS
AVDD
AGND
DVDD
DGND
NOTES
04741-004
1. THE PIN NUMBERS REFER TO THE LFCSP PACKAGE ONLY.
P2.7/PWMCLK (A15/A23)
P2.5/PWM0 (A13/A21)
P2.6/PWM1 (A14/A22)
P2.3/SS/T2 (A11/A19)
P2.2/MISO (A10/A18)
P2.4/T2EX (A12/A20)
P2.0/SCLK (A8/A16)
P2.1/MOSI (A9/A17)
P1.2/AIN3/REFIN2+
P1.3/AIN4/REFIN2–
P1.6/AIN7/IEXC1
P1.7/AIN8/IEXC2
P3.2 (INT0)
P3.3 (INT1)
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
P3.0 (RxD)
P3.1 (TxD)
P3.6 (WR)
P1.0/AIN1
P1.1/AIN2
P1.4/AIN5
P1.5/AIN6
P3.7 (RD)
P3.4 (T0)
P3.5 (T1)
46 47 48 49 52 53 54 55 56 1 2 3 9 10 11 12 30 31 32 33 39 40 41 42 18 19 20 21 24 25 26 27
AIN1 56 ADuC847
AIN2 1
AIN3 2 12-BIT
ADC DAC
PRIMARY ADC CONTROL VOLTAGE BUF 14 DAC
AIN4 3 BUF PGA CONTROL
24-BIT AND OUTPUT DAC
AIN5 9 - ADC CALIBRATION
AIN
AIN6 10 MUX
DUAL
AIN7 11 16-BIT 40 PWM0
PWM - DAC
AIN8 12 CONTROL MUX
AIN9 15 DUAL 41 PWM1
16-BIT
AIN10 16 PWM
42 PWMCLK
AINCOM/DAC 13
BAND GAP 62 kBYTES PROGRAM/ 2304 BYTES
FLASH/EE 24 T0
REFERENCE USER RAM
SINGLE- 16-BIT 25 T1
COUNTER
4 kBYTES DATA/ CYCLE WATCHDOG TIMERS 33 T2
FLASH/EE 8052 TIMER
REFIN+ 8 VREF 39 T2EX
REFIN– 7 DETECT MCU POWER SUPPLY
2 DATA POINTERS CORE MONITOR
11-BIT STACK POINTER 20 INT0
PLL WITH PROG.
200A 200A CLOCK DIVIDER 21 INT1
DOWNLOADER
DEBUGGER WAKE-UP/
IEXC1 11 CURRENT
SOURCE RTC TIMER
IEXC2 12
SINGLE-PIN
EMULATOR
MIX
UART UART SPI SERIAL I2C SERIAL
POR SERIAL PORT TIMER INTERFACE INTERFACE
OSC
4 5 6 22 36 51 23 37 38 50 17 18 19 44 43 45 30 31 32 33 28 29 34 35
XTAL1
MOSI
SCLK
SCLK
SDATA
MISO
RESET
XTAL2
PSEN
RxD
TxD
EA
ALE
SS
AVDD
AGND
DVDD
DGND
NOTES
04741-070
1. THE PIN NUMBERS REFER TO THE LFCSP PACKAGE ONLY.
P2.7/PWMCLK (A15/A23)
P2.5/PWM0 (A13/A21)
P2.6/PWM1 (A14/A22)
P2.3/SS/T2 (A11/A19)
P2.2/MISO (A10/A18)
P2.4/T2EX (A12/A20)
P2.0/SCLK (A8/A16)
P2.1/MOSI (A9/A17)
P1.2/AIN3/REFIN2+
P1.3/AIN4/REFIN2–
P1.6/AIN7/IEXC1
P1.7/AIN8/IEXC2
P3.2 (INT0)
P3.3 (INT1)
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
P3.0 (RxD)
P3.1 (TxD)
P3.6 (WR)
P1.0/AIN1
P1.1/AIN2
P1.4/AIN5
P1.5/AIN6
P3.7 (RD)
P3.4 (T0)
P3.5 (T1)
46 47 48 49 52 53 54 55 56 1 2 3 9 10 11 12 30 31 32 33 39 40 41 42 18 19 20 21 24 25 26 27
AIN1 56 ADuC848
AIN2 1
AIN3 2 12-BIT
ADC DAC
PRIMARY ADC CONTROL VOLTAGE BUF 14 DAC
AIN4 3 BUF PGA CONTROL
16-BIT AND OUTPUT DAC
AIN5 9 S-D ADC CALIBRATION
AIN
AIN6 10 MUX
DUAL
AIN7 11 16-BIT 40 PWM0
PWM S-D DAC
AIN8 12 CONTROL MUX
AIN9 15 DUAL 41
16-BIT PWM1
AIN10 16 PWM
42 PWMCLK
AINCOM/DAC 13
BAND GAP 62 kBYTES PROGRAM/ 2304 BYTES
FLASH/EE 24 T0
REFERENCE USER RAM
SINGLE- 16-BIT 25 T1
COUNTER
4 kBYTES DATA/ CYCLE WATCHDOG TIMERS 33
TIMER T2
REFIN+ 8
FLASH/EE 8052
VREF 39 T2EX
REFIN– 7 DETECT MCU POWER SUPPLY
2 × DATA POINTERS CORE MONITOR
11-BIT STACK POINTER 20 INT0
PLL WITH PROG.
200µA 200µA CLOCK DIVIDER 21 INT1
DOWNLOADER
DEBUGGER WAKE-UP/
IEXC1 11 CURRENT
SOURCE RTC TIMER
IEXC2 12
SINGLE-PIN
EMULATOR
MIX
UART UART SPI SERIAL I2C SERIAL
POR SERIAL PORT TIMER INTERFACE INTERFACE
OSC
4 5 6 22 36 51 23 37 38 50 17 18 19 44 43 45 30 31 32 33 28 29 34 35
XTAL1
SCLK
MOSI
SCLK
SDATA
MISO
RESET
XTAL2
AVDD
AGND
DVDD
DGND
RxD
TxD
PSEN
EA
ALE
SS
NOTES
04741-072
1. THE PIN NUMBERS REFER TO THE LFCSP PACKAGE ONLY.
B I2CADD1 SPIDAT
BITS RESERVED NOT USED RESERVED RESERVED RESERVED
F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H 0 F1H 0 F0H 0
F0H 00H F2H 7FH F7H 00H
MDO MDE MCO MDI I2CM I2CRS I2CTX I2CI I2CCON GN0L2 GN0M2 GN0H2 GN1L2 GN1H2
BITS ADuC845 ONLY ADuC845 ONLY RESERVED RESERVED
EFH 0 EEH 0 EDH 0 ECH 0 EBH 0 EAH 0 E9H 0 E8H 0
E8H 00H E9H xxH EAH xxH EBH xxH ECH xxH EDH xxH
RDY0 RDY1 CAL NOXREF ERR0 ERR1 ADCSTAT ADC0L ADC0M ADC0H ADC1M ADC1H ADC1L PSMCON
NOT AVAILABLE
BITS ON ADuC848
ADuC845 ONLY ADuC845 ONLY ADuC845 ONLY
DFH 0 DEH 0 DDH 0 DCH 0 DBH 0 DAH 0 D9H 0 D8H 0 D8H 00H D9H 00H DAH 00H DBH 00H DCH 00H DDH 00H DEH 00H DFH DEH
TF2 EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 T2CON RCAP2L RCAP2H TL2 TH2
BITS RESERVED RESERVED RESERVED
CFH 0 CEH 0 CDH 0 CCH 0 CBH 0 CAH 0 C9H 0 C8H 0 C8H 00H CAH 00H CBH 00H CCH 00H CDH 00H
PRE3 PRE2 PRE1 PRE0 WDIR WDS WDE WDWR WDCON CHIPID EDARL EDARH
BITS RESERVED RESERVED RESERVED RESERVED
C7H 0 C6H 0 C5H 0 C4H 1 C3H 0 C2H 0 C1H 0 C0H 0 C0H 10H C2H A0H C6H 00H C7H 00H
PADC PT2 PS PT1 PX1 PT0 PX0 IP ECON EDATA1 EDATA2 EDATA3 EDATA4
BITS RESERVED RESERVED
BFH 0 BEH 0 BDH 0 BCH 0 BBH 0 BAH 0 B9H 0 B8H 0 B8H 00H B9H 00H BCH 00H BDH 00H BEH 00H BFH 00H
SM0 SM1 SM2 REN TB8 RB8 TI RI SCON SBUF I2CDAT I2CADD T3FD T3CON EWAIT
BITS RESERVED
9FH 0 9EH 0 9DH 0 9CH 0 9BH 0 9AH 0 99H 0 98H 0 98H 00H 99H 00H 9AH 00H 9BH 55H 9DH 00H 9EH 00H 9FH 00H
T2EX T2 P1
BITS RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
97H 1 96H 1 95H 1 94H 1 93H 1 92H 1 91H 1 90H 1 90H FFH
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TCON TMOD TL0 TL1 TH0 TH1 RESERVED RESERVED
BITS
8FH 0 8EH 0 8DH 0 8CH 0 8BH 0 8AH 0 89H 0 88H 0 88H 00H 89H 00H 8AH 00H 8BH 00H 8CH 00H 8DH 00H
04741-073
SFR NOTE:
SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT ADDRESSABLE.
Figure 7. Complete SFR Map for the ADuC845, ADuC847, and ADuC848
FUNCTIONAL DESCRIPTION
8051 INSTRUCTION SET
Table 4. Optimized Single-Cycle 8051 Instruction Set
Mnemonic Description Bytes Cycles 1
Arithmetic
A A,Rn Add register to A 1 1
ADD A,@Ri Add indirect memory to A 1 2
ADD A,dir Add direct byte to A 2 2
ADD A,#data Add immediate to A 2 2
ADDC A,Rn Add register to A with carry 1 1
ADDC A,@Ri Add indirect memory to A with carry 1 2
ADDC A,dir Add direct byte to A with carry 2 2
ADD A,#data Add immediate to A with carry 2 2
SUBB A,Rn Subtract register from A with borrow 1 1
SUBB A,@Ri Subtract indirect memory from A with borrow 1 2
SUBB A,dir Subtract direct from A with borrow 2 2
SUBB A,#data Subtract immediate from A with borrow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC @Ri Increment indirect memory 1 2
INC dir Increment direct byte 2 2
INC DPTR Increment data pointer 1 3
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC @Ri Decrement indirect memory 1 2
DEC dir Decrement direct byte 2 2
MUL AB Multiply A by B 1 4
DIV AB Divide A by B 1 9
DA A Decimal adjust A 1 2
Logic
ANL A,Rn AND register to A 1 1
ANL A,@Ri AND indirect memory to A 1 2
ANL A,dir AND direct byte to A 2 2
ANL A,#data AND immediate to A 2 2
ANL dir,A AND A to direct byte 2 2
ANL dir,#data AND immediate data to direct byte 3 3
ORL A,Rn OR register to A 1 1
ORL A,@Ri OR indirect memory to A 1 2
ORL A,dir OR direct byte to A 2 2
ORL A,#data OR immediate to A 2 2
ORL dir,A OR A to direct byte 2 2
ORL dir,#data OR immediate data to direct byte 3 3
XRL A,Rn Exclusive-OR register to A 1 1
XRL A,@Ri Exclusive-OR indirect memory to A 2 2
XRL A,#data Exclusive-OR immediate to A 2 2
XRL dir,A Exclusive-OR A to direct byte 2 2
XRL A,dir Exclusive-OR indirect memory to A 2 2
XRL dir,#data Exclusive-OR immediate data to direct 3 3
CLR A Clear A 1 1
CPL A Complement A 1 1
SWAP A Swap nibbles of A 1 1
RL A Rotate A left 1 1
BANKS BIT-ADDRESSABLE
The 11-bit stack pointer is visible in the SPH and SP SFRs. The
SELECTED (BIT ADDRESSES) SP SFR is located at 81H as with a standard 8052. The SPH SFR
VIA
BITS IN PSW 20H is located at B7H. The 3 LSBs of the SPH SFR contain the 3
1FH extra bits necessary to extend the 8-bit stack pointer in the SP
11
18H SFR into an 11-bit stack pointer.
17H
10 07FFH
10H FOUR BANKS OF EIGHT
0FH REGISTERS
R0 TO R7
01
08H
07H RESET VALUE OF UPPER 1792
BYTES OF
04741-008
00 STACK POINTER
ON-CHIP XRAM
00H (DATA + STACK
FOR EXSP = 1,
DATA ONLY
Figure 8. Lower 128 Bytes of Internal Data Memory FOR EXSP = 0)
Internal XRAM
CFG845/7/8.7 = 0 CFG845/7/8.7 = 1
The ADuC845, ADuC847, and ADuC848 contain 2 kbytes of
on-chip extended data memory. This memory, although on- 100H
chip, is accessed via the MOVX instruction. The 2 kbytes of FFH
256 BYTES OF LOWER 256
internal XRAM are mapped into the bottom 2 kbytes of the ON-CHIP DATA BYTES OF
RAM
external address space if the CFG84x.0 (Table 7) bit is set; ON-CHIP XRAM
04741-010
(DATA + (DATA ONLY)
STACK)
otherwise, access to the external data memory occurs just like a 00H 00H
standard 8051.
Figure 10. Extended Stack Pointer Operation
Even with the CFG84x.0 bit set, access to the external (off chip), External Data Memory (External XRAM)
XRAM occurs once the 24-bit DPTR is greater than 0007FFH. There is no support for external program memory access to the
FFFFFFH FFFFFFH
parts. However, just like a standard 8051-compatible core, the
ADuC845/ADuC847/ADuC848 can access external data
memory using a MOVX instruction. The MOVX instruction
automatically outputs the various control strobes required to
EXTERNAL EXTERNAL
access the data memory. The parts, however, can access up to
DATA
MEMORY
DATA
MEMORY
16 Mbytes of external data memory. This is an enhancement of
SPACE SPACE the 64 kbytes of external data memory space available on a
(24-BIT (24-BIT
ADDRESS ADDRESS standard 8051-compatible core. See the Hardware Design
SPACE) SPACE)
Considerations section for details.
000000H 000000H
04741-013
ANALOG S-∆ S-∆ ∆IGITAL
MUX BUF PGA MO∆
XOR SINC3 FILTER 3 × (8 × SF)
INPUT 2 OUTPUT
AIN + VOS
AIN – VOS
Figure 12. Block Diagram of the ADC Input Channel with Chop Enabled
SYNCHRONOUS CHANGE
(I.E. CHANNEL CHANGE)
NO/INVALID
OUTPUT SAMPLE 3 + SAMPLE 4
2
SAMPLE 1 + SAMPLE 2
2
NO OUTPUT
VALID OUTPUT
SAMPLE 2 + SAMPLE 3 SAMPLE 4 + SAMPLE 5
2 2
04741-012
VALID OUTPUT
ASYNCHRONOUS CHANGE
(I.E. DISCONTINUOUS INPUT CHANGE)
NO OUTPUT
SAMPLE 3 + SAMPLE 4
2
SAMPLE 1 + SAMPLE 2
2
UNSETTLED OUTPUT
VALID OUTPUT
SAMPLE 2 + SAMPLE 3 SAMPLE 4 + SAMPLE 5
2 2
VALID OUTPUT
Table 10. ADuC845 and ADuC847 Typical Output RMS Noise (µV) vs. Input Range and Update Rate with Chop Enabled
Input Range
SF Word Data Update Rate (Hz) ±20 mV ±40 mV ±80 mV ±160 mV ±320 mV ±640 mV ±1.28 V ±2.56 V
13 105.03 1.75 1.30 1.65 1.5 2.1 3.1 7.15 13.3
23 59.36 1.25 0.95 1.08 0.94 1.0 1.87 3.24 7.1
27 50.56 1.0 1.0 0.85 0.85 1.13 1.56 2.9 3.6
69 19.79 0.63 0.68 0.52 0.7 0.61 1.1 1.3 2.75
255 5.35 0.31 0.38 0.34 0.32 0.4 0.45 0.68 1.22
Table 11. ADuC845 and ADuC847 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Enabled
Input Range
SF Word Data Update Rate (Hz) ±20 mV ±40 mV ±80 mV ±160 mV ±320 mV ±640 mV ±1.28 V ±2.56 V
13 105.03 12 13 14 15 15.5 16 16 16
23 59.36 12 13.5 14.5 15.5 16.5 16.5 17 16.5
27 50.56 12.5 13.5 15 16 16.5 17 17 17.5
69 19.79 13 14 15.5 16 17.5 17.5 18 18
255 5.35 14.5 15 16 17 18 18.5 19 19.5
Table 12. ADuC848 Typical Output Noise (µV) vs. Input Range and Update Rate with Chop Enabled
Input Range
SF Word Data Update Rate (Hz) ±20 mV ±40 mV ±80 mV ±160 mV ±320 mV ±640 mV ±1.28 V ±2.56 V
13 105.03 1.75 1.30 1.65 1.5 2.1 3.1 7.15 13.3
23 59.36 1.25 0.95 1.08 0.94 1.0 1.87 3.24 7.1
27 50.56 1.0 1.0 0.85 0.85 1.13 1.56 2.9 3.6
69 19.79 0.63 0.68 0.52 0.7 0.61 1.1 1.3 2.75
255 5.35 0.31 0.38 0.34 0.32 0.4 0.45 0.68 1.22
Table 13. ADuC848 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Enabled
Input Range
SF Word Data Update Rate (Hz) ±20 mV ±40 mV ±80 mV ±160 mV ±320 mV ±640 mV ±1.28 V ±2.56 V
13 105.03 12 13 14 15 15.5 16 16 16
23 59.36 12 13.5 14.5 15.5 16 16 17 16
27 50.56 12.5 13.5 15 16 16 16 16 16
69 19.79 13 14 15.5 16 16 16 16 16
255 5.35 14.5 15 16 16 16 16 16 16
Figure 15. Block Diagram of ADC Input Channel with Chop Disabled
Table 14. ADuC845 and ADuC847 Typical Output RMS Noise (µV) vs. Input Range and Update Rate with Chop Disabled
Table 15. ADuC845 and ADuC847 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Disabled
Table 16. ADuC848 Typical Output RMS Noise (µV) vs. Input Range and Update Rate with Chop Disabled
Table 17. ADuC848 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Disabled
Data Update Input Range
SF Word Rate (Hz) ±20 mV ±40 mV ±80 mV ±160 mV ±320mV ±640mV ±1.28 V ±2.56 V
3 1365.33 7.5 9 9 9 9 9 9 9
13 315.08 11.5 12.5 13.5 14 13.5 14 14 14
68 59.36 13 14 14.5 15.5 16 16 16 16
82 49.95 13 14 15 16 16 16 16 16
255 16.06 13.5 14.5 15.5 16 16 16 16 16
04741-016
REFIN± pins. This feature arose in connection with strain-gage DAC
An additional feature of the Sinc3 filter is a second notch filter Figure 22, Figure 23, Figure 24, and Figure 25 show the frequency
positioned in the frequency response at 60 Hz. This gives response of the ADC, yielding an overall output rate of 16.6 Hz
simultaneous 60 Hz rejection to whatever notch is defined by with chop enabled and 50 Hz with chop disabled. Also detailed
the SF filter. This 60 Hz filter is enabled via the REJ60 bit in the in these plots is the effect of the fixed 60 Hz drop-in notch filter
ADCMODE register (ADCMODE.6). The notch is valid only (REJ60 bit, ADCMODE.6). This fixed filter can be enabled or
for SF words ≥ 68; otherwise, ADC errors occur, and, the notch disabled by setting or clearing the REJ60 bit in the ADCMODE
is best used with an SF word of 82d giving simultaneous 50 Hz register (ADCMODE.6). This 60 Hz drop-in notch filter can be
and 60 Hz rejection. This function is useful only with an ADC
ADuC845/ADuC847/ADuC848
ADuC845/ADuC847/ADuC848
CSP PACKAGE
INPUT 4
AIN5 AIN5
0 mV to 640 mV, 0 V to 1.28 V and 0 V to 2.56 V, while in FULLY DIFFERENTIAL
INPUT 5
AIN6 AIN6
bipolar mode the ranges are ±20 mV, ±40 mV, ±80 mV, ±160 mV,
INPUT 6
AIN7 AIN7
±320 mV, ±64 0 mV, ±1.28 V, and ±2.56 V. These ranges should FULLY DIFFERENTIAL
INPUT 7
AIN8 AIN8
AIN9 AIN9
INPUT 10
FULLY DIFFERENTIAL
matching specification of 2 µV (typical with chop enabled)
INPUT 9
AIN10 AIN10
04741-017
means that calibration need only be carried out on a single AINCOM AINCOM
range and need not be repeated when the ADC range is
changed. This is a significant advantage compared to similar Figure 17. Unipolar and Bipolar Channel Pairs
with the same definitions as used for the primary ADC above.
where:
–10 –10
–20 –20
–30 –30
–40 –40
GAIN (dB)
GAIN (dB)
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
–110 –110
04741-018
04741-021
–120 –120
0 10 20 30 40 50 60 70 80 90 100 110 10 30 50 70 90 110 130 150 170 190 210 230 250
FREQUENCY (Hz) SF (Decimal)
Figure 18. Filter Response, Chop On, SF = 69 Decimal Figure 21. 60 Hz Normal Mode Rejection vs. SF, Chop On
10
–10
–10
–30
–30
–50
AMPLITUDE (dB)
AMPLITUDE (dB)
–50
–70
–70
–90
–90
–110
–110
–130
–130
04741-019
–150
0 10 20 30 40 50 60 70 80 90 100 –150
04741-022
0.1
10.1
20.1
30.1
40.1
50.1
60.1
70.1
80.1
90.1
100.1
110.1
120.1
130.1
140.1
150.1
160.1
170.1
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. Filter Response, Chop On, SF = 255 Decimal Figure 22. Chop Off, Fadc = 50 Hz, SF = 52H
0 10
–10
–10
–20
–30 –30
–40
AMPLITUDE (dB)
–50
GAIN (dB)
–50
–60 –70
–70
–190
–80
–90 –110
–100
–130
–110
04741-020
–120 –150
04741-023
SF (Decimal)
FREQUENCY (Hz)
Figure 20. 50 Hz Normal Mode Rejection vs. SF Word, Chop On Figure 23. Chop Off, SF = 52H, REJ60 Enabled
–20 –20
–40 –40
AMPLITUDE (dB)
AMPLITUDE (dB)
–60 –60
–80 –80
–100 –100
–120 –120
04741-024
04741-025
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 24. Chop On, Fadc = 16.6 Hz, SF = 52H Figure 25. Chop On, Fadc = 16.6 Hz, SF = 52H, REJ60 Enabled
FUNCTIONAL DESCRIPTION
ADC SFR INTERFACE
The ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the following
sections.
Table 22. ADC SFR Interface
Name Description
ADCSTAT ADC Status Register. Holds the general status of the primary and auxiliary (ADuC845 only) ADCs.
ADCMODE ADC Mode Register. Controls the general modes of operation for primary and auxiliary (ADuC845 only) ADCs.
ADC0CON1 Primary ADC Control Register 1. Controls the specific configuration of the primary ADC.
ADC0CON2 Primary ADC Control Register 2. Controls the specific configuration of the primary ADC.
ADC1CON Auxiliary ADC Control Register. Controls the specific configuration of the auxiliary ADC. ADuC845 only.
SF Sinc Filter Register. Configures the decimation factor for the Sinc3 filter and, therefore, the primary and auxiliary (ADuC845
only) ADC update rates.
ICON Current Source Control Register. Allows user control of the various on-chip current source options.
ADC0L/M/H Primary ADC 24-bit (16-bit on the ADuC848) conversion result is held in these three 8-bit registers. ADC0L is not available on
the ADuC848.
ADC1L/M/H Auxiliary ADC 24-bit conversion result is held in these two 8-bit registers. ADuC845 only.
OF0L/M/H Primary ADC 24-bit offset calibration coefficient is held in these three 8-bit registers. OF0L is not available on the ADuC848.
OF1L/H Auxiliary ADC 16-bit offset calibration coefficient is held in these two 8-bit registers. ADuC845 only.
GN0L/M/H Primary ADC 24-bit gain calibration coefficient is held in these three 8-bit registers. GN0L is not available on the ADuC848.
GN1L/H Auxiliary ADC 16-bit gain calibration coefficient is held in these two 8-bit registers. ADuC845 only.
• Any change to the MD bits immediately resets both ADCs • If the parts are powered down via the PD bit in the PCON
(auxiliary ADC only applicable to the ADuC845). A write register, the current ADCMODE bits are preserved, that is,
to the MD2–MD0 bits with no change in contents is also they are not reset to default state. Upon a subsequent
treated as a reset. (See the exception to this in the third resumption of normal operating mode, the ADCs restarts
note of this section.) the selected operation defined by the ADCMODE register.
• If ADC1CON1 and ADC1CON2 are written when • Once ADCMODE has been written with a calibration
ADC0EN = 1, or if ADC0EN is changed from 0 to 1, both mode, the RDY0/1 (ADuC845 only) bits (ADCSTAT) are
ADCs are also immediately reset. In other words, the reset and the calibration commences. On completion, the
primary ADC is given priority over the auxiliary ADC and appropriate calibration registers are written, the relevant
any change requested on the primary ADC is immediately bits in ADCSTAT are written, and the MD2–MD0 bits are
responded to. Only applicable to the ADuC845. reset to 000B to indicate that the ADC is back in power-
down mode.
• On the other hand, if ADC1CON is written to or if
ADC1EN is changed from 0 to 1, only the auxiliary ADC • Any calibration request of the auxiliary ADC while the
is reset. For example, if the primary ADC is continuously temperature sensor is selected fails to complete. Although
converting when the auxiliary ADC change or enable the RDY1 bit is set at the end of the calibration cycle, no
occurs, the primary ADC continues undisturbed. Rather update of the calibration SFRs takes place, and the ERR1
than allow the auxiliary ADC to operate with a phase bit is set. ADuC845 only.
difference from the primary ADC, the auxiliary ADC falls
into step with the outputs of the primary ADC. The result • Calibrations performed at maximum SF (see Table 28)
is that the first conversion time for the auxiliary ADC is value (slowest ADC throughput rate) help to ensure
delayed by up to three outputs while the auxiliary ADC optimum calibration.
update rate is synchronized to the primary ADC. Only
• The duration of a calibration cycle is 2/Fadc for chop-on
applicable to ADuC845. If the ADC1CON write occurs
mode and 4/Fadc for chop-off mode.
after the primary ADC has completed its operation, the
auxiliary ADC can respond immediately without having to
fall into step with the primary ADCs output cycle.
Note that because the reference-detect does not operate on the REFIN2± pair, the REFIN2± pins can go below 1 V.
1
Note the following about the temperature sensor:
When the temperature sensor is selected, user code must select the internal reference via the AXREF bit and clear the AUNI bit (ADC1CON.5) to select bipolar coding.
Chop mode must be enabled for correct temperature sensor operation.
The temperature sensor is factory calibrated to yield conversion results 800000H at 0°C (ADC chop on).
A +1°C change in temperature results in a +1 LSB change in the ADC1H register ADC conversion result.
The temperature sensor is not available on the ADuC847 or ADuC848.
The bits in this register set the decimation factor of the ADC. This has a direct bearing on the throughput rate of the ADC along with the
chop setting. The equations used to determine the ADC throughput rate are
1
Fadc (Chop On) = × 32.768 kHz
3 × 8 × SFword
1
Fadc (Chop Off) = × 32.768 kHz
8 × SFword
During ADC calibration, the user-programmed value of SF word is used. The SF word does not default to the maximum setting (255) as it
did on previous MicroConverter® products. However, for optimum calibration results, it is recommended that the maximum SF word be set.
A write to the ICON register has an immediate effect but does not reset the ADCs. Therefore, if a current source is changed while an ADC
is already converting, the user must wait until the third or fourth output at least (depending on the status of the chop mode) to see a fully
settled new output.
Both IEXC1 and IEXC2 can be configured to operate on the same output pin thereby increasing the current source capability to 400 µA.
FLASH/EE MEMORY
TECHNOLOGY endurance and Flash/EE memory data retention.
Figure 26. Flash/EE Memory Development Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
Overall, Flash/EE memory represents a step closer to the ideal
terms, a single endurance cycle is composed of four independent,
memory device that includes nonvolatility, in-circuit program-
sequential events:
mability, high density, and low cost. The Flash/EE memory
technology allows the user to update program code space in- 1. Initial page erase sequence
circuit, without needing to replace onetime programmable
(OTP) devices at remote operating nodes. 2. Read/verify sequence
Flash/EE Memory on the ADuC845, ADuC847, ADuC848 3. Byte program sequence
The ADuC845/ADuC847/ADuC848 provide two arrays of
4. Second read/verify sequence
Flash/EE memory for user applications—up to 62 kbytes of
Flash/EE program space and 4 kbytes of Flash/EE data memory In reliability qualification, every byte in both the program and
space. Also, 8-kbyte and 32-kbyte program memory options are data Flash/EE memory is cycled from 00H to FFH until a first
available. All examples and references in this datasheet use the fail is recorded, signifying the endurance limit of the on-chip
62-kbyte option; however, similar protocols and procedures are Flash/EE memory.
applicable to the 32-kbyte and 8-kbyte options unless otherwise
noted, provided that the difference in memory size is taken into As indicated in the Specifications table, the ADuC845/ADuC847/
account. ADuC848 Flash/EE memory endurance qualification has been
carried out in accordance with JEDEC Specification A117 over
The 62 kbytes Flash/EE code space are provided on-chip to the industrial temperature range of –40°C, +25°C, +85°C, and
facilitate code execution without any external discrete ROM +125°C. (The LFCSP package is qualified to +85°C only.) The
device requirements. The program memory can be programmed results allow the specification of a minimum endurance figure
in-circuit, using the serial download mode provided, using over supply and temperature of 100,000 cycles, with an endurance
conventional third party memory programmers, or via any figure of 700,000 cycles being typical of operation at 25°C.
user-defined protocol in user download (ULOAD) mode.
Retention is the ability of the Flash/EE memory to retain its
The 4-kbyte Flash/EE data memory space can be used as a programmed data over time. Again, the parts have been qualified
general-purpose, nonvolatile scratchpad area. User access to in accordance with the formal JEDEC Retention Lifetime Specifi-
this area is via a group of seven SFRs. This space can be cation (A117) at a specific junction temperature (TJ = 55°C). As
programmed at a byte level, although it must first be erased in part of this qualification procedure, the Flash/EE memory is
4-byte pages. cycled to its specified endurance limit described previously,
before data retention is characterized. This means that the
Flash/EE memory is guaranteed to retain its data for its full
specified retention lifetime every time the Flash/EE memory is
reprogrammed. It should also be noted that retention lifetime,
based on an activation energy of 0.6 eV, derates with TJ as shown
in Figure 27.
200
ADI SPECIFICATION low through an external 1 kΩ resistor. Once in serial download
100 YEARS MIN.
150
AT TJ = 55C mode, the hidden embedded download kernel executes. This
allows the user to download code to the full 62 kbytes of Flash/EE
100 program memory while the device is in circuit in its target
application hardware.
50
A PC serial download executable (WSD.EXE) is provided as
04741-028
0 part of the ADuC845/ADuC847/ADuC848 Quick Start
40 50 60 70 80 90 100 110
TJ JUNCTION TEMPERATURE (C) development system. Application Note uC004 fully describes
the serial download protocol that is used by the embedded
Figure 27. Flash/EE Memory Data Retention download kernel. This application note is available at
FLASH/EE PROGRAM MEMORY www.analog.com/microconverter.
04741-030
ENABLE P1.0 RESET VDD
block is used to store the user code as shown in Figure 28.
EMBEDDED DOWNLOAD/DEBUG KERNEL
PERMANENTLY EMBEDDED FIRMWARE ALLOWS
Figure 29. Flash/EE Memory Parallel Programming
CODE TO BE DOWNLOADED TO ANY OF THE FFFFH
62 kBYTES OF ON-CHIP PROGRAM MEMORY. 2kBYTE The command words that are assigned to P1.1, P1.2, P1.3, and
THE KERNEL PROGRAM APPEARS AS NOP F800H
INSTRUCTIONS TO USER CODE. P1.4 are described in Table 31.
Table 31. Flash/EE Memory Parallel Programming Modes
Port 1 Pins
USER PROGRAM MEMORY
62 kBYTES OF FLASH/EE PROGRAM MEMORY
F7FFH
P1.4 P1.3 P1.2 P1.1 Programming Mode
ARE AVAILABLE TO THE USER. ALL OF THIS
SPACE CAN BE PROGRAMMED FROM THE
62kBYTE 0 0 0 0 Erase Flash/EE Program, Data, and
0000H
PERMANENTLY EMBEDDED DOWNLOAD/DEBUG Security Mode
KERNEL OR IN PARALLEL PROGRAMMING MODE.
1 0 1 0 Program Code Byte
0 0 1 0 Program Data Byte
04741-029
04741-074
EITHER THE DOWNLOAD/DEBUG 0000H
KERNEL OR USER CODE (IN ULOAD
MODE) CAN PROGRAM THIS SPACE
Alternatively, ULOAD mode can be used to save data to the
56 kbytes of Flash/EE memory. This can be extremely useful in Figure 31. Flash/EE Program Memory Map in ULOAD Mode (32-kbyte Part)
data logging applications where the parts can provide up to ULOAD mode is not available on the 8-kbyte Flash/EE program
60 kbytes of data memory on-chip (4 kbytes of dedicated memory parts.
Flash/EE data memory also exist).
Flash/EE Program Memory Security
The upper 6 kbytes of the 62 kbytes of Flash/EE program The ADuC845/ADuC847/ADuC848 facilitate three modes of
memory (8 kbytes on the 32-kbyte parts) are programmable Flash/EE program memory security: the lock, secure, and serial
only via serial download or parallel programming. This means safe modes. These modes can be independently activated,
that this space appears as read-only to user code; therefore, it restricting access to the internal code space. They can be
cannot be accidentally erased or reprogrammed by erroneous enabled as part of serial download protocol, as described in
code execution, making it very suitable to use the 6 kbytes as a Application Note uC004, or via parallel programming.
bootloader. A bootload enable option exists in the Windows®
Lock Mode
serial downloader (WSD) to “Always RUN from E000H after
Reset.” If using a bootloader, this option is recommended to This mode locks the code memory, disabling parallel program-
ensure that the bootloader always executes correct code after ming of the program memory. However, reading the memory in
reset. parallel mode and reading the memory via a MOVC command
from external memory are still allowed. This mode is deactivated
Programming the Flash/EE program memory via ULOAD by initiating an ERASE CODE AND DATA command in serial
mode is described in the Flash/EE Memory Control SFR download or parallel programming modes.
section of ECON and also in Application Note uC007
Secure Mode
(www.analog.com/microconverter).
This mode locks the code memory, disabling parallel program-
EMBEDDED DOWNLOAD/DEBUG KERNEL
ming of the program memory. Reading/verifying the memory
PERMANENTLY EMBEDDED FIRMWARE ALLOWS
CODE TO BE DOWNLOADED TO ANY OF THE FFFFH in parallel mode and reading the internal memory via a MOVC
62 kBYTES OF ON-CHIP PROGRAM MEMORY. 2kBYTE
THE KERNEL PROGRAM APPEARS AS NOP F800H command from external memory are also disabled. This mode
INSTRUCTIONS TO USER CODE.
F7FFH is deactivated by initiating an ERASE CODE AND DATA
6kBYTE
USER BOOTLOADER SPACE
E000H
command in serial download or parallel programming modes.
THE USER BOOTLOADER
SPACE CAN BE PROGRAMMED IN Serial Safe Mode
DOWNLOAD/DEBUG MODE VIA THE
62 kBYTES
KERNEL BUT IS READ ONLY WHEN This mode disables serial download capability on the device. If
EXECUTING USER CODE
OF USER
CODE
dFFFH serial safe mode is activated and an attempt is made to reset the
USER DOWNLOADER SPACE 56kBYTE
MEMORY
EITHER THE DOWNLOAD/DEBUG 0000H part into serial download mode, that is, RESET asserted (pulled
KERNEL OR USER CODE (IN high) and de-asserted (pulled low) with PSEN low, the part
ULOAD MODE) CAN PROGRAM
04741-031
THIS SPACE interprets the serial download reset as a normal reset only. It
therefore does not enter serial download mode, but executes only
a normal reset sequence. Serial safe mode can be disabled only
Figure 30. Flash/EE Program Memory Map in ULOAD Mode (62-kbyte Part)
by initiating an ERASE CODE AND DATA command in
parallel programming mode.
PAGE ADDRESS
ADuC848 peripherals, the interface to this memory space is via
(EADRH/L)
a group of registers mapped in the SFR space. A group of four
BYTE 1 BYTE 2 BYTE 3 BYTE 4
data registers (EDATA1–4) holds the 4 bytes of data at each 03H (000CH) (000DH) (000EH) (000FH)
page. The page is addressed via the EADRH and EADRL 02H BYTE 1
(0008H)
BYTE 2 BYTE 3 BYTE 4
(0009H) (000AH) (000BH)
registers. Finally, ECON is an 8-bit control register that can be 01H BYTE 1 BYTE 2 BYTE 3 BYTE 4
(0004H) (0006H) (0007H)
written to with one of nine Flash/EE memory access commands 00H
(0005H)
BYTE 1 BYTE 2 BYTE 3 BYTE 4
to trigger various read, write, erase, and verify functions. A (0000H) (0001H) (0002H) (0003H)
block diagram of the SFR interface to the Flash/EE data memory
EDATA1 SFR
EDATA2 SFR
EDATA3 SFR
EDATA4 SFR
BYTE
array is shown in Figure 32. ADDRESSES
ARE GIVEN IN
04741-032
ECON—Flash/EE Memory Control SFR BRACKETS
VDD–50mV
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional equivalent VDD–100mV
AVDD
VREF
R
OUTPUT
BUFFER
R 100mV
14 50mV
04741-034
R
0mV
000H FFFH
HIGH-Z
DISABLE
(FROM MCU) Figure 34. Endpoint Nonlinearities Due to Amplifier Saturation
R
The endpoint nonlinearities shown in Figure 34 become worse
R
as a function of output loading. Most data sheet specifications
assume a 10 kΩ resistive load to ground at the DAC output. As
04741-033
mode.
3
Linearity degradation near ground and VDD is caused by satura-
tion of the output amplifier; a general representation of its effects
(neglecting offset and gain error) is shown in Figure 34. The 2
dotted line indicates the ideal transfer function, and the solid
line represents what the transfer function might look like with 1
endpoint nonlinearities due to saturation of the output amplifier. DAC LOADED WITH 0000H
0 5 10 15
mode only. In 0 V-to-VREF mode (with VREF < VDD), the lower SOURCE/SINK CURRENT (mA)
nonlinearity would be similar, but the upper portion of the Figure 35. Source and Sink Current Capability with VREF = AVDD = 5 V
transfer function would follow the ideal line to the end,
showing no signs of the high-end endpoint linearity error.
2
Two of these modes allow the PWM to be configured as a Σ-Δ
DAC with up to 16 bits of resolution. A block diagram of the
PWM is shown in Figure 38.
1 12.583MHz (FVCO)
EXTERNAL CLOCK ON P2.7 CLOCK PROGRAMMABLE
32.768kHz (FXTAL) SELECT DIVIDER
DAC LOADED WITH 0000H
32.768kHz/15
04741-036
0
0 5 10 15 16-BIT PWM COUNTER
SOURCE/SINK CURRENT (mA)
Figure 36. Source and Sink Current Capability with VREF = AVDD = 3 V
For larger loads, the current drive capability may not be suffi- COMPARE
P2.5
P2.6
cient. To increase the source and sink current capability of the
DAC, an external buffer should be added as shown in Figure 37.
04741-038
MODE PWM0H/L PWM1H/L
ADuC845/ The PWM uses control SFR, PWMCON, and four data SFRs:
ADuC847/ DAC 14 PWM0H, PWM0L, PWM1H, and PWM1L.
ADuC848
PWMCON (as described in Table 34) controls the different
04741-037
PWM1H
0
0
04741-039
P2.5
P2.5
04741-040
P2.6
PWM1H/L 80µs
16-BIT 16-BIT
PWM0H/L
12.583MHz LATCH
0
P2.6 0 0 1 0 0
CARRY OUT AT P2.6
04741-042
80µs
PWM1H/L = 4000H
PWM0H
0
318µs
P2.5 16-BIT 16-BIT
04741-043
P2.6 3.146MHz LATCH
04741-044
Σ-Δ DAC output. Mode 4 provides non-return-to-zero Σ-Δ PWM1H/L = 4000H
DAC outputs. RZ mode ensures that any difference in the rise
and fall times does not affect the Σ-Δ DAC INL. However, RZ Figure 44. PWM Mode 6
mode halves the dynamic range of the Σ-Δ DAC outputs from
0 V− to AVDD down to 0 V to AVDD/2. For best results, this Mode 7
mode should be used with a PWM clock divider of 4.
In Mode 7, the PWM is disabled, allowing P2.5 and P2.6 to be
If PWM1H is set to 4010H (slightly above one-quarter of FS), used as normal.
typically P2.6 is low for three full clocks (3 × 80 ns), high for
one-half a clock (40 ns), and then low again for one-half a clock
(40 ns) before repeating itself. Over every 65536 clocks, the
PWM compromises for the fact that the output should be
slightly above one-quarter of full scale by leaving the output
high for two half clocks in four every so often.
The main features of the MicroConverter I2C interface are Software Master Mode
The ADuC845/ADuC847/ADuC848 can be used as an I2C
• Only two bus lines are required: a serial data line (SDATA) master device by configuring the I2C peripheral in master mode
and a serial clock line (SCLOCK). and writing software to output the data bit-by-bit. This is
referred to as a software master. Master mode is enabled by
• An I2C master can communicate with multiple slave
setting the I2CM bit in the I2CCON register.
devices. Because each slave device has a unique 7-bit
address, single master/slave relationships can exist at all To transmit data on the SDATA line, MDE must be set to enable
times even in a multislave environment. the output driver on the SDATA pin. If MDE is set, the SDATA
pin is pulled high or low depending on whether the MDO bit is
• The ability to respond to two separate addresses when set or cleared. MCO controls the SCLOCK pin and is always
operating in slave mode. configured as an output in master mode. In master mode, the
• On-chip filtering rejects <50 ns spikes on the SDATA and SCLOCK pin is pulled high or low depending on the whether
the SCLOCK lines to preserve data integrity. MCO is set or cleared.
SLAVE 2
last rising edge of SCLOCK.
Figure 45. Typical I2C System Software must control MDO, MCO, and MDE appropriately to
generate the start condition, slave address, acknowledge bits,
data bytes, and stop conditions. These functions are described
in Application Note uC001.
The user can choose to poll the I2CI bit or to enable the
interrupt. In the case of the interrupt, the PC counter vectors to
003BH at the end of each complete byte. For the first byte, when
the user gets to the I2CI ISR, the 7-bit address and the R/W bit
appear in the I2CDAT SFR.
Note that both SPI and I2C use the same ISR (Vector Address 3BH); therefore, when using SPI and I2C simultaneously, it is necessary to
check the interfaces following an interrupt to determine which one caused the interrupt.
ISPI FLAG the transmitted byte is completely transmitted, and the input
byte is waiting in the input shift register. The ISPI flag is set
Figure 46. SPI Timing, All Modes automatically, and an interrupt occurs, if enabled. The value in
the shift register is latched into SPIDAT only when the trans-
mission/reception of a byte has been completed. The end of
transmission occurs after the eighth clock has been received if
CPHA = 1, or when SS returns high if CPHA = 0.
The parts incorporate two data pointers. The second data SFR Address: A7H
pointer is a shadow data pointer and is selected via the data Power-On Default: 00H
pointer control SFR (DPCON). DPCON features automatic Bit Addressable: No
hardware post-increment and post-decrement as well as an
automatic data pointer toggle.
Table 42. DPCON SFR Bit Designations
Bit No. Name Description
7 ---- Not Implemented. Write Don’t Care.
6 DPT Data Pointer Automatic Toggle Enable.
Cleared by the user to disable autoswapping of the DPTR.
Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction.
5, 4 DP1m1, DP1m0 Shadow Data Pointer Mode. These bits enable extra modes of the shadow data pointer operation, allowing
more compact and more efficient code size and execution.
DP1m1 DP1m0 Behavior of the Shadow Data Pointer
0 0 8052 behavior.
0 1 DPTR is post-incremented after a MOVX or a MOVC instruction.
1 0 DPTR is post-decremented after a MOVX or MOVC instruction.
1 1 DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction can be useful for
moving 8-bit blocks to/from 16-bit devices.)
3, 2 DP0m1, DP0m0 Main Data Pointer Mode. These bits enable extra modes of the main data pointer operation, allowing more
compact and more efficient code size and execution.
DP0m1 DP0m0 Behavior of the Main Data Pointer
0 0 8052 behavior.
0 1 DPTR is post-incremented after a MOVX or a MOVC instruction.
1 0 DPTR is post-decremented after a MOVX or MOVC instruction.
1 1 DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction is useful for
moving 8-bit blocks to/from 16-bit devices.)
1 ---- Not Implemented. Write Don’t Care.
0 DPSEL Data Pointer Select.
Cleared by the user to select the main data pointer. This means that the contents of this 24-bit register are
placed into the DPL, DPH, and DPP SFRs.
Set by the user to select the shadow data pointer. This means that the contents of a separate 24-bit register
appear in the DPL, DPH, and DPP SFRs.
Note the following:
• The Dual Data Pointer section is the only place in which MOV DPTR,#0 ;Main DPTR = 0
main and shadow data pointers are distinguished. MOV DPCON,#55H ;Select shadow DPTR
Whenever the DPTR is mentioned elsewhere in this data ;DPTR1 increment mode
sheet, active DPTR is implied. ;DPTR0 increment mode
;DPTR auto toggling ON
• Only the MOVC/MOVX @DPTR instructions MOV DPTR,#0D000H ;DPTR = D000H
automatically post-increment and post-decrement the MOVELOOP: CLR A
DPTR. Other MOVC/MOVX instructions, such as MOVC MOVC A,@A+DPTR ;Get data
PC or MOVC @Ri, do not cause the DPTR to automatically ;Post Inc DPTR
post-increment and post-decrement. ;Swap to Main DPTR(Data)
MOVX @DPTR,A ;Put ACC in XRAM
To illustrate the operation of DPCON, the following code copies
;Increment main DPTR
256 bytes of code memory at Address D000H into XRAM,
;Swap Shadow DPTR(Code)
starting from Address 0000H.
MOV A, DPL
JNZ MOVELOOP
Six SFRs are associated with the time interval counter, INTERVAL
TIMEBASE TIEN
TIMECON being its control register. Depending on the SECOND COUNTER
SELECTION
MUX
SEC
configuration of the IT0 and IT1 bits in TIMECON, the selected
time counter register overflow clocks the interval counter. When
this counter is equal to the time interval value loaded in the MINUTE COUNTER
MIN
INTVAL SFR, the TII bit (TIMECON.2) is set and generates an
interrupt, if enabled. If the part is in power-down mode, again HOUR COUNTER
with TIC interrupt enabled, the TII bit wakes up the device and HOUR
8-BIT
resumes code execution by vectoring directly to the TIC INTERVAL COUNTER
can be written initially with the current time; the TIC can then
be controlled and accessed by user software. In effect, this
04741-047
INTVAL SFR
facilitates the implementation of a real-time clock. A basic block
diagram of the TIC is shown in Figure 47. Figure 47. TIC Simplified Block Diagram
To enable the TIC as a real-time clock, the HOUR, MIN, SEC, and HTHSEC registers can be loaded with the current time. Once the
TCEN bit is high, the TIC starts. To use the TIC as a time interval counter, select the count interval—hundredths of seconds, seconds,
minutes, and hours via the ITS0 and ITS1 bits in the TIMECON SFR. Load the count required into the INTVAL SFR.
Note that INTVAL is only an 8-bit register, so user software must take into account any intervals longer than are possible with 8 bits.
Therefore, to count an interval of 20 seconds, use the following procedure:
MOV TIMECON, #0D0H ;Enable 24Hour mode, count seconds, Clear TCEN.
MOV INTVAL, #14H ;Load INTVAL with required count interval...in this case 14H = 20
MOV TIMECON, #0D3H ;Start TIC counting and enable the 8bit INTVAL counter.
04741-068
P1.x
P0.x READ PIN
PIN TO ADC
PIN
INTERNAL
BUS D Q
WRITE
Figure 49. Port 1 Bit Latch and I/O Buffer
CL Q
TO LATCH
LATCH Port 2
04741-048
P3.x
Table 47. Port 2 Alternate Functions INTERNAL PIN
BUS D Q
Pin No. Alternate Function
WRITE
P2.0 SCLOCK for SPI TO LATCH CL Q
LATCH
P2.1 MOSI for SPI
P2.2 MISO for SPI READ
04741-071
P2.3 SS and T2 clock input PIN ALTERNATE
INPUT
P2.4 T2EX alternate control for T2 FUNCTION
READ
PIN ANL Logical AND, for example, ANL P1, A
ORL Logical OR, for example, ORL P2, A
Figure 50. Port 2 Bit Latch and I/O Buffer XRL Logical EX-OR, for example, XRL P3, A
Port 3 JBC Jump if Bit = 1 and clear bit, for example, JBC
Port 3 is a bidirectional port with internal pull-ups directly P1.1, LABEL
controlled via the P3 SFR (B0H). Port 3 pins that have 1s CPL Complement bit, for example, CPL P3.0
written to them are pulled high by the internal pull-ups and, in INC Increment, for example, INC P2
that state, can be used as inputs. As inputs, Port 3 pins pulled DEC Decrement, for example, DEC P2
externally low source current because of the internal pull-ups. DJNZ Decrement and jump if not zero, for example,
DJNZ P3, LABEL
Port 3 pins with 0s written to them drive a logic low output MOV PX.Y, C1 Move Carry to Bit Y of Port X
voltage (VOL) and are capable of sinking 4 mA. Port 3 pins also CLR PX.Y1 Clear Bit Y of Port X
have various secondary functions as described in Table 48. The SETB PX.Y1 Set Bit Y of Port X
___________________________________________
alternate functions of Port 3 pins can be activated only if the 1
These instructions read the port byte (all 8 bits), modify the addressed bit,
corresponding bit latch in the P3 SFR contains a 1. Otherwise, and write the new byte back to the latch.
the port pin remains at 0.
Table 48. Port 3 Alternate Functions Read-modify-write instructions are directed to the latch rather
Pin No. Alternate Function than to the pin to avoid a possible misinterpretation of the
P3.0 RxD (UART input pin, or serial data I/O in Mode 0)
voltage level of a pin. For example, a port pin might be used to
drive the base of a transistor. When 1 is written to the bit, the
P3.1 TxD (UART output pin, or serial clock output in Mode 0)
transistor is turned on. If the CPU reads the same port bit at the
P3.2 INT0 (External Interrupt 0)
pin rather than the latch, it reads the base voltage of the
P3.3 INT1 (External Interrupt 1)
transistor and interprets it as Logic 0. Reading the latch rather
P3.4 T0 (Timer/Counter 0 external input)
than the pin returns the correct value of 1.
P3.5 T1 (Timer/Counter 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)
1
These bits are not used to control Timer/Counters 0 and 1, but are used instead to control and monitor the external INT0 and INT1 interrupt pins.
C/T = 1
CORE P3.4/T0
CLK1
CONTROL
C/T = 0 TR0
INTERRUPT
TL0 TH0
(5 BITS) (8 BITS) TF0
RELOAD
C/T = 1 GATE TH0
P3.4/T0 (8 BITS)
P3.2/INT0
04741-051
CONTROL
TR0 NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION) Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
Figure 52. Timer/Counter 0, Mode 0
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
In this mode, the timer register is configured as a 13-bit register. separate counters. This configuration is shown in Figure 55.
As the count rolls over from all 1s to all 0s, it sets the timer TL0 uses the Timer 0 Control Bits C/T, Gate, TR0, INT0, and
overflow flag, TF0. TF0 can then be used to request an TF0. TH0 is locked into a timer function (counting machine
interrupt. The counted input is enabled to the timer when TR0 cycles) and takes over the use of TR1 and TF1 from Timer 1.
= 1 and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the Therefore, TH0 then controls the Timer 1 interrupt. Mode 3
timer to be controlled by external input INT0 to facilitate pulse- is provided for applications requiring an extra 8-bit timer or
width measurements. TR0 is a control bit in the special function counter.
register TCON; Gate is in TMOD. The 13-bit register consists of
When Timer 0 is in Mode 3, Timer 1 can be turned on and off
all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of
by switching it out of and into its own Mode 3, or it can still be
TL0 are indeterminate and should be ignored. Setting the run
used by the serial interface as a baud rate generator. In fact, it
flag (TR0) does not clear the registers.
can be used in any application not requiring an interrupt from
Mode 1 (16-Bit Timer/Counter) Timer 1 itself.
Mode 1 is the same as Mode 0 except that the Mode 1 timer CORE CORE
CLK1 CLK/12
register runs with all 16 bits. Mode 1 is shown in Figure 53.
C/T = 0
INTERRUPT
TL0
(8 BITS) TF0
CORE
CLK1 C/T = 1
C/T = 0 P3.4/T0
INTERRUPT CONTROL
TL0 TH0
(8 BITS) (8 BITS) TF0 TR0
C/T = 1
P3.4/T0 GATE
CONTROL P3.2/INT0
TR0
INTERRUPT
GATE CORE TH0
(8 BITS) TF1
CLK/12
P3.2/INT0
04741-050
TR1
NOTES
04741-052
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION) NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
T2 C/ T2 = 1
PIN CONTROL
TR2
RELOAD
TRANSITION
DETECTOR
RCAP2L RCAP2H
TF2
TIMER
INTERRUPT
T2EX EXF2
PIN
CONTROL
EXEN2
04741-053
*NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
CORE
CLK1 C/ T2 = 0
TL2 TH2
(8 BITS) (8 BITS) TF2
T2 C/ T2 = 1
PIN CONTROL
TR2
CAPTURE TIMER
INTERRUPT
TRANSITION
DETECTOR
RCAP2L RCAP2H
T2EX EXF2
PIN
CONTROL
EXEN2
04741-054
*NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
04741-055
TxD
(SHIFT CLOCK)
setting the SMOD bit in PCON, the frequency can be doubled
Figure 58. 8-Bit Shift Register Mode to Core_Clk/32. Eleven bits are transmitted or received: a start
bit (0), 8 data bits, a programmable 9th bit, and a stop bit (1).
Mode 1 (8-Bit UART, Variable Baud Rate) The 9th bit is most often used as a parity bit, although it can be
Mode 1 is selected by clearing SM0 and setting SM1. Each data used for anything, including a ninth data bit if required.
byte (LSB first) is preceded by a start bit (0) and followed by a
To transmit, the 8 data bits must be written into SBUF. The
stop bit (1). Therefore, 10 bits are transmitted on TxD or are
ninth bit must be written to TB8 in SCON. When transmission
received on RxD. The baud rate is set by the Timer 1 or Timer 2
is initiated, the 8 data bits (from SBUF) are loaded into the
overflow rate, or a combination of the two (one for transmission
transmit shift register (LSB first). The contents of TB8 are
and the other for reception).
loaded into the 9th bit position of the transmit shift register.
Transmission is initiated by writing to SBUF. The write to SBUF The transmission starts at the next valid baud rate clock. The
signal also loads a 1 (stop bit) into the 9th bit position of the TI flag is set as soon as the stop bit appears on TxD.
transmit shift register. The data is output bit-by-bit until the
Reception for Mode 2 is similar to that of Mode 1. The 8 data
stop bit appears on TxD and the transmit interrupt flag (TI) is
bytes are input at RxD (LSB first) and loaded onto the receive
automatically set as shown in Figure 59.
shift register. When all 8 bits have been clocked in, the
START STOP BIT following events occur:
BIT
D0 D1 D2 D3 D4 D5 D6 D7
TxD
The 8 bits in the receive shift register are latched into SBUF.
TI
(SCON.1)
The 9th data bit is latched into RB8 in SCON.
04741-056
SET INTERRUPT
I.E., READY FOR MORE DATA
The receiver interrupt flag (RI) is set.
Figure 59. 8-Bit Variable Baud Rate
All of the following conditions must be met at the time the final
Reception is initiated when a 1-to-0 transition is detected on shift pulse is generated:
RxD. Assuming that a valid start bit is detected, character
reception continues. The start bit is skipped and the 8 data bits RI = 0
are clocked into the serial port shift register. When all 8 bits
have been clocked in, the following events occur: Either SM2 = 0 or SM2 = 1
The 8 bits in the receive shift register are latched into SBUF. Received stop bit = 1
The 9th bit (stop bit) is clocked into RB8 in SCON. If any of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
The receiver interrupt flag (RI) is set.
Modes 1 and 3 Baud Rate Generation Timer 2 is selected as the baud rate generator by setting the
TCLK and/or RCLK in T2CON. The baud rates for transmit
The baud rates in Modes 1 and 3 are determined by the overflow
and receive can be simultaneously different. Setting RCLK
rate in Timer 1 or Timer 2, or in both (one for transmit and the
and/or TCLK puts Timer 2 into its baud rate generator mode as
other for receive).
shown in Figure 60.
Timer 1 Generated Baud Rates
In this case, the baud rate is given by the formula
When Timer 1 is used as the baud rate generator, the baud rates
Modes 1 and 3 Baud Rate =
in Modes 1 and 3 are determined by the Timer 1 overflow rate Core Clock Frequency
and the value of SMOD as follows:
(16 × [65536 − (RCAP 2 H : RCAP 2 L )])
2 SMOD
Modes 1 and 3 Baud Rate = × Timer 1 Overflow Rate
32
TIMER 1
OVERFLOW
0 1
SMOD
CORE CONTROL
CLK1 C/ T2 = 0 TIMER 2
TL2 TH2 OVERFLOW 1 0
(8 BITS) (8 BITS) RCLK
T2 C/ T2 = 1 RX
PIN 16
CLOCK
1 0
TR2 TCLK
RELOAD
16 TX
CLOCK
RCAP2L RCAP2H
CONTROL
TRANSITION
DETECTOR
EXEN2
04741-057
NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
1 0
÷ 2 DIV
For example, to get a baud rate of 9600 while operating at a core
clock frequency of 1.5725 MHz, that is, CD = 3,
Rx CLOCK
1 0 DIV = log(1572500/(16 × 9600))/log2 = 3.35 = 3
÷ 16
04741-058
T3 Rx/Tx T3EN
CLOCK Tx CLOCK Note that the DIV result is rounded down.
Figure 61. Timer 3, UART Baud Rate T3FD = (2 × 1572500)/(23−1 × 9600) − 64 = 18 = 12H
Two SFRs (T3CON and T3FD) are used to control Timer 3. Therefore, the actual baud rate is 9588 bps, which gives an error
T3CON is the baud rate control SFR, allowing Timer 3 to be of 0.12%.
used to set up the UART baud rate, and to set up the binary
divider (DIV). The T3CON and T3FD registers are used to control Timer 3.
T3CON – Timer 3 Control Register
SFR Address: 9EH
Power-On Default: 00H
Bit Addressable: No
Table 55. T3CON SFR Bit Designations
Bit No. Name Description
7 T3BAUDEN T3UARTBAUD Enable.
Set to enable Timer 3 to generate the baud rate. When set, PCON.7, T2CON.4, and T2CON.5 are
ignored. Cleared to let the baud rate be generated as per a standard 8052.
6 Not Implemented. Write Don’t Care.
5 Not Implemented. Write Don’t Care.
4 Not Implemented. Write Don’t Care.
3 Not Implemented. Write Don’t Care.
2, 1, 0 DIV2, DIV1, DIV0 Binary Divider
DIV2 DIV1 DIV0
0 0 0 Binary Divider 0. See Table 57.
0 0 1 Binary Divider 1. See Table 57.
0 1 0 Binary Divider 2. See Table 57.
0 1 1 Binary Divider 3. See Table 57.
1 0 0 Binary Divider 4. See Table 57.
1 0 1 Binary Divider 5. See Table 57.
1 1 0 Binary Divider 6. See Table 57.
Table 57. Common Baud Rates Using Timer 3 with a 12.58 MHz PLL Clock
Ideal Baud CD DIV T3CON T3FD % Error
230400 0 1 81H 2DH 0.18
LATCH
Separate analog and digital power supply pins (AVDD and DVDD,
A0–A7
respectively) allow AVDD to be kept relatively free of the noisy
ALE
digital signals often present on a system DVDD line. In this mode,
P2 A8–A15 the part can also operate with split supplies, that is, using different
voltage supply levels for each supply. For example, the system
RD OE
can be designed to operate with a DVDD voltage level of 3 V and
WR WE
04741-059
LATCH
04741-061
A0–A7 50
ALE
A8–A15
Figure 64. External Dual-Supply Connections
P2
(56-Lead LFCSP Pin Numbering)
LATCH
A16–A23 As an alternative to providing two separate power supplies,
AVDD can be kept quiet by placing a small series resistor and/or
RD OE ferrite bead between it and DVDD, and then decoupling AVDD
04741-060
04741-062
50
04741-087
INTERNAL
(56-Lead LFCSP Pin Numbering) CORE RESET
Notice that in both Figure 64 and Figure 65 a large value (10 µF)
reservoir capacitor sits on DVDD and a separate 10 µF capacitor Figure 67. 5 V Part POR Operation
sits on AVDD. Also, local decoupling capacitors (0.1 µF) are POWER CONSUMPTION
located at each VDD pin of the chip. As per standard design
The DVDD power supply current consumption is specified in
practice, be sure to include all of these capacitors and ensure
normal and power-down modes. The AVDD power supply
that the smaller capacitors are closer than the 10 µF capacitors
current is specified with the analog peripherals disabled. The
to each VDD pin with lead lengths as short as possible. Connect
normal mode power consumption represents the current drawn
the ground terminal of each of these capacitors directly to the
from DVDD by the digital core. The other on-chip peripherals
underlying ground plane. Finally, note that, at all times, the
(such as the watchdog timer and power supply monitor)
analog and digital ground pins on the part must be referenced
consume negligible current and are therefore included with the
to the same system ground reference point. It is recommended
normal operating current. The user must add any currents
that the LFCSP paddle be soldered to ensure mechanical
sourced by the parallel and serial I/O pins, and those sourced by
stability but be floated with respect to system VDDs or grounds.
the DAC to determine the total current needed at the ADuC845/
POWER-ON RESET OPERATION ADuC847/ADuC848 DVDD and AVDD supply pins. Also, current
drawn from the DVDD supply increases by approximately 5 mA
An internal power-on reset (POR) is implemented on the
during Flash/EE erase and program cycles.
ADuC845/ADuC847/ADuC848.
3 V Part POWER-SAVING MODES
For DVDD below 2.63 V, the internal POR holds the part in reset. Setting the power-down mode bit, PCON.1, in the PCON SFR
As DVDD rises above 2.63 V, an internal timer times out for described in Table 6, allows the chip to be switched from
typically 128 ms before the part is released from reset. The user normal mode into full power-down mode.
must ensure that the power supply has at least reached a stable
In power-down mode, both the PLL and the clock to the core
2.7 V minimum level by this time. Likewise on power-down,
are stopped. The on-chip oscillator can be halted or can
the internal POR holds the part in reset until the power supply
continue to oscillate, depending on the state of the oscillator
drops below 1 V. Figure 66 illustrates the operation of the
power-down bit (OSC_PD) in the PLLCON SFR. The TIC,
internal POR.
driven directly from the oscillator, can also be enabled during
2.63V TYP power-down. However, all other on-chip peripherals are shut
DVDD
1.0V TYP 128ms TYP 128ms TYP 1.0V TYP down. Port pins retain their logic levels in this mode, but the
DAC output goes to a high impedance state (three-state) while
ALE and PSEN outputs are held low. There are five ways to
terminate power-down mode:
04741-063
INTERNAL
CORE RESET
• Asserting the RESET Pin
Returns to normal mode. All registers are set to their reset
Figure 66. 3 V Part POR operation
default value and program execution starts at the reset
vector once the RESET pin is de-asserted.
Clock Oscillator
As described earlier, the core clock frequency for the ADuC845/
PLACE ANALOG PLACE DIGITAL
b. COMPONENTS COMPONENTS ADuC847/ADuC848 is generated from an on-chip PLL that
HERE HERE
locks onto a multiple (384 times) of 32.768 kHz. The latter is
AGND DGND generated from an internal clock oscillator. To use the internal
clock oscillator, connect a 32.768 kHz parallel resonant crystal
between XTAL1 and XTAL2 as shown in Figure 69.
ADuC845/ADuC847/ADuC848
XTAL1
PLACE ANALOG PLACE DIGITAL 32
c. COMPONENTS COMPONENTS 12pF
HERE HERE 32.768kHz
XTAL2 12pF
04741-065
Figure 68. System Grounding Schemes
Figure 69. Crystal Connectivity to ADuC845/ADuC847/ADuC848
If the user plans to connect fast logic signals (rise/fall time < 5 ns)
to any of the ADuC845/ADuC847/ADuC848’s digital inputs, As shown in the typical external crystal connection diagram in
add a series resistor to each relevant line to keep rise and fall Figure 69, two internal 12 pF capacitors are provided on-chip.
times longer than 5 ns at the parts’ input pins. A value of 100 Ω These are connected internally, directly to the XTAL1 and XTAL2
or 200 Ω is usually sufficient to prevent high speed signals from pins. The total input capacitance at both pins is detailed in the
coupling capacitively into the part and affecting the accuracy of Specifications table. Note that the total capacitance required for
ADC conversions. a particular crystal must be in accordance with the crystal
manufacturer. However, in most cases, no additional external
When using the LFCSP package, it is recommended that the capacitance is required above that already supplied on-chip.
paddle underneath the chip be soldered to the board to provide
maximum mechanical stability. However, it is recommended OTHER HARDWARE CONSIDERATIONS
that this paddle not be grounded but left floating. All results In-Circuit Serial Download Access
and specifications contained in this data sheet are taken or Nearly all ADuC845/ADuC847/ADuC848 designs can take
recorded with the paddle floating. advantage of the in-circuit reprogrammability of the chip. This
is accomplished by a connection to the parts’ UART, which
System Self-Identification
requires an external RS-232 chip for level translation if down-
In some hardware designs, it may be advantageous for the loading code from a PC. Basic configuration of an RS-232
software to be able to identify the host MicroConverter. connection is shown in Figure 70 with a simple ADM3202-
The CHIPID SFR is a read-only register located at SFR address based circuit. If users would rather not include an RS-232 chip
C2H. The upper nibble of this SFR designates the MicroConverter on the target board, refer to Application Note uC006,
within the Σ-Δ ADC family. User software can read this SFR to “A 4-Wire UART-to-PC Interface” available at
identify the host MicroConverter and therefore execute slightly www.analog.com/microconverter, for a simple (and zero-cost-
different code if required. The CHIPID SFR reads as follows for per-board) method of gaining in-circuit serial download access
the Σ-Δ ADC family of MicroConverter products. Note that the to the part.
ADuC845/ADuC847/ADuC848 are treated as one part as far as
the CHIPID is concerned.
1kΩ DVDD
1kΩ
2-PIN HEADER FOR
EMULATION ACCESS
44 43 (NORMALLY OPEN)
PSEN
EA
11 P1.6/IEXC1/AIN7
200µA/400µA
EXCITATION AVDD ADuC845/ADuC847/ADuC848
CURRENT
4 AVDD
0.1µF LFCSP PACKAGE
5 AGND
6 AGND XTAL2 35
RTD
7 REFIN– XTAL1 34
8 REFIN+ 32.768kHz
RREF
5.6kΩ 56 P1.0/AIN1
1 P1.1/AIN2
RESET
DGND
DVDD
RxD
TxD
DVDD 17 18 19 22 36 51 23 37 38 50
RS-232 INTERFACE1
STANDARD D-TYPE
ADM3202 SERIAL COMMS
CONNECTOR TO
C1+ VCC PC HOST
0.1µF 0.1µF
V+ GND 1
C1– T1OUT 2
C2+ R1IN 3
C2– R1OUT 4
0.1µF
V– T1IN 5
T2OUT T2IN 6
R2IN R2OUT 7
8
9
04741-088
NOTES
1. EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS PART
OF AN EXTERNAL DONGLE AS DESCRIBED IN APPLICATION NOTE uC006.
In addition to the basic UART connections, users also need a download mode and fail to begin user code execution. To
way to trigger the chip into download mode. This is prevent this, ensure that no external signals are capable of
accomplished via a 1 kΩ pull-down resistor that can be pulling the PSEN pin low, except for the external PSEN jumper
jumpered onto the PSEN pin, as shown in Figure 70. To get the itself or the method of download entry in use during a reset or
parts into download mode, connect this jumper and power- power-cycle condition.
cycle the device (or manually reset the device, if a manual reset Embedded Serial Port Debugger
button is available), and it is ready to receive a new program
From a hardware perspective, entry to serial port debug mode is
serially. With the jumper removed, the device powers on in
identical to the serial download entry sequence described
normal mode (and runs the program) whenever power is cycled
previously. In fact, both serial download and serial port debug
or RESET is toggled. Note that PSEN is normally an output and
modes are essentially one mode of operation used in two
that it is sampled as an input only on the falling edge of RESET,
different ways.
that is, at power-on or upon an external manual reset. Note also
that if any external circuitry unintentionally pulls PSEN low
during power-on or reset events, it could cause the chip to enter
1kΩ DVDD
1kΩ
2-PIN HEADER FOR
EMULATION ACCESS
44 43 (NORMALLY OPEN)
PSEN
EA
11 P1.6/IEXC1/AIN7
200µA/400µA
EXCITATION AVDD ADuC845/ADuC847/ADuC848
CURRENT
4 AVDD DGND
0.1µF LFCSP PACKAGE
5 AGND DVDD
6 AGND XTAL2 35
RTD
7 REFIN– XTAL1 34
8 REFIN+
RREF
5.6kΩ 56 P1.0/AIN1
1 P1.1/AIN2
AVDD
R
2 P1.2/AIN3/REFIN2+
R 15 AIN9
16 AIN10
3 P1.3/AIN4/REFIN2–
RESET
DGND
DVDD
RxD
TxD
DVDD 17 18 19 22 36 51 23 37 38 50
04741-067
RS232
CONNECTION
TIMING SPECIFICATIONS
AC inputs during testing are driven at DVDD – 0.5 V for Logic 1 and 0.45 V for Logic 0. Timing measurements are made at VIH min for
Logic 1 and VIL max for Logic 0 as shown in Figure 72.
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a
100 mV change from the loaded VOH/VOL level occurs as shown in Figure 72.
AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise
noted.
04741-077
0.2DVDD – 0.1V POINTS
VLOAD + 0.1V VLOAD – 0.1V
0.45V
ALE (O)
t WHLH
PSEN (O)
tLLDV
tLLWL t RLRH
RD (O)
tAVWL
tRLDV
tRHDZ
tLLAX tRHDX
tAVLL
tRLAZ
PORT 0 (I/O) A0�A7 (OUT) DATA (IN)
tAVDV
04741-078
ALE (O)
tWHLH
PSEN (O)
t LLWL t WLWH
WR (O)
t AVWL
t QVWX tWHQX
t LLAX
tAVLL t QVWH
A0�A7 DATA
04741-079
Parameter
Min Max Unit
tL SCLCK Low Pulse Width 1.3 µs
tH SCLCK High Pulse Width 0.6 µs
tSHD Start Condition Hold Time 0.6 µs
tDSU Data Setup Time 100 µs
tDHD Data Hold Time 0.9 µs
tRSU Setup Time for Repeated Start 0.6 µs
tPSU Stop Condition Setup Time 0.6 µs
tBUF Bus Free Time Between a Stop Condition and a Start Condition 1.3 µs
tR Rise Time of Both SCLCK and SDATA 300 ns
tF Fall Time of Both SCLCK and SDATA 300 ns
tSUP1 Pulse Width of Spike Suppressed 50 ns
____________________________________________
1
Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns.
tBUF tSUP
tR
tDSU tDSU tF
tDHD tDHD
tRSU tR
tPSU tSHD tH
tL tSUP S(R)
PS tF
04741-080
STOP START REPEATED
CONDITION CONDITION START
SCLOCK
(CPOL = 0)
tSH tSL
tSR tSF
SCLOCK
(CPOL = 1)
tDAV
tDF tDR
MOSI
MSB BITS 6–1 LSB
04741-081
tDSU tDHD
SCLOCK
(CPOL = 0)
tSH tSL
tSR tSF
SCLOCK
(CPOL = 1)
tDAV
tDOSU tDF tDR
MOSI
MSB BITS 6–1 LSB
04741-082
tDSU tDHD
SS
tSS tSFS
SCLOCK
(CPOL = 0)
SCLOCK
(CPOL = 1)
MISO
MSB BITS 6–1 LSB
04741-083
tDSU tDHD
SS
tSS tSFS
SCLOCK
(CPOL = 0)
tSH tSL
tSR tSF
SCLOCK
(CPOL = 1)
tDAV
tDOSS
tDF tDR
tDSU tDHD
tXLXL
TxD
(OUTPUT CLOCK)
SET RI
tQVXH
OR
tXHQX SET TI
tDVXH tXHDX
04741-086
RxD
(INPUT DATA) LSB BIT 1 BIT 6 MSB
OUTLINE DIMENSIONS
14.15
1.03 2.45 13.90 SQ
MAX
0.88 13.65
0.73
39 27
SEATING 40 26
PLANE
7.80
REF
TOP VIEW 10.20
(PINS DOWN)
10° 10.00 SQ
2.10 6° 9.80
2.00 2° 0.23
0.11 VIEW A
1.95 PIN 1
52 14
7°
0.25 0° 1 13
MIN
0.10
COPLANARITY 0.38
0.65 BSC
0.22
VIEW A LEAD PITCH
ROTATED 90° CCW LEAD WIDTH
8.10 0.30
0.60 MAX
8.00 SQ 0.23
7.90 0.18
0.60
MAX PIN 1
43 56 INDICATOR
42 1
PIN 1 0.50
INDICATOR BSC
7.85
7.75 SQ EXPOSED 6.25
PAD
7.65 6.10 SQ
5.95
29 14
28 15
0.50 0.25 MIN
TOP VIEW 0.40 BOTTOM VIEW
0.30 6.50 REF
0.80 MAX
1.00 12° MAX 0.65 TYP FOR PROPER CONNECTION OF
0.85 THE EXPOSED PAD, REFER TO
0.80 0.05 MAX THE PIN CONFIGURATION AND
0.02 NOM FUNCTION DESCRIPTIONS
SIDE VIEW COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.20 REF 0.08
06-07-2012-A
PLANE
NOTES
NOTES
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.