Holtek BC2161 V182

BC2161
Sub-1GHz OOK
Transmitter with Encoder
Features Development Tools

• Operating voltage: VDD=2.2V~3.6V For rapid product development and to simplify device
parameter setting, Holtek has provided relevant
• Complete Sub-1GHz OOK (BT=0.5) modulation
development tools which users can download from
transmitter
the following link:
• Key input function
♦ 2 key inputs for the 8-pin SOP-EP package type https://www.holtek.com/rf-workshop
♦ 8 key inputs for the 16-pin NSOP-EP package https://www.holtek.com/rf-chip-parameters-setting-
types tool
• Avoid battery exhaust due to jammed button

(MAX_FCNT[7:0]) General Description
• Frequency bands: 315MHz, 433MHz, 868MHz,
915MHz The BC2161 is a highly integrated OOK transmitter
for remote wireless applications. The transmitter is a
• Integrated 320-bit FUSE data memory
true "data-in, antenna-out" monolithic device making
• Output power of up to 13dBm it very easy for users to implement wireless systems.
• Supports 2-wire I2C interface
The BC2161 can operate at the 315MHz, 433MHz,
• Low sleep current of 0.4μA 868MHz and 915MHz frequency bands. It supports
• TX current consumption @ 433MHz: an OOK modulation scheme and can operate with a
♦ TYP. 18.5mA(10dBm, Data=1)/Typ. 11.2mA symbol rate of up to 24ksps.
(10dBm, 50% duty cycle) The BC2161 offers a programmable output power
• Programmable symbol rate from 1.5ksps to 24ksps level. It is capable of delivering +13dBm maximum
for OOK modulation power into a 50Ω load. The BC2161 adopts agile state
machines to ease the control and minimize the power
• Integrated full range VCO, loop filter and Fractional-N
consumption. With an external crystal and a few
PLL synthesizer
external components, the BC2161 can implement a
• Supports 16MHz crystal complete solution for an effective RF transmitter.
• 4-step programmable TX Power: 0/5/10/13 dBm
These features can be easily programmed through
• FCC / ETSI Compliant I2C interface or internal FUSE. With these combined
• Sm a ll s ize p ac k ag e ty p e s : 8 -p in S O P -EP, features the BC2161 can provide a power-saving and
16-pin NSOP-EP/QFN cost effective solution for a huge range of remote
wireless applications.
Abbreviation Notes
• TX: RF Transmitter
• SX: Synthesizer
• PA: Power Amplifier
• OOK: On-Off Keying
• PLL: Phase Lock Loop
• MMD: Multi-Mode Divider
• XTAL: External Crystal
Rev. 1.82 1 June 07, 2023

BC2161
Block Diagram
D4~D7/A0~A4 XOSC XOSCIN

Data latch
D2~D3 & VDDRF VDDRF
Code
Generator VDDRF
OOK Ramp
Modulator PA RFOUT
Control
PAVSS
D0/SDA/ICPDA
PAVSS PAVSS
Digital
Control
Logic DVDD DVDD
DVDD
D1/SCL/ICPCK Fuse
& Data GND VSS
LED Memory
GND GND
: Expose Pad
Pin Assignment
D0/SDA/ICPDA 1 16 D1/SCL/ICPCK
LED 2 15 D2
DVDD 3 14 D3
NC 4 VSS/ 13 D4/A0
RFOUT 1 8 DVDD VSS 5 EP 12 D5/A1
PAVSS 2 VSS/ 7 LED RFOUT 6 11 D6/A2
VDDRF 3 EP 6 D0/SDA/ICPDA PAVSS 7 10 D7/A3
XOSCIN 4 5 D1/SCL/ICPCK VDDRF 8 9 XOSCIN
BC2161 BC2161
8 SOP-EP-A 16 NSOP-EP-A
D0/SDA/ICPDA
D1/SCL/ICPCK
LED
D2
16 15 14 13
DVDD 1 12 D3
VSS 2 VSS/ 11 NC
RFOUT 3 EP 10 D4/A0
PAVSS 4 9 D5/A1
5 6 7 8
VDDRF
XOSCIN
D7/A3
D6/A2
BC2161
16 QFN-A
Rev. 1.82 2 June 07, 2023

BC2161
Pin Description
The function of each pin is listed in the following table. Note that where more than one package type exists the
table will reflect the situation for the 16-pin NSOP-EP package type.
Pin No. Pin Name Function Type Description

D0 I Data input
1 D0/SDA/ICPDA SDA I/O I2C data pin
ICPDA I/O ICP data pin
2 LED LED O LED indicator
3 DVDD DVDD PWR RF digital positive power supply
4 NC No connection — —
5 VSS Ground PWR Ground
RF output signal from power amplifier
6 RFOUT PA_OUT AO
– Connect to matching circuit
7 PAVSS VSSRF_PA PWR RF ground
8 VDDRF VDDRF PWR Analog positive power supply
9 XOSCIN Crystal AI Crystal input
Compound pin
10~13 D4/A0~D7/A3 D4/A0~D7/A3 I
Data / Address / Key Trigger input
14,15 D2, D3 D2, D3 I Data input
D1 I Data input
16 D1/SCL/ICPCK SCL I I2C clock pin
ICPCK I ICP clock pin
— VSS/EP Ground PWR Exposed pad, must be connected to ground
Legend: I: Digital Input O: Digital Output AI: Analog Input

AO: Analog Output PWR: Power
Absolute Maximum Ratings

Supply Voltage........................................................................................................................... VSS-0.3V to VSS+3.6V
Voltage on I/O Pins................................................................................................................... VSS-0.3V to VDD+0.3V
Storage Temperature............................................................................................................................ -60°C to 150°C
Operating Temperature.......................................................................................................................... -40°C to 85°C
ESD HBM............................................................................................................................................................ ±2kV
* Devices being ESD sensitive. HBM (Human Body Mode) is based on MIL-STD-883.
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings"
may cause substantial damage to the device. Functional operation of this device at other conditions beyond
those has listed in the specification is not implied and prolonged exposure to extreme conditions may affect
device reliability.
Rev. 1.82 3 June 07, 2023

BC2161
D.C. Characteristics
Ta=25°C, VDD=3.3V, fXTAL=16MHz, OOK modulation with Matching circuit,
PAOUT is powered by VDD=3.3V, unless otherwise noted.
Symbol Parameter Description Min. Typ. Max. Unit
VDD Operating Voltage — 2.2 3.3 3.6 V
TA Operating Temperature — -40 — 85 °C
TFP FUSE Program Temperature — — 25 — °C
VIH High Level Input Voltage — 0.7VDD — VDD V
VIL Low Level Input Voltage — 0 — 0.3VDD V
VOH High Level Output Voltage @IOH=-5mA 0.8VDD — VDD V
VOL Low Level Output Voltage @IOL=5mA 0 — 0.2VDD V
ISleep in the Deep Sleep Mode — 0.4 — μA
Current Consumptions
IL Data low & PA off current — 6.0 — mA
POUT=0dBm — 10.5 —
Current Consumption @ 315MHz Band
POUT=10dBm — 18.5 — mA
(Data=1)
POUT=13dBm — 24.5 —
POUT=0dBm — 11.0 —
(Data=1)
POUT=13dBm — 25.0 —
IH
POUT=0dBm — 13.5 —
(Data=1)
POUT=13dBm — 24.5 —
POUT=0dBm — 12.5 —
POUT=10dBm — 19 — mA
(Data=1)
POUT=13dBm — 24 —
A.C. Characteristics
RF Characteristics
Ta=25°C, VDD=3.3V, fXTAL=16MHz, OOK modulation with Matching circuit,
PAOUT is powered by VDD=3.3V, unless otherwise noted.
Symbol Parameter Condition Min. Typ. Max. Unit
ZRF
315
433
fRF RF Operating Frequency Range — — — MHz
868
915
XTAL
fXTAL RF Operating XTAL Frequency General case — 16 — MHz
ESR XTAL Equivalent Series Resistance — — — 100 Ω
CL XTAL Capacitor Load — — 16 — pF
XTAL Tolerance(1) — — ±20 — ppm
tStartup XTAL Startup Time(2) — — 1 — ms
PLL
fSTEP RF Frequency Synthesizer Step — — 0.5 — kHz
Phase Noise @ 100k offset -78
PLL Phase Noise @ 433MHz — —
Phase Noise @ 1M offset -105 dBc/
PNPLL
Phase Noise @ 100k offset -68 Hz
PLL Phase noise @ 868MHz — —
Phase Noise @ 1M offset -100
Rev. 1.82 4 June 07, 2023

BC2161
Symbol Parameter Condition Min. Typ. Max. Unit

TX
Symbol Rate OOK modulation 1.5 — 24 ksps
@ 433MHz 0 — 13
POUT RF Transmitter Output Power dBm
@ 868MHz 0 — 13
EROOK OOK Extinction Ratio OOK Modulation depth — 70 — dB
@ 315MHz
Occupied Bandwidth @ 433MHz
— 400 — kHz
(OOK, -20dBc) @ 868MHz
@ 915MHz
f < 1GHz — — -36
47MHz < f < 74MHz
Transmitter Spurious Emission 87.5MHz < f < 118MHz
SETX — — -54 dBm
(POUT=10dBm) 174MHz < f < 230MHz
470MHz < f < 790MHz
2nd, 3rd Harmonic — — -30
Note: 1. This is the total tolerance including (1)Initial tolerance (2)Crystal loading (3)Aging and (4)Temperature
dependence.
2. Depend on crystal property.
I2C Characteristics
Ta=-40°C~85°C, Ta=25°C Typical
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I2C Characteristics
fSCL Serial Clock Frequency — — — 1 MHz
tBUF Bus Free Time between Stop and Start Condition SCL=1MHz 250 — — ns
tLOW SCL Low Time SCL=1MHz 500 — — ns
tHIGH SCL High Time SCL=1MHz 500 — — ns
tsu(DAT) Data Setup Time SCL=1MHz 100 — — ns
tsu(STA) Start Condition Setup Time SCL=1MHz 250 — — ns
tsu(STO) Stop Condition Setup Time SCL=1MHz 250 — — ns
th(DAT) Data Hold Time SCL=1MHz 100 — — ns
th(STA) Start Condition Hold Time SCL=1MHz 250 — — ns
tr(SCL) Rise Time of SCL Signal SCL=1MHz — — 100 ns
tf(SCL) Fall Time of SCL Signal SCL=1MHz — — 100 ns
tr(SDA) Rise Time of SDA Signal SCL=1MHz — — 100 ns
tf(SDA) Fall Time of SDA Signal SCL=1MHz — — 100 ns
Rev. 1.82 5 June 07, 2023

BC2161
Power on Reset Electrical Characteristics

-40°C to 85°C Ta=25°C Typical
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV
RRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms
Minimum Time for VDD Stays at VPOR to Ensure
tPOR — — 1 — — ms
Power-on Reset
VDD
tPOR RRPOR
VPOR
Time
Functional Description To provide extra user flexibility, the device contains

an area of FUSE memory, which is a kind of one-time
This fully integrated RF transmitter can operate in the programmable non-volatile memory. If the FUSE has
315MHz, 433MHz, 868MHz and 915MHz frequency not been programmed, which can be determined by
bands. The additional of a crystal and a limited checking the EFPGM bit in the CFG0 register, users
number of external components are all that is required should connect the device to an MCU and setup the
to create a complete and versatile RF transmitter relevant RF register configurations in the I2C Mode
system. The device includes an internal power using an I2C interface. For devices whose FUSE are
amplifier and is capable of delivering up to +13dBm. already programmed, the FUSE memory contents
Such a power level enables a small form factor will be copied to the relevant registers automatically.
transmitter to operate near the maximum transmission However, the registers will be reset to their initial
regulation limits. The device can operate with OOK state when the device is powered off.
receiver type.
State Control
The device has integrated state machines that control the state transition between the different modes.
Power-on States
Power Off
Yes Match pattern Yes FUSE

ICPCK==0? Key Mode
Power on Det. In 32ms？ programming
No
No
No
No Copy FUSE to
CRC check No
EFPGM==0? registers & CRC Encoder==0?
fail?
Calculate
Yes Yes
Yes
FUSE power off I2C Mode
Rev. 1.82 6 June 07, 2023

BC2161
After power on, if the ICPCK pin is kept at a High FUSE ICP Mode
level by the internal pull-high function and the
EFPGM bit state is high, the FUSE data will be
Power off
automatically copied to the corresponding registers
and will be also used for CRC calculation. If the
EFPGM bit state is low, the FUSE power will be Power on
turned off and the device will enter the I2C mode.
ICPCK=Low
Key Mode
If users want to enter the Key mode, the Fuse must
Yes
be programmed, the Encoder bit should be set high.
During the Standby mode, if there is no key trigger
Matching pattern
event, the device will enter the Deep Sleep Mode Det. In 32ms
after a 2ms delay. When a key trigger event occurs,
which is a level trigger generated by pressing a Yes
button for more than 1ms, the transmitter will start
to transfer data. The interval between data frames FUSE
can be figured out using the following equation: 2ms programming
× (FRAME_GAP[2:0]). The transmission will end
when the Frame counter stops. The device will then After powering on, the device checks the ICPCK pin
enter the Deep Sleep Mode after a fixed delay time state, which is active low but which will be pulled
of 2ms. In the Deep Sleep Mode, the clock stops and high by the internal pull high function. By adding this
register configurations will all be reset. The device procedure, the device can still enter the programming
can only be woken up by an edge detection, which interface to check the programmed value even if it has
is implemented by pulling the Key pins from high been programmed. For the 8-pin package applications,
to low. After this happens the FUSE memory will be it is recommended that the D0 pin should be used
automatically copied to the relevant registers and the as a Key. As the device clock frequency is 16MHz,
device will enter the Standby mode. the device will enter the ICP Mode for FUSE
programming after a delay time of 32ms. Note that
TX Copy FUSE to the FUSE can only be programmed once.
Transmit registers
Key Transmission Copy Edge

Trigger done finish Detect
Standby mode Timer

Encoder==1 Deep Sleep
Key Mode & Timer on time up
No Key Trigger
Rev. 1.82 7 June 07, 2023

BC2161
I2C Mode
Encoder==0
I2C Mode
Copy FUSE to I2C write

I2C stop
registers TX data
Edge detect
TX
Deep Sleep Light Sleep Standby
Transmit
Delay for 10ms Frame counter stop
The device will enter the I2C Mode if the Encoder bit I2C Serial Programming
is low. Note that in the I2C mode, the device should
be connected with an MCU and operate as an I2C In the I2C Mode, the MCU can configure the internal
slave. During the Light Sleep Mode, the timer will be relevant registers using I2C serial programming. The
on and will start counting. After a delay time of 10ms transmitter only supports the I 2C format for byte
the device will enter the Deep Sleep Mode. If a toggle write, page write, byte read and page read formats.
action occurs on the SDA or SCL pin, the timer will The transmission procedure is shown below.
be reset and will restart counting. The device can be It should be noted that the I2C is a non-standard I2C
woken up from the Deep Sleep Mode if a falling edge interface, which only supports a single device for
is detected on pin SCL or SDA. Here it should be connection.
noted that the high-to-low pulse should be maintained
for at least 1ms. In this situation the FUSE data will • Symbol definition
be copied to the registers again and the device will ♦ S: Start symbol
return to the Light Sleep Mode. In this way the MCU ♦ RS: Repeat Start
can generate a complete I2C format to initiate the ♦ P: Stop symbol
follow-up state machine. To start a data transmission,
the I2C write TX data procedure must be executed ♦ DADDR[6:0]: device address, 21h
first and when finished the TX transmission will be ♦ R/W: read write select, R(0):write, (1): read
initiated after the I2C stop. The frames are transmitted ♦ RADDR[7:0]: register address
continuously, the TX transmission ends when the
frame counter stops after which the device will return
♦ ACK: A(0): ACK, NA(1): NAK
to the Light Sleep Mode. ♦ Bus Direction:
♦ Host to device:
Deep Light
Sleep Wake up Sleep Device to host:
State
SCL or SDA Low

I2C
1ms Start
Note: In the Key Mode, pins D0~D7 can be used as key

triggers, however in the I2C Mode, pins D0~D7
have no key trigger function and only pins D0
and D1 have wake-up functions. Therefore it is
suggested that for the 16-pin package types, pins
D2~D7 should be pulled high in the I2C Mode.
Rev. 1.82 8 June 07, 2023

BC2161
Byte Write
S DADDR[6:0] W A RADDR[7:0] A DATA A P
Page Write
S DADDR[6:0] W A RADDR[7:0] A DATA A DATA(n+1) A DATA(n+x) A P
Byte Read
S DADDR[6:0] W A RADDR[7:0] A RS DADDR[6:0] R A DATA NA P
Page Read
S DADDR[6:0] W A RADDR[7:0] A RS DADDR[6:0] R A DATA(n) A DATA(n+1) A DATA(n+x) NA P
tHIGH tLOW Repeated Start

Stop Start
Slave Addres
SCL
SDA
th(DAT) tsu(DAT)
tBUF
th(STA) tsu(STA)
Stop
SRW ACK Data ACK

SCL
SDA
tf(SDA) tr(SDA) tf(SCL) tr(SCL)

tsu(STO)
S = Start (1 bit)
SA = Slave Address (7 bits)
SR = SRW bit (1 bit)
M = Slave device send acknowledge bit (1 bit)
D = Data (8 bits)
A = ACK (RXAK bit for transmitter, TXAK for receiver, 1 bit)
P = Stop (1 bit)
I2C Communication Timing Diagram
Rev. 1.82 9 June 07, 2023

BC2161
Programming Methodology Example 1: HT6P20B

The device programming interface should utilise an Format:
adaptor with an integrated 16MHz crystal. Pilot(24 λ) Address(22-bit) Data(2-bit) End(4-bit)
Programming
Pin Name Pin Description
Pilot code is 24λ → LEAD_CODE[2:0]=000b;
Function
Address: [155555h], Address Length is 22-bit →
ICPCK ICPCK ICP clock
ADDR_LEN[2:0]=100b;
ICPDA ICPDA ICP data/address
VDD VDDRF & DVDD Power supply
DATA: 2 Keys (D1/D0) → KEY_SEL[1:0]=00b;
PAVSS & VSS & End code is 4-bit → END_CODE[1:0]=01b;
VSS, EP Ground
Exposed-Pad
Bit format: Low to High → Waveform=0b ;
XTAL IN
XOSCIN IC system clock → 1λ low + 2λ high (Data=Zero) / 2λ low + 1λ high
(Adaptor)
(Data=One)
When programming the device needs to be located
Data
on a Socket with a 16MHz crystal connected between Pilot 22-bit Address D1D0 End-Code
pin XOSCIN and ground. Holtek provides an e-link Press D0
or e-WriterPro tool for communication with the PC.
Between the e-link and the device there are four Press D0&D1
interconnecting lines, namely VDD, VSS, ICPCK and simultaneously
ICPDA pins.
Writer Connector IC Programming

Signals
Example 2: HT6P20D
Pins
Format:
Writer_VDD VDDRF
Pilot(24 λ) Address(20-bit) Data(4-bit) End(4-bit)
DVDD
ICPDA ICPDA Pilot code is 24λ → LEAD_CODE[2:0]=000b;

Address: [55555h]; Address Length is 20-bit →
ICPCK ICPCK ADDR_LEN[2:0]=011b;
PAVSS DATA: 4 Keys (D3/D2/D1/D0) → KEY_SEL[1:0]=01b;
Writer_VSS VSS
EP End code is 4-bit → END_CODE[1:0]=01b;
XOSCIN
* * Bit format: Low to High → Waveform=0b;
16MHz
→ 1λ low + 2λ high (Data=Zero) / 2λ low + 1λ high
(Data=One)
To other Circuit
Note: * may be resistor or capacitor - the resistance of Pilot 20-bit Address
Data
End-Code
D3D2D1D0
* must be greater than 1kΩ and the capacitance
Press D2
of * must be less than 1nF.
Press D2&D3
Encoder Packet Example – OOK Modulation simultaneously
Packet Structure:
Example 3: HT6P427A
Leading
(Strat) Address Data (CRC) (End) Format:
Code
Pilot(32 λ) Address(20-bit) Data(4-bit)
In the above structure, the procedures enclosed in
brackets mean optional and can therefore be disabled. Pilot code is 32λ → LEAD_CODE[2:0]=001b;
The rest are leading code, address and data, which are Address: [99999h]; Address Length is 20-bit →
necessary parts of the packet. These parameters can ADDR_LEN[2:0]=011b;
be configured but can never be disabled.
DATA: 4 Keys (D3/D2/D1/D0) → KEY_SEL[1:0]=01b;
Bit format: High to Low → Waveform=1b;
→ 1λ high + 3λ low (Data=Zero) / 3λ high + 1λ low
(Data=One)
Rev. 1.82 10 June 07, 2023

BC2161
Data End code is 4-bit → END_CODE[1:0]=01b;

Pilot 20-bit Address D3 D2 D1 D0
Press D0 Bit format: Low to High → Waveform=0b;
Press D2&D3 → 1λ low + 2λ high (Data=Zero) / 2λ low + 1λ high
simultaneously
(Data=One)
Data
Example 4: HT6P437A Pilot 24-bit Address D3 D2 D1 D0 End-Code
Format: Press D2
Internal External
Pilot(32 λ) Data(4-bit) Press D0&D1
Address(20-bit) Address(4-bit) simultaneously

Example 7: HT12E
Address: [DDDDDh] + Dipswitch; Address Length is Format:
20-bit → ADDR_LEN[2:0]=011b;
Pilot(37 λ) Address(8-bit) Data(4-bit)
DATA: 4 Dipswitches (A3/A2/A1/A0) + 4 Keys (D3/
D2/D1/D0) → KEY_SEL[1:0]=10b; Pilot code is 37λ → LEAD_CODE[2:0]=010b;
Bit format: High to Low → Waveform=1b; Address: [55h]; Address Length is 8-bit → ADDR_
LEN[2:0]=000b;
(Data=One) DATA: 4 Keys (D3/D2/D1/D0) → KEY_SEL[1:0]=01b;
External 4-bit
Address Data
Bit format: Low to High → Waveform=0b;
Pilot Internal 20-bit Address
A3 A2 A1 A0 D3 D2 D1 D0
Press D0
A3A2A1A0 → 0110 → 1λ low + 2λ high (Data=Zero) / 2λ low + 1λ high
Press D2&D3 (Data=One)
simultaneously
A3A2A1A0 → 0110
Data
Pilot 8-bit Address D3D2D1D0
Example 5: HT6P237A
Press D2
Format:
Pilot(24 λ) Address(22-bit) Data(2-bit) End(4-bit) Press 4 Keys
simultaneously
Example 8: Custom Format
Address: [3EEEEEh]; Address Length is 22-bit →
ADDR_LEN[2:0]=100b; Format:
Pilot Start Address Data CRC End
DATA: 2 Keys (D1/D0) → KEY_SEL[1:0]=00b; (16 λ) (6 λ) (8-bit) (4-bit) (8-bit) (4 λ)
End code is 4-bit → END_CODE[1:0]=01b;
Start code is 6λ → START_BIT[1:0]=01b;
→ 1λ low + 2λ high (Data=Zero) / 2λ low + 1λ high
(Data=One) Address: [93h]; Address Length is 8-bit → ADDR_
LEN[2:0]=000b;
Data
Pilot 22-bit Address
D1D0End-Code DATA: 4 Keys (D3/D2/D1/D0) → KEY_SEL[1:0]=01b;
Press D1
CRC: 8-bit → CRC[1:0]=10b;
Press D0&D1
simultaneously
End Code is 4λ → END_CODE[1:0]=10b;
Bit format: High to Low → Waveform=1b;
Example 6: HT6P247A
Format:
(Data=One)
Press D0
Pilot Start End
Pilot code is 24λ → LEAD_CODE[2:0]=000b; 16λ 6λ
Address: 4 bits Data: 4 bits CRC: 8 bits
4λ
Address: [777777h]; Address Length is 24-bit →

ADDR_LEN[2:0]=101b;
DATA: 4 Keys (D3/D2/D1/D0) → KEY_SEL[1:0]=01b;
Rev. 1.82 11 June 07, 2023

BC2161
Fuse Register Map

This list provides a summary of all internal registers. Their detailed operation is described under their relevant
section in the functional description.
Register Bit
Address
Name 7 6 5 4 3 2 1 0
00h CFG0 Reserved EFPGM XO_TRIM[5:0]
01h CFG1 FRAME_GAP[2:0] Reserved
02h CFG2 Reserved
03h CFG3 Reserved
04h CFG4 Reserved
05h CFG5 Reserved
06h CFG6 Reserved
07h CFG7 Reserved
08h CFG8 Reserved
09h CFG9 Reserved
0Ah CFG10 D_K[3:0] TXPWR[3:0]
0Bh CFG11 D_N[5:0] BAND_SEL[1:0]
0Ch CFG12 D_K[11:4]
0Dh CFG13 D_K[19:12]
0Eh CFG14 BIT_WIDTH[4:0] LEAD_CODE[2:0]
0Fh CFG15 ADDR_LEN[2:0] END_CODE[1:0] START_BIT[1:0] Waveform
10h CFG16 Reserved Encoder Reserved CRC_SEL[1:0] KEY_SEL[1:0]
11h CFG17 Reserved
12h CFG18 Reserved
13h CFG19 Reserved
14h CFG20 Reserved
15h CFG21 ENCODER_ADDRL[7:0]
16h CFG22 ENCODER_ADDRM[7:0]
17h CFG23 ENCODER_ADDRH[7:0]
18h CFG24 ENCODER_ADDRU[7:0]
19h CFG25 FRAME_CNTR[7:0]
1Ah CFG26 Reserved
1Bh CFG27 Reserved
1Ch CFG28 Reserved TXD_INV TXD_REV LED_SWD Reserved
1Dh CFG29 Reserved
1Eh CFG30 MAX_FCNT[7:0]
1Fh CFG31 EFCRC_L[7:0]
20h CFG32 EFCRC_H[7:0]
21h CFG33 Reserved TX_FLAG
22h CFG34 Reserved
23h CFG35 Reserved
24h CFG36 Reserved
25h CFG37 Reserved
26h CFG38 Reserved
27h CFG39 Reserved
28h CFG40 I2C_DATA
If the Fuse is un-programmed, the BC2161 device will have a default state, determined by register initial values.
Operating Frequency: 433.92MHz TX Output Power: 10dBm
XTAL Capacitor Load: 14.85pF Encoding Format: HT6P427A
Symbol Rate: 4ksps Encoder: I2C Mode
Rev. 1.82 12 June 07, 2023

BC2161
• CFG0: Configuration Control Register 0

Address Bit 7 6 5 4 3 2 1 0
Name Reserved EFPGM XO_TRIM[5:0]
00h R/W R/W R R/W
Initial Value 1 0 1 0 0 0 0 0
Bit 7 Reserved, must be [0b1]

Bit 6 EFPGM: FUSE programmed, read only by the Holtek RF Tool
0: Fuse is not programmed – FUSE data is not mapped to the configuration registers
1: Fuse is programmed – FUSE data is mapped to the configuration registers
Bit 5~0 XO_TRIM[5:0]: Trim the internal capacitor load value for the crystal
XO_TRIM[5:0] Equiv. CL (pF) XO_TRIM[5:0] Equiv. CL (pF)
0 9.87 32 14.85
4 10.00 36 15.48
8 10.12 40 16.16
12 11.44 44 16.81
16 12.16 48 17.49
17 12.33 52 18.07
18 12.49 56 18.67
20 12.83 60 19.20
24 13.50 63 19.61
28 14.15

Address Bit 7 6 5 4 3 2 1 0
Name FRAME_GAP[2:0] Reserved
01h R/W R/W R/W
Bit 7~5 FRAME_GAP[2:0]: TX frame interval time

t = 2ms × (FRAME_GAP[2:0])
000: 0ms
001: 2ms
010: 4ms
011: 6ms
100: 8ms
101: 10ms
110: 12ms
111: 14ms
Bit 4~0 Reserved, must be [0b10101]

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
02h R/W R/W
Rev. 1.82 13 June 07, 2023

BC2161

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
03h R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
04h R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
05h R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
06h R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
07h R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
08h R/W R/W
Rev. 1.82 14 June 07, 2023

BC2161

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
09h R/W R/W
• CFG10: Configuration Control Register10

Address Bit 7 6 5 4 3 2 1 0
Name D_K[3:0] TXPWR[3:0]
0Ah R/W R/W R/W
Bit 7~4 D_K[3:0]: Fractional of dividend for MMD, which will be described later.
Bit 3~0 TXPWR[3:0]: RF output power stage selection
The device has several output power values which are 0, 5, 10 and 13dBm.
TXPWR[3:0] RF Output Power (Typ.)
0000 0dBm
0100 5dBm
1000 10dBm
1100 13dBm
TXPWR[3:0] Fine Tune Level (Typ.)

XX00 0
XX01 1
XX10 2
XX11 3
Note that the adjusting range: Level 3 > Level 2 > Level 1 > Level 0

Address Bit 7 6 5 4 3 2 1 0
Name D_N[5:0] BAND_SEL[1:0]
0Bh R/W R/W R/W
Bit 7~2 D_N[5:0]: Integer of dividend for MMD

Bit 1~0 BAND_SEL[1:0]: Band Frequency Coarse Selection
BAND_SEL Frequency Divider
00 315MHz 2
01 433MHz 2
10 868MHz 1
11 915MHz 1
Note that the BAND_SEL only selects an approximate frequency range while the exact frequency
value is determined by the D_N and D_K bit fields. For example, the 433.92MHz belongs to 433MHz
frequency band in the BAND_SEL setting.
Rev. 1.82 15 June 07, 2023

BC2161

Address Bit 7 6 5 4 3 2 1 0
Name D_K[11:4]
0Ch R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name D_K[19:12]
0Dh R/W R/W
D_K[19:0]: 20-bit fractional of dividend for MMD

For example: XO=16MHz and TX frequency band=433MHz
1. For D_N field, (433M×Divider)/16M=54.125,
Take the integer part → D_N[5:0]=54-32=22=010110b
2. For D_K field, (433M×Divider)/16M=54.125,
Take the fractional part → D_K[19:0]=0.125 × 220=131072=0010-0000-0000-0000-0000b
Frequency Divider X’TAL D_N[5:0] D_K[19:4] D_K[3:0]

315MHz 2 16MHz 000111 0110-0000-0000-0000 0000
433MHz 2 16MHz 010110 0010-0000-0000-0000 0000
433.92MHz 2 16MHz 010110 0011-1101-0111-0000 1010
868MHz 1 16MHz 010110 0100-0000-0000-0000 0000
915MHz 1 16MHz 011001 0011-0000-0000-0000 0000

Address Bit 7 6 5 4 3 2 1 0
Name OOK Bit Rate[4:0] LEAD_CODE[2:0]
0Eh R/W R/W R/W
Bit 7~3 OOK Bit Rate[4:0]: Define the data bit rate (0.5k~6kbps)
OOK Bit Rate Data Rate tDW OOK Bit Rate Data Rate tDW
00000 0.5kbps 2ms 10000 2.1kbps 0.476ms
00001 0.6kbps 1.67ms 10001 2.2kbps 0.454ms
00010 0.7kbps 1.43ms 10010 2.3kbps 0.434ms
00011 0.8kbps 1.25ms 10011 2.4kbps 0.416ms
00100 0.9kbps 1.11ms 10100 2.5 kbps 0.4ms
00101 1.0kbps 1ms 10101 2.6kbps 0.384ms
00110 1.1kbps 0.91ms 10110 2.7kbps 0.37ms
00111 1.2kbps 0.83ms 10111 2.8kbps 0.357ms
01000 1.3kbps 0.77ms 11000 2.9kbps 0.344ms
01001 1.4kbps 0.72ms 11001 3.0kbps 0.333ms
01010 1.5kbps 0.667ms 11010 3.5kbps 0.285ms
01011 1.6kbps 0.625ms 11011 4.0kbps 0.25ms
01100 1.7kbps 0.59ms 11100 4.5kbps 0.222ms
01101 1.8kbps 0.55ms 11101 5.0kbps 0.2ms
01110 1.9kbps 0.53ms 11110 5.5kbps 0.181ms
01111 2.0kbps 0.5ms 11111 6.0kbps 0.166ms
Rev. 1.82 16 June 07, 2023

BC2161
Bit 2~0 LEAD_CODE[2:0]: Define the lead code

000: 23λLow + 1λHigh (HT6P20B/HT6P2x7A)
1λ
23λ
001: 1λHigh + 31λLow (HT6P4x7A)

λ 31λ
010: 36λLow + 1λHigh (HT12E)
1/3 bit sync. period

pilot period (12 bits)
011: 16λHigh+ 16λLow

16λ
16λ
100: (1λHigh + 1λLow) × 8 times, 16 symbols in total

λ
λ × 8 times

2λ × 8 times
2λ

λ
λ × 12 times

2λ × 12 times
2λ

Address Bit 7 6 5 4 3 2 1 0
Name ADDR_LEN[2:0] END_CODE[1:0] START_BIT[1:0] Waveform
0Fh R/W R/W R/W R/W R/W
Bit 7~5 ADDR_LEN[2:0]: Define the address length

ADDR_LEN Format
000 (HT12E) 8 bits
001 12 bits
010 16 bits
011 (HT6P427A) 20 bits
100 (HT6P20B, HT6P237A) 22 bits
101 (HT6P247A, HT6P437A) 24 bits
110 28 bits
111 32 bits
Rev. 1.82 17 June 07, 2023

BC2161
Bit 4~3 END_CODE[1:0]: Define the End code

END_CODE Format
00 Disable
01 (HT6P20B, HT6P237A, HT6P247A) (1λ Low + 2λ High + 2λ Low + 1λ High) × 2=(12λ)
10 4λ (Note 1)
11 2λ + 2λ (Note 2)
Notes:
1. The high or low level of the 4λ END_CODE is the opposite of the previous symbol level.
• Example 1: Clear the Waveform to "0", no matter that whether the data is "1" or "0", the last sym-
bol will be High, here the 4λ must be 4λ Low.
Pilot(24 λ) Address(22-bit) Data(2-bit) End(4 λ)

Address: [155555h]; Address length is 22-bit → ADDR_LEN[2:0]=100b;
1λ Low + 2λ High (Data=Zero) / 2λ Low + 1λ High (Data=One)
Data End-Code
Pilot 22-bit Address
D1D0 4λ
Press D0
Press D0&D1
simultaneously
• Example 2: Set the Waveform to "1", no matter whether the data is "1" or "0", the last symbol will
be Low, here the 4λ must be 4λ High.
2. 2λ + 2λ: these two 2λ are opposite to each other, while the high or low level of the first 2λ is opposite
to the previous symbol level.
• Example 1: Clear the Waveform to "0", no matter whether the data is "1" or "0", the last symbol
will be High, and here the 2λ + 2λ must be 2λ Low + 2λ High.
Pilot(24 λ) Address(22-bit) Data(2-bit) End(2 λ+2 λ)

Address: [155555h]; Address length is 22-bit → ADDR_LEN[2:0]=100b;
1λ Low + 2λ High (Data=Zero) / 2λ Low + 1λ High (Data=One)
Pilot 22-bit Address Data End-Code

D1D0 2λ+2λ
Press D0
Press D0&D1
simultaneously
• Example 2: Set the Waveform to "1", no matter that the data is "1" or "0", the last symbol will be
Low, and here the 2λ + 2λ must be 2λ High + 2λ Low.
Rev. 1.82 18 June 07, 2023

BC2161
Bit 2~1 START_BIT[1:0]: Only for OOK Encoder

START_BIT Format
00 Disable
01 (2λ Low + 4λ High)
10 (4λ High + 2λ Low)
11 6λ Low
Bit 0 Waveform:
Waveform Format
Low to High
1λ 2λ
Bit "0"
tDW
0
(HT6P20B, HT12E, 1λ 2λ
HT6P2x7A)
Bit "1"
Address/Data bit
1λ low + 2λ high (data=Zero)
2λ low + 1λ high (data=One)
High to Low
1λ 3λ
Bit "0"
tDW
1
(HT6P4x7A) 1λ 3λ
Bit "1"
Address/Data bit
1λ high + 3λ low (data=Zero)
3λ high + 1λ low (data=One)

Address Bit 7 6 5 4 3 2 1 0
Name Reserved Encoder Reserved CRC_SEL[1:0] KEY_SEL[1:0]
10h R/W R/W R/W R/W R/W R/W

Bit 6 Encoder: Mode selection
0: I2C Mode
1: Key Mode
Rev. 1.82 19 June 07, 2023

BC2161
Bit 3~2 CRC_SEL[1:0]: Select the address + data for CRC processing
The unit is Bit (not λ), the address is used as the high order of CRC polynomial and the data is used as
the low order.
CRC_SEL Format Polynomial Initial Value Note
00 Disable — — OOK
4 Bits → Take the low nibble of the CRC8
01 — — OOK
calculated result
10 8 Bits → X8 + X5 + X4 + 1 0x31 0x00 OOK
11 Reserved — — —
Bit 1~0 KEY_SEL[1:0]

KEY_SEL Format Data bits
00 2 Keys 2 bits
01 4 Keys 4 bits
10 4 Dipswitches + 4 Keys 4 bits (4-bit external address + 4-bit data)
11 8 Keys 8 bits
For the 16-pin package type, in the Key mode:

1. If this bit field is set as "00" then to select Keys D0~D1, the other 6 keys D2~D7 have no trigger
function;
2. If the value is "01" then to select Keys D0~D3, the other 4 keys D4~D7 have no trigger function;
3. If the value is "10" then to select 4 Dipswitches + 4 Keys, the 4 dipswitch I/O status will be latched
after power on, the dipswitches will maintain a pull-high or pull low status according to the latched
high or low level to avoid current leakage in the Deep Sleep mode. These four dipswitches D4~D7
have no trigger function but will affect the address.
4. If dipswitch ever been changed, it is recommended to re-trigger key or re-power on.
In the I2C Mode, the TX transmitting data is determined by the I2C_DATA bit field while the transmitting
data bit format is determined by the KEY_SEL bit field. The Data bit formats is shown as below:
I2C Mode OOK
2 Keys xx
4 Keys xxxx
4 + 4 Keys AAAAxxxx
8 Keys xxxx_xxxx
For 2-key/4-key/8-key configurations the data bit can be 2 bits, 4 bits and 8 bits respectively. As the
above table shows, if the KEY_SEL bit field is set as “10” to select 4 Dipswitches + 4 Keys, then I2C
will transmit 8-bit data (bit 7 ~ bit 0) and the bit 7 ~ bit 4 is regarded as Address.
In the Key Mode, the TX transmitting data is determined by the keys while the transmitting data bit
format is determined by the KEY_SEL bit field. The Data bit formats is shown as below:
Key Mode OOK
2 Keys xx
4 Keys xxxx
4 + 4 Keys AAAAxxxx
8 Keys xxxx_xxxx
As the above table shows, if the KEY_SEL bit field is set as “10” to select 4 Dipswitches + 4 Keys,
the value of “A”is determined by Dipswitches and have no TX transmit trigger function. The data bit
format can be 2 bits, 4 bits and 8 bits when the KEY_SEL bit field is configured to select 2 keys, 4
keys and 8 keys respectively. When the bit field is set to select 4 Dipswitches + 4 Keys, then the low
nibble, bit 3~bit 0, is regarded as data and the 4-bit Dipswitches values is regarded as address.
Rev. 1.82 20 June 07, 2023

BC2161
LSB MSB
Internal Address
LSB MSB
Internal Address External Address (dipswitch) DATA
A0 A1 ~ An An+0 An+1 An+2 An+3 D3 D2 D1 D0
or
D0 D1 D2 D3
• HT6P427A
Pilot-code A0~A19 D0~D3
• HT6P437A
• HT6P237A
Pilot-code A0~A21 D1~D0 "0101"
• HT6P247A
• HT6P20B
• HT12E2Tx

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
11h R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
12h R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
13h R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
14h R/W R/W
The CFG17~CFG20 are reserved registers, whose default value must be fixed as 0xB0, 0xB1, 0xB2 and 0xB3
respectively.
Rev. 1.82 21 June 07, 2023

BC2161

Address Bit 7 6 5 4 3 2 1 0
Name ENCODER_ADDRL[7:0]
15h R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name ENCODER_ADDRM[7:0]
16h R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name ENCODER_ADDRH[7:0]
17h R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name ENCODER_ADDRU[7:0]
18h R/W R/W
The CFG21~CFG24 define the encoder address.

Address Bit 7 6 5 4 3 2 1 0
Name FRAME_CNTR[7:0]
19h R/W R/W
Bit 7~0 FRAME_CNTR[7:0]

The Frame Counter calculates the frame numbers using the following equation:
CNTR=FRAME_CNTR[7:0] + 1
0000: Transmit 1 complete frame
0001: Transmit 2 complete frames
:

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
1Ah R/W R/W
Rev. 1.82 22 June 07, 2023

BC2161

Address Bit 7 6 5 4 3 2 1 0
Name Reserved
1Bh R/W R/W
• CFG28 : Configuration Control Register28

Address Bit 7 6 5 4 3 2 1 0
Name Reserved TXD_INV TXD_REV LED_SWD Reserved
1Ch R/W R/W R/W R/W R/W R/W

Bit 6 TXD_INV: data inverse
0: No inverse. If key trigger, data will be "1".
1: DATA "0" will be inversed as "1" and vice versa. If key trigger, data will be "0".
Bit 5 TXD_REV: Data MSB and LSB reverse control
0: LSB MSB
Internal Address (ENCODER_ADDR) External Address(dipswitch) Data
D0 D1 D2 D3
1: LSB MSB
Internal Address (ENCODER_ADDR) External Address(dipswitch) Data
D3 D2 D1 D0
Bit 4 LED_SWD: LED switch

0: LED follows the TX
1: LED follows the symbol high

Address Bit 7 6 5 4 3 2 1 0
Name MAX_FCNT[7:0]
1Eh R/W R/W
Bit 7~0 MAX_FCNT[7:0]

The TX will be disabled when the Frame Counter stops. However this bit field is used for the counted
frames multiplication. This function is disabled when the bit field value is "0", otherwise the keys
should be pressed and hold for a maximum waiting time to disable the TX, where the maximum wait-
ing time = (FRAME_CNTR[7:0]+1) × MAX_FCNT[7:0]
The TX will be disabled when the Frame Counter stops. This feature can be used to prevent battery ex-
haust due to continued transmission made by jammed button.
BC2161 Frame (HT6P20B packet format)
Bit format:
1λ low + 2λ high → Data = Zero
2λ low + 1λ high → Data = One
Rev. 1.82 23 June 07, 2023

BC2161
Data Rate: 1kbps

1λ Time: 1ms/3 = 0.3333ms
Numbers of λ in a frame → 28-bit × 3λ + 24λ = 108λ
1 Frame time → 108λ × 0.3333ms = 35.9964ms
Example 1:
FRAME_CNTR[7:0] = 03b → Frame 1 / Frame 2 / Frame 3 / Frame 4
MAX_FCNT[7:0] = 00b
Key Trigger Key Release
Key State
Tx Packet Frame 1 Frame 2 Frame 3 Frame 4 Frame 1 Frame 2 Frame 3 Frame 4 Enter Stand-by
Key Trigger
Key State
Tx Packet Frame 1 Frame 2 Frame 3 Frame 4 Frame 1 Frame 2 Frame 3 Frame 4 Frame 1 Frame 2 Frame 3 Frame 4 Frame 1
：Key de-bounce
Example 2:
FRAME_CNTR[7:0]= 00b → Frame 1
MAX_FCNT[7:0] = 04b
When stuck key occurs, the power consumption caused by Tx continuous transmission can be avoided
by setting the MAX_FCNT[7:0] bits.
Total Frame Numbers = (FRAME_CNTR[7:0]+1) × MAX_FCNT[7:0]
Key Trigger
Key State
Tx Packet Frame 1 Frame 1 Frame 1 Frame 1 Enter Deep Sleep
：Key de-bounce

Address Bit 7 6 5 4 3 2 1 0
Name EFCRC_L[7:0]
1Fh R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name EFCRC_H[7:0]
20h R/W R/W
EFCRC field: for FUSE CRC calculation

The address range of the CRC calculation is from 00h to 1Eh, which contains 31 bytes in total. The input order is
LSB first, the CRC polynomial is X16 + X15 + X2 +1. The CRC on-line calculator can be accessed by the following
website: http://www.sunshine2k.de/coding/javascript/crc/crc_js.html
Rev. 1.82 24 June 07, 2023

BC2161
For example:
Data filled in the address range of 00h~1Eh are listed below:
0x4F 0x03 0x99 0x48 0xAB 0xCD 0xEF 0x7B 0x33 0x44 0xAB 0xCD 0xEF 0x93 0xFA 0x00 0x45 0xA9 0xB8
0xC7 0xD6 0xE5 0xF4 0x03 0x12 0x03 0x03 0x08 0xB6 0x00 0x00
The online calculator should be setup with the following configuration:
1. CRC width: select "CRC-16"
2. CRC parametrization: select "Custom"
3. CRC detailed parameters: select "Input reflected"
4. Polynomial: 0x8005
5. Initial Value: 0xFFFF
6. Final Xor Value: 0x0
7. CRC Input Data: select "Bytes" and fill in the data
8. Click on "Calculate CRC!"
9. Result CRC Value: 0x768C
As the following on-line calculator web interface screenshot shows:
Rev. 1.82 25 June 07, 2023

BC2161

Address Bit 7 6 5 4 3 2 1 0
Name Reserved TX_FLAG
21h R/W R/W R

Bit 0 TX_FLAG: Transmission flag
0: Transmission is in progress, LED on
1: No transmission, LED off
Default: LED off Default: LED off
Flag (Read Only): "1" Default: LED on Flag (Read Only): "1"
Flag (Read Only): "0"
Delay for
2ms
Standby Frame 1 Frame 2 Frame 3 Frame N Deep Sleep

Address Bit 7 6 5 4 3 2 1 0
Name I2C_DATA[7:0]
28h R/W R/W
Bit 7~0 I2C_DATA[7:0]: Data and address to be transmitted in the I2C mode
As the I2C state machine shows, the TX transmission will only be initiated after the I2C_DATA[7:0] field
has been written and the I2C stop is executed. The relationship between this bit field and the KEY_SEL
field in the CFG16 is described as below:
1. If KEY_SEL selects 2 Keys, the I2C will only transmit the data of bit 0 and bit 1, namely 2-bit data.
2. If KEY_SEL selects 4 Keys, the I2C will only transmit the data of bit 0~bit 3, namely 4-bit data.
3. If KEY_SEL selects 4 Dipswitches + 4 Keys, the I2C will transmit the data of bit 0~bit 7, so the 4-bit
External Address (Bit 4~Bit 7) and 4-bit data (Bit 0~Bit 3).
4. If KEY_SEL selects 8 Keys, the I2C will transmit the data of bit 0~bit 7, namely 8-bit data.
5. It should be noted that in the I2C mode, D0~D7 have no trigger function, the data is all determined
by the I2C_DATA bit field while the bit number is controlled by the KEY_SEL bit field.
Rev. 1.82 26 June 07, 2023

BC2161
Application Circuits
3.3V
0.1µF
Matching Circuit
1 8
RFOUT DVDD
R
2 7
PAVSS LED
3 6
3.3V VDDRF D0/ICPDA
4 5
XOSCIN D1/ICPCK
Crystal
16MHz EP Key Input
Rev. 1.82 27 June 07, 2023

BC2161
Package Information
Note that the package information provided here is for consultation purposes only. As this information may
be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the
Package Information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be
transferred to the relevant website page.
• Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• The Operation Instruction of Packing Materials
• Carton information
Rev. 1.82 28 June 07, 2023

BC2161
8-pin SOP-EP (150mil) Outline Dimensions

Dimensions in inch
Symbol
Min. Nom. Max.
A ― 0.236 BSC ―
B ― 0.154 BSC ―
C 0.012 ― 0.020
C' ― 0.193 BSC ―
D ― ― 0.069
D1 0.076 ― 0.090
E ― 0.050 BSC ―
E2 0.076 ― 0.090
F 0.000 ― 0.006
G 0.016 ― 0.050
H 0.004 ― 0.010
α 0° ― 8°
Dimensions in mm
Symbol
Min. Nom. Max.
A ― 6.00 BSC ―
B ― 3.90 BSC ―
C 0.31 ― 0.51
C' ― 4.90 BSC ―
D ― ― 1.75
D1 1.94 ― 2.29
E ― 1.27 BSC ―
E2 1.94 ― 2.29
F 0.00 ― 0.15
G 0.40 ― 1.27
H 0.10 ― 0.25
α 0° ― 8°
Note: For this package type, refer to the package information provided here, which will not be updated by the
Holtek website.
Rev. 1.82 29 June 07, 2023

BC2161
16-pin NSOP-EP (150mil) Outline Dimension

D1
1 8

E2

16 9
THERMAL VARIATIONS ONLY

Dimensions in inch
Symbol
Min. Nom. Max.
A — 0.236 BSC —
B — 0.154 BSC —
C 0.012 — 0.020
C’ — 0.390 BSC —
D — — 0.069
E — 0.050 BSC —
D1 0.152 — 0.186
E2 0.066 — 0.101
F 0.000 — 0.006
G 0.016 — 0.050
H 0.004 — 0.010
α 0° — 8°
Dimensions in mm
Symbol
Min. Nom. Max.
A — 6.00 BSC —
B — 3.90 BSC —
C 0.31 — 0.51
C’ — 9.90 BSC —
D — — 1.75
E — 1.27 BSC —
D1 3.86 — 4.72
E2 1.68 — 2.56
F 0.00 — 0.15
G 0.40 — 1.27
H 0.10 — 0.25
α 0° — 8°
Rev. 1.82 30 June 07, 2023

BC2161
SAW Type 16-pin QFN (3mm×3mm for FP0.25mm) Outline Dimensions
D2
13 16
b
12 1
E2
E
e
9 4
8 5
A1
A3 L K
D
A
Dimensions in inch
Symbol
Min. Nom. Max.
A 0.028 0.030 0.031
A1 0.000 0.001 0.002
A3 — 0.008 REF —
b 0.007 0.010 0.012
D — 0.118 BSC —
E — 0.118 BSC —
e — 0.020 BSC —
D2 0.063 — 0.069
E2 0.063 — 0.069
L 0.008 0.010 0.012
K 0.008 — —
Dimensions in mm
Symbol
Min. Nom. Max.
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A3 — 0.203 REF —
b 0.18 0.25 0.30
D — 3.00 BSC —
E — 3.00 BSC —
e — 0.50 BSC —
D2 1.60 — 1.75
E2 1.60 — 1.75
L 0.20 0.25 0.30
K 0.20 — —
Rev. 1.82 31 June 07, 2023

BC2161
Copyright© 2023 by HOLTEK SEMICONDUCTOR INC. All Rights Reserved.

The information provided in this document has been produced with reasonable
care and attention before publication, however, HOLTEK does not guarantee
that the information is completely accurate. The information contained in this
publication is provided for reference only and may be superseded by updates.
HOLTEK disclaims any expressed, implied or statutory warranties, including but
not limited to suitability for commercialization, satisfactory quality, specifications,
characteristics, functions, fitness for a particular purpose, and non-infringement of
any third-party’s rights. HOLTEK disclaims all liability arising from the information
and its application. In addition, HOLTEK does not recommend the use of
HOLTEK’s products where there is a risk of personal hazard due to malfunction
or other reasons. HOLTEK hereby declares that it does not authorise the use of
these products in life-saving, life-sustaining or safety critical components. Any use
of HOLTEK’s products in life-saving/sustaining or safety applications is entirely
at the buyer’s risk, and the buyer agrees to defend, indemnify and hold HOLTEK
harmless from any damages, claims, suits, or expenses resulting from such use.
The information provided in this document, including but not limited to the content,
data, examples, materials, graphs, and trademarks, is the intellectual property
of HOLTEK (and its licensors, where applicable) and is protected by copyright
law and other intellectual property laws. No license, express or implied, to any
intellectual property right, is granted by HOLTEK herein. HOLTEK reserves the
right to revise the information described in the document at any time without prior
notice. For the latest information, please contact us.
Rev. 1.82 32 June 07, 2023

Holtek BC2161 V182

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Holtek BC2161 V182

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BC2161

Features Development Tools

• Avoid battery exhaust due to jammed button

Rev. 1.82 1 June 07, 2023

D4~D7/A0~A4 XOSC XOSCIN

Rev. 1.82 2 June 07, 2023

Pin No. Pin Name Function Type Description

Legend: I: Digital Input O: Digital Output AI: Analog Input

Absolute Maximum Ratings

Rev. 1.82 3 June 07, 2023

Rev. 1.82 4 June 07, 2023

Symbol Parameter Condition Min. Typ. Max. Unit

Rev. 1.82 5 June 07, 2023

Power on Reset Electrical Characteristics

Functional Description To provide extra user flexibility, the device contains

Yes Match pattern Yes FUSE

FUSE power off I2C Mode

Rev. 1.82 6 June 07, 2023

Key Transmission Copy Edge

Standby mode Timer

Rev. 1.82 7 June 07, 2023

Copy FUSE to I2C write

Delay for 10ms Frame counter stop

SCL or SDA Low

Note: In the Key Mode, pins D0~D7 can be used as key

Rev. 1.82 8 June 07, 2023

tHIGH tLOW Repeated Start

SRW ACK Data ACK

tf(SDA) tr(SDA) tf(SCL) tr(SCL)

Rev. 1.82 9 June 07, 2023

Programming Methodology Example 1: HT6P20B

Writer Connector IC Programming

ICPDA ICPDA Pilot code is 24λ → LEAD_CODE[2:0]=000b;

Rev. 1.82 10 June 07, 2023

Data End code is 4-bit → END_CODE[1:0]=01b;

Pilot code is 32λ → LEAD_CODE[2:0]=001b;

Address: [777777h]; Address Length is 24-bit →

Rev. 1.82 11 June 07, 2023

Fuse Register Map

Rev. 1.82 12 June 07, 2023

• CFG0: Configuration Control Register 0

Bit 7 Reserved, must be [0b1]

• CFG1: Configuration Control Register 1

Bit 7~5 FRAME_GAP[2:0]: TX frame interval time

• CFG2: Configuration Control Register 2

Bit 7~0 Reserved, must be [0b10110110]

Rev. 1.82 13 June 07, 2023

• CFG3: Configuration Control Register 3

Bit 7~0 Reserved, must be [0b01000001]

• CFG4: Configuration Control Register 4

Bit 7~0 Reserved, must be [0b01000010]

• CFG5: Configuration Control Register 5

Bit 7~0 Reserved, must be [0b00010100]

• CFG6: Configuration Control Register 6

Bit 7~0 Reserved, must be [0b10011001]

• CFG7: Configuration Control Register 7

Bit 7~0 Reserved, must be [0b01011000]

• CFG8: Configuration Control Register 8

Bit 7~0 Reserved, must be [0b10100010]