CD4029BC Presettable Binary/Decade Up/Down Counter

October 1987
Revised January 2004

CD4029BC
Presettable Binary/Decade Up/Down Counter
General Description Features
The CD4029BC is a presettable up/down counter which ■ Wide supply voltage range: 3V to 15V
counts in either binary or decade mode depending on the ■ High noise immunity: 0.45 VDD (typ.)
voltage level applied at binary/decade input. When binary/
decade is at logical “1”, the counter counts in binary, other- ■ Low power TTL compatibility: fan out of 2 driving 74L
wise it counts in decade. Similarly, the counter counts up or 1 driving 74LS
when the up/down input is at logical “1” and vice versa. ■ Parallel jam inputs
A logical “1” preset enable signal allows information at the ■ Binary or BCD decade up/down counting
“jam” inputs to preset the counter to any state asynchro-
nously with the clock. The counter is advanced one count
at the positive-going edge of the clock if the carry in and
preset enable inputs are at logical “0”. Advancement is
inhibited when either or both of these two inputs is at logi-
cal “1”. The carry out signal is normally at logical “1” state
and goes to logical “0” state when the counter reaches its
maximum count in the “up” mode or the minimum count in
the “down” mode provided the carry input is at logical “0”
state.
All inputs are protected against static discharge by diode
clamps to both VDD and VSS.

Ordering Code:
Order Number Package Number Package Description
CD4029BCWM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
CD4029BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4029BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Connection Diagram

Top View

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CD4029BC
Logic Diagram

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 CD4029BC
Absolute Maximum Ratings(Note 1) Recommended Operating
(Note 2) Conditions (Note 2)
DC Supply Voltage (VDD) −0.5V to +18 VDC DC Supply Voltage (VDD) 3V to 15 VDC
Input Voltage (VIN) −0.5V to VDD + 0.5 VDC Input Voltage (VIN) 0V to VDD VDC
Storage Temperature Range (TS) −65°C to +150°C Operating Temperature Range (TA) −55°C to +125°C
Power Dissipation (PD) Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
Dual-In-Line 700 mW ture Range” they are not meant to imply that the devices should be oper-
Small Outline 500 mW ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
Lead Temperature (TL)
Note 2: VSS = 0V unless otherwise specified.
(Soldering, 10 seconds) 260°C

DC Electrical Characteristics (Note 2)

−55°C +25°C +125°C
Symbol Parameter Conditions Units
Min Max Min Typ Max Min Max
IDD Quiescent Device Current VDD = 5V 5 5 150
VDD = 10V 10 10 300 µA
VDD = 15V 20 20 600
VOL LOW Level |IO| < 1 µA
Output Voltage VDD = 5V 0.05 0 0.05 0.05
VDD = 10V 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05
VOH HIGH Level |IO| < 1 µA
Output Voltage VDD = 5V 4.95 4.95 5 4.95
VDD = 10V 9.95 9.95 10 9.95 V
VDD = 15V 14.95 14.95 15 14.95
VIL LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5
Input Voltage VDD = 10V, VO = 1V or 9V 3.0 3.0 3.0 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0
VIH HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5
Input Voltage VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0 V
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0
IOL LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36
Current (Note 3) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9 mA
VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4
IOH HIGH Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36
Current (Note 3) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9 mA
VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4
IIN Input Current VDD = 15V, VIN = 0V −0.1 −10−5 −0.1 −1.0
µA
VDD = 15V, VIN = 15V 0.1 10−5 0.1 1.0
Note 3: IOH and IOL are tested one output at a time.

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CD4029BC
AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, RL = 200k, Input trCL = tfCL = 20 ns, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
CLOCKED OPERATION
tPHL or tPLH Propagation Delay Time VDD = 5V 200 400
to Q Outputs VDD = 10V 85 170 ns
VDD = 15V 70 140
tPHL or tPLH Propagation Delay Time VDD = 5V 320 640
to Carry Output VDD = 10V 135 270 ns
VDD = 15V 110 220
tPHL or tPLH Propagation Delay Time CL = 15 pF
to Carry Output VDD = 5V 285 570
VDD = 10V 120 240 ns
VDD = 15V 95 190
tTHL or tTLH Transition Time/Q VDD = 5V 100 200
or Carry Output VDD = 10V 50 100 ns
VDD = 15V 40 80
tWH or tWL Minimum Clock VDD = 5V 160 320
Pulse Width VDD = 10V 70 135 ns
VDD = 15V 55 110
trCL or tfCL Maximum Clock Rise VDD = 5V 15
and Fall Time VDD = 10V 10 µs
VDD = 15V 5
tSU Minimum Set-Up Time VDD = 5V 180 360
VDD = 10V 70 140 ns
VDD = 15V 55 110
fCL Maximum Clock Frequency VDD = 5V 1.5 3.1
VDD = 10V 3.7 7.4 MHz
VDD = 15V 4.5 9
CIN Average Input Capacitance Any Input 5 7.5 pF
CPD Power Dissipation Capacitance Per Package (Note 5) 65 pF
PRESET ENABLE OPERATION
tPHL or tPLH Propagation Delay Time VDD = 5V 285 570
to Q output VDD = 10V 115 230 ns
VDD = 15V 95 195
tPHL or tPLH Propagation Delay Time VDD = 5V 400 800
to Carry Output VDD = 10V 165 330 ns
VDD = 15V 135 260
tWH Minimum Preset Enable VDD = 5V 80 160
Pulse Width VDD = 10V 30 60 ns
VDD = 15V 25 50
tREM Minimum Preset Enable VDD = 5V 150 300
Removal Time VDD = 10V 60 120 ns
VDD = 15V 50 100
CARRY INPUT OPERATION
tPHL or tPLH Propagation Delay Time VDD = 5V 265 530
to Carry Output VDD = 10V 110 220 ns
VDD = 15V 90 180
tPHL, tPLH Propagation Delay Time CL = 15 pF
to Carry Output VDD = 5V 200 400
VDD = 10V 85 170 ns
VDD = 15V 70 140
Note 4: *AC Parameters are guaranteed by DC correlated testing.
Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application
note, AN-90.

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 CD4029BC
Logic Waveforms
Decade Mode

Binary Mode

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CD4029BC
Switching Time Waveforms

Cascading Packages
Parallel Clocking

Ripple Clocking

Carry out lines at the 2nd or later stages may have a negative-going spike due to differential internal delays. These spikes
do not affect counter operation, but if the carry out is used to trigger external circuitry the carry out should be gated with the
clock.

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 CD4029BC
Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M16B

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CD4029BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D

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 CD4029BC Presettable Binary/Decade Up/Down Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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