Converters with 8-Channel Analog Multiplexer

Using the ADC0808/ADC0809 8-Bit mP Compatible A/D

National Semiconductor
Using the ADC0808/ Application Note 247
ADC0809 8-Bit mP Larry Wakeman
September 1980
Compatible A/D Converters
with 8-Channel Analog
Multiplexer

INTRODUCTION
The ADC0808/ADC0809 Data Acquisition Devices (DAD) The second function block, the successive approximation
implement on a single chip most the elements of the stan- A/D converter, transforms the analog output of the multi-
dard data acquisition system. They contain an 8-bit A/D plexer to an 8-bit digital word. The output of the multiplexer
converter, 8-channel multiplexer with an address input latch, goes to one of two comparator inputs. The other input is
and associated control logic. These devices provide most of derived from a 256R resistor ladder, which is tapped by a
the logic to interface to a variety of microprocessors with MOSFET transistor switch tree. The converter control logic
the addition of a minimum number of parts. controls the switch tree, funneling a particular tap voltage to
These circuits are implemented using a standard metal-gate the comparator. Based on the result of this comparison, the
CMOS process. This process is particularly suitable to appli- control logic and the successive approximation register
cations where both analog and digital functions must be im- (SAR) will decide whether the next tap to be selected
plemented on the same chip. should be higher or lower than the present tap on the resis-
tor ladder. This algorithm is executed 8 times per conver-
These two converters, the ADC0808 and ADC0809, are
sion, once every 8 clock periods, yielding a total conversion
functionally identical except that the ADC0808 has a total
time of 64 clock periods.
unadjusted error of g (/2 LSB and the ADC0809 has an
unadjusted error of g 1 LSB. They are also related to their When the conversion cycle is complete the resulting data is
big brothers, the ADC0816 and ADC0817 expandable 16 loaded into the TRI-STATEÉ output latch. The data in the
channel converters. All four converters will typically do a output latch can then be read by the host system any time
conversion in E 100 ms when using a 640 kHz clock, but before the end of the next conversion. The TRI-STATE ca-
can convert a single input in as little as E 50 ms. pability of the latch allows easy interface to bus oriented
systems.
1.0 FUNCTIONAL DESCRIPTION
The operation of these converters by a microprocessor or
The ADC0808/ADC0809, shown in Figure 1 , can be func- some control logic is very simple. The controlling device first
tionally divided into 2 basic subcircuits. These two subcir- selects the desired input channel. To do this, a 3-bit channel
cuits are an analog multiplexer and an A/D converter. The address is placed on the A, B, C input pins; and the ALE
multiplexer uses 8 standard CMOS analog switches to pro- input is pulsed positively, clocking the address into the mul-
vide for up to 8 analog inputs. The switches are selectively tiplexer address register. To begin the conversion, the
turned on, depending on the data latched into a 3-bit multi- START pin is pulsed. On the rising edge of this pulse the
plexer address register. internal registers are cleared and on the falling edge the
start conversion is initiated.

AN-247

TL/H/5623 – 1
FIGURE 1. ADC0808/ADC0809 Functional Block Diagram

TRI-STATEÉ is a registered trademark of National Semiconductor Corp.

C1995 National Semiconductor Corporation TL/H/5623 RRD-B30M115/Printed in U. S. A.

As mentioned earlier, there are 8 clock periods per approxi- full-scale is of great importance. For example, the poten-
mation. Even though there is no conversion in progress the tiometric displacement transducers of Figure 3 have this
ADC0808/ADC0809 is still internally cycling through these feature. When the wiper is at midscale, the output voltage is
8 clock periods. A start pulse can occur any time during this VO e VF c (Wiper Displacement) e VF c 0.5. This en-
cycle but the conversion will not actually begin until the con- ables the use of much less accurate and less expensive
verter internally cycles to the beginning of the next 8 clock references. The important consideration for this reference is
period sequence. As long as the start pin is held high no noise. The reference must be ‘‘glitch free’’ because a volt-
conversion begins, but when the start pin is taken low the age spike during a conversion cycle could cause conversion
conversion will start within 8 clock periods. inaccuracies.
The EOC output is triggered on the rising edge of the start
pulse. It, too, is controlled by the 8 clock period cycle, so it
will go low within 8 clock periods of the rising edge of the
start pulse. One can see that it is entirely possible for EOC
to go low before the conversion starts internally, but this is
not important, since the positive transition of EOC, which
occurs at the end of a conversion, is what the control logic
is looking for.
Once EOC does go high this signals the interface logic that
the data resulting from the conversion is ready to be read.
The output enable (OE) is then raised high. This enables the
TRI-STATE outputs, allowing the data to be read. Figure 2
shows the timing diagram.
2.0 ANALOG INPUTS
2.1 Ratiometric Inputs
The arrangement of the REF( a ) and REF(b) inputs is in-
tended to enable easy design of ratiometric converter sys-
tems. The REF inputs are located at either end of the 256R
resistor ladder and by proper choice of the input voltages
several applications can be easily implemented.
Figure 3 shows a typical input connection for ratiometric
transducers. A ratiometric transducer is a conversion device
whose output is proportional to some arbitrary full-scale val-
ue. In other words, the transducer’s absolute output value is
of no particular concern but the ratio of the output to the FIGURE 3. Ratiometric Converter
with Separate Reference

TL/H/5623 – 2
FIGURE 2. ADC0808/ADC0809 Timing Diagram

2
Since highly accurate references aren’t required it is possi- are shown in Figures 5 and 6 . The magnitude of the refer-
ble to use the system power supply as a reference, as ence voltage, VREF e REF( a ) b REF(b), can be varied
shown in Figure 4 . If the power supply is to be used in this from about E 0.5V to VCC, but the center voltage must be
manner supply noise must be kept to a minimum to pre- maintained within g 0.1V of VCC/2. This constraint is due to
serve conversion accuracy. If possible the supply should be the design of the transistor switch tree, which could mal-
well bypassed and separate reference and supply PC board function if the offset from center scale becomes excessive.
traces, originating as close as possible to the power supply Variation of the reference voltage can sometimes eliminate
or regulator, should be used. This is illustrated in Figure 4 . the need for external gain blocks to scale the input voltage
External accessibility of both ends of the resistor ladder en- to a full-scale range of 5V.
ables several variations on these basic connections, and

TL/H/5623 – 15
FIGURE 4. Ratiometric Converter with Power Supply Reference

TL/H/5623 – 3
FIGURE 5. Mid-Supply Centered Reference Using LM336 2.5V Reference

3
 TL/H/5623 – 4
FIGURE 6. Mid-Supply Centered Reference Using Buffered Resistors

Figure 5 shows a center referencing technique, using two As the reference voltage decreases, system noise will be-
equal resistors to symmetrically offset an LM336 2.5V refer- come more significant so greater precaution should be en-
ence, from both supplies. The offset from either supply is: forced at lower voltages to compensate for system noise;
VCC b VREF i.e., adequate supply and reference bypassing, and physical
VOFF e e 1.25V as well as electrical isolation of the inputs.
2
These resistors should be chosen so that they limit current 2.2 Absolute Analog Inputs
through the LM336 to a reasonable value, say 5 mA. The The ADC0808/ADC0809 may have been designed to easily
total resistor current is: utilize ratiometric transducers, but this does not preclude
IR e IREF a ILADDER a ITRAN the use of non-ratiometric inputs. A second type of input is
where ILADDER is the 256R ladder current, ITRAN is the cur- the absolute input. This is one which is independent of the
rent through all the transducers, and IREF is the current reference. This implies that its absolute numerical voltage
through the reference. R1 and R2 should be well matched value is very critical, and to accurately measure this voltage
and track each other over temperature. the accuracy of the reference voltage becomes equally crit-
ical. The previous designs can be modified to accommodate
For odd values of reference voltage, the reference could be absolute input signals by using a more accurate reference.
replaced by a resistor, but due to loading and temperature In Figure 4 the power supply reference could be replaced by
problems, these resistors should be buffered to the REF( a ) LM336-5.0 reference. R1 and R2 of Figure 6 , and R1 and
and REF(b) inputs, Figure 6 . The power supply must be R3 of Figure 7 may have to be made more accurately equal.
well bypassed as supply glitches would otherwise be
passed to the reference inputs. The reference voltage mag- In some small systems it is possible to use the precision
nitude is: reference as the power supply as shown in Figure 7 . An
unregulated supply voltage l5V is required, but the LM336-

# J
R2 5.0 functions as both a regulator and reference. The drop-
VREF e VDD For R3 e R1
2R1 a R2 ping resistor R must be chosen so that, for the whole range
There are several op amps that can be used for buffering of supply currents needed by the system, the LM336-5.0 will
this ladder. Without adding another supply, an LM358 could stay in regulation. As in Figure 4 separate supply and refer-
be used if the REF( a ) input is not to be set above 3.5V. The ence traces should be used to maintain a noiseless supply.
LM10 can swing closer to the positive supply and can be If the system requires more power, an op amp can be used
used if a higher VREF( a ) voltage is needed. as shown in Figure 8 to isolate the reference and boost the
As the REF( a ) to REF(b) voltage decreases the incremen- supply current capabilities. Here again, a single unregulated
tal voltage step size decreases. At 5V one LSB represents supply is required.
E 20 mV, but at 1V, one LSB represents E 4 mV.

4
2.3 Differential Inputs
Differential measurements can be obtained by playing a lit- from the first result. (See Figure 9 .) When using this proce-
tle software trick. This simply involves sequentially convert- dure, both input signals must be stable throughout both con-
ing two channels then subtracting the two results. For ex- version times or the end result will be incorrect. One way to
ample, if the difference voltage between channel 1 and 2 is get around this is to use two sample/holds which are sam-
required, merely convert channel 1 and read the result. pled at the same time.
Then convert channel 2, input the result, and subtract it

FIGURE 7. Precision Reference used as a Power Supply FIGURE 8. Precision Reference Buffered
for Power Supply

TL/H/5623 – 5
FIGURE 9. Software Controlled Differential Converter

5
A second method is to use two chips to convert a differen- parallel data acquisition scheme. Figure 11 shows this cir-
tial channel, Figure 10 . Typically each channel 1 would be cuit in which all the input channels are connected in pairs
connected to opposite sides of the differential input. Both through LF398 monolithic sample/holds. Under normal op-
converters are started simultaneously. When both convert- eration a sample/hold is accessed through an MM74C42
ers’ EOC outputs go high the output of the AND gate will go which will pulse an MM74C221, generating a sample pulse.
high indicating that the data is ready to be read. After a sample/hold is done sampling the signal, the appro-
The circuit in Figure 10 can be slightly modified to provide priate channel is started. If this process is alternated be-
increased data throughput by using two converters in a tween two converters the sample rate can be doubled.

TL/H/5623 – 6
FIGURE 10. Dual Converter Differential Circuit

6
2.4 Analog Input Considerations
Analog inputs into the ADC0808/ADC0809 can handle any pedance of the transducer or buffer. Using transducers with
input signal that is maintained within the supply limits, but large source impedances can cause errors due to compara-
some careful consideration must be given to the output im- tor input currents.

TL/H/5623 – 7
FIGURE 11. Parallel Data Acquisition with Sample/Holds

7
To understand the nature of these currents a short discus- many TTL circuits. The data outputs of the ADC0808/
sion of comparator operation is required. Figure 12 shows a ADC0809 are capable of driving one standard TTL load
simplified model of the comparator and multiplexer. This which is adequate for most small systems, but for larger
comparator alternately samples the input voltage and the systems extra buffering may be necessary. The EOC output
ladder voltage. As it samples the input, CC and CP are is not quite as powerful as the data outputs, but normally it is
charged up to the input voltage. It then samples the ladder not bussed like the data outputs.
and discharges the capacitor. The net charge difference is The converter inputs are standard CMOS compatible inputs.
determined by a modified inverter chain and results in a 1 or When TTL outputs are connected to any of the digital inputs
0 state at the output. a pull-up resistor should be tied from the TTL output to VCC,
Eight samples are made per conversion, resulting in eight E 5 kX. This will ensure that the TTL will pull-up above
spikes of varying magnitude on the input. 3.5V.
If the source resistance is large, it adds to the RC time con- Usually the converter clock will be derived from the micro-
stant of the switched capacitor which will inhibit the input processor system clock. Some slower microprocessor
from settling properly, causing errors. As one might expect, clocks can be used directly, but at worst a few divider
the maximum source resistance allowable for accurate con- stages may be necessary to divide microprocessor clock
versions is inversely proportional to clock frequency. This frequencies above 1.2 MHz to a usable value.
resistance should be s1 kX at 1.2 MHz and s2 kX at 640 The timing of the START and ALE pulses relative to channel
kHz. If a potentiometer-type ratiometric transducer is used it selection and signal stability can be critical. The simplest
should be s5 kX at 1.2 MHz and s10 kX at 640 kHz. approach to microprocessor interfaces usually ties START
If large source impedances are unavoidable (t2 kX at 640 and ALE together. When these lines are strobed the ad-
kHz), the transient errors can be reduced by placing a by- dress is strobed into the address register and the conver-
pass capacitor t0.1 mF from the analog inputs to ground. sion is started. The propagation delay from ALE to compar-
This will reduce the spikes to a small average current which ator input of the selected input signal is about E 3.0 ms
will cause some error as well, but this can be much less (input source resistance kk1 kX). If the start pulse is very
than the error otherwise incurred. The maximum voltage er- short the comparator can sample the analog input before it
ror for a potentiometer input with a bypass capacitor added is stable. When using a slow clock s500 kHz the sample
is: period of the comparator input is long enough to allow this
delay to settle out.

Ð (
RPOT Ck If the ADC0808/ADC0809 clock is l500 kHz, a delay be-
VERR & (IIN) V
5 640 kHz tween the START and ALE pulses is required. There are
three basic methods to accomplish this. The first possibility
where RPOT e total potentiometer resistance; IIN e maxi- is to design the microprocessor interface so that the START
mum input current at 640 kHz, 2 mA; and Ck e clock fre- and ALE inputs are separately accessible. This is simple if
quency. some extra address decoding is available. Separate acces-
For standard buffer source impedance the maximum error sibility of the START and ALE pins allows the microproces-
is: sor, via software, to set the delay time between the START
and ALE pulses.

Ð # 640 kHz J ( V
Ck
VERR e IINRS If extra decoding is not available, then START and ALE
could be tied together. To obtain the proper delay, the mi-
croprocessor would cause START/ALE to be strobed twice
where RS e buffer source resistance; IIN e the maximum
by executing the load and start instruction twice. The first
input current at 640 kHz, 2 mA; and Ck e clock frequency.
time this instruction is executed, the new channel address is
3.0 MICROPROCESSOR INTERFACING loaded and the conversion is started. The second execution
The ADC0808/ADC0809 converters were designed to inter- of this instruction will reload the same channel address and
face to most standard microprocessors with very little exter- restart the conversion. But since the multiplexer address
nal logic, but there are a few general requirements which register contents are unchanged the selected analog input
must be considered to ensure proper converter operation. will have already settled by the time the second instruction
Most microprocessors are designed to be TTL compatible is issued. Actual implementations of these ideas are shown
and, due to speed and drive requirements, incorporate in following sections.

TL/H/5623 – 8
FIGURE 12. Analog Multiplexer and Comparator Input Model

8
A third possibility when ALE and START are tied together is ADC0808/ADC0809 data must be read.
to stretch the microprocessor derived ALE/START pulse by
3.1 Interfacing to the 8080
inserting a one-shot at these inputs and creating a positive
pulse l3 ms. Since ALE loads the multiplexer register on The simplest interface would contain no address decoding,
the positive going edge of the pulse and START begins the which may seem unreasonable; but if the system ports are
conversion on the falling edge, the width of the pulse sets I/O mapped, up to 8 of them can be connected to the CPU
the ALE to START delay time. with no decoding. Each of the 8 I/O address lines would
serve as a simple port enable line which would be gated
Most microprocessor interfaces would be designed such
with read and write strobes to select a particular port. This
that a START pulse is issued by a memory or I/O write
scheme is shown in Figure 13 . A7 is the address line used
instruction, although a memory or I/O read can be used.
and, whenever it is zero and an I/O read or write is low, the
The ALE strobe on the other hand, requires a write by the
port is accessed. This implementation shows A, B, C con-
CPU when A, B, and C are connected to the data bus, and
nected to D0, D1, D2 causing the information on the data
could use a read instruction if A, B, and C are connected to
bus to select the channel, but A, B, and C could be connect-
the address bus, but the software could get confusing. The
ed to the address bus, with a loss of only 3 ports. Both
logic to derive the OE strobe must be connected to the
decoding schemes are tabulated in Figure 14 . (Remember
microprocessor so that a memory or I/O read instruction will
A, B, C inputs are only valid when selecting a channel to
cause OE to be pulsed. A read is required since the
convert, and are not used to read data.)

FIGURE 13. Minimum 8080/8224/8228 Interface TL/H/5623 – 9

Output Port Output Port

A7 A6 A5 A4 A3 A2 A1 A0 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0
Description Description
1 1 1 1 1 1 1 0 X X X Spare Port
0 1 1 1 1 0 0 0 Channel 0 Port
1 1 1 1 1 1 0 1 X X X Spare Port
1 1 1 1 1 0 1 1 X X X Spare Port 0 1 1 1 1 0 0 1 Channel 1 Port
1 1 1 1 0 1 1 1 X X X Spare Port 0 1 1 1 1 0 1 0 Channel 2 Port
1 1 1 0 1 1 1 1 X X X Spare Port 0 1 1 1 1 0 1 1 Channel 3 Port
1 1 0 1 1 1 1 1 X X X Spare Port 0 1 1 1 1 1 0 0 Channel 4 Port
1 0 1 1 1 1 1 1 X X X Spare Port 0 1 1 1 1 1 0 1 Channel 5 Port
0 1 1 1 1 1 1 1 0 0 0 Channel 0 Port 0 1 1 1 1 1 1 0 Channel 6 Port
0 1 1 1 1 1 1 1 0 0 1 Channel 1 Port 0 1 1 1 1 1 1 1 Channel 7 Port
0 1 1 1 1 1 1 1 0 1 0 Channel 2 Port
1 1 1 1 0 X X X Spare Port
0 1 1 1 1 1 1 1 0 1 1 Channel 3 Port
0 1 1 1 1 1 1 1 1 0 0 Channel 4 Port 1 1 1 0 1 X X X Spare Port
0 1 1 1 1 1 1 1 1 0 1 Channel 5 Port 1 1 0 1 1 X X X Spare Port
0 1 1 1 1 1 1 1 1 1 0 Channel 6 Port 1 0 1 1 1 X X X Spare Port
0 1 1 1 1 1 1 1 1 1 1 Channel 7 Port X e don’t care
FIGURE 14a. Write Address Decoding for 8080 Output FIGURE 14b. Modified Write Address Decoding for 8080
Ports (A, B, C Connected to D0, D1, D2) Output Ports (A, B, C Connected to A0, A1, A2)

9
 Two LSTTL NOR gates are used to generate the ADC0808/ The I/O port address structure for Figure 13’s implementa-
ADC0809 read/write strobes. When the 8080 writes to the tion is shown in Figure 14a . If the A, B, C inputs are tied to
ADC0808/ADC0809 the ALE and START inputs are A0, A1, A2 inputs the port structure is as shown in Figure
strobed, loading and starting the conversion. When the CPU 14b . The later method makes each channel look like a sep-
reads the ADC0808/ADC0809 the OE input is taken high, arate port address, whereas if A, B, C are tied to the data
and the data outputs are enabled. bus the ADC0808/ADC0809 looks like one start conversion
Figure 13 implements a simple interrupt concept where port address whose channel is selected by the 3-bit status
EOC is tied directly to the 8080 interrupt input. When the word written to it on the data bus.
INS8228 is used and the INTA pin is tied high through a 1 Figure 15 shows a slightly more complex interface, where
kX resistor, the interrupt will cause a restart, RST, instruc- the address is partially decoded by a DM74LS139, dual 2-4
tion to be executed, which will then cause a jump to a re- line decoder which creates the read and write strobes to
start vector and execution of the interrupt routine. If a very operate the converter. This design interfaces to the proces-
simple multi-interrupt system is desired, a wire OR’ed con- sor in a polled type of interface. An MM80C97 TRI-STATE
figuration employing resettable latches as shown in Figure buffer is used to buffer the EOC line to the data bus, as well
13’s inset can be used. In this simple design the MM74C74 as provide the correct level for the START, ALE, and OE
is reset when the ADC0808/ADC0809 data is read. If more pulses. The converter clock is a divided 8080 system clock.
complicated interrupt structures are required, then an inter-
rupt controller is usually the best solution.

Address A7 – A0 Description
0 0 X X X X X X Write-Start Conv.
0 0 X X X X X X Read-Input Data
0 1 X X X 0 0 0 Channel 1 Select
0 1 X X X 0 0 1 Channel 2 Select
0 1 X X X 0 1 0 Channel 3 Select
0 1 X X X 0 1 1 Channel 4 Select
0 1 X X X 1 0 0 Channel 5 Select
TL/H/5623 – 10
0 1 X X X 1 0 1 Channel 6 Select
0 1 X X X 1 1 0 Channel 7 Select
0 1 X X X 1 1 1 Channel 8 Select
0 1 X X X X X X Read-Input EOC

FIGURE 15. 8080/8224/8228 Interface Using Partial Decoding

10
Typically, the software to use Figure 15 would first select than A0, A1, A2, so that the information on the data bus
the desired channel by writing the channel address to the selects the channel to be converted. Figure 15 can be con-
ALE port address, 01XXXCBA, where X e don’t care, and nected in an interrupt mode by incorporating the interrupt
CBA is the channel address. Next the conversion is started flip-flop of Figure 13 .
by writing to the START address, 00XXXXXX. Now the proc- A few typical utility routines to operate the ADC0808/
essor must wait a few instruction cycles to allow EOC to fall. ADC0809 application in Figure 13 are shown in Figure 16a .
Once EOC falls, its status can be checked by reading the These routines assume that the resettable interrupt flip-flop
EOC line, address 01XXXXXX. When the EOC line is detect- is used. Figure 16b illustrates some typical polled I/O rou-
ed high again (a low on DO), the data can be read by ac- tines for Figure 15 . Notice that in Figure 16a the OUT
cessing the OE port, address 00XXXXXX. As in the previous START1 instruction is executed twice to allow the analog
example the A, B, C inputs can be tied to D0, D1, D2 rather input signal to settle as discussed earlier.
;
;
; START CONVERSION (A, B, C CONNECTED TO D0, D1, D2)
;
CHANN1 EQU 7
START1 EQU 7FH
DATA EQU 7FH
;
START: LDA CHANN1 ; LOAD CHANNEL ADDRESS INTO ACE
OUT START1 ; STORE IT TO ADC0808/ADC0809 AND START
OUT START1 ; RESTART ADC0808/ADC0809 TO ACCOUNT FOR
; ; MULTIPLEXER DELAY
EI ; ENABLE INTERRUPTS IF NOT ALREADY
Ð Ð ; PROCESS PROGRAM
;
; INTERRUPT HANDLER ROUTINE
;
INTRP: IN DATA ; READ DATA AND RESET INTERRUPT
Ð Ð ; PROCESS DATA
EI ; ENABLE INTERRUPTS IF DESIRED
RET ; RETURN TO MAIN PROGRAM

FIGURE 16a. Typical 8080 Resettable Interrupt I/O Routines

;
; START CONVERSION (A, B, C CONNECTED TO A0, A2, A3) AND POLL EOC
; (FIGURE 15)
SELECT EQU 40H ; SELECT CHANNEL 0
START EQU 00H ; START CONVERTER
EOCIN EQU 40H ; READ EOC
DATA EQU 00H ; READ DATA
START: OUT SELECT ; SELECT CHANNEL
OUT START ; START CONVERSION
N0P ; INSERT INSTRUCTIONS TO WAIT 0-8
N0P ; CLOCK PERIODS OF ADC0808/ADC0809 CLOCK
N0P ; FOR EOC TO DROP (8N0Ps MINIMUM)
N0P
N0P
;
; READ AND TEST EOC
;
STATUS: IN EOCIN ; INPUT EOC BIT
ANI 01H ; MASK OUT OTHER BITS
JZ READY ; IF INPUT BIT IS ZERO JUMP READY
Ð Ð ; ELSE CONTINUE EXECUTING PROGRAM
; OR
; CONTINUOUS POLLING ROUTINE
;
STAT 2: IN EOCIN ; INPUT EOC STATUS BIT
ANI 01H ; MASK OUT ALL BITS BUT D0
JNZ STAT 2 ; JUMP TO TRY AGAIN IF NOT READY
READY: IN DATA ; IF READY INPUT DATA
Ð Ð ; CONTINUE EXECUTING PROGRAM

FIGURE 16b. Typical Polled I/O Routines for ADC0808/ADC0809

11
The application in Figure 17 uses a 6-bit bus comparator memory would be set aside, as is accomplished by the
and a few gates to decode a read and write strobe. Viewed DM8131. Figure 18 also illustrates a typical 6800 interrupt
from the CPU this interface looks like a bidirectional data scheme using a flip-flop and open collector transistor. The
port whose address is set by the logic levels on the Tn in- interrupt is reset when the data is read. If more ports are
puts of the DM8131 comparator. When data is written to the needed, a decoder could be added as shown in Figure 19 .
ADC0808/ADC0809 the 3 least significant bits on the ad- Figure 19 also illustrates a polled I/O mode using TRI-
dress bus define the channel to be converted. The rest of STATE buffer to gate EOC onto the data bus. As with the
the bits are decoded to provide the START and ALE INS8080 the A, B, C inputs of the ADC0808/ADC0809 can
strobes. When the conversion is completed EOC sets the be connected to the address bus or the data bus.
interrupt flip-flop, and when the data is read the interrupt is The 6800 differs from the INS8080 in that the 6800 has a
reset. single read/write (R/W) strobe and a valid memory address
Both the decoder and the bus comparator methods of ad- (VMA), whereas the INS8080 has separate read and write
dress decoding have their own advantages. Bus compara- strobes (I/OR and I/OW). Normally, to obtain a read pulse,
tors will more completely decode addresses but are capable VMA, R/W and w2 are gated together and, for a write R/W
of only a limited number of port strobes. Decoders, on the is inverted. w2 is the 6800 phase 2 system clock. Also no-
other hand, provide less decoding but more port strobes. tice that the 6800 INT interrupt input is active low. This en-
There is a trade off for minimum parts systems as far as ables a standard wired-OR open collector design to be im-
which route to go, and it will depend on the CPU and type of plemented.
system. Figure 20 illustrates some typical 6800 software utility rou-
3.2 Interfacing to the 6800 tines for either polled or interrupt interfaces. Again notice
double start instructions.
The ADC0808/ADC0809 easily interface to more than one
microprocessor. The 6800 can also be used to control the 3.3 Z80 Interface
converter. The 6800 has no separate I/O address space so Interfacing the Z80 to the ADC0808 is much the same as
all I/O transfers must be memory mapped. In general more interfacing to an 8080/8224/8228 CPU group. CPU instruc-
address decoding logic is required to ensure that the I/O tion timing is very similar, except the read/write control sig-
ports don’t overlap existing memory. For small systems a nals are slightly different. Instead of the I/OW write strobe
partial address decoding scheme is shown in Figure 18 . there is the IOREQ and WR and instead of I/OR, IOREQ
Generally, if several ports are desired, a small block of and RD are supplied.

TL/H/5623 – 11
FIGURE 17. Interrupt-Type 8080/8224/8228 Interface Using 6-Bit Bus Comparator

12
FIGURE 18. Typical 6800 Interface with Partial Address Decoding

FIGURE 19. Full Decoded 6800 Interface Address TL/H/5623 – 12

13
 *
*UTILITY ROUTINES FOR ADC0808/ADC0809 INTERFACE
*
*
*LOAD AND START CONVERSION (FIGURE 18)
*
STATUS EQU $D800 START ADDRESS FOR CHANNEL 0
DATA EQU $D800 CONVERTER DATA ADDRESS
*
*
*
START STA STATUS SELECT CHANNEL 0 AND START
STA STATUS DO AGAIN TO LET INPUTS SETTLE
LDX ÝVECTOR LOAD INTERRUPT VECTOR ADDRESS
STX $FFF8 STORE IT
ÐÐ EXECUTE MISC PROGRAM
ÐÐ
ÐÐ
CLI ENABLE INTERRUPT IF NOT ALREADY
ÐÐ EXECUTE MISC PROGRAM
WAI WAIT FOR INTERRUPT
*
*INTERRUPT HANDLER (FIGURE 18)
*
VECTOR LDAA DATA LOAD DATA RESET INTERRUPT
CLI ENABLE INTERRUPTS (OPTION)
ÐÐ EXECUTE PROGRAM
RTI RETURN TO MAIN PROGRAM
*
*START AND TEST CONVERSION POLLED MODE (FIGURE 19)
*
DATA2 EQU $F800 CONVERTER DATA ADDRESS
CHANN2 EQU 02 CHANNEL 2 ADDRESS
EOCIN EQU $F900 EOC INPUT PORT
START2 LDAA CHANN2 LOAD A ACCUMULATOR
STAA STATUS LOAD ADDRESS AND START
N0P WAIT
STAA STATUS RESTART TO LET MUX SETTLE
N0P 8 N0PS TO WAIT FOR EOC
ÐÐ TO GO LOW
LDAA EOCIN LOAD EOC STATUS BIT
ANDA 01 MASK BITS 1 – 7
BEQ READY IF A e 0 THEN CONVERTER DONE
*
*
ÐÐ EXECUTE MISC PROGRAM
*
*CONTINUOUS POLLING OF EOC (FIGURE 19)
*
*
POLLIT LDAA EOCIN LOAD EOC STATUS
ANDA CHANN2 MASK MSBs
BNE POLL IT IT ACC i 0 NOT READY, LOOP
READY LDAA DATA ELSE READ DATA
ÐÐ CONTINUE PROGRAM
ÐÐ

FIGURE 20. Typical I/O Routines for ADC0808/ADC0809 and 6800 Interface

14
 4.0 CONCLUSION
Figure 21 shows a very simple Z80 interface, which is simi- Both the ADC0808 and the ADC0809 can be easily used in
lar to the INS8080 interface of Figure 13 , except that the microprocessor controlled environments. Many sophisticat-
interrupt flip-flop design is closer to the 6800 designs. This ed medium throughput applications can be handled with a
is because the Z80 INT is active low as is the 6800, but the minimum of extra hardware, but additional hardware can in-
INS8080 INT is active high. crease flexibility and simplify software. Putting both the mul-
Figure 22 shows a fully decoded bus comparator design tiplexer and A/D on the same chip frees the designer from
where the DM8131 decodes 5 address bits and the IOREQ matching multiplexers and A/Ds to implement a 7 or 8-bit
I/O request strobe. Two NOR gates gate the RD and WR accurate system. Design time and overall system cost can
strobes for ALE, START and OE inputs. be reduced by using these low cost converters.

TL/H/5623 – 13
FIGURE 21. Simple Z80 Interface

15
 Converters with 8-Channel Analog Multiplexer
Using the ADC0808/ADC0809 8-Bit mP Compatible A/D

TL/H/5623 – 14
FIGURE 22. Z80 Partial Decoding Interface
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