I C Timer Cookbook
I C Timer Cookbook
I C Timer Cookbook
IC TIMER COOKBOOK
by
Walter G. Jung
FIRST EDITION
THIRD PRINTING-1978
Before the 555 timer was introduced in 1972, most monostable and
astable RC timing circuits were designed from the ground up, using
either discrete semiconductors or ICs as the active elements. The
advent of the 555 has changed all of that, making timer designs for
most applications a simple hookup of four to five low-cost compo-
nents. Currently, a 555 (or one of its derivatives) can satisfy about
75% or more of timing requirements with precision, simplicity, and
low cost.
Although nothing was revolutionary in its basic concept or the-
ory, the 555 caught on very quickly after its introduction. Perhaps it
was just an IC idea whose time had come in terms of getting the
right ingredients into a single chip. Nevertheless, its popularity is
probably rivaled by no other linear circuit (with the exception of the
op amp), and circuit designers are continually producing new and
previously undocumented uses for it.
Success, of course, spawns growth in even greater dimensions; the
IC timer idea soon became available in duals, then in more sophisti-
cated and wide-range versions, and also in timer/ counter combina-
tions. This book discusses all of these types of timers, using repre-
sentative industry standard devices as examples.
Today the IC timer is king of virtually all RC-timer applications
with periods greater than 10 µs, and timing periods can readily be
extended into days, weeks, or even months, if desired. The devices
are available from many sources, they are versatile, easy to design
with, easily programmed or controlled, and interface readily with
digital devices. The IC timer represents another milestone of prog-
ress in solid-state electronics, and is certainly a tool from which we
can all benefit.
Some of the circuits contained in this book have been published
previously. In these cases, a specific reference is given accompanying
the discussion. The author gratefully acknowledges the work of the
authors who have provided the concepts discussed. A general bibli-
ography of timer circuit designs is also contained in Appendix D.
WALTER G. JUNG
Acknowledgments
In the course of preparing this book, the author was aided by vari-
ous sources of information. For the use of their technical material,
the author is grateful to the following companies:
Exar Integrated Systems
lntersil, Inc.
National Semiconductor Corp.
Signetics Corp.
Also, the following industry publications were helpful in allowing
use of their copyrighted material:
Electronics
Electronic Design
EDN
The author is also grateful to the following individuals who com-
mented critically on various portions of the manuscript: Bob
Zwicker and Alan Grebene of Exar, Bill O'Neil of Intersil, Carl Nel-
son and Bob Pease of National, and Russ Long and Ted Vaeches of
Signetics.
Finally, to my wife Anne goes a special note of thanks for the
typing of the manuscript. Thanks also to my research assistants,
Jeannie and Mark.
W.G.J.
To Mom
Contents
Part I-Introducing the IC Timer
CHAPTER
RC TIMER BASICS . 11
1.1 The Monostable RC Timer 11
1.2 The Astable RC Timer 14
CHAPTER 2
IC TIMER TYPES 19
2.1 The 555 Single-Unit General-Purpose Timer 19
2.2 The 556 Dual-Unit General-Purpose Timer 33
2.3 The 322 and 3905 Wide-Range, Precision,
Monostable Timers 36
2.4 The 2240, 2250, and 8260 Programmable Timer/Counters . 46
CHAPTER 3
GENERAL OPERATING PROCEDURES AND
PRECAUTIONS IN USING IC TIMERS . 63
3.1 Standard Pinouts and Terminal Designations 63
3.2 Timing Component Considerations 65
3.3 General Design Precautions 70
3.4 Peripheral Devices 71
Part Ill-Appendixes
APPENDIX A
MANUFACTURERS' DATA SHEETS . . 239
APPENDIX B
SECOND-SOURCE GUIDE . . 267
APPENDIX C
TIMING COMPONENT MANUFACTURERS . 271
APPENDIX D
BIBLIOGRAPHY OF IC TIMER DESIGN IDEAS 275
INDEX 281
I
RC Timer Basics
11
Trigger
v+* Input
R*
'
1---------0 Output
Threshold/
µ---------
51 Control Timing Diagram
Timing ~th*
Ramp
I I
I I
I I
Output _J--L
*General timing expression: I I
:.__ T*_:
_ I (Y-V;)
T - R, C, og, V -V
I I
c th
Fig. 1-1. Block diagram illustrating the basic operation of a monostable RC timer.
12
v+ Trigger
----------------- ---1I
I
I
I
R*1 I
I
I
R*
I
Control
I
I
Flip-Flop I
>o---o~ Output
R2*
C*
I
*If R2 = 2R 1,
V,h = 2/3V+.
Then,
T = R, C, log, ( l _ 1213 )
= R,C,log,3
= l.lR,C,.
Fig. 1-2. Circuit implementation of the basic monostable RC timer.
13
or
T =RtCtlo~3
= l.0986RtCt.
We can then round this off to T = l.lRtCt, which is the basic equa-
tion for the period of a monostable timer having a threshold voltage
that is 2/ 3 of the charging voltage.
One interesting thing to note about this type of circuit is that the
period is not dependent upon the absolute level of V +, because Vth
is derived as a fraction of V +. Mathematically speaking, it can be
said that the V + term divides out. Electrically speaking, it can be
said that the capacitor is both charged from and compared to a fixed
fraction of the same voltage. Either way it is an important advantage
(as we will soon see) to have a basic timing equation that does not
critically depend upon the supply voltage.
v+
R,
~
I Output
I-f,- - - -
Threshold/ i--------ci
Output h_f--D
I I I
_...: tl :_:
Timing Expression (t 1 or t 2 ) :
: ~t2
(v -v)
I I
t=R Clog _c_ _; I I
14
At the beginning, assume switch Si to be open. In this state, the
output will be high and capacitor Ct will charge toward V + through
resistors Rta and Rtb. This portion of the cycle is somewhat similar
to that described previously in the case of the monostable timer.
When the timing ramp across Ct reaches the voltage level of Vth+,
the circuit changes states. The output now goes low, which causes
switch Si to close. With Si closed, the Rta -Rtb node is grounded,
which places Rtb in parallel with Ct, and effectively removes R ta
from the circuit. Ct now begins to discharge through Rtb , and the
timing ramp decays exponentially toward ground. When the voltage
across Ct reaches the lower threshold of Vth-, the circuit once again
will revert to its high output state, with Si opening and Ct charging
toward v+.
The circuit will continue to oscillate between the two threshold
voltage points of Vt11+ and Vu1_, with the output changing state with
each threshold crossing. Referring to the timing diagram in Fig. 1-3,
the positive-going timing period is termed ti, and the output is high
during this period. The negative-going timing period is t2, and the
output is low during this period. The total timing period of a single
cycle is called T, which is simply the sum of the individual timing
periods, ti and t 2. For each of the two timing periods, the general
expression will again be
t = RtCtlOge ( ~c ~ ~:J .
A circuit implementation of this astable timer is illustrated in Fig.
1-4. Here we note that there are two comparators, the upper comp
and the lower comp. These comparators establish the two threshold
voltages, Vt11+ and Vth-, as the fractions of V+ determined by the
divider resistor string, Ri-R 2-R3 • The upper comp is referenced to
the higher voltage, Vth+. The lower comp is referenced to the lower
voltage, Vth-· Transistor Q 1 perfmms a function similar to that of
switch Si in Fig. 1-3, while the control flip-flop drives Q 1 and the
output buffer as directed by the comparator inputs.
In operation, the circuit performs just as described for Fig. 1-3,
with an output and timing ramp in accordance with the timing dia-
gram. The voltage across Ct is made to oscillate between the two
comparator thresholds, Vu1+ and Vth-· Rt" + Rtb and Ct control tim-
ing period ti, while Rtb and Ct control timing period t2. The general
timing expression for either of these periods is as noted in Fig. 1-3.
=
In this case, with comparator thresholds Vu1+ 2/3V+ and Vth- =
l/3V, the equations for ti and t 2 are as follows:
For ti, the voltage across Ct starts at a voltage of Vu1- (which is
Vt), charges toward V+ (which is Ve), and reaches its upper limit
atVth+· Then,
15
v+
r----
1
---------------- ---------------- --, I
I I
I I
I
I : Output
I
I
Control
Flip-Flop
DF
{•1 l
=.!J..
T
R,a + R.b
R, 0 + 2R, b
V,h- = l/3V+
2/3)
t I = (Rt a + Rt b ) Ct log. ( 1/3
= (R, a + R b) C log 2
1 1 0
t2 = R,b C, log.(=~~~)
=R,bC,log 0 2
= 0.693R, b c I
T=t 1 +t 2
= 0.693 (R,
a
+ 2R, b
) C,
- (R
ti - t. +
R )C l
tb
(( V+) - V
t oge ( v+) - vth+ .
th-)
With Vth+ and Vth- as fractions of V+ as noted, this may be written
as
16
which reduces to
ti= (Rta + Rtb) Ct logf 2
= 0.693 ( Rta + Rtb) Ct.
For t 2, the equations are similar:
which simplifies to
-2/3V+)
t2 = Rt11 Ct logf ( -l/ 3V +
= Rtb Ct logf 2
= 0.693 Rt11 Ct.
The total period, T, is simply the sum of periods ti and t2, or
T =ti+ t2
=
0.693 ( Rta + RtJ Ct + 0.693 Rtb Ct
=
0.693 (Rt. + 2Rtb) Ct.
Since time and frequency are related reciprocally, we can now
also write an equation for the operating frequency, f:
1
f =T
1
0.693 (Rt. + 2Rt") Ct
1.44
(Rt,.+ 2RtJ Ct.
The ratio of the individual periods (ti or t 2 ) to the total period is
called the duty factor, DF. With respect to period ti, the duty factor
is
ti
DF<t)1 =-
T
Rt + Rt11
3
Rta + 2Rt11
and for period t 2 , the duty factor is
t2
DF<tl=-
~ T
17
In summary, there are a number of important features that charac-
terize the astable RC timer. The timing period is governed by Ct and
resistors Rt,. and Rtb, as is the operating frequency. The duty cycle
is controlled by the ratio of timing resistors. And, for this type of
timer as well as for the monostable, the timing period is independent
of the supply voltage.
What has been described in this chapter is a concept that allows
(in theory at least) a very simple and predictable form of mono-
stable and/ or astable timer design based only on R and C values to
define operation. With this groundwork, we are now ready to exam-
ine IC timer types and their modes of operation.
18
2
IC Timer Types
19
v+
8
------------------------------------,
v+ :
I
I
I
I
Control I
Voltage I
Threshold 6
Control
Flip-Flop
01s·01e
2VBE
(Internal Reference,
Latch Input)
Reset 4 0 - - - 4 : ' - - - - - - - 4
Discharge 7 o-~--......
I
I
I
I
I
I
I
IL _____ _
Ground
In Fig. 2-1, note the resistive divider string across the V+ line
comprising equal-value resistors R 7 , R 8 , and R 9 • This voltage divider
provides the reference voltages for the upper and lower comparators
of 2/ 3V + and 1/ 3V +, respectively. In the schematic~ of Fig. 2-2,
this divider may also be noted, biasing Q4 and Q 13 • Transistors
Q1-Q8 make up the upper comparator, while Q10-Q 13 form the lower
comparator. In both comparators, Darlington differential input
stages are used for low ( 100 nA) input currents, which in turn al-
lows a wide range of (external) timing resistor values to be used.
The upper comparator point of 2/ 3V + is brought outside the IC
package (via pin 5) to allow external control of the timing period
( when desired) .
0
Some variation in internal circuitry is evident between different manufac-
turers of 555 devices; therefore, reference designations and exact circuit details
may vary from that shown here when compared with a given data sheet.
20
8
v+o-~---~~~---<1~~~~..--~~~--~~~~~~--~~~~~~...-~~--~~--~---.
R3 ~ R"
4.7kn ~ l kn
Q9
R,
5kn
:n
cp I r R,o
~
n
"'
:r
•g
!!. Control 5
;;· Voltage
0
...;. Ra I CIs
~~ ~"'P"I
•
UI 2 5kn O,a t
UI Trigger E
UI
i• -(a,, I
4 R14
~ Reset o ~ Q25 "Nv-{ 024
7 220 n
Discharge
Q,5 I I R,6
Rs
R lOOn R
R6 9
lOkn lOOkn 5 kn J l L:; kn
Ground
J=
~
The two comparator outputs are taken from transistors Q6 and
Q10-Q11; these in turn are fed to the control flip-flop, which is a latch
formed by Qrn-Q1 7 ( Qis is an additional input whose function will
be described shortly). In operation, a low input to the trigger pin
(base of Q 10 ) causes a positive-going output from Q 10-Q 11 . This
causes the latch to be set by pulling the collector of Q 15 low. This
then causes Qi 7 (and the input to Q20 and Q24) to also go low, and
the output (pin 3) to go high. This set condition of the latch will
remain until the circuit is reset.
To reset the flip-flop back to its original state, either of two condi-
tions can be satisfied. If the output of Q 6 goes high, the latch will be
reset via the input to the base of Q16, removing drive from Q17 • The
latch may also be reset by taking the base of Q25 low, via the reset
input (pin 4). This removes base drive from Qi 7 by biasing diode-
connected Q18 "off." Regardless of the method, the reset state turns
Q20 (and Q24 ) "on" once again, causing an output-low condition.
The output stage formed by Q 20-Q 24 is a totem-pole design, which
has the virtue of being a high current drive for either source or sink
22
loads. This design is a versatile one, as it can readily drive TTL in-
puts with a chip supply of 5 volts, yet it can also sink or source 200
mA when operated from 15 volts. A photomicrograph of the 555 sili-
con chip layout is shown in Fig. 2-3.
2. 1.2 Definition of Pin Functions
As an aid to understanding the 555 more completely, this section
provides a short description of the functional characteristics of each
pin. This not only will serve as an aid to understanding the use of
the 555 as a timer, but will also greatly facilitate its use in some of
the more imaginative nontimer uses of which it is capable. To am-
plify this discussion, the reader is referred to the 555 data sheet re-
produced in Appendix A.
V+ (Pin 8)
The V + pin (referred to as Vee by some manufacturers) is the
positive supply voltage terminal of the device. Supply-voltage oper-
ating range for the 555 is +4.5 volts (minimum) to + 16 volts (maxi-
mum), and it is specified for operation between +5 volts and + 15
volts. The device will operate essentially the same over this range of
voltages without change in timing period. Actually, the most signifi-
cant operational difference is the output drive capability, which in-
creases for both current and voltage range as the supply voltage is
increased. Sensitivity of time interval to supply voltage change is
low, typically 0.1 % per volt.
Ground ( Pin 1 )
The ground (or common) pin is the most-negative supply poten-
tial of the device, which is normally connected to circuit common
when operated from positive supply voltages.
Output (Pin 3)
The output of the 555 comes from a high-current totem-pole
stage made up of transistors Q20-Q2.i· Transistors Q 21 and Q 22 pro-
vide drive for source-type loads, and their Darlington connection
provides a high-state output voltage about 1.7 volts less than the V +
supply level used. Transistor Q 2 4 provides current-sinking capability
for low-state loads referred to V + (such as typical TTL inputs).
Transistor Q2 4 has a low saturation voltage, which allows it to inter-
face directly, with good noise margin, when driving current-sinking
logic. Exact output saturation levels vary markedly with supply volt-
age, however, for both high and low states. At a V + of 5 volts, for
instance, the low state VcE <sat) is typically 0.25 volt at 5 mA. Oper-
ating at 15 volts, however, it can sink 100 mA if an output-low volt-
age level of 2 volts is allowable (power dissipation should be con-
23
sidered in such a case, of course). High-state level is typically 3.3
volts at V + = 5 volts; 13.3 volts at V + = 15 volts. Both the rise and
fall times of the output waveform are quite fast, typical switching
times being 100 ns.
The state of the output pin will always reflect the inverse of the
logic state of the latch, and this fact may be seen by examining Fig.
2-1 (or Fig. 2-2). Since the latch itself is not directly accessible, this
relationship may be best explained in terms of latch-input trigger
conditions. To trigger the output to a high condition, the trigger in-
put is momentarily taken from a higher to a lower level. [The exact
voltage levels are discussed under "Trigger (Pin 2) ."] This causes
the latch to be set and the output to go high. Actuation of the lower
comparator is the only manner in which the output can be placed
in the high state. The output can be returned to a low state by caus-
ing the threshold to go from a lower to a higher level [exact levels
are discussed under "Threshold (Pin 6)"], which resets the latch.
The output can also be made to go low by taking the reset to a low
state near ground [exact levels are discussed under "Reset (Pin 4 )"].
24
One precaution that should be observed with the trigger input
signal is that it must not remain lower than 1/3V + for a period of
time longer than the timing cycle. If this is allowed to happen, the
timer will retrigger itself upon termination of the first output pulse.
Thus, when the timer is driven in the monostable mode with input
pulses longer than the desired output pulse width, the input trigger
should effectively be shortened by differentiation.
The minimum-allowable pulse width for triggering is somewhat
dependent upon pulse level, but in general if it is greater than 1 µs,
triggering will be reliable (see data sheet in Appendix A).
A second precaution with respect to the trigger input concerns
storage time in the lower comparator. This portion of the circuit can
exhibit normal turn-off delays of several microseconds after trigger-
ing; that is, the latch can still have a trigger input for this period of
time after the trigger pulse. In practice, this means the minimum
monostable output pulse width should be on the order of 10 µs to
prevent possible double triggering due to this effect.
The voltage range that can safely be applied to the trigger pin is
between V + and ground. A de current, termed the trigger current,
must also flow from this terminal into the external circuit. This cur-
rent is typically 500 nA and will define the upper limit of resistance
allowable from pin 2 to ground. For an astable configuration operat-
ing at V + = 5 volts, this resistance is 3 Mn; it can be greater for
higher V + levels.
Threshold ( Pin 6 )
This pin is one input to the upper comparator (the other being
pin 5) and is used to reset the latch, which causes the output to go
low. Resetting via this terminal is accomplished by taking the termi-
nal from below to above a voltage level of 2/3V+ (the normal volt-
age on pin 5). The action of the threshold pin is level sensitive,
allowing slow rate-of-change waveforms.
The voltage range that can safely be applied to the threshold pin
is between V + and ground. A de current, termed the threshold cur-
rent, must also flow into this terminal from the external circuit. This
current is typically 100 nA, and will define the upper limit of total
resistance allowable from pin 6 to V +. For either timing configura-
tion operating at V+ = 5 volts, this resistance is 16 Mn.
Reset ( Pin 4)
This pin is also used to reset the latch and return the output to a
low state. The reset voltage threshold level is 0.7 volt, and a sink
current of 0.1 mA from this pin is required to reset the device. These
levels are relatively independent of operating V+ level; thus the
reset input is TTL compatible for any supply voltage.
25
The reset input is an overriding function; that is, it will force the
output to a low state regardless of the state of either of the other
inputs. It may thus be used to terminate an output pulse prema-
turely, to gate oscillations from "on" to "off," etc. Delay time from
reset to output is typically on the order of 0.5 µs, and the minimum
reset pulse width is 0.5 µs. Neither of these figures are guaranteed,
however, and may vary from one manufacturer to another. When
not used, it is recommended that the reset input be tied to V + to
avoid any possibility of false resetting.
Discharge ( Pin 7 )
This pin is the open collector of an npn transistor ( Q14 , Fig. 2-2),
the emitter of which goes to ground. The conduction state of this
transistor is identical in timing to that of the output stage. It is "on"
(low resistance to ground) when the output is low and "off" (high
resistance to ground) when the output is high.
In both the monostable and astable timer modes, this transistor
switch is used to clamp the appropriate nodes of the timing network
to ground. Saturation voltage is typically below 100 m V for currents
of 5 mA or less, and off-state leakage is about 20 nA (these parame-
ters are not specified by all manufacturers, however).
Maximum collector current is internally limited by design, thereby
removing restrictions on capacitor size due to peak pulse-current
discharge. In certain applications, this open collector output can be
used as an auxiliary output terminal, with current-sinking capability
similar to the output (pin 3).
2. 1.3 Basic Operating Modes
With the definition and functional description of the 555 timer just
completed, we have now reached a point where the basic modes of
operation of the device can be discussed in more detail. In essence,
this amounts to only two modes: the monostable (or one-shot) mode
and the astable (or free-running) mode. Both of these modes of op-
eration have been discussed at length in conceptual terms; this sec-
tion relates the practical operating points of the 555 to the previous
material.
The two basic operating modes have a great number of variations;
these are treated as specific design examples within the applications
section (Part II). The 555, being such a versatile device, also has a
virtually limitless number of possible operating options not neces-
sarily directly related to the monostable and astable modes. These
are much more difficult to categorize, but they will also in some way
be dependent upon the internal structure just described. These more
esoteric operating modes are also treated as specific design examples
in the applications section.
26
v+ (+5v to +15V)
Timing Diagram
Trigger :-::i. _ ..r:==--::--
--c.r-------- l ; 3 v+
ln put
4 8 C, Voltag~-- 2 i 3 v+
R.* I --0
6
Reset v+
Output r----, ---- =V+
Threshold ~ ~--0
~ T* 14---
3
l_f 555
Output
2
Trigger Trigger
Input
Control 5
Voltage
7
Discharge
Ground c1
C,* 0.01 µ.F
Fig. 2-4. The 555 timer connected as a triggered monostable-its most basic mode
of operation.
Monostable Mode
In Fig. 2-4, the 555 is shown connected in its most basic mode of
operation-as a triggered monostable. One immediate observation to
be made is the utter simplicity of this circuit; it consists of only the
two timing components, Rt and Ct; the timer itself; and bypass ca-
pacitor C 1 ( C 1 is not absolutely essential for operation but is recom-
mended for noise immunity).
When the trigger input terminal is held higher than l/3V +, the
timer is in its standby state and the output is low. When a trigger
pulse appears with a level less than l/3V+, the timer is triggered
and starts its timing cycle. The output rises to a high level near V+;
at the same time Ct begins to charge toward V +. When the Ct volt-
age crosses 2/3V+, the timing period ends with the output falling
once again to zero, ready for another input trigger. This action is
graphically illustrated in the timing diagram of Fig. 2-4.
In this most simple circuit it should be noted that there are no
trigger input conditioning components used. The implication of this
is that the driving source in itself must be capable of satisfying the
trigger voltage requirements. If the timer is operated from +5 volts
in a TTL system, for instance, the input drive will automatically be
TTL compatible since l/3V + = 1.6 volts, which is centered in the
27
TTL output swing. Under this type of condition there are no restric-
tions on the input pulse, other than that it have a width of less than
T. (Other forms of drive can be dealt with also, and will be covered
later.) Due to the internal latching mechanism, the timer will always
time out once triggered, regardless of any subsequent noise (such as
bounce) on the input trigger. This factor is a great asset in inter-
facing the 555 with noisy sources.
The output pulse width is defined as l.lRtCt, and with relatively
few restrictions, Rt and Ct can have a wide range of values. There
is actually no theoretical upper limit on T, only practical ones. The
lower limit is 10 µs. You may then consider the range of T to be
10 µs to infinity, bounded only by R and C limits. Techniques cov-
ered in a later section of this chapter will illustrate how T can be
effectively multiplied by virtually any number to achieve periods of
days, weeks, and even months if desired.
A reasonable lower limit for Rt is on the order of 10 kn, mainly
from the standpoint of power economy. (Although Rt can be lower
than 10 kn without harm, there is no need for this from the stand-
point of achieving a short pulse width.) A practical minimum for Ct
is about 100 pF; below this the effects of stray capacitance become
noticeable, limiting accuracy and predictability. Since it is obvious
that the product of these two minimums yields a T that is less than
10 µ,s, there is much flexibility in the selection of Rt and Ct. Usually
Ct is selected first to minimize size ( and expense); then Rt is chosen.
The upper limit for Rt is on the order of 13 Mn but should be less
than this if all of the accuracy of which the 555 is capable is to be
achieved. The absolute upper limit of Rt is determined by the thresh-
old current plus the discharge leakage when the operating voltage
is +5 volts. For example, with a threshold plus leakage current of
120 nA, this gives a maximum value of 14 Mn for Rt (even this value
may be optimistic). Also, if the Ct leakage current is such that the
sum of the threshold current and the leakage current is in excess of
120 nA, the circuit will never time out because the upper threshold
voltage will not be reached. Therefore, it is good practice to select
a value for Rt so that, with a voltage drop of 1/ 3V + across it, the
current through it will be much larger than the threshold current
plus total leakage currents. This current value should be at least 10
times the threshold current plus leakage current. For best accuracy,
the value should be 100 times more, if practical.
From the preceding, it should be obvious that the real limit to be
placed on Ct is its leakage, not its capacitance value. In practice,
however, this becomes one of capacitance value, since larger-value
capacitors have higher leakages as a fact of life. Low-leakage types
are available in values up to about 10 µF, however, and are pre-
ferred for long timing periods. If low-leakage units higher than this
28
can be found, there is no limit from a circuit standpoint to using
them, even up to 1000 µF.
The ultimate criterion of the components selected for Rt and Ct
is the degree of accuracy desired (or expected). In general, the
selection of Rt and Ct is not a trivial task because the inherent preci-
sion of the 555 is better than that of most resistors and capacitors.
A detailed discussion of the selection rationale for timing compo-
nents is taken up in Chapter 3, and this should be carefully studied
before designs are attempted.
As previously mentioned, input trigger source conditions can exist
that will necessitate some type of signal conditioning to ensure com-
patibility with the triggering requirements of the 555. One example
of such a conditioning circuit is shown in Fig. 2-5. Here, input com-
ponents C 1, Ri, and D 1 have been added, for two reasons. C 1 and R 1
form a pulse differentiator to shorten the input trigger pulse to a
width less than 10 µs (in general, less than T). Their values (and
relative quality) are not critical; the main criterion is that the width
of the resulting differentiated pulse (after C1) should be less than
the desired output pulse for the period of time it is below the l/3V+
trigger level. This effect is shown in the waveform sketch in Fig. 2-5.
The pulse as it exists at the R 1-C 1 junction will rest quiescently
at the base line of V +, since R 1 is referred to V +. Therefore, the
positive-going edge of the pulse would result in a voltage rise above
V +, were it not for D 1 • Diode D 1 is simply a switching diode con-
nected to clamp positive excursions to the V+ level. This circuit will
V+ (+5V to+ 15V)
R1 R, 4 8
10 k!l Reset v+
D1 1N914 6
Threshold
7
3
Output t - - - - - - - o Output
c1 555
;;:,~" 'r1
2
Trigger
1000 pF
Control 5
L_J
I I
7
Voltage
I I Discharge
II ' \
I
c2
I I \ Ground
After~--v+ 0.01 µF
c,
C1 - - - - - - - - - - 1 /3V+
29
operate satisfactorily if the input pulse has the same amplitude as
V + and has a fast fall time.
Some further refinement of the input trigger circuit may be neces-
sary if the input pulse has a peak amplitude that is less than the 555
supply voltage. For example, the circuit of Fig. 2-5 will not work
when driven from a 5-volt TTL source with a timer V + of 15 volts,
since the 5-volt p-p amplitude is less than 2/3V + ( 10 volts). In this
type of situation, the trigger input can be biased to a level closer to
the 1/ 3V + threshold, thus increasing sensitivity. Fig. 2-6 illustrates
this solution to the problem. Here, resistor R 2 has been added to the
previously described differentiator, forming a voltage divider that
will have a de base line of l/2V +. This biases the trigger input at
this level; therefore, the amplitude of the trigger pulse need only be
the difference in this de level and l/3V+, or simply l/6V+. In the
example mentioned, a 5-volt TTL source with a timer V + of 15 volts,
will work satisfactorily, as the 5-volt p-p amplitude is greater than
1/6 of 15 volts. The exact R 1-R 2 bias level used is not critical and
may be adjusted to suit differing input requirements.
Astable Mode
The 555 connected as an astable timer is diagrammed in Fig. 2-7.
This circuit also uses a minimum number of parts: the three timing
components-Rt. , Rtb, and Ct; the timer itself; and bypass capacitor
C 1 • Upon startup, the voltage across Ct will be low, which causes
~----0 Output
Fig. 2-6. The addition of R2 improves the sensitivity of the input trigger
conditioning circuit.
30
the timer to be triggered via pin 2. This forces the output high, turn-
ing off the discharge transistor and providing a current path for
charging Ct via Rta and Rt". Ct charges toward V+ until the voltage
reaches a level of 2/ 3V +, whereupon the upper threshold is reached,
causing the output to go low. Capacitor Ct then discharges toward
ground via Rt" until its voltage reaches l/3V+, the lower trigger
point. This triggers the timer once again, beginning a new cycle.
The timer then continues to oscillate between the 2/3V+ and l/3V+
comparator threshold levels, forming a triangular timing ramp. The
_J--i_j--[_-== ~v+
I I I
Rta * 4 8
Reset v+ Output
I I I
Threshold ~ tl* :.. :
R * Output
3
t-- - - - u Output
l
1
f-f--t2*
1
'b I I
555 .._T*----4
I I
2
- - - --1 Trigger
*Output Timing
Control 5
Voltage t1 = 0.693 (R + R,b) C,
10
7
Discharge
t2 = 0.693 R,b C,
DF - R,b
(121-R,a +2R,b
time duration of the high output period is ti, and the low output
period is t 2 • Their sum is the total period, T. The frequency of oper-
ation is simply the reciprocal of T. The duty factor for either the high
or low output state is simply that period divided by the total period.
Operating restrictions of the astable mode are few, and some are
similar to monostable operation. The upper frequency limit is on the
order of 100 kHz for reliable operation, due to internal storage times.
There is no theoretical limit on the lower frequency, only that im-
posed by Rt and Ct limitations.
The limits on Ct are identical to those in the monostable mode.
The maximum value of Rt. + Rtb is the same as that for Rt of the
31
monostable, as they are functionally equivalent. This limit is 14 Mfi
or less.
Many applications may demand specific duty factors, which can
be programmed (within limits) by the ratios of Rt a and Rt b . As Rtb
becomes large with respect to Rt,. , the duty factor approaches 50%
(or square-wave operation), which can be noted from the duty
factor expression. Conversely, as Rt,. becomes large with respect
to Rtb, the duty factor increases toward unity ( 100%) as Rtb ap-
proaches zero. 0 Rtb must not be allowed to reach zero, however.
The practical range of duty factors, therefore, is from nearly 50%
to about 99%; or, in terms of Rt" -Rtb ratios, Rtb may be 1/ 100
of Rt a . There is no limit to what fraction Rt a may be of Rtb , except
for the absolute value restrictions. If Rt,. is to be a very small frac-
tion of Rtb, its value can be as low as 1 kfi, if desired, the ultimate
limit being power dissipation.
There are a multitude of variations that can be applied to this
astable circuit, but it is shown here in its simplest form. The varia-
tions will be covered in a special section of the applications portion
of the book ( Part II ) .
2. 1.4 Specifications
A brief discussion of the performance specifications of the 555 is
appropriate at this point in order to bring the overall operating capa-
bilities of the device into proper perspective.
Although the 555 is basically a simple and low-cost device, it is
capable of an unusual degree of accuracy. Its performance capabili-
ties are, in fact, such that it can be used in all but the most sophisti-
cated of applications. This discussion covers only the highlights of
its performance; the detailed specifications are contained in Appen-
dix A. The specifications discussed here are in terms of commercial
( 0°C to +70°C) devices, as are the application discussions through-
out the book for all devices.
First of all, consider the basic accuracy of the 555 in terms of the
fundamental monostable timing expression, T = l.lRtCt. There is a
typical initial error of only 1% due to timer imperfections (Rt and
Ct tolerance errors must be considered separately). For astable
operation the error is somewhat greater, typically about 2% (this
parameter is not specified by all 555 manufacturers, however).
Drift with temperature is typically only 50 ppm/ °C (or 0.005% /
°C) for the monostable mode. Drift in the astable mode, like the
initial accuracy, is somewhat greater, or about 150 ppm/ °C (not
0
This definition of duty factor is based on the ratio of output high time (true
in a logical sense) which is t1, to total time, T.
32
specified by all manufacturers). These parameters apply for opera-
tion at a V + of both +5 volts and + 15 volts.
The drift with supply voltage, by design ideally zero, does have
an error coefficient due to device limitations. This is typically 0.1 %
of timing error per volt of supply voltage change, which is still quite
small.
The output-current drive capability has already been mentioned;
i.e., the ability to drive both sink and source loads of up to 200 mA,
and TTL compatibility when operated from 5 volts.
The input trigger and timing nodes are operable at low currents,
which permits a wide range of timing resistor values. In addition, the
reset function is available and it is also TTL compatible.
Finally, the device consumes a moderate amount of power, rang-
ing from 3 mA at 5 volts to 10 mA at 1.5 volts (exclusive of load
current).
~fany of the specifications and performance features of the 5.55
have carried over to other similar timers; thus they are obviously
well accepted. This is specifically reflected in the next device to be
discussed-the 556.
33
v+(14)
r--
1 I
I I
I
Control : I
Voltage I I
I
(3, 1 l)C>-------1 1 Output
1 ><>----() (5, 9)
Threshold
C>---+---1
(2, 12) I Control
Output
I Flip-Flop
I 5 kn Stage
I
I
I
I
Trigger 1
u------1
(6, 8) I
I
I
I 5kn
I
1
Reset
(4,10)
1
Discharge
(1,13) 0,-+-------...
t----+------~
I
I
I
I
l__________ --~-------------------------~
Ground (7)
Fig. 2-8. Functional block diagram of the 556 dual timer (one-half of circuit shown).
34
""'O
+-;;;:- oN' Ol -;::-
Q) Q;
-ro ~ 0
Q)
""'O
>::.. ..s::
:UN
~
] .E
Ol
01~
.... (") c
:::> ,..._
c
0 0 c-i
Ol
~ ~
Q)
~ ± 0 0
J:~
I- u > ~ ~ (5
0
Fig. 2-9. Schematic of the 556 dual timer (one-half of circuit shown).
35
Courtesy Signetics Corp.
Fig. 2-10. Photomicrograph of the 556 silicon chip.
36
ficed, however, was that of astable operation, as both the 322 and
3905 are basically monostable timers. Thus, although both the 322
and 3905 possess the technical performance that justifies the term
precision timers, they are not completely general purpose in the
same sense as the 555 and 556 devices are.
The 322 is available in either a 10-pin T0-5 style metal-can pack-
age, or in a 14-pin dual in-line plastic package (DIP), while the
3905 is available in an 8-pin dual in-line ( MINIDIP) plastic
package.
37
w
CD
l! (10,5)
~ Boost (11)* v+
~ r---------------
1
-----------------,
I
v+ o •
I
.....,
c I
:a Voltage Voltage
I 3.15 V
Reference Regulator
I
a·:a~
(4,2) I
R16 Oia-028
!!:. __J I
er I 4kn I
RlS
I
0... Voltage* : 20kn I
Adjust (7)~r--'--- I
a.
""" 1
iii' Output Collector
ca R/C
QI Stage I (12, 6)
(5,3) Control
3 --
Exclusive- Emitter
0 Flip-Flop 032-036
... oR Gate I (1,7)
Ri7
;. 04, 06 Oa-09
I
•w..., 6.9kn
Trigger
~ (3,1)
:g Trigger Amp
,,8; 02-03
01
a~
s·
:a
3 Logic
0
:a (2,8)
0 I
I =
•I
DI
I
=-er
L_
i" -~------------------------------------------------------J
Ground
..a·
(6,4) *Not available with the 3905.
!"
=
latch does not simply yield a high output, as in 555-type timers, for
two reasons. The first of these is an exclusive-OR gate, which has as
its two inputs the latch output and the logic input pin. The function
of this gate is to control the relative on/ off state of the output stage
by the logic input. When the logic pin is low, the output stage is
"on" during the timing cycle and is "off" otherwise. When the logic
pin is high, the output stage is "off" during the timing cycle and is
"on" otherwise.
The output stage is equivalent to a floating npn power transistor,
and both collector and emitter pins are brought outside the package
for external connection. Thus, the output stage can be wired in either
a common-collector or a common-emitter fashion. This composite
transistor has a voltage standoff capability of 40 volts, and it is also
current limited internally. With the flexibility that this output stage
and the gating combination possess, many different functions can be
performed.
The schematic of Fig. 2-12 illustrates the internal circuitry of the
322/ 3905. Again, the first designated pin number refers to the 322
(in the 14-pin DIP), while the second number refers to the 390.5.
The trigger input amplifier is made up of Q2 and Q3, which in turn
drive the npn/pnp latch, Q4 and Q(>· The discharge transistor, Qt, is
driven from the latch and Q 2 •
Transistors Q14-Qli form a pnp input differential comparator, and
Qu-Qrn further amplify the output of Qrn-Qrn. The· comparator is
interfaced to the latch by Q7 • It also drives the exclusive-OR gate,
Q8-QH. The boost terminal of the 322 is connected to the emitter of
Q:rn within the comparator bias circuitry. Jumpering this pin to V +
turns on Q:rn, which increases the operating current of Q 1 cQ17> and
thus the comparator speed.
Transistors Qis-Q 28 comprise the voltage regulator. The actual
regulator is Q18-Q 24 ; Q 2;, and Q26 serve as start-up components only.
The output voltage is 3.15 volts, and light external loads may be
connected.
The output stage, consisting of Q:{ 2 -Q:rn, has a "floating" base drive
supplied by Q 31 • This drive is either passed to the output or shunted
away by Q 8 (the exclusive-OR gate) to control the conduction state
of the output. ·within the output stage, Q 32 provides current limiting
at 120 mA, and Q34-Q 3 ;; serve as voltage clamps to prevent excess
storage time in Q3 A photomicrograph of the LM322 silicon chip is
(i.
39
& Collector V+ Boost*
(12,6) ( 10,5) (11)
"'t ~
! Emitter
::-. (1,7)
n
s. v,.,
;. (4,2) .--lJ R, 0
Ground ( Pins 6, 4)
This pin is the most negative supply potential of the device (nor-
mally connected to circuit common when operating from positive
supply voltages).
Collector ( Pins 12, 6 )
This output pin is the collector of the floating npn output transis-
tor. This transistor has a minimum breakdown of 40 volts and is
current-limited to 120 mA. For outputs taken from the collector, the
emitter is normally grounded. The output is taken from the collector
with a load referred to V+, or other positive voltage of 40 volts or
less.
Emitter ( Pins 1, 7)
This output pin is the emitter of the npn output transistor. For
outputs taken from the emitter, the collector is tied to V + (or other
positive voltage). The output is taken from the emitter with a load
referred to ground. The collector may be connected to a voltage
higher than V +, but the emitter will pull up (when "on") to a volt-
age somewhat less than V +.
41
Courtesy National Semiconductor Corp.
Fig. 2-13. Photomicrograph of the LM322 silicon chip.
42
timing capacitor reaches +2 volts, the comparator changes states,
ending the timing cycle.
The threshold current is typically 300 pA for the 322 operating in
the unboosted mode, and for the 3905. When the 322 is operating in
the boosted mode, the threshold current increases to 30 nA. For safe
operation, external voltages applied to the R/ C input should be be-
tween zero and +5 volts.
Trigger ( Pins 3, I )
This pin is used to start the timing cycle with a positive-going
pulse. The trigger threshold is TTL compatible, with a typical
threshold voltage of +1.6 volts. Current at threshold is 20 µA, and
the input is overvoltage protected for voltages up to ±40 volts.
The timer will not retrigger if the trigger cycle is held high during
the timing cycle but will time out. However, the timing capacitor
will not be discharged until the trigger input is lowered below the
threshold (this does not affect the output).
Logic ( Pins 2, 8 )
This pin determines the state of conduction of the output transis-
tor during the timing cycle. When the logic pin is high, the output
transistor is "off" during the timing period ("on" otherwise). When
the logic pin is low, the output transistor is "on" during the timing
period ("off" otherwise).
The logic input switching threshold is 150 mV, and 150 µA of
current must be sunk by the source in the low state. Safe voltage
applied to this pin is zero to +5 volts.
Boost (Pin 11on322; Not Available on 3905)
This pin increases the speed of the comparator when connected to
the V + pin. It is used when operating at short timing periods ( ~1.0
ms) for greater accuracy.
2.3.3 Basic Operation
The basic mode of operation for the 322/ 3905 is that of a mono-
stable timer. Astable operation can be achieved with some additional
circuitry, if desired. This section deals with the practical points of
applying the device in its basic mode.
Monostable Mode
There are two different ways that the 322/ 3905 timer can be used
in the monostable mode of operation: with the output taken from
the collector, or with the output taken from the emitter. Fig. 2-14
illustrates the collector-output option, where the emitter of the out-
put b·ansistor is connected to common (ground). RL is the load re-
43
Timing Diagram
v+
Trigger u----~
(+4.5V to +40V) Trigger ..:.fl.:.------- 1.6 V
I
I
Input I
L~~ic v+
R,*
V ,. 1
R/C
322/3905
Collector
Emitter
Output*
! to
v,.,
Logic
Ground
:
---1
I
I
~ T*~
1
L___J ----
: :
I
--
Ground
With logic low, output is low during T.
c,*
T = R,C,
R, and C, value ranges (see text):
R, : 10 kn to l 00 Mn
C,: 100 pF to 100 µF
Fig. 2-14. The 322/3905 connected in the basic monostable mode of operation, with the
output taken from the collector terminal.
44
Timing Diagram
SL v+
Trigger
(+4.5V to +40V)
Trigger _:fl=------- 1·6 V
Input I
I
C, : ~---- 2V
~*
Trigger Voltage ---Y' ~ -- OV
Logic v+ I
I
I
I
Logic 1 1 __ =V+
322/3905 to~
V ref : : - - - - 0V
Output* I I
Ground
*With logic high, output is low during T.
C,* RL With logic low, output is high during T.
T= R1 C 1
R, and ( 1
value ranges (see text):
Fig. 2-15. The 322/ 3905 connected in the basic monostable mode of operation, with the
output taken from the emitter terminal.
end of the timing range, an unboosted 322 (or 3905) can achieve
timing periods of hours or more, limited only by the timing com-
ponents.
Due to the extremely low comparator current capability of the
322/3905, the allowable range of Rt is from 10 kn to 100 Mn. The
ultimate limit is more a function of the availability of high-value
resistors. Capacitor C 1 can range from 100 pF on the low end (a
practical limit due to stray capacitance) up to 100 µF on the high
end. The real limit on Ct will also be one of availability. With the
322 and 3905 timers, the operating range is essentially unrestricted
from the standpoint of the device itself; the limitations are practical
ones set by Rt and Ct.
Astable Mode
Because these devices do not offer the capability of astable opera-
tion by themselves, this mode will not be treated in this section but
will be covered in the applications section of the book.
2.3.4 Specifications
A discussion of the specifications of the 322 and 3905 will serve to
bring their performance capability into overall focus. Of all the de-
vices discussed thus far, these two are capable of the highest degree
45
of performance and best overall accuracy, in addition to their basic
flexibility. For reference, data sheets are included in Appendix A.
Initial timing error for the 322/ 3905 is specified differently than
for 555-type devices, which simply have a lumped percentage error.
The 322/ 390.5 units break the error down into its several different
components, such as timing-ratio tolerances, Ct saturation voltage,
etc. Furthermore, some of the error is specified for a minimum and
maximum, whereas the 555 error is only specified as typical.
Timing ratio error for the 322/3905 is listed as a worst-case limit
of ±3.2%. Normally it will be much better than this and more com-
parable to the 1% 'typical of the 555. Temperature drift is listed as
30 ppm/ °C typical, which is an excellent figure. Supply-voltage
sensitivity is not listed separately but is included in the total error
for timing ratio. By itself it would be about 50 ppm/V.
Output drive capability of the 322/3905 is quite different than
that of the ;:555 devices, because of the floating transistor. The 322/
3905 can withstand voltages of 40 volts and can handle currents up
to 50 mA. Drive capability in the collector-outpu t mode is typically
0.25 volt at 8 mA; 0.7 volt at 50 mA. In the emitter-output mode,
the drive capability is 1.8 volts at 3 mA; 2.1 volts at 50 mA. A big
point in favor of the uncommitted output arrangement is the ability
to drive loads that are referred to voltages higher than V+, up to
40 volts.
Trigger voltage is typically 1.6 volts which is TTL compatible and
requires 25 µA of source current. Minimum trigger pulse width is
0.25 µs.
A significant difference between 555 devices and the 322/ 3905 is
their very low input threshold currents. For the 3905 (and the 322
unboosted) this is only 300 pA typical. For the 322 in the boosted
mode, the threshold current rises to 30 nA.
Another major point of usefulness for the 322/3905 is the 3.15-volt
reference output. Although this voltage has no influence on the tim-
ing accuracy, it has a specified tolerance of ±5% and good regula-
tion. This feature can be a valuable asset in system design.
The 2240, 2250, and 8260 are three different types of devices which
fall into a special class of timer I Cs-that of programmable timer/
counters. These units include a timing section made up of a 555-type
oscillator, followed by a counter section. The timing period of the
counter is externally programmable by the user.
In simplest block diagram terms, the timer portion generates a
basic timing pulse of a period, T. This is then multiplied (or
46
counted) by the counter to effectively increase the timing period by
a desired multiplication factor. The multiplication factor can be
made externally variable, thus the term programmable timer I
counter. Differences between the various devices mentioned are gen-
erally in terms of the functioning of the counter section, the timer
sections all being similar.
The XR-2240 is manufactured by Exar Integrated Systems, who
pioneered the concept of the timer/ counter. It is a binary program-
mable device with an 8-bit counter section. Timing is programmable
from lRtCt to 255 RtCt, where Rt and Ct are the timing components
that define the basic timing interval, which is T = RtCt. Two or more
2240 devices can be cascaded to extend the timing interval indefi-
nitely, counting in binary fashion.
The XR-2250, also manufactured by Exar, is a bed (binary-coded
decimal) programmable device. The time-base section of the 2250
is similar to the 2240, but the counter is an 8-bit design arranged to
count in decimal fashion over two decades. It is programmable from
lRtCt to 99RtCt. Two or more 2250 devices can be cascaded to ex-
tend the timing interval indefinitely, counting in decimal fashion.
The ICL 8260, manufactured by Intersil, is designed for seconds/
minutes/hours counting applications. The time-base section is simi-
lar to the 2240 and 2250, and the counter section is programmable
from I to 59RtCt. Two 8260s can be cascaded to count seconds and
minutes.
This programmable timer/ counter section is somewhat larger in
scope than the previous sections of this chapter because it discusses
an entire family of timing devices, each of which is a large-scale
system in itself. Although there are differences between the timers
covered, these are differences of detail rather than concept. There-
fore, the 2240 will be discussed initially in detail, and when its opera-
tion is understood, it will be relatively easy to transfer your thinking
to the 2250 and 8260 types.
2.4. 1 The 2240 Binary Programmable Timer/ Counter
The XR-2240 is produced by Exar, as mentioned previously, and
it is second-sourced by others under the 2240 part-number designa-
tion. It is also second-sourced by Intersil under the 8240 designa-
tion. The 2240 can be operated in either the basic monostable or
astable timing modes, as well as a variety of other modes. It is pack-
aged in a 16-pin dual in-line package.
Functional Diagram
A functional block diagram of the 2240 is shown in Fig. 2-16A. The
two main functional portions of this diagram are the time-base sec-
tion and the counter. The time-base section may be seen at the left
47
~
v+
16
r-- -----------------------------------------------------------------~I
1 I
I I
I I
I I
I
I Regulator
I I
I Output
I
: R, 15
15kn
Modulation 9 t~ I
~ 12 I
"T1
c : R2
:s Reset
!l :a.59 10
a· I kn Control
:s Flip-Flop -:-2 -:-2 -:-2
!!!.. R/C~ Logic
CT 13 I Trigger
0
n I I 11
~ I I
a.. I I
iii' I I
<g I I
QI I
: RJ I
? :5kn I
I
I I
I I
"II
I I
-?" I I
I I
::! I I
I
!" I ___ JI
...
:r L-- - -<>--0--0--0--0-
• 9 14 1 2 3 4 5 6 7 8
~ Ground Time-Base T 2T 4T ST 16T 32T 64T 128T
8 Output
!r. Binary Counter Outputs
::s
II
~
of the diagram and is made up of a 555-type astable oscillator, with
a buffered output at pin 14. The counter is seen at the right and con-
sists of 8 binary stages, with a buffered output available from each.
Each output is low for the multiple of the time-base period shown.
The T output (pin 1), for instance, is low for a period, T, while the
2T output (pin 2) is low for a period, 2T, etc.
A third subsection is the control logic, a circuit consisting of a
latch that is set and reset by pins 11 and 10, respectively. This circuit
controls the timer/ counter, resetting all counter stages when com-
manded, and starting the timer circuit upon command by a trigger.
The conb·ol functions and counter stages are powered by an on-
chip voltage regulator, which produces a nominal 4- to 6-volt output.
This is made available at pin 15. The time-base portion of the circuit
is connected directly across V+ and uses the 555 scheme of charging
from and comparing against the same ( V +) voltage, for timing-
period supply-voltage independence.
In operation, an external timing resistor and capacitor are con-
nected to the R/ C node, somewhat similarly to the connection for the
555 monostable. The capacitor is charged toward V+ via Rt, and the
timing ramp is compared to a fraction of V + generated by the R 1-
R2-R~ divider. The upper threshold is 0.731 of V +. Capacitor Ct is
discharged toward ground by the discharge transistor, and the lower
threshold is 0.269 of V +.
Although on the surface this scheme appears similar to the 555
astable timing mode, there are some important differences. First is
Trigger
v: :::J'. .____,
I
1T
Output
I
I
I
2T
Output
v: ~~~~-1'. . __________.
I
I
I
I
I I
;---T- :
I I
...
' >---- 2T ---~
49
the fact that this circuit is a triggered astable, and will always oper-
ate in an astable mode, even if the timer/ counter as a whole is used
as a monostable. An understanding of how the circuit functions may
be gained from the timing diagram of Fig. 2-16B.
In the reset or standby state, the time-base oscillator is inhibited
by Qz, which clamps the R/ C node to nearly the V + level. This may
be noted on the timing diagram in the sketch for the timing ramp.
When the circuit is triggered, Q2 turns off, removing the clamp. The
discharge transistor, Q:{, then rapidly brings the capacitor voltage
down to the lower comparator threshold. This changes the state of
the oscillator flip-flop, and Ct now charges toward V +. When the
upper threshold is reached, Qa discharges Ct again. The oscillator
will then continue to cycle until the control logic is reset.
Although the time-base operation is astable, the timing is highly
asymmetrical because Q:~ discharges Ct very rapidly but is charged
slowly through Rt. It is for this reason that the timing expression for
T is stated simply as a single period-the discharge time is short
enough to be neglected. This discharge time period generates the
short negative-going time-base output pulses. Note that the very
first discharge cycle is from V+, rather than 0.731 of V+. This factor
will result in only a slightly longer first timing period than the rest
because the discharge current for Ct is high. The timing scale is
exaggerated in the diagram to illustrate this point. In practice, the
error due to this effect is minimal, particularly for multiple time
counts.
In the 2240, the values of resistors R 1 and R2 are chosen such that
Ri + Rz = e = ~·'
Ri
9 ...,183
.
This makes the threshold voltage exactly equal to one time constant
so the timing period, T, is then simply:
T = RtCt.
In the timing diagram of Fig. 2-1613, two of the eight available
counter outputs are shown. The 1T output is low for one time-base
period; the 2T output is low for two time-base periods; and the re-
maining outputs, although not shown, follow a similar progression
( 4T, ST, 16T, etc.).
The reset input on the 2240 will terminate operation of the time
base and reset all counters to the zero-count state when taken high.
Timer programming is accomplished by simply wiring together the
appropriate counter outputs and feeding the common connection
back to the reset input. Since the outputs will remain low (or logi-
cally true) for their respective time periods, connecting two (or
more) together causes the common low output period to be the sum
50
of the individual timing periods. Thus, a period of 3T would be
achieved by wiring together outputs 1T and 2T; a period of 7T
would be achieved by wiring together outputs lT, 2T, and 4T; etc.
This is shown in Fig. 2-17, with an example of a programmed count
of lOT ( 2T + 8T). Regardless of the count programmed, when the
common output line goes high, the 2240 is reset, and the timing cycle
is ended.
51
of the reset input is similar to the trigger input; it responds to posi-
tive-going pulses at a level of 1.4 volts.
Rf C (Pin 13). The connection for the external timing resistor and
capacitor. Internally, this pin is connected to the inputs of both
comparators and the discharge and clamp transistors.
The time-base oscillator is astable in nature, and the waveform
appearing across Ct will be an exponentially rising sawtooth with a
short retrace. Timing voltage thresholds are 0.731 of V + for the up-
per comparator and 0.269 of V + for the lower comparator.
The timing sequence of time-base operation is illustrated in Fig.
2-16B. The time-base output is low (or true) when the timing capac-
itor is being discharged. This time is a small percentage of the total
timing period. The timing expression for the 2240 is T = RtCt, as the
upper comparator threshold voltage is set to a level of 0.632 of the
charging voltage.
Comparator threshold currents are not specified for the 2240; this
point is taken care of by specifying a maximum range of timing
components (these are discussed under "Basic Operating Modes").
Modulation (Pin 12). The pin that allows access to the upper
comparator reference voltage, which is normally 0.731 of V+. The
de voltages applied to this point may be used to control the time-
base period, if desired. Also, the time-base oscillator may be syn-
chronized to an external source by applying signals to this pin. Safe
voltage limits for this pin are between zero and V +.
v+ v+
lT v+ Rt
2T
4T R/C
ST 2240
16T ct
32T
'----------<E------~---0 Output
52
Time-Base Output (Pin 14). The output from the time-base oscil-
lator. The pulse on this pin is high during the reset state and goes
low upon triggering (and with each subsequent time-base period).
Timing is as shown in Fig. 2-16B.
The time-base output is internally connected to the counter input,
as shown in Fig. 2-16A. The negative-going time-base pulses trigger
the counter section. An external pull-up resistor from this pin to the
regulator output (pin 15) is required for operation. A value for this
resistor in the vicinity of 20 kn is recommended, but it is not critical.
The 2240 may also be operated with an external clock source, if
desired. In such a case, the time-base output pin serves as an input
to the counter section. Counter input trigger threshold is 1.5 volts.
Also, the counter may be disabled, if necessary, by clamping pin 14
to ground externally.
Regulator Output (Pin 15). The output of an on-chip voltage
regulator, which powers the counter and logic sections of the 2240.
If two or more 2240s are cascaded, the regulator output can be used
to power the counter sections of succeeding devices without their
time bases, in the interest of low power consumption. Output current
from this pin should be 10 mA or less.
With a V + of L5 volts, the regulator output will be typically 6.3
volts; it is typically 4.4 volts with a V + of 5 volts. If the time base is
to be used with a V + of 4.5 volts or less, it is recommended that pin
16 be jumpered to pin 15.
Basic Operating Modes
The 2240 is capable of operation in either the monostable or the
astable timing mode. Timing is programmable in either mode, and
operation is achieved with a low number of external components.
Monostable Mode. The 2240 is shown connected for monostable
operation in Fig. 2-18. In this circuit, Rt and Ct set up the time base
for the desired basic period, T. Programming is accomplished by
jumpers, switches, or other suitable means. The timer output appears
across the common load resistor, RL, and the output pulse width, T 0 ,
53
U'I
,,. "'l'I
,p·
~
~
-t v+
::r
CD (+5V to +15V)
~
~ - Timing Diagram
.co. RL
0 RT
"ti lOkn Trigger _:f="l:.:-------- l.4V
0 22 kn ~ R,* I
( 4>-----0-- lT V+ Regulator
I I
'!!Ill I
=
o·=-
?
Other circuit components are Rh which serves as a load resistor
for the time-base output, and Ct, a noise bypass to ensure noise
immunity within the time-base upper comparator. The value shown
for RL is not a critical one, and the voltage to which it is returned
need not be the same voltage as the chip supply, as long as it is be-
tween 5 volts and 1.5 volts. Thus, a 2240 may readily drive various
forms of logic, as wel1 as discrete stages.
The range of timing components useful with the 2240 is broad. It
is recommended that the timing resistance be between 1 kn and
10 Mn. The capacitance should be between 0.01 µF and 1000 µF.
In addition to these limits, there is a maximum limit on the time-base
oscillation frequency of about 100 kHz, which effectively places a
minimum on T of 10 µs. All of these constraints should be met in an
optimum design.
Astable Mode. The astable mode of operation for the 2240 is
shown in Fig. 2-19. This circuit is similar to the monostable mode of
operation, with the exception that the reset input is not connected
to the output. This allows the 2240 to continue oscillation, once
started by a trigger pulse. With a single counter output connected to
RL and the output bus, the 2240 will oscillate at a frequency, fo,
which is:
1
ti.= 2nRtCt'
where n is the count of the particular tap selected ( 1, 2, 4, 8, etc. ) .
The factor of 2n is derived from the fact that, in terms of frequency,
the basic timing taps of the 2240 counter are multiples of one-half
period.
The circuit will not self-start with the application of power be-
cause the internal logic will revert to the reset state. A pulse applied
to the trigger input will start synchronous oscillations, with timing
as shown. If desired, oscillation may be halted by the application of
a reset pulse, which will cause the output to go high. The circuit will
then remain in that state until triggered again. If automatic power-
up oscillation is desired, the trigger input can be wired to the regu-
lator output (pin 1.5) which will self-start the circuit. Timing com-
ponent considerations are identical to those of the basic monostable
circuit.
Specifications
The specifications of the 2240 are by nature different from the
previous timers discussed, since it is a much more complex device.
Still there are many similarities, so the following discussion will em-
phasize the differences from 555-type timers. For reference purposes,
a 2240 data sheet is included in Appendix A.
55
UI
°' "'l'I
«?" Timing Diagram
~
V+ (+5V to +15V) Trigger __J=L----- 1.4 V
...:r~
•
~
Output~_r-
~ RI ' I I
Rt * I I I
8 22kn I I I
ft = nR 1 C 1
0
'
c
- 64T Trigger Trigger
i l
f =--
- - - - - --<J Reset 0 2nR 1 C 1
ft l 28T Ground Reset --~--
=
0 (optional)
=i where,
=i c1
Cll
0.01 µF n = l, 2, 4, 8, 16, 32, 64, or 128.
;a.
;-
..
Ill
!!&. Output
Ill
er
..
0
'a **c 2 is a shunt capacitance of ~ 300 pF, required for a
!C. C 1 of~O.lµFandaV+~7Vdc.
=
c;·
?
The 2240 operates from a similar range of power-supply voltages-
+4 volts to + 15 volts. Typical supply current is 4 mA at +5 volts;
13 mA at + 15 volts. A substantial portion of this current is consumed
by the time base; only LS mA is consumed by the counter.
Timing accuracy is very good, typically 0.5% at a V + of 5 volts.
Drift with temperature varies somewhat with supply voltage, being
200 ppm/ °C at +5 volts, but 80 ppm/ °C at 1.5 volts. Supply-voltage
timing sensitivity is listed as 0.08% per volt (typical) for supply
voltages of 8 volts or more.
The maximum operating frequency is typically 130 kHz, as de-
fined by the minimum timing components. It is recommended that
the timing resistance be between 1 kn and 10 Mn, while the timing
capacitance should be between 0.01 µF and 1000 µF.
The trigger and reset inputs of the 2240 have very similar sensitiv-
ities. The voltage thresholds are 1.4 volts, the impedance is 25 kn,
and the current is 10 µA at an input voltage of 2 volts. Trigger re-
sponse time is 1 µ,s, while reset response time is 0.8 µs.
The counter section has a maximum toggle rate of 1.5 MHz typical.
While this is above the maximum frequency of the internal time
base, it does indicate that the 2240 is useful with an external clock
at higher rates.
The counter trigger input (time-base output) has a trigger thresh-
old of 1.4 volts and an impedance of 20 kn. For the counter outputs,
rise and fall times are 180 ns with a load of 3 kn and 10 pF. Each
output can sink 4 mA at a voltage of 0.4 volt or less. OH-state leak-
age is typically 0.01 µA at a voltage of 15 volts.
2.4.2 The 2250 BCD Programmable Timer/ Counter
The XR-2250 is also manufactured by Exar Integrated Systems.
It is second-sourced by Intersil under the 8250 designation, with a
slightly different pin configuration. The 2250, like the 2240, may be
operated in either the basic monostable or the astable timing mode,
as well as a variety of other modes. It is packaged in a 16-pin dual
in-line package.
Functional Diagram
A functional block diagram of the 2250 is shown in Fig. 2-20. This
diagram is essentially the same as that for the 2240, the primary dif-
ference being in the counter section. Minor differences include a
new pin designation for the modulation input (pin 15), the deletion
of the regulator output, an internal load resistor on the time-base
output, and the addition of a carry-out terminal (pin 12) used to
cascade two or more 2250s.
In the counter section, it may be noted that there are still eight
stages, with a similar arrangement of output pins. In the 2250, how-
57
Q '$ N "'"'
uO-
---------------------------------,
I
I
:
I
I
I
I
0 ~
"U
t ~ Q----+----'l~-"'"-_-_-_.,i,_-_-_,,,...,..,-1,----_-.,i,..._-_-_.,i,_-_-_..._-_-_-:_-_-_-_--"-"'_"'__
" -_-::_o_~~-.:=_-.:=_-.:=_-.:=_-.:=_-=.._---<:1 ~ j
Q:~~~ 11 :
---------------------------------~
·~ ~ ~~
Fig. 2-20. Functional block diagram of the 2250 bed programmable timer/counter.
58
ever, the counters are arranged in groups of four bits. The first four
bits (I, 2, 4, and 8) are connected in a feedback arrangement so that
they count in bed from 0 to 9. The output from this first four-bit set,
which may be called a units decade, drives a second four-bit set:
10, 20, 40, and 80.
The second set of counters is the tens decade, and similarly counts
from 0 to 9 by virtue of feedback. As the input drive is in units of
ten, however, the actual output count is in tens; therefore, this sec-
tion counts from 0 to 90.
The carry-out terminal, pin 12, is used in applications where two
or more 2250s are to be cascaded. This pin goes low at a count of
100 and is used to drive the time-base (counter) input of a succeed-
ing 2250, which will then count hundreds (and thousands).
The remaining functions of the 2250 are the same as has been
described previously for the 2240. Programming is accomplished by
connecting the appropriate output pins to the output bus. The only
difference is that the maximum count for the 2250 is 99 rather than
255 in the case of the 2240. The control logic, trigger and reset in-
puts, and the time-base section operate in a manner very similar to
the 2240.
Definition of Pin Functions
The only additional pin on the 2250 that is functionally different
from the 2240 is the carry-out pin, which is described next. There
are, however, some pinout differences between the Exar 2250 and
the Intersil 8250, which are noted. The reader is referred to the 2250
and the 8250 data sheets in Appendix A.
Carry Out (Pin 12 on the 2250; Pin 15 on the 8250). This pin is
used to signal an overflow of the counter, corresponding to a count
of 100. This output goes low at a count of 100 and is used to drive
the counter of a suc~eeding 2250 via the time-base output (counter
input) pin. The output is TTL compatible and can thus be used to
drive other forms of logic if desired.
Modulation (Pin 1.5 on the 2250; Pin 12 on the 8250). Function-
allv, there is no difference between this pin on the 2240 and the
22.50. In the 22.50 it is placed on pin 1.5, whereas the 82.50 retains the
use of pin 12 for this function.
Time-Base Output (Pin 14). There is an internal load resistor
added on this pin; therefore, a load resistor is not needed externally
as is the case with the 2240.
59
similar to Fig. 2-18 (with the exception of the pinout differences),
and the basic timing expression is
To= nRtCt.
In this case, however, n is variable from 1 to 99.
The basic astable connection is similar to Fig. 2-19, and the fre-
quency expression is
1
fo = 2nRtCt ·
60
------------------------ ---------1
I
I
I
I
I
I
I ~
*°': ~~
I
I
I
I
c ~
--'\N\.-----4-----'1r-----~-------,Jlr----V;! ~ %
~o
..,
~--,i,--+---.--,i,---+-----~o~ ~---+----oo- g
: l5
et:: M...ll:
_______________________ 11
__________ JI
~~ ~~
:g
~
61
Basic Operating Modes
There are no functional differences in the basic operating modes
between the 8260 and the 2250 (or 8250), with the exception of the
counting.
Specifications
There are no major specification differences in the 8260 over the
8250. For reference purposes, an 8260 data sheet is included in
Appendix A.
REFERENCES
1. Carnenzind, H. R. "The 555 Timer Story." Monogram, No. 2, October 1973.
Interdesign, Inc., Sunnyvale, Calif.
2. Grehene, A. B. "Linear IC's Mark Time With a Minimum of Components."
Electronic Products, April 16, 1973.
3. - - - . "The Programmable Timer/Counter-A New IC With a Myriad of
Applications." Proceedings of Electronic Products Magazine IC Seminar,
October 1973.
4. - - - . "Which IC Timer to Buy." Electronic Design, February 1, 1974.
5. Hnatek, E. R. "Put the IC Timer to Work in a Myriad of Ways." EDN,
March 5, 1973.
6. Idnani, C. "An Integrated Circuit Dual Timer." IEEE Transactions, BTR-
20, No. 4, November 1974.
7. Jung, W. G. "The IC Time Machine." Popular Electronics, November 1973,
January 1974.
8. Mattera, L. "IC Timers Make the Most of Delay." Electronics, June 21, 1973.
9. Nelson, C. Versatile Timer Operates From Microseconds to Hours. National
Semiconductor Application Note AN-97, December 1973. National Semi-
conductor Corp., Santa Clara, Calif.
10. "Time .... IC Controlled." QST, June 1972.
11. Timer/Counter Applications Brochure. Intersil, Inc., Cupertino, Calif., Fall
1975.
12. Wyland, J. "A Solid State Timer Device for the Consumer." WESCON
Proceedings, August 1973.
13. - - - ; Hnatek, E. R. "Unconventional Uses for IC Timers." Electronic
Design, June 7, 1973.
62
3
In this final chapter of Part I, we are but one step removed from
applying IC timers in actual circuits. However, in a practical sense,
this chapter is of great importance because it will enable the reader
to reap maximum benefit from a given device by optimizing its
performance and minimizing possible application pitfalls.
63
4 8
Legend:
6
R v+ R =Reset
TH
3 TH = Threshold
OUT TR= Trigger
2 555
TR DIS = Discharge
5 OUT= Output
v
7 V, =Control Voltage
DIS v+ =Supply Voltage
GND GND = Ground (Common)
9
4 14 10
2
R v+ 12 R
TH TH
5 9
OUT OUT
6 556 8 556
TR TR
A 3 B 11
v v
13
DIS DIS
GND
7 I
I
-4'-
(B) Type 556 (14-pin package).
Fig. 3-1. Pinouts and terminal designations for the 555/556 timers.
put pin, etc. As a further aid to understanding, these pins will al-
ways appear in locations similar to that shown.
3. 1.2 322/ 3905 Monostable Timers
The pinouts and terminal designations for the 322 and 3905 mono-
stable timers are as shown in Fig. 3-2. There are several differences
in terminology as well as slight differences between the two devices.
As shown, the 322 is in a 14-pin dual in-line package and uses 10 of
the available 14 pins. Pins used on the 322 that are not common to
the 390.5 are Vadj and boost. The 390.5 is in a low-cost, 8-pin package,
and consequently does not make these functions available. For all
other considerations, however, the two devices are functionally and
electrically identical. The schematic symbol is the same for the two
devices except for the pin availability and numbering used.
3.1.3 2240/2250/8260 Programmable Timer/Counters
The pinouts and terminal designations for the 2240, 2250, and
8260 programmable timer I counters are as shown in Figs. 3-3, 3-4,
64
Legend:
3 11 R/C =Timing R/C Node
TR B TR= Trigger TR
2 10 8 5
v+ Va= Vadi * L v+
V r =V ref
4 322 12 L =Logic 2 3905
v c B =Boost* v c 6
C = Collector Output
5 E = Emitter Output 3 7
R/C E R/C
v 0
GND v+ =Supply Voltage GND
GND = Ground (Common)
7 6 4
*Not available with 3905.
(A) Type 322 (14-pin package). (B) Type 3905 (8-pin package).
Fig. 3-2. Pinouts and terminal designations for the 322/3905 timers.
and 3-5, respective1y. All three devices are supplied in a 16-pin dual
in-line package.
Legend:
v+ =Supply Voltage
16 REG = Regulator Output
TBO =Time-Base Output
1T v+ REG R/C = Timing R/C Node
2T TBO MOD= Modulation (Control Voltage)
4T R/C TR= Trigger
BT 2240 R =Reset
12
16T MOD GND =Ground (Common)
32T l T = l R, C, (Time-Base Period)
64T
11 2T = 2R,C,
TR
10 4T = 4R,C,
128T R
GND 8T = SR, C, Multiples of
9 l 6T = l 6R, C, Time-Base Period
32T = 32R, C, in Binary ( l T to 255T)
64T = 64R,C,
128T = 128R,C,
Fig. 3-3. Pinouts and terminal designations for the 2240 binary programmable
timer/counter.
65
16 * Pin designations for 2250 and
ls
Decade
l lT
2T
4T
v+ MOD
ST- 2250/
TBO
R/C
14
13
S250 differ as follows:
MOD
2250
15
S250
12
lOT 8250* CO co 12 15
10s
Decade
I 20T
40T
SOT
GND
9
TR
R
11
10
Legend:
V+ =Supply Voltage
MOD= Modulation (Control Voltage)
TBO = Time-Base Output
R/C = Timing R/C Node
CO = Carry Output
TR= Trigger
R =Reset
GND = Ground (Common)
1T
2T
T = 1s Decade
4
Multiples of
ST Time-Base Period
: I= Hh O&ode
in BCD (lT to 99T)
SOT)
Fig. 3-4. Pinouts and terminal designations for the 2250/8250 bed programmable
timer/ counter.
12
GND =Ground (Common) lOT
{ MOD
l
10s
20T
Decade 11
40T TR
10
:~
IT = h D&ode )
Multiples of
GND
R
9
Time-Base Period
lOT/
~;) = 1Os Decade
j in BCD (1 T to 59T)
Fig. 3-5. Pinouts and terminal designations for the 8260 seconds/ minutes/hours
programmable timer/counter.
66
extremes). Thus, it is fairly certain that a wide range of values will
be available for any given resistor type.
In the class of general-purpose resistors, both carbon-composition
and carbon-film types are available. These are generally supplied in
tolerances of 5% and 10%, with some carbon-film units in 2%
tolerances. Temperature coefficients vary depending on the exact
type and value but are in the range of 200 to 500 ppm/ °C. These
types of resistors are suitable for breadboarding or for general-
purpose noncritical applications where a total range of resistance
uncertainty and/ or instability can be 10% or more.
A higher-quality resistor is the metal-film type available from a
large number of manufacturers. These units are supplied in a much
broader range of values, even down to and including 1% increments
if desired. Initial tolerances can be from 0.1% to 1%, and TCs are
available from 25 to 100 ppm/ °C. It is this type of resistor that is
most suitable for precision or semiprecision timers. Their cost, while
higher than that of carbon resistors, is reasonable when performance
is considered.
In general, the foregoing statements are true for resistor values
from 100 !1 to 1 Mn. Unfortunately, for values above a few megohms,
precise and stable resistor types become harder to procure and are
more expensive. When accuracy and stability are required in the
range of 1 M!1 to 100 Mn, the unit selected will most likely not be a
stock component.
Applications that require long timing periods should be examined
very closely for possible tradeoffs between the resistor and the
capacitor. Also, a timer/ counter to extend the timing range should
be considered. This latter option can often be a workable solution
in view of the cost and procurement problems of high-value resistors
and capacitors.
Adjustment is often desirable in the timing resistor. If not handled
carefully, however, the introduction of a potentiometer can sacrifice
the reliability of a timing circuit. From a reliability standpoint, it is
good practice to avoid potentiometers if at all possible. Of course,
there are situations that demand them, such as panel-operated cir-
cuit controls. In these cases, it is always best to select a high-
quality control, due to the frequency of adjustment, operational
"feel," environment, etc.
Circuit-trimming potentiometers can also be sources of trouble. In
general, the percentage of resistance range of a trimmer should be
minimized to just in excess of that required. For example, a poten-
tiometer that has a relatively poor TC will have its TC in the cir-
cuit improved by a factor of ten if the trim range is reduced to 10%.
The open-element carbon-type trimmer should be avoided, if pos-
sible, unless performance requirements are modest. The multitum
67
cermet types provide excellent performance for their cost and are
available in a wide range of values.
Regardless of the resistor type used, its stability will be enhanced
if it is well derated with regard to power. This will usually not be a
problem except for low-value resistors at the higher supply voltages.
A good goal is 1/ 5 or less of rated power, rather than the usual
"half-power" reliability rule.
3.2.2 Capacitors
Capacitor selection is by far the biggest problem of all in the
design of a timing circuit, for several reasons. These reasons include
the necessity for understanding the many capacitor types, their per-
formance/ cost tradeoffs, and the severe limitations of capacitors for
timing applications, particularly in the larger values. Capacitors are
by their very nature a somewhat imprecise component, and few
types are even available that have tolerances below 5%. Of those
types that are available, not all are suitable for timing applications,
for one reason or another. In addition, the range of available values
is limited.
In general, for timing circuit use, a capacitor must have very low
leakage, good dielectric-absorption characteristics, and a low tem-
perature coefficient for stability. The low-leakage point is an obvi-
ous m 1e; if a timer is to use a capacitor that is to be charged from a
1-µA source, it must have a self-leakage much lower than this. Fur-
thermore, the leakage must remain low over conditions of voltage,
environment, and time. The second point is particularly important
for timing-circuit capacitors. Some dielectrics used in capacitors ex-
hibit the phenomenon known as dielectric absorption (abbreviated
DA). Very simply, this means that when the capacitor is charged
and then discharged by shorting the leads together, the dielectric
does not give up all of the energy that was stored when the capacitor
was charged. The capacitor is then said to exhibit a residual volt-
age. For timing circuits, this is an obvious drawback because the
timing principle depends upon starting from zero. And, in some ca-
pacitor types, the DA (measured in percent) can be as high as
several percent, so it is a very real problem.
Capacitor types with high dielectric absorption should be avoided
for timing circuits if good performance is desired. These include
papers, ceramics, and some mica types. All of these types can have
DAs of 3% to 5%. Impregnated dielectrics will generally be poor in
terms of dielectric absorption, although they may excel in other char-
acteristics. There is one family of capacitor types, however, that is
very good in terms of dielectric absorption, and that is the plastic-
film capacitors. These include polystyrenes, polycarbonates, and
some others.
68
Polycarbonate types are below 1% for dielectric absorption, and
polystyrene and parylene types exhibit a DA below 0.1 %. Teflon °
is another excellent capacitor dielectric for timing circuits, its only
drawback being its relatively high cost.
Polystyrene is one of the best dielectrics in terms of cost and per-
formance, but it does have two limitations. It cannot be used above
85°C, and it is available in capacitance values only up to about 1
µF, and this range is not always available from all sources. Advant-
ages of polystyrene include tolerances down to 1% and a very linear
TC of -120 ±50 ppm/ °C. While not zero, this TC is low enough for
many applications; for other applications, the fact that the TC is
linear allows compensation with a thermistor if necessary. This TC
is the lowest available in low-dielectric-absorption types. Polystyrene
capacitors are available from many sources.
Parylene, a proprietary dielectric of Union Carbide, is used in the
Kemet F310 series of plastic-film capacitors. These types range in
value from 0.001 µF to 1 µF with tolerances down to 0.5%. Their TC
is linear at -200 ±30 ppm/ °C. This capacitor type is useful over a
temperature range of --55°C to+ 125°C.
Polycarbonate is the next most suitable dielectric and is widely
available from a number of suppliers at moderate cost. The values
range up to several tens of microfarads from some suppliers, and
close-tolerance units are available. Temperature coefficient in this
type is not as linear as in the polystyrene or parylene types; thus it
cannot be compensated as easily. In general, types can be obtained
that will exhibit a total value change of less than 1% over a 0°C to
70°C temperature range, without compensation.
Although this discussion obviously involves low-voltage capacitor
types (i.e., 25 to 50 Vdew), we are nevertheless still talking about a
relatively large physical device for capacitances of 1 µF or above
(i.e., 1 to 2 inches in length). This is, unfortunately, one of the
capacitor "facts of life." To some extent, capacitor size in a given ap-
plication can be minimized by increasing the value of the timing re-
sistor; in fact, this tradeoff should always be made because capacitor
price is a strong function of size (and not necessarily a linear one) .
Where possible, timer/ counters can help minimize capacitor size, as
previously mentioned.
One type of capacitor that has not as yet been mentioned is the
electrolytic type. This is simply because electrolytics are far from
optimum for timing-capacitor use. Their drawbacks are: very loose
tolerances, poor stability, and high leakages. In general, aluminum
electrolytics are not suitable at all for timing circuits, unless the
application is one of low-performance requirements.
0
A registered trade name of E. I. duPont de Nemours & Co., Inc.
69
Tantalum electrolytics can be used with certain qualifications. For
limited temperature ranges such as 0°C to 50°C, tantalums are very
attractive economically and offer reasonable performance. One ex-
ample of this type is the Union Carbide Kemet T310 series. In gen-
eral, voltage derating wil1 aid in controlling leakage in these types.
Since leakage can be as high as several microamperes in tantalum
types, a reduction of usable resistance range will accompany their
use. Timing current should be several times greater than the highest
anticipated capacitor leakage.
For reference, a list of suppliers of suitable timing resistors and
capacitors is included in Appendix C.
70
'"~-----~---------------------------·
71
V+ (+4 V to +36V) (+lOV to +30V) V+
(+5 v to +15v) ( +5v to +15V)
6
,1
L_I ,5
,,.~ ~ lOM!!
4
I
I I
5.1M!l'1-~_t ___
L~_,
I Rodi .
1
___ J lOkn Rod; ~
50 kn
V- (GND) V- (GND)
(-5V to -15V) (-5V to -15V)
V + ( + 5 V to + 15 V ) V + ( + 5 V to +30 V)
(+2.5V to +7.5V) cit
(+5V to +15V)
---~
od1
7 r i
1 ~25knr _ _J
15
V- (GND)
V- (GND) (-5V to -15V)
(- 2.5V to -7.5V)
V- (GND)
V- (GND) (-2V to -15V)
(-2.5V to -l5V)
(E) Types 308/308A. (F) Types 3080/3080A.
Fig. 3-6. Timer-compatible op amps.
72
The 3140 also has the ability to operate with the input at zero
volts (ground) when operated from a single supply. This one fea-
ture is highly desirable for use with timers, as it eliminates the need
for the dual supplies usua1ly required with op amps. The combina-
tion of features mentioned makes the 3140 probably the single most
useful op amp for timer use. The pinouts for the 3140 are identical to
the 741, as seen in Fig. 3-6A. This particular pin configuration (with
the nulling) is the most standard one among op amps and is appli-
cable to many others in addition to the 741 and 3140. Some examples
are the 8007, 1456, 1436, and 776, to name just a few.
Another popular general-purpos e op amp is the 301.A, which is
shown in Fig. 3-6B. Pin configuration is similar to the 741, but an
additional compensation capacitor (Cc) is necessary. This hookup
is also suitable for the 748 and 777 types.
The 3130 (shown in Fig. 3-6C) is another FET-input op amp, one
which preceded the 3140. It is limited to a total supply voltage of
15 volts, but also has the ability to operate with the input at zero
volts when operated from a single supply. It requires a compensa-
tion capacitor (Cc) and has the unique characteristic of an output
stage that can swing to each supply limit. It can be used from +5
volts to +15 volts; thus it is directly compatible with 555-type timers.
The 356 (shown in Fig. 3-6D) is also a FET-input amplifier but
with de performance specifications that place it in a more premium
class than the 3130 or 3140. It is suitable for higher-accurac y appli-
cations that demand high stability in terms of input specifications. It
is nulled differently, as shown.
Pinouts for the 308-type op amps are shown in Fig. 3-6E. As may
be noted, this amplifier is compensated identically to the 301A. The
main difference is that there is no provision for offset nulling in the
308 types. This is not necessarily a disadvantage as the 308.A features
a maximum offset voltage of .500 µ V, plus other premium specifica-
tions such as a typical bias current of 1..5 n.A. These devices can op-
erate from single supplies as low as 5 volts and possess the highest de
accuracy of the types listed here.
Pinouts for the 3080 amplifier types are shown in Fig. 3-6F. This
device is not a conventional op amp but is an operational transcon-
ductance amplifier (OTA). The output is in the form of a current,
I 0 , the maximum value of which is programmable by means of cur-
rent I.Anc into a third input terminal. The direction of output current
flow (into or out of the output) is determined by the differential in-
puts. The 3080.A is useful over a programming current range of more
than five decades, and both types are useful over wide supply-volt-
age ranges.
Quad and dual op-amp types are also available and are useful in
systems applications. Pinouts for the 324 and 3403 quad op amps are
73
V- (GND)
(-1.5V to -15V)
14 13 12 11 10 9 8
324/3403
2 3 4 5 6 7
v+
(+3V to +30V)
( + 1.5 V to + 15 V)
358/1458
.----------~-a-v v+
(+3V to +30V)
(+l.5 v to +15V)
v- v---4_,___ _ _ _ _ _ __
(GND)
(-l.5V to -15V)
74
shown in Fig. 3-7A. Both these devices operate from single supplies
from below +5 volts to +30 volts, and they will operate with the
inputs (and outputs) at zero volts. Their input bias current is much
higher than the 3130, 3140, or 356 types, however. They are internally
compensate d and have no offset-null provision. Of the two units,
the 324 is more useful to timer applications for several reasons. It
has a very low (standby) supply current ( 0.8 mA), and its input
bias current is much lower than the 3403 ( 45 nA). Both devices have
a wide supply-volta ge range.
The 3.58 op amp, shown in Fig. 3-7B is a dual device in an 8-pin
package. Its electrical performance is identical to the 324. The 1458,
which has identical pinouts, is simply two 741-type devices. The
supply-volta ge range shown is for the 358 only; the 1458 is subject
to the same supply-volta ge and input/ output restrictions as a 741.
For further insight into these devices, and op amps in general, ref-
erences are listed at the end of the chapter.
3.4.2 Logic Devices
Logic devices that are compatible with timers could include vir-
tually all of those available, which number in the thousands. How-
ever, certain devices interface more readily with timers than others,
due to supply-volta ge range, threshold levels, and/ or loading con-
siderations. For instance, if the timer circuit is operated from a 5-
volt supply, the entire 54/74 series of TTL logic is available to the
designer for interfacing, at both the timer input and output. A dis-
cussion of the hundreds of TTL devices available is beyond the
scope of this book, however, and the reader is referred to the refer-
ences at the end of the chapter.
One logic family that is highly compatible with timers is the
CMOS family, as it has an identical supply-volta ge range of +5 volts
to + 15 volts. Furthermore , CMOS inputs are essentially nonloading,
as their input current is only 10 pA. They have a logic threshold of
% of V+; therefore, they may be driven from virtually any timer
output without concern for interfacing problems. Also, the very
low leakage characteristi c of CMOS switching elements makes them
ideal for direct use within the RC timing section, without compro-
mise in timer performance . Finally, the speed capability of CMOS,
while far from the highest by modern logic standards, is more than
adequate in terms of compatibilit y with timers. At low speeds and/
or long timing periods, the virtually zero power dissipation of CMOS
is a strong point in its favor. It is for these reasons that CMOS de-
vices are used within the applications section.
A few CMOS devices that are compatible with timers are shown
in Fig. 3-8. These devices are from the CD4000 Series, a logic family
introduced by RCA and second-sour ced by many others.
75
v+ v+
(+5V to +15V) (+5V to +15V)
4049 4050
2 2
4 4
6 6
9 10 10
12 12
15 15
8 8
GND GND
(A) Type 4049 hex inverter. (B) Type 4050 hex buffer.
Fig. 3-8. Timer-compatible
76
v+
(+5V to +l5V)
14 r
4016/4066
51
l
IN/OUT -- --<t1'o---
I
2
-- OUT/IN
I
I
I
I
13 I
CONT. --
52
-- 4 -if(0- 3
IN/OUT
I - OUT/IN
I
I
I
I
CONT. --
5 I
SJ
8 9
IN/OUT -- -~o---
I - OUT/IN
I
I
I
I
CONT. -- 6 I
54
ll lO
IN/OUT - -<t1'o---
I
I
- OUT/IN
I
I
CONT. --
12 I
r
GND
77
J
v+
l+sv to +1sv1
6 l 3 10
12
J8 N
l
GND
v+
<( (+40V max.)
I
I IN 1--o......u_r-0----.-----0 v /
317 I
I
ADJ 1.25 V
~
:: Ri* *V 0 = 1.25 ( 1 + ~)
50µ.A i (COM) 1 1
----------1
.': R2 *
••
'
-=!:-
(A) The 317 as basic voltage regulator.
v+
<( ( +40V max.)
I
I IN OUT
L--
317 --,
I
... 1.25V
ADJ l.25V •:Rt * I0 = -R - + 50µ.A
~µ.A' ~OM) l1
----------1
I
I
t
78
For buffering and logical inversion of timing signals, the 4049
hex inverter shown in Fig. 3-8A is very useful. This device can be
operated from +5 volts to + 15 volts as a general-purpose inverter
but may also be used as a logic level converter, with a 5-volt supply
and a 15-volt input as one example. This device is very useful in such
cases as driving a TTL system from a 15-volt timer output. The 4050,
shown in Fig. 3-8B, is a device that operates similarly but does not
invert the signal.
The 4016, shown in Fig. 3-8C, is not a logic element in the strictest
sense but is actually a set of four logically controlled switches.
Switches S1-S 4 are CMOS transistors whose conduction state is con-
trolled by input control lines. Switch Si, for example, is "on" when
pin 13 is high and is "off" when pin 13 is low. The switches are
bilateral and may be referred to any voltage between zero and the
V+ level used. The "on" resistance is typically 300 n at a V + of 15
volts, and off-state leakage is typically 100 pA. A device that has
identical pinouts but features a lower "on" resistance is the 4066.
The R0 n in this device is typically 80 n at a V + of 15 volts; otherwise
it is similar to the 4016.
Another device that can be quite useful in timing circuitry is the
4007, shown in Fig. 3-8D. This unit is an array of uncommitted n-
and p-channel MOS transistors, which can be wired for a variety of
functions. Gate drive to any input is the typically low CMOS cur-
rent of IO pA. This same basic circuit structure is also available in
the RCA CA3600, which is characterized for linear service.
There are, of course, many more CMOS devices that are suitable
for use with timers. One notable family is the 54C/74C series by
National Semiconductor, which is also second-sourced by others.
This CMOS family is functionally equivalent to, and pin-compatible
with, the 54/74 TTL types, but with CMOS characteristics. Func-
tions include most of the TTL series counterparts, and some not
found in the CD4000 series.
For further background on CMOS devices, references are listed at
the end of the chapter.
3.4.3 Regulators
Fig. 3-9 illustrates the 317, a 3-terminal, positive voltage-regulator
IC, which is useful with or within timer circuits. This device is a
programmable output regulator with a current capability of up to
1.5 A and an output voltage range of + 1.25 volts to +37 volts. It
may be used as either a voltage or a current regulator and is avail-
able in T0-3, T0-5, and T0-220 packages. The two basic modes of
operation (as a voltage regulator or as a current regulator) are il-
lustrated in Figs. 3-9A and 3-9B, respectively. Salient points of device
operation are the 1.25-volt ±4% terminal voltage between the OUT
79
Substrate
14 13 12 11 10 9 8
3046/3086
2 3 4 5 6 7
and ADJ terminals, and the 50-µA bias current flowing from the
ADJ terminal.
3.4.4 Transistor Arrays
A very convenient IC for use with timer circuits is the monolithic
transistor array. This type of device, which is available in a variety
of configurations, is a great aid to circuit design from the stand-
point of matching device characteristics and packing density. A
popular representative type is the 3046 array shown in Fig. 3-10.
These five transistors have general-purpose specifications, but they
also feature matching characteristics and thermal tracking. The
3086 is an array that has identical pinouts but with slightly different
specifications.
REFERENCES
1. Calebotta, S. CMOS, The Ideal Logic Family. National Semiconductor
Application Note AN-77. National Semiconductor Corp., Santa Clara, Calif.
2. Dansky, S.; Funk, R. E. Handling and Operating Considerations for MOS
Integrated Circuits. RCA Application Note ICAN-6000, March 1974. RCA
Solid State Div, Somerville, N .J.
3. Havasy, A.; Kutzin, M. Interfacing COS/MOS With Other Logic Families.
RCA Application Note ICAN-6602, November 1973. RCA Solid State Div.,
Somerville, N .J.
4. Johnson, F. L. Capacitors . . . Dielectric Absorption. Technical Bulletin
No. 10. Electrocube Inc., San Gabriel, Calif.
5. Jung, W. G. "A Guide to CMOS Operation." Part 1, Popular Electronics,
March 1974. Part 2, Popular Electronics, April 1974. "How CMOS Devices
Are Used in Linear Applications," Popular Electronics, August 1974.
80
6. - - - . IC Op-Amp Cookbook. Howard W. Sams & Co., Inc., Indianapolis,
1974.
7. Lancaster, D. TTL Cookbook. Howard W. Sams & Co., Inc., Indianapolis,
1974.
8. Melen, R.; Garland, H. Understanding CMOS Integrated Circuits. Howard
W. Sams & Co., Inc., Indianapolis, 1975.
9. Redfern, T. P. 54C/74C Family Characteristics. National Semiconductor
Application Note AN-90. National Semiconductor Corp., Santa Clara, Calif.
10. Manufacturer's Data Sheets:
l LM.317
MM54C/74C
CA3600
Voltage/Current Regulator.
Series, Logic Devices.
CMOS Transistor Array.
ll
CA3046 NPN Transistor Array.
CA3086 NPN Transistor Array.
RCA CA3130 Operational Amplifier.
CA3140 Operational Amplifier.
CA3080 Operational Transconductance
Amplifier ( OTA ) .
CD4000 Series, Logic Devices.
11. Military Specifications:
MIL-C-19978D-Capacitor, Fixed, Plastic (or Paper-Plastic) Dielectric
( Hermetically Sealed in Metal, Ceramic, or Glass Cases ) , General Specifi-
cation For.
MIL-C-55514A-Capacitor, Fixed, Plastic (or Metallized Plastic) Dielectric,
DC, in Nonmetal Cases, General Specification For.
81
II
IC TIMER APPLICATIONS
4
85
some specific voltage (or range of voltages), much as + 15 volts
rather than the general V +, this is listed. In such cases, the limita-
tions of the circuit will be discussed further within the accompanying
text.
Also in the interest of overall clarity, the input trigger conditioning
circuitry is not shown. The reader is cautioned, however, to provide
satisfactory trigger signals for the device being used (see Chapter 2
for details of device triggering requirements).
v+ Timing Diagram
Enable - - , r--'-,
(optional) U L___
I
Input i__t:----'~
I I
Enable 0------------ I
ct J/t1_
I
rOn I 11 , _ __ _
Rt
.J Off
1 Mn
4 8 Output _J--ti__.,____
D1 6 R v+ I
I
I
I
1N914 ~----tTH OUTi-3_..._-o :._ T*_:
u - - - - - 4 E - - --tTR
2 Output 1
Trigger
555
u 7
DIS GND
c1
0.01 µ.F
~------+---o Output 2
(Open Collector)
86
voltage across Ct reaches the threshold of pin 6, the output goes low,
ending the timing cycle. This discharges Ct through D 1 initially, un-
til the voltage decreases to the contact potential of D 1 ( 0.6 to 0.7
volt). Capacitor Ct then discharges more slowly through Rt to its
final level between pulses.
There are some weaknesses to the circuit, primarily involving the
different manner of charging and discharging Ct. An output pull-up
resistor ( R 1 ) is added to force the output completely up to the V +
level in the high state. The value of R 1 should be lower than Rt for
minimum error in timing, if it is not actually included as part of Rt
in the timing cycle calculations.
Diode D 1 can effectively and rapidly discharge Ct, but only down
to 0.6 to 0. 7 volt, when it ( D 1 ) ceases to conduct. After D 1 turns off,
Ct must then discharge through Rt· The period of time required to
discharge Ct completely is longer than in the conventional mono-
stable circuit, and is the major drawback of this circuit. This can
cause timing error and/ or pulse-width change if the circuit is re-
triggered just after a completed output pulse. The circuit is thus not
optimum for high-duty-cycle operation.
Like the basic 555 monostable, this circuit can be enabled by a
high voltage level (or pulse) to pin 4 or inhibited by a low voltage
level. Also, a low voltage level (or pulse) to this pin during the tim-
ing cycle will terminate or reset the output prior to the normal con-
clusion of the timing cycle. These characteristics of reset operation
are identical to those of the standard 555 monostable, and the use
of resetting is entirely optional.
0
W. G. Jung, "555 One-Shot Circuit Features Negative Output With Positive
Triggering," Electronic Design, August 16, 1976.
87
v+
Timing Diagram
R, D,
Input ~----- 213 V+
4.7 kn 1N914
ct ~--v+
R*
I I --l/3V+
_fl_ 4
9lkn Output --L__c--v+ __
Trigger t 6 T~ 3 I I
0
OUT Output l : :
2 - T*-_.,
TR 555 5
v,
C* 7
I
DIS GND
0.01 µF
Trigger
Input
~uToPin6
1000 pF
1N914
OV to +15V
lOkn
88
high duty cycles. An alternate form of this circuit, which eliminates
this problem, is described next.
4
R
_fl n----~--6-1TH 3
OUT ~--------<i Output 1
Trigger 2
-----r TR 555 Ve 5 ov to +15V
ct 7
DIS GND cl
0.01 µF 0.01 µF
~--------------___.., Output 2
89
v+
R*I
1Mn
3
2
OUT 1--------- -<1 Output
~-~---fTR 555 Ve 5
1000 pF 7 DIS I I
~ T*_:
C1 C* GND C3
0.01 µ,F t
O.Ql µ,F 0.01µ,F
v+
~----~-8-tLTR v+ 5
2
V,
3905 c 1---------
6 --u Output
R*
t
1Mn 3 7
R/C E I I
GND ~T~
C*t 4
O.Ql µ,F
90
is depressed are removed by the integrating action of R 1 and C 1 .
The resultant clean negative spike is then passed through C'.! to the
555 as a trigger pulse. This fires the monostable, generating an out-
put pulse of width T = l.lRtCt. Upon release of S 1 , C 1 recharges to
V +, and the circuit awaits the next switch actuation.
The time constants and circuit arrangement of the trigger cir-
cuitry are chosen for a single trigger and output pulse for each
switch depression only. Furthermore, the circuit will not trigger on
switch release and \Vill produce only one pulse regardless of how
long S1 is held down. The circuit will also retrigger as fast as S 1 can
be reactuated.
In some cases, the 5.55 can be triggered more directly by a simple
switch contact from pin 2 to ground. However, this is usually unde-
sirable because the output will remain high after one timing period
if the switch is held closed, which is an undefined mode of operation.
The input triggering network consisting of Ri, R 2 , R 3 , C 1, and C2
eliminates this problem. Although five components are used,none of
them are critical.
The minimum output pulse width of this type of circuit should be
longer than the bounce of the switch used; typically this will be 10
ms or less. Thus, the circuits shown are 10 ms or more in pulse
width.
A circuit arranged for the 3905 timer is shown in Fig. 4-4B. Here a
similar trigger network is included, with slightly different values be-
cause of the lower trigger-input impedance of the 3905. In operation,
Ri charges C 1 upon closure of S1 , which fires the timer, creating an
output pulse of T = RtCt. Although a negative-going output pulse
is shown, it should be recalled that this device can be arranged for
either negative or positive outputs, according to the state of the
logic input. As in the 555 circuit, the switch and trigger circuit is de-
signed for a single output pulse upon actuation of Si, and it will not
trigger on switch release.
0
J. C. Heater, "Monolithic Timer Makes Convenient Touch Switch," EDN,
December I, 1972.
91
because the input impedance will be essentially that of R1, and the
trigger input will not draw significant current when held above its
1/ 3V+ threshold voltage.
With threshold control R 2 adjusted so that the voltage at pin 2 is
held above 1/ 3V+, the circuit will remain in its quiescent state (out-
put low) prior to triggering. When the contact plate is touched, the
body capacitance of the person touching the plate, being effectively
in parallel with the high resistance of Ri, will lower the overall im-
pedance between pin 2 and ground sufficiently to reduce the voltage
at pin 2 to below the 1I3V + trigger threshold. Thus, the timer will
be triggered and will time out, producing an output pulse of width
T = l. lRtCt. The timing period should be made longer than the
anticipated contact time, otherwise the timer will retrigger after
completion of the first output pulse. In the example shown in Fig.
4-5, the timing period is about 5 seconds.
The contact plate can be any conducting material arranged for
convenient finger contact. Also, some type of feedback to the oper-
ator is desirable, such as a lamp or LED to indicate that switching
has occurred as a result of contact.
v+
R,*
4.7 Mn 4 8
,.....;..&.--......_,
6 T~ v+
3
OUT1- - - - - - 0 Output
2
Contact
~----<E----+------1 TR 555 5
SL
Plate Ve I I
R, 7 I I
22Mfl
DIS GND ~T~
C*t
lµF c,
0.01 µ.F
*T = 1.1 R, C,.
(Choose R, and C, for pulse width greater
than anticipated contact time.)
92
v+
Power
Output
V~
Timing Diagram
:
_r--1__
l Normal
Power-Up
Sequence
Rt *
~ T*_:
470kn
4 8
Reset Vb===~) Use of Reset
r-----,L (optional)
.___ _ _6-t T~ v+ 0 utput ____J
I I
3
OUT 1-- - - n Output l :..__ ""'T ___:
2
TR
555 OVto ___jL_
7 +15V
DIS GND
R2
4.7kn
~--,...------e--u Output 2
v+
Timing Diagram
Power v+ j
0 I
Output
v+ J__s-I
0 I I
:~T~
93
threshold is reached, which completes the cycle. A single output
pulse is produced in this fashion, and the circuit will not recycle
without the removal of power.
The preceding has assumed the reset input (pin 4) to be high,
which allows the sequence to occur as described. Once cycled, how-
ever, this one-shot configuration can also be recycled, if desired, by
taking the reset input low. This forces an output-low condition, and
discharges Ct through D 1 and the source. The output will remain low
for the duration of the low state at the reset input. The timer will
then produce an output pulse when the reset input is taken high once
again.
The width of the output pulse produced when the circuit is re-
cycled through the use of the reset input is slightly shorter in time
because of Di, which prevents the complete discharge of Ct. This
is usually of small consequence, since the pulses produced by this
type of circuit rarely require precision. The use of the reset function
is entirely optional, and if not needed, D 1 and R 1 can be omitted. The
circuit has two outputs, the normal pin 3 output (output 1) and
also the uncommitted pin 7 output (output 2). Both produce an
output-high condition during the timing cycle.
A circuit that performs the power-up one-shot function with a
3905 timer is shown in Fig. 4-6B. Both the 322 and 3905 have the
capability of producing an output timing cycle automatically upon
the application of power. As a consequence, there is no triggering
required of the circuit, and it produces an output-low condition for
the duration of the timing period after the application of power.
Upon completion of the timing cycle, the output goes high and stays
high until the power is recycled.
This circuit cannot be recycled with the power on, due to the
absence of a reset function on the 322/3905 timer types. However,
the circuit does have the ability to produce either high or low out-
puts during the timing cycle by use of the logic input (pin 2 on the
322; pin 8 on the 3905). The circuit as shown uses the 3905 since
the timing interval is much greater than 1 ms, but the 322 can also
be used if desired.
94
single trigger input. When the input is driven to zero, it has reached
the threshold level of the reset input. Since the reset function is over-
riding, the output is held low even though the trigger input is below
its l/3V+ threshold. When the input rises, the reset function loses
control and the trigger input assumes command. The output then
rises, and a timing cycle begins.
If no additional trigger pulses are received prior to completion of
the timing cycle, an output pulse of normal width will be produced.
(See the timing diagram of Fig. 4-7 for normal operation. ) The only
difference between operation in this circuit and a conventional 555
monostable is that timing begins on the rising (trailing) edge of
the input pulse rather than on the falling (leading) edge.
When input triggers are spaced at time intervals less than the
normal timing cycle, the cycle will not reach completion and the
output will go low with the falling edge of each input pulse. This is
shown in the timing diagram for restartable operation. It may be
noted that Ct is never allowed to reach the normal voltage level;
thus, the output pulses are not controlled by Rt and Ct in this circuit.
The output is actually an amplified replica of the input.
v+
R*
I
150kn
4 8
R,
4.7 kn 6 T~ v+
3 Output
OUT
Trigger 2
TR 555
5
Ve
LJ 7
DIS GND
C*
t
c,
O.OlµF O.Ql µF
Timing Diagrams
I
Input LJ
Normal
ct ~ Operation
Output J-----LrL
I I
:__ T*_:
* T = 1.1 R, c I .
I
(As shown, T Input
I I
I I
Restartable
c,~
I I Operation
I I
Output 1-JLJ-u-L
Fig. 4-7. Restartable one-shot circuit.
95
Appropriate selection of Rt and Ct can control the .. crossover" time
period when the circuit ceases to function as a normal monostable
and begins restartable operation. This may be anywhere within the
range of component values allowable for the 555.
The circuit of Fig. 4-8 is similar to the circuit of Fig. 4-7 in that it
modifies the normal triggering characteristic of a 555-type mono-
stable during an output pulse. There is a difference, however, in the
fact that the output of the monostable shown in Fig. 4-8 is not reset,
although a new timing cycle is begun. This type of operation is
termed retriggerable.
In this circuit, which is made up of two halves of a 556, section B
is a conventional 555-type monostable with timing components Rt 2
and Ct 2 • This section is triggered by the negative-going pulse from
section A, which is a simplified inverted monostable. The free out-
put terminal of section A (pin 1) is used to clamp Ct of section B 2
v+
R'2*
lSOkn
D1 4 14 10
1N914
v+
n---+----...--2-iT~ 5
12
TH
R
OUT 9
_ _ _ _ _ _6-1 TR 556 OUT Output
'---""---8-1 TR 5 56
Trigger A B
13
DIS GND DIS
c,1
2200 pF
c'2 *
0.1 µ.F
Timing Diagrams
Input _n_____Sl__
I
~
Normal
c,2
Output
I
I
..r-L__lL_
I
I) Operation
I I
:___ T*_:
*T = l.lR, 2C, 2.
_n__n___n__n_
I
Input
I I • I
I I I I
I I I I Retriggerable
c,2
~
I
Operation
Output
96
for the duration of the output pulse of section A, which in this case
is 100 µs. Input triggers to section A are positive, and initiate both
timer sections, since the first section fires the second section.
During normal operation, where the input triggers are received
at a time interval longer than the period of monostable B, the out-
put is conventional and is shown in the timing diagram for normal
operation. Output pulses occur at the input rate, and the output
pulse width is equal to l.lRt,C t.,. When the input period is shorter
than l.lRt" Ct", the parallel dis~harge of Ct2 by monostable A be-
gins to have an effect on the output. This is illustrated by the timing
diagram for retriggerable operation, which shows the voltage across
Ct . being returned to zero with each input pulse. As a consequence,
Ct~ never reaches the 2/3V+ voltage threshold of timer B; thus, timer
B never times out. Under these conditions, the output remains at a
steady, high de level. It wi11 continue to do so as long as input
b·iggers are received at a period less than l.lRt_,Ct,.
This circuit can be scaled to operate at virtu~Ily- any rate consis-
tent with the range of component values allowable with a 555. The
output pulse width of the input section should be maintained at a
small percentage of that of the second section. However, this time
must be long enough to ensure complete discharge of Ct, during the
timing period of the input section. Other than this crit~rion, there
is little that is critical regarding the input section.
97
periods of 10 µ,s or less, some trimming may be necessary with Rt
or Ct because of limitations in predictability and propagation delays.
These concepts can be extended further by using the proceding
circuits or others previously described to build general timing sys-
tems, as shown in Fig. 4-11. Here a "bank" of timers is shown that
are triggered simultaneously by a single input. They produce three
separate outputs of widths T 1 , T 2 , and T 3 , respectively. The actual
timer circuits used could be any described thus far for monostable
operation. The example shown indicates positive triggering with
negative output.
Similarly, a "chain" of timers can be constructed as in Fig. 4-12.
Here, three delays of widths Ti, T 2 , and T 3 are operated in sequence.
Thus, T 1 triggers T 2 ; T 2 triggers T 3 ; and so on, for more delays. This
type of system is also referred to as a sequential timer. It also could
use any of the monostable timers described thus far.
Di R'2**
R* 1N914
•1 Ri 9.lkn
910kn
2
4
,_....
R
__v+ 14
..........,
C1
lOkn
12
10
.----.----.
R
TH TH
ouT~5---..... ~--
9
ouT~----~
Input o---+--6~TR 556 1000pf .__--+-<~8 TR 556
A V, 3 B V, 11
lf DIS GND C1 /* 13
DIS
...__ _____,
c C2
t, * 0.01 µ.F
7 0.01µ.F
0.01µ.f
Timing Diagram
Input lJ I
I
c, 1 •
~
*T 1 =1.lR,
1
98
Timing Diagram
v+
Input __fl__
I
I
I
Output l l___J
I I
Input r.----
11 3 ']]___ ~Ti:.:
2 L TR B 10 TR B 10 :
v+ Ri L v+ R2 ,
~T2.:..*
4 v 322 c 12 lkn 4 v 322 ( ,_1_2__1_kn""' I I
Rt1 *
5
'(3905)
1
Rt2 **
5
'( 39o5 ) Output 2~
RIC GND E 4.7kn l
R/C GND E
c t2**
6 6
lOOOpF
line is low, S2 is "on," connecting Rt., to V+. The timing period then
is l.lRt 2 Ct. Resistors Rt 1 and Rt 2 ca-n be any two resistances within
the capability of the 555.
Although this switching arrangement is sho\vn within a basic 555
monostable circuit, it may also be applied to virtuaJly any mono-
Timing Diagram
Input JL
I
I
I
i-T1~
Input Output l i___r--
I
I
I
I
I
I
iT2i
Output 2 L___j
I
I
I
I
I
~T3---:
Output 3 l r
Fig. 4-11. A "bank" of timers.
99
Timing Diagram
Input LJ I
I
I
Outputl hI I
~TT.;
I
I
Output 2 I I
I I
-T2--:
I
I
I
Input I
I
L
I
I I
..__T3__,.,.
stable circuit discussed thus far. This includes the modified 555
types, as well as circuits using the 322 and 3905.
For remotely selectable monostable timing periods that are in-
tegral multiples of one another, a programmable timer I counter is an
effective performer, as shown in Fig. 4-14. This circuit is in essence
a basic 2240 binary (or 2250 for bed) programmable monostable
+15 v
Enable
r On
_J Off
6
Control
Input
Rt2**
1sv_s-T1 4 8
OV T2 lBOkn
6 R v+
TH 3 Output
OUT
Trigger
2
TR
AT _JL
555
1_f ct *· ** 7 Ve 5
*TT= l.lRtT Ct. DIS GND CT
0.01 µF 0.01 µF
**T2 = l.lRt2 Ct.
(As shown, TT= l ms; T2 = 2ms.)
Fig. 4-13. Selectable-time programmable monostable using 555 type.
100
v+
')
•A
~·
"" R2
10 8 3 l lOkn
t 54 ) S3 . 52 ,, 51
~ 7 ' A2 14
air r ri r,
:;· ~ I 4016 16
DI I I I i
I I I I v+
-< R1 . R,*
12 11 6 9 5 4 131 2 REG
i A1 22kn • lOOkn
Input l -- l lT 2240 (MOD) 15 .....
~ 14 l
.2:: Control 2 -
J 2 2T (Binary) TBO
"a 3 13
Lines* 4 -- 4T 2250 R/C
c; 4 BT (BCD)
~ 8 -- C,*
DI 5 16T (lOT) MOD
3 -
16 (10) -
6 (CO)
..lL :.;: 0.01 µF
3
DI
32 (20) v 32T(20T) Jl
7 64T(40T) 11 ~
Ir -
64 (40) - TR Input
i" -
128 (80) - S 128T(BOT) R.J_O
3
0
:I 12 10 6 8 5 3 131 1 :-;:: c1
0
!.!:. I GND 0.01 µF Timing Diagram
DI s : s,
Ir I I 54 : CJ 53 : ) 2 I I
7 A3 91
i" L L L L
)
~ 4016 14 Input
c +- JL
!!!. +- I
:I I
ca I
11 9 4 2
N
N r Output 1 i--f
0
. r,·7
i where, Output 2
s---L
1 ,
N
N I T *I
UI n = weight of digital input word: t CMOS inverters. ._ 0-
g 1 ~ n ~ 255 (binary))
.:<" ( 1~ n ~ 99 (BCD)
"a
!' As shown, T = 1 ms:
for 2240, 1 ms ~ T0 ~ 255 ms)
( for 2250, 1 ms ~ T ~ 99 ms
0
g
circuit, to which digitally programmable switching has been added.
Here, the timing is programmed by A2 and A3 , a pair of 4016 CMOS
quad analog switches. The combination of 2240 (or 2250) timing
taps connected to common load resistor R2 will determine the total
monostable delay, as shown in Fig. 4-14. A given timing tap is acti-
vated when the corresponding digital control input is high and is
"off" when the control input is low.
With a 2240 used as shown, timing is programmable from the
minimum basic interval of 1 ms, up to 255 ms. A 2250 may also be
used (note the minor pin differences at pins 12 and 15), which would
yield programmable timing of 1to99 ms.
A CMOS output buffer stage as shown is recommended for com-
pletely valid logic levels. This is because there is some deterioration
of "O" and ''l'' states at R 2 , due to the additional "on" resistance of
switches A 2 and A 3 , and also loading at the reset input. The circuit
will operate over 5 to 15 volts, but operation is optimum at a V+ of
10 to 15 volts.
Standard applications of both the 555 and 322/ 3905 timers allow
timing periods that extend into the range of several minutes. The 322
operating unboosted (or the 3905) can reach even into the hour
range, if high-value components are available. There are, however,
many situations requiring long timing periods that can benefit by
reduction in value of the timing components. From a system stand-
point, this is usually desirable, since high-value capacitors and re-
sistors are both expensive and hard to obtain. Two methods of
achieving this goal are shown in Figs. 4-15 and 4-16.
In Fig. 4-15, a 322 timer is illustrated in a monostable circuit that
extends the range of the timing components by two orders of magni-
tude. In this circuit (as opposed to a normal 322 monostable), it
will be noted that Rt is returned to the junction of R1 and R2 rather
than to the reference voltage (pin 4). Resistors R 1 and R 2 reduce
the voltage applied to Rt to a fraction of the reference voltage of
3.15 volts. Resistor R 2 is returned to the output of A2 , which serves
as a buffer for the timing ramp across Ct. This technique effectively
"multiplies" the value of Rt by the inverse of the R 1-R 2 division ratio.
In this case Ri and R 2 have a 100: 1 ratio, which increases the ap-
parent value of Rt 101 times. The resulting new timing expression is
then:
or
102
v+
T6gge<~
R2*
,p~
lkn
3
v+ 10 R4
R,*
4.7 kn
7.5Mn 12
C t-- ---u Output
RJ
C2 lkn
~ C,*
0.lµF 4.7 µF Timing Diagram
Input .JL
V- I
*T = R1 +R R2(R C) : ~--2V
2
I t.
c, --(' L-ov
I
--,L__JI __
-v+
R R = 101 ,
Output ov
For R1 + 2
I I
2
:_ T*~
T = lOlR,C,. (As shown, T = l hour.)
103
v+
i (+10v to +15V)
Timing Diagram
c2 R*
1 RJ Input LJ
__c-1 I
lSOkn 4.7kn I
~O.lµ.F
c, YL
I I
R4 R2*
r-------
I
~·
"" Output h
lOOkn 2kn I
I I I
t
!"
~ T*~
A OUTI 3 Output l
2ITR 1
i:::J 555 v,' 5
Q., 71
Ill DIS
9- GND
iil
:::J Output 2
ca
Ill
3
- -4
0
:::J 141 A3
0 c1
!!I. 4016
Ill
'ii- : ""'"10,ll,12t 0.01 µ.F
IT
i"
c
!!!.
31
w6.8.
5 2
:::J
ca
"'"'
-<"' I
'a R1 + R1 (l.lR,C,).
!' 0----------------------------------~ *T = R2
Enable S ~
R, + R2 _ 100
For _R_2_ - IT '
A useful option available with both the 5.55 and 322 timers is the
ability to control their output pulse width with a variable voltage.
This feature may be used to either trim the pulse width to a desired
time interval, or to control it from an externally derived voltage for
voltage-controlled (or modulated) applications. This technique is
illustrated in Fig. 4-17.
In Fig. 4-17A, a 555 monostable circuit is shown with a control
voltage applied to pin .5, the voltage-control pin. To trim the pulse
width to a desired time, a 10-k.n potentiometer, Radh can be con-
nected across the V+ line as shown, with its arm going to pin 5. Vari-
ation of the potentiometer output will then vary the timing period
of the monostable (over a fairly broad range, if desired). With the
potentiometer connected in this fashion, operation will continue to
be supply-voltage independent.
v+ v+
.--~~~~·-------,
I
I
I Input n-------.
8 I 3
I
V+ I 2
L
TR
3 I
OUT 1
Input 2 Output :
~f'--41,___,TR
555
I
c 12
I Output
I
7 I I
DIS GND __$Rodi I
c, Co~t~ol-~ lOkn :
Voltage~ Rodi ~
1 kn~ Control'-----~--'
+voltage
105
An external voltage can also be applied to pin 5 (in lieu of the
potentiometer) and will vary the timing period also. This can be
used for pulse-width modulation, for instance. Operable limits are
from approximately 12 volts down to 2 volts at a V + of 15 volts, and
proportionately less with lower supply voltages. The pulse-width-
versus-voltage-control characteristic is not linear.
A 322 timer can also be operated in a voltage-controlled configura-
tion, as shown in Fig. 4-17B. Here the 3.15-volt internal reference
voltage is applied to a l-k!1 potentiometer, Radj, with the arm applied
to the control-voltage terminal, pin 7. Operation is generally similar
to that described for the 555, but a greater dynamic range of control
is possible. The timing may be adjusted about the nominal 2-volt
setting for trim purposes or may be taken all the way to zero for
extreme variation in pulse width. The dynamic range of adjustment
capability of this circuit approaches 100: 1 or more. Furthermore,
due to the internal regulator, it is highly independent of supply volt-
age.
Although operation is basically nonlinear, it can be made approxi-
mately linear if the pin 7 voltage is a small fraction of 2 volts; that
is to say, very low on the R/C charging curve. External voltages can
also be applied to this circuit for pulse-width modulation, if de-
sired.
A 2240 programmable timer I counter may also be voltage con-
trolled, as shown in Fig. 4-18. The time-base section of this device
is somewhat similar to that of a 555 in operation, with the voltage-
control terminal (pin 12) nominally at 2/ 3V+. It is adjusted or mod-
v+
------,
R2 I
R, I
lOkn 16 R, I
22kn I
lT v+ REG 15 I
14 I
2T TBO I
13 I
4T R/C
Program I
ST 2240
as
Desired
MOD
12
~Radi
Contro 10 kn
11 Voltage 1
TR I
10
R I
c, I
I
9 I
L-------~----~-~=-----E--o Output
..._------E'---+------~
Input
106
ulated in a manner similar to a 555. Similar comments apply to the
other members of the timer/ counter family.
The safe limits of the control-voltage pins must be observed with
any of the devices used in voltage-controlled circuits. Care should
be taken in lead length and dress, as extraneous noise introduced
into a control terminal can induce undesirable jitter on the output
pulse.
+uv
7
TR 555
DIS GND
v ------<
5
R3
10 kn
C,* *for V+ of 15 V:
0.01 µf v c, 4.2
T=-',-, 1t~R'
t t
I
v, 6 T == 0.24 V, R,C,.
(Control Voltage) (As shown, Tmax == 1 ms with
V,= 10 V.)
107
would be 2/3V+; here, it is generally termed Ve. When the Ct volt-
age reaches Ve volts, the timing cycle ends. The general timing ex-
pression for output pulse T is
T = VeCt
It '
where Ve is the voltage at pin 5, and It is the current supplied by Qi.
Current It can be approximated for a V + of 15 volts as
It= ii~.
Then Tis
T 0.24V eRtCt. =
Note that this expression is not exact. As a particular example, if
Ve= 10 volts, Rt= 47 kn, and Ct= 0.01 µ,F, T works out to be
slightly over 1 ms. Current It is, of course, linearly variable by R 3
or by an external voltage applied to pin 5.
In general, It should be 1 mA or less, and Ct can be any value
compatible with the 555. The dynamic range of Ve in this circuit is
4: 1 or more, operating at 15 volts. The circuit will function at lower
voltages, but with some sacrifice in stability and accuracy.
Another simple, linear-ramp monostable circuit is shown in Fig.
4-20. This circuit uses a 322 as the timing device. In this circuit, Qi
is the constant-current source, developing a timing current, It.
Transistor Q1 provides a constant current that is effectively regulated
v+
Trigger 0------------.
Timing Diagram
R,*
LED 1 lOOkn Input _fL
r---- I
MV5020 Ql I
(or equiv.) C : /"1 ----V,
2N3906 ,........._3_ __._'l~l '~ L--ov
2 TR 8 10 I
Q2
L V+ Output --i____r-
1 I
2N3904 :,._ T....:
Ri *T = V,Ct I a_!_
1 kn It I t Rt
C,* Tao V,RtCt
0.1 µ,F
(As shown, Tmax = 30 ms
I with V, = 3 V.)
6
108
by light-emittin g diode LEDi. The typical LED forward voltage
drop of 1.6 volts is applied to Qi, causing about 1 volt to be dropped
across Rt. The timing current flowing in Q 1 is then
1
It=-·
Rt
The general timing expression for output pulse T is
T = V(,Ct.
It
With substitution for It, this becomes
109
5
It = 50 µ,A + (1it ).
This constant current charges Ct, forming a linear ramp of voltage
at pin 5 of the 322. The same voltage also appears at the ramp out-
put, shifted upward 1.25 volts (the output voltage of the 317).
Loading at the ramp output does not affect the timing.
The high performance of both the 317 and the 322 enables this
circuit to be very stable and highly immune to supply-voltage fluc-
tuations. The width of the output pulse can be varied over a range
of about 100: 1, from a Ve of 3 volts downward. Due to the speed
capability of both devices, operation down to a few microseconds of
output pulse width is possible.
In the example of Fig. 4-21, the conversion sensitivity is 100 µ,s
per volt of Ve. Conversion sensitivity is set by Rt, which trims It. It
is best to maintain It within the range of 100 µA to 1 mA. (Note that
part of It is due to the 50-µ,A bias current from the ADJ terminal of
the317.)
The circuit of Fig. 4-22 uses an extension of the principle set forth
in Section 4.14 to create a timer that features an even wider range of
operation, in addition to the basic feature of linear voltage control.
v+
Timing Diagram
OUT
1-----~~--~~-- ~-~~-oRamp
Output lnput_JL_
o, I
R,* 1N914 RJ
Ramp
l l.25V + V
~--- '
1.3 kn lOO!l
Output : 1
---1.25 V
I I
3
-Lr I I
I,* i A,
R2
4.7 kn
Pulse
Output 1
:_. T*_:
1
4
v 322 t - - - - - - u Pulse
Output
5 R/C E
C*t v0 GND *
T = -v,1-c, , where,
0.1 µF 7 6 1
l.25
RI l,=50µA+R,.
l kn
(As shown, T/V, = lOOµs/V.)
110
v+
{+lOV to +15V)
OUT
Ramp 1
Timing Diagram
Pulse r---i
Output _J L
I I
~T*_:
Input
3
v- 2 10
c2 (-5V to -15V) LTR v+ R5
.0.1/LF+ A1 12 lOkO
...---------~-+-iv, 322 4
c.....-----u Pulse Output
C*
I
E 1 5 R/C
~l~k~n--·-----~~V0=--~~
GND
4.7 ILF 7
*T = V, R, C,
v,.1
(As shown, T = 1 hr with V,= 3 V and V, 01 calibrated for 0.3 V.)
This circuit is easily calibrated and adjusted, and has a variable tim-
ing range of up to one hour.
In this circuit, a 322 is again used as the basic timing device, but
with the constant current for timing supplied by a current source
consisting of A2 and As. Amplifier As is a FET-input op amp, used
here as a buffer to isolate the high-impedanc e R/ C timing node. The
typical 30-pA input current of this device ensures that the major
bias-current error of the circuit is that of the 322 ( unboosted) . This
allows It to range downward to about 1 nA for predictable operation.
Since As is connected as a voltage follower, it "bootstraps" the
timing voltage created across Ct. A replica of this linear voltage ramp
appears as Ramp 2. During the timing interval, Ramp 2 will sweep
from zero volts up to Vc (the control voltage), which is applied
either via R4 or from an external source.
The 1.25-volt three-terminal regulator, A2 , "floats" atop the Ramp
2 voltage. It maintains its 1.25-volt output across R 1 and R2 , and
thus also delivers a level-shifted output, Ramp 1. Ramp 1 will sweep
from 1.25 volts up to 1.25 volts plus Ve during the timing cycle.
111
As the voltage across R 1 and R 2 is maintained constant at 1.25
volts, any portion of this may be picked off via R1. The voltage be-
tween the arm of R 1 and the Ramp 2 bus is also constant, and is
termed V ref· This low and constant voltage is applied across Rt (by
virtue of the op amp) to set up the constant timing current, It, which
is simply
I _ Vref
t - Rt'
where V rpf is the voltage selected by Ri. Here, V ref can range from
less than 0.3 volt up to 1.25 volts. The timing equation is then
T= VeRtCt
Vrpf .
112
and the pulse width is linearly variable via Ve. The feature of the
circuit that makes it ratiometric is the type of constant-current source
used. Here, Qi sets up a current through R 2 • This current will be
equal to the 322 reference voltage divided by Rt, since the V1m of
Q1 and the V BE of Q:! cancel each other. The op amp, A2 , causes the
current in R:! to be duplicated in Ra. The current in Q2 is then used
as the charging current for Ct. Various values of Rt can be connected
from the emitter of Qi to ground, and will program a corresponding
Trigger +15V
Ql
2N3904
C,,,
vm o--H-- 2N3906
Q2
Output
o.11-1F
I, i Timing Diagram
Input JL
I
R,* : __.....,---Y
R,
100 k!l 0 C, ~ L--0~
l k!l I I
V/ r------1 --- v +
Output ~ ~--O V
* V,R,C, . ~ T*-~
T= -v-' where, v,.1 = 3.15 V, and v, IS a percentage of v,.1·
<el
timing current in Ct over a wide range. Values for Rt can span two
to three decades ranging from a minimum of 50 kn upward. How-
ever, if a three-decade range of operation is desired, the offset volt-
age of A2 should be nulled with R;;, an optional trim network, and
the boost connection on the 322 (pin 11 ) should be deleted.
The circuit is ratiometric because with a given timing current set
up in Ct, which is proportional to the reference voltage of the 322,
a percentage of this reference voltage is used as V<:· Therefore,
changes in Vref cancel out, in a manner similar to the basic timing of
the 322 as an exponential ramp timer.
113
The circuit is quite flexible, and can be set up for a wide range of
operational modes other than that shown. For example, it may be
used as a linear pulse-width modulator by applying an ac signal to
the optional Vm point as shown. Rm is a series resistor used to scale
the peak modulation current so that it is equal to It; it should be
equal in value to Rt with peak modulation voltages of 3.15 volts.
Capacitor Cm is an ac coupling capacitor chosen for the desired 3-dB
rolloff point ( 16 Hz as shown). If modulation is not used, and Rt is
I M!l or less, a 741 may be used for A2 without the offset nulling.
REFERENCES
1. Lefferts, P. A. "LED Used as Voltage Reference Provides Self-Compensating
Temperature Coefficient." Electronic Design, February 15, 1975.
2. Litus, J. Jr.; Niemiec, S.; Paradise, J. Transmission and Multiplexing of
Analog or Digital Signals Utilizing the CD4016A Quad Bilateral Switch. RCA
Application Note ICAN-6601, August 1971. RCA Solid State Div., Somer-
ville, N.J.
3. Sherwin, J. S. The Field Effect Transistor Constant Current Source. Siliconix
Application Note, January 1971. Siliconix Inc., Santa Clara, Calif.
4. Siliconix Application Note AN73-7, December 1973. An Introduction to
FETs. Siliconix Inc., Santa Clara, Calif.
114
5
0
S. A. Orrel, "IC Timer Plus Resistor Can Produce Square Waves," Elec-
tronics, June 21, 1973; Copyright © McGraw-Hill, Inc., 1973.
115
high-state saturation limit of a 555 is nearly 2 volts below V+. This
causes some time asymmetry in the waveform, particularly at low
supply voltages near 5 volts. The timing period would be simply 2 X
0.693RtCt (or l.386RtCt) were it not for this error. In light of this
error, the time equation given is approximately l.4RtCt, and this will
vary with differing supply-voltage levels. However, even in view of
this limitation, the circuit is still quite useful due to its inherent sim-
plicity and low cost.
v+
Timing Diagram
R,*
iso ko 4 8 c,~
I I
6 R v+ I I
TH
OUT
3 Output s-LJ
I I
2 555
TR :.__ T*____:
5
v
C,* GND *Ti0i l.4R 1 C 1
0.01 µ.F c1 0.7
0.01µ.F fo;;;;ER(
I I
116
v+
RI
l kn
Output l
R.*
4 8
75 kn R
6 v+
- - ---1TH
OUT
3 ov to +15v
2
..,__--'--ITR 555
7
v, 5
C,* DIS
GND
0.01 µF c,
0.01 µ.F
Output 2
* R1 ~ R,, T = 1.386 R, C,
f - _!_ - 0.722
0
- T - R,C,
(As shown, f 0 S!! l kHz.)
except for the fact that R1 is made a very small fraction of Rt. This
will provide a nearly equal charge and discharge resistance path
for Ct. As a result, the timing periods are equal, or at least equal con-
sistent with the match of resistances. In practice, the output very
closely approximates a square wave.
A virtue of this configuration is that the timing network is not
driven from the output; therefore, loading at pin 3 will have no ef-
fect on timing. Pin 3 may then be loaded on a relatively unrestricted
basis.
v+
4.7 kn T = l .386R, C,
0.722
R,* fo=R(
8 I I
lM!l 150
6 v+ (As shown, f 0 :::= Hz.)
3 Output
OUT 1 - - - - - - u
2
TR SSS
v 5
7
L . . - - ---1 DIS
C* GND
c,
4700 pFf~~~~~~~~-~~~~~~
1
0.01 µF
117
While the circuit of Fig. 5-3 is an effective means of producing
square waves, there will be situations where the necessary constraint
of a large ratio of Rt to Ri will be prohibitive. An improved version,
shown in Fig. 5-4, removes restrictions on the value of Rt. Here, the
resistor corresponding to Ri of Fig. 5-3 is removed and replaced by
a FET switch, Qi. Transistor Qi is a device selected for an "on" re-
sistance of 100 ohms or less. Since 100 ohms is at least 2 orders of
magnitude smaller than a lower Rt limit of 10 kn, this configuration
will guarantee square-wave symmetry to within 1% or better, down
to Rt= 10 kn. For timing resistances higher than 10 kn, asymmetry
due to Rt mismatch is even less.
v+
(+l2V to +15V)
Ri
Q1 4.7kn
El 13,
2N4861
R*I 8
R v+
.,._-+--+--6-1TH 3
OUT i - - - - - - - < . . i Output
2 TR 555
v, 5
7
DISGND
C,*
C1 *T = l.386R, C,
0.01 µF 0.722
fo = R, C,
118
v+
R1
lOOkll
4
R/
6 6 R
260Mn TH
A 1 OUT 1-3- - - 0 Output
2 555
TR
7
C,* DIS GND
10 µF cl
O.OlµF
*T =
1.386 R, C,
(As shown, T = 1 hr.)
Fig. 5-5. Square-wave astable with range extended by buffering the timing network.
a I-hour timing interval. This is not the upper limit of the circuit
by any means, as Rt can be much higher if the leakage resistance of
Ct and the surrounding circuit is also appreciably higher.
The use of a buffer stage as A2 is applicable to other timer cir-
cuits as well, either to extend the range of Rt and Ct or to provide a
v+
Ri
4.7 kn
R2*
lMn
R,* R3 *
4 8
36Mfl 14 kn R v+
6
TH
A 1 OUT1-3- - - 0 Output
2
TR
555 v, 5
7
DIS GND
C,*
c,
lµF'T~---~-----------------~ 0.01 µf
R +R
*T = ~ (1.386 R, C,)
3
R2+ R _ 100
for -R-- 3 -1.
3 386
, T = 100 R, C,.
(As shown, T = 1 hr.)
119
buffered version of the timing waveforms for external use when de-
sired.
A very useful extension of the buffered timing network is shown
in Fig. 5-6. Here, another FET op amp, the 3140, is used as the
buffer for the timing network, but additional circuitry is added to
effectively "multiply" the value of the timing components. This cir-
cuit is similar to that of Fig. 5-.5 in that pin 7 of the 555 switches the
voltage applied to the timing network between V + and ground. In
Fig. 5-5, however, the switched voltage is applied directly to Rt. In
the circuit of Fig. 5-6, the voltage appearing across Rt is first scaled
down by the voltage divider consisting of R 2 and R 3 • ·with the "cold"
end of R 3 returned to the output of A 2 , this has the effect of multiply-
ing the effective value of Rt by the division ratio of R2 and R:~.
The actual ratio selected for R 2 and R 3 can vary over a wide range,
as long as the square wave of voltage appearing across R:{ is about
50 m V or more. In this circuit, the ratio is chosen to be 100 times
the reciprocal of twice the natural log of 2. This makes the timing ex-
pression for the astable simply
If desired, R:{ can be used to trim the timing period. The output
waveform will remain essentially square, as long as R:~ is maintained
much larger than R 1 • This circuit is also supply independent in oper-
ation, as is the basic 555 astable.
An even further extension of the idea of "multiplying" the timing
component values is shown in Fig. 5-7. \Vhereas the circuit of Fig.
5-6 multiplied the resistance value, this circuit multiplies the capaci-
tance value. With the exception of op amp A2B, this circuit is identi-
cal in concept to the basic buffered square-wave astable of Fig. 5-5.
Note, however, that Ct is not returned to ground in this circuit but
to the output of op amp A 21h which is an amplifier that functions as
a capacitance multiplier. The basic timing waveform, which appears
at the output of op amp A2 A, is amplified by the ratio of R3 to R 2
and fed back to the bottom end of Ct. This increases the effective
value of Ct by the ratio of the gain of the A2B stage, or R3 / R 2. In this
example, the value of Ct is multiplied by 4.7, making it effectively a
4.7-µ,F capacitor rather than a 1-µ,F one.
The penalty for this "electronic gain" in capacitance is the addition
of the amplifier stage A2 B and the necessity of a negative supply. The
negative supply is not inherently necessary for operation, but for
practical gain values, it is. To obtain useful gains in capacitance, the
A2B stage should amplify by a factor of 2 or more. To do this, it must
be capable of swinging large amplitudes at its output, since its input
is V +I 3 volts, as set by the 555. In the case here, the gain of 4.7
causes A2B to develop over a 20-volt p-p output at a V + of 15 volts.
120
v+
(+10v to +15V)
R,
lOOkn
4
R
~--~~---~~----+~-----. TH 6
3
R,' OUTt------<..J Output
2 A,
15M!l TR
555 v, 5
R2 * 7
DIS GND
lOkO c,
D,
1N914 0.01 µF
C,*
1 µF
v- R
For~= 4.7, T = 6.5 R, C,.
(-lOV to -15V) R2
1 0.154
f=- =--
T R, C,
(As shown, T ;;;;,; 100 s.)
Fig. 5·7. Square-wave astable with range extended by buffering and by
capacitance multiplication.
For this reason the V- supply should be equal and opposite the V +
supply.
The circuit is supply independen t in operation, and works well
over a 10- to 15-volt range. Other op-amp types may be used instead
of the 358 type shown. For example, a FET type could be used for
the voltage follower. The amplifier stage is not critical in terms of
amplifier type, except from the standpoint of output swing capa-
bility. The 358 or 324 types are noteworthy in terms of this param-
eter.
It would seem that the marriage of resistance and capacitance
multiplicatio n techniques just described should be capable of yield-
ing effective RtCt multipliers of several hundred. The proof of this
theory is left as a classic "exercise for the reader."
121
verting comparator by connecting the reference terminal to pins 2
and 3. This disables the discharge transistor and allows pin 5 to be
freely used as a comparator input. Then, by connecting the RtCt
network around the device, the circuit can be made to oscillate by
introducing positive feedback to the Vadj input, pin 7. The voltage
thresholds established at this terminal will determine the end limits
of the RC charging curve, which appears across Ct.
When the comparison voltages at pin 7 are chosen to be 1.96 volts
and 1.19 volts (for high and low thresholds, respectively), the timing
expressions for t 1 and t 2 become 0.5RtCt. Quite conveniently, this
makes the total period ( T) of the square wave simply l.ORtCt. The
circuit shown in Fig. 5-8 accomplishes this in somewhat rudimentary
fashion by the use of diodes D 1 and D 2 • The main asset of this tech-
nique is simplicity. When the output is low, D 1 and D 2 pull pin 7
down to their threshold voltage of about 1.2 volts. When the output
is high, pin 7 reverts to its normal potential of 2 volts. This nominally
achieves the desired objective of 1.96-volt and 1.19-volt thresholds,
but the accuracy and stability of the circuit are limited by the diode
voltage.
The output is a square wave, with an amplitude equal to the refer-
ence voltage. This makes the output TTL compatible, and the use
of the reference voltage for timing makes the circuit highly immune
to supply-voltage fluctuations, as in a 322 monostable. The circuit
can use the full range of timing components available to the 322,
and judicious use of the boost te1minal allows either high speed or
v+
3 R, Timing Diagram
2 TR 1 kn
L
Output ~ ,,,,...---- 1.96 v
4 v' 322 c .....1_2--------- u C t ...../
I
iI ~-------
I
1
I
1.19V
I
5 R/C E 1
o, I
I
I
I
I
I - - - 3.15 V
Vo 1N914 Output ~--OV
I I I
7 ~ t,~ 12:.:
02 I I
I I
1N914 :,.___ T*___;
C* lOOkn T= t1 +t 2 =R, C,
I l~pF f=2._~_1_
T R, C,
(As shown, f = 100 kHz.)
Fig. 5·8. Type 322 square-wave astable circuit.
122
very long timing-period operation. The boost terminal should be
used above I kHz.
16 Ri
R,*
22 kn
v+ REGi-1_5_-vvy, 39 kn
TBO 1-1...;..
4 -+----
"
R/C i-1_3_ _ _ ____,,
Frequency 2240
Programming*
12
MOOi-- - - - . C*
t
0.01 µF
c1
O.Olµf
L---------------0 Output
* - 1
f0 -
2 nR,C,' where,
As shown:
n f 0 (Hz)
1 1280
2 640
4 320
8 160
16 80
32 40
64 20
128 10
123
this ensures an output square wave for any frequency selected. Since
the 2240 is also programmable, it actually yields an entire range of
frequencies that can be programmed in binary fashion. If the time-
base frequency is set to be a power of 2, the submultiple frequencies
available with programming will fall as integer frequencies, as shown
in the table of Fig. 5-9.
The circuit of Fig. 5-9 can also be made digitally programmable,
in terms of output square-wave frequency, by substituting an analog
switch for the simplified programming shown in Fig. 5-9. This cir-
cuit is shown in Fig. 5-10. Here, A2 is an eight-input, one-output
CMOS multiplexer-th e 4051. This device has a three-line, channel-
select control-inputs A, B, and C. These inputs are used to select
one of the eight possible switching paths through the device. With
all Os for instance, input pin 13 is connected to output pin 3. As used
here, this programs the output to a frequency of %nRtCt, where n
is the number represented by the digital input word. As may be seen
by the truth table, this three-line control may be used to select any
one of the eight basic output frequencies of the 2240, and all are
square-wave in form.
Output buffering is recommended for use with this circuit, and
can take the form of a simple pair of CMOS inverters as shown. In
the example of Fig. 5-10, the basic frequency is 1 Hz; thus, the pe-
riod is 1 second. As the frequency is divided, the time is multiplied;
thus, this circuit will yield outputs with periods of 1, 2, 4, 8, 16, 32,
64, or 128 seconds.
124
v+
R,* 1 Mn
16 16 R1
Input 13 l v+ REG 15 22 kn
14 2 lT 14
Control TBO i -_,t--~
Lines 15 3 2T
1------14T A1 R/C t-1_3E-----
t-12_ _4--t T
8
Inputs 1 5 T 2240 MOD 12
16
5 6
32T
3 2 7 0.5µF
Output 64T
4 8
128T
GND
7
c 0.01
8 9 1 µF
Outputs
*Truth Table
tcMOS Inverters. Input Output
C B A n f.
0 0 0 l 1/2 R, C,
0 0 l 2 1/4 R,C,
0 l 0 4 1/8 R, C,
0 l 1 8 1/16 R, C,
l 0 0 16 1/32 R, C,
l 0 1 32 1/64 R,C,
l l 0 64 1/128 R, C,
l 1 1 128 1/256 R, C,
125
~
-°"
v+
Timing Diagram
Output l u-l.
I I I
::!! t I I
tp Enable I I I
rOn
~ Output 2 _fl__f
I I
_J Off I
- ~tt:-:
d
c : ~t2*.:
I I
!.. I I
0 ---T*--
:I
~
:r
~
Ill
;.
O"'
i"'
ft
~- *ti= R,1 c,1
~- t1 = R,2C'2
T=t 1 +t 2
l
f=-
T
v+
Output 1
Output 2
Output 3
I
3 '11
"'l'I 2~ 8 110
«?" A v+ RJ
3
~ 4.v, 322 c I 12 4.7 k!l
~
ri
:r E
..;· GND
O.lµF
:::
II
1c1 6
.,...=-
i"
g. Timing Diagram
ft
Outputl~
t2 = R,2 C,2
:,.t2~
I I
t3 = R, C, 3
3 Output 2 II IL__Ir - - ; -j- iL__jr
I I I
T= t1 + t2 + t3 : :,._ t3~
Output 3 _J---i___j----1
l I I
f= r I I
I I
-r*-
-tS
With three timers within the loop, the timing periods are ti, t2,
and t 3 , and they will be generated in the sequence as shown. As
previously, there are no inherent limits of any one timing period
with respect to the others. The total period, T, is the sum of the
individual periods, after which the cycle repeats itself.
This type of astable is useful where a prescribed sequence of tim-
ing events is required, with timing periods of an arbitrary relation-
ship.
(>T. vV. James, "Single Diode Extends Duty-Cycle Range of Astable Circuit
Built With Timer IC," Electronic Design, March 1, 1973.
128
+15V
Timing Diagram
68kn
R'b * c,~
I I I
I
DI 75ko I
I
I
I
I
4 8 I I I
1N914
'-------...--1rHR
6 v+ Output Sl__jl_
OUT ~3------() Output
I I I
:_ti*~ t 2 *..:
2 TR 555 : :
Ve 5 ~T*~
7
DIS GND
C,* c,
0.01 µF 0.01 µF
T=t 1 +t 2
fa =.: T
0
M. S. Robbins, "IC Timer's Duty Cycle Can Stretch Over 99%," Elec-
tronics, June 21, 1973; Copyright © McGraw-Hill, Inc., 1973.
129
+uv
Timing Diagram
R *
'o
l3Mn c, ~
I I
I I
R * I I
'b 4 8 I I
10,000 times Rtb, which yields a ti/t2 ratio of 10,000:1. With Ct equal
to 0.1 µ,F, the circuit will yield a 100-µ,s output pulse once every
second.
A very interesting version of this circuit results when the timing
resistances, Rta and Rtb, are made the center-to-end resistances of a
single potentiometer. With the arm of the potentiometer centered,
Rta = Rtb, so the duty cycle will be 50%, producing output square
waves. As the arm is varied to either side of center, Rt increases
as Rtb decreases (or vice-versa), but the total resistance r~mains the
same. As a result, the duty cycle can be varied without changing the
operating frequency with this type of adjustment.
5.9.3 Astable With Independently Adiustable Timing Periods
and Auxiliary Output*
The circuit of Fig. 5-15 is very similar to that of Fig. 5-14, but it
has one additional resistor, R 1 • If desired, an auxiliary output is
also available across this resistor; it is shown as Output 2. Loading
must be kept light at this terminal, if used.
0
A. R. Klinger, "Getting Extra Control Over Output Periods of IC Timer,"
Electronics, September 19, 1974; Copyright © McGraw-Hill, Inc., 1974.
130
+uv
Ri
1 kn
o, 02
1N914 1N914
R * R * 4 8
'a 'b
'--~--~---~~------1TH
6 R v+
OUTi-3--~ Output 1
2
TR 555
v, 5
7
DIS
GND
C,* cl
O.OlµF
I
L ________ -----------0 Output 2
t1 = 0.76R 10
C,
t2 = 0.76R 1 b C,
Fig. 5-15. Astable with independently adjustable timing_periods and auxiliary output.
The timing components ( Rta, R tb, D1, D2, and Ct) perform func-
tions similar to their counterparts in Fig. 5-14. If R 1 is made much
lower than Rta' Rta will be dominant as the timing resistor. The tim-
ing equations are then simply t = 0.76RtCt, where Rt is Rta or Rtb. It
should be noted that any loading at the auxiliary output can influ-
ence the timing if it alters the high- or low-state voltage. Output 2
is therefore most suitable for CMOS or other minimal loads.
0
J. P. Carter, "Astable Operation of IC Timers Can Be Improved," EDN,
June 20, 1973.
131
two monostable networks time-share the 555 level-sense circuitry,
alternately charging and discharging their respective capacitors.
The time relationships between the two monostable circuit halves
may be noted in the timing diagram.
This circuit has no drawbacks from the standpoint of limited
supply-voltage range or temperature sensitivity, as do those pre-
viously discussed. Its disadvantage is the requirement of two tim-
ing capacitors as well as two timing resistors, which can make the
matching of timing periods more difficult. Obviously, however, there
is no interaction between timing networks, and the circuit can utilize
the full range of component values usable with the 555.
v+ Timing Diagram
Enable
I
: ./'1--2/3V+.71
Enable o-------- C, a -Y ~ 0 V _,/ L
r On (I~:---v+
..J Off R, * 4 8 RI 'b I
I
I
I - - - - - - - 2/3V
+
Output~-- v+
0
6 R v+ l kn
TH I I ov I --
:. t 1 *.!-- t 2*~
3
OUT t-- - - - - + - - + - - 0
2 TR SSS Output : 1
R1 b* :__T*-___:
1
7 5
DIS GND V,
DI *t 1 = l.lR, C,0 0
1N914
t2 = l.lR,b C,b
c 'a *
T=t 1 +t 2
= l.l(R, 0 C, 0 + R,b C,b)
l
fo - r
0.91
This circuit can easily be gated "on" and "off" by the use of the
reset pin (pin 4) as shown. When this pin is low, the output is held
low. When the enable line is taken high, the circuit starts oscillating
synchronously with the t 1 period. The first cycle (and all succeeding
cycles) are of the proper width, unlike the conventional 555 astable
when gated.
132
+uv
R, 14
4.7kn
A2
4016
4
680n s,
2
I Output l
L-- 3
13 A, OUT
2
TR 555
5
+s v to
4
52
3
vc +15V
7
I DIS GND
__ J
R2
5
4.7kn
C,*
53
9 1 µF Output 2
RI b* 6
lOMn 7 c1
0.01 µF
*t1 = 0.693 R, C, 0
t2 = 0.693 R,b C,
T=t, +t 2
= 0.693 (R, + R,b) C, 0
l
fo = r
1.44
133
then of the form t = 0.693RtCt. This also makes the total timing
P eriod the sum of t 1 and t 2 , or T = 0.693 (Rt a +Rt b ) Ct.
The advantage of this circuit is the total independence of Rta
and Rtb, which can range over the full gamut of component values
usable with the 555. The only restriction occurs at timing resistances
of a few kilohms or less, where the typical 300-ohm "on" resistance
of the analog switch will become a significant part of Rt. In the ex-
ample shown, t 1 is approximately 700 µs, while t 2 is 7 seconds, a
dynamic range of 10,000: 1. Although this is not actually "limitless,"
the practical limits are defined by the component values of the 555,
not by the resistances of switch A2 • If desired, the range of resistance
values can be extended even further by insertion of a buffer ampli-
fier between Ct and the 555, in a manner similar to Fig ..5-5. A bonus
of this circuit is the auxiliary output available at pin 7 of the timer,
which can be referred to any voltage from zero to + 15 volts.
v+
Timing Diagram
R,*
l.5Mn 4 8 C, ~}I II
(Times not
6 R v+ Output I
ll l rII- 1 1 to sea Ie. )
TH 3 0 utput U U u
OUT I II
2 555
R, TR ~t,•....;: t*
: ~:-- 2
l kn 7 :.__ T*__:
DIS GNO
C*
t c, *T = t1 +t 2
' - - - - - - - + - - - - ' O.Ql µF t1 = 0.693 R, C,
If R1 ~ R,, t 2 • T, and t 1 ~ T, then
T !e! 0.693 R, C,
f=_!_
T
1.44
a-
R,C,
(As shown, f :!! 10 Hz.)
134
In the circuit of Fig. 5-18, the basic 555 astable timing network is
reduced to a single timing resistor and capacitor. This not only sim-
plifies the circuit but, as will be seen, also simplifies its timing expres-
sion. In this circuit, Ct is charged through Rt and is discharged
through R1. If R 1 is made a very small fraction of Rt-that is, 1/ 100
or less-the output high time, ti, will occupy almost the total timing
period, T. This is because the very short period, t 2 , is such a small
fraction of T. Under these conditions, the timing ramp is an ex-
ponential ramp with a very short retrace. The output is a series of
short negative pulses of width t 2 , which occur at the basic frequency
(or repetition rate).
Since t 2 is much less than T, the timing expression for ti can be
simplified to t 1 9'0 T. As t 1 will be 0.693RtCt, this can also be the
expression for T. Thus, the simplified astable expression is
T 9'0 0.693RtCt.
Frequency is the reciprocal of T, or
f = 1.44
- Rtct·
Within these guidelines, the circuit can be operated over a fairly
broad range of frequencies. For best accuracy, time t:! should be
maintained greater than 50 µs. This time is approximately 0.693
R1Ct, and Ri and Ct can be optimized to maintain (or exceed) this
minimum pulse width.
135
tion of the total period, T, that this error has a correspondingly small
effect on the total period. The circuit may be said to be semisyn-
chronous, since it starts up immediately with a positive-going out-
put pulse but does have a very slight error in period T of the first
cycle (compared with subsequent cycles).
v+ Timing Diagram
D1 c,~IB.
as1c T".
I I 1mmg I
II I
1N914 R1 Output ...JL__Jl_fl__ (Times not
4.7 kn ti*__:~ : to scale.)
Enable o-------- Output : ~t2 ~
r On 4 8 ~T~
Off ...J
6R v+ En~~
....---+--1 TH 3 Gated
OUT
555 O~Jl..._JL_ Timing
I I
v, 5 ~T~
*T=t 1 +t 2
C,* c1
0.01 µF 0.0lµF
t2 = 0.693 R, C,
If R1 • R,, t 1 <( T, and t 2 =: T, then
T == 0.693 R, C,
1
f=r-
1.44
== R.c.
(As shown, f == 1 kHz.)
136
+uv
7 A2 14
4016
(Asshown,f 1 ~100 Hz;
f2 ~ 120 Hz.)
6
Control o-~~--+----' 4 8
Input 6 THR v+
3
Ifl A 1 OUT Output
f2 R1
10 kn
2 TR
7
555 Ve 5
1f
DIS GND
C,*
c1
0.01 µ.F
0.01 µ.f
5. 13 PROGRAMMABLE-FREQUENCY ASTABLES
The concept of electronic selection of Rt can be carried a step
further to yield a circuit that is programmable over a wide range of
frequencies using only four switches. This circuit is also a modified,
simplified astable using a 555, and is shown in Fig. 5-21. Here there
are four timing resistors, Rt through Rt It will be noted that these
1 4
•
resistors are binary weighted; that is, each resistor is twice the value
of its neighbor. This type of configuration comprises a simple 4-bit
d/ a converter, with the switching being accomplished by the quad
CMOS analog switch, A 2 • With this device, the respective switch
sections close when the control inputs are high.
With four bits of control, this circuit will have 24 -1, or 15, pos-
sible output frequencies. If the basic Rt is considered the highest
value (which will govern the lowest frequency), the output fre-
quency will be
1.44)
f 0 ~ n ( RtCt '
where n is the number from 1 to 15 as programmed by the control
inputs weighted 1, 2, 4, 8, etc. In this example, Rt is 1.6 Mn and Ct
137
+15V
10 9 4
5, 53 52 51 A2
7
r- r- r- r- 4016
I I I I 14
I I I I
11 6 s 3 13 2
L5B -Bit 4 (1)
Control Bit 3 (2) v--,..--
lnputs Bit 2 (.4)0----4'---+--'"""
4
1M5B-Bit 1 (8) o-~;..--R-*-~R-*~;..-----'
., •3
R *
'2
R *
'1 6 T~
A1 OUT 3 Output
(1.44)
200kn 2
*f an - - TR 555 1J
0 R, C, '
R1
s
where,
C,* 4.7kn
c1
n is digital input word: 1 ~ n ~ 1S 0.009µF 0.0lµF
(As shown, with base R, of 1.6 Mn, 100 Hz ~ f0 ~ 1500 Hz.)
v+
R.*
R1 50kfl
16
22 kn
v+ REG 15
14
TBO
13
RIC
Frequency 2240 C2
12
Programming* MOD 270pf
C.*
TR
R 0.0lµF
(n + l)R,C,
-1-
I I
R3 I I
R1 C 1 ---l --
I
I
I
I
4.7 kfl
C3
__n__n__
:i; 1000 pf
Output
tcMOS buffer 1
recommended. *f
0
=-...,..---
(n+l)R,C,'
where,
1 ~ n ~ 255
131
is 0.009 ,uF; therefore, fo ranges from 100 Hz to 1500 Hz in 100-Hz
steps.
Again, since this is a modified, simplified astable, the output is a
negative pulse whose repetition rate is variable. This concept of
wider-range programming can also be applied to other astable cir-
cuits as mentioned previously.
A programmable astable that uses the selectable-counter timing
taps of the 2240 is shown in Fig. 5-22. This circuit generates a posi-
tive-going output pulse of width RtCt. The pulse repeats at an in-
terval of ( n + 1) RtCt, where n is the programmed number. Thus,
output frequency f 0 is
5 Ct
ti=--·
It
139
+lSV
Timing Diagram
R*
l't c, ~
I
910kn II II
:~t,*..::
I II
I (Times not
a, I -: ~t2*
I to scale.)
2N3906 ~T~
Pulse : :
02 4 8 outpum
E113, 6 R v+
TH 3 Pulse
2N4861 OUT
2 Output
TR 555
v 5
R1
lOkn 0.01 /LF
Ramp
Output
4.4 v
*for V+ = 15 V, I, =--R,
5 c,
t,=1,-
=l.lR,C,
t2 =0.7R C, 1
If t 2 ~ t 1,
T= 1.lR, C,
1
to= r
0.91
-R.c.
(As shown, f 0 =100 Hz.)
Fig. 5-23. Simple linear-ramp astable circuit.
Since
I =< 4.4 V
t - Rt '
ti = l.lRtCt.
The time, t 2 , is set much smaller than t 1 by design and will be
about 0.7R 1Ct. This equation is not precise, as the current It is "on"
140
during time t 2 • Since t 2 is much less than ti, t 1 is approximate ly equal
to T, the total period. Then it can be said that
T = l.lRtCt.
This circuit, like the basic 5.S.5 astable, is essentially supply inde-
pendent. It does, however, work best at the higher supply voltages;
thus, 15 volts is recommende d. The design equations are approxi-
mate, due to several error sources: the Vm: of Qi, the asymmetry of
tdt 2 , comparator threshold, and so on. It is a very simple circuit,
however, and a good vehicle for study or experimenta tion. If the
ramp is to be used externally, it must be buffered. A suitable buffer
is an n-channel FET, such as the E113 or 2N4861 shown.
5Ct
ti=T.
for high values of Rt. For low values of Rt, It approaches the satura-
tion current ( In 88 ) of the FET. Unfortunate ly, Vm; in this expression
is not readily predictable, and will vary from unit to unit due to
normal FET production tolerances. Therefore, it is best to use a
potentiomet er for Rt in this type of circuit to compensate for V Gs
variations. The FET used, if other than the E230, should have a
gate-to-sour ce cutoff voltage of 2 volts or less to operate properly.
For design guidance, an average V,rn is on the order of 1 volt. (This
will vary somewhat with current, of course.)
\Vith the component values shown, t 1 is variable from less than
.SO µs to over 2 ms, and t:! is nominally .SO µs. The value specified for
141
+15V
Timing Diagram
Ql Pulse
E230,
2N4867
Output
C
r-1f )
II
""}.1 ~
I
(Times not
to scale.)
02 I j~ j\_,.
R*
t
II I
01
8
-P-t/ i
Q2 1N914 ~T*~
El 13,
6
TH
R v+
3 Pulse
2N4861 OUT
2 Output
Ri TR 555
5
6.8 kn
C.*
0.01 µF
c1
0.01 µF
I
b lf
Sync
Ramp
Output
*1 = VGS
I R,
ti=~
I,
_SR, C,
- --v;;-
t2 = 0.693 R C, 1
l
fo= r
(As shown, f 0 is variable from < 400 Hz to > l 0 kHz.)
142
output pulses. This is accomplished with virtually no change in the
component count, just some rearrangement. In this circuit, Ct is
charged from the output via Di and Ri during period ti. Due to the
presence of Di and an output voltage less than V+, the ti timing
equation is approximately ti= RiCt. However, as this is both impre-
cise and unstable, ti should be minimized to reduce its overall con-
tribution (and thus the percentage of error) to the period T. During
t 2 , Ct is discharged by Qi, which is gated by pin 7 of the 555. The
timing expression for t 2 is
t 2 = 5RtCt.
VGs
A potentiometer is also used in this circuit for Rt to compensate
for VGs variations (and thus variations in It) of FET Q1 • With the
+uv Timing Diagram·
Enable JI
R2 Pulse 1
4.7kn
Output Jl.__jl_
~
111
Enable o-.t-------~-_...
c I
Ig,'; Pulse
II I
...!:.. ti* :
4 8 II I
Q2 Output
El13, v+ :L.-tt-1
2N4861 Q, 3 I I
OUT :.._T*~
E230, 555
2N4867 Ve 5
7
DIS GND
R.* C1
SO kn 0.01 µF
bIL
Sync
Ramp
Output
SC,
t, =-,-,
_5R,C,
- VGS
f
o
=..!_T
143
component values shown, ti is 10 µs and t 2 ranges from about 50 µs
to over 2 ms. The circuit can easily be gated "on" and "off" by the
use of the reset pin as shown. Oscillations start immediately, and if ti
is short compared to T, there will be little error caused by the gating.
The circuit can also be synchronized by breaking the Ci connection
at point "X" and applying positive pulses to pin 5.
5.14.4 Wide-Range Square-Wave/Triangle-Wave Generator
The circuit of Fig. 5-26 employs linear-ramp techniques in an in-
teresting manner, using a single constant-current source for both
the charge and discharge of Ct. The result is the generation of time-
symmetrical ramps, or triangle waves, as well as square waves.
In this circuit, the charge and discharge currents for Ct must
come through the diode bridge formed by Di-D 4 • Bridge Di-D 4
consists of four general-purpose switching diodes that serve to steer
current in the proper direction through the current source made up
of Qi and Rt. The unique feature of this type of current source is
that it is a two-terminal device and needs no external bias connec-
tions. Thus, it serves nicely here as a floating current regulator.
The output pin serves as a source of current for the timing net-
work, and its state of high or low determines the direction of current
+uv
*t =t =~=5R,C,
1 2 1, VGS
T = t1 +t 2
l
fo =T
(As shown, f 0 is variable from
20 Hz to 20 kHz.}
8
Q2 v+
El 13,
2N486l OUT 1 - 3 - - - - - - 0 Square-Wave
2 TR 555 Output l
+sv to
Ve 5 +l5V
2200 pF
7 DIS GND
1 c1
'------+---E'--~-------' O.Ol µF R1
.4.7 kn Square-Wave
------------'i.J Output 2
144
How into or out of Ct, for charge or discharge. Diodes D 2 and D 3 and
transistor Qi conduct during charge while Di, D 4 , and Qi conduct
during discharge. Since both charge and discharge currents flow
through the same current regulator circuit, the currents are equal,
and thus times ti and t 2 are equal. As a result, triangle waves are
formed across Ct.
There are two square-wave outputs from the circuit, as shown.
The triangle wave is 5 volts p-p in level, as set by the internal thresh-
olds of the 555. As shown, the circuit can cover the entire audio range
of 20 Hz to 20 kHz with a single 2.5-MD potentiometer for Rt.
REFERENCES
1. Litus, J. Jr.; Niemiec, S.; Paradise, J. Trammission and Multiplexing of
Analog or Digital Signals Utilizing the CD4016A Quad Bilateral Switch.
RCA Application Note ICAN-6601, August 1971. RCA Solid State Div.,
Somerville, N.J.
2. Sherwin, J. S. The Field Effect Transistor Constant Current Source. Siliconix
Application Note, January 1971. Siliconix Inc., Santa Clara, Calif.
3. Siliconix Application Note AN73-7, December 1973. An Introduction to
FETs. Siliconix Inc., Santa Clara, Calif.
145
6
147
without "chatter" or other oscillations at the change-of-state points.
The circuit will not respond to signals with p-p amplitudes of less
than l/3V+; the signal peaks must pass through 2/3V+ and l/3V+
for operation. If desired, the output can be strobed "off" by holding
the reset pin low, via the strobe input. If not used, the reset input
should be connected to V +.
v+
Strobe
_J Active r------- -----,
Disabled
R/
+1
I
D*
1~914
4
,.._,..R_ _
6 TH
8
v...._+~
10 k!l
ouT~3~--i:,---~~~~-u
I
Input o--·-.-·/-.---+- .... Output l
1 2 TR SSS
I
5 JRJ
+
D* I
7 V, - - - - ~Threshold
lN9l: DIS
I
I 10 k!l
GND
I
I
I
IL_________ Output 2
_
Timing Diagram
Output
*Include R2 , D 1 , and D 2
if input signal peaks are greater
than v+ or less than ground.
148
6.1.2 Inverting Bistable Buffer*
A modification of the Schmitt trigger is shown in Fig. 6-2. This cir-
cuit is an inverting bistable, and can also be used to amplify or re-
generate signal waveforms. In this circuit, R 1 and R~ bias the input
to 1/2 V +, midway between comparison thresholds. Therefore, an
input signal of only l/6V+ is required to trip either comparator.
For any input above the threshold, the output is a high-level wave-
form at pin 3, with an uncommitted output at pin 7. Note that this
circuit responds only to edges of the waveform, due to the differ-
entiation.
v+
R*l
4 8
22 kn
6 R v+
C1* TH 3
Input <>--1---... 2
OUT t-----o Output 1
1000 pF TR 555
R2 * GND
22 kl!
~---------u Output 2
Timing Diagram
Input
1___Jl_-}- Must exceed
I I I - 1 /6 v+.
t--+-t
I I
It may be noted by the reader that the 555 used alone without the
differentiating network will also invert and buffer signals applied to
pins 2 and 6 in common. If timing error is of no consequence, the
circuit can be used simply in this fashion, but output delay may be
as high as several microseconds when the input is driven to ground.
The input differentiation network minimizes this delay to well be-
low a microsecond. Component values of the differentiator are not
highly critical but should be selected for an RC time constant of
10 µs or less.
149
6. 1.3 Set-Reset (R-S} Flip-Flop
The 555 can also be used as a set-reset ( R-S) flip-flop, as shown
in Fig. 6-3. This circuit allows independent control of the internal
latch by separating the inputs, as shown. A low pulse to the set in-
put will force the output high. The output will then remain high
until reset. There are two reset inputs: pin 4 and pin 6. Pulsing
either input to the level shown will return the output to the low
state (see the timing diagram in Fig. 6-3, which illustrates this). The
pin 4 input is overriding and can also be used as a master inhibit,
which will cause the 555 to ignore further input changes when held
low.
v+
R1 ~ RJ
4.7kn > 4.7 kn
lI ~
Reset
Inputs 4 8
v+
Jl --
6
TH
R
3
2 OUT -- Output 1
-- SSS
Set Input lJ TR
I
7
DIS
Ri :
~ND
4.7 kn • ~ Output 2
=>=-
. R,
4.7 kn
Timing Diagram
)
0 V to +15 V
Set 1J
I
I
Reset (Pin 4) :
I
Lf
I
I I
Output~
Set lJ
I
I
Reset (Pin 6) : fl_
I I
Output _j----1_
Fig. 6-3. Set-reset (R·S) flip-flop.
If the inputs at pin 6 or pin 2 are levels rather than pulses, differ-
entiation may be required, as in the 555 monostable. Differentiation
should also be used if minimum delay is required, as in the inverting
bistable buffer.
150
6.1.4 Voltage Comparator*
The function of a voltage comparator is a very useful one, and
one for which a 322 is ideally suited. Its use as such is shown in Fig.
6-4. The 322 is set up for comparator use by connecting its trigger
input high, which disables the internal discharge transistor. The R/C
pin is then used as a comparator input, and will compare with re-
spect to the voltage at the Vadj pin (or in the case of the 3905, a
fixed +2 volts). The threshold of the comparator can be varied over
a range of zero to Vrer by means of the threshold control, R1 .
v+
3 11
8
10
v+ R2
4 12 4.7kn
----1V, 322 C ~-------o Output
R;"
Input o--JVl~-E----~ RIC 5
lOko V0 GND
7 6
RI >4------J
lkn
Threshold
Timing Diagram
M_J-
!
Logic Low
*Output : : :
LogicHig~
151
Due to the high gain (and high speed with boost used), the 322
makes a very useful comparator. It can be powered from a wide
range of supply voltages without threshold changes, and the output
has good drive capability.
6. 1.5 Zero-Crossing Detector
Fig. 6-5 illustrates a practical use of the 322 comparator-as a
zero-crossing detector. Output 1 of this circuit is high when the in-
put is above zero, and is low when the input is below zero.
Stage Ai is a 322 comparator set up with a threshold of zero volts,
established by grounding pin 7. The output of Ai is a square wave
that is in phase with the zero crossings of the input. Some positive
feedback is applied via R 2 to avoid "chatter" due to noise near the
zero crossings. With a value of 22 kfl for R 1 , the input can be up to
± 10 volts in amplitude.
Stage A2 is a monostable connected to fire when output 1 goes
high, or at the zero crossings. This section is not an essential part of
the zero-crossing detector itself, but such pulses are useful for time
marks.
v+
3 11 3 11
TR B TR B
2 L 10 2 L 10
v+ v+ R,
4 Ai A2 12 2.2 kn
v c c
322 R, Output 2
5 lOku
In put v---"""r-------1 R/C E E
v 0 GND GND
7 6 c, 6
1000 pf
Output 1
Timing Diagram
Input (V-- 0 V
Output l JL_f
I
Output 2 lJ lf
Fig. 6-5. Zero-crossing detector.
152
6. 1.6 Window Detector
Fig. 6-6 illustrates another comparator application-a window de-
tector. This circuit has a high output whenever the input voltage is
between threshold 1 and threshold 2 in amplitude, or is within this
voltage "window."
Stage A:~ is a monostable connected to fire when output I goes
when the input is above threshold 1. Stage A:! is an inverting com-
parator; its output will be low when the input is above threshold 2.
With the second threshold adjusted higher than the first, the out-
puts can be tied together and will indicate when the input is within
the window ( see the timing diagram in Fig. 6-6) . Both thresholds
can range from zero to 3.15 volts, but threshold 2 must be higher
than threshold 1 for the circuit to function properly.
3 11 3
TR B TR
10 2
v+ L
4 A, A Output
v c 12 4 V, 2 Ct-1_2_---o
322 322
5 5 1
R/C R/C E
v a GND Vo GND
R2 7 6 7 6
R3
1 kn 1 kn
Threshold l Threshold 2
Input
R,
22 kn
Timing Diagram
153
+sv
3 11
B 10
v+
R;"
c 12 Output
10 kn
Input O-.J\IV"'lr-_ _ ___...,___-4
5 R/C El
Va GND
R1 7 6
4.7kn
cnoise .l.
lOOOpF TI R2
L__ ,._4_.7_k_n_ _ __..._ ____.
Fig. 6-7. line receiver using 322 type.
OUT~----E------o
3
Output l
555 R2
7
DIS
GND
--
c1
i I
:
10 kn
Threshold
lOOOpF 0.01 µF 1
Output 2
154
to the reference voltage (pin 4). The circuit can also be adjusted for
other logic level inputs by changing the R1-R2 values. Finally, the
circuit can be used as a logic level converter by returning R:{ to a
voltage level higher than +5 volts; for example, + 1.5 volts for CMOS
logic.
A 555 line receiver is shown in Fig. 6-8, and is similar in some re-
gards to the 322 version. This circuit is inverting, with Rin and Ciwise
performing functions similar to their counterparts of Fig. 6-7. A
strobe input is added here, which will hold the output low when
the strobe input is low.
With a +5-volt supply, input thresholds will be 3.3 volts and 1.6
volts, respectively. This is somewhat high for a TTL logic input; thus,
a threshold control may be necessary to optimize input sensitivity.
The circuit has dual outputs, and output 1 will be TTL compatible
with a chip supply of +5 volts. Output 2 can be used as a logic level
converter, and can be referred to voltages up to + 15 volts (for any
chip supply voltage).
Note that where the 322 circuit of Fig. 6-7 could convert from low
to higher logic levels, the 555 circuit of Fig. 6-8 can also convert
from high to lower logic levels, such as CMOS to TTL, by using a
+15-volt chip supply and referring output 2 to the lower logic level.
A very useful line receiver circuit is one that responds to differen-
tial (or balanced input) drive signals. This circuit, shown in Fig.
6-9, uses both comparator inputs of the 322, with out-of-phase TTL
drives applied to the ( +) and ( - ) inputs, respectively. It can de-
liver an undisturbed output with about 1 volt of common-mode noise
on both input lines. The output is in phase with the ( + ) input. As
shown, the output is TTL compatible, but R4 may be referred to
higher voltages if required. Overall delay is on the order of 1 µs.
+sv
3 11
TR B
2 l 10
v+ R4
Ri 4 v 322 c 12 1 kn
Output
1 kn 5
(+) R/C E
Va GND
R3
Inputs 7 6
22on
(-)
R2
1 kn
155
6.1.8 Differential Line Driver
As a source of balanced drive signals, the circuit of Fig. 6-10 is
useful. It uses the dual-unit 556, plus three discrete components. In
this circuit, section A of the 556 is a noninverting buffer amplifier,
while section B is an inverting bistable. The push-pull drive outputs
are matched in transition times to within less than 0.5 µs.
Section B could be a simple Schmitt trigger, similar to Fig. 6-1,
were it not for delay problems of the internal comparator. The differ-
entiating network consisting of Ci, R 1 , and R2 prevents this delay
by not allowing the input (pins 8 and 12) of section B to be held
low. The open-collector outputs of both stages (pins 1 and 13) are
also available for use, if so desired.
v+
Input
Non inverted
Push-Pull
4 14 10
Drive
R v+ R
2 12 TH
Outputs
TH
5 9 Inverted
OUT OUT
6 t--+-----'-IS TR 556
TR 556 '--t
A 220 pF
B
.--
1
DIS
GND R2
p DIS
I
I I
I l 10kfl 1
156
TRANSMITTER RECEIVER
v+ v+
(Transmitter) (Receiver)
r----------,
I I
l: 4N37 :5
.--------4....-JV\i'V-~• ~-0---+-JV'li'V-..-----.
I
Data 4 8 I 4 8
I
Input
6
R v+ I
I
::::
6
R v+
TH I
TH
OUT 1-'----<~
3 2
1
3 Data
A1 I 2 TR A2 OUT Output
I
555 ~----------~ 555
5
r-_! DIS V, c1
GND : GND 0.01 µF
I
I
Open-
Collector
Output
TRANSMITTER RECEIVER
v+ v+
(Transmitter) (Receiver)
TR
2
L R,
12 1 kn Data
Cr-------u
Output
11
TR B E 1
2
L v+ 10
6
I
I
I I
L-----------'
Data
Input
157
tively slow rate-of-change data inputs. If the receiver and transmit-
ter are to be physically separated by an appreciable distance, the
4N37 should be located within the receiver circuit, and twisted-pair
lines should be run from the transmitter output to the LED input of
the 4N37. The system works over the full range of supply voltages
usable with the 555, and the supplies of the two sections need not
be the same.
Another type of optoisolator that is not as limited in speed is the
LED/photodiode optoisolator, shown in Fig. 6-12 within a 322-
driven data-link system. This circuit is capable of a much higher
speed of operation, with little increase in complexity.
In the transmitter portion, A1 is a 322 connected as a simple com-
parator to drive the LED of the optoisolator. It accepts TTL inputs,
as shown.
The receiver portion is also a comparator, but with additional
biasing to match the photodiode output. Photodiode optoisolators
are typically very low in current transfer ratio; the type shown here
will typically transfer only 0.2% of the LED input current as out-
put. Therefore, the amplifier that follows it must be capable of high
gain (as well as speed). Furthermore, to realize the speed, the load
resistance must be held low, which tends to minimize the useful
voltage output. It is these requirements that dictate the extra com.:
plexity of the A2 comparator stage.
Here, R;, and R6 set up a 70-m V bias voltage at pin 7 of the 322.
With the photodiode "off,'' R~ and R.1 bias pin 5 to 50 mV. A 50-mV
(or more) photodiode output will overcome this bias and switch the
comparator. The high gain of the 322 will then deliver a fully satu-
rated output swing of zero volts to V +.
The system shown is noninverting overall, from data-input to
data-output terminals. System delay is on the order of 2 µ,s, with
most of this delay due to the 322 stages. The receiver can be oper-
ated from any supply voltage usable with the 322, but the transmit-
ter should be matched to its supply voltage by selection of R 2 • The
R 2 value shown was chosen for a V+ of 5 volts. This system is ca-
pable of isolation comparable to that of the 4N37, as the MCD2
also features a 1500-volt isolation rating.
158
v+
v+
v+
322/
3905 c 322/
3905
v+
v+
v+
v+ 1, l ~
LED, 555/556
OUT
OUT
555/556
GND
'l
GND
1, l LED 1
I,= (V+)-(Voat + V1 )
R,
(C) Using the 555/556 timers in the LED-on- (D) Using the 555/556 timers in the LED-on-
with-output-low, LED-off-with-output-high- with-output-high, LED-off-with-output-low
. mode of operation. mode of operation.
Fig. 6-13. Methods for driving LEDs.
15t
the desired LED forward current according to the equation shown.
The voltage across R 1 is the supply voltage minus the 1.6-volt LED
drop and the 2-volt emitter saturation voltage of the timer. This cir-
cuit is most effective at supply voltages of 10 volts or more because
at lower voltages the LED and timer voltage drops are a large per-
centage of the supply voltage; thus the current can vary appreciably.
Fig. 6-13B shows the 322/3905 timers in their collector-output
mode. The LED will be "on" when the output is low in this circuit,
and the voltage across R 1 is the supply voltage minus the LED volt-
age drop and the collector saturation voltage. This circuit is useful
over the entire range of supply voltages.
For both the emitter and collector output operating modes, the
desired LED on/ off state may be programmed by use of the logic
pin (see Chapter 2).
In the circuit of Fig. 6-13C, which uses the 555/556 timers, the
LED is "on" when the output is low, and "off" when the output is
high. The voltage across R 1 is the supply voltage minus the low-state
saturation voltage and the LED voltage drop. Like the circuit of Fig.
6-13B, this circuit is useful over the entire range of timer supply
voltages.
In the circuit of Fig. 6-13D, which also uses the 555/556 timers,
the LED is "on" when the output is high, and "off" when the output
is low. The voltage across R 1 is the supply voltage minus the high-
state saturation voltage and the LED voltage drop. This circuit is
most useful at supply voltages above 10 volts.
6.2.2 Driving Incandescent lamps
Although driving small panel-mounted incandescent lamps may
seem to be a trivial matter, there are certain problems that can be
troublesome if not completely thought out. Due to the highly non-
linear resistance/voltage characteristic of incandescent lamps, tum-
on current surges can be many times the rated steady-state value for
the lamp in use. If not limited, these surges can cause failure of the
driver, or the lamp itself. An effective solution to this problem is to
use a drive current that is peak-limited to a value somewhat higher
than the normal operating current. This can easily be realized by
using the 322/3905 timers with their built-in current-limiting fea-
ture, and is shown in Fig. 6-14.
In Fig. 6-14A, the 322/3905 timers are shown in the emitter out-
put mode driving a 28-volt, 40-mA lamp. For this mode, as well as
the collector output mode shown in Fig. 6-14B, the supply voltage
used should be compatible with the lamp rating. In the examples
shown, a 28-volt supply is used, but lower voltages (such as 12 volts
or 14 volts) can also be used with lower-voltage lamps. Generally,
any lamp with a 50-mA or less current rating can be used with these
160
+2BV +2BV +28V
(see text) +5V 9 (see text)
I
(see text) I
v+ v+
322/ 322/
3905 c 3905 c- - - -
E
GND
(A) Using the 322/ 3905 timers in the (B) Using the 322/3905 timers in the
emitter-output mode of operation. collector-output mode of operation.
Fig. 6-14. Methods for driving incandescent lamps.
two circuits. Note that in Fig. 6-14B, the V+ for the timer can be
either the lamp supply or a lower-voltage supply such as +5 volts
when available.
6.2.3 D.riving Relays
Fig. 6-15 illustrates methods of driving relays using timers, a
technique in which the total current-switching capability is extended
to amperes and the total voltage-switching capability is extended to
hundreds of volts. In Fig. 6-15A, the 322/ 3905 timers are shown in
the emitter output mode. In this mode, the relay is activated when
the emitter is high, and will drive the relay coil to the supply volt-
age minus the emitter output saturation voltage of the timer. Relays
within the 322/ 3905 output current capability of 50 mA will generally
be 24- to 28-volt types, as standard lower voltage types require ap-
preciably higher currents. All timer-driven relay circuits should use
a reverse clamping diode, such as Di, across the coil. This diode can
be a 1-A rectifier, such as one of the 1N4000 series types.
The collector output option shown in Fig. 6-15B allows a separate
supply voltage to be used for the relay (if desired). In straightfor-
ward form, the relay would be returned to the timer V +, which for
a 28-volt relay would require operating the timer on 28 volts also.
A useful option is to return the relay to a 28-volt supply, while the
timer is operated from a lower voltage such as 5 volts. The relay
supply may be any voltage up to the timer rating of 40 volts (com-
patible with the relay used, of course). This technique is effective
in controlling noise typically generated on a relay supply line.
A 555/556 relay circuit is shown in Fig. 6-15C. This circuit will
activate the relay when the timer output is low. The circuit can most
161
v+ v+ +28V
(+28V) (see text) 9 (see text)
I
I
D1
v+ v+ 11 •·
322/ 322/
3905 c 3905 c
Ei---...--.
GND
11 •·
(A) Using the 322/3905 timers in the (B) Using the 322/3905 timers in the
emitter-output mode of operation. collector-output mode of operation.
v+ v+
(+lOV to +15V) (+15 V preferred)
v+
11 •·
OUTt----~ OUTi---------.
555/556 555/556
GND 11 •·
GND
(C) Using the 555/ 556 timers in the (D) Using the 555/ 556 timers in the
relay-activated-with-output-low, relay- re Iay-a ct iv ated-with-output-hi g h, relay-
deactivated-with-output-high mode of deactivated-with-output-low mode of
operation. operation.
Fig. 6-15. Methods for driving relays.
162
6.2.4 Booster Amplifiers
There are many situations that demand a higher current or volt-
age output than IC timers can handle alone, with operating speeds
faster than that of a relay. This application requirement may be
satisfied by the use of booster amplifier stages, as illustrated in
Fig. 6-16.
In Fig. 6-16A, a 555/5.56 circuit for driving an npn power transis-
tor is shown. This circuit will be "on" when the timer output is high,
and the current/voltage capability is set by the device chosen for
Qi. As shown, the popular "3055" can handle up to 60 volts at cur-
rents of about 2 amperes. vVith this circuit, the timer V + should be
15 volts to ensure adequate base drive for Q1 •
+15V v++
(up to 60V)
----, I
v+
Ri
Load
*I
D1
OUT
555/556 220 n Ql
MJE3055
2N3055
GND
v+ v++ v+ v++
(up to 60V) (up to 60V)
----,
*
----,
I I
*D
I
I
1 Load
I
I
D1
v+ ____ J I
____ JI
v+
OUT 322/
555/556 l N4001 3905 (>------4
GND GND
(B) Using the 555/ 556 timers to drive an (C) Using the 322/ 3905 timers to drive an
npn Darlington power transistor. npn Darlington power transistor.
Fig. 6-16. Methods for driving power booster amplifiers.
163
Current output capability, which is limited in Fig. 6-16A by the
minimum gain of the transistor, can be increased by using a power
Darlington device as shown in Fig. 6-16B. Here the 2N6055 unit can
handle up to 5 amperes. Base drive is set by Ri, which should be
selected in accordance with the timer V+ used for a base drive of
5 mA in Qi. As shown, the Ri value is for a V + of 5 volts. This cir-
cuit relaxes the drive requirements from the timer due to the high
gain of the Darlington.
A circuit arranged for the 322/ 3905 is shown in Fig. 6-16C. In
general, this circuit is similar to that of Fig. 6-16B, but the need
for diode D 2 is eliminated and the circuit has the added flexibility
of on/ off control through the use of the logic input of the timer.
Transistor Q 1 is "on" in this circuit when the output transistor of the
timer is "off." Again, R 1 should be chosen for a 5-mA drive to Q 1 with
the timer supply voltage used.
In all three of the circuits in Fig. 6-16, a reverse clamping diode
(shown dotted) should be used if the load is inductive in nature.
This would include relays, solenoids, etc.
The time-delay relay function is one in which the closing (or open-
ing) of relay contacts, which apply power to an external circuit, is
timed to occur at some specific interval after the application of
power to the timer. Several examples of time-delay relay circuits are
shown in Figs. 6-17, 6-18, and 6-19.
6.3. 1 Circuits for Closing Relay Contacts After a Time-Delay Period
Fig. 6-17 illustrates two time-delay relay circuits in which the re-
lay contacts close after a delay interval. The time delay begins with
the application of power to the timer.
Fig. 6-17A is a 555 delay circuit, which may be recognized as a
variation of the simple power-up one-shot circuit that was de-
scribed in Chapter 4 (Section 4.6, Fig. 4-6A). The example illus-
trated times-out after 11 seconds, closing relay K1 • Relay Ki is a
12-volt, 80-mA relay, a type that is readily available from a number
of suppliers.
Fig. 6-17B is a similarly operating circuit that uses a 3905 and
drives a 24-volt, 40-mA relay. (This type of relay is available from
the same series as the 12-volt units used in Fig. 6-17A.) In this cir-
cuit, advantage is taken of the low timing current of the 3905. The
circuit uses 60 Mn for Rt and 1 µ,F for Ct to yield a delay interval of
one minute. As mentioned in Section 6.2.3 concerning 322/ 3905 relay
drivers, the timer V + can be lower than +24 volts if a lower voltage
supply such as +5 volts or + 15 volts is available.
164
- ---------------------------------------------
v+ ~
(+10v to +15V) o-+1
R*
t
lOMn
6
4
TH
R v+
8
3
1N4002
D1
.rt
OUT
2
TR SSS
c* t
*T = 1.1 Rt Ct (As shown, T = 11 s.)
1 µF GND
t K1 = 12-V de @ 80-mA coil, contacts to suit.
(Potter & Brumfield KHP, KUP Series or equivalent.)
+24V +24V
(see text)
?
:i.
D1
o-l1
I
I
K1t
TR
~----"'-18 L
lO.lµF
c1
2
v'
390S
v+ 5
6
c !-'--------'
II
Rt 7
60Mn
GND
*T = Rt Ct (As shown, T =l min.)
16S
+28V
~
o-11
I
I
I
I
D1
1N4003
v+ ._.s_ _ _-1 _ _ ___.
2 3905 c6
v,
3 7
R/C E *T = R. c.
GND
4
t K1 = 24-V de @ 40-mA coil, contacts to suit.
C*
t {Potter & Brumfield KHP, KUP Series or equivalent.)
The basis of operation for this circuit is that the standby current
of the timer prior to time-out is relatively low; in fact, it must be
lower than the minimum actuation current of the relay to prevent
premature closure of the relay contacts. \Vith the application of
power the timer begins timing out, and during the timing interval
the timer appears as a relatively high impedance to the relay; thus,
the relay remains open. When the timing interval is completed, the
output stage of the timer conducts and a large current flows through
the relay coil, causing the contacts to close. The relay will then re-
main closed until power is recycled, as in the circuit of Fig. 6-l 7B.
This two-terminal timed switch may be used to drive loads other
than relays if their current thresholds are compatible with the 322/
3905 characteristics.
6.3.2 Circuits for Closing Relay Contacts During a Time-Delay Period
Fig. 6-19 illustrates two time-delay relay circuits in which the
relay contacts are closed during a relay interval, then opened. Again,
the time delay begins with the application of power to the timer.
Fig. 6-19A is a .555 delay circuit, which is also a power-up one-shot
like the circuit of Fig. 6-17A. In this case, the relay is arranged to
be "on" during the delay interval. This particular example is a 30-
second timer and uses the same relay types as the circuit of Fig.
6-17A.
Fig. 6-19B is a 3905 "on-for-time-delay" circuit. The relay is driven
from the emitter output, with the collector output connected to +24
166
+uv
*T = 1.lR, C, (As shown, T = 30 s.)
tK 1 = 12-V de@ 80-mA coil, contacts to suit.
(Potter & Brumfield KHP, KUP Series or equivalent.)
RI *
15Mn 4 8
R v+ 02
6
TH
3
1N4002 :i.
2
OUT a-ti
I
TR 555 I
I
01 K1t
C*
,II
I
1.8 µF 1N4002
GNO
+24V
R*
2 v 3905 c 6
:i
20Mn
I
E
7 o-!J
I
Icl
~ 0.1 µF
GND
4 01
I
I
Kit
1N4003
II
(B) Using 3905 type.
Fig. 6-19. Time delay relay circuits-relay contacts close during time delay period.
volts. This circuit uses the same relay types as the circuit of Fig.
6-l 7B. As shown, it is designed for a delay of two seconds.
All of the time-delay relay circuits described in this section time-
out once and only once, beginning with the application of power to
the timer. As shown, they can be recycled only by the removal of
power. However, if desired, the 555-based circuits can be recycled
by using the reset method illustrated in Fig. 4-6A of Chapter 4.
Some of the most useful timer circuits fall under the category of
function generators, circuits that generate the basic triangle, square,
167
and sine waveforms. A wide variety of function-generator circuits
are possible using IC timers, and since they are generally so useful,
a number of them will be discussed in this section. All of the types
to be discussed generate the basic triangle and square waveforms,
and a sine-wave output may be realized by the addition of a simple
sine-wave converter, which is also illustrated.
6.4. 1 CMOS Function Generator
Figs. 6-20 and 6-21 illustrate two function-generator circuits whose
main attribute is low cost, as they use only a single 555 timer plus a
CMOS triple inverter, A:.!. Either of these two circuits can be as-
sembled at negligible cost, and both of them furnish a variety of
waveforms.
The basic CMOS function generator is shown in Fig. 6-20. It uses
the 555 as a Schmitt trigger, A1, and section A2B of the CMOS in-
verter as an integrator. Section A2 A of the CMOS is a logic inverter,
and these three portions of the circuit make up the basic function
generator. Section A 2 c of the CMOS is an optional inverter that can
be used to provide a fourth output, if desired.
This circuit uses the CMOS and 555 characteristic supply-voltage
ratiometric principles to advantage, as the voltage thresholds of A1
and the logic level of A2 A are proportional to V +. As a result, opera-
tion is supply independent and the circuit operates from +5 volts to
+15 volts. It can be voltage controlled, if desired, by applying a con-
trol voltage to the Ve terminal (pin 5) of the timer. If voltage control
is used, it works best at a supply voltage of + 15 volts.
This circuit can operate up to 100 kHz and down to extremely low
frequencies since the CMOS inverters have very low input current.
Resistor Rt can range from 100 kn up to 100 Mn if desired. The
amplitude of the triangle-wave output is Vc/2 volts; or, if Ve is not
used, simply V+I 3 volts.
Another version of this circuit is shown in Fig. 6-21, which fea-
tures a linear, frequency-tuning control, R2. In this circuit, R 1 and
R2 divide down the voltage applied to Rt, thus increasing the effec-
tive value of Rt and lowering the frequency in so doing. The fre-
quency is lowered by the ratio of (Ra + Rb) I Ra, where Ra and Rb
are the portions of the R 1-R2 voltage divider as noted in the diagram.
However, this type of control is effective only over about a 10:1
range, due to the offset of the CMOS inverters.
The same general statements concerning allowable values of tim-
ing components and frequency range that were made for the circuit
of Fig. 6-20, also apply to this circuit. In both circuits, predictability
and waveform symmetry are somewhat inexact due to variations in
the CMOS threshold characteristics; therefore, the design equations
are approximate.
168
C*
v+
I
"fl 1500 pf
c!i' ( < ( ( G Triangle-Wave~
9' t t Output
...,
p
m
II 4 8
I!!.
ft
n 61 R v+
!: TH
3
0 21 TR A OUTI 1: Square-Wave UL
1 Output l
"'2" 55 5 5
:I Rt 71 Ve t---<1•~-....&-- Ve*
!l Timing Diagram
;;· lOOkn DIS
:I c1 v
GND Triangle
CD
0.01 µF Wave ~====Vc/2
I I I C
:I
•
Square _H_tu
!I.
=
~ Wave
L-------------1---c: Square-Wave UL (l,2,4) ~ti*
l· Output 2 i ~t2*
:r I I
< I I
0 ...-T*-
; Square-Wave
CD JU
ft Output 3
0
'a '---~--------------<'l Square-Wave UL
i.
i" Output 4
a.
"a
Ve R, C, 1 v+
•i· *ti= t2a~ f=-a---
T 2Vc R, C,
!-'-
(As shown, f as 5 kHz.)
2V R,C,
T=t, + t 2 a V + t A2 = 4007, 3600 or other CMOS inverter.
i
v+
C*
I
390pf
Triangle-Wave
Output
2
8
6
R v+
TH
1,5 3
2 TR A1 OUT
Square-Wave
555 5
I 14 7
v, Output 1
I DIS
I
GND
8,13: 6
I
c1
71 0.01 µ.f
I
111
I
I
I
10 1
Square-Wave
I
I
I
Output 2
I
_____ JI
Square-Wave
1 (0.75 )( Ra ) Output 3
f =fa R.(, Ra+ Rb
(As shown, f is variable from 2 kHz to 20 kHz.)
170
D1 LED 1 +uv
1N756 MV5020 // Timing Diagram
., I c,
I ------10 v
(;I.') I {f;') I ~ 1O µF
.D- ~. Triangle Wave ~---- 5 y
I I I
Q1 I I I
I I I
"II I I I
2N3906
t?" l kn s Mn, Square Wave JU
Cl" I I I
...., t* ~I
RABC*
1 : :.....!.-- t2*
I I
""'~ :..T~
a.
!
.. R1
:I lOkn
m Triangle-Wave
~"' Output
...
c JI ABC
:I
..er 41 18
i"
c
:I
>6 I v+ Square-Wave
- r 61"
, TH A,OUTLJ
!l. TR 555 o Output l
er
:I v, 5
m R~ R6
1
:I
• l.5kn C*
I
4.7 kn GND c1
.= 0.002 µF 0.1 µF
~ RJ I R2
Square-Wave
4.7 kn 1.5 kn
Output 2
*t 1 = t 2 aE 5RABC C, l 0.1
f=-aii---
T RABC c,
T 1
=t +t 2 ii'l!! l OR ARC cI
(As shown, f is variable from 10 Hz to 50 kHz.)
:::!
-
of the OT A. Here, pin 2 is biased at a fixed 2 volts, and pin 3 is
driven by a fraction of the output of the timer. \Vhen pin 3 of Az is
higher than pin 2 (as driven by the timer output), the triangle wave
ramps positive, forming the t 1 alternation of the output wave. When
pin 3 of A2 is lower than pin 2, the triangle wave ramps negative,
forming the t 2 alternation of the output. The times are equal because
the magnitude of the OTA output current is the same for either
polarity.
The asset that the OTA lends to this application is a wide range
of current output, which will linearly follow the IABc programming
input. In this example, the constant current, I.me, is set up by Qi
and its associated components, which form a current regulator. The
series combination of D 1 and LED 1 make up an equivalent 10-volt
zener, which is used to stabilize the pin 5 threshold of the 555. This
makes the amplitude of the triangle waveform independent of sup-
ply voltage. The LED also biases Qi as a current source (see Chap-
ter 4, Section 4.13, Fig. 4-20). Current output is adjusted by RABc,
the emitter resistance of Qi. Here, RABC is adjustable over a 5000:1
range; thus, the timing period and frequency of this oscillator are
also adjustable over a 5000: 1 range. In this circuit, the range spans
10 Hz to 50 kHz, but other ranges are possible by appropriate selec-
tion of Ct.
\Vith a FET-input device utilized for A:~, the permissible range
of It (or IA.Be) can go as low as 1 nA (or less). This indicates that
the inherent capability of the circuit is even greater than is realized
in this particular example. If It is appreciably greater than the
threshold current of the 555, and a triangle-wave output is not
necessary, the circuit can be simplified by eliminating A3 and driv-
ing the 555 directly from Ct. In general, this is permissible for cur-
rents of 1 µA or more.
6.4.3 Function Generator With Logarithmic Control Characteristics
A function generator with an even wider tuning range is shown
in Fig. 6-23. This circuit utilizes the natural logarithmic relation-
ship between the base-emitter voltage ( V 1m) and the collector cur-
rent of a silicon bipolar transistor to create a tuning action that
compresses four to five decades of variation into a single control
rotation. This has the convenience of allowing a linear control to be
calibrated in even decades of frequency over its operating range.
The circuit is similar to that of Fig. 6-22 insofar as the basic wave-
forming circuits are concerned, which in this circuit comprise A1-
A3. This circuit also produces one triangle-wave and two square-
wave outputs.
The logarithmic tuning characteristic is developed by matched
monolithic transistors, Q1-Q4. This subcircuit forms a current gen-
172
"Tl
ca· Rs High-Frequency +uv
25 kn Calibrate
*t = t = (V+) C, where I is exponentially
2
°'.:,,w i 3 I' , '
R6
~ 18kn Q3t
related to V BE of Q 1.
a.
! 2(V+)C,
Ill 5 Frequency T =t1 + t2 =--3-1,
:II
ca 7 /Adjust 11 c1 •
~ 1 1.51 t
R1 9 Q4t lOµF
f=r=(V+)C,
c:II
Ill
1 kn low-
I
er /Frequency 10 (As shown, f max = l 0 kHz.)
ii" Ra Calibrate
...
c ! IABC =I, t Transistors integral to 3046 or 3086 IC array.
:II 2.5 kn
!l Triangle-Wave
c;·
:II Output
ca
CD
:II
Ill .1. C3
0= 10.lµF 4 8
. Ri
!. R v+
;. lOkn 6 TH
3 Square-Wave
0 A, OUTI 0
ca 2 Output 1
TR
a. 2 SSS V, 5 l
:II'"
3 7
n
DIS
n GND
..1.. C4
R2
0 O.OlµF
a 1.5 kn 1
Square-Wave
in R9 Output 2
:II'" RJ R4 4.7 kn
Ill
ii1n 4.7kn l.5kn
ii.
:::j µ·
w
erator with an output, I.me, which becomes the timing current, It.
Transistors Qb Q2, and Q:{ form a voltage regulator that produces
an output of 2V 1m. A reference current of nominally 500 µA is set
up in Q 1 and Q:! by resistors R;; and Rn. This current corresponds to
the full-scale It that yields the maximum operating frequency, and
the V BE of Q1-Q 2 corresponds to this maximum frequency.
The emitter resistance of Q:{ is split into two sections: control R1
and control Rs. A variable voltage output from frequency control R1
is applied to Q4 , an emitter follmver. Since Qi, Q 2 , and Q-i are mono-
lithically matched and have V 1rn/ 1,, characteristics similar to the in-
ternal transistor at pin 5 of the 3080A, the collector current of Q-i
( IA1w) will be exponentially related to the V 1m of Qi. With R1 at
maximum resistance, I,uw will be nominally equal to the reference
current, or 500 µA. As R 7 is reduced, the current ( I.uw) in Q-i will
decrease exponentially with the linearly decreasing voltage. Viewed
another way, the voltage control characteristic of Q4 is logarithmic
with respect to I.uw (and It). The wide current range of the 3080A
allows adjustment of I.me (and It) over a very wide range-five
decades or more ( 100,000: 1).
In this circuit, control Rs is used to set the lower-scale operating
point; it is adjusted for the desired low-frequency limit with fre-
quency control R 7 at minimum. Control R;; is used to calibrate the
maximum operating frequency with R 7 at maximum. \Vith the values
shown, the upper operating frequency is 10 kHz, and the lower fre-
quency limit can be, by appropriate adjustment of Rs, four or five
decades lower, as desired. There will be some interaction between
calibration controls, so adjustments should be repeated at least
twice. This circuit is very flexible due to its wide operating range
and ease of adjustment. It would make a valuable laboratory tool
as a simple and inexpensive source of quality waveforms.
6.4.4 Voltage-Controlled Oscillators
A very practical function generator circuit is the voltage-controlled
oscillator ( VCO). This circuit is valuable for instrumentation use
or in electronic music applications. It produces the basic symmetri-
cal triangle and square waveforms as outputs, but with the fre-
quency related to an external control voltage. There are actually
many different types of VCO circuits that can use IC timers to ad-
vantage. Two examples of these circuits are shown in Figs. 6-24 and
6-25.
Fig. 6-24 is a relatively straightforward VCO circuit, variations of
which are seen often in IC manufacturers' literature. The version
described here is optimized for single supply operation and uses
only three active devices. It operates with control voltages in the
range of zero to+ 15 volts, and has a tuning-range capability of three
174
+uv
.,.. C2 - C*
I
c!i" 0.1 µF .r Timing Diagram
0.01 µF
./.'\:---- 213 v+
~
"~
vi
I I
v..I __ 113 v+
< Triangle-Wa ve : : :
g. R*
I 4 8 Output : : :
Al I I I
ca R1 t lOkn v+ I I I
61 R I I I
•A lOkn TH I I I
0 3 I I I
V/ I I I
~ R" 2 A 1 OUT
I I Square-Wav e JU
2. (lOmV to
4.7knl:i TR 555 5 R, Output 1 t *
i" lOV) ~ :
Q. 7 1
R3 'DIS v, 1okn i ~ t 2*
0 R2 t Low-
lOkn 10 kn I I
Frequency GND cl High-
2:iii : T* :
Calibrate O.OlµF Frequency ..,_ --
i Calibrate
!. 21 4 9' +uv
;.
;· 10,11,12tJ 7 I 6.ls1 is, !s, A, 114 Square-Wav e
Al Output 2
*For v+ = 15 V,
•.
I
·~40
I 16
< I I
~ lOR C
Al 13 t1 =t2=-v-1 ,-1
ca 31 5 8 6 •R
• 6
ti T= t 20R I I
0 4.7kn 1
+ t2 = v, c
a
~ f=~=_v_,_
T 20R, C1
(As shown, f is variable from 5 Hz to 5 kHz.)
t Ground unused CMOS switch terminals.
t Ri = R2.
5i
decades or more, with the output frequency linearly related to the
control voltage.
The 555 timer, Ai, is used as a Schmitt trigger, which establishes
input voltage thresholds of l/3V+ and 213V+, respectively. Op
amp A2 is connected as an integrator, which forms a symmetrical
triangle wave at its output with an amplitude of 1/ 3V + (set by the
555). A3 is a 4016 CMOS quad bilateral switch that connects tim-
ing resistor Rt either to the control voltage ( Vc) or to ground. (Only
three sections of the 4016 are used in this circuit; terminals for the
other section should be grounded. )
In operation, with an input of V c volts applied, a matched pair
of resistors, R 1 and R 2 , establish a bias voltage reference for Az of
Vcl 2 volts. With section S1 of A3 "on," Rt is connected to ground,
which causes a current equal to V cl 2Rt to flow in Rt. This (constant)
current causes a linearly rising ramp of voltage to appear across Ct
at the output of A2 • When this voltage ramp reaches 213V+, the
output of the 555 goes low, switching section S2 of A3 ..on," which in
turn connects Rt to Ve·· This again causes a current of Vcl 2Rt to flow
in Rt, but in the opposite direction, which causes the voltage across
Ct to ramp downward. When this voltage reaches 113V +, the cycle
repeats.
The output of A 2 will oscillate between the limits of 113V + and
2/3V+ for any value of Ve. However, since the current in Rt is pro-
portional to Vc, the slope of the ramps produced (i.e., timing pe-
riods t 1 and t 2 ) will be inversely proportional to Vc, which in turn
makes the frequency of operation directly proportional to Vc· This
behavior is consistent over a range of voltages that are compatible
with the input characteristics of the op amp used for A2 • Therefore,
a device that can operate with a Ve near ground (a 3140) is used in
this circuit to optimize the dynamic range. The fact that the 3140 is a
FET-input device also permits large values of timing resistance to
be used.
In order for this circuit to operate at its maximum capability, it
is recommended that offset nulling, in the form of control R 3 , be
used with A2 • This control also serves to calibrate the low-frequency
end of the operating range, at a Ve of 10 mV. Calibration of the high-
frequency end of the operating range is done with R5 , which trims
the 555 threshold about the nominal 10-volt point. An alternative
method of achieving high-frequency calibration would be to trim Rt.
Note that the threshold levels in this circuit are referenced to V +,
which will require regulation for best stability if Ve is supplied from
an external source. However, if Ve is derived as a fraction of V+
(such as a voltage divider or potentiometer), variations in V + will
have little effect, since the circuit would be ratiometric. For best
results, Ve should also be a low-impedance source.
176
A VCO function-gen erator circuit in which the output frequency
is exponentiall y related to the control voltage is shown in Fig. 6-25.
In this circuit, a linear increment of control voltage causes an ex-
ponential change in the output frequency. In practice, this type of
VCO is advantageou s because it can be driven with a linear time
base of voltage and used with a logarithmic frequency display, as
for example in frequency-re sponse tests.
This circuit is like that of Fig. 6-23 in terms of its function-
generator circuitry. Here, A2, A3 , and Ai are connected similarly to
their counterparts of Fig. 6-23. The distinguishin g feature of the
circuit of Fig. 6-25 is the timing-curre nt generator, which consists
of monolithic transistors Qi-Q:{ and op amp A.1 . It is the function of
this subcircuit to convert a linear voltage input into an exponen-
tially related current, IAnc, which ultimately becomes It. The cir-
cuit does this by again utilizing the natural logarithmic Vim/le bi-
polar transistor characteristi cs, and also the inherent close matching
between the monolithic transistors, Qi-Q:~·
In operation, a reference current of 10 nA is supplied to tran-
sistor Qi through resistor R:~. With zero volts input applied to Ri,
the 10 nA flowing in Q 1 will set up a V1m voltage drop across it.
This voltage is applied to A.1, which is a FET-input device con-
nected as a voltage follower. The output of A.1 is connected to pin 5
of the 3080A, A2. Thus, A2 sees the same voltage as Qi. Since Qi
and the internal transistor at pin 5 of the 3080A have closely matched
V nE/ le characteristi cs (as mentioned previously in Section 6.4.3 for
the circuit of Fig. 6-23), a current identical to that in Qi ( 10 nA)
will flow into pin 5 of A:i at zero volts input.
When an input voltage is applied to Ri. the collector of Q 1 begins
to rise. Because of the constant-cur rent source driving Qi, the volt-
age drop across Q 1 does not change; therefore, the incremental in-
put-voltage changes applied to Qi will appear (increased by the V BE
of Qi) at pin 3 of A.i, and thus also at pin 5 of A:!.
It is a physical property of matched silicon bipolar transistors that
for each 10-to-l change in collector current the base-emitter voltage
must change by a factor of 60 m V (at room temperature ). In the
circuit of Fig. 6-25, it can be seen that an input change of 60 m V
to the emitter of Qi will also appear as a 60-m V change to pin 5 of
the 3080A, by virtue of the voltage follower, A4 • Therefore, with Qi
operating at 10 nA, increasing the input voltage to the emitter of Qi
by 60 m V will increase the current ( IAnc) to pin 5 of the 3080A by
a factor of 10 (to 100 nA). Further increases in the input voltage
follow the same progression; each 60-m V change in voltage to the
emitter of Qi causes a 10-to-l change in IAnc (and thus also in It).
The useful range of this circuit is four decades, and it is set up
for a timing-curre nt range of 10 nA to 100 µA. With the Ct value
177
:::i R"
+nv
00
150kn
*t = t = 5C,
"" C2 i 2 I,
<?" 11 8
9" 9 6 at I O.lµF T=t +t = lOC,
v at
2 3 1 2 I,
~
< 7 f=_!_=_I,_
g. R1
QI T lOC,
ca 33kn Rs R6 where_
0 2.2kn lkn )
( R2Vc
I = 10 (Rl + R2) 0.06 -a
'a"' a 1t ~t
i 3 l
i" For values shown,
a. ] o<Vc/21-8
! ~ f=--- Triangle-Wave
£: lOC,
ii I Output
t Transistors integral to 3046 or
i 3086 IC array.
E c1
;: 0.1 µF
>C
• Ra J_ C3 4
'U R2 Square-Wave
0 O.lµF R
:a 1 kn lOkn l 6 Output 1
:a
• TH
::r. IABC
l 3
!.
<
0
:;' 2
QI 7 s
ca DIS Ve
• R9 GND ISquare-Wave
0 1.5 kn Output 2
a"' 3 R12 1 I
~ Rio R11 C,* 4.7 kn
4.7 kn l.5kn O.OOlµF c..
0.01 µF
shown, this yields a frequency range of 1 Hz to 10 kHz. Since an in-
put voltage range of 60 m V per decade is a rather awkward parame-
ter for system use, the input voltage divider, R 1-R:!, scales a larger
(and more practical) input voltage range down to the required
levels. As shown, the circuit has a tuning range of 2 volts per decade;
i.e., zero volts = 1 Hz and 8 volts = 10 kHz. This can actually be
scaled to any value desired by the appropriate choice of R 1 •
Because of the nature of the current generator used in this cir-
cuit, frequency calibration of the circuit is somewhat more complex
than in the previous circuit of Fig. 6-24. Offset nulling of A 1 is
mandatory for calibration, due to the low voltages seen at the input.
This can be accomplished initially by temporarily shorting Q 1 and
applying 400 mV to pin 3 of Ai. Then, using a DVM of 1-mV sensi-
tivity, adjust R 7 for the least voltage differential between terminals
2 and 3 of A"1. This should produce a lc)\v-end frequency close to 1
Hz. If the frequency is within 20% of 1 Hz, it can be adjusted more
precisely with a final touch-up trim of R 7 • Calibration of the high-
end frequency is accomplished by applying an 8-volt input to H,,
and then trimming H 1 for an output frequency of 10 kHz.
6.4.5 Triangle-to-Sine-Wav e Converter
The triangle-to-sine-wav e converter shown in Fig. 6-26 is appro-
priate for use with any of the function-generator circuits described
in this section. This circuit converts the constant-amplitude, triangle-
wave output of the basic function generator into a low-distortion,
constant-amplitude sine wave. The circuit operates on the principle
of the gradual cutoff characteristics of a differential transistor pair, a
concept of sine-wave shaping introduced by Grebene. ~
In this circuit, transistors Q 1 and Q:c are a pair of monolithically
matched devices. These transistors, along with Q:1 and Q"1, are con-
tained in a single IC array-the 3046 (or 3086). With the triangle-
waveform drive to Q 1 at an optimum level, there will exist an opti-
mum value of emitter coupling resistance, R 1.:, that will minimize the
distortion content of the sine-wave output. Both of these conditions
(i.e., optimum drive and optimum emitter resistance) must be met
for minimum output distortfon. \Vith regard to the drive at the base
of Qh the optimum triangle-wave amplitude is 346 m V p-p, and the
R 1 -R:~ input attenuator should be designed for this level. The R 1-R 2
values shown assume an input of 5 volts p-p; they should be altered
if an input level other than 5 volts is used. \Vith correct drive, RE
is trimmed for a distortion null in the output, and for the design
shown, the RE value will be in the range of 240 ohms.
0
A. B. Grebene, "Monolithic \Vavefonn Generation," IEEE Spectrum, April
1972.
179
+15V
r----
I R3 R9
I C2
2.2 kn 18kn
: Rio
11-'F
f-k~ ---., 11
+~Vout
c1 rll Qlt
2.5-V rms
5 REt Q2f 9
10 f.lF 1 1 Mn Sine Wave
V," o---;I 250n
4 10 Rs
5-V p-p I R1* R*
2 3
Triangle Wave : 15 kn 1.1 kn 1 kn
I
I
I R4
I 03t 8 04t 14
I D1 lOkn
: 1N754 6 12
I
I 7 13
I
I Rs R6 R1
I 2.2 kn
I 2.2kn 2.2 kn
L ____
* V,"(R, ; RJ = 0.346 V
(As shown, R1 and R2 values are for a Vin of 5 V p-p.)
t Re = 240 n nominal. Use trim network for lowest THO (see text).
t Transistors integral to 3046 or 3086 IC array.
Fig. 6-26. Triangle-to-sine-wave converter.
180
performance, wide-range pulse generator. Both the pulse repetition
rate and the pulse width are adjustable in this design over ranges
exceeding four decades. The circuit consists of two functional blocks:
the repetition-rate ( reprate) generator consisting of timer A 1 and
its associated circuitry; and the pulse generator, timer A~ and its
associated circuitry. Positive output pulses from the reprate gener-
ator trigger the pulse generator, which then produces output pulses
of the desired width.
The reprate generator consists of a current-control led 555 astable
circuit, which is set up to produce positive-going, 7-µs output pulses.
These pulses trigger the 322 pulse generator directly. Control of the
repetition rate of these pulses controls the basic pulse-generatio n
rate of the circuit as a whole.
In the 555 astable circuit, there are two timing capacitors, Ct
1
and Ct~· Resistor Rt and capacitor Ct 1 set the width of the positive
output pulse in the normal 555 monostable manner. Capacitor
Ct~, however, is charged by current source Q 4 and discharged by
current source Q3 • During the 7-µs output pulse interval, current
source Q4 is gated by the diode gate, D 1-D 2 , into Ct.,, charging it
toward V+. After the 7-µs interval this current is rem~ved, and Ct~
is then discharged to the 5-volt pin 2 threshold of the 5.55 by current
source Q:1 . This particular circuit arrangement causes the output
pulse frequency to be a linear function of the current from Q:~· Thus,
this circuit can be directly calibrated for frequency in terms of the
current output of Q;1 •
Transistor Q:~ is an exponential, voltage-control led current source,
similar to that previously described in Section 6.4.3, Fig. 6-23. Here,
R 1 and R 2 set up the reference current in Qi, and Q:i conducts a
percentage of this current depending on the setting of the pulse-
rate control, Ra. The full-scale setting of R 3 produces the maximum
frequency, and lower frequencies are produced at lower settings of
Ra. The full-scale frequency is trimmed to calibration by Rh and
the low-frequency limit is calibrated by R4 , which sets the range
of Ra.
The practical low-frequency limit in this circuit is about five
decades below full scale when buffer transistor Q10 is used. If a
tuning range this broad is not desired, Q10 and Rm can be elimi-
nated, and Ct~ connected directly to the timer. The range of this
configuration will be about three decades, and is limited by the 55.5.
The reprate generator also has a trigger output from amplifier stage
Q;;. The negative-going spikes at this output terminal can be used
for external synchronization , etc.
The pulse-generato r circuit also uses an exponentially variable
current generator to achieve single-control, wide-range timing. In
this circuit, Q9 is the controlled current source. The pnp transistor
181
CD
-..., High-Frequency
+uv A
Calibrate ?
R6 c1
R,
lkn
R,
I/LED ~J=-;-i
25kn 1
10
MV5020
2 22kn I " Tdgge.
R ~ 8 a. o,
33kn A 7
Qt 2N3906 1N914 R Output
4.7kn 12
17 02
Q,* 4\ 5 , 13
1N914 QlO Re
31
, E230 I ~ 1 kn
RJ 2 QJ*
lkn Pulse
ourf3_J1L_______ • B
3
Rate 21TR 5~~ 5
Ve
Ri6
47kn _L c
c,2 2
1
1500pF C, 0.01 µF
220pF
----...-~
"'l'I Low-Frequency
~·
Calibrate
t~ c
*Transistors integral to 3046 or 3086 IC array.
~
0.: t Matched transistor pair such as 2N38 l 0 dual unit, or
.t pair of selected discrete units such as 2N3906s .
:II
ca
•
"D
!-
CD A---~~~~~~~~~~~~~~
~~~~~~ ---,
caCD
:I
I f f l I
Ill
=
~
52
51
Q9t Pulse Polarity
R11 ~- I
lkn Pulse
(+)
Width
QB t
Q7
2N3906
c,3
11
220 pF
Q6*
10
R12
2.5 kn
Minimum-Width
Calibrate
m
-
w
pair, QH-Qn, operates analogously to the npn pair, Q1-Q:l, and pro-
duces an output current to the pulse-generator timing capacitor,
Cta. The timing current is exponentially related to the V BE of QR in
this case. This gives the pulse generator a control range of five
decades or more within one rotation of potentiometer R11, the pulse-
width control.
The reference current for this current-generator circuit is derived
from Q1 via Qn, a transistor that scales down the Q1 current to the
requirements of the pulse-generator circuit. The reference current
flowing in Q1 is approximately 300 µ,A; this current is reduced by a
factor of about ten by QH. The final operating current for Qs-Q9 is
set by control R 12 , which calibrates the minimum pulse width of the
circuit, with R 11 set to minimum width. Control R 10 calibrates the
maximum pulse width, with R 11 set to maximum. The range capabil-
ity here is about five decades, if a matched transistor pair such as a
2N3810 dual unit is used for transistors Q8 and Qu. Alternatively, a
pair of discrete transistors that have similar base-emitter voltages
at 50 µ,A can be selected from a batch of 2N3906s or other high-gain
units.
To realize best performance over the total operable range of this
circuit, the boost connection of the 322 (pin 11) should be opti-
mized for the operating pulse width. This is done via switch S2,
which should connect the boost below 1 ms and disconnect it above
1 ms. Switch S1 programs the logic input of the 322 (pin 2) for the
desired polarity of output, and switch S8 adjusts the amplitude of
the pulse output. With the values shown, the maximum operating
frequency is 50 kHz, and the minimum pulse width is 10 µ,s. The
opposite end of the respective frequency and pulse-width ranges can
be set by the user as desired, and can be 0.5 Hz ( or lower) for pulse
rate, or 1 second (or more) for pulse width. Once set up, the oper-
ation of this circuit is stable, and there is no control interaction.
184
v+
Ve
Input
Voltage
l
Level Sensor
Monostable
(Comparator)
t,. V ·.J==~ I
I
I
I
I
I
t 1* --+.---I
I
_n_
I
tl*~t----tt~
I I
~T*~ Output
*Basic V/F relationships: Pulse
_t. vc 1 _t. vc 1
t 1 - - - , and, t2- - - .
12-11 11
Thus, t.VC 1 =t 1 (1 2 -1 1),and,t.VC =t 1 , so, t {1 -1 )=t 1 .
1 2 1 1 2 1 2 1
Then t 2 in terms of t 1 is:
- tl(l2-l1)
t2- 11 .
T=t +t =t +(t1(12-l1 ))
1 2 1 11 .
Simplifying, T = t 1 ( ~) ·
In terms of frequency, f = ~T = 11
- - •
t 1 12
185
in resistor Ra. During period ti, the gated current source, 12, is
switched "on," and the current in C 1 will be the algebraic sum of
currents I:! and I 1. (In this circuit, current I:! must always be greater
than current Ii.) During period t:.!, current source 12 is "off," and
the current in C 1 will consist only of Ii.
The alternate switching of currents 11 and 12 into the integrator
causes the output of the integrator to ramp up and down by a volt-
age of !l. V, the difference between the amplitude limits. One ampli-
tude peak of /::,. V (in this case the positive peak) is fixed by the com-
parison threshold established by the level sensor. When the ramp
reaches this threshold (at the end of period t:!), the level sensor
changes state, which fires the monostable producing the output
pulse of width t 1 • The gated current, h then causes the integrator to
ramp down for the t 1 period, causing a voltage change of !l. V. This
voltage change will vary with the magnitude of Ii (and the input
voltage), being maximum at lower levels of I 1.
With the application of some basic charge/voltage relationships
and op-amp theory, it can be shown that the basic t 1 and t:.! relation-
ships are:
/l.VC1
I1'
t l =:!--1
!l. VC1
t:! =-I-1-.
Both of these equations contain the term !l. VC 1 due to the charge-
balancing mechanism; therefore, in terms of t 1 and t 2 , the two equa-
tions can be expressed mathematically as being equal to !l. VC 1 and
thus equal to each other, or:
ti ( 12 - 11) = t:!l1.
Then the equation fort:! can be expressed in terms of t 1 as
_ tt(h- Ii)
t.:! - 11 .
The equation for the total period, T, is simply the sum of ti and t 2 ,
or:
T =ti+ t2
=ti+ c1(\~ Ii)).
After some simplification, this becomes
186
f = .!.
T
11
ttl2.
These last two equations are the crux of the entire matter insofar as
the theory of v / f converters is concerned , and warrant some dis-
cussion. For example, it can be seen from the frequency expression
that frequency is directly proportion al to I h which is the input cur-
rent. Therefore, conversion sensitivity can be scaled for a given volt-
age by adjustmen t of Ra. Frequency is also inversely proportion al to
t 1 and h Note that in terms of 11 and 12 , the equation is ratiometric .
Thus, if 12 and l 1 are made to track one another in the same propor-
tion, there will be no net change in frequency. This point has im-
portant practical value, as will be seen in the first actual v/f circuit
described.
It should also be noted that the AV and C1 terms have disap-
peared. The practical implicatio n of this point is that neither C 1 nor
the comparato r threshold need be highly stable to maintain accu-
racy, as their drifts cancel during operation. The required stable
elements are only those that affect It, h, or t 1 • All but one of the
blocks in the block diagram can be satisfied by the use of an IC
timer. With the addition of a high-perfo rmance op amp, a high-
quality v If converter can be built at very reasonable cost.
Fig. 6-29 illustrates a high-perfo rmance v/f converter that ac-
cepts control voltage inputs in the range of zero to -10 volts, with
-10 volts yielding a full-scale output frequency of 10 kHz. The cir-
cuit uses two 322 timers and an op amp, plus some additional com-
ponents. Output 2 is a series of positive-going pulses that are nomi-
nally 15 volts in amplitude but can be programm ed to other logic
levels. Output 1 delivers TTL-comp atible pulses of width t 1 •
This circuit very closely resembles the block diagram of Fig. 6-28
in almost all respects. Amplifier A 1 is the op-amp integrator; A 2 is
the comparato r; and A:{ is the precision monostabl e. Transistor Q 1
is a switch that connects Rh to the 3.15-volt reference voltage during
the t 1 timing period of timer A3 , performin g the gated-curr ent-
source function. The design is based on an 12 of 1 mA, a t 1 of 50 µs,
and an 11 of 0.5 mA for a full-scale frequency of 10 kHz.
Within the circuit, the comparato r threshold of A2 is +3.15 volts
establishe d by connecting pin 7 to pin 4, the reference output. This
threshold establishes the upper limit of the AV output swing of Ai.
As A1 reaches the 3.15-volt threshold, the A2 comparato r output goes
high, which fires monostabl e A;{. A3 is a 322 timer set up for a nomi-
nal t 1 pulse width of 50 µs. During the t 1 period, Qi is saturated,
which forces a nominal current of 1 mA through Rb. This current
187
OI)
OI) +lSV
-
.,,
c?' o,
'l" I 2* ! 2N2219 Rs
~ io kn
ca·%::r c2 Jl
.,; 10 kn I O.lµF
Output 2
0
-= 31 111 3 11
3
Ill
Rt(
10 kn TR
3-1 /3 k~ TR B I.~ I B 110
~ 2 L
CD R4 v+
25
~ A2 k!l AJ
10 kn c, 4lv c 12 4 v
... R2 322 mo { 322
0
<
-
::::J 11 ;- _____ _j
0.022 µF 1kn 1 R/t
c~ 1
Output 1
5IR/C E E (TTL Compatible)
Vt GND
= lOkn lOkn va GND I
0 V to
7 6 95.3 kn 6
!.
= -lOY
;. 1%
::::J Ra *t 20 kn
CD RJ
ca
~ lOOkn =
::c·
CD C4
;· *f =_v_,_
"D 150pF Low-Frequency Ra t, I2
s.
n
Calibrate = 1000 v,
0 R6
a 2.7 kn
C3 where,
2. 0.1 µF
t1 0
= R, C, = 50µs, R = 20 kn, 1 = 1 mA. 2
<
~
Ill t R,, C 1 , R0 , and Rb are stable, low- TC components (see text).
ca
!'
r -15 v
causes Ai to ramp negative for the ti period. When the ti period has
ended, h is switched off and Ai ramps positive (again) toward the
3.15-volt threshold.
There are several details of this circuit that are worthy of mention
in the interest of optimizing performan ce. The Ii and 12 current-
determinin g resistors, Ra and Rb, are best contained within a
matched resistor array, preferably one with low differentia l match-
ing errors and a low tracking TC. If this is done, there will be no
sacrifice in accuracy and there will be a considerab le savings in
cost. Absolute tolerances for Ra and Rb should be l % in order to
guarantee the calibration of the circuit. As an alternative , Ra and Rb
can be 20 kn and 3.3 kn low-TC discrete resistors. For best per-
formance, Rt and Ct, which are the only other passive componen ts
that influence accuracy, should be low-TC types and of high qual-
ity in general. This would indicate a metal film resistor and a cermet
trimmer for Rt, and a polystyren e or polycarbo nate capacitor for Ct.
Overall calibration is achieved by nulling the offset voltage of Ai
at an input of 10 m V for low-freque ncy calibration , while Rt is
trimmed with an input of 10 volts for a full-scale output frequency
of 10 kHz. These adjustmen ts should be repeated at least once.
When calibrated , this circuit has a useful dynamic range of greater
than 10,000: 1, and nonlineari ty is better than 0.05% of full scale.
Possible options to the circuit could include adjustmen ts of Ra for
different input voltage sensitivities, or the use of a current input con-
nected directly to the inverting ( - ) input of A 1 . Full-scale current
would be 0.5 mA in this case. Due to the internal regulation , oper-
ation is essentially independe nt of the ±15-volt power-sup ply levels.
A more modest performan ce version of this circuit can be built by
substitutin g a 3140 for A 1 , which also allows single-sup ply operation
(by grounding pin 4 of the 3140). The 3140 should also be nulled
for low-freque ncy calibration .
A v / f converter that accepts positive inputs in the range of zero
to + 10 volts is shown in Fig. 6-30. This circuit is otherwise similar
to the previous one in terms of input sensitivity, scale factor, and
output pulse form. It also features a high degree of supply-vo ltage
immunity and stable operation over a range of input voltages of
three decades or more. Although this circuit does not obviously re-
semble the block diagram of Fig. 6-28, it does operate in a similar
manner; the "blocks" of the system are just not as readily apparent.
In this circuit, Ci is the charge-ba lance capacitor and is here con-
nected to ground. The main difference in form between this circuit
and the previous one is that there is no integratin g op amp. There-
fore, C 1 is charged and discharged by two active current sources,
which produce the currents 11 and h Current 11 is generated by Ai
and its associated componen ts, which make up a precision voltage-
189
;
0
"Tl A3 OUT
cp· v+~
(+1ov to 317
°" ADJ R,
1.2 kn l .~kn i.21 kn l kn
w +15V) I C5 D.
!=> Ql 1%
= 0.1 µF 1N4001
x 2N3906
ca·:r
r r v· Q2
D2
I
-a 2N3906
s. R7 1N914
0
3.3 kn --++
3
DI R3 Ra* t Dl ll '2* --
~ l N914 R,*t 8
Ill l kn 4
11 .45.3 kn
~ High-Frequency R• R v+
1% _fl
Calibrate TH
n
- 6 13
0 D3 A2OUT Output
:I
< 1% 1N914 2 TR 555 (TTL Compatible)
~ 6 7
= R*1
DIS
~
~· V* 3 C1 GND
:r ,~
"'C lOk!! R* c. 0.1 µF c,* t
0 V to 2
1% 100 pF 1000 pF
~· +10 v l kn
<. 1% 1%
Ill R,o
:;·
"O lOMn
~ R9
n *f =
0 50 kn k~~ 1J(R1 ~RJ
+15V () VvV\, • II---'
a = 1000 v,
i Low-Frequency
where, R
< Calibrate 2
~ Ra= 1.818 kn, ti= R, C, = 50 µs, 12 = l mA, R1 + R2- - 11
DI
v-
ca
!' (-10 V to
t R,, C,, Ra, and Rb ore stable, low-TC components (see text).
-15V)
controlled current source ( VCCS ) . The input voltage, in the 0- to
+ 10-volt range, is divided by R 1 and R2 , and is then applied to the
noninverting ( +) input of Ai. The connection of Q3 in the feedback
loop forces a current through Ra that drops a voltage equal to the
voltage across R2 , which is a precise fraction of the input voltage, Ve.
Thus, the collector current of Q 3 is made to be a precise linear func-
tion of Ve. This collector current is current 11 , which in this case dis-
charges Ci during the t 2 timing interval.
In this circuit, a 555 (A:~) performs both the functions of the level
sensor and the precision monostable. This is accomplished by using
the l/3V+ threshold of the pin-2 trigger input to sense the voltage
on Ci, and to fire the monostable when this voltage reaches the
l/3V+ level. The pulse width produced is l.lRtCt, as in the con-
ventional case. A further refinement is the regulation of the supply
voltage to the 555, which highly stabilizes the ti pulse width. With
the supply voltage chosen ( +5 volts), this also provides an auto-
matic TTL-compatibl e output.
The function of the gated current source, 12, is accomplished by
A3 , a 317 regulator, which also provides a stabilized voltage output
for the 555 and A1 • The current-regulat or function is provided by
Q2, which produces a nominal current output of I mA. This current
charges C 1 during the time ti, and is gated into C 1 by the Di-D2
diode gate when the 555 output is high. The voltage output of the
regulator appears across R 8 and is nominally 5.6 volts, which is
dropped to 5.0 volts for the 555 by diode D 4 • If a TTL-compatib le
output is not necessary, D 4 can be eliminated (shorted) with no re-
duction in performance. The overall system is similar to that de-
scribed in the block diagram of Fig. 6-28, except for the slope of the
charge and discharge of Ci. Here, Ci charges in a positive direction
during ti and in a negative direction during t 2. This, however, is
just a difference in application, not in basic concept.
Circuit components that influence accuracy-name ly, Ra, Rb, Rt,
and Ct-require good stability, as was described for their counter-
parts of Fig. 6-29. Also, the input divider resistors, R 1 and R2, should
be stable I% types. The op amp used for Ai warrants some discus-
sion insofar as optimizing the cost/performan ce of the circuit is con-
cerned. The device shown, the 308A, is a precision, low-offset, low-
drift type, a consideration that is necessary because only I volt full
scale is applied to the noninverting input of Ai. Three decades below
this level, the input voltage is only I m V, so the offset and drift
errors of Ai can be significant if not controlled. The 308A has a
typical offset of 300 µV, which allows a three-decade tuning range
even without offset nulling. However, for best low-level linearity, A1
should be nulled anyway; thus, R9 and R 10 are included in the cir-
cuit for this purpose. As an alternative, a 308 or a 301A can be sub-
191
stituted for Ai with reasonably good performance resulting after
nulling. These types will require a reduction of Rio by a factor of 10
in order to accommodate their higher offset voltage. Finally, if de-
sired, this circuit can be made to operate from a single power supply
by using a 3140 for Ai. This is accomplished by grounding pin 4 of
the 3140 and using its regular nulling connections.
Input Signal
{Frequency to be Measured)
,__ J __,
: Waveform : Integrator
Precision Precision
1 Conditioner
Monostable Limiter (Low-Pass Filter)
:(Comparator):
L _______ J
DC Output
(Average Voltage Proportional
to Frequency)
192
The final block is an integrator, which smoothes the de time-
averaged pulses into a ripple-free de voltage. This voltage repre-
sents the input frequency , and adjustmen ts of the monostabl e pulse
width (or limiter amplitude ) can be made to calibrate the system
for specific scale factors.
Efficient design of a frequency- to-voltage conversion system is
aided greatly by IC timers, which incorporat e most of the capabili-
ties outlined in Fig. 6-31. Examples of these application s are shown
in Figs. 6-32 and 6-33.
In Fig. 6-32~, a 322 timer is shown in a very simple configurat ion
that is suitable for use as a basic frequency meter, in this case a
tachomete r. Here, the 322 is connected as a calibrated monostabl e.
The emitter output mode is used, with the collector tied to the refer-
ence voltage. When triggered, the output of the monostabl e goes
high for the timing period. The pulse width is effectively regulated
by the basic characteris tics of the 322, while the pulse amplitude is
limited to the reference voltage by the collector connection . Thus,
this circuit functions as both a precision monostabl e and a limiter,
simultaneo usly.
For use as a frequency meter or tachomete r, a de meter connected
across R 2 will integrate the pulses, in many cases with no additional
componen ts. At low frequencie s or for lightly damped meter move-
ments, some additional filtering in the form of shunt capacitanc e
may be necessary.
This circuit can be used as a simple tachomete r to indicate engine
rpm by applying the informatio n in the table for the particular en-
gine in use. Note that a 60-Hz reference input applied to this cir-
cuit can be used as a frequency calibration standard; for an eight-
cylinder, four-cycle engine, this frequency correspond s to 900 rpm.
Full-scale de output of the circuit is 3 volts, and R 1 is adjusted to
obtain a pulse width that gives the correct rpm indication . In the
example shown, this would be 0.18 of full scale (for 900 Hz). Full
scale in this case would be 5000 rpm.
Trigger input conditioni ng must be used with this circuit for
tachomete r use; therefore, an input network for this purpose is
shown in the inset. Some adjustmen t of componen t values may be
required for specific circumstan ces.
A circuit that is more suited to bench or lab use as a frequency
meter is shown in Fig. 6-33. This circuit is identical in concept to
that of Fig. 6-32 insofar as the use of the 322 is concerned . How-
ever, it also includes a post filter and scaling amplifier. Here the 322
0
C. Nelson, Versatile Timer Operates From Microseconds to Hours, National
Semiconduc tor Application Note AN-97, December 1973. National Semiconduc -
tor Corp., Santa Clara, Calif.
193
...
"°,,.
Input Conditioning for Tachometer Use
From lOko
.... Distributor o--1~ Basic Tachometer Information
c?" Points
~ber ofCylinders I 4 +ti~8
°"w Plug Firings/ ' 2
I 3 j 4
~
~ Revolution -+-- --~
<
Plug Firings/ J 16.? 25 33.33 j
1
i
0::J Second @ 500 RPM I ~
<
ID
:::. v+ RPM Calibration I 1aoo I 1200 I 900 I
~ Point for 60 Hz L I ---l
Ill
Jl
Plug Firings/ I 166.7 I 250 1 333.3
"'D" Trigger 111
31 Second @ 5000 RPM I
e:
;:;· 2 I TR B I 10
; v+
.a
-c
ID 4lv Ai c I 12 *Let T =Rt ----
_ f 0.95
Ct =
full scale
~ R.* 322 .IL
'<
300 k!l (As shown, ffull scale= 333.3 Hz; suitable for
3 5IR/C E
ID
v GND 8-cylinder engine, 5000 rpm full scale.)
i DC Output
-::;- C,*
7 6 I Full Scale= 3 V
~
:r 0.01 µF
0
3 Ri R2
~
l k!l Full-Scale 3.9 kn
~ Calibrate
i" v+
( +9 V to + 15 V)
"~ Full-Scale
~ Calibrate
Cs
,,< O.lµF
0
:I
r R..i c4
Rs
lOOkn
Jl lOOkn 47pF
i= Trigger
II 3
__._
Ill
Ill ii
~!
JLTR
:I
"1:1 A1
la CD 4
II :::- v, 322 _rt R1 R3 DC Output
3 CD R,* C
n lOMn
"1:1 .a lOMn Full Scale= 5 V
560kn 5IR/C
Cl
;; i:I
:" ~
c1 C2
~ II 1500 pF 1500 pF Zero
C*
I
Calibrate
R1
I
E
::;.·
1500 pF
3.9kn
:r
~
"'a
0
ii" *Let T = R C _ 0.95
:::!> I t=f-
full scale
f
II
:I (As shown, f 1ullscale = 1 kHz.)
CL.
;
"'
is wired as before, and generates positive output pulses across Ri.
These pulses are integrated by the filter I amplifier consisting of
R 2-Ci, R:~-C 2 , and A2 • This two-pole filter effectively removes ripple
due to the pulses, and the amplifier provides gain and zero adjust-
ments. This allows exact trimming at both the upper and lower
limits of the frequency range.
A 3130 op amp is used for A2 because of its rail-to-rail output
swing capability. The full-scale output is 5 volts, and with the buf-
fering capability that the amplifier provides, this circuit can readily
drive low-sensitivity meters, etc. Control Rn provides low-frequency
calibration at 1I100 of full scale, and Rr; provides high-frequency
calibration at full scale. As shown, full scale is set for 1 kHz, but Rt
(or Ct) can be switched for other ranges. This circuit can be bat-
tery operated, if desired, and makes a handy portable tool.
A very high accuracy f Iv converter can be implemented by using
the basic components of a v / f converter, as shown in Fig. 6-34.
This circuit is simply a v/f converter that has been reconnected to
perform the f Iv function. It also follows the block diagram of Fig.
6-31, but with higher precision. The frequency to be converted is
applied to monostable A 2 , either directly if in the form of pulses or
square waves compatible with the 322 trigger requirements, or indi-
rectly after first being conditioned. Low-frequency or slow-rate-of-
rise waveforms can be shaped by a zero-crossing detector (see Fig.
6-5), which would be the function shown in the dotted block. The
standardized output pulses from the monostable drive Rb, which
forms the input resistor of op amp A 1 . A 1 is connected here as a scal-
ing amplifier and filter. Resistor Ra is connected as a feedback re-
sistor, and capacitor C 1 filters the pulse content from the output
waveform, producing a smoothed de output.
The output voltage range of this circuit is exactly the same as the
input range of the v/f converter on which it is based, namely, zero
to -10 volts. The full-scale frequency is 10 kHz, and all other design
parameters and stability considerations are simliar to Fig. 6-29. The
circuit can be optimized for dynamic range by calibrating with R 1
at the low end, and with Rr; at the high end.
One problem that often arises in system design is the "odd" power-
supply voltage. This is usually a negative voltage for one particular
circuit, when 99% of the system uses a positive voltage. Another
example is a voltage higher than the standard positive supply bus
of the system. With just a few additional components, 555-type
timers can be operated as transformerless de-to-de converters that
can simply and easily satisfy many of these low-power, odd-voltage
196
+15V
l' * 2 a,
l_ C2 R4
r------ 2N2219 10 kn
I
; I 0.1 /LF
I I
r---------,I
I
I : Input Signal :
I Conditioning
.,, I I
I I
ca· Rb t
[~: I
{See Text)
I 31 111
I , lOkn L---------.J 21 TR B 110
.,..°"w L v+
::z:: I
ca·:r -------~ lOkn J v, A,
322
c 112
~ c1
n ...,{ 5
!; R/C *V 0 = fR 0
t 1 12
Ill
n GND
'<
1%
6 -1000
< c,*t
R3 Ro* t where,
-
n
0
:i 2.7 kn 470pF
R0 kn, t 1
< .---- 1%
= 20 = R, C, = 50 /Ls,
~ 12 = l mA.
~ R2
4.7Mn tR,, C,, R
0
, and Rb are stable,
CJ low-TC components.
+15V~~
Low-Frequency 0.1/LF =
Calibrate -15V
DC Output*
Input
FrequencJ1n.
'°'4
requirements. Examples of this type of use are illustrated in Figs.
6-35 through 6-39. Fig. 6-35 is a very basic de/ de converter that
produces a negative output voltage from a positive voltage source.
This circuit is nothing more complicated than a 555 minimum-
component astable with a peak-to-peak detector across its output.
It could be used, for example, to derive the negative supply volt-
age for a number of op amps.
There are several keys to successful use of this circuit. First, it is
advantageous to operate the oscillator at a high frequency in order
to minimize the value of filter capacitance. For example, the oscil-
lation frequency of this circuit is 10 kHz. Second, the rectifier diodes
should preferably have a low forward voltage drop in order to mini-
mize their losses. For this reason, the germanium types shown are
suited to the current levels available from a 555 output. Third, this
circuit works best at the higher supply voltages; i.e., from + 10 volts
to + 15 volts. This is because the 555 totem-pole output does not
quite swing the full range of the supply voltage, and below + 10
volts, the losses due to this fact become excessive.
This circuit is suitable for light loads in the range of 10 to 20 mA.
With a 15-volt supply and a 1-kfl load, the output is about -12.4
volts; with a 10-volt supply, it drops to -7.5 volts. These figures will
be somewhat less if 1N914 silicon diodes are used for D 1 and D 2 •
To obtain higher voltages from this type of circuit, the voltage-
doubler technique can be used to advantage, as shown in Fig. 6-36.
In this circuit, a second peak-to-peak detector is added in series with
the first detector. Here, diodes D 3 and D 4 form the second detector,
with D 3 referenced to the output of the first detector filter, C 2 • The
voltage output from this circuit is approximately -24 volts with a
+ 15-volt supply, dropping to -14.5 volts with a + 10-volt supply.
v+
(+1ov to +15V)
R,
6Bkn 4 8
R v+
6
TH
3
OUT
2
TR A1
555
D1
c, GND 1N270
lOOOpF
198
v+
(+1ov to +15Y)
Rt
4
6Bkn 02
6 R
TH c1 1N270
3
OUT
2 A1
TR 10 µF
555
(2
+ 10 µF
GND
D1
c,
1N270
1000 pF
D4
C3 1N270
--~1
lOµF
D3 I C4
lOµF
i
Yo
1N270
·--j
Fig. 6-36. De/ de converter with negative output voltage doubler.
199
v+
(+lOV to +15V)
o,
4 8 1N270
v+ 02
c, 1N270
3
A OUT
2 1
TR
555 10 µF
C2
GND lOµF
+uv
4 8
R v+
6
. TH
3
A, OUT
2
TR 555 lOOOpF Q,
7 2N2219
DIS
GND o, 03
1N270 C, 1N270
lOOµF
D2
Q2 1N270
220 fl
2N3904
D*
*Output Voltage Table '
-5 V 1N751
-6 V l N751 or 1N752
-7.5 V 1N754
Fig. 6-38. De/de converter with regulated negative output voltages of -5 to -8 volts.
200
is regulated by controlling the current in Q2 • Transistor Q2 is in
tum driven by zener diode D 4 , which senses the output voltage.
This scheme is quite effective in controlling the output amplitude,
since the change in output voltage due to loading is considerably
less than 1% for load currents of 25 mA or less. The output voltage,
which is in the range of -5 to -8 volts with this circuit, is set up
simply by choosing a zener diode with a voltage that, when added
to the VBE of Q2, gives the desired voltage. For a -5-volt output,
for example, the 1N751 is appropriate.
For output voltages greater than -8 volts, the voltage doubler of
Fig. 6-39 should be used. This circuit is useful in the range of -8 to
-15 volts, and as in the circuit of Fig. 6-38, the output is scaled
by the choice of zener diode-in this case D 5 •
R,
R, 1 kn
68k!l 8
v+
Cs
3
OUT
2 A,
TR 1000 pf QI
555
7 2N2219
DIS 02
GND cl 1N270
lOOµF
c, D, c2
1N270 lOOµF
lOOOpf
+
c,
QJ Vo*
lOOµF
2N3904
D5•
Fig. 6-39. De/ de converter with regulated negative output voltages of - 8 to -15 volts.
201
continuously and always at the same frequency even in the absence
of primary power. Such a circuit is shown in Fig. 6-40. This circuit is
either a 60-Hz amplifier or an oscillator, depending on the presence
or absence of a 60-Hz ac reference signal at R 1 . In normal operation,
the presence of a 6.3-volt rms signal at R 1 causes an ac current to
flow in the Ri-C 1 series path to ground. A portion of this input volt-
age appears across C 1 ; for the values shown, this signal will be about
2 volts p-p in amplitude.
Timing capacitor Ct would normally be returned to ground in a
555 square-wave astable. In this case, however, it is connected to
Ci, which elevates the common end with the 2-volt p-p, 60-Hz ref-
erence signal. This signal passes through Ct to the timer, and is am-
plified by virtue of the timer acting as a Schmitt trigger. Thus, the
output is a square wave that is locked to the incoming 60-Hz line
frequency.
DC From D1
Primary
Power Source 1N4001
+sv to
,...----------+ - - - - - - - -0 Remainder
of System
1N4001
Backup
Battery Rt 8
Power
I 1.2 Mn v+
3
A OUT i -- - - - < 1 Output
1
TR 555 V, 5 (60-Hz Square Wave)
7
R*
1
DIS
6.3 V rms GND
(60 Hz) 22 kn C2
0.01 µF
202
sync. The output for either free-runni ng or synchroni zed operation
is a 60-Hz square wave. The particular method of sync shown here
is preferred over pulse injection at pin 5, since the R 1-C 1 network
forms a natural, low-pass filter. This minimizes sensitivity to line
transients, which could have disastrous effects if injected directly at
pin 5. The circuit is, of course, not limited to 60-Hz application s
only; it may be used at any frequency by the selection of appropriat e
componen t values. Also, the input waveform is relatively noncritica l,
due to the integrating effect of R 1 and C 1 .
The circuit of Fig. 6-41 has the capability of producing both sine
waves and square waves of low distortion from a single source. The
circuit combinati on forms an oscillator that simultaneo usly generates
both sine-wave and square-wa ve outputs, with the basic accuracy
determine d by the sine-wave portion. In the circuit, A1 is a 5.35 timer
connected in what may seem to be a minimum- componen t astable
oscillator. This would be true if the bottom end of Gi were
grounded, and the R6 -C 4 combinati on would then produce a fre-
quency of about l kHz. However, C 4 is returned to the output of A2 ,
and in operation is actually a coupling capacitor. The 555 functions
OV to +lSV
+lSV
R1
4.7 kn -, n
.-----+----+-------~---o LJ L
R1
2.2Mn
our~-+-11:-'VV\,._...-t.,__.-....i
3
A1
6
555
7
DIS
GND
47 pF
R2
8.2 kn
C4
0.01 µF
203
as an astable on start-up only; once the square-wave oscillations
start, they are coupled to the A2 circuit, which forms a multiple-
feedback bandpass filter. (Design details of this type of filter appear
in author Jung's IC Op-Amp Cookbook, published by Howard W.
Sams & Co., Inc., 1974. pp. 335-336.) This filter removes the har-
monic content of the square wave, producing a relatively clean sine-
wave output with a distortion content of less than 2%. This sine-
wave output is fed back to the timer via C 4 , and the timer in this
mode actually functions as a Schmitt trigger, shaping the input sine
wave into an output square wave.
In addition to the sine-wave output, there are two square-wave
outputs from the 55.5. A high-level output is available from pin 3,
and an isolated, open-collector output is available from pin 7. This
output may be referred to any positive voltage from 0 to 15 volts.
The interesting feature of the circuit is that the center frequency of
the filter is almost the sole determinant of frequency. The timer
components, R(j and C-i, have only a secondary effect, and serve
primarily to start the loop oscillating at about the nominal fre-
quency. In this example, the frequency is 1 kHz, but other fre-
quencies can be selected by adjusting the values of C 1 and C 2 (and
C-i for large frequency changes). Resistor R 2 can be trimmed for
fine-frequency changes. Resistor R 1 can be trimmed to adjust the
amplitude of the output waveforms; the value shown yields an out-
put of about 9 volts p-p.
The need often arises for a clock source that is capable of more
accurate and/ or stable performance than the basic RC astable timer
circuit can achieve. This type of application is usually satisfied by a
more stable oscillator, either an LC type or a crystal type. These two
forms of oscillators can also be realized with IC timers, and are
described in this section.
6. 11. 1 LC Oscillators
Both the 555 and 322 timer types can be used to build LC oscil-
lators. The realized performance of the two devices is different, how-
ever, so this discussion highlights the key points to be considered
in applying each timer to this application.
A 555 LC oscillator is shown in Fig. 6-42, and on the surface ap-
pears quite simple. However, there are a number of points that need
to be considered in optimizing the performance of this circuit. Two
basic criteria for oscillation are an in-phase feedback condition at
resonance and a loop gain greater than unity. Since a 555 inverts
signals between its input and its output, the resonant circuit used
204
v+ *C 1 =C 2 =2C
L1 =L
1
f=27TVLE
C*
1
(As shown, f = 10 kHz.)
0.047 µF
3
OUT Output
Lt A1
lOmH 555 Ve 5
7
~-...l\N'V--o.-----1 DIS
R3 GND
c= 0.047 µF 1 kn C3
0.01 µF
205
value. Lower values of R 3 suppress the astable mode, while higher
values (when allowable) enhance the LC filtering of the tank.
The output of the circuit is nominally a square wave, but the sym-
metry is not perfect due to the high voltage threshold of the 555
(l/3V+ ). The tank can develop p-p voltages in excess of V+ in
operation; thus R 2 is included as an input protection resistor for the
555. The circuit can be used with any supply voltage allowable with
the 555, and its operation is not strongly sensitive to supply-voltage
fluctuations, although it is not completely supply independent. Due
to the internal comparator delays with large input overdrive, this
circuit is best used below .50 kHz.
A circuit that is highly optimized for LC oscillator use is the 322
configuration of Fig. 6-43. This circuit uses the 322 features of
sensitive voltage comparison and internal regulation to advantage,
and has both excellent stability and supply-voltage immunity. The
322 is connected here as an inverting comparator with the collector
output loaded with a resistor to the reference voltage, rather than
to V+. This regulates the amplitude of the output, making circuit
operation highly immune to supply-voltage fluctuations.
The inverting comparator connection is used, which allows the
previously described pi network to be used as the tank circuit. Here
v+
3
R,
TR
2 1 kn
4 A, 12
---u Output
V,
322
C i-:-=----..._---
RJ 3 v p-p
.-J"l"'k"'n_ _ _--1:-_5-1 R/C E 1
I Vo GND
~ R4 71
I
6
~ 1 kn I
Optional +----J
(see text) ~ Rs
~ 1 kn *C, = C2 = 2C
"-------------' l1 =l
l 1* 1
100 mH
f=27TVlc
Ct Ct (As shown, f a 10 kHz.)
T 4700 pf T 4700 pf
---1~
206
the comparator input is biased by de coupling through the tank.
There is essentially no shunt loading of the tank, which is an aid to
achieving a high Q. The feedback signal from the tank is coupled
by R3, which prevents possible input stage damage due to high-
amplitude signals (possible with some networks). With pin 7 open,
the output square wave will be slightly asymmetric, because the
tank de bias of 1.6 volts is lower than the 2-volt threshold at pin 7.
If this is undesirable, optional resistors R.1 and R;; can be added.
Equal values of resistance for R.1 and R.1 will yield a nominal sym-
metry of 50%. Or, for adjustable symmetry of the square wave,
a 2-kfl potentiometer can be used for R.1 and R,.. This option is
recommended for highest stability of the circuit. The comparator,
with the output clamped to the reference voltage, provides ex-
tremely hard limiting of the sine-wave input, which is an additional
aid to circuit stability.
Unlike the 555 version, this circuit places no constraints on the LC
ratio. Performance of this oscillator as a system will be essentially
limited by the components chosen for L 1 and C 1-C:.!. These compo-
nents should have a high Q and a low TC (or complementing TCs)
for best overall stability. The circuit works well up to about 100 kHz,
where the internal delays of the 322 begin to limit the stability. Out-
put from the circuit is +.5-volt CMOS or TTL compatible; and, for
best stability, the use of a buffer stage is recommended to prevent
load variations from being reflected back into the circuit.
6. 11.2 Crystal Oscillator/ Divider Circuits
Although it is possible to configure IC timers such as the 322
directly as crystal oscillators, their performance is not optimum and
is restricted to relatively low frequencies. A more efficient method of
precise frequency generation is to use a CMOS inverter stage as the
active portion of the oscillator, which allows excellent stability over
a wide frequency range-from 10 kHz to 10 MHz. The oscillator
output can be used either directly at the crystal frequency where
applicable, or divided down to lower frequencies with a divider
chain. There are a number of CMOS frequency dividers (counters)
designed specifically for this application, and many of them con-
veniently include an on-chip oscillator stage. This technique is il-
lustrated in block-diagram form in Fig. 6-44. This illustration shows
a general configuration for an oscillator/ divider combination. The
crystal oscillator circuit will consist of an amplifier stage, plus the
crystal and its associated tuning components. The oscillator output
(with suitable buffering) can be used directly at the frequency of
oscillation when desired. Examples of such use are microprocessor
clocks, tv chrominance oscillators, and other similar time bases re-
quiring high stability.
207
Since low-frequency crystals tend to be large, expensive, and not
necessarily optimum in stability, an attractive and common method
of generating a low-frequency clock source is a combination oscil-
lator I divider. Such a device can use an inexpensive high-frequency
crystal for the oscillator, and divide its signal down to the required
final frequency with a digital divider. This technique is attractive
both technically and economically, as it yields better overall stabil-
ity. In addition, the resultant circuitry can be minimal in both size
Crystal
Fig. 6-44. Block diagram of crystal oscillator/ divider combination, with table of
representative devices.
and cost. The table in Fig. 6-44 lists a number of devices suitable
for this purpose. Virtually any required division ratio can be imple-
mented from this table by choosing an appropriate device (or com-
bination of devices). Many of them incorporate an on-chip oscillator
stage (as noted), and some of them also feature logic-programmable
division ratios. A detailed discussion of these devices is beyond the
scope of the book, but a few of the more easily applied units are
shown in typical circuit arrangements.
208
A CMOS Oscillator
A basic crystal oscillator using a CM OS inverter as the gain stage
is shown in Fig. 6-45. This circuit uses a 3600 or a 4007 CMOS array
with one section used as the oscillator amplifier, the other two as
buffers. Section AlA is connected as a linear inverting amplifier,
biased by resistor R1. This resistor, which has a value in the range
of 15 to 20 Mn, establishes a class-A bias for the stage, forcing it to
operate in its linear region. The crystal, Yi, is connected in a pi
network with tuning capacitors C 2 and C 3 • These capacitors are
selected to yield an equivalent load capacitance, CL, as required by
the crystal in use. This capacitance is typically in the range of 12 to
30 pF. Capacitor C 8 is made variable, and trims the crystal to its
specified frequency by adjusting to this capacitance.
c1
0.01 µF +sv
r (see text)
8, 13 ><>-1_2_ _--o ¢A
' - - - - - - - - - - - u ¢8
*Y 1 = 32.768 kHz, CL= 10.7pF
Y*
1 (CTS Knights TX-4 or equiv.)
C2
t A1 = 3600 or 4007 CMOS array.
22 pF
This circuit will operate over a fairly broad range of supply volt-
ages and frequencies. Best operation in terms of stability is realized
when the supply voltage is constant; thus, a low-power regulator
may be desirable in some cases. Although the circuit will operate at
+3 volts (which would allow the use of a 322 as a regulator), this is
not recommended because of parameter variations of the 3600 and
4007 units at this voltage. More reliable operation may be obtained
at supply voltages of 5 to 6 volts. Within the oscillator stage itself,
drain resistors R2 and R3 also help stabilize the oscillator against
supply-voltage changes; thus, they are recommended for best per-
209
------------------------------,,
formance. They can be eliminated (shorted) if the supply is regu-
lated or if best stability is not a prime performance requirement.
Inverter sections Arn and A 1c serve as both buffers and waveform
shapers. Their output levels will, of course, be equal to the supply
voltage used. Output current drive is limited for low voltage ( == +5
volts) supplies to less than 1 mA. This is not sufficient to drive TTL
logic without buffering, so a 4049 (or a 4050) can be used for the
two buffer stages, if desired. The oscillator stage itself must use
either a 3600 or a 4007 unit, not just any CMOS inverter. This is
because some general-purpose CMOS inverters have built-in multi-
stage buffers, and as a consequence are not suitable for linear service
( 4000B series units are of this nature).
If it is desired to drive logic levels higher than 5 volts, a 322 can
be used as a level shifter (for frequencies below 100 kHz). The high
current drive capability of the 322 allows a high fan-out, and the
logic level can be referred to much higher voltages such as 10-volt or
15-volt CMOS, or even higher (up to 40 volts).
An interesting companion circuit that can be used directly with
the CMOS oscillator to form an oscillator/divider combination is
shown in Fig. 6-46. This circuit demonstrates the principle of binary
divider devices using the already familiar 2240 units. This two-stage
divider circuit uses only the counter stages of the two 2240s. The
first ( A1 ) is a divide-by-2 8 stage; the second ( A2 ) is a divide-by-27
v+ (see text)
)
> R, > R2
• 1o kn •10 kn
Clock Input -
~
(32,768 Hz)
16 16
15
v+ REG V+REG ~
14 14
TBO TBO
13 13
R/C R/C
A, A2
2240 2240
(72s) TR 11
-----<
,_!_ 64T (...!...27)
. TR JJ__
~
8
128T
GND
I
I
I
..
,> RJ
l kn
GND
>
>
9 ) 9
i l
I
0----------------~ ~Divided Output
+6 Y to (1 Hz)
CMOS Oscillator
(if required)
210
stage. The composite division ratio is then their product, 215 . This
circuit will yield a 1-Hz square-wave output from a 32,768-Hz clock
with crystal oscillator stability. This is not, of course, the limit to
available frequencies, as all 16 timing taps from 21 through 216 are
available at the A1-A 2 outputs. This factor is one major reason why
a 2240 (or pair of 2240s) might be desirable for this application. A
second reason is the availability of the 6-volt regulator output at pin
15, which can be used as a stabilized voltage source for the CMOS
oscillator. If the oscillator circuit of Fig. 6-45 is used in this manner
with a 2240, it is recommended that the 2240 supply voltage be in
the range of + 10 to + 15 volts for best oscillator stability.
The particular design example chosen is by no means the upper
limit of speed. The CMOS oscillator can operate up to 1 MHz or
more, and the 2240 counters can operate at rates well above 100
kHz. This combination can therefore be operated with many varied
oscillator frequencies and division ratios. It should also be pointed
out that the 22.50 and the 8250 counters can yield decade dividers,
which operate similarly.
Precision Oscillators
An example of a high-precision, low-frequency clock source using
the lntersil 7038A device is shown in Fig. 6-47. The 7038A function-
ally consists of an oscillator stage, plus a divider chain with a length
of 2 16, with a tap at 2 1:{. There are two outputs from the final ( 2 16 )
+3V
GND V+
3
OUT l (2 16)1-- - - - - - u 64 Hz
I
OUT 2 (2 16 )~-----.o
4
64 Hz
Ai Square
7038A Waveforms
OUT 3 (2 13 )~-----·o 512 Hz
5
Fig. 6-47. A high-precision crystal oscillator/ divider circuit using the lntersil 7038A.
211
divider stage in push-pull format (pins 3 and 4). The 2 13 stage (pin
5) is a single-ended source and must use an external pull-down
resistor ( Ri). The drive from output pins 3 and 4 is TTL compati-
ble (for one load or less), and pin 5 is 3-volt CMOS compatible. The
device can use crystals in the range of 0.5 to 10 MHz, and operates
at a +3-volt supply level. Current drain is quite low, allowing effi-
cient two-cell battery operation; or it may use a 3-volt regulator
(such as the 322).
As shown, a 4.194304-MHz crystal is used, which yields comple-
mentary 64-Hz drives and a 512-Hz drive. The crystal specified is
designed for a Cr, of 12 pF, which is provided by the C 2-C:~ trim
network. These capacitors should be low-TC units, preferably NPO
types. Overall performance of this circuit is quite high, featuring
less than 0.1 ppm/ °C stability in the 0-70°C range, and less than
0.1 ppm/V of supply sensitivity.
Another high-precision clock source is shown in Fig. 6-48. This
circuit uses the Intersil 7213, which has four outputs, as shown.
They are TTL compatible with the addition of pull-up resistors.
The composite output (output 2) consists of 16-Hz and 1024-Hz
waveforms, gated at a 2-Hz rate. The outputs as shown, with the
crystal specified, are directly usable in electronic clocks. This de-
+3V
R,
0.01 µF 10 kn
R"
4 10
lOkn
GND V+
12
OUT 1 (2 18 ) i-----t:-------t:-----v Output 1 (16-Hz Square Wave)
7213
OUT 3 (2
22
) ~2------+---+--~ Output 3 (1 pulse/second, 7.8 ms)
OUT4~1_4 ___________
Output 4 (1 pulse/minute,125ms)
(2 22 x 60) 0
5 6
osc osc
OUT IN *y 1 = 4.194304 MHz (CTS Knights MP-041 or equiv.)
cl=12pF
Fig. 6-48. A high-precision crystal oscillator/ divider circuit using the lntersil 7213.
212
vice also uses a 4.194304-MHz crystal and a 3-volt supply, and over-
all stability is comparable with the circuit of Fig. 6-47. Pull-up
resistors must be used on the active outputs, which can be referred
to voltages other than the 3-volt supply. By breaking the connec-
tion at point "X" and referring R 1-R.1 to +5 volts, for example, an
optimum TTL interface is obtained. The outputs should see voltages
less than +6 volts in all cases.
A third high-precision clock source is shown in Fig. 6-49. This
circuit uses the National Semiconductor 5369 device, which here
employs a standard 3.58-MHz color-tv crystal as the oscillator, and
divides the signal down to 60 Hz (pin 1). A buffered oscillator-
frequency output is also included (pin 7), which can be used either
for monitoring purposes or to drive a second divider chain. These
outputs are CMOS compatible and swing between the supply-
voltage levels.
The 5369 oscillator can be employed over a very wide frequency
range, from 10 kHz to 4.5 MHz. Above a few megahertz, however,
it must use supply voltages of 10 volts or more, as in the case shown
here. The supply-voltage range in general is +3 to + 15 volts, and a
local regulator can be used for optimum stability. The oscillator bias
resistor must be added externally across the crystal as shown.
+lOV
0.01 µF
2 8
GND v+ 7
Buffered
TUNER 1 - - - - - - - u Oscillator
A1 OUT Output
5369
DIVIDER 1 60-Hz
OUTt-----~ Output
OSC IN OSC OUT
5 6 Duty Cycle for 60-Hz Output
v+ ----=-rl___J
Q v ----
. ..
I I I
20Mn
,..
: 0.45 : 0.55 :
...,
*Y 1 = 3.579545 MHz
Y*
1
Ct= 18 pF
C3 (CTS Knights MP-036 or equiv.)
5-40 pF
Fig. 6·49. A high-precision crystal oscillator/ divider circuit using the National
Semiconductor 5369.
213
_______
............................................................................................._
The use of any of the devices described in this section can satisfy
virtually any specific oscillator frequency requirement, either di-
rectly or by the additional use of one of the divider units. In apply-
ing these units, however, the reader is cautioned to always ensure
input/ output compatibility when coupling between differing de-
vices, particularly when operating at differing supply voltages.
6. 11.3 "Never-Fail" 1-Hz Clock
A basic timing requirement is a 1-Hz (or 1-pps) clock source.
There are a variety of ways that such a source can be implemented,
but one popular method is to derive the timing reference from the
60-Hz power line. In Fig. 6-50, a circuit is shown that produces
output pulses at 1-second intervals with the basic accuracy referred
to the power line. Stage A 1 is a freewheeling 60-Hz oscillator syn-
chronized to the 60-Hz reference. The 60-Hz output of this stage is
divided by A2 , an 8260 operating as a divide-by-60 counter. The 60-
Hz input is fed to pin 14, with the time base disabled by connecting
pin 13 to ground through R3 • The carry-out terminal, pin 15, is used
as the divide-by-60 output and produces a TTL (or 5-volt CMOS)
compatible logic swing.
With backup power applied to the Di-D 2 OR gate, this circuit
will continue to run in the absence of a 60-Hz input; thus, the term
never fail. The circuit can operate over a +5-volt to + 15-volt sup-
ply range, but power drain is minimized at +5 volts, making the
operation more suitable for battery use at this level.
214
Di
1N4001
Primary DC O •• ,
D2
1N4001
Backup DC o ~I '
""
~·
'1'
UI R2
~ 10 kn
16
..i
< R, 8 v+ 5
1.2Mn CO j 1 < o Output (1 pulse/second)
61 R v+
TH TBOITT-1
13 J
c, 3 R/C I
-=~ 0.01µ.F
A OUTl
1 A2 -, n ------ =5 v
2ITR
% 555 8260 ~ ~---- OV
v 15 I I
,.... R1 I I
71
0
... DIS 11 ,__ 1 s ------
!'"' 22 kn GND TR~
I
6.3 V rms R
GND R3
60 Hz C2 9 l kn
0.01 µ.F
~
u;
~
•
52 s, +uv
)
Minutes Seconds
.R
lOkn
Common Common
5 9 5 9 A
402010 s 4 2 1 40 2010 8 4 2 1
- B
16 16 j
1 v+ 1 v+ co 15
1T - 1T
2 14 2 14
2T TBO- 2T TBO c
-----3 13 ~ 4T R/C 13
4T R/C
4 4
ST A3 ST A2
5 5
lOT lOT 8260
6 8260 6
20T 20T
7 11 7 11
40T TR 40T TR
R ~- R ~-
GND GND
9 9
• R, ;. R2
• 1 kn •• 1 kn
0
••'""
; - E
c~
--
;·
"'!!.
Ill
,,
~
ii'
:I
•.."
3· 117 VAC
4
~ Output
11, 0
,,.. kn 3
A K,
12V
GND
II 80mA
B
LED 1
MV5020
Timing Indicator
D~
R6
1N914
lOkn
CJ I A,
8260
R3
D2 6.3 V rms
1N914 60 Hz
GND 1 kn
Reference
9 53
~ Start Time
0
E
N
~
cycle, relay driver A4 holds relay Ki closed, which applies ac power
to the device being controlled. The timing indicator, LEDi, is also
lit during this period, indicating an active timing cycle.
As shown, the timer can control intervals of up to 1 hour ( 59 min-
utes, 59 seconds) in 1-second increments. Should longer time pe-
riods be desired, a 2250 or 82.50 bed counter can be driven from the
carry out terminal (pin 15) of Aa. It would be controlled by a third
thumbwheel switch pair, variable from 00 to 99 and wired to the
1, 2, 4, 8, 10, 20, 40, and 80 outputs of the 2250/8250, with the com-
mon line tied to R 4 • This option would allow intervals of up to 100
hours to be programmed in 1-second increments.
The supply voltage shown for the circuit is + 1.5 volts, which is a
level actually required for the 555 relay driver. This voltage need
not be regulated, however, and all circuit components are non-
critical. Relay Ki should have 10-ampere contacts, or heavier, suit-
able for ac loads. This circuit has a wide variety of potential uses;
e.g., as a darkroom timer, a kitchen timer, etc., with an inherent
accuracy that is quite high due to the use of the 60-Hz power-line
reference. An alternative method of operation would be to use the
time-base-oscillator section of stage A1 as the 60-Hz reference.
6. 13 TIME-MARK GENERATOR
An interesting use for a timer/ counter is shown in Fig. 6-52-a
time-mark generator. This is a circuit that produces precisely spaced
output pulses that can be used for calibrating the time bases of in-
struments such as oscilloscopes. This version is programmable in
either binary or bed terms, depending on the device used for A1 •
For calibration uses, such a circuit demands the highest time-base
precision. Thus, this circuit should be used with an external clock
source of high accuracy, such as one of the crystal oscillator sources
of Section 6.11.
In operation, a negative-going clock pulse triggers the 2240 (or
2250) control flip-flop to start the counters, via the first CMOS in-
verter. The second CMOS inverter reinverts the positive trigger to
a negative one, and clocks the time-base input at pin 14. The in-
ternal time base is disabled in this application by the 1-kfl resistor
( R:!) from pin 13 to ground.
With Ai counting, the output bus at R 1 is low and will stay low
for the time duration selected by the programming switches. \\Then
the programmed time interval is completed, the bus voltage rises,
which resets the internal control flip-flop via pin 10. This completes
one timing cycle, which is of length T The next input clock pulse
0 •
218
v+
16
v+
---0---0--11 lT Ai
---o---o-2-12T 2240 TBO t-l-'-4_ _ _ ____,
3 T (bin) R/C ,_1_3_ _.....,
Programming 4 4 2250
Jumpers or ST (bed)
5
Switches* 16T(lOT)
6
32T(20T)
l 64T(40T)
S l28T(80T)
GND
9
Clock Input
t CMOS Inverters
Timing Diagram
~~T/----~
l ~ n ~ 255 (binary))
( l ~ n ~ 99 (bed)
(As shown, T0 = 4.)
Fig. 6-52. Time-mark generator.
ming bus via the third CMOS inverter, in order to reestablish logic
levels.
The negative-going output pulses are of a single clock period of
width T in this circuit, and will occur at time intervals of:
T0 = (n + l)T,
where n is the number programmed into the timer/counter. This
number is from 1 to 255 for the 2240, and from 1 to 99 for the 2250.
Thus, T 0 is variable from 2T to 256T with a 2240, and from 2T to
IOOT with a 2250.
This circuit is also a programmable frequency divider, as it di-
vides the input frequency inherently. For an input frequency of f,
the output frequency will be f 0 , which is expressed as
219
Both devices shown in Fig. 6-52 can be used for either basic pur-
pose, with the 2240 having a greater range, but with the 2250 having
programming that is easier to use. Note that this circuit can be
made completely electronic in programming by the use of the tech-
nique discussed in Chapter 4, Section 4.10, Fig. 4-14.
Finally, two (or more) of these circuits can be cascaded for
greatly expanded timing capability. For a two-stage circuit, the mini-
mum output time will be ( n + 1) ~T, which for the 2240 is 65,536T,
and for the 2250 is 10,000T. Note that this implementation can also
be made electronically programmable, if desired.
6. 14 PHASE-LOCKED LOOPS
fo = ~'
where M is the division ratio of the circuit and is an integer. The
circuit accepts an input reference frequency in the form of a square
wave, and limits its amplitude to V+ volts p-p in the first CMOS in-
verter, A:~A· The output of A3 A is integrated by the RC network,
R9-C2, forming a 2-volt p-p triangle reference waveform across C2.
This triangle wave is sampled by cascaded sample/hold switches,
S1 and S2, which are portions of a 4016 CMOS analog switch. Switch
S1 is "on" during the high output state of A 1 , the local (£0 ) clock
oscillator. When S 1 is "on," Cm, the first sample/hold capacitor, is
effectively in parallel with C 2; thus, the reference triangle is im-
pressed across C 111 • When S1 switches "off," Cm retains the last in-
stantaneous voltage level of the reference waveform. Switch S2,
which is driven from the complemented output of A1 via inverter
A3B, is "on" when S1 is "off," and vice versa. During the S2 "on" pe-
riod, S2 transfers the sampled charge on Cm to CH2. When S1 again
turns "on," S2 is "off." Because of this "bucket-brigade" process of
the cascaded sample/hold components-sample , hold/transfer, and
sample again-Cn 2 is never allowed to see transient or large varia-
220
v+ (+1ov to +15V)
R2
+jl----,
4.99 kn c,... l-
1% 10 µF .
RJ
"Tl
ip· R, ~lOkn
'1' R"
U'I 61.9 kn
~
R,
)>
1% 4.7 kn
"Cl
f/
:r 3
OUTI Output
::: 2ITR A,
(1 kHz)
555 v, I 5
'f 71 f'
CD c, DIS *fo =ti.
""
a.. GND
0 0.0lµF Rs 1.44
0
~ 10 kn C, [R 2 + 2 (R 3 + R4 )]
.... CJ
; (As shown, f 0
.a 100 pF
= 1 kHz with f, = 2 kHz and M = 2.)
c
CD
~
'< * * 4016 CMOS switch sections.
Q. R, Ra
;:· lOOkn 33kn
a.: A3B t CMOS inverters.
,.= 1.3
..
n
f R9 a! ~
1
~ A R9t S**413 s2** 5 R6
fr Input 3A 6.8 kn 1 2 3 ~ 4 10 kn -
Reference~~
1
Frequency ..,.... l C2 _l CH 1 _l CH 2
(2 kHz) T 0.1 µF J 0.01 µF J 0.01 µF I
...,
~
tions in voltage. The voltage stored on Cm is the sampled error volt-
age of the loop, which is read out by FET amplifier A2. Amplifier A2
amplifies the voltage on CJI2 by a factor of 4/3, a ratio chosen so as
to apply the nominal + 10-volt bias to the control voltage input (pin
5) of timer Ai when the sampled voltage is +7.5 volts. This relation-
ship will occur when the reference ramp is sampled at its midpoint,
assuring a nominally correct bias condition for frequency lock.
The amplified error voltage applied to Ai via Rr; induces changes
in the center frequency of A1 in a direction to cause and maintain a
locked condition. An interesting feature of the circuit is that there
is no overriding limit to the ratio of L to fr, and, in practice, the
sample time period of f 0 can be many times a reference cycle of fr.
This is because the usable sampled error voltage is only the last in-
stantaneous voltage across Cm, and it is relatively immaterial how
many prior cycles of fr have occurred. In practice, this means f 0 can
be integer multiples of fr, ranging up to about ten.
In a given design, the 555 oscillator components are selected for
the desired f 0 , as in the standard astable case. In the circuit of Fig.
6-53, resistor R 9 is selected for the fr to be used according to the re-
lationship shown. This particular relationship is not overly critical
and will work with some latitude of values for R 9 , but the refer-
ence waveform should be 2 volts p-p or less for optimum dynamic
range. The circuit has an inherent supply-rejection capability, due
both to the 555 design and to the nature of the sample/hold system
used. In the example shown, f 0 = I kHz for an fr of 2 kHz when
M = 2. The circuit will also work with higher values of M, generat-
ing a I-kHz output of fr= 2 kHz, and so on.
An even more flexible form of phase-locked loop is the frequency
synthesizer/frequency multiplier shown in Fig. 6-54. In this cir-
cuit, the sample/hold components operate as previously described,
but a programmable timer/counter (A 1 , a 2240) is used as a volt-
age-controlled oscillator ( VCO). This circuit can generate fre-
quencies both above and below the reference frequency. In the cir-
cuit, the 2240 timer/counter generates a frequency, f 0 , which is
locked as a programmable multiple of the reference frequency, fr
(or a subharmonic of fr). The relationship is simply
n
fo=fr ( ~
+ 1)
where n is the number programmed into the timer/counter, and M
is the ratio between fr and its subharmonic used in the phase-lock
process. M is an integer, typically between 1 and 10.
The example shown in Fig. 6-54 illustrates some interesting capa-
bilities, since it generates a phase-locked output frequency that is
not a direct multiple of the reference frequency. For f 0 = 50 Hz,
222
..,, v+
c?' c, '? (+lOV to +15V)
~10 µ.F I
°"Vt~
R3
>
"CJ R, ,,~kn
':I"
~ 2.2 kn 16 R, R,*
cp
0 lT v+ REG 15 l.SMn
~
1% f/
Frequency
.a."' 4T , R/C 13
reo Output
0 Multiplier
~
0
Programming
a2T A 14 ST 2240
16T MOD 12 *f
•
j_ *
= f ' (11__±_!)
M
... _
(As shown , n -4.) ~ 32T c
.a 64T T o.~lµ.F 1
c S!--
128T R5 R, C,
-..
~ GND
10 kn
1'< 9 I C5
(As shown, f 0 = 50 Hz with
:I 1000 pF f, = 60 Hz, n = 4, and M = 6.)
;.
::
i:i' R6
f--i = * * 4016 CMOS switch sections.
4.7kn
.t t CMOS inverters.
~ R, Re
.
.a A3B
c lOOkn 47 kn f R9 C2 =:: ~
.. 'VV'v-- f'
:I
'<
"' _s
3 lOOpF
~ 6
"[
!'
~-
~·
....,
....,
w
n = 4, and M = 6, S 1 will be "on" for a period of l/f every n clock
0,
224
c, +uv
1 uf
::!!
'?
t
!" ------0 Trigger
5!
,, Reset
0
+
~
=
II
~· R,o
II
; lOkn
Staircase Staircase
'::I Amplitude Output
Ill (±10V)
iil
~ -1
...,
t? -15V
starting by virtue of the connection of the trigger input (pin 11) to
pin 1.5, but the separate use of the trigger and reset inputs can be
employed for start/ stop operation, if so desired.
The 7.530 is basicallv a 10-bit d/ a converter, but it can be used
for 8-bit operation by· grounding the two LSB inputs, pins 12 and
13, as is clone here. The remaining eight inputs are connected to
the corresponding outputs of the 2240, and 10-kfl pull-up resistors
are used to define the logic levels. This device requires only a single
positive power supply at pin 14, and it is also directly compatible
with the supply-voltage range of the 2240.
The 7.530 is a current output device; thus, A: 1, a 301A op amp, is
used as a current-to-voltage converter. This converts the zero to
±1-mA output current of the 7.530 to a zero to ±10-volt voltage
swing at the staircase output terminal. Although ±1.S-volt supplies
are indicated for the circuit, it will also perform with ±.5-volt sup-
plies with little reduction in performance (other than output ampli-
tude, of course).
6.16 A/ D CONVERTER
226
r--t~~~~-t~~~~~~~-.-~~~~-+~~~~~-----r~ +15V
R1 > . R, 1 R2
lOkn > · lOOknr-- 10 kn Timing Diagram
I4 14 10 Start
2 R v+ R Conversion l___ )
>tart
:onversion
C
1
-TH A
1 OUT 5
(
•
lOOOpF
12
-TH
Ai OUT-9-
Reset n I
- V':.: l~OpF
?" R14 = A, 7 R3
> 12 358
a. v.'" "~ 10••kn 6 (
lOkn "
10 kn
+ • - V 1+ 10 V
Q nominal) R R R R R R R R
"0
:I
(0 v to 1OV)
1
_ ___,6;7;8:....,.9:....,.10_,..1-'-1,_1::.. .2,_1:.:..3_ _ ___,,___ _ _~--4-----~
~
. 10 kn y V > • : 16 R12
.------.i......,,...--1~6 ' 11 · · · 1 v+ 15 22kn ·
c 7 J_ R, LSB 2=: lO
2
1T REG
14
· • ,> 10 kn
100 PF T 2 -6 9 3 2T TBO 13
~ 2 S 4T A2 R/Cr-----~---_.
4
A 1ouT, r' 7
ST 2240
1 5
A3 r• 5
16T MOD~
1 /2 358 7530 r3 6 6 32T
+ 2. r' 5
4
7
64T TRt-1-:1~:----~----T----t----4
Rt--~=---~'----~----'
10
4 MSB T' S 128T
__1 -•...!l._ GND
I OUT, 2 13 ) ) ~ J ) l '~ c
r'o'- MSB LSB 9 ::,:: s
"'-15V GND C 270pF C Sta us
6 .... _.._ •2 Ou put
~
3I 8-Bit Data Output 0.01 µF T T 0.01 µF
~
and removes the clamp from the counter input (pin 14), enabling
the counters to start counting. The counters will now count upward
toward full scale during the conversion cycle.
The advancing count from the counter drives the 7530 d/ a con-
verter, which produces an increasingly negative output. This nega-
tive output is compared against the input voltage, Vin, by compara-
tor A4 , one-half of a 358 op amp. The reference for this comparator
is zero volts, established by the ground on the ( +) input. When
the d/ a output voltage is equal to the input voltage, the ( - ) com-
parator input crosses zero, which forces the output positive. The
positive-going comparator output resets the control Rip-flop through
C 3 , which brings the status line low, indicating a complete conver-
sion. The 2240 output data are now valid, as the d/ a output is equal
to the input voltage. The negative-going edge of the status line can
be used to strobe the 8-bit output data into a storage register for
subsequent processing.
The system can be calibrated by either of two methods. If a sta-
ble variable voltage in the range of +9 to + 11 volts is available, this
can be used as Vrf'f and applied to the 7530 reference input (pin 15).
This could be a divided-down, + 15-volt power-supply voltage if it
is sufficiently stable. Alternatively, a fixed, stable, + 10-volt source
can be connected to Vrer, and R 15 trimmed ±10% to calibrate the
output for all "ls" with +9.960 volts applied to Vin·
Although the level of the binary output data as shown is 15 volts
due to pull-up resistors Rn-Rm being returned to + 15 volts, these
resistors (alone) can be returned to +5 volts for TTL compatibility,
if desired (with no other circuit alterations being necessary).
6. 17 SPEED ALARM
228
v+
Input Pulse
o----~
Train
3 11 3
Jl TR B TR
2 2
v+ 10R1 L v+ lO R.•
lOOkn lOkn
~---4--1V' A1 C t----+--'V\,rv--<1>---4--1V' A1 C i-1_2- - - u Alarm
R,* 322 12 322 Output
68 kn 5 R/C E 5 R/C E l High= f," > f,*
C.* Va GND l R3 GND (see text)
0.01 µF 7 6 lOMn 6
C1
Calibrate 0.1 µF
* f, = Reference Frequency
0.632
R, C,
=
(As shown, f, l kHz.)
fixed 2 volts, the comparator will change states when the filtered
voltage at pin 5 goes above or below 2 volts. The voltage compari-
son threshold becomes the voltage that corresponds to the desired
frequency.
The circuit is set up for a given frequency of detection by setting
a specific pulse width for monostable A 1 • Since the average voltage
being compared is 2 volts, which is 0.632 times the maximum volt-
age of 3.15 volts, a very simple criterion for the monostable pulse
width evolves. Simply stated, the monostable pulse width should be
0.632 times the input pulse period. In this circuit, for example, the
detection frequency is I kHz, which is a period of I ms; thus, Rt
and Ct are selected to yield a 632-µs pulse width. For best results,
the monostable pulse width should be trimmed for calibration, via
Ri, to just actuate the comparator at the desired frequency.
This is a very sensitive comparison system, and, in practice, it
can detect an "on" to "off" transition that is less than I% of the in-
put frequency. It can easily be set up for any frequency, up to about
100 kHz. For very low frequencies, R 3 or C 1 may have to be in-
creased in value.
Normally, this circuit would be used to indicate an over-speed
condition, or when the input frequency is greater than the reference
frequency. When this occurs, the output of the circuit will go high.
However, the opposite sense can also be detected by connecting the
logic input of A2 (pin 2) to the reference voltage. The output in
229
this case will be high when the input is below the reference fre-
quency, and low when it is above the reference frequency.
TR
8 v+ S R3
L
10 k!1
Alarm 2 V A, C t-6----u Alarm
Output: R2 r 3905 I Output:
2 V A1 C 1-6----0
R2 ' 3905 High = lOk!1 R/C E7 :High= Overvoltage
3
10 k!1 3 R/C E 7 Undervoltage R1 : GND :
5k!1 I 4 :
GND
I
R" _ _ _~
:i..-.J..,·.,,·~ :
_____ J
1 MO
230
(pin 8) to ground. Resistor R 1 is adjusted for an output of just be-
low 2 volts for a supply voltage just below the desired overvo]tage
limit. A further increase in supply voltage will then trip the com-
parator, causing an alarm. In this version of the circuit some hystere-
sis may be desirable, and this can be achieved by using the optional
resistor, R 1 .
Both of these circuits are capable of good performance due to the
combination of characteristics provided by the 390.5 (or 322). Al-
though both of them deliver a high-state output on an error condi-
tion, it may be desired to have a low-state (or current-sinking) out-
put to drive a relay or alarm device, such as a Sonalerff\ 4 , directly.
This can easily be accomplished by reversing the state of the logic
pin from that shown in each circuit.
0
A registered trademark of P. R. Mallory & Co., Inc.
231
v+
R, R1 R3
lOMn 1 Mn Q1 1ookn
2N3904
s 1 ~ <>---:i 4 14 10
Reset 2 R
._____.__--.iTH V+ 12 THR
A 1 OUT 1--i,--~-~
5
o, A1 9 Alarm
1N914 6
TR 556 5560UT Output:
A S TR B
DIS High=
c, GND Alarm
2 µF Condition
7
S5 ................ S"
~
Tamper
Switches i s2
Defeat
232
v+
I
Enable ·~ Ri
Input 0----4'----~ ;· 27011
I
_J~ '/J
R,
470 kn R
• a V+
©~o,
I
6 TH I
OUTi-3_ _ _ _, ------o To other circuits,
2 TR Al if used.
555
c, GND
0.1 µf
LED1
(MV5020 or equiv.)
233
~
+15 V C2
100,uF
Enable
+il--i
Input
.,,
son Off
' s, /
Chirp - Warble
~·
'I"
!:
,.. 4 14
[ lMn R,
~ [ 1 Mn R v+ R,
!. R, 1 I Rate 2ITH 2 10on
II 19 lW
lOkn 5 lOkn OUT
iii A, OUT A,
3 6ITR B TR
556 556
;· A B vclll o, snor
t- c, 1N4001 45n
!:. c,, c,2 K
0 GND lOµF PM Speaker
:- 0.01,uF
0.1,uF 7
R2
100 kn RJ
Warble 1 kn
Depth
oscillator. Since the tone oscillator is also being frequency-m odulated
simultaneously, this produces a "chirp" sound. For this mode only,
the warble oscillator is gated; gating of the tone oscillator then auto-
matically follows.
REFERENCES
I. Alvsten, B. "Linearize Your VIF Converter." Electronic Design, Novem-
ber 8, 1973.
2. ---."Calcu late With a V IF Converter." Electronic Design, June 7, 1974.
3. DeFreitas, R. "Delta Sigma Modulation-T he Low Cost Way to Send Data."
Electronic Design, January 18, 1974.
4. Grebene, A. B. "Monolithic Waveform Generation." IEEE Spectrum, April
1972.
5. Harrison, R. "Survey of Crystal Oscillators." Ham Radio, March 1976.
6. Jung, W. G. "The Signal Path: Function Generators." db, The Sound
Engineering Magazine, December 1975.
7. Kime, R. C. "The Charge Balancing AID Converter: An Alternative to
Dual Slope Integration." Electronics, May 24, 1973.
8. McDem1ott, J. "Focus on Crystals for Frequency Control." Electronic
Design, July 5, 1976.
9. Meyer, R. G.; Sansen, M. C.; Lui, S.; Peeters, S. "The Differential Pair as
a Triangle Sine Wave Converter." IEEE Journal of Solid State Circuits,
Vol. SC-11, No. 3, June 1976.
10. Pease, R. Teledyne Inc. Amplitude to Frequency Converter. U.S. Patent No.
3,746,968; Filed September 1972.
11. Pouliot, F. "Have You Considered V/F Converters?" Analog Dialogue,
Vol. 9, No. 3, 1975.
12. Robbins, M. S. Electronic Clocks and Watches. Howard W. Sams & Co.,
Inc., Indianapolis, 1975.
13. Teledyne Philbrick Applications Bulletin AN-I. Voltage-to-Fre quency Con-
verter. Teledyne Philbrick, Dedham, Mass.
14. Teledyne Philbrick Applications Bulletin AN-2. Need a 1 kHz Full-Scale
V-F? Teledyne Philbrick, Dedham, Mass.
15. Teledyne Philbrick Applications Bulletin AN-6. Magnitude-Plu s-Sign ADC
Using a V-F Converter. Teledyne Philbrick, Dedham, Mass.
16. Teledyne Philbrick Applications Bulletin AN-9. V-F's As Long-Term
Integrators. Teledyne Philbrick, Dedham, Mass.
17. Teledyne Philbrick Applications Bulletin AN-11. V-F's F-V's and Audio
Tape Recorders. Teledyne Philbrick, Dedham, Mass.
18. Teledyne Philbrick Applications Bulletin AN-20. Solve Your Measurement
Problems With V-F and F-V. Teledyne Philbrick, Dedham, Mass.
19. Teledyne Philbrick Applications Bulletin AN-22. How to Specify and Test
Voltage-to-Fre quency and Frequency-to- Voltage Converters. Teledyne
Philbrick, Dedham, Mass.
235
20. Young, R. "Get ±0.02% Full-Scale VCO Accuracy." Electronic Design,
March 15, 1973.
21. Zuch, E. L. "Voltage-to-Frequency Converters: Versatility Now at a Low
Cost." Electronics, May 15, 1975.
236
Ill
APPENDIXES
APPENDIX A
239
!i!!JDDtiC!i TIMERI 555
LINEAR INTEGRATED CIRCUIT~
DESCRIPTION PIN CONFIGURATIONS (Top View)
The NE/SE 555 monolithic timing circuit is a highly stable T PACKAGE
controller capable of producing accurate time delays, or
oscillation. Additional terminals are provided for triggering
0
or resetting if desired. In the time delay mode of operation,
the time is prec1sely controlled by one external resistor and r 5 Control Voltage
capacitor. For a stable operation as an oscillator, the free Trigger
0
6 Threshold
Output Discharge
running frequency and the duty cycle are both accurately 6
0 Vee
controlled with two external resistors and one capacitor. 5
V PACKAGE
FEATURES
•
•
•
TIMING FROM MICROSECONDS THROUGH HOURS
OPERATES IN BOTH ASTABLE AND MONOSTABLE
MODES
ADJUSTABLE DUTY CYCLE
GroundoVcc
fogger Doscha<ge
Threshold
• HIGH CURRENT OUTPUT CAN SOURCE OR SINK Output
200mA
Control Voltage
• OUTPUT CAN DRIVE TTL
• TEMPERATURE STABILITY OF 0.005% PER °C
ORDER PART NOS. SE555V/NE555V
• NORMALLY ON AND NORMALLY OFF OUTPUT
BLOCK DIAGRAM
240
SIGNETICS TIMER • 555
ELECTRICAL CHARACTERISTICS TA= 25°e, Vee= +5V to +15 unless otherwise specified
NOTES
1. Supply Current when output high typically 1mA Ins.
241
SIGNETICS TIMER • 555
TYPICAL CHARACTERISTICS
1
Slf\IK mA
242
SIGNETICS TIMER • 555
lI
I -
-- ---- r -
I
I
-
\
-..___
i r---
- -- -~
,______
i
-
--~t-+
I I
PROPAGATION DELA'V
vs VOLTAGE LEVEL
OF TRIGGER PULSE
243
..................................................................................... ...........................
FEATURES
• TIMING FROM MICROSECONDS TO HOURS
• REPLACES TWO 555 TIMERS
• OPERATES IN BOTH ASTABLE, MONOSTABLE.
TIME DELAY MODES
• HIGH OUTPUT CURRENT
• ADJUSTABLE DUTY CYCLE
• TTL COMPATIBLE
• TEMPERATURE STABILITY OF 0.005% PER °C
APPLICATIONS
PRECISION TIMING
SEQUENTIAL TIMING
PULSE SHAPING
PULSE GENERATOR
ORDER NO. SE556A, NE556A
MISSING PULSE DETECTOR
TONE BURST GENERATOR
PULSE WIDTH MODULATION ABSOLUTE MAXIMUM RATINGS
TIME DELAY GENERATOR Supply Voltage +18V
FREQUENCY DIVISION Power Dissipation 600mW
INDUSTRIAL CONTROLS Operating Temperature Range NE556 0°C to +70°C
PULSE POSITION MODULATION SE556 -55°C to +125°C
APPLIANCE TIMING SE556C -55°C to +125°C
TRAFFIC LIGHT CONTROL Storage Temperature Range -65°e to +150°C
TOUCH TONE ENCODER Lead Temperature (Soldering, 60 sec) +300°C
BLOCK DIAGRAM
,----
l
I
244
SIGNETICS DUAL TIMER . 556
ELECTRICAL CHARACTERISTICS TA= 25°C, Vee= +5V to+ 15 unless otherwise specified
SE 556 NE 556
PARAMETER TEST CONDITIONS UNITS
MIN TYP MAX MIN TYP MAX
Supply Voltage 4.5 18 4.5 16 v
Supply Current Vee= 5V RL =~ 5 6 mA
Vee= 15V RL =~ 10 11 10 14 mA
Low State, Note 1
Timing Error !Monostable) RA= 2Kl1to100K!"l.
Initial Accuracy C = 0 1µF Note 2 0.5 1.5 0.75 %
Drift with Temperature 30 100 50 ppm/QC
Drift with Supply
0.05 0.2 0.1 %/Volt
Voltage
Timing Error IAstable) RA, RB= 2Kn to 100Kn
Initial Accuracy C = 0.1µF Note 2 1.5 I 2.25 %
Drift with Temperature 90 150 ppm/QC
Drift with Supply I
0.15 0.3 %/Volt
Voltage
Threshold Voltage 2/3 2/3 x Vee
Threshold Current Note 3 30 100 30 100 nA
Trigger Voltage Vee= 15v 4.8 5.2 5 v
Vee= 5V 1.45 1.67 1.9 1.67 v
Trigger Current 0.5 0.5 µA
Reset Voltage 04 0.7 1.0 0.4 0.7 1.0 v
Reset Current 0.1 0.1 mA
Control Voltage Level Vee= 15v 9.6 10 10.4 9.0 10 11 v
Vee= 5V 2.9 3.33 3.8 2.6 3.33 4 v
Output Voltage !low) Vee= 15v
ISINK = 10mA 0.1 0.15 0.1 .25 v
ISINK = 50mA 0.4 0.5 0.4 75 v
ISINK = 100mA 2.0 2.25 2.0 2.75 v
I ISINK = 200mA 2.5 2.5
V CC= 5V
ISINK = BmA 0.1 0.25 v
ISINK = 5mA 25 35
Output Voltage !high)
lsouRCE = 200mA 12.5 12.5
Vee= 15v
1souRCE lOOmA
Vee= 15v 130 13.3 !1 13.3 v
Vcc=5v 3.0 3.3 2.75 3.3 v
Rise Time of Output 100 100
Fall Time of Output 100 100
Discharge Leakage Current 20 100 20 100 nA
Matching Characteristics
!Note 4)
Initial Timing Accuracy 0 05 0.1 0.1 0.2
Timing Drift with
'10 +lQ ppm 1"c
Temperature
Drift with Supply
0 1 0.2 0.5 S1,/Volt
Voltage
245
SIGNETICS DUAL TIMER • 556
TYPICAL CHARACTERISTICS
11 cc·!>v
....... ~-+-++--7
0 / I .--i.--
~?~~+--+-+-+----;
->--
I F
>:3 08
;, f---t--t--+-t--+---+-1---4-+---i
1
SOUFIL(
246
SIGNETICS DUAL TIMER • 556
" ~
i ,(,I f
---- --~~ -----+-+-+-+--A___,__.
f---- ++=H==---=+==+=+~~=t
PROPAGATION DELAY
vs VOLTAGE LEVEL
OF TRIGGER PULSE
247
Industrial/ Automotive/Functional Blocks
typical applications
Basic Timer-Collector Output •nd Timing Chart One Hour Timer with Reset ind Manu1I Cycle End
248
absolute maximum ratings
Power 01ss1pa11on 500mW Operating Temperature Range
v+ Voltage 40V LM122 55'c<; TA<;+125'c
Collector Output Voltage 40V LM222 25" C <; TA <; +85' C
VREF Current 5mA LM322 o'·c <;TA<; +70°C
Trigger Voltage t4QV LM2905 -40.'C <;TA<; +85"C
V ADJ Voltage (forced) 5V LM3905 0°C <TA<; +70"C
Logic Reverse Voltage 55V
Output Short C1rcu1t Duration (Note 11
Lead Temperature (Soldering, 10 sec) 300 c
Timing Ratio TA 25"c. 4.5V < v• <; 40V 0 626 0.632 0 636 0 620 0.632 0.644 0 620 0 632 0644
Boost Tied 10 V+ (Note 3! 0 620 0.632 0644 0620 0.632 0644
Comparator Input Current TA = 25 C. 4 5V ,. V' < 40V 0 3 10 03 1.5 0 5 15
Boost Tied to V+ 30 100 30 100
Note 1: Contmuous output shorts are not allowed. Short circuit duration at ambient temperatures up to 40°C may be calculated from t = 120/
Vee seconds, where Vee is the collector to emitter voltage across the output transistor during the short
Note 2: These specifications apply for TAMIN-::;_ TA:; TAMAX unless otherwise noted
Note 3: Output pulse Width can be calculated from the follovv1ng equation: t == !Rt)(Ctl [1 - 2{0 632 - r) - Vc/VREF) where r 1s timing ratio
and Ve is capacitor saturation voltage. This reduces tot=- (AtHC 1 ) for all but the most critical appltcatrons.
Note 4: Sign reversal may occur at high temperatures I> l00°Cl where comparator input currerot ts predominately leakage. See typical curves
t
Comparator Bias Current
Comparator Bias Curren1 Comparator Bias Current I LM122/LM222/LM322)
56
• --+t+ -! t-1+,
I lr,=-•n
t + 1+- '···••cl I
: ~±J1+-rt_':_ +
48 I I
·····-
16 -TA=10Cl'C:~'r·~±tr
TA=12SC TRIGGER"Hf"
: rr I I T~T.·125'Cr-
\ I I I \I I I I I
·• l l
-TT~t
!
t- t-r~
! 11 i
COMPARATOR lfllitUT VOLTAGE (VI COMPARATOR INPUT VOLTAGE IV) COMPARATOR INPUT VOLTAGE !VJ
~~~~~~~~~~~~~~-~~~~~~
249
typical performance characteristics (con 't)
~
.
TRIGGERVOLTAGE{V) TEMPERATURE ( C)
80
v; 40
60
40
20
20
-60
-80
~~
5~
.-'---+--+--+--~--
2 +---+"-
>
~~
5~
4
2 ~4~...............""'*~""-~
250
connection d"iagrams
'""""OD
1 7
ual-ln-LonePack lOGIC
v.. u l fMITTER
RIC J 15 COlUCTOR
41
GNO
.,.~·.:·:o;
Packagelat
,, EMITTER
'"" : COll!CTOA
RfC BOOST
1
GJID v•
v.. o.
Q TOP VIEW
rder Number LM122F
See Package 3
Courtes Y Nat1onal
. Se m1conductor
. Corp.
251
functional diagram v•
-----------1
r- NON INVERTING LATCHING BUFFER
(OUTPUT LATCHES HIGH WHEN
' ORIVENTOTHEHIGHSTATEIF
~··
TRIGGER IS LOW-OUTPUT UNLATCHES
lfTRIGGEAISPULSEDHt)
/
I v•o•_,~_...;;..;.....__~~~
~- "01'--------1
I
-L-
-.-" I LOGIC
CIRCUIT
I
I
L _ 'o""-'-----
1 I
I I
I I
I I
- - - ________ _ .J
L------ --
timing diagram
SIGNAL ON RIC PIN
•v
V2,LOGICP!NLOW
v+ is the positive supply terminal of the LM122. The trigger terminal is used to start a timing
When using a single supply, this terminal may be cycle (see functional diagram). Initially, 01 is
driven by any voltage between 4.5V and 40V. saturated, Ct is discharged and the latching buffer
The effect of supply variations on timing period output (V 1 I is latched high. A trigger pulse un·
is less than 0.005%/V, so supplies with high ripple latches the buffer, V 1 goes low and turns 01
content may be used without causing pulse width off. The timing capacitor Ct connected from R/C to
changes. Supply bypassing on v+ \s not generally GND will begin to charge. When the voltage at the
needed but may be necessary when driving highly R/C terminal reaches the 2.0V threshold of the
comparator, the comparator toggles, latching the
reactive loads. Ou iescent current drawn from the
y+ terminal is typically 2.5 mA, indepeodent of buffer output (Vl I in the high state. This turns
the supply voltage. Of course, additional current on 01, discharges the capacitor Ct and the cycle is
will be drawn if the reference is externally loaded. ready to begin again.
The V REF pin is the output of a 3. 15V series If the trigger is held high as the timing period ends,
regulator referenced to the ground pin. Up to the comparator will toggle and Vl will go high
5.0 mA can be drawn from this pin for driving exactly as before. However, Vl will not be latched
external networks. In most applications the timing and the capacitor will not discharge until the trig·
resistor is tied to VREf, but it need not be in ger again goes low. When the trigger goes low, V 1
situations where a more linear charging current is remains high but is now latched.
252
pin function description (con't)
Trigger threshold is typically 1.6V at 25cC and has includes capacitively coupled signals because even
a temperature dependence of -5.0 mV l°C. Cur small values of capacitors contain enough energy
rent drawn from the trigger source is typically to degrade the input stage if the capacitor is driven
20µA at threshold, rising to 600µA at 30V, then with a large, fast slewing signal. The V ADJ pin may
leveling off due to F ET action of the series resistor, be used to abort the timing cycle. Grounding this
R5. For negative input trigger voltages, the only pin during the timing period causes the timer to
current drawn is leakage in the nA region. The react just as if the capacitor voltage had reached its
trigger can be driven from supplies as high as normal RC trigger point; the capacitor discharges
t40V, even when device supply voltage IS only and the output charges state. An exception to this
5V occurs if the trigger pin is held high when the
V ADJ pin is grounded. In this case, the output
The R/C pin is tied to the non-inverting side of changes state, but the capacitor does not discharge.
the comparator and to the collector of 01. Timing
ends when the voltage on this pm reaches 2.0V If the trigger drops while V ADJ is being held low,
11 RC time constant referenced to the 3.15V discharge will occur immediately and the cycle
regulator). 01 turns on only if the trigger voltage will be over. If the trigger is still high when V ADJ
has dropped below threshold. In comparator or is released, the output may or may not change
regulator applications of the timer, the trigger state, depending the voltage across the timing
1s held permanently high and the R/C pm acts capacitor. For voltages below 2.0V across the
just like the input to an ordinary comparator. timing capacitor, the output will change state
The maximum voltages which can be applied to immediately, then once more as the voltage rises
this pin are +5.5V and 0. 7V. Current from the past 2.0V. For voltages above 2.0V, no change
R/C pin is typically 300 pA when the voltage is will occur in the output. This pin is not available
negative with respect to the V ADJ terminal. For on the LM2905/LM3905
higher voltages, the current drops to leakage levels
In the boosted mode, input current is typically In noisy environments or 1n comparator-type
30 nA. Gain of the comparator is very high, applications, a bypass capacitor on the V ADJ
200,000 or more, depending on the state of the terminal may be needed to eliminate spurious
logic reverse pin and the connection of the out· outputs because it IS high impedance point. The
put transistor. size of the cap will depend on the frequency and
energy content of the noise. A 0. lµF will generally
The ground pin of the LM122 need not necessarily suffice for spike suppression, but several µF may
be tied to system ground. It can be connected to be used 1f the timer is subjected to high level 60 Hz
any positive or negative voltage as long as the EM!
supply is negative with respect to the v+ terminal
Level shifting may be necessary for the input The emitter and the collector outputs of the
trigger if the trigger voltage is referred to system timer can be treated just as if they were an
ground. This can be done by capac1t1ve coupl 1ng ordinary transistor with 40V minimum collector-
or by actual resistive or active level shifting. One emitter breakdown voltage. Normally, the emitter
point must be kept in mind; the emitter output is tied to the ground pin and the signal is taken
must not be held above the ground terminal with from the collector, or the collector is tied to v+
a low source impedance. This could occur, for and the signal is taken from the emitter. Variations
instance, if the emitter were grounded when the on these basic connections are possible. The
ground pin of the LM122 was tied to a negative collector can be tied to any positive voltage up to
supply. 40V when the signal IS taken from the emitter.
However, the emitter will not be pulled higher
than the supply voltage on the v+ pin. Connecting
The terminal labeled V ADJ is tied to one side of
the collector to a voltage less than the v+ voltage
the comparator and to a voltage divider between
is allowed The emitter should not be connected
VREF and ground. The divider voltage is set at
to a low impedance load other than that to which
63.2% of VREF with respect to ground-exactly
the ground pin is tied. The transistor has built-in
one RC time constant. The impedance of the
current limiting with a typical knee current of
divider is increased to about 30k with a series
120 mA. Temporary short circuits are allowed;
resistor to present a minimum load on external
even with collector-emitter voltages up to 40V
signals tied to V ADJ· This resistor is a pinched
The power x time product, however. must not
type with a typical variation in nominal value of
exceed 15 watt-seconds for power levels above the
-50%, +100% and a TC of 0.7%/°C. For this
maximum rating of the package. A short to 30V,
reason, external signals !typically a pot between
for instance, can not be held for more than 4
V REF and ground I connected to V ADJ should
seconds. These levels are based on 40°C maximum
have a source resistance as low as possible. For
initial chip temperature. When 'driving inductive
small changes in V ADJ, up to several kl"l is all
loads, always use a clamp diode to protect the
right, but for large variations, 250!"2 or less should
transistor from inductive kick-back.
be maintained. This can l;>e accomplished with a 1 k
pot, since the maximum impedance from the A boost pin is provided on the LM 122 to
wiper is 250!"2. If a voltage is forced on V ADJ from increase the speed of the internal comparator.
a hard source, voltage should be limited to --0.5, The comparator is normally operated at low
and +5.0V, or current limited to ±1.0 mA. This current levels for lowest possible input current.
253
pin function description (con't)
For timing periods less than 1 ms, where low input Figure 2 is again a basic timer, but with the output
current is not needed, comparator operating taken from the emitter of the output transistor.
current can be increased several orders of magni· As wrth the collector output, either a high or
tude. Shorting the boost terminal to v+ increases low condition may be obtained during the timing
the emitter current of the vertical PNP <:!rivers period.
in the differential stage from 25 nA to 5µA. This
pin is not available on the LM2905/LM3905.
254
XR-22 40
Programmable Timer/ Count er
PRINCIPLE OF OPERATION
The XR-2240 Programmable Timer/Counter is a monolithic controller capable of producing ultra-long
time delays without sacri-
ficing accuracy for time delays from micro-seconds up to five days. Two timing circuits can be
cascaded to generate time delays
up to three years. The circuit is comprised of an internal time-base oscillator, a programmable
8-bit counter and a control flip-
flop. The time delay is set by an external R-C network and can be programmed to any value from
I RC to 255 RC.
In as table operation, the circuit can generate 256 separate frequencies or pulse-patterns from a
single RC setting and can be
synchronized with external clock signals. Both the control inputs, pins 10-11, and the outputs,
pins 1-8, are compatible with
TTL and DTL logic levels.
The timing cycle for the XR-2240 IS initiated by applying a positive-going trigger pulse to pin 11.
The trigger input actuates the
time-base oscillator, enables the counter section, and sets all the counter outputs to "low" state.
The time-base oscillator gener-
ates timmg pulses with its period, T, equal to I RC. These clock pulses are counted by the binary
counter section. The timing
cycle is completed when a positive-going reset pulse is applied to pin I 0.
In most timing applications, one or more of the counter outputs are connected back to the reset
terminal. In this manner, the
circuit will start timing when a trigger is applied and will automatically reset itself to complete
the timing cycle when a program-
med count is completed. If none of the counter outputs are connected back to the reset terminal,
the circuit would operate in its
astable or free-running mode, subsequent to a trigger input.
Figure 1 Figure 2
255
ELECTRICAL CHARACTERISTICS
Test Conditions: See Figure 3, v+ = SV, TA= 2S°C, R = 10 krl, C = 0.1 µF, unless otherwise noted_
XR-2240 XR-2240C
PARAMETERS UNIT CONDITIONS
MIN TYP MAX MIN TYP MAX
GENERAL CHARACTERISTICS
Supply Voltage IS IS v Forv+<4.5V,ShortPin 15
to Pin 16
Supply Current 3.S 6 4 7 mA v+ = 5V, VTR =O, VRs = sv
Total Circuit 12 16 13 18 mA v+ = ISV, VTR = 0, VRs = sv
Counter Only I LS mA See Figure 4
Regulator Output. VR 4.1 4.4 3_9 44 v Measured at Pin I 5, v+ =S V
6.0 6.3 6.6 S.8 6.3 6.8 v v+ = I SV, See Figure S
TIME BASE SECTION See Figure 3
•Timing error Solely introduced by XR-2240, measured aso/i of ideal time-base period ofT = l.00 RC
-*Propagation delay from application of trigger (or reset) input to corresponding state change in counter output at pin I.
Figure 3. Generalized Test Circuit Figure 4. Test Circuit for Low-Power Figure 5. Test Cirt--uit for Counter Section
Operation (Time-Base Powered Down)
256
RESET AND TRIGGER IN~UTS (PINS IO AND 11)
·~-
,. - ' ~
The circuit is reset or triggered with positive-going control
pulses applied to pins 10 and 11. The threshold level for these
controls is approximately two diode drops("" l.4V) above
•no- - -
', :'-,(OFTIMINI>: ground.
Minimum pulse widths for reset and trigger inputs, minimum
trigger delay time and minimum re-trigger delay time are shown
in Figure I 0. Once triggered, the circuit is immune to additional
·;~, .:. "' ' '" ,~ ·- trigger inputs until the end of the timing cycle.
~------
Pins JO and 11
~-·""'
rides reset.
TIMING TERMINAL (PIN 13)
~- The time-base period T is determined by the external R-C net-
work connected to this pin. When the time-base is triggered,
'l\FV•
TIME-BASE OUTPUT (PIN 14)
10K Rl Time-Base output is an open-collector type stage, as shown in
Figure 2 and requires a 20 Kfl pull-up resistor to Pin I 5 for
proper operation of the circuit. At reset state, the time-base
--j Tc~
.~
J1T
! ,. ,~ , .~
~ - JllRIGGER
output is at "high" state. Subsequent to triggering, it pro-
duces a negative-going pulse train with a period T = RC, as
shown in the diagram of Figure 8.
Time-base output is internally connected to the binary counter
LJ '" • " il""" section and also serves as the input for the external clock signal
OUTP~ - when the circuit is operated with an external time-base.
1 " "' - The counter input triggers on the negative-going edge of the
":" lT T0 2SSTWHERE l•RC
timing or clock pulses applied to pin 14. The trigger threshold
for the counter section is "" +I. 5 volts. The counter section
FiJi?:ure 9. Circuit Connection for Timing Applications (Switch S1 can be disabled by clamping the voltage level at pin 14 to
Open for A stable Operations, Closed for Monostable Operations) ground.
257
Note: Under certain operating conditions such as high supply
voltages ( v+ > 7 V) and small values of timing capacitor
(C < 0. I µF) the pulse· width of the tlme·base output at pin I 4
may be too narrow to trigger the counter sectwn. Thts can be
corrected by connectmg a }00 pF capacitor from pin 14 to
ground.
REGULATOR OUTPUT (PIN 15)
This terminal can serve as a y+ supply to additional XR-2240
circuits when several timer circuits are cascaded (See Figure
11) to minimize power dissipation. For nrcuit operat10n with
external clock, pin l 5 can be used as the v+ terminal to power-
down the internal time-base and reduce power dissipation.
The output current shall not exceed 10 mA. (b) Free-running or Contmuous
(a) Operat10n with l-.xternal
When the internal t1me'.hase 1s used with y+ <; 4.SV, pin I 5 Trigger and Reset Control<; Operation
should be shorted to pin 16.
l·tgure 12. (1rru1t (onncrt1ons for AstableOpcrat1on
258
XR-2250
BCD Programmable Timer/Counter
ADVANCE INFORMATION
The XR-2250 BCD Programmable Timer/Counter is a monolithic controller capable of producing ultra-long time delays without
sacrificing accuracy. In most applications, it provides a direct replacement for mechanical or electromechanical timing devices
and generates programmable time delays from micro-seconds up to 24 hours. Two timing circuits can be cascaded to generate
time delays up to six months.
As shown in Fig. l, the circuit is comprised of an internal time-base oscillator, a BCD programmable 8-bit counter and a control
flip-flop. The time delay is set by an external R-C network and can be programmed to any value form l RC to 99RC.
259
ELECTRICAL CHARACTERISTICS PrdHrnnary
Test Conditions: v+= SY. TA= +25''c. R = 10 Kl2.C = 0 I µF unks" nthnw1\t' notnf
XR-2250 XR-2250C
UNITS CONDITIONS
PARAMETERS
MIN. TYP MAX MIN TYP MAX
Recommended R.rnge
Tmung Component.;;
10 0.001 10 ~tl2
Timing Resistor R 0 001
1000 0.01 1000 µF
Timmg CapJcitor C 0.007
*Timing error sokly introduced by XR-2.250 meJsured a'>,-; ol ideJ! timt•-bast• pn1od of T:::: l .OORC
PRINCIPLE OF OPERATION
The timing cycle for the XR-2250 is 1n1t1ated hy applying a t1mt' 1.lt>lay ot 46RC. Pins 2. J and 7 are shorted together to
positive-going tngger pulse to Pin 11. The trigger input Jctuatt's ~IVt' 2 + 4 + 40 ~ 46RC. In this manner, XR-2250 can pro-
the t1me-hase oscillator, enahlcs the t·ounter section and .;;;t'ts vidt' 2 dt'cades of BCD programmed timing. As shown in
all the counter outputs to "low" •d;Jte. The tinlt'-hast• o.;;;nlli..t- Fig. J. two XR-2250 cncuits can he cascaded to provide time
tor generates timing rulses with its rt.:-r10J T. equal to l RC delays from l RC to lJ944RC. In cascaded operation, carry-out
These cl(Kk rulses art' countt'J hy the BCD programmahk terminal (pm 12) of Umt I is connected to counter input
counter section. Tht' timrng l..'yL·\e 1s completed when a pre-sd (pin 14)ofUnit 2
count is reached. or when a positive reset 'iignal ts applied to
Note· To eliminJte the effect of switL·hing transients at the
Pin 10
comnH.rn output hus. it is recommended that a filter cJpacitor,
Programming 1s Jone hy .;;eleL'llvely shorting any one or .i CL should he connel'ted to the output, as shown in Figures~
comhinat1on of the countt'T outputs to the L·ommon pull-up Jnd 3. This filter cJpJc1tJnce CL should be chosen such that
resii;;tor, RL, as shown in Fig. 2. Thu\, for t'xample. to get a the output time constant. RLCL is:;;. 2 µsec, where RL is the
output pull-up resistor.
LI
_, - 10 "RC
Figure 2 Cirrn1t Connection for Monost.ibk Opl'r.itlon hµurt' J. CiTL'Ult Cnnn1..•ction for Ca.'icaded Operation
260
11
8240
PROGRAMMABLE TIMERS/COUNTERS 8250
8260
261
ABSOLUTE MAXIMUM RATINGS
Supply Voltage 18V Operating Temperature
Power Dissipation 8240M, 8250M, 8260M -55°C to +125°C
Ceramic Package 750mW 8240C, 8250C, 8260C 0°C to +75°C
Derate above +25'C 6mW/°C Storage Temperature - 65°C to +150°C
Plastic Package 625 mW
De rate above + 25" C 5.0mW/°C
-=-~~~-;A;~;~~~~~-fi.~?~~L~~J_~~~J-~~~k~~~I~,~~;r~ __c_o_N_~_1T_1_0N_s_ _ _ _ _ _ __
GENERAL CHARACTERISTICS
·t
Total Circuit (Trigger± mA
All outputs ON. (Worst Case)
See Figure 3, 8240 only
mA
Counter Only
--~!;;\or Output, V~ 41
1
-44~- 3 9- -4
15
4 - -v-- Measured at Pin 15, v+ = 5V
18240only) 60 63 66 58 63 68 V v+=15V,SeeFigure4
--TIMEBASE SECTION --~-- See Figure 2
~-T~i.;-g-A~curacy - - - - - · n 5 2.0 o5 - -5·-- --~1,1;~ = o, vrn = 5v, Note 1
Temperatu.re Drift 15.o 300 200 ppm/C v+ = 5V Over Operating Temperature
80 80 ppmfc v+ = 15V
Supply Dnft 0 05 0.2 0.08 0.3 %/V v+ ;;;,8 Volts, See Figure 11
Input
0.8
15--T 1.5 MHz
See Figure 4, v+
VRS = 0, VTR = 5V
Max Input to Pin 14
= 5V
l
Impedance 15 15 k!.1 Measured at Pin 14
Threshold 1.0 14 10 1.4 v
Output Measured at Pins 1 thru 8
Rt>e Time 180 RL = 3k, CL= 10pf
Fall Time 180 180
VouT Low
Leakage Current 000~ o: 0.2
0.01
0.4
15
---~-~--~--~-----~-------
v
µA
lslNK = 3.2 mA
VoH = 15V
NOTE 1: Timing error solely introduced by 8240, measured as % ot ideal time-base period of T = 1.00 RC.
NOTE 2: Propagation delCjy from application of trigger (or reset) input to corresponding state change in counter output at Pin 1
262
ELECTRICAL CHARACTERISTICS 8250
Test Conditions: See Figure 2, V 1 - 5V, TA = 25 C, R 10 kS~, C = 0 1 µF, unless otherw1St' noted.
CONDITIONS
__ 1___
Supply Voltage 4 5 18 4.5 I 18 -T v
Supply Current I
Total C11cuit !Reset) 3.5 6 4 I
7 mA v+ =5V, VTR -- 0, VRs = 5V
12 16 13 18 mA v+ 15V, VTR = 0, VRs = 5V
J_
=
Total Circtttt (T11gger) 24 24 v+ - 15V, VTR = 5V, VRs = 0
All outputs ON.(Worst Case)
------·--·-----------
TIME BASE SECTION See Figure 2
- - - - - - - - - - --
2.0 0.5 VRs - 0, VTR = 5V, Note 1
Timing Accuracy
Temperature Drift 1°56 300 200 1
! ppmtc V' = 5V Over Operating Temp.
1005
i130
80 80 ppmfc v+ = 15V
Supply Drift 0.2 I 008 0.3 %/V v+ >8 Volts, See Figure 11
Max. Frequency 100 130 kHz R 1 kH. C = 0 007 µF
1rne ase utput
24 2.8
-~-; v
VTB HIGH
VTB LOW 0.2 04 0.2 04 v
Modulation Voltage
Level 3.00 2.80 3 50 4.20 v
10.5 v
-------------
Recommended Range
---+-
of Timing Components : I
T1m1ng Resistor, R ;0.001 10 lo.001 I 10 MH
_ _____:r_i_'l111'9 Capacitor~E_J~_.0_07_~--~l_O_OO_~_
oo 2-l__ __l!_cl_o~ µF
TRIGGER/RESET CONTROLS
-~ o-T--,-~--1 ~ 0 - r--:--iM~as~;;;;:i-;;-;-~----
Threshold 14
Current 8 I 10 i µA VRs- o, VTR =2V
;3 ::::L~red
Impedance 25 2
Response Time 1
Reset
Reset Threshold
Reset Current
14
8
2.0 I 1:
10
1
I
20 II µA
I
VTR
at Pin 10
o, VRs - 2v
o ~ L ___ µ~~~
Irnpedance 25 2
Response Tirne 08 _j_____L I J___Note_2_ _ __
COUNTER SECTION See Figure 4, v+ -- 5V
Max. Toggle Rate 0.8 1.5 ~------r--,-5-T·
J lj ;
I :~H:z i-VRs O, Vrn = 5V
Max. Input Pin 14
Input
lnpedance 15 I I 15 I kH I Measured at Pin 14
Threshold
Output
Rise Time
1.0
14 ,!
I
1' 1 .0 i 14 1 l' v II Measured at Pins 1 thru 8
l
180 II I '. 18.0 nsec RL=3k,CL-10pF
Fall Time ' 180 ' 180 nsec
VouT Low
Leakage Current ooo; L o ( _ i ___Looo; _ - o1~ - -- µ~ -- ·- ~~-~K__1~J mA
CARRYOUTGATE- -
Vco Low
vco High
NOTE 1 Timing error solely introduced by 8250, med sured as% of ideal of T - 1 00 RC
NOTE 2 P1opagJt1on deldy from apµl1cat1on oi tr1gqer (or reset) input 10 c<)ne,;pon,ding state change in counter output at Pin 1
263
ELECTRICAL CHARACTERISTICS
Test Conditions: See Figure 2, v+ = 5V, TA= 25°C, R = 10 kD, C = 0.1 µF, unless otherwise noted.
8260
8260M 8260C
-
PARAMETERS UNITS CONDITIONS
MIN. TYP. MAX. . Ml~l_~~j_1',o1A_X_·~---~------·----------<
------ ----·--r
GENERAL CHARACTERISTICS
Supply Voltage
Supply Current
4.5
18 T-4.5}____[_
-,-BI~
Total Circuit (Re.set) I 3.5
12
6
161
4
13
7
18
mA
mA
v+=5V,VTR=O,VRs=5V
v+·=15V,VTR=O,VRs=5V
Total Circuit (Trigger) 24 24 v+ = 15V, VTR = 5V, VRs = 0
All outputs ON. (Worst Case)
--~ -~ --
TIME BASE SECTION See Figure 2
---------~ ~-~ --·~--....---~---- ~~.--------- -------------;
Timing Accuracy 05 2.0 0.5 % VRs = 0, VTR = 5V, Note 1
Temperature Drift 150 300 200 ppm/°C v+ = 5V Over Operating Temp.
80 80 ppm/'C v+ = 15V
Supply Drift 0.05 0.2 0.08 0.3 %/V v+:;;, 8 Volts, See Figure 11
Max. Frequency 100 130 130 kHz R = 1 kD. C = 0.007µF
Time Base Output Measured at Pin 14
I
VTB HIGH 2.4 28 2.4 i
2.8 V Isource= BOµA
VTB LOW 02 0.4 I 0.2 0.4 V 'sink= 3.2mA
Modulation Voltage I I Measured at Pin 12
Level
3.00 3.50 4.0 2.80 I 3 50 I 4 20 v j:+= 5V
~e: ~'~~~e 8
5 5
Recommended Range l0. I --4-----1l0. V
of Timing Components
Timing Resistor, R 0.001 10 0.001 l\ 10 MD
_ _Timing Capa~or, C ~~-~----- _1_000 ~~- --~1_0_0_0_~_._µ_F___ _ _ _ _ _ _ _ _ _ _ _ __
TRIGGER/RESET CONTROLS
---~-----~--- - ..--------~~------
v ]_""""'"'""''"'5
t -or·
Vco Low
02
. I 0.4 - -t-J2 ls1NK = 3 2 mA
NOTE 1: Timing error solely introduced by 8260, measured as% of ideal time-base period of T . : : 1.00 RC
NOTE 2: Propagation delay from application of trigger (or reset) input to corresponding state change in counter output at Pin 1
264
Figure 2. Generalized Test Circuit Figure 3. Test Circuit for low-Power Figure 4. Test Circuit for Counter Section
Operation !Time-Base Powered Oownl 8240 Only.
10 1] 14 l£ 18
~UPPL Y VOL TAGF VOL TS•
Figure 5. Supply Current vs. Supply Figure 6. Recommended Range of Figure 7. Time-Base Period, T, as a
Voltage in Reset Condition Timing Component Values Function of External RC
g
~ 0, ~~+-------t------+-----1
Vee
Figure 8. Minimum Trigger and Reset Figure 9. Power Supply Drift Figure 10.
Pulse Widths at Pins 10 and 11 A) Minimum Trigger Delay Time Sub-
sequent to Application of Power
Bl Minimum Re-trigger Time, Subs&-
quent to a Reset Input
--+- - - ~ + - - -
''):''• -- -· +- - - _ __, - -
ro
2 O':i
-
~ ~- ~:-+
265
ORDERING INFORMATION
PACKAGE INFORMATION
[::::::::i
()92
_. - 10B
A~o
••:- ,o~~
·- 100 -
NON'
266
APPENDIX B
Second-Source Guide
267
Timer Type Package Manufacturer Part No.
268
IC Timer Manufacturers
Fairchild Camera and Instrument Corp. RCA Corp., Solid State Div.
Semiconductor Components Group Route 202
464 Ellis Street Somerville, NJ 08876
Mountain View, CA 94042
Signetics Corp.
lntersil, Inc. 811 East Arques Avenue
l 0900 North Tant au Avenue Sunnyvale, CA 94086
Cupertino, CA 95014
Silicon General, Inc.
Lithic Systems, Inc. 7382 Bolsa Avenue
15800 Sanborn Road Westminster, CA 92683
P.O. Box 478
Saratoga, CA 95070 Teledyne Semiconductor
1300 Terra Bella Avenue
Motorola Semiconductor Products, Inc. Mountain View, CA 94043
5005 East McDowell Road
Phoenix, AZ 85008 Texas Instruments, Inc.
P.O. Box 5012
Dallas, TX 75222
269
APPENDIX c
Timing Component Manufacturers
271
Capacitors
272
Resistors
273
APPENDIX D
Design Awards
EDN
221 Columbus Avenue
Boston, MA 02116
Designer's Casebook
Electronics
1221 Avenue of the Americas
New York, NY 10020
275
1972
276
1974
1. Fusar, T. J. "IC Timer Makes Economical Automobile Voltage Regulator."
Electronics, February 21, 1974.
2. Hofheimer, R. "One Extra Resistor Gives 555 Timer 50% Duty Cycle."
EDN, March 5, 1974.
3. ~filler, P. A. "Clocked Circuit Debounces Multiple Single Throw Contacts
Synchronously." Electronic Design, March 15, 1974.
4. Blackburn, J. A. "Winking LED Notes Null for IC Timer Resistance Bridge."
Electronics, March 21, 1974.
5. Dugan, K. R. "Making Music With IC Timers." Electronics, April 18, 1974.
6. Predescu, J. "Tester Built for Less Than $10 Gives Go/No-Go Check of
Timer I Cs." Electronic Design, May 24, 1974.
7. Herring, L. W. "Generating Tone Bursts With Only Two IC Timers."
Electronics, May 30, 1974.
8. Pohlman, D. T. "Timer/Counter Chip Synthesizes Frequencies and It
Needs Only a Few Extra Parts." Electronic Design, June 21, 1974.
9. Beckwitt, D. J. "AC Ohmmeter Provides Novel Use for Optoisolators."
EDN, July 5, 1974.
10. Klinger, A. R. "Single Part Minimizes Differences in Monostable and Astable
Periods of 555." Electronic Design, July 19, I974.
11. Paiva, M. D. "Start a Logic Circuit in the Proper Mode When Power Is
Turned ON or Interrupted." Electronic Design, August 2, 1974.
12. Laughlin, E. G. "Inexpensive Pulse Generator Is Logic Programmable."
EDN, August 20, 1974.
13. Gartner, T. "IC Timer and Voltage Doubler Form a DC-DC Converter."
Electronics, August 22, 1974.
14. Klinger, A. R. "Getting Extra Control Over Output Periods of IC Timer."
Electronics, September 19, 1974.
15. Buckman, G. H. "Simple LED Flasher Is Controllable." EDN, September
20, 1974.
16. Gephart, R. L. "Mini-DIP Bistable Flip-Flop Sinks or Sources 200 mA."'
EDN, October 5, 1974.
17. Gulbranson, G. "Precision Timer Can Be Used to Make a Stable, Adjustable
Crowbar Driver." Electronic Design, October 11, 1974.
18. Woodward, W. S. "Simple 10 kHz V/F Features Differential Inputs." EDN,
October 20, 1974.
19. Martens, A. E. "Switch Selects Accurate Time Delays." EDN, November 5,
1974.
20. Althouse, J. "IC Timer, Stabilized by Crystal, Can Provide Subharmonic
Frequencies." Electronic Design, November 8, 1974.
21. Morgan, L. G. "Electronic Ignition System Uses Standard Components."
Electronic Design, November 22, 1974.
22. Felps, J. "Timer Circuit Generates Precision Power-On Reset." Electronics,
November 28, 1974.
23. Klinger, A. R. "Generator's Duty Cycle Stays Constant Under Load."
Electronics, November 28, 1974.
277
24. Long, J. D. "Burglar Alarm Is Effective Yet Simple and Inexpensive."
EDN, December 20, 1974.
25. Galluzzi, P. "Circuit Provides Slow Auto-Wiper Cycling With 1-20 Seconds
Between Sweeps." Electronic Design, December 20, 1974.
26. Hinkle, F. E.; Edvington, J. "Timer IC and Photocell Can Vary LED
Brightness." Electronics, December 26, 197 4.
27. Lacefield, M. M. "Simple Step-Function Generator Aids in Testing Instru-
ments." Electronics, December 26, 1974.
1975
1. Dogra, S. "Operate a 555 Timer on a ±15V Supply and Deliver Op Amp
Compatible Signals." Electronic Design, January 18, 1975.
2. Lickel, K. "Compensating the 555 Timer for Capacitance Variations."
Electronics, February 6, 1975.
3. Kraengel, W. D. "Optically Coupled Ringer Doesn't Load Phone Line."
Electronics, February 20, 1975.
4. Johnson, K. R. "High Voltage Power Supply From a 5V Source Regulated
by Timer Feedback Circuit." Electronic Design, April 1, 1975.
5. Tandon, V. B. "Circuit Converts Single Trace Scope to Dual Trace Dis-
play for Logic Signals." Electronic Design, April 12, 1975.
6. Hinkle, F. E. "Overrange Indicator Can Enhance Frequency Meter." Elec-
tronics, April 17, 1975.
7. Flynn, E. A. "Put a Pendulum in Your Electronic Grandfather Clock."
EDN, May 5, 1975.
8. Black, S. L. "555 as Switching Regulator Supplies Negative Voltage."
Electronics, May 15, 1975.
9. Durgavich, T. "Compact DC-DC Converter Yields ±15V From +5V."
Electronics, June 12, 1975.
10. Saunders, L. "Locked Oscillator Uses a 555 Timer." EDN, June 20, 1975.
11. Wise, R. M. "Capacitive Transducer Senses Tension in Muscle Fibers."
Electronics, June 26, 1975.
12. Hilsher, R. W. "Constant Period With Variable Duty Cycle Obtained From
555 Timer With Single Control." Electronic Design, July 5, 1975.
13. Dance, J. B. "Ultrasonic Transmitter/Receiver Generates a 20 ft Beam That
Detects Objects." Electronic Design, August 2, 1975.
14. Lewis, G. R. "Low-Cost Temperature Controller Built With Timer Circuits."
Electronic Design, August 16, 1975.
15. Fleagle, J. E. "Timer ICs Control Life-Test Cycling." Electronics, Oc-
tober 2, 1975.
16. Nichols, J. C. "Versatile Delay-on-Energize Timer 'Uses Two 555s." EDN,
October 5, 1975.
17. Tenny R. "Linear VCO Made From a 555 Timer." Electronic Design,
October 11, 1975.
18. Domiciano, P. "Inverter Uses Ferrite Transformer to Eliminate Cross-
Conduction." Electronic Design, October 25, 1975.
19. Chetty, P. R. K. "IC Timers Control DC-DC Converters." Electronics,
November 13, 1975.
278
1976
I. Chetty, P. R. K. "Put a 555 Timer in Your Next Switching Regulator De-
sign." EDN, January 5, 1976.
2. Gualtieri, D. M. "Triangular Waves From 555 Have Adjustable Symmetry."
Electronics, January 8, 1976.
3. Gardner, M. R. "Line Drivers Made From 555 Timers Provide Inverted or
Noninverted Outputs." Electronic Design, January 19, 1976.
4. Bochstabler, R. W. "Bistable Action of 555 Varies With Manufacturer."
Electronics, February 19, 1976.
5. Jung, W. G. "Power Ramp Generator Delivers an Easily Adjustable IA Out-
put." Electronic Design, March 1, 1976.
6. Blair, D. G. "Timer Chip Becomes Meter That Detects Capacitance Changes
of 1 Part in 10." Electronic Design, March 1, 1976.
7. Bainter, J. R. "Dual 555 Timer Circuit Restarts Microprocessor." Electronics,
March 18, 1976.
8. Cicchiello, F. N. "Timer IC Stabilizes Sawtooth Generator." Electronics,
March 18, 1976.
9. Hanisko, J. "Timer/Counter Functions as PLL Component." EDN, March
20, 1976.
10. Graf, C. R. "Audio Continuity Tester Indicates Resistance Values." Elec-
tronics, April 1, 1976.
11. Berlin, H. M. "555 Timer Tags Waveforms in Multiple Scope Display."
Electronics, April 29, 1976.
12. Gergek, F. "Potentiometer and Timer Control Up/Down Counter." Elec-
tronics, May 13, 1976.
13. Cicchiello, F. N. "IC Timer Circuit Yields 50% Duty Cycle." Electronics,
May 13, 1976.
14. Lo, C. C. "CD Ignition System Produces Low Engine Emissions." EDN,
May 20, 1976.
15. Zwicker, R. M. "Phase Locked Loop Circuit Multiplies Frequencies by 2 to
256." Electronic Design, May 24, 1976.
16. Klinger, A. R. "Logic Probe Built From IC Timer Is Compatible With
TTL, RTL & CMOS." Electronic Design, June 7, 1976.
17. McClellan, A. "Current Source and 555 Timer Make Linear V-F Con-
verter." Electronics, June 10, 1976.
18. McNatt, M. S. "Computer Sound Effects Generated With Only Four ICs."
Electronic Design, July 5, 1976.
19. Redmile, B. D. "Tail-Biting One-Shot Keeps Car Door Light On." Elec-
tronics, July 8, 1976.
20. Kranz, P.; Seger, J. "A Simple Battery Charger for Gel Cells Detects Full
Charge and Switches to Float." Electronic Design, July 19, 1976.
21. Kraus, K. "Timer IC Paces Analog Divider." Electronics, August 5, 1976.
22. Jung, W. G. "555 One-Shot Circuit Features Negative Output With Positive
Triggering." Electronic Design, August 16, 1976.
23. Sandberg, B. "State Diagrams for a 555 Timer Aid Development of New
Applications." Electronic Design, August 16, 1976.
279
24. Murugesan, S. "Create a Versatile Logic Family With 555 Timers." EDN,
September 5, 1976.
25. Lalitha, M. K.; Chetty, P. R. K. "Variable-Threshold Schmitt Trigger Uses
555 Timer." EDN, September 20, 1976.
26. Srinivasan, M. P. "Special-Purpose Pulse-Width Modulator Produces an
Output of Same Polarity as Input." Electronic Design, September 27, 1976.
27. Jung, W. G. "Build a Function Generator With a 555 Timer." EDN, Oc-
tober 5, 1976.
28. Piankian, R. "Timer Extends Life of Teletypewriter." Electronics, Novem-
ber 25, 1976.
29. Sarpangal, S. "IC Timer Drives Electric Fuel Pump." Electronics, Novem-
ber 25, 1976.
30. Grundy, G. L. "Engine Staller Thwarts Car Thieves." Electronics, Decem-
ber 23, 1976.
1977
1. Morgan, D. R. "Control 10 to 10,000 Hz Digitally and Get Complementary
Output Frequencies." Electronic Design, January 18, 1977.
2. Shiff, V. E.; Parr, R. H. "Watchdog Circuit Guards µP Systems Against
Looping." Electronic Design, January 18, 1977.
280
Index
A Astable-cont
timer circuits
A/d converter, 226-228 simplified astable, 134-135
Alarm square-wave astables, 116-118
burglar, 231-232 with extended range, 118-121
indicators, 232-235 type 322 square-wave astable,
speed, 228-230 121-123
Amplifiers, booster, 163-164 type 2240 "guaranteed" square-
Appliance timer, universal, 214, 216- wave astable, 123-124
218 wide-range square-wave/triangle-
Astable wave generator, 144-145
mode of operation
555 timer, 30-32
2240 timer/counter, 55, 56
B
RC timer, 14-18
timer circuits, 115-145
astable with independently ad- Bipolar staircase generator, 224-226
justable timing periods, 129- Bistable buffer, inverting, 149
130 Booster amplifiers, 163-164
astable with independently ad- Burglar alarm, 231-232
justable timing periods and
auxiliary output, 130-131
astable with independently con- c
trollable timing periods, 128-
129 Capacitors, timing, 68-70
astable with separately controlla- Charge balancing, 185
ble timing periods, 131-132 Circuits
astable with totally independent astable timer, 115-145
and "limitless" timing peri- astable with independently ad-
ods, 132-134 justable timing periods, 129-
"chain" astable, 125-128 130
dual "one-shot" astable, 124-125 astable with independently ad-
gated simplified astable, 135-136 justable timing periods and
improved linear-ramp astable, auxiliary output, 130-131
141-142 astable with independently con-
improved minimum-component trollable timing periods, 128-
astable, 116 129
minimum-component astable, 115- astable with separately controlla-
116 ble timing periods, 131-132
negative linear-ramp astable, 142- astable with totally independent
144 and "limitless" timing peri-
programmable-frequency astables, ods, 132-134
137-139 "chain" astable, 125-128
selectable-frequency astable, 136- dual "one-shot" astable, 124-125
137 gated simplified astable, 135-136
simple linear-ramp astable, 139- improved linear-ramp astable,
141 141-142
281
Circuits-cont CMOS function generator, 168-170
astable timer Comparator, voltage, 151-152
improved mm1mum-component Converters
astable, 116 a/ d, 226-228
minimum-component astable, 115- d/a, 224-226
116 de/de, 196, 198-201
negative linear-ramp astable, 142- frequency-to-voltage, 192-196
144 triangle-to-sine-wave, 179-180
programmable-frequenc y astables, voltage-to-frequency, 184-192
137-139 Crystal oscillator/ divider circuits, 207-
selectable-frequency astable, 136- 214
137 CMOS oscillator, 209-211
simple linear-ramp astable, 139- precision oscillators, 211-214
141
simplified astable, 134-135 D
square-wave astables, 116-118 D/a converter, 224-226
with extended range, 118-121 Data link, optoisolated, 156-158
type 322 square-wave astable, De/de converters, 196, 198-201
121-123 Design precautions, IC timers, 70-71
type 2240 "guaranteed" square- Detector
wave astable, 123-124 window, 153
wide-range square-wave I triangle- zero-crossing, 152
wa ve generator, 144-145 Dielectric absorption, 68
monostable timer, 85-114 Differential line driver, 156
delayed-pulse generation, 97-98 Duty factor, 17
extended-range monostables, 102- definition of, 32
105
fast voltage-to-pulse-width con- E
verter, 109-110
Error detectors, power-monitor, 230-
555 monostable with auxiliary
231
output, 86-87
improved inverted monostable, 89 F
inverted monostable, 87 -89
linear-ramp monostables, 107-109 Free-running mode of operation, 555
long-period voltage-controlled timer, 30-32
timer, 110-112 Freewheeling, power-fail oscillator,
manually triggered monostables, 201-203
89-91 Frequency meter, lab-type, 193, 195-
power-up one-shots, 92-94 196
programmable monostables 98- Frequency-to-voltage converters, 192-
, 102 , 196
ratiometric voltage-to-pulse-width Function generators, 167-180
converter, 112-114 CMOS, 168-170
restartable one-shot, 94-96 triangle-to-sine-wave converter, 179-
retriggerable one-shot, 96-97 180
touch switch, 91-92 voltage-controlled oscillators, 17 4-
voltage-controlled monostables, 179
105-107 wide-range, tunable, 170-172
Clock sources, more precise, 204-214 with logarithmic control characteris-
crystal oscillator I divider circuits, tics, 172-174
207-214 G
CMOS oscillator, 209-211
precision oscillators, 211-214 Generator
LC oscillators, 204-207 bipolar staircase, 224-226
"never-fail" 1-Hz clock, 214, 215 time-mark, 218-220
282
IC timers-cont
IC timers systems applications
general operating procedures and output drive circuits
precautions, 63-81 driving incandescent lamps,
design precautions, 70-71 160-161
peripheral devices, 71-80 driving LEDs, 159-160
logic devices, 75-79 driving relays, 161-162
op amps, 71-75 phase-locked loops, 220-224
regulators, 79-80 power-monitor error detectors,
transistor arrays, 80 230-231
pinouts and terminal designations, sine-wave/square-wave oscillator,
63-65, 66 203-204
timing component considerations, speed alarm, 228-230
65-70 time-delay relay circuits, 164-167
capacitors, 68-70 time-mark generator, 218-220
resistors, 65-68 universal appliance timer, 214,
systems applications, 14 7-236 216-218
a/d converter, 226-228 voltage-to-frequency converters,
alarm indicators, 232-235 184-192
bipolar staircase generator, 224- wide-range pulse generator, 180-
226 184
burglar alarm, 231-232 types, 19-62
de/de converters, 196, 198-201 322 precision monostable, 36-46
freewheeling, power-fail oscilla- basic operation, 43-45
tor, 201-203 definition of pin functions, 39,
frequency-to-voltage converters, 41-43
192-196 functional diagram and sche-
function generators, 167-180 matic, 37-39, 40
CMOS, 168-170 package styles, 37
triangle-to-sine-wave converter, specifications, 45-46
179-180
voltage-controlled oscillators, 555 single-unit general-purpose,
174-179 19-33
wide-range, tunable, 170-172 basic operating modes, 26-32
with logarithmic control char- definition of pin functions, 23-
acteristics, 172-174 26
logic functions, 147-158 functional diagram and sche-
differential line driver, 156 matic, 19-23
inverting bistable buffer, 149 package styles, 19
line receivers, 153-155 specifications, 32-33
optoisolated data link, 156-158 556 dual-unit general-purpose,
Schmitt trigger, 147-148 33-36
set-reset ( R-S) flip-flop, 150 basic operating modes, 34
voltage comparator, 151-152 definition of pin functions, 33
window detector, 153 functional diagram and sche-
zero-crossing detector, 152 matic, 33, 34, 35
more-precise clock sources, 204- specifications, 34, 36
214 2240 programmable timer/
crystal oscillatorI divider cir- counter, 46-57
cuits, 207-214 basic operating modes, 53-55,
LC oscillators, 204-207 .56
"never-fail" 1-Hz clock, 214, definition of pin functions,51-53
215 functional diagram, 47-51
output drive circuits, 158-164 package styles, 47
booster amplifiers, 163-164 specifications, 55, 57
283
IC timers-cont Modes of operation-cont
types 556 timer, 34
2250 programmable timer/ 2240 timer/counter, 53-55, 56
counter, 46-47, 57-60 astable, 55, 56
basic operating modes, 59-60 monostable, 53-55
functional diagram, 57 -59 2250 timer/counter, 59-60
package styles, 57 3905 timer, 43-45
specifications, 60 8260 timer/counter, 62
3905 precision monostable, 36-46 Monostable
basic operation, 43-45 mode of operation
definition of pin functions, 39, 555 timer, 27-30
41-43 2240 timer/counter, 53-55
functional diagram and sche- RC timer, 11-14
matic, 37-39, 40 timer circuits, 85-114
package styles, 37 delayed-pulse generation, 97-98
specifications, 45-46 extended-range monostables, 102-
8250 programmable timer/ 105
counter, 57, 59 fast voltage-to-pulse-width con-
8260 programmable timer/ verter, 109-110
counter, 46-47, 60-62 555 monostable with auxiliary
basic operating modes, 62 output, 86-87
definition of pin functions, 60 improved inverted monostable, 89
functional diagram, 60, 61 inverted monostable, 87 -89
package styles, 60 linear-ramp monostables, 107-109
specifications, 62 long-period voltage-controlled
Incandescent lamp driver circuits, 160- timer, 110-112
161 manually triggered monostables,
Indicators, alarm, 232-235 89-91
Inverting bistable buffer, 149 power-up one-shots, 92-94
programmable monostables, 98-
102
Lab-type frequency meter, 193, 195- ratiometric voltage-to-pulse-width
196 converter, 112-114
LC oscillators, 204-207 restartable one-shot, 94-96
LED driver circuits, 159-160 retriggerable one-shot, 96-97
Line driver, differential, 156 touch switch, 91-92
Line receivers, 153-155 voltage-controlled monostables,
Logic devices, 75-79 105-107
Logic functions, IC timers, 147-158
N
differential line driver, 156
inverting bistable buffer, 149 "Never-fail" 1-Hz clock, 214, 215
line receivers, 153-155
0
optoisolated data link, 156-158
Schmitt trigger, 147-148 One-shot mode of operation, 555 timer,
set-reset ( R-S) flip-flop, 150 27-30
voltage comparator, 151-152 Op amps, 71-75
window detector, 153 Operating modes
zero-crossing detector, 152 322 timer, 43-45
555 timer, 26-32
M astable, 30-32
Modes of operation monostable, 27-30
322 timer, 43-45 556 timer, 34
555 timer, 26-32 2240 timer/counter, 53-55, 56
astable, 30-32 astable, 55, 56
monostable, 27-30 monostable, 53-55
284
Operating modes-cont Relay driver circuits, 161-162
2250 timer/counter, 59-60 Resistors, timing, 65-68
3905 timer, 43-45
8260 timer/counter, 62 s
Optoisolated data link, 156-158 Schmitt trigger, 147-148
Oscillator/divider circuits, crystal, 207- Set-reset ( R-S) flip-flop, 150
214 Sine-wave/square-wave oscillator, 203-
CMOS oscillator, 209-211 204
precision oscillators, 211-214 Specifications
Oscillators 322 timer, 45-46
free-wheeling, power-fail, 201-203 555 timer, 32-33
LC, 204-207 556 timer, 34, 36
sine-wave/square-wave, 203-204 2240 timer/counter, 55, 57
voltage-controlled, 174-179 2250 timer/counter, 60
Output drive circuits, 158-164 3905 timer, 45-46
booster amplifiers, 163-164 8260 timer/counter, 62
driving incandescent lamps, 160-161 Speed alarm, 228-230
driving LEDs, 159-160 Staircase generator, bipolar, 224-226
driving relays, 161-162 Systems applications, IC timer, 147-
236
p a/ d converter, 226-228
alarm indicators, 232-235
Package styles bipolar staircase generator, 224-226
322 timer, 37 burglar alarm, 231-232
555 timer, 19 de/de converters, 196, 198-201
2240 timer/counter, 47 freewheeling, power-fail oscillator,
2250 timer/counter, 57 201-203
3905 timer, 37 frequency-to-voltage converters,
8260 timer/counter, 60 192-196
Peripheral devices, 71-80 function generators, 167-180
logic devices, 75-79 CMOS, 168-170
op amps, 71-75 triangle-to-sine-wave converter,
regulators, 79-80 179-180
transistor arrays, 80 voltage-controlled oscillators, 174-
Phase-locked loops, 220-224 179
Pin functions wide-range, tunable, 170-172
322 timer, 39, 41-43 with logarithmic control charac-
555 timer, 23-26 teristics, 172-174
556 timer, 33 logic functions, 147-158
3905 timer, 39, 41-43 differential line driver, 156
8260 timer/ counter, 60 inverting bistable buffer, 149
Power-fail oscillator, freewheeling, line receivers, 153-155
201-203 optoisolated data link, 156-158
Power-monitor error detectors, 230-231 Schmitt trigger, 147-148
Pulse generator, wide-range, 180-184 set-reset ( R-S) flip-flop, 150
voltage comparator, 151-152
R window detector, 153
zero-crossing detector, 152
RC timing circuits more-precise clock sources, 204-214
basic theory of operation, 11-18 crystal oscillator/divider circuits,
astable type, 14-18 207-214
monostable type, 11-14 CMOS oscillator, 209-211
Receivers, line, 153-155 precision oscillators, 211-214
Regulators, 79-80 LC oscillators, 204-207
Relay circuits, time-delay, 164-167 "never-fail" 1-Hz clock, 214, 215
285
Systems applications, IC timer-cont Timers, IC-cont
output drive circuits, 158-164 circuits
booster amplifiers, 163-164 astable
driving incandescent lamps, 160- negative linear-ramp astable,
161 142-144
driving LEDs, 159-160 programmable-frequency asta-
driving relays, 161-162 bles, 137-139
phase-locked loops, 220-224 selectable-frequency astable,
power monitor error detectors, 230- 136-137
231 simple linear-ramp astable, 139-
sine-wave/square-wave oscillator, 141
203-204 simplified astable, 134-135
speed alarm, 228-230 square-wave astables, 116-118
time-delay relay circuits, 164-167 square-wave astables, extended
time-mark generator, 218-220 range, 118-121
universal appliance timer, 214, 216- type 322 square-wave astable,
218 121-123
voltage-to-frequency converters, 184- type 2240 "guaranteed" square-
192 wa ve astable, 123-124
wide-range pulse generator, 180-184 wide-range square-wave/trian-
gle-wave generator, 144-145
monostable, 85-114
T delayed-pulse generation, 97-98
extended-range monostables,
Tachometer, 193-194 102-105
Time-delay relay circuits, 164-167 fast voltage-to-pulse-width con-
Time-mark generator, 218-220 verter, 109-110
Timers, IC 555 monostable with auxiliary
circuits output, 86-87
astable, 115-145 improved inverted monostable,
astable with independently ad- 89
justable timing periods, 129- inverted monostable, 87-89
130 linear-ramp monostables, 107-
astable with independently ad- 109
justable timing periods and long-period voltage-controlled
auxiliary output, 130-131 timer, 110-112
astable with independently manually triggered monosta-
controllable timing periods, bles, 89-91
128-129 power-up one-shots, 92-94
astable with separately control- programmable monostables, 98-
lable timing periods, 131-132 102
astable with totally indepen- ratiometric voltage-to-pulse-
dent and "limitless" timing width converter, 112-114
periods, 132-134 restartable one-shot, 94-96
"chain" astable, 125-128 retriggerable one-shot, 96-97
dual "one-shot" astable, 124- touch switch, 91-92
125 voltage-controlled monostables,
gated simplified astable, 135- 105-107
136 universal appliance timer, 214,
improved linear-ramp astable, 216-218
141-142 general operating procedures and
improved minimum-component precautions, 63-81
astable, 116 design precautions, 70-71
minimum-component astable, peripheral devices, 71-80
115-116 logic devices, 75-79
286
Timers, IC-cont Timers, IC-cont
general operating procedures and types
precautions 3905 precision monostable, 36-46
peripheral devices basic operation, 43-45
op amps, 71-75 definition of pin functions, 39,
regulators, 79-80 41-43
transistor arrays, 80 functional diagram and sche-
pinouts and terminal designations , matic, 37-39, 40
63-65, 66 package styles, 37
timing component consideratio ns, specifications, 45-46
65-70 8250 programmab le timer/
capacitors, 68-70 counter, 57, 59
resistors, 65-68 8260 programmab le timer/
types, 19-62 counter, 46-47, 60-62
322 precision monostable, 36-46 basic operating modes, 62
basic operation, 43-45 definition of pin functions, 60
definition of pin functions, 39, functional diagram, 60, 61
41-43 package styles, 60
functional diagram and sche- specifications, 62
matic, 37-39, 40 Timing circuits, RC
package styles, 37 basic theory of operation, 11-18
specifications, 45-46 astable type, 14-18
555 single-unit general-purp ose, monostable type, 11-14
19-33 Transistor arrays, 80
basic operating modes, 26-32 Triangle-to-sine-waYe converter, 179-
definition of pin functions, 23- 180
26
functional diagram and sche-
matic, 19-23 u
package styles, 19
specifications, 32-33 Universal appliance timer, 214, 216-
556 dual-unit general-purp ose, 218
33-36
basic operating modes, 34
definition of pin functions, 33
v
functional diagram and sche- Voltage comparator, 151-152
matic, 33, 34, 35 Voltage-con trolled oscillators, 17 4-179
specifications, 34, 36 Voltage-to-f requency converters, 184-
2240 programmab le timer/ 192
counter, 46-57
basic operating modes, 53-55,
56 w
definition of pin functions, 51-
Wide-range pulse generator, 180-184
53 Wide-range , tunable function genera-
functional diagram, 47-51
tor, 170-172
package styles, 47
with logarithmic control character-
specifications, 55, 57
istics, 172-17 4
2250 programmab le timer/ Window detector, 153
counter, 46-47, 57-60
basic operating modes, 59-60
functional diagram, 57-59
package styles, 57
z
specifications, 60 Zero-crossing detector, 152
287
COOi< BOO i<
The monolithic IC timer first appeared in 1972, and quickly established itself as
one of the most popular IC function blocks. So versatile and popular is this
device that the original timer prototype, the 555, is now available from a dozen
or more alternate sources at a single piece price of less than a dollar. Further
evidence of the viability of the IC timer concept is the fact that multiple 555s
have also appeared, as well as second generation timers capable of greater
range, precision, and programmability.
For these reasons, a timer applications book is more than appropriate.
Like the author's previous Sams publication, IC Op-Amp Cookbook, this book
is intended to be a collection of various circuit "recipes" useful in applying IC
timers. It is written in a practical, easy-to-read style that is suitable for readers
with a broad range of backgrounds and experience. All circuit examples are
complete with design equations and component yalues, and are optimized for
maximum cost effectiveness.
The book is divided into three main parts: Part I includes Chapters 1, 2,
and 3, which serve to introduce the IC timer and cover basic and generalized
information. Part II, the applications section, is the heart of the book and in-
cludes over 100 different timing circuits covering a wide range of uses. This
section is subdivided into three chapters: Chapter 4-Monostable Timer Cir-
cuits; Chapter 5-Astable Timer Circuits; and Chapter 6-IC Timer Systems
Applications. Part Ill consists of four appendixes: Appendix A contains repro-
ductions of timer manufacturers' data sheets; Appendix B lists various second-
source manufacturers for all timer devices discussed; Appendix C lists various
manufacturers of passive (RC) timing components; and Appendix D is an ex-
tensive bibliography of design articles that have appeared in electronic in-
dustry publications.
This book provides an excellent introduction to the field of IC timers and
their applications for anyone involved in modern solid-state electronics-from
hobbyist, to technical and engineering student, to practicing technician or en-
gineer. Not on ~ y does it contain many practical and useful circuits, it is also a
valuable reference of basic theoretical information.
$9.95/21416