IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO.

10, OCTOBER 2008 2269

Analysis and Design of RF CMOS Attenuators

Hakan Dogan, Member, IEEE, Robert G. Meyer, Fellow, IEEE, and Ali M. Niknejad, Member, IEEE

Abstract—Attenuators are analyzed for their minimum Inser- II. ATTENUATOR DESIGN ANALYSIS
tion Loss (IL), maximum attenuation and source-load matching
performance. These results are used to make trade-offs in the de- In this section, we analyze different types of attenuators in
sign of a CMOS attenuator with wide dynamic range, designed terms of their design parameters, which are insertion loss (IL),
and fabricated in a 0.13 m CMOS process. The design employs maximum attenuation, source and load matching properties. We
two non-identical cascaded T-stages that are activated consecu- will limit our analysis to most commonly used attenuator types,
tively to improve linearity. The design operates in the frequency -Attenuators and T-Attenuators. Fig. 1 shows the topology of
band of DC-2.5GHz with 0.9–3.5 dB insertion loss and 42 dB max-
imum attenuation in the entire frequency range. Worst case S11 is these two configurations.
8.2 dB across the frequency band. The design achieves an IIP3
+
of 20 dBm at mid-attenuation. A. Minimum Insertion Loss
Index Terms—Attenuator, attenuator analysis, attenuation con- Fig. 2 gives the schematic for the minimum IL condition of a
trol loop, CMOS attenuator, highly linear attenuator, parasitic ef- single-stage -Attenuator. In a -Attenuator such as this one,
fects on attenuators, RF attenuator. minimum attenuation occurs when the series device is com-
pletely on and the shunt devices are off. In that case, loss at low
frequencies comes only from the nonzero on-resistance of the
I. INTRODUCTION series device. As this resistor gets smaller, the signal loss due to
the insertion of the attenuator gets smaller. At higher frequen-
T HE received signal power in cable and wireless commu-
nication systems may vary by orders of magnitude. These
systems thus require precise gain control in the signal path to
cies, there is additional loss caused by the parasitic capacitors to
ground and minimizing these capacitors reduces the loss. Fur-
limit the incident power to the receiver circuitry. Similarly, thermore, for high impedance systems, the finite shunt device
emerging communication standards such as WCDMA require off-resistance becomes comparable with the source resistance
stringent power control on the transmitted signal. and causes the series device not to turn on completely in order
Variable-gain amplifiers (VGAs) are the traditional method for good matching, therefore increases the insertion loss.
of implementing gain control. However, it has been shown in The parasitic capacitors are mainly due to the gate capaci-
the literature that FET attenuators are also good candidates for tors of the devices and the junction capacitors between the drain
achieving the same function with superior performance in var- and source implants and the p-substrate of the chip. The gate
ious design criteria such as linearity and power handling require- capacitors consist of the gate-oxide capacitors and the overlap
ments, which are exteremely important for wideband applica- capacitors due to the overlap of the gate area and the source
tions such as cable modem receivers [1]–[3], [6], [18]. These or drain areas. The resistor is placed in series with the
requirements generally are very difficult to meet with VGAs, gate in order to isolate the gate capacitors, thus minimizing the
hence, power dissipation in these components may be hundreds total parasitic capacitance to ground at a given node and broad-
banding the network. Fig. 2 also gives the equivalent lumped
of milliwatts in order to meet these specifications. Attenuators
resistor-capacitor network for the schematic given in the same
with FET devices in their resistive linear region, on the other
figure.
hand, are passive blocks and do not dissipate any static power.
Assuming that the attenuator is symmetric with respect to the
Furthermore, the downscaling of CMOS technology provides
input and output nodes, and capacitors are equal in
faster devices, which are suitable for broadband RF applications
value. These capacitors consist of the gate-oxide and junction
that can be integrated on a single chip. In this work, the design
parasitic capacitors of the devices as explained above and can
of wideband, highly-linear CMOS attenuators is discussed. The
be expressed as
design of a sample attenuator along with the simulated and mea-
sured results is given. The attenuator exhibits a linear-in-dB at- (1)
tenuation curve and matches to the port impedances at the input
and output over the entire frequency range of operation. The gate-to-drain capacitor in this equation is scaled by two
since the gate-drain and gate-source capacitors of are con-
Manuscript received December 6, 2007; revised June 23, 2008. Current ver- nected in series as a result of the large resistor in series with the
sion published October 8, 2008. This work was supported by the U.S. Army gate. in Fig. 2 is the series combination of the gate-drain and
Research Office under Grant DAAD19-00-1-0550. Chip fabrication was pro-
vided by STMicroelectronics.
gate-source capacitors of and given by .
H. Dogan is with Atheros Communications, Santa Clara, CA 95054 USA Assuming is equal to , we now can write the IL equa-
(e-mail: [email protected]). tion for the network as
R. G. Meyer and A. M. Niknejad are with the Department of Electrical Engi-
neering and Computer Science, University of California, Berkeley, CA 94720-
1770 USA (e-mail: [email protected]). (2)
Digital Object Identifier 10.1109/JSSC.2008.2004325

0018-9200/$25.00 © 2008 IEEE

2270 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 10, OCTOBER 2008

Fig. 1. Attenuator networks. (a) 5-Network. (b) T-Network.

The first part of this equation gives the insertion loss of the
network at low frequencies. in (2) can be approximated by
[2], [9]

(3)

where models the drain and source resistances, mobility degra-

dation and other short channel effects. The exponential increase
of the drain current with value in the subthreshold region
is modeled by the parameter .
In a fashion similar to the -Attenuator, the series devices
of the T-Attenuator at the minimum gain setting are completely
on and the shunt device is turned off. The loss in the attenuator
is now dependent on the two series resistors, and the sizes of
these resistors determine the amount of the loss. Fig. 3 shows
the T-Attenuator in its minimum insertion loss setting. As men-
tioned previously for the -Attenuator, the capacitors in this
figure denote the gate-oxide capacitors and the junction capaci-
Fig. 2. Minimum insertion loss condition for a 5-Network and the equivalent tors of the MOS devices. The lumped resistor-capacitor network
circuit model.
equivalent of the schematic is also given in this figure.
We can conclude from the symmetry of the attenuator that
is equal to and is equal to . These capacitors
can be approximated as
(4)
(5)

(6)

The transfer function for the circuit can be approximated for

fairly small at the minimum attenuation setting as

(7)

The frequency independent term in (2) and (7) gives the IL

for the attenuator at low frequencies. The dominant pole causes
the IL to degrade at higher frequencies. The pole magnitude is
set by the sum of all the parasitic capacitors from any node in
the attenuator to ground, with the assumption that is much
smaller than and . Therefore, minimizing the total para-
sitic capacitors to ground in both of the attenuators will extend
the bandwidth for the IL. Using large gate resistors serves this
Fig. 3. Minimum insertion loss condition for a T-Network and the equivalent
circuit model.
purpose as a result of isolating the gate capacitors of the se-
ries devices from input to output rather than being terminated
DOGAN et al.: ANALYSIS AND DESIGN OF RF CMOS ATTENUATORS 2271

Fig. 4. IL versus series device width for the 5- and T-Attenuators at DC.
Fig. 5. IL versus frequency for the 5-Attenuator (W = 40 m, 80 m).
to ground. Furthermore, as explained previously, a tradeoff be-
tween the IL and the flatness of IL over frequency is apparent
since increasing the device size to improve the IL introduces
larger parasitic capacitors, which limit the bandwidth of the
circuit.
T-type attenuators mainly achieve attenuation by shorting the
middle node of the circuit in Fig. 3 to ground with the help of
the MOS device . Minimizing the on-resistance of this de-
vice increases the maximum achievable attenuation. Therefore,
in this type of a network, the shunt device is usually made large.
In addition, the series devices are chosen large to minimize the
IL of the attenuator. Thus, the T-Attenuator has three large de-
vices whose parasitic capacitors add up to give the dominant
pole of the system. As a result, the total parasitic capacitance in
this network is much larger than the -Network, resulting in a
frequency response that is not as broad as in the latter. This is
apparent in Figs. 5 and 6. Furthermore, as in the -Attenuator,
for high impedance systems, finite shunt device off-resistance
becomes comparable with the source resistance. This causes the
series device resistance to increase and compensate for the re-
duced impedance for adequate matching, which increases the
insertion loss for all frequencies. Fig. 6. IL versus frequency for the T-Attenuator (W = 80 m, 160 m).
Fig. 4 shows the simulated IL of the -Attenuator and T-At-
tenuator together as a function of the series device size. This
graph verifies that for a given device size, the T-Network has the input. At lower frequencies, almost complete isolation can
larger loss and the IL improves with increasing device sizes. be achieved from this topology. However, the leakage of the
Figs. 5 and 6 show the simulated IL curve as a function of fre- channel and additional parasitic resistances and inductances
quency for different low frequency IL and maximum attenuation from the circuit ground to the common ground limit the iso-
settings. As shown by (2) and (7), the IL shows a single dom- lation of the attenuator even at lower frequencies, since these
inant pole roll off. In addition, improving the IL from 1 dB to create additional coupling paths from the input to the output.
0.5 dB lowers the corner frequency of the attenuator. Similarly, However, the isolation achieved from this kind of an attenuator
increasing the shunt device size in the T-Network to improve with careful chip planning may be adequate for almost all
maximum attenuation has a very large impact on the corner fre- applications owing to very high off-resistances of the MOS
quency due to increased parasitic capacitance in the circuit. devices.
Fig. 7 gives the equivalent circuit for the -Attenuator for
B. Maximum Attenuation the maximum attenuation condition. The series device in this
In the case of maximum attenuation, the series device in the schematic is modeled by a resistance, , and a capacitor,
-Attenuator completely shuts off, isolating the output from , that form a feedthrough path from the input to the output.
2272 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 10, OCTOBER 2008

Fig. 7. Maximum attenuation condition for the 5-Network and the equivalent
circuit model.
Fig. 8. Maximum attenuation condition for the T-Network and the equivalent
circuit model.

It can be seen by inspection that if the resistance of the se-

ries device is infinite when it is off, this feedthrough capacitor
gives a zero in the transfer function at DC. The shunt devices It can be shown from this equation that in the absence of any
have channel resistances equal to and assuming perfect ground parasitics, the gain has a zero at and
matching at DC and a large . low frequency gain from the input of the attenuator is
Capacitors in this network can be given as

(8) (11)

(9)
It is easy to show that the two poles in the transfer function are
around in the absence of ground parasitics. Given that
It is important to realize that values of these capacitors are de-
the shunt devices (therefore ) are small, this pole magnitude
pendent on the biasing of the transistor, therefore in each anal-
is much higher than the useful frequency range of this network.
ysis they need to be handled carefully. In the off state, the device
Consequently, the maximum attenuation of the -Network be-
gate capacitor consists of the overlap capacitors, whereas in the
comes flat over a wide frequency range until the zero becomes
on state, the capacitor is composed of the overlap and the gate
effective at the frequency of .
oxide capacitors. Similarly the junction capacitors are functions
The T-Attenuator has slightly different performance from the
of the transistor biasing.
-Attenuator for the maximum attenuation setting. When the
We now can write the maximum attenuation achievable from
isolation is maximum, the series devices have equivalent re-
as
sistances close to and , and the shunt device is com-
pletely on with a very small channel resistance. The size of
the shunt resistance determines the maximum attenuation value
since smaller resistance corresponds to better grounding of the
intermediate node.
Fig. 8 gives the equivalent circuit for the maximum attenua-
tion setting of a T-Attenuator. The T-Attenuator in this condi-
tion is fairly wideband since the intermediate node has a very
small resistance to ground and the capacitors connected to this
node have very small time constants, therefore the transfer func-
tion has very high pole magnitudes. Parasitic capacitors at the
input and output nodes consist only of the junction capacitors,
(10) thus the total parasitic capacitors at these nodes are relatively
DOGAN et al.: ANALYSIS AND DESIGN OF RF CMOS ATTENUATORS 2273

small. Consequently, from a qualitative point of view, this net-

work has a very wide frequency response in the maximum at-
tenuation case. Capacitor values in this network are given in (4),
(5) and (6). As mentioned previously, these capacitors are func-
tions of the biasing of the transistors and therefore are different
in value from the minimum attenuation case.
Assuming that is much smaller than , maximum at-
tenuation for this network from can be approximated as

Fig. 9. Maximum attenuation versus frequency for the 5-Attenuator.

(12)

and the low-frequency gain of the network is given by

(13)

If we assume that the and values are close to each other

and ground termination is ideal, (12) suggests that the gain of
the system increases, or equivalently the attenuation drops with
increasing frequency. However, it is important to realize that
the pole and zero magnitudes for the attenuator are fairly large
given that is 50 and and are small parasitic device
capacitors. Therefore, the frequency response of the attenuator
is flat in a very wide frequency range.
Fig. 9 gives the maximum attenuation of a -Network for
two different IL values. Improving the IL by increasing the se-
ries device size increases the size of in Fig. 7, therefore the
maximum attenuation value at a given frequency degrades as a
result. The flat parts of the curves are as a result of the nonzero Fig. 10. Maximum attenuation versus frequency for the T-Attenuator.
off-resistance of the MOS device. Increasing the size of the de-
vice decreases this leakage resistance while increasing . Con-
sequently, the zero magnitude stays the same in the two curves. device size is increased ten times to improve the maximum at-
This figure also shows the effect of parasitic resistance and in- tenuation by 20 dB, the flatness of the curve persists because
ductance in the ground path, namely at the source terminals of of the reasons given above. We can safely conclude from this
and . The curves suggest that a parasitic resistance of 1 graph that the maximum attenuation is flat in the useful fre-
limits the DC isolation by creating a path from input to the quency range. Effect of parasitic ground resistance and induc-
output, in the path. Isolation degrades 6 dB for each tance is also shown on this plot. Parasitic resistance simply adds
time this parasitic resistance doubles. Similarly, a parasitic in- to the on-resistance of , therefore limits the isolation for rea-
ductance in the ground path causes limited isolation. It causes sons given in this section. If the parasitic resistance is equal to
a low frequency pole which is a function of and in on-resistance, this degradation becomes 6 dB. In the case
the attenuation transfer function and maximum attenuation de- of parasitic inductance, this inductance creates a pole approxi-
grades 20 dB per decade as a result as shown in Fig. 9. mately in the attenuation transfer function.
Fig. 10 gives the maximum attenuation as a function of fre- It is apparent from Figs. 9 and 10 that maximum attenuation is
quency for the T-Attenuators. Five different plots are for three vulnerable to any parasitic elements in the ground path. There-
attenuators with different IL and maximum attenuation settings. fore, careful layout planning is particularly important in these
The curves are flat over a very wide frequency range and even- systems and multiple stages should always be considered for
tually start rising as expected. Even for the case where the shunt adequate isolation.
2274 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 10, OCTOBER 2008

C. Impedance Matching
In this section, we limit our analysis to variations from ideal
matching due to high frequency effects. For this purpose, we
make the assumption that at low frequencies, best possible
matching is achieved between the source impedance and the
input impedance of the attenuator and similarly between the
load impedance and the output impedance of the attenuator. For
instance, at the lowest attenuation setting of the -Attenuator,
best possible matching is in fact not perfect since the source
impedance matches to the sum of on-resistance of the series de-
vice and the load resistance. Therefore, perfect matching cannot
be achieved and we will refer to “best possible matching.”
Given that the block we are dealing with is a wideband
system, the match at low frequencies is resistive. As we move
to higher frequencies, the parasitic capacitors of the devices
start degrading the matching of the system. Since the operating
point of each device in the attenuator depends highly on the
attenuation amount, it is necessary to find a worst-case scenario.
This worst case can be identified as the minimum attenuation Fig. 11. S11 versus series device width for the T and 5-Networks at minimum
setting for both attenuator types since it can easily be seen that attenuation at DC.
when the on-resistance of the series device approaches
zero, the input, output and any internal nodes are shorted to
each other. The total parasitic capacitors at these nodes are
summed up and form a single dominant pole. Therefore, in this
operating condition, the dominant pole magnitude for the S11
response of the attenuators becomes the smallest, limiting the
frequency response of the system.
In light of this conclusion, we now can estimate the input
impedance of the -Network given in Fig. 2 using (A1) and
assuming a small as

(14)

in this equation is given in (1). It is clear from (14) that,

to the first order, the dominant pole magnitude for the input
impedance of the network scales with the total parasitic capaci-
tors in the network that are terminated at the ground. Therefore,
minimizing the capacitors to ground broadens the frequency re-
sponse of the system, as in the minimum IL case. This is partly
achieved by shunting gate capacitors of the series devices to the
Fig. 12. S11 versus frequency for the 5-Network in the minimum attenuation
output using . mode.
Similarly, the input impedance of the T-Network for worst-
case matching in Fig. 3 can be estimated using (A2) and as-
suming a small as device size decreases the channel resistance of the device that is
in between the source and load impedances. The curve for the
(15) T-Attenuator is shifted up since there are two series resistors
in this network. By way of making the series resistor smaller,
This equation verifies that the network has a single dominant the source matches to the load better, improving the matching
pole that is a function of all the parasitic capacitors in the system of the system. However, increasing the device sizes in return
that are terminated at ground in a manner similar to the -Atten- degrades the frequency response of the S11 parameter as shown
uator case. Equation (15) is an approximate result and is valid in Figs. 12 and 13.
in the useful frequency range of the attenuator. We define this Fig. 12 shows that although increasing the series device size
useful frequency range as S11 equal to or better than , to improve the IL of the attenuator improves the low frequency
which is a commonly accepted limit for a reasonable matching S11 response, the pole of the input impedance given by (14)
to the desired impedance. moves to a smaller magnitude. As a result, the frequency corner
Fig. 11 shows the simulated low frequency S11 response of of the -Attenuator degrades as shown in this figure. Similarly,
the T and -Attenuators as a function of the series device width. Fig. 13 shows the S11 response of the T-Network as a function
The trend of the plot is mainly due to the fact that increasing the of frequency. It is also evident from this plot that as the device
DOGAN et al.: ANALYSIS AND DESIGN OF RF CMOS ATTENUATORS 2275

Fig. 14. Circuit schematic of the impedance matching feedback network.

Fig. 13. S11 versus frequency for the T-Network in the minimum attenuation
mode.
signal across the two inputs of the amplifier generates the feed-
back voltage identified as . This feedback voltage is
sizes increase in the network, the corner frequency for adequate then applied back to the attenuator in order for the feedback
matching degrades. Improving the maximum attenuation by 20 to minimize the error signal. Consequently, as varying
dB via increasing the shunt device size ten times reduces the changes the attenuation of the network, the feedback network
frequency corner dramatically as shown in the graph. adjusts the value of to keep the low frequency input
and output impedances of the attenuator block constant and
D. Impedance Matching Feedback Loop equal to value. The same control voltages are applied to the
In order to match to the desired impedance at the input and RF attenuator to get the same attenuation and matching charac-
output ports of the attenuator as the gain of the system varies, teristics.
a feedback system needs to be incorporated in the design. The Applying the control voltage to the shunt device as opposed
feedback senses any variation from the ideal matching condition to the series device has its advantages. First, at the minimum
and forces the system to compensate for the changes. The shunt attenuation setting, the shunt device is driven at the gate with
devices in the attenuator types we analyzed are typically used to 0 V as opposed to the feedback voltage, which settles down to a
compensate for the change in the series device as the signal is nonzero voltage. This limits the additional loss due to the shunt
attenuated. Therefore, while an external control voltage controls devices. Additionally, when the control voltage is less than the
the series device channel resistance, a feedback control voltage threshold voltages of the shunt devices, these devices operate in
controls the channel resistance of the shunt devices. the subthreshold region where their characteristics are exponen-
In order not to disturb the operation of the RF attenuator with tial. Therefore, the attenuator responds in a linear-in-dB fashion
the impedance matching network, a dummy replica attenuator to the control voltage at low attenuation settings, meaning the
is used to sense and correct the impedance via the generation of attenuation in dB increases linearly with the control voltage,
a feedback voltage. The control voltage along with the feedback which is highly desirable for attenuators. This is shown in detail
voltage then can be applied to the RF attenuator to match while below.
attenuating. Linear-in-dB attenuation curve is generally much desired in
Fig. 14 gives the circuit diagram of a RF attenuator with the communication systems. The slope of the attenuation curve usu-
feedback control loop used for matching to the source and load ally determines the resolution that can be achieved in the gain
impedances [6]–[8]. The resistors and form a voltage di- control and if this slope is very high in some regions and very
vision branch from to ground resulting in a DC voltage at low in others, it becomes troublesome to estimate the level of
the negative operational amplifier (opamp) input. This voltage gain control with the control voltage. Especially in high slope
is compared to the voltage at the positive input, which is gen- regions, small variations in the control voltage result in large
erated by the voltage division of the resistor and the equiva- variations in the gain of the system. Overall, a gain curve with
lent DC resistance of the replica attenuator. resistors in the very large and slow regions requires very high dynamic range in
feedback loop are on-chip components with values equal to the the gain control loop, which is not desirable. Once a relatively
input source resistance. Deviation in the values of these resis- linear-in-dB gain control curve is achieved by design, the gain
tors as a result of process drift degrades the impedance matching control loop can easily be calibrated to compensate for varia-
of the RF attenuator. However, S11 is still better than 10 dB tions in the slope.
even with 50% drift in these resistor values. The feedback ampli- In order to find the attenuation equation as a function of the
fier compares the voltages between its two inputs and the error control voltage for the -Network given in Fig. 1(a), we can
2276 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 10, OCTOBER 2008

start by writing the low-frequency equivalent input impedance

of the system. In calculating the input impedance, we will start
out assuming is equal to and is equal to .
Then, using (A4)–(A6), the attenuation equation can be written
as

(16)

where is given by (17), which gives the derivative of the

drain current as a function of the drain-source voltage [2]

(17)

(18)

(19)
(20)

Fig. 15. Attenuation versus control voltage for a 5-Attenuator.

The control voltage is applied to the gate of the shunt tran-
sistors and the value in (19) and (20) is equal to ,
assuming the bias voltages at the input and output are set to 0 V.
The device equation used in (17) is explained in detail in [2].
Logarithm of inverse of (16) gives the attenuation in dB scale.
We can easily find the criteria for linear-in-dB gain control for
the attenuator simply by taking the derivative of dB scale atten-
uation equation. It can be shown that such a condition holds true
when is constant for all
values.
Fig. 15 gives the simulated attenuation of the -Network
as a function of the control voltage. As mentioned previously,
linear-in-dB attenuation is desirable in gain control blocks.
Fig. 15 shows a linear response to the control voltage in the first
25–30 dB attenuation range. In the first parts of the attenuation
curve, the shunt device is in weak and moderate inversion
displaying the exponential characteristics and the series device
is in strong inversion, resulting in a linear gain control curve.
In the latter parts of the attenuation curve, the shunt device
becomes linear and the series device is exponential resulting in
an increased gain change with control voltage.
Fig. 15 omits any frequency and parasitic resistance effects Fig. 16. Attenuation versus control voltage for a T-Attenuator.
in the attenuation curve. First, the feedforward capacitance due
to the series device in the -Attenuator limits the maximum
attenuation at higher frequencies, limiting the tail of the curve the gates of the devices. In a manner similar to the -Attenuator
in Fig. 15 at higher frequencies. This is desirable in most cases case, the control voltage is applied to the shunt device and the
since the nonlinear part of the curve is shifted up resulting in a feedback voltage controls the series devices.
more linear overall curve. With the same assumptions as in the previous section and
Second, on-chip parasitic resistors limit the attenuation curve using (A7)–(A9), we can write the attenuation equation for a
at higher attenuation settings. The most dominant of these re- T-Network as
sistors is the one from the attenuator ground to absolute ground.
If the attenuator is not well grounded, this creates an additional (21)
feedthrough path from the input to output via the shunt devices.
These effects also shift the curve in Fig. 15 up at the higher where is given as similar to (17).
attenuation region. Consequently, when frequency and on-chip Fig. 16 shows the simulated attenuation curve as a function
parasitic effects take effect, the attenuation curve becomes more of the control voltage. The curve is linear in the first part be-
linear as shown in measured attenuator data in Section III. cause of the reasons given for the -Attenuator. Namely, the
In order to find the attenuation curve for the T-Attenuator shunt device in its exponential region gives a linear-in-dB re-
we can do a similar analysis as was done for the -Attenuator. sponse in the first 20 dB of attenuation. In the second part of the
Fig. 1(b) shows the T-Network with the bias voltages applied to curve, unlike the -Attenuator, the gain changes slower with the
DOGAN et al.: ANALYSIS AND DESIGN OF RF CMOS ATTENUATORS 2277

Fig. 17. Two-stage cascaded T-Attenuator circuitry with limited attenuation first stage and regular second stage.

control voltage. This is mainly due to the fact that attenuation

is achieved by the change in the shunt device resistance, and in
the latter parts of the curve in Fig. 16 the shunt device operates
in strong inversion region, slowing the rate of change of the at-
tenuation curve with the control voltage.

III. ATTENUATOR DESIGN EXAMPLE

A. Design Methodology
The analysis of the attenuators in the previous section showed
that with the advancements in CMOS technology, it is possible
to design attenuators with multi-gigahertz frequency corners. It
has also been shown in the literature that -Attenuators with
good IL and isolation can even be designed to work as high as
10 GHz with the technology used in this paper [3]. In the rest
of this publication, we will focus our attention to trying to trade
off available bandwidth with another equally important design Fig. 18. Simulated attenuation versus control voltage for the two stages of the
parameter in attenuators, linearity. attenuator.
It has been shown in [2] that T-Networks in general are more
linear than the -Networks, especially at higher attenuation set- is achieved since M3 and M7 are large devices and have small
tings. It has also been proved in the same work that forcing the on-resistances.
series devices in a T-Network to turn off at higher attenuation
(23)
settings improves the linearity of the network further, since these
devices no longer generate distortion. The attenuator presented (24)
here makes use of this fact along with other design techniques
to trade off bandwidth with linearity. The use of shunt resistors across the series devices forces
Fig. 17 shows the generalized circuit diagram of the proposed these devices to turn off at the maximum attenuation setting
attenuator design. The design consists of two T-stages cascaded for good matching at the input and output ports. As mentioned
and utilizes an asymmetric approach rather than the traditional above, since the series devices are off, they do not contribute any
symmetric approach to attenuator design. In the case of min- distortion when the attenuator moves closer to maximum atten-
imum attenuation, the series devices are on and the shunt devices uation. Furthermore, at maximum attenuation, the shunt devices
turn off. Consequently, the input and the output low frequency are highly linear since their channel is strongly inverted and very
impedances are given by small signal swing is present across their terminals due to their
small on-resistance [2]. Overall, at high attenuation settings, the
(22) attenuator is highly linear. This is desirable for most applica-
tions since high attenuation corresponds to large incident power
if we assume that is much smaller than , and is equal to the receiver.
to , thereby giving adequate matching to the source and load. Although the use of shunt resistors improves the linearity
When the attenuator is in the maximum isolation setting, the when close to the maximum attenuation, this improvement was
series devices turn off, and the input and output impedances can shown to be limited to the last 5–10 dB attenuation range of at-
be given as (23) and (24), respectively, therefore good matching tenuators that have isolation in excess of 30 dB [2]. It is very
2278 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 10, OCTOBER 2008

Fig. 19. Overall attenuator block diagram with RF attenuator and 10X scaled replica attenuators in impedance matching FB loops for the input and output ports.

desirable for such gain control blocks to improve their linearity opamp subtractors were used to generate and .
in the first 5–10 dB attenuation range and stay highly linear in An attenuation curve dependent on a single control voltage was
the rest of the gain range. achieved as a result. The overall attenuation curve with respect
In order to achieve this desired response, the two stages to a single external control voltage, , is also shown in
in Fig. 17 attenuate the signal consecutively rather than con- Fig. 18. Furthermore, the attenuation curve is monotonous and
currently. Initially the first stage starts attenuating, and the mostly independent of kinks in the presence of variation of shift
second stage is in its minimum attenuation mode. In this mode, voltage amplitudes due to process corners.
the second stage is highly linear since the series devices are It can be shown that the overall linearity of two cascaded
strongly inverted and the shunt devices are off. Once the first stages is approximately [12]
stage reaches its maximum attenuation, it is highly linear for the
reasons discussed above and the second stage starts attenuating.
(25)
Maximum attenuation of the first stage in Fig. 17 is lim-
ited to around 12 dB. This is achieved by inserting two resis-
tors of values in shunt with M1 and in series with M3. This equation suggests that the effective linearity of the
Fig. 18 shows the attenuation curve of the first and second stages second stage scales inversely with the attenuation ( ) of the
with respect to and , respectively. In this figure, first stage. Since the signal is attenuated by 12 dB before it
second stage attenuation curve is drawn assuming the first stage reaches the second stage, the linearity of the second stage is
is at maximum setting. The attenuation of the first stage reaches improved by 12 dB. As a result, the linearity of the proposed
its maximum value of 12 dB when reaches around 0.5 V. attenuator design improves within the first 10–12 dB of atten-
The second stage starts attenuating for values of around uation.
0.2 V. In the final design, around 100 mV and 200 mV were Use of resistors to limit the attenuation range of the first stage
subtracted from , respectively, to generate and degrades the frequency response of the attenuator, since the
. Shift voltage values were generated on-chip and simple same attenuation can be achieved using a much smaller shunt
DOGAN et al.: ANALYSIS AND DESIGN OF RF CMOS ATTENUATORS 2279

Fig. 20. Overall attenuator circuitry with control voltage generation.

device that has an on-resistance of . Larger device sizes the drains and sources. Comparison amplifiers were designed to
result in smaller on-resistance for the devices and using them minimize input offset (using circuit and layout techniques such
along with the resistors as given in the design guarantees low as large device sizes and cross-quad and interleaved layout) in
signal voltage or current swing across the devices when the at- order to reduce impedance matching error as a result of the low
tenuator is in maximum attenuation setting. However, this in re- 60 mV comparison voltage.
turn causes larger parasitic capacitors in the circuit, which limits Fig. 20 shows the final attenuator design schematic. Opamps
the frequency response. Furthermore, using T-Networks instead 1 and 2 are used to buffer the shift voltages whereas 3 and 4
of the broader -Networks results in further degradation in fre- generate control voltages, and . The design incor-
quency response. Consequently, the design presented in this sec- porates two interconnected feedback loops and local feedback
tion trades off bandwidth for linearity. loops in the control voltage generation circuitry. Each feedback
Fig. 19 gives the block diagram of the attenuator. The two loop was compensated to prevent any stability problems. Sta-
feedback loops control the impedance of the input and output bility was verified extensively via simulations over all process
separately using replica attenuators and use to and temperature corners. Simulated settling time was less than
match to and . Control voltages are applied to the shunt 1 s from minimum-to-maximum attenuation and vice versa.
devices to obtain a linear-in-dB attenuation control as explained Other design parameters include noise performance and
previously. The replica attenuator equivalent resistances were PSRR. Simulations showed that the noise figure (NF) of the
scaled up by 10X to reduce the die area (smaller devices) and attenuator is equal to the IL at the minimum attenuation mode
power dissipation in the comparison branches. The DC bias and increases by 1 dB per dB of attenuation thereafter. Power
voltage at the input and output of the RF attenuator was set to supply rejection from is generally excellent since the
ground to maximize the overdrive values for the devices signal path does not have a direct connection to the power
and hence minimize the IL. The comparison node voltages at supply. Only path from the power supply is through the control
the opamp input were set to around 60 mV by choosing the voltages, and these have the large gate resistors in front of
resistors in the comparison branches to be 10 k and 500 them which block any leakage of power supply noise from the
(10X scaled). This in return minimizes the resistance offset gate of the devices to the drain or the source. However, the
between the RF and replica attenuators due to DC differences at design is susceptible to any ground noise coupling. Simulations
2280 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 10, OCTOBER 2008

Fig. 21. Chip photograph. (I ,V and V are generated on chip).

Fig. 23. Measured and simulated insertion loss and maximum attenuation
versus frequency.

Fig. 22. Measured and simulated attenuation curves versus control voltage
V for f =100 MHz.

show very little rejection for the ground noise. To overcome

this problem, very careful layout design and good termination
of local ground to common ground is required. Also, with a
differential approach, all supply noise can be rejected with
good matching between differential components.
Fig. 24. Measured and simulated S11 parameter versus control voltage V
B. Experimental Results at 100 MHz, 1 GHz and 2.5 GHz.
The attenuator has been fabricated in a commercially avail-
able 0.13 m digital CMOS technology. The chip measures 3.5 dB from DC to 2.5 GHz. IL flatness is 1 dB in the frequency
700 1000 m with all the bias generation integrated on chip. band of DC-1.5 GHz. The discrepancy from the simulated IL
Measurements were made with cascade probes, a HP8719C is most likely due to on-chip parasitics and modeling errors.
Network Analyzer, a HP8563E Spectrum Analyzer and HP The measured maximum attenuation is around 42 dB and flat
function generators. Fig. 21 shows the attenuator chip photo- with frequency as expected for T-configurations. The three
graph. simulated curves were generated with different parasitic in-
Fig. 22 shows the attenuation curve with the control voltage terconnect resistor values from the attenuator ground to the
when the input is at 100 MHz. Measured attenuation curves actual chip ground. With 0 parasitic interconnect resistor
were quite independent of frequency, except for their higher the designed maximum attenuation is around 50 dB. When
insertion loss at higher frequencies. The attenuation curve is the interconnect resistor is set to 0.5 , simulated maximum
mostly linear-in-dB especially in the first 40 dB of attenuation. attenuation drops down to 42 dB and similarly it drops down
The slight kink in the measurement results is thought to be due to to 36 dB for an interconnect resistor of 1 . To minimize the
the poor choice of shift voltages and the variations in the process interconnect resistors, attenuator ground connections were laid
from typical corner. out by stacking up available metal layers. Process variations and
Fig. 23 gives the minimum IL and maximum attenuation coupling to the output from substrate due to nonzero substrate
with frequency. The IL degrades from 0.9 dB to less than resistance cause additional deviation from the simulated values.
DOGAN et al.: ANALYSIS AND DESIGN OF RF CMOS ATTENUATORS 2281

Fig. 25 shows that the linearity of the attenuator starts de-

grading as the first stage starts attenuating. This is mainly caused
by turning on the shunt device, which starts generating distor-
tion and decreasing the gate overdrive voltage of the series de-
vices, which make them more nonlinear. However, as the gate
overdrive voltage of the shunt device increases, its linearity im-
proves. Moreover, decreasing the gate voltages of the series de-
vices increase their channel resistance further, which cause the
shunt fixed resistors to dominate and limit the distortion genera-
tion in those devices. As a result, the linearity improves again as
the attenuation of the first stage increases to its maximum value.
This process repeats itself for the attenuation range of the second
stage, causing the second dip in the linearity curves. However,
the linearity degradation is limited for the second stage because
of the reasons given above in the circuit description part. As
a result, improvement in distortion performance is observed at
the higher attenuation settings. The distortion performance of
existing attenuators shows and values of less than 10
dBm [3], [4]. With the present approach, the attenuator linearity
is improved at higher attenuation settings allowing increased
Fig. 25. Measured IIP2 and IIP3 results for two tones at 100–101 MHz and
0
1–1.001 GHz with 8 dBm and 3 dBm input power at lower and higher atten- power handling. The 1 dB compression point of the attenuator
uation settings respectively for each tone. was measured to be 2.5 dBm, which is the limit that the atten-
uator can handle.
Fig. 24 is a plot of S11 response of the attenuator at different The total power dissipation for the attenuator was 1.9 mW
attenuation settings and different frequencies. Worst case S11 drawn from a 1.2 V power supply. Table I gives a summary of
is at minimum attenuation setting as explained in the previous the performance spec for the attenuator.
section. Worst case S11 is 8.2 dB at 2.5 GHz for the minimum
IL setting. S22 was measured to be as good as or better than S11 APPENDIX
across all corners.
The input impedance of the -Network given in Fig. 2 is
Fig. 25 gives the distortion performance of the attenuator in
given in (A1) at the bottom of the page.
terms of and for two tones at 100 MHz-101 MHz and
The input impedance of the T-Network given in Fig. 3 is given
1 GHz-1.001 GHz for the two graphs respectively. The input
in (A2) at the bottom of the page, where is given by
power to the attenuator was around 8 dBm for the lower at-
tenuation settings and 3 dBm for the higher attenuation set-
tings. The intermodulation distortion generation follows a sim- (A3)
ilar trend for both the low and high frequency ranges, except
that the linearity of the attenuator is slightly improved at higher The input resistance of the -Network can be given as
frequencies. This is mainly due to the more effective gate boot-
strapping at higher frequencies via the parasitic gate capacitors (A4)
and the 10 k resistors at the gates of the devices. It has been
shown in the literature that modulating the gate of a triode-de- For an ideal match at the input, we can set given in (A4)
vice with the average of the drain and source signal amplitudes equal to . Solving this equation, can be written as a
help linearize the device [5]. It is verified with simulations that function of and as
the two tone separation does not cause any variation in distor-
tion products as long as these tones or the resulting products are
(A5)
within the bandwidth of the attenuator.

(A1)

(A2)
2282 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 10, OCTOBER 2008

TABLE I
ATTENUATOR MEASURED PERFORMANCE SUMMARY

The attenuation of the network at low frequencies can be [10] Y. Tsividis, K. Suyama, and K. Vavelidis, “Simple “reconciliation”
written as MOSFET model valid in all regions,” Electron. Lett., pp. 506–508,
Mar. 1995.
[11] Y. Tsividis, Operation and Modeling of the MOS Transistor. New
(A6) York: McGraw-Hill, 1999.
[12] B. Razavi, RF Microelectonics. Englewood Cliffs, NJ: Prentice-Hall,
1998.
Similarly, attenuation curve equations for a T-Network are [13] R. G. Meyer, “Intermodulation in high-frequency bipolar transistor in-
tegrated-circuit mixers,” IEEE J. Solid-State Circuits, vol. SSC-21, no.
4, pp. 534–537, Aug. 1986.
[14] W. M. C. Sansen and R. G. Meyer, “Distortion in bipolar transistor
variable-gain amplifiers,” IEEE J. Solid-State Circuits, vol. SC-8, no.
4, pp. 275–282, Aug. 1973.
(A7) [15] BSIM3 Version 3 Manual, Final Version. BSIM Research Group, Dept.
(A8) EECS., Univ. California, Berkeley [Online]. Available: http://www-de-
vice.EECS.Berkeley.EDU/~bsim3
[16] R. G. Meyer and P. R. Gray, Analysis and Design of Analog Integrated
(A9) Circuits, 3rd ed. New York: Wiley, 1993.
[17] K. Vavelidis, Y. Tsividis, F. O. Eynde, and Y. Papananos, “Six terminal
MOSFET’s: Modeling and applications in highly linear, electronically
tunable resistors,” IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 4–12,
Jan. 1997.
REFERENCES [18] A. Maxim et al., “A fully integrated 0.13 m CMOS digital low-IF
DBS satellite tuner using a ring oscillator-based frequency synthe-
[1] H. Dogan, R. G. Meyer, and A. M. Niknejad, “A DC-2.5 GHz wide-dy- sizer,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 967–982, May
namic-range attenuator in 0.13 m CMOS technology,” in 2005 VLSI 2007.
Circuits Symp. Dig., pp. 90–93.
[2] H. Dogan and R. G. Meyer, “Intermodulation distortion in CMOS at-
tenuators and switches,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp.
529–539, Mar. 2007.
[3] H. Dogan, R. G. Meyer, and A. M. Niknejad, “A DC-10 GHz
linear-in-dB attenuator in 0.13 m CMOS technology,” in Proc. IEEE Hakan Dogan (S’00–M’06) was born in Malatya,
Custom Integrated Circuits Conf., 2004, pp. 609–612. Turkey, on June 6, 1976. He received the B.S. degree
[4] R. H. Caverly, “Distortion in broad-band gallium arsenide MESFET in electrical engineering from University of Southern
control and switch circuits,” IEEE Microw. Theory Tech., vol. 39, no. California (USC), Los Angeles, in 1999, and the M.S.
4, pp. 713–717, Apr. 1991. and Ph.D. degrees in electrical engineering from the
[5] R. Bayruns et al., “The bootstrapped gate FET (BGFET)—A new con- University of California, Berkeley, in 2001 and 2005,
trol transistor,” in IEEE GaAs IC Symp. Dig., 1995, pp. 136–139. respectively.
[6] R. Kaunisto, P. Korpi, J. Kiraly, and K. Halonen, “A linear-control He is currently with Atheros Communications Inc.,
wide-band CMOS attenuator,” in Proc. IEEE Int. Symp. Circuits and Santa Clara, CA, where he is involved with dual-band
Systems (ISCAS’01), 2001, vol. 4, pp. 458–461. wireless-LAN tranceiver, Bluetooth transceiver and
[7] B. Maoz, “A novel, linear voltage variable MMIC attenuator,” IEEE GPS receiver chipset designs. In the summer of 2000,
Microw. Theory Tech., vol. 38, no. 11, pp. 1675–1683, Nov. 1990. he was with HP Labs, where he was involved with the design of clock and data
[8] H. Kondoh, “DC-50 GHz MMIC variable attenuator with a 30 dB dy- recovery circuits for high speed serial data links. During the summers of 2001
namic range,” in 1988 IEEE MTT-S Dig., New York, NY, Jun. 1988, and 2002, he was with Maxim Integrated Circuits, where he was involved with
pp. 499–502. the design of cable modem tuners and satellite receivers.
[9] M. T. Terrovitis and R. G. Meyer, “Intermodulation distortion in cur- Dr. Dogan is a member of various honor societies. He is the recipient of the
rent-commutating CMOS mixers,” IEEE J. Solid-State Circuits, vol. Analog Devices Outstanding Student Designer Award and the Philip S. Biegler-
35, no. 10, pp. 1461–1473, Oct. 2000. Excellence in Electrical Engineering Award from USC.
DOGAN et al.: ANALYSIS AND DESIGN OF RF CMOS ATTENUATORS 2283

Robert G. Meyer (S’64–M’68–SM’74–F’81) was Ali M. Niknejad (S’93–M’00) received the B.S.E.E.
born in Melbourne, Australia, on July 21, 1942. He degree from the University of California, Los An-
received the B.E., M.Eng.Sci., and Ph.D. degrees geles, in 1994, and the Masters and Ph.D. degrees
in electrical engineering from the University of in electrical engineering from the University of
Melbourne in 1963, 1965, and 1968, respectively. California, Berkeley, in 1997 and 2000. During his
In 1968, he was employed as an Assistant Lecturer graduate studies, he authored ASITIC, a CAD tools
in electrical engineering at the University of Mel- that aids in the simulation and design of passive
bourne. Since September 1968, he has been with the circuit elements such as inductors into silicon
Department of Electrical Engineering and Computer integrated circuits.
Sciences, University of California, Berkeley, where After graduation from Berkeley, he worked in in-
he is now Professor Emeritus and Professor in the dustry focusing on the design and research of analog
Graduate School. His research interests are high-frequency analog integrated RF integrated circuits and devices for wireless communication applications. He
circuit design and device fabrication. He has acted as a consultant on electronic is currently an Associate Professor in the Department of Electrical Engineering
circuit design for numerous companies in the electronics industry. He is a and Computer Science, University of California, Berkeley, and codirector of
coauthor of the book Analysis and Design of Analog Integrated Circuits (Wiley, the Berkeley Wireless Research Center and the BSIM Research Group. His re-
1977, 1984, 1993, 2001), editor of the book Integrated Circuit Operational search interests lie within the area of wireless and broadband communications,
Amplifiers (IEEE Press, 1978), and coeditor of the book Integrated Circuits for including the implementation of integrated communication systems in silicon
Wireless Communications (IEEE Press, 1999). using CMOS, SiGe, and BiCMOS processes. Focus areas of his research include
Dr. Meyer was President of the Solid-State Circuits Council and has been an analog and RF circuits, device physics and modeling, and numerical techniques
Associate Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS and of the in electromagnetics, with an emphasis on the analysis and modeling of active
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. and passive devices at microwave frequencies for IC applications.
Prof. Niknejad has served as an associate editor of the IEEE JOURNAL OF
SOLID-STATE CIRCUITS and is now serving on the TPC for the IEEE ISSCC.
He was a corecipient of the Outstanding Technology Directions Paper Award at
ISSCC 2004 for codeveloping a modeling approach for devices up to 65 GHz.