uA2240C PROGRAMMABLE TIMER/COUNTER

SLFS045 JUNE 1978 REVISED MAY 1988

D D D D D

Accurate Timing From Microseconds to Days Programmable Delays From 1 Time Constant to 255 Time Constants Outputs Compatible With TTL and CMOS Wide Supply-Voltage Range External Sync and Modulation Capability

N PACKAGE (TOP VIEW)

OUTPUTS

description

The uA2240C consists of a time-base oscillator, an 8-bit counter, a control flip-flop, and a voltage regulator. The frequency of the time-base oscillator is set by the time constant of an external resistor and capacitor at R/C and can be synchronized or modulated by signals applied to the modulation input. The output of the time-base section is applied directly to the input of the counter section and also appears at (TIME BASE). TIME BASE may be used to monitor the frequency of the oscillator, to provide an output pulse to other circuitry, or (with the time-base section disabled) to drive the counter input from an external source. The counter input is activated on a negative-going transition. The reset input stops the time-base oscillator and sets each binary output, Q0Q7, and the time-base output to a TTL high level. After resetting, the trigger input starts the oscillator and all Q outputs go low. Once triggered, the uA2240C will ignore any signals at the trigger input until it is reset. The uA2240C timer/counter may be operated in the free-running mode or with output-signal feedback to the reset input for automatic reset. Two or more binary outputs may be connected together to generate complex pulse patterns, or each output may be used separately to provide eight output frequencies. Using two circuits in cascade can provide precise time delays of up to three years. The uA2240C is characterized for operation from 0C to 70C.
AVAILABLE OPTIONS SYMBOLIZATION DEVICE uA2240C PACKAGE SUFFIX N OPERATING TEMPERATURE RANGE 0C to 70C VT max AT 25C 2V

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

VCC REGULATOR TIME BASE R/C MODULATION TRIGGER RESET GND

OUTPUTS

INPUTS

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1988, Texas Instruments Incorporated

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uA2240C PROGRAMMABLE TIMER/COUNTER

SLFS045 JUNE 1978 REVISED MAY 1988

functional block diagram

VCC 16 REG OUT 15

TRIGGER

11

S & R

Voltage Regulator

RESET

10

Time Base Oscillator 7 k 12 12 k R/C 13 T T T S S S

MODULATION

GND

9 14 Time Base Q0 1 Q1 2 Q7 8

= open-collector outputs

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Output voltage: Q0 Q7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Output current: Q0 Q7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Regulator output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Continuous total dissipation at (or below) 25C free-air temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
NOTE 1: Voltage values are with respect to the network ground terminal.

recommended operating conditions

MIN Supply voltage, VCC (see Note 2) Timing resistor Timing capacitor Counter input frequency (Pin 14) Pull-up resistor, time-based output Trigger and reset input pulse voltage Trigger and reset input pulse duration External clock input pulse voltage External clock input pulse duration NOTE 2: For operation with VCC 4.5 V, short regulator output to VCC. 2 2 3 1 4 0.001 0.01 1.5 20 3 NOM MAX 14 10 1000 UNIT V M F MHz k V s V s

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443

uA2240C PROGRAMMABLE TIMER/COUNTER

SLFS045 JUNE 1978 REVISED MAY 1988

electrical characteristics at 25C free-air temperature

PARAMETER Regulator output voltage Modulation input open circuit voltage Trigger threshold voltage High-level trigger current Reset threshold voltage High-level reset current Counter input (time base) threshold voltage Low-level output current, Q0 Q7 High-level output current, Q0 Q7 Supply current TEST CIRCUIT 1 2 1 1 1 1 1 2 2 2 1 1 3 VCC = 5 V, VCC = 15 V, VCC = 5 V, VCC = 15 V, VCC = 5 V, VCC = 5 V, VCC = 5 V, VCC = 5 V, VCC = 5 V, VCC = 5 V, VOL < 0.4 V VOH = 15 V, VCC = 5 V, VCC = 15 V, V+ = 4 V TEST CONDITIONS TRIGGER and RESET open or grounded TRIGGER and RESET open or grounded TRIGGER and RESET open or grounded TRIGGER and RESET open or grounded RESET at 0 V TRIGGER at 2 V, TRIGGER at 0 V TRIGGER at 0 V TRIGGER and RESET open or grounded TRIGGER at 2 V, RESET at 2 V, TRIGGER at 0 V, TRIGGER at 0 V, RESET at 0 V, TRIGGER at 0 V RESET at 5 V RESET at 5 V 1 2 RESET at 0 V MIN 3.9 5.8 2.8 TYP 4.4 6.3 3.5 10.5 1.4 10 1.4 10 1.4 4 0.01 4 13 1.5 15 7 18 mA 2 2 6.8 4.2 MAX UNIT V V V A V A V mA A

operating characteristics at 25C free-air temperature (unless otherwise noted)

PARAMETER Initial error of time base Temperature coefficient of timebase period Supply voltage sensitivity of timebase period Time-base output frequency Propagation delay time Output rise time 2 TEST CIRCUIT 1 1 1 1 VCC = 5 V, TEST CONDITIONS TRIGGER at 5 V, RESET at 0 V VCC = 5 V VCC = 15 V MIN TYP 0.5 200 80 0.08 R = MIN, C = MIN From TRIGGER input From RESET input CL = 10 pF Q0 Q7 130 1 0.8 180 0.3 MAX 5 UNIT % ppm/C %/ V kHz s

TA = 0C to 70C VCC 8 V VCC = 5 V, See Note 3 RL = 3 k k,

ns Output fall time 180 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. This is the time-base period error due only to the uA2240C and expressed as a percentage of nominal (1.00 RC). NOTE 3: Propagation delay time is measured from the 50% point on the leading edge of an input pulse to the 50% point on the leading edge of the resulting change of state at Q0.

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443

uA2240C PROGRAMMABLE TIMER/COUNTER

SLFS045 JUNE 1978 REVISED MAY 1988

PARAMETER MEASUREMENT INFORMATION

VCC R = 10 k (Unless Otherwise Specified) 0.01 F Connected for Operating Characteristics Tests Only

R/C C = 0.1 F (Unless Otherwise Specified) TRIG RESET TIME BASE Q0 20 k Q1 uA2240C

MOD

VCC

REGULATOR Q4 Q5 Q6 Q7

Q2

Q3

Each Q0 Thru Q7 Output Load = 10 k

Figure 1. General Test Circuit

VCC

1 k (Disables Oscillator) 3V 0V Input Signal for Operating Characteristics Tests Only R/C TRIG RESET Time Base Q0 Q1 uA2240C Q2 Q3 Q4 Q5 Q6 Q7 MOD VCC REGULATOR (Open)

Each QO Thru Q7 Output Load = RL

Figure 2. Counter Test Circuit

(Open) V+ = 4 V

R/C TRIG RESET TIME BASE Q0 Q1

MOD

VCC REGULATOR

uA2240C Q2 Q3 Q4

Q5

Q6

Q7

Each QO Thru Q7 Output Load = 10 k These connections may be open or ungrounded for this test.

Figure 3. Reduced-Power Test Circuit (Time Base Disabled)

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443

uA2240C PROGRAMMABLE TIMER/COUNTER

SLFS045 JUNE 1978 REVISED MAY 1988

TYPICAL CHARACTERISTICS
NORMALIZED TIME-BASE PERIOD vs MODULATION INPUT VOLTAGE
2.5

2 Normalize Timing

1.5

RC 0.5 0 1 2 3 4 5 6 Modulation Voltage V

Figure 4

APPLICATION INFORMATION
Figure 5 shows voltage waveforms for typical operation of the uA2240C. If both RESET and TRIGGER are low during power up, the timer/ counter will be in a reset state with all binary (Q) outputs high and the oscillator stopped. In this state, a high level on the trigger input starts the time-base oscillator. The initial negative-going pulse from the oscillator sets the Q outputs to low logic levels at the beginning of the first time-base period. The uA2240C will ignore any further signals at the TRIGGER until after a reset signal is applied to RESET. With TRIGGER low, a high level at the reset input will set Q outputs high and stop the time-base oscillator. If the reset signal occurs while TRIGGER is high, the reset is ignored. If RESET remains high when TRIGGER goes low, the uA2240C will reset.

TRIGGER RESET TBO Q0 Q1 Q7

Figure 5. Timing Diagram of Output Waveform

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443

uA2240C PROGRAMMABLE TIMER/COUNTER

SLFS045 JUNE 1978 REVISED MAY 1988

APPLICATION INFORMATION
In monostable applications of the uA2240C, one or more of the binary outputs will be connected to RESET as shown in Figure 6. The binary outputs are open-collector stages that can be connected together to a common pullup resistor to provide a wired-OR function. The combined output will be low as long as any one of the outputs is low. This type of arrangement can be used for time delays that are integer multiples of the time-base period. For example, if Q5 (25 = 32) only is connected to the reset input, every trigger pulse will generate a 32-period active-low output. Similarly, if Q0, Q4, and Q5 are connected to RESET, each trigger pulse creates a 49-period delay. In astable operation, the uA2240C will free-run from the time it is triggered until it receives an external reset signal. The period of the time-base oscillator is equal to the RC time constant of an external resistor and capacitor connected as shown in Figure 6 when the modulation input is open (approximately 3.5 V internal, (see Figure 4). Under conditions of high supply voltage (VCC > 7 V) and low value of timing capacitor (C < 0.1 F), the pulse duration of the time-base oscillator may be too short to properly trigger the counters. This situation can be corrected by adding a 300-pF capacitor between the time-base output and ground. The time-base output (TBO) is an open-collector output that requires a 20-k pullup resistor in VREG for proper operation. The time-base pin may also be used as an input to the counters for an external timebase or as an active-low inhibit to interrupt counting without resetting. The modulation input varies the ratio of the time-base period to the RC time constant as a function of the DC bias voltage (see Figure 4). It can also be used to synchronize the timer/counter to an external clock or sync signal. The regulator output is used internally to drive the binary counters and the control logic. This terminal can be used to supply voltage to additional uA2240C devices to minimize power dissipation when several timer circuits are cascaded. For circuit operation with an external clock, the regulator output can be used as the VCC input terminal to power down the internal time base and reduce power dissipation. When supply voltages less than 4.5 V are used with the internal time base, VREG should be shorted to VCC.
VCC

16 R 13 RC C 0.1 F 12 11 TRIGGER 10 RESET 4.7 k GND 9 S1 MODULATOR TIME BASE uA2240 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 VCC REGULATOR

15 20 k 14 1 2 3 4 5 6 7 8 Output 10 k RL

Figure 6. Basic Connections for Timing Applications

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