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    4458-542 Vlsi Design Elex

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    uttareshwar shinde
    This document contains instructions for a 12 question exam on VLSI design. It has two sections, with 6 questions each. Students must answer 1 question from Section I and 1 from Section II. Section I covers topics like transmission gates, technology scaling, SRAM, DRAM, VHDL coding, and finite state machines. Section II addresses differences between FPGA and CPLD, SRAM architecture, fault testing, boundary scan techniques, clock distribution, EMI design, and chip input/output pads. The exam has a total of 100 marks and is allotted 3 hours for completion.

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    4458-542 Vlsi Design Elex

    Uploaded by

    uttareshwar shinde
    30 views3 pages
    This document contains instructions for a 12 question exam on VLSI design. It has two sections, with 6 questions each. Students must answer 1 question from Section I and 1 from Section II. Section I covers topics like transmission gates, technology scaling, SRAM, DRAM, VHDL coding, and finite state machines. Section II addresses differences between FPGA and CPLD, SRAM architecture, fault testing, boundary scan techniques, clock distribution, EMI design, and chip input/output pads. The exam has a total of 100 marks and is allotted 3 hours for completion.

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    4458-542 VLSI DESIGN ELEX

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    This document contains instructions for a 12 question exam on VLSI design. It has two sections, with 6 questions each. Students must answer 1 question from Section I and 1 from Section II. Section I covers topics like transmission gates, technology scaling, SRAM, DRAM, VHDL coding, and finite state machines. Section II addresses differences between FPGA and CPLD, SRAM architecture, fault testing, boundary scan techniques, clock distribution, EMI design, and chip input/output pads. The exam has a total of 100 marks and is allotted 3 hours for completion.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    30 views3 pages

    4458-542 Vlsi Design Elex

    Uploaded by

    uttareshwar shinde
    This document contains instructions for a 12 question exam on VLSI design. It has two sections, with 6 questions each. Students must answer 1 question from Section I and 1 from Section II. Section I covers topics like transmission gates, technology scaling, SRAM, DRAM, VHDL coding, and finite state machines. Section II addresses differences between FPGA and CPLD, SRAM architecture, fault testing, boundary scan techniques, clock distribution, EMI design, and chip input/output pads. The exam has a total of 100 marks and is allotted 3 hours for completion.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    Total No. of Questions : 12] SEAT No.

    P734 [Total No. of Pages : 3


    [4458] - 542
    B.E. (Electronics) (Semester - I)
    VLSI DESIGN
    (2008 Course)
    Time : 3 Hours] [Max. Marks :100
    Instructions to the candidates:
    1) Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6 from Section - I & Q.7 or Q.8,
    Q.9 or Q.10, Q.11 or Q.12 from Section - II.
    2) Answers to the two sections should be written in separate answer-books.
    3) Neat diagrams must be drawn wherever necessary.
    4) Figures to the right indicate full marks.
    5) Use of non programmable electronic pocket calculator is allowed.
    6) Assume suitable data, if necessary.

    SECTION - I

    Q1) a) Explain the transmission gate. Design Y = ABC + AD using Transmission


    gates. State the advantages of Transmission gate. [8]
    b) Explain Technology scaling. Describe the various effect of scaling on
    wires, memory, time and architecture. [8]

    OR

    Q2) a) Explain the followings : [8]


    i) Body effect
    ii) Hot electron effect
    b) Explain static and dynamic power dissipation. Derive an expression for
    power delay product. [8]

    Q3) a) Draw and explain SRAM in detail. [8]


    b) Draw and explain 6T RAM cell working. [8]

    OR

    Q4) a) Explain role of memories in PLDs. [8]


    b) Draw and explain DRAM in detail. [8]

    P.T.O.
    Q5) a) Write a VHDL code and Test bench for Full Adder in structural modeling
    style. [9]
    b) Draw FSM state diagram for Mealy sequence detector to detect 11001
    and write aVHDL code for it. [9]

    OR

    Q6) a) What do you meant by metastability? List the solutions and explain any
    one in detail. [8]
    b) Draw FSM and write a VHDL code for a system which has a single bit
    input ‘M’ and two single bit outputs ‘Y’ and ‘Z’. The output of system
    asserted to logic’ l’ to ‘Y’ and logic ‘0’ to ‘Z’ when system detect input
    stream of serial bits . . ..1001 ... or ... 1010. . . respectively. [10]

    SECTION - II

    Q7) a) Differentiate FPGA and CPLD between logic implementation. [8]


    b) With neat schematic, explain the architectural building blocks of FPGA.
    Give limitations of FPGA over CPLD. [8]

    OR

    Q8) a) With suitable schematic, explain Anti-fuse and Flash technologies for
    PLD. [8]
    b) Draw and Explain CMOS architecture of SRAM. [8]

    Q9) a) What are types of Faults? Explain with schematic. What is meant by
    Fault Coverage? [8]
    b) Write a short note on: BIST, JTAG and TAP Controller. [8]

    OR

    Q10)a) What is need of design for testability? What do you meant by Observability
    and Controllability? Explain. [8]
    b) What are objectives of boundary scan techniques? Explain Boundary
    scan in details. [8]

    [4458]-542 2
    Q11)a) What is clock skew and clock jitter? Explain different techniques of
    clock distribution. [9]
    b) Explain: [9]
    i) EMI immune design.
    ii) Off-chip connections.
    iii) Supply and Ground Bounce.

    OR

    Q12)a) Explain the terms: [9]


    i) Switch Box Routing.
    ii) Design Validation.
    iii) Global Routing.
    b) Explain input pad, output pad and 3 stage pad design in a Chip. [9]

    jjj

    [4458]-542 3

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