4458-542 Vlsi Design Elex
4458-542 Vlsi Design Elex
4458-542 Vlsi Design Elex
SECTION - I
OR
OR
P.T.O.
Q5) a) Write a VHDL code and Test bench for Full Adder in structural modeling
style. [9]
b) Draw FSM state diagram for Mealy sequence detector to detect 11001
and write aVHDL code for it. [9]
OR
Q6) a) What do you meant by metastability? List the solutions and explain any
one in detail. [8]
b) Draw FSM and write a VHDL code for a system which has a single bit
input M and two single bit outputs Y and Z. The output of system
asserted to logic l to Y and logic 0 to Z when system detect input
stream of serial bits . . ..1001 ... or ... 1010. . . respectively. [10]
SECTION - II
OR
Q8) a) With suitable schematic, explain Anti-fuse and Flash technologies for
PLD. [8]
b) Draw and Explain CMOS architecture of SRAM. [8]
Q9) a) What are types of Faults? Explain with schematic. What is meant by
Fault Coverage? [8]
b) Write a short note on: BIST, JTAG and TAP Controller. [8]
OR
Q10)a) What is need of design for testability? What do you meant by Observability
and Controllability? Explain. [8]
b) What are objectives of boundary scan techniques? Explain Boundary
scan in details. [8]
[4458]-542 2
Q11)a) What is clock skew and clock jitter? Explain different techniques of
clock distribution. [9]
b) Explain: [9]
i) EMI immune design.
ii) Off-chip connections.
iii) Supply and Ground Bounce.
OR
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