HCPL-7723/0723

50 MBd 2 ns PWD High Speed CMOS Optocoupler

Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product

Description Features
Available in either 8-pin DIP or SO‑8 package style respec- • +5 V CMOS compatibility
tively, the HCPL-7723 or HCPL-0723 optocoupler utilize • High speed: 50 MBd min.
the latest CMOS IC technology to achieve out­standing • 2 ns max. pulse width distortion
speed performance of minimum 50 MBd data rate and
• 22 ns max. prop. delay
2 ns maximum pulse width distortion.
• 16 ns max. prop. delay skew
Basic building blocks of HCPL-7723/0723 are a CMOS
• 10 kV/µs min. common mode rejection
LED driver IC, a high speed LED and a CMOS detector
IC. A CMOS logic input signal controls the LED driver • –40 to 85°C temperature range
IC, which supplies current to the LED. The detector • Safety and regulatory approvals:
IC incorporates an integrated photodiode, a high speed
transimpedance amplifier, and a voltage comparator with UL recognized
an output driver. – 5000 Vrms for 1 min. per UL1577 for HCPL-7723 for
option 020
– 3750 Vrms for 1 min. per UL1577 for HCPL-0723
CSA component acceptance notice #5
Functional Diagram IEC/EN/DIN EN 60747-5-2
– Viorm = 630 Vpeak for HCPL-7723   option 060
**VDD1 1 8 VDD2** – Viorm = 560 Vpeak for HCPL-0723   option 060

VI 2 7 NC*
Applications
IO
NC* 3 6 VO
• Digital fieldbus isolation: CC-Link, DeviceNet, Profibus,
LED1
SDS, Isolated A/D or D/A conversion
GND1 4 5 GND2
• Multiplexed data transmission
SHIELD
• High speed digital input/output
• Computer peripheral interface
* PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT
UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE. • Microprocessor system interface
PIN 7 IS NOT CONNECTED INTERNALLY.
** A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN
PINS 1 AND 4, AND 5 AND 8.

TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT LED1 VO, OUTPUT
H OFF H
L ON L

CAUTION: It is advised that normal static precautions be taken in handling and assembly of
this component to prevent damage and/or degradation, which may be induced by ESD.
Package Outline Drawings
HCPL-7723 8-Pin DIP Package

9.65 ± 0.25 7.62 ± 0.25

(0.380 ± 0.010) (0.300 ± 0.010)

OPTION 060 CODE*

TYPE NUMBER 8 7 6 5 6.35 ± 0.25
(0.250 ± 0.010)
A XXXXV DATE CODE

YYWW

1 2 3 4

1.78 (0.070) MAX.

1.19 (0.047) MAX.

+ 0.076
5° TYP. 0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
3.56 ± 0.13 4.70 (0.185) MAX.
(0.140 ± 0.005)

0.51 (0.020) MIN.

2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
*OPTION 300 AND 500 NOT MARKED.
1.080 ± 0.320 0.65 (0.025) MAX.
(0.043 ± 0.013) NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
2.54 ± 0.25
(0.100 ± 0.010)


HCPL-7723 Package with Gull Wing Surface Mount Option 300

LAND PATTERN RECOMMENDATION

9.65 ± 0.25
1.016 (0.040)
(0.380 ± 0.010)

8 7 6 5

6.350 ± 0.25
10.9 (0.430)
(0.250 ± 0.010)

1 2 3 4

2.0 (0.080)
1.27 (0.050)

1.780 9.65 ± 0.25

(0.070) (0.380 ± 0.010)
1.19 MAX.
(0.047) 7.62 ± 0.25
MAX. (0.300 ± 0.010)
+ 0.076
0.254 - 0.051
3.56 ± 0.13 + 0.003)
(0.140 ± 0.005) (0.010 - 0.002)

1.080 ± 0.320
(0.043 ± 0.013) 0.635 ± 0.25
(0.025 ± 0.010)
0.635 ± 0.130 12° NOM.
2.54
(0.100) (0.025 ± 0.005)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.

HCPL-0723 Small Outline SO-8 Package

LAND PATTERN RECOMMENDATION

8 7 6 5
5.994 ± 0.203
(0.236 ± 0.008)
XXXV
3.937 ± 0.127 YWW TYPE NUMBER 7.49 (0.295)
(0.155 ± 0.005) (LAST 3 DIGITS)
DATE CODE

PIN ONE 1 2 3 4
1.9 (0.075)
0.406 ± 0.076
(0.016 ± 0.003) 1.270 BSC
(0.050) 0.64 (0.025)

* 5.080 ± 0.127 7° 0.432

45° X
(0.200 ± 0.005) (0.017)

3.175 ± 0.127
(0.125 ± 0.005) 0 ~ 7° 0.228 ± 0.025
1.524
(0.009 ± 0.001)
(0.060)

0.203 ± 0.102
(0.008 ± 0.004)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 0.305 MIN.
5.207 ± 0.254 (0.205 ± 0.010) (0.012)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.

OPTION NUMBER 500 NOT MARKED.

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.


Device Selection Guide
8-Pin DIP (300 mil) Small Outline SO-8
HCPL-7723 HCPL-0723

Ordering Information
HCPL-0723 and HCPL-7723 are UL Recognized with 3750 Vrms for 1 minute per UL1577.

   Option
Part RoHS non RoHS Surface Gull Tape UL 5000 Vrms/ IEC/EN/DIN
Number Compliant Compliant Package Mount Wing & Reel 1 Minute rating EN 60747-5-2 Quantity
-000E no option 300 mil DIP-8 50 per tube
-300E -300 X X 50 per tube
-500E -500 X X X 1000 per reel
-020E -020 X 50 per tube
HCPL-7723 -320E -320 X X X 50 per tube
-520E -520 X X X X 1000 per reel
-060E -060 X 50 per tube
-360E -360 X X X 50 per tube
-560E -560 X X X X 1000 per reel
-000E no option SO-8 100 per tube
HCPL-0723 -500E -500 X X X 1500 per reel
-060E -060 X 100 per tube
-560E -560 X X X X 1500 per reel

To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-7723-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN
EN 60747-5-2 Safety Approval and RoHS compliant.
Example 2:
HCPL-0723 to order product of Small Outline SO-8 package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and
RoHS compliant will use ‘–XXXE.’


Solder Reflow Temperature Profile Regulatory Information
300 The HCPL-7723/0723 have been
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK
approved by the following organi-
PEAK
TEMP.
245°C
TEMP. zations:
240°C
PEAK
TEMP. UL
230°C
Recognized under UL1577,
TEMPERATURE (°C)

200
2.5°C ± 0.5°C/SEC.
SOLDERING
160°C 30 TIME
200°C
component recognition program,
150°C SEC.
140°C File E55361.
30
3°C + 1°C/–0.5°C SEC.
CSA
100
PREHEATING TIME Approved under CSA Component
150°C, 90 + 30 SEC. 50 SEC.
Acceptance Notice #5, File
TIGHT
ROOM TYPICAL CA88324.
TEMPERATURE LOOSE

0
IEC/EN/DIN EN 60747-5-2
0 50 100 150 200 250
Approved under:
TIME (SECONDS)
IEC 60747-5-2:1997+A1:2002/
Note: Non-halide flux should be used. EN 60747-5-2:2001+A1:2002/
DIN EN 60747-5-2 (VDE 0884
Teil 2): 2003-01.
Recommended Pb-Free IR Profile (Option 060 only)
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
tp
20-40 SEC.
260 +0/-5 °C
Tp
217 °C
TL
RAMP-UP
TEMPERATURE

3 °C/SEC. MAX. RAMP-DOWN

150 - 200 °C 6 °C/SEC. MAX.
Tsmax
Tsmin
ts tL
PREHEAT 60 to 150 SEC.
60 to 180 SEC.

25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C

Note: Non-halide flux should be used.

Insulation and Safety Related Specifications

  Value
Parameter Symbol 7723 0723 Units Conditions
Minimum External Air Gap L(I01) 7.1 4.9 mm Measured from input terminals to output
(Clearance) terminals, shortest distance through air.
Minimum External Tracking L(I02) 7.4 4.8 mm Measured from input terminals to output
(Creepage) terminals, shortest distance path along body.
Minimum Internal Plastic Gap 0.08 0.08 mm Insulation thickness between emitter and
(Internal Clearance) detector; also known as distance through
insulation.
Tracking Resistance CTI ≥ 175 ≥ 175 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking Index)
Isolation Group IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1)


All Avago data sheets report the creepage and clearance the surface of a printed circuit board between the solder
inherent to the optocoupler component itself. These fillets of the input and output leads must be considered.
dimensions are needed as a starting point for the There are recommended techniques such as grooves
equipment designer when determining the circuit insula- and ribs, which may be used on a printed circuit board
tion requirements. However, once mounted on a printed to achieve desired creepage and clearances. Creepage
circuit board, minimum creepage and clearance require- and clearance distances will also change depending on
ments must be met as specified for individual equipment factors such as pollution degree and insulation level.
standards. For creepage, the shortest distance path along

IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060)

HCPL-7723 HCPL-0723
Description Symbol Option 060 Option 060 Units
Installation classification per DIN VDE 0110/1.89, Table 1
  for rated mains voltage ≤ 150 V rms I-IV I-IV
  for rated mains voltage ≤ 300 V rms I-IV I-III
  for rated mains voltage ≤ 450 V rms I-III
Climatic Classification 55/85/21 55/85/21
Pollution Degree (DIN VDE 0110/1.89) 2 2
Maximum Working Insulation Voltage VIORM 630 560 V peak
Input to Output Test Voltage, Method b* VPR 1181 1050 V peak
  VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
  Partial Discharge < 5 pC
Input to Output Test Voltage, Method a* VPR 945 840 V peak
  VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec,
  Partial Discharge < 5 pC
Highest Allowable Overvoltage* VIOTM 6000 4000 V peak
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values (maximum values allowed in the
event of a failure, also see Thermal Derating curve,
Figure 11)
  Case Temperature TS 175 150 °C
  Input Current IS,INPUT 230 150 mA
  Output Power PS,OUTPUT 600 600 mW
Insulation Resistance at TS, VIO = 500 V RIO ≥ 109 ≥ 109 Ω

*Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations sec-
tion IEC/EN/DIN EN 60747-5-2, for a detailed description.

Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be en-
sured by means of protective circuits.

Note: The surface mount classification is Class A in accordance with CECC 00802.


Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Storage Temperature TS –55 125 °C
Ambient Operating Temperature[1] TA –40 85 °C
Supply Voltages VDD1, VDD2 0 6.0 Volts
Input Voltage VI –0.5 VDD1 +0.5 Volts
Output Voltage VO –0.5 VDD2 +0.5 Volts
Average Output Current IO 10 mA
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile See Solder Reflow Temperature Profile Section

Recommended Operating Conditions

Parameter Symbol Min. Max. Units
Ambient Operating Temperature TA –40 85 °C
Supply Voltages VDD1, VDD2 4.5 5.5 V
Logic High Input Voltage VIH 2.0 VDD1 V
Logic Low Input Voltage VIL 0.0 0.8 V
Input Signal Rise and Fall Times tr, tf 1.0 ms

Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Logic Low Input Supply Current[2] IDD1L 7 10 mA VI = 0 V
Logic High Input Supply Current[2] IDD1H 1.8 3 mA VI = VDD1
Output Supply Current IDD2L 12.5 17.5 mA
IDD2H 12 16.5 mA
Input Current II –10 10 µA
Logic High Output Voltage VOH 4.4 5.0 V IO = –20 µA, VI = VIH
4.0 4.8 V IO = –4 mA, VI = VIH
Logic Low Output Voltage VOL 0 0.1 V IO = 20 µA, VI = VIL
0.5 1.0 V IO = 4 mA, VI = VIL


Switching Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Propagation Delay Time to Logic tPHL 16 22 ns CL = 15 pF CMOS Signal Levels
Low Output[3]
Propagation Delay Time to Logic tPLH 16 22 ns CL = 15 pF CMOS Signal Levels
High Output[3]
Pulse Width PW 20 ns CL = 15 pF CMOS Signal Levels
Maximum Data Rate 50 MBd CL = 15 pF CMOS Signal Levels
Pulse Width Distortion[4] |tPHL - tPLH| |PWD| 1 2 ns CL = 15 pF CMOS Signal Levels
Propagation Delay Skew[5] tPSK 16 ns CL = 15 pF CMOS Signal Levels
Output Rise Time (10% – 90%) tR 8 ns CL = 15 pF CMOS Signal Levels
Output Fall Time (90% - 10%) tF 6 ns CL = 15 pF CMOS Signal Levels
Common Mode Transient Immunity |CMH| 10 15 kV/µs VCM = 1000 V, TA = 25°C,
at Logic High Output[6] VI = VDD1, VO > 0.8 VDD2
Common Mode Transient Immunity |CML| 10 15 kV/µs VCM = 1000 V, TA = 25°C,
at Logic Low Output[6] VI = 0 V, VO < 0.8 V


Package Characteristics
All Typical Specifications are at TA = 25°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Input-Output Momentary –7723 VISO 3750 V rms RH ≤ 50%, t = 1 min,
Withstand Voltage[7,8,9] Option 020 5000 TA = 25°C
–0723 3750
Input-Output Resistance[7] R I-O 10 12 Ω VI-O = 500 V dc
Input-Output Capacitance C I-O 0.6 pF f = 1 MHz
Input Capacitance[10] C I 3.0 pF
Input IC Junction-to-Case –7723 θjci 145 °C/W Thermocouple located at
Thermal Resistance –0723          160 center underside of package
Output IC Junction-to-Case –7723 θjco 145 °C/W
Thermal Resistance –0723 135
Package Power Dissipation PPD 150 mW

Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee functionality.
2. The LED is ON when VI is low and OFF when VI is high.
3. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO sig-
nal. tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO
signal.
4. PWD is defined as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.
5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature
within the recommended operating conditions.
6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum com-
mon mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising
and falling common mode voltage edges.
7. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
8. In accordance with UL1577, each HCPL-0723 is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detec-
tion current limit, II-O ≤ 5 µA). Each HCPL-7723 is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detec-
tion current limit. II-O ≤ 5 µA.)
9. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 entitled
“Optocoupler Input-Output Endurance Voltage.”
10. CI is the capacitance measured at pin 2 (VI).


Application Information Propagation Delay, Pulse-Width Distortion and Propa-
gation Delay Skew
Bypassing and PC Board Layout
Propagation Delay is a figure of merit which describes
The HCPL-7723/0723 optocouplers are extremely easy to how quickly a logic signal propagates through a system
use. No external interface circuitry is required because as illustrated in Figure 3. The propagation delay from low
the HCPL-7723/0723 use high-speed CMOS IC technol- to high (tPLH) is the amount of time required for an input
ogy allowing CMOS logic to be connected directly to the signal to propagate to the output, causing the output to
inputs and outputs. change from low to high. Similarly, the propagation delay
As shown in Figure 1, the only external components from high to low (tPHL) is the amount of time required for
required for proper operation are two bypass capacitors. the input signal to propagate to the output, causing the
Capacitor values should be between 0.01 µF and 0.1 µF. output to change from high to low.
For each capacitor, the total lead length between both
ends of the capacitor and the power-supply pins should
not exceed 20 mm. Figure 2 illustrates the recommended
printed circuit board layout for the HCPL-7723/0723.

VDD1 1 8 VDD2
C1 C2
VI 2 7 NC
YWW
720

NC 3 6 VO

GND1 4 5 GND2

C1, C2 = 0.01 µF TO 0.1 µF

Figure 1. Functional diagram.

VDD1 VDD2

VI
YWW
720

C1 C2
VO

GND1 GND2

C1, C2 = 0.01 µF TO 0.1 µF

Figure 2. Recommended printed circuit board layout.

INPUT 5 V CMOS
VI 50%
0V
tPLH tPHL

VOH
OUTPUT 90% 90%
VO 10% 10% 2.5 V CMOS
VOL

Figure 3. Timing diagram to illustrate propagation delay, tplh and tphl.

10
Pulse-width distortion (PWD) is the difference between As mentioned earlier, tPSK can determine the maximum
tPHL and tPLH and often determines the maximum data parallel data transmission rate. Figure 5 is the timing
rate capability of a transmission system. PWD can be diagram of a typical parallel data application with both
expressed in percent by dividing the PWD (in ns) by the the clock and data lines being sent through the opto-
minimum pulse width (in ns) being transmitted. Typically, couplers. The figure shows data and clock signals at the
PWD on the order of 20-30% of the minimum pulse width inputs and outputs of the optocouplers. In this case the
is tolerable. data is assumed to be clocked off of the rising edge of
the clock.
Propagation delay skew, tPSK, is an important parameter
to consider in parallel data applica­tions where synchro- Propagation delay skew represents the uncertainty of
nization of signals on parallel data lines is a concern. If where an edge might be after being sent through an op-
the parallel data is being sent through a group of op- tocoupler. Figure 5 shows that there will be uncertainty
tocouplers, differences in propagation delays will cause in both the data and clock lines. It is important that these
the data to arrive at the outputs of the optocouplers at two areas of uncertainty not overlap, otherwise the clock
different times. If this difference in propagation delay signal might arrive before all of the data outputs have
is large enough it will determine the maximum rate at settled, or some of the data outputs may start to change
which parallel data can be sent through the optocou- before the clock signal has arrived. From these consid-
plers. erations, the absolute minimum pulse width that can
be sent through optocouplers in a parallel application is
Propagation delay skew is defined as the difference
twice tPSK. A cautious design should use a slightly longer
between the minimum and maximum propagation
pulse width to ensure that any additional uncertainty in
delays, either tPLH or tPHL, for any given group of optocou-
the rest of the circuit does not cause a problem.
plers which are operating under the same conditions (i.e.,
the same drive current, supply voltage, output load, and The HCPL-7723/0723 optocouplers offer the advantage of
operating temperature). As illustrated in Figure 4, if the guaranteed specifications for propagation delays, pulse-
inputs of a group of optocouplers are switched either ON width distortion, and propagation delay skew over the
or OFF at the same time, tPSK is the difference between recommended temperature and power supply ranges.
the shortest propagation delay, either tPLH or tPHL, and
the longest propagation delay, either tPLH or tPHL.

VI 50% DATA

INPUTS
2.5 V,
VO CLOCK
CMOS
tPSK

VI 50%
DATA

OUTPUTS
tPSK
CLOCK
2.5 V,
VO CMOS
tPSK

Figure 4. Timing diagram to illustrate propagation delay skew, tpsk. Figure 5. Parallel data transmission example.
For product information and a complete list of distributors, please go to our website: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0566EN
AV02-0643EN - August 7, 2007