ACPL-M60L

Small Outline, 5 Leads, High CMR, High Speed,

Logic Gate Optocouplers

Data Sheet

Description Features
The ACPL-M60L is an optically coupled gate that com- • Dual Voltage Operation (3.3V/5V)
bines a GaAsP light emitting diode and an integrated • Low power consumption
high gain photo detector. The output of the detector
• 15 kV/µs minimum Common Mode Rejection (CMR)
IC is an open collector Schottky-clamped transistor. The
at VCM = 1000 V (3.3V operating voltage)
internal shield provides a guaranteed common mode
transient immunity specification of 15 kV/µs at 3.3V op- • High speed: 15 MBd typical
eration. • LVTTL/LVCMOS compatible
This unique design provides maximum AC and DC circuit • Low input current capability: 5 mA
isolation while achieving LVTTL/LVCMOS compatibility. • Guaranteed AC and DC performance over tempera-
The optocoupler AC and DC operational parameters are ture: –40˚C to +85˚C
guaranteed from –40˚C to +85˚C, allowing trouble-free
system performance. • Safety approvals; UL, CSA, IEC/EN/DIN EN 60747-5-2
• Surface mountable
These optocouplers are suitable for high speed logic
interfacing, input/output buffering, as line receivers in • Very small, low profile JEDEC Registered package
environments that conventional line receivers cannot outline
tolerate and are recommended for use in extremely high
ground or induced noise environments. Applications
• Isolated line receiver
Functional Diagram
• Computer-peripheral interfaces
• Microprocessor system interfaces
• Digital isolation for A/D, D/A conversion
ANODE 1 6 VCC
• Switching power supply
5 VO • Instrument input/output isolation
• Ground loop elimination
CATHODE 3 4 GND
• Pulse transformer replacement
• Field buses

CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-xxxx is UL Recognized with 3750 Vrms for 1 minute per UL1577 and is approved under CSA Component Ac-
ceptance Notice #5, File CA 88324.
Option
RoHS
Part Number Compliant Package Surface Mount Tape & Reel IEC/EN/DIN EN 60747-5-2 Quantity
ACPL-M60L -000E SO-5 X 100 per tube
-500E X X 1500 per reel

To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry. Combination of Option 020 and Option 060 is not available.
Example 1:
ACPL-M60L-500E to order product of Surface Mount SO-5 in Tape and Reel packaging with RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

Schematic

+ IF ICC
VCC
1 6
IO
VO
5

–
GND
3 4
ACPL-M60L SHIELD

USE OF A 0.1 µF BYPASS CAPACITOR TRUTH TABLE

MUST BE CONNECTED BETWEEN PINS (POSITIVE LOGIC)
6 AND 4 (SEE NOTE 1). LED OUTPUT
ON L
OFF H

2
Package Outline Drawing

ANODE 1 6 VCC

4.4 ± 0.1
M60L 7.0 ± 0.2 5 VOUT
(0.173 ± 0.004)
XXX (0.276 ± 0.008)

CATHODE 3 4 GND

0.4 ± 0.05
(0.016 ± 0.002)

3.6 ± 0.1*
(0.142 ± 0.004)

0.102 ± 0.102 0.216 ± 0.038

2.5 ± 0.1 (0.004 ± 0.004)
(0.098 ± 0.004) (0.0085 ± 0.0015)

7 MAX.
1.27 BSC 0.71 MIN.
(0.050) (0.028)

MAX. LEAD COPLANARITY

= 0.102 (0.004)
DIMENSIONS IN MILLIMETERS (INCHES)
* MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006)

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.

Land Pattern
4.4
(0.17)

1.3
(0.05)
2.5
(0.10)

2.0
(0.080) 0.64
(0.025)
8.27
(0.325)

3
Solder Reflow Temperature Profile

300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK
PEAK
TEMP.
TEMP.
245°C
240°C
PEAK
TEMP.
230°C
TEMPERATURE (°C)

200
2.5°C ± 0.5°C/SEC.
SOLDERING
30 TIME
160°C
150°C SEC. 200°C
140°C
30
3°C + 1°C/–0.5°C SEC.

100
PREHEATING TIME
150°C, 90 + 30 SEC. 50 SEC.

TIGHT
ROOM TYPICAL
TEMPERATURE LOOSE

0
0 50 100 150 200 250

TIME (SECONDS)

Note: Non-halide flux should be used

Recommended PB-Free IR Profile

TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
tp
20-40 SEC.
260 +0/-5 °C
Tp
217 °C
TL
RAMP-UP
TEMPERATURE

3 °C/SEC. MAX. RAMP-DOWN

150 - 200 °C 6 °C/SEC. MAX.
Tsmax
Tsmin
ts tL
PREHEAT 60 to 150 SEC.
60 to 180 SEC.

25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C

Note: Non-halide flux should be used

4
Insulation and Safety Related Specifications
Parameter Symbol Value Units Conditions
Minimum External Air Gap L (I01) ≥ 5 mm Measured from input terminals to output
(Clearance) terminals
Minimum External Tracking Path L (I02) ≥ 5 mm Measured from input terminals to output
(Creepage) terminals
Minimum Internal Plastic Gap 0.08 mm Through insulation distance, conductor to
(Clearance) conductor
Tracking Resistance CTI 175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group (per DIN VDE 0109) IIIa Material Group DIN VDE 0109

Absolute Maximum Ratings (No Derating Required up to 85˚C)

Parameter Symbol Min. Max. Units Note
Storage Temperature TS –55 125 ˚C
Operating Temperature† TA –40 85 ˚C
Average Forward Input Current IF 20 mA 1
Reverse Input Voltage VR 5 V
Input Power Dissipation PI 40 mW
Supply Voltage (1 minute maximum) VCC 7 V
Output Collector Current IO 50 mA
Output Collector Voltage VO 7 V
Output Collector Power Dissipation PO 85 mW
Solder Reflow Temperature Profile See Package Outline Drawings section

Recommended Operating Conditions

Parameter Symbol Min. Max. Units
Input Current, Low Level IFL* 0 250 µA
Input Current, High Level[1] IFH** 5 15 mA
Power Supply Voltage VCC 2.7 3.6 V
4.5 5.5 V
Operating Temperature TA –40 85 ˚C
Fan Out (at RL = 1 kΩ)[1] N 5 TTL Loads
Output Pull-up Resistor RL 330 4 k Ω

*The off condition can also be guaranteed by ensuring that VFL ≤ 0.8 volts.
**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be
used for best performance and to permit at least a 20% LED degradation guardband.

5
Electrical Specifications
Over recommended Operating Condition (TA = –40°C to +85°C , 2.7V ≤ VDD ≤ 3.6V) unless otherwise specified.
All Typicals at VCC = 3.3 V, TA = 25°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
High Level IOH* 4.5 50 µA VCC = 3.3 V, VO = 3.3 V 1
Output Current IF = 250 µA
Input Threshold ITH 3.0 5.0 mA VCC = 3.3 V, VO = 0.6 V,
Current IOL (Sinking) = 13 mA
Low Level VOL* 0.35 0.6 V VCC = 3.3 V, IF = 5 mA 2
Output Voltage IOL (Sinking) = 13 mA
High Level Supply Current ICCH 4.7 7.0 mA IF = 0 mA, VCC = 3.3 V
Low Level Supply Current ICCL 7.0 10.0 mA IF = 10 mA, VCC = 3.3 V
Input Forward VF 1.4 1.5 1.75* V TA = 25˚C, IF = 10 mA 5
Voltage
Input Reverse BVR* 5 V IR = 10 µA
Breakdown Voltage
Input Diode ∆VF/ –1.6 mV/˚C IF = 10 mA
Temperature ∆TA
Coefficient
Input-Output Insulation VISO 3750 VRMS RH ≤ 50%, t = 1 min. 12, 13
Input Capacitance CIN 60 pF f = 1 MHz, VF = 0 V

*The JEDEC Registration specifies 0˚C to +70˚C. Avago specifies –40˚C to +85˚C.

Electrical Specifications
Over recommended temperature (TA = –40°C to +85°C , 4.5V ≤ VDD ≤ 5.5V) unless otherwise specified.
All Typical specification at VCC = 5V, TA = 25 °C
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
High Level IOH 5.5 100 µA VCC = 5.5 V, VO = 5.5 V 1
Output Current IF = 250 µA
Input Threshold ITH 2 5 mA VCC = 5.5 V, IO ≥13 mA,
Current VO = 0.6 V
Low Level VOL 0.4 0.6 V VCC = 5.5 V, IF = 5 mA, 2
Output Voltage IOL (Sinking) = 13 mA
High Level Supply Current ICCH 4 7.5 mA VCC = 5.5 V, IF = 0 mA,
Low Level Supply Current ICCL 6 10.5 VCC = 5.5 V, IF = 10 mA,
Input Forward V­F 1.4 1.5 1.75 V TA = 25°C, IF = 10 mA 5
Voltage 1.3 1.85 IF = 10 mA
Input Reverse BVR 5 IR = 10 µA
Breakdown Voltage
Input Diode ∆VF/∆TA -1.6 mV/°C IF = 10 mA
Temperature
Coefficient
Input-Output Insulation VISO 3750 VRMS RH ≤ 50%, t = 1 min. 12, 13
Input Capacitance CIN 60 pF VF = 0V, f = 1 MHz

*All typicals at TA = 25°C, VCC = 5 V.

6
Switching Specifications
Over recommended temperature (TA = –40˚C to +85˚C), VCC = 3.3 V, IF = 7.5 mA unless otherwise specified.
All Typicals at TA = 25˚C, VCC = 3.3 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Propagation Delay tPLH 90 ns RL = 350 Ω 6, 7, 8 5
Time to High Output CL = 15 pF
Level
Propagation Delay tPHL 75 ns RL = 350 Ω 6, 7, 8 6
Time to Low Output CL = 15 pF
Level
Pulse Width |tPHL – tPLH| 25 ns RL = 350 Ω 9 8
Distortion CL = 15 pF
Propagation Delay tPSK 40 ns RL = 350 Ω
Skew CL = 15 pF
Output Rise Time tr 45 ns RL = 350 Ω
(10-90%) CL = 15 pF
Output Fall Time tf 20 ns RL = 350 Ω
(90-10%) CL = 15 pF

*JEDEC registered data for the 6N137.

Switching Specifications
Over recommended temperature (TA = -40°C to 85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified.
All Typicals at TA = 25˚C, VCC = 5 V.
Parameter Symbol Min. Typ.* Max. Unit Test Conditions Fig.  Note
Propagation Delay tPLH 20 48 75 ns TA = 25°C, RL=350 Ω 6, 7, 8 5
Time to High CL=15pF
Output Level 100 RL=350 Ω, CL=15pF
Propagation Delay tPHL 25 50 75 ns TA = 25°C, RL=350 Ω 6, 7, 8 6
Time to Low CL=15pF
Output Level 100 RL=350 Ω, CL=15pF
Pulse Width |tPHL - tPLH| 3.5 35 ns RL= 350 Ω 9 8
Distortion CL = 15 pF
Propagation tPSK 40 ns RL= 350 Ω
Delay Skew CL = 15 pF
Output Rise Time trise 24 ns RL= 350 Ω
(10%-90%) CL = 15 pF
Output Fall Time tfall 10 ns RL= 350 Ω
(10%-90%) CL = 15 pF

*All typicals at TA = 25°C, VCC = 5 V.

7
 Parameter Sym. Device Min. Typ. Units Test Conditions Fig. Note
Logic High |CMH| ACPL-M60L 15,000 25,000 V/µs |VCM| = 1000 V VCC = 3.3 V, IF = 0 mA, 9 9, 11
Common VO(MIN) = 2 V,
Mode RL = 350 Ω, TA = 25˚C
Transient 10,000 15,000 VCC = 5 V, IF = 0 mA, 9 9, 11
Immunity VO(MIN) = 2 V,
RL = 350 Ω, TA = 25˚C
Logic Low |CML| ACPL-M60L 15,000 25,000 V/µs |VCM| = 1000 V VCC = 3.3 V, IF = 7.5 mA, 9 10, 11
Common VO(MAX) = 0.8 V,
Mode RL = 350 Ω, TA = 25˚C
Transient 10,000 15,000 VCC = 5 V, IF = 7.5 mA, 9 10, 11
Immunity VO(MIN) = 0.8 V,
RL = 350 Ω, TA = 25˚C

Notes:
1. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 20 mA.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 15 mA.
3. Derate linearly above +80˚C free-air temperature at a rate of 2.7 mW/˚C for the SOIC-5 package.
4. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in
Figure 11. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
5. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge
of the output pulse.
6. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge
of the output pulse.
7. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified
test conditions.
8. See test circuit for measurement details.
9. CMH is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state
(i.e., Vo > 2.0 V).
10. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
(i.e., Vo < 0.8 V).
11. For sinusoidal voltages, (|dVCM | / dt)max = πfCMVCM (p-p).
12. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together.
13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS for 1 second (Leakage
detection current limit, II-O ≤ 5 µA).

15 15
VCC = 3.3 V
IOH – HIGH LEVEL OUTPUT CURRENT – µA

V CC = 5.5 V
I OH - HIGH LEVEL OUTPUT CURRENT - µA

VO = 3.3 V V O = 5.5 V
IF = 250 µA I F = 250 µA

10 10

5 5

0 0
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 8 0 100
TA – TEMPERATURE – C T A - TEMPERATURE - °C

Figure 1. Typical high level output current vs. temperature.

8
 ITH – INPUT THRESHOLD CURRENT – mA

ITH – INPUT THRESHOLD CURRENT – mA

12 6
VCC = 3.3 V VCC = 5.0 V
VO = 0.6 V VO = 0.6 V
10 5

8 4
RL = 350 KΩ
6 3 RL = 350 Ω
RL = 1 KΩ RL = 1 kΩ

4 2

2 1
RL = 4 kΩ
RL = 4 KΩ
0 0
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100

TA – TEMPERATURE – C TA – TEMPERATURE – C

Figure 2. Typical input threshold current vs. Temperature

HCPL-M600 fig 13

0.8 0.5
VCC = 3.3 V V CC = 5.5 V
VOL – LOW LEVEL OUTPUT VOLTAGE – V

0.7 IF = 5.0 mA I F = 5.0 mA

V OL - LOW LEVEL OUTPUT VOLTAGE - V

0.6 0.4
I O = 12.8 mA
0.5

0.4 0.3

0.3 IO = 13 mA

0.2 0.2

0.1
0 0.1
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100
T A - TEMPERATURE - °C
TA – TEMPERATURE – °C

Figure 3. Typical low level output voltage vs. temperature.

70 80 1000
VCC = 3.3 V V CC = 5.0 V TA = 25 °C
I OL - LOW LEVEL OUTPUT CURRENT - mA
IOL – LOW LEVEL OUTPUT CURRENT – mA

VOL = 0.6 V V OL = 0.6 V

100
IF
IF – FORWARD CURRENT – mA

60 60
+
10 VF
–

50 40 1.0
I F = 5.0 mA
IF = 5.0 mA
0.1
40 20
0.01

20 0 0.001
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 1.1 1.2 1.3 1.4 1.5 1.6
T A - TEMPERATURE - °C
TA – TEMPERATURE – °C VF – FORWARD VOLTAGE – V

Figure 4. Typical low level output current vs. temperature. Figure 5. Typical input diode forward charac-
teristic.

9
 3.3 V
PULSE GEN. IF
ZO = 50 Ω� 1 VCC 6
tf = tr = 5 ns IF = 7.50 mA
0.1 µF INPUT
RL IF = 3.75 mA
BYPASS IF
OUTPUT VO
5 MONITORING
tPHL tPLH
*CL NODE
INPUT
3 4 OUTPUT
MONITORING
GND VO 1.5 V
NODE RM

*CL IS APPROXIMATELY 15 pF WHICH INCLUDES

PROBE AND STRAY WIRING CAPACITANCE.

PULSE GEN.
Z O = 50 Ω
t f = t r = 5 ns +5 V

IF
1 V CC 6
RL I F = 7.5 mA
0.1µF
BYPASS OUTPUT V O INPUT
5 I F = 3.75 mA
MONITORING IF
NODE
*C L t PHL t PLH
INPUT
MONITORING 3 4
NODE GND OUTPUT
RM VO 1.5 V

*C L IS APPROXIMATELY 15 pF WHICH INCLUDES

PROBE AND STRAY WIRING CAPACITANCE.

Figure 6. Test circuit for tPHL and tPLH.

150 100
VCC = 3.3 V V CC = 5.0 V
IF = 7.5 mA I F = 7.5 mA
120 80
tP – PROPAGATION DELAY – ns

t P - PROPAGATION DELAY - ns

t PHL , R L = 350Ω
tPLH , RL = 350 Ω
90 60

60 40

tPHL , RL = 350 Ω t PLH , R L = 350Ω

30 20

0 0
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100
TA – TEMPERATURE – C T A - TEMPERATURE - °C

Figure 7. Typical propagation delay vs. temperature.

10
 50 40
PWD – PULSE WIDTH DISTORTION – ns VCC = 3.3 V

PWD - PULSE WIDTH DISTORTION - ns

IF = 7.5 mA
40 30
V CC = 5.0 V
I F = 7.5 mA
30 20

RL = 350 Ω R L = 350 kΩ
20 10

10 0

0 -10
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100
TA – TEMPERATURE – C T A - TEMPERATURE - °C

Figure 8. Typical pulse width distortion vs. temperature.

IF

B
1 VCC 6 3.3 V
A VCM (PEAK)
0.1 µF 350 Ω VCM
BYPASS 0V
5 OUTPUT VO SWITCH AT A: IF = 0 mA
VFF 3.3 V CMH
MONITORING VO
NODE VO (MIN.)
4 SWITCH AT B: IF = 7.5 mA
3
GND VO (MAX.)
VO
0.5 V CML

+ –
PULSE
GENERATOR
ZO = 50 Ω

IF

B +5 V
1 VCC 6
0.1 µF 350 Ω VCM (PEAK)
A VCM
BYPASS OUTPUT VO
5 0V
MONITORING SWITCH AT A: IF = 0 mA
VFF NODE
5V CMH
VO VO (MIN.)
3 4
GND SWITCH AT B: IF = 7.5 mA
VO VO (MAX.)
0.5 V CML
+ _
PULSE
GENERATOR
ZO = 50 Ω

Figure 9. Test circuit for common mode transient immunity and typical waveforms.

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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2008 Avago Technologies. All rights reserved. Obsoletes AV01-0273EN
AV02-0891EN - December 18, 2008