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    p3055ldg Niko

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    Алексей Гомонов
    This document provides specifications for an N-channel logic level enhancement mode field effect transistor. The transistor has a drain-source breakdown voltage of 25V, on-state drain current of 12A, and on-state resistance of 50-120mOhms. It is housed in a TO-252 package and is halogen-free and lead-free. Absolute maximum ratings and electrical characteristics are provided including input capacitance, rise/fall times, and forward voltage.

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    p3055ldg Niko

    Uploaded by

    Алексей Гомонов
    18 views4 pages
    This document provides specifications for an N-channel logic level enhancement mode field effect transistor. The transistor has a drain-source breakdown voltage of 25V, on-state drain current of 12A, and on-state resistance of 50-120mOhms. It is housed in a TO-252 package and is halogen-free and lead-free. Absolute maximum ratings and electrical characteristics are provided including input capacitance, rise/fall times, and forward voltage.

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    This document provides specifications for an N-channel logic level enhancement mode field effect transistor. The transistor has a drain-source breakdown voltage of 25V, on-state drain current of 12A, and on-state resistance of 50-120mOhms. It is housed in a TO-252 package and is halogen-free and lead-free. Absolute maximum ratings and electrical characteristics are provided including input capacitance, rise/fall times, and forward voltage.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    18 views4 pages

    p3055ldg Niko

    Uploaded by

    Алексей Гомонов
    This document provides specifications for an N-channel logic level enhancement mode field effect transistor. The transistor has a drain-source breakdown voltage of 25V, on-state drain current of 12A, and on-state resistance of 50-120mOhms. It is housed in a TO-252 package and is halogen-free and lead-free. Absolute maximum ratings and electrical characteristics are provided including input capacitance, rise/fall times, and forward voltage.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    N-Channel Logic Level Enhancement P3055LDG

    NIKO-SEM TO-252 (DPAK)


    Mode Field Effect Transistor
    Halogen-Free & Lead-Free

    D
    PRODUCT SUMMARY
    V(BR)DSS RDS(ON) ID 1. GATE
    2. DRAIN
    25 50mΩ 12A G
    3. SOURCE

    ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)


    PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS
    Gate-Source Voltage VGS ±20 V
    TC = 25 °C 12
    Continuous Drain Current ID
    TC = 100 °C 8 A
    1
    Pulsed Drain Current IDM 45
    Avalanche Energy L = 0.1mH EAS 60
    mJ
    TC = 25 °C 48
    Power Dissipation PD W
    TC = 100 °C 20
    Operating Junction & Storage Temperature Range Tj, Tstg -55 to 150
    1
    °C
    Lead Temperature ( /16” from case for 10 sec.) TL 275

    THERMAL RESISTANCE RATINGS


    THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS
    Junction-to-Case RθJC 3
    Junction-to-Ambient RθJA 75 °C / W
    Case-to-Heatsink RθCS 1
    1
    Pulse width limited by maximum junction temperature.

    ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted)


    LIMITS
    PARAMETER SYMBOL TEST CONDITIONS UNIT
    MIN TYP MAX
    STATIC
    Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = 250µA 25
    V
    Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250µA 0.8 1.2 2.5
    Gate-Body Leakage IGSS VDS = 0V, VGS = ±20V ±250 nA
    VDS = 20V, VGS = 0V 25
    Zero Gate Voltage Drain Current IDSS µA
    VDS = 20V, VGS = 0V, TJ = 125 °C 250
    1
    On-State Drain Current ID(ON) VDS = 10V, VGS = 10V 12 A

    REV 1.0 Feb-19-2009


    1
    N-Channel Logic Level Enhancement P3055LDG
    NIKO-SEM TO-252 (DPAK)
    Mode Field Effect Transistor
    Halogen-Free & Lead-Free

    Drain-Source On-State VGS = 5V, ID = 12A 70 120


    1 RDS(ON) mΩ
    Resistance VGS = 10V, ID = 12A 50 90
    1
    Forward Transconductance gfs VDS = 15V, ID = 12A 16 S
    DYNAMIC
    Input Capacitance Ciss 450
    Output Capacitance Coss VGS = 0V, VDS = 15V, f = 1MHz 200 pF
    Reverse Transfer Capacitance Crss 60
    2
    Total Gate Charge Qg 15
    2 VDS = 0.5V(BR)DSS, VGS = 10V,
    Gate-Source Charge Qgs 2.0 nC
    Gate-Drain Charge
    2
    Qgd ID = 6A 7.0
    2
    Turn-On Delay Time td(on) 6.0
    2
    Rise Time tr VDS = 15V, RL = 1Ω 6.0
    nS
    2
    Turn-Off Delay Time td(off) ID ≅ 12A, VGS = 10V, RGS = 2.5Ω 20
    2
    Fall Time tf 5.0
    SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
    Continuous Current IS 12
    A
    1
    Forward Voltage VSD IF = IS, VGS = 0V 1.5 V
    Reverse Recovery Time trr 30 nS
    Reverse Recovery Charge Qrr 0.043 µC
    1
    Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2%.
    2
    Independent of operating temperature.

    REMARK: THE PRODUCT MARKED WITH “P3055LDG”, DATE CODE or LOT #

    REV 1.0 Feb-19-2009


    2
    N-Channel Logic Level Enhancement P3055LDG
    NIKO-SEM TO-252 (DPAK)
    Mode Field Effect Transistor
    Halogen-Free & Lead-Free

    REV 1.0 Feb-19-2009


    3
    N-Channel Logic Level Enhancement P3055LDG
    NIKO-SEM TO-252 (DPAK)
    Mode Field Effect Transistor
    Halogen-Free & Lead-Free

    REV 1.0 Feb-19-2009


    4

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