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AC6921A8

AC6921A

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0% found this document useful (0 votes)
439 views

AC6921A8

AC6921A

Uploaded by

Rafael Bruno
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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AC6921A Datasheet

AC6921A Datasheet

Zhuhai Jieli Technology Co.,LTD


Version:V1.0

Date:2018.04.20

Copyright © Zhuhai Jieli Technology Co.,LTD. All rights reserved.


AC6921A Datasheet

AC6921A Features
High performance 32-bit RISC CPU
RISC 32-bit CPU
DC-160MHz operation
Support DSP instructions
64Vectored interrupts
4 Levels interrupt priority

Flexible I/O
33 GPIO pins
All GPIO pins can be programmable as input or output individually
All GPIO pins are internal pull-up/pull-down selectable individually
CMOS/TTL level Schmitt triggered input
External wake up/interrupt on all GPIOs

Peripheral Feature
One full speed USB 2.0 OTG controller
One audio interface supports IIS, left adjusted, right adjusted and DSP mode
Four multi-function 16-bit timers, support capture and PWM mode
Three 16-bit PWM generator for motor driving
One 16-bit active parallel port
One full-duplex basic UART
Two full-duplex advanced UART
Three SPI interface supports host and device mode
Two SD Card Host controller
One IIC interface supports host and device mode
One SPDIF receiving interface without analog amplify
One Quadrate decoder
Watchdog
2 Crystal Oscillator
16-bit Stereo DAC with headphone amplifier, SNR >= 95dB
1 channel ADC , SNR >= 90dB
1 channel MIC amplifier
2 channels Stereo analog MUX
14 channels 10-bit ADC
2 channels 8 levels Low Voltage Detector
Power-on reset
Embedded PMU support low power mode

Bluetooth Feature
CMOS single-chip fully-integrated radio and baseband
Compliant with Bluetooth V5.0+BR+EDR+BLE specification

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The information contained herein is the exclusive property of JIELI and shall not be distributed, reproduced, or disclosed in whole or in part without
prior written permission of JIELI.
AC6921A Datasheet

Bluetooth Piconet and Scatternet support


Meet class2 and class3 transmitting power requirement
Support GFSK and π/4 DQPSK all paket types
Provides +2dbm transmitting power
receiver with -89dBm sensitivity
Support a2dp\avctp\avdtp\avrcp\hfp\spp\smp\att\gap\gatt\rfcomm\sdp\l2cap profile

FM Tuner
Support worldwide frequency band 76-108MHz
Fully integrated digital low-IF tuner & frequency synthesizer
Autonomous search tuning
Digital auto gain control (AGC)
Digital adaptive noise cancellation
Programmable de-emphasis (50/75 uS)
Receive signal strength indicator (RSSI)
Radio search in multi-channel simultaneously
Digital volume control

Power Supply
VBAT is 2.2V to 5.5V
VDDIO is 2.2V to 3.6V
RTCVDD is 2.2V to 3.6V

Packages
LQFP48(7mm*7mm)

Temperature
Operating temperature: -20℃ to +70℃
Storage temperature: -65℃ to +150℃

3
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The information contained herein is the exclusive property of JIELI and shall not be distributed, reproduced, or disclosed in whole or in part without
prior written permission of JIELI.
AC6921A Datasheet

1、Pin Definition

1.1 Pin Assignment

Figure 1-1 AC6921A_LQFP48 Package Diagram

4
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The information contained herein is the exclusive property of JIELI and shall not be distributed, reproduced, or disclosed in whole or in part without
prior written permission of JIELI.
AC6921A Datasheet

1.2 Pin Description

Table 1-1 AC6921A_LQFP48 Pin Description

High
PIN I/O
Name Drive Function Other Function
NO. Type
(mA)
CLKOUT0:
UART1TXA:Uart1 Data Out(A);
SPI2CLKA:SPI2 Clock(A);
SD1DAT0B:SD1 Data0(B);
1 PB0 I/O 8 GPIO ALNK_SCLKB:Audio Link Serial
Clock (B);
SD0DAT3B:SD0 Data3(B);
ADC6:ADC Input Channel 6;
Touch0:Touch Input Channel 0;
2 VSSIO P / Ground
3 VBAT P / LDO Power
4 RTCVDD P / RTC Power 3.3v
RTCIO1 RESET1:
5 PR1 I/O 10
(output 0V) ADC12:ADC Input Channel 12;
RTCIO2 RESET2:
6 PR2 I/O 10
(pull up) ADC12:ADC Input Channel 12;
RTCIO3
7 PR3 I/O 10 RESET3:
(pull up)
RESET0:
8 PR0 I/O 10 RTCIO0
OSCO_32K
9 BT_AVDD P / BT Power 1.3v
10 BT_RF P /
11 FMIP I /
12 VSSIO P / Ground
13 BT_OSCI I / BT OSC In
14 BT_OSCO O / BT OSC Out
SD1CLKA:SD1 Clock(A);
SPI1DOB:SPI1 Data Out(B);
UART2RXD:Uart2 Data In(B);
15 PC5 I/O 24 GPIO
IIC_SDA_B:IIC SDA(B);
COM0:LCD COM Output 0;
SEG21:LCD SEG Output21;
SD1CMDA:SD1 Command(A);
16 PC4 I/O 24 GPIO
SPI1CLKB:SPI1 Clock(B);

5
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The information contained herein is the exclusive property of JIELI and shall not be distributed, reproduced, or disclosed in whole or in part without
prior written permission of JIELI.
AC6921A Datasheet

UART2TXD:Uart2 Data Out(B);


IIC_SCL_B:IIC SCL(B);
COM1:LCD COM Output 1;
SEG20:LCD SEG Output20;
SD1DAT0A:SD1 Data0(A);
SPI1DIB:SPI1 Data In(B);
UART0RXC:Uart0 Data In(C);
17 PC3 I/O 24 GPIO TMR3:Timer3 Clock Input;
COM2:LCD COM Output 2;
SEG19:LCD SEG Output19;
ADC10:ADC Input Channel 10;
ALNK_DAT2A:Audio Link Data2(A);
18 PA13 I/O GPIO
SEG13:LCD SEG Output13;
IIC_SDA_C:IIC SDA(C);
UART0TXC:Uart0 Data Out(C);
19 PC2 I/O 24 GPIO
COM3:LCD COM Output 3;
SEG18:LCD SEG Output18;
CAP2:Timer2 Capture;
20 PA12 I/O 24 GPIO ALNK_DAT1A:Audio Link Data1(A);
SEG12:LCD SEG Output12;
IIC_SCL_C:IIC SCL(C);
SD1DAT2A:SD1 Data2(A);
21 PC1 I/O 24 GPIO UART1RXB:Uart1 Data In(B);
COM4:LCD COM Output 4;
SEG17:LCD SEG Output17;
SD1DAT3A:SD1 Data3(A);
UART1TXB:Uart1 Data Out(B);
22 PC0 I/O 24 GPIO
COM5:LCD COM Output 5;
SEG16:LCD SEG Output16;
UART1RXD:Uart1 Data In(D);
USB Negative
SPI2DOB:SPI2 Data Out(B);
23 USBDM I/O 4 Data
IIC_SDA_A:IIC SDA(A);
(pull down)
ADC11:ADC Input Channel 11;
USB Positive UART1TXD:Uart1 Data Out(D);
24 USBDP I/O 4 Data SPI2CLKB:SPI2 Clock(B);
(pull down) IIC_SCL_A:IIC SCL(A);
TMR1:Timer1 Clock Input;
ALNK_DAT0A:Audio Link Data0(A);
25 PA11 I/O 24 GPIO SPI2DIB:SPI2 Data In(B);
SEG11:LCD SEG Output11;
Touch7:Touch Input Channel 7;
SD0DAT1A:SPI0 Data1(A);
26 PA10 I/O 24 GPIO
BT_FREQ:
6
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The information contained herein is the exclusive property of JIELI and shall not be distributed, reproduced, or disclosed in whole or in part without
prior written permission of JIELI.
AC6921A Datasheet

UART2RXB:Uart2 Data In(B);


ADC5:ADC Input Channel 5;
ALNK_LRCKA:Audio Link Word
Select(A);
SEG10:LCD SEG Output10;
SD0DAT2A:SD1 Data2(A);
BT_Priority:
UART2TXB:Uart2 Data Out(B);
27 PA9 I/O 24 GPIO ADC4:ADC Input Channel 4;
ALNK_SCLKA:Audio Link Serial
Clock(A);
SEG9:LCD SEG Output9;
SD0DAT3A:SD0 Data3(A);
Wlan_Active:
UART0RXD:Uart0 Data In(B);
28 PA8 I/O 24 GPIO
ALNK_DAT3A:Audio Link Data3(A);
SEG8:LCD SEG Output8;
Touch15:Touch Input Channel 15;
SD0CLKA:SD0 Clock(A);
BT_Active:
UART0TXD:Uart0 Data Out(D);
TMR0:Timer0 Clock Input;
29 PA7 I/O 24 GPIO
ALNK_MCLKA:ALNK Master
Clock(A);
SEG7:LCD SEG Output7;
Touch14:Touch Input Channel 14;
SD0CMA:SD0 Command(A);
UART0RXA:Uart0 Data In(A);
UART1_RTS:Uart1 Request to send;
30 PA6 I/O 24 GPIO ADC3:ADC Input Channel 3;
IIC_SDA_D:IIC SDA(D);
SEG6:LCD SEG Output6;
Touch13:Touch Input Channel 13;
SD0DAT0A:SD0 Data0(A);
UART0TXA:Uart0 Data Out(A);
UART1_CTS:Uart1 Clear to send;
31 PA5 I/O 24 GPIO ADC2:ADC Input Channel 2;
IIC_SCL_D:IIC SCL(D);
SEG5:LCD SEG Output5;
Touch12:Touch Input Channel 12;
PWM1:Timer1 PWM Output;
32 PA4 I/O 24 GPIO AMUX1R:Simulator Channel1 Right;
ADC1:ADC Input Channel 1;

7
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The information contained herein is the exclusive property of JIELI and shall not be distributed, reproduced, or disclosed in whole or in part without
prior written permission of JIELI.
AC6921A Datasheet

UART2RXA:Uart2 Data In(A);


SEG4:LCD SEG Output4;
Touch11:Touch Input Channel 11;
AMUX1L:Simulator Channel1 Left;
ADC0:ADC Input Channel 0;
33 PA3 I/O 24 GPIO UART2TXA:Uart2 Data Out(A);
SEG3:LCD SEG Output3;
Touch10:Touch Input Channel 10;
PLNK_DAT1:PLNK Data1;
CLKOUT1:
CAP3:Timer3 Capture;
34 PA2 I/O 24 GPIO
UART1RXC:Uart1 Data In(C);
SEG2:LCD SEG Output2;
Touch9:Touch Input Channel 9;
PLNK_SCLK:PLNK Serial Clock;
PWM0:Timer0 PWM Output;
35 PA1 I/O 24 GPIO UART1TXC:Uart1 Data Out(C);
SEG1:LCD SEG Output1;
Touch8:Touch Input Channel 8;
DAC Right
36 DACR O /
Channel
DAC Left
37 DACL O /
Channel
38 DACVDD P / DAC Power
39 VCOM P / DAC Reference
40 DACVSS P / Ground
PLNK_DAT0:PLNK Data0;
MIC:MIC Input Channel;
41 PA0 I/O 24 GPIO
UART0RXB:Uart0 Data In(B);
SEG0:LCD SEG Output0;
42 VDDIO P / IO Power 3.3v
UART0TXB:Uart0 Data Out(B);
AMUX0R:Simulator Channel0 Right;
SPI1DOA:SPI1 Data Out(A);
SD1DAT3B:SD1 Data3(A);
43 PB5 I/O 8 GPIO
ALNK_DAT3B:Audio Link Data3(B);
SD0CLKB:SD0 Clock(B);
ADC9:ADC Input Channel 9;
Touch5:Touch Input Channel 5;
PWM3:Timer3 PWM Output;
44 PB4 I/O 8 GPIO AMUX0L:Simulator Channel0 Left;
SPI1CLKA:SPI1 Clock(A);

8
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The information contained herein is the exclusive property of JIELI and shall not be distributed, reproduced, or disclosed in whole or in part without
prior written permission of JIELI.
AC6921A Datasheet

SD1DAT2B:SD1 Data2(B);
ALNK_DAT2B:Audio Link Data2(B);
SD0CMDB:SD0 Command(B);
ADC8:ADC Input Channel 8;
SPI0_DAT2AB(2):SPI0 Data2(AB);
Touch4:Touch Input Channel 4;
PWM2:Timer2 PWM Output;
UART2RXC:Uart2 Data In(C);
SPI1DIA:SPI1 Data In(A);
SD1DAT1B:SD1 Data1(B);
45 PB3 I/O 8 GPIO ALNK_DAT1B:Audio Link Data1(B);
SD0DAT0B:SD0 Data0(B);
AMUX2R:Simulator Channel2 Right;
SPI0_DAT3AB(3):SPI0 Data3(AB);
Touch3:Touch Input Channel 3;
ALNK_MCLKB:Audio Link Master
Clock(B);
46 PB6 I/O 8 GPIO AMUX2L:Simulator Channel2 Left;
SPI0_DIB(1):SPI0 Data In(B);
Touch6:Touch Input Channel 6;
UART2TXC:Uart2 Data Out(C);
SPI2DIA:SPI2 Data In(A);
SD1CLKB:SD1 Clock(B);
47 PB2 I/O 8 GPIO ALNK_DAT0B:Audio Link Data0(B);
SD0DAT1B:SD0 Data1(B);
SPI0_CLKB:SPI0 Clock(B);
Touch2:Touch Input Channel 2;
TMR2:Timer2 Clock Input;
UART1RXA:Uart1 Data In(A);
SPI2DOA:SPI2 Data Out(A);
SD1CMDB:SD1 Command(B);
48 PB1 I/O 8 GPIO ALNK_LRCKB:Audio Link Word
Select(B);
SD0DAT2B:SD0 Data2(B);
ADC7:ADC Input Channel 7;
Touch1:Touch Input Channel 1;

9
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The information contained herein is the exclusive property of JIELI and shall not be distributed, reproduced, or disclosed in whole or in part without
prior written permission of JIELI.
AC6921A Datasheet

2、Electrical Characteristics

2.1 PMU Characteristics

Table 2-1
Symbol Parameter Min Typ Max Unit Test Conditions
VBAT Voltage Input 2.2 3.7 5.5 V
V3.3 _ 3.3 _ V LDO5V = 5V, 100mA loading
Voltage output
V1.2 _ 1.2 _ V LDO5V = 5V, 50mA loading
V13 Voltage output 1.3 V LDO5V=5V, 100mA loading
VDACVDD DAC Voltage _ 3.1 _ V LDO5V = 5V, 10mA loading
IL3.3 Loading current _ _ 150 mA LDO5V = 5V

2.2 IO Input/Output Electrical Logical Characteristics

Table 2-2
IO input characteristics
Symbol Parameter Min Typ Max Unit Test Conditions
Low-Level Input
VIL -0.3 _ 0.3* VDDIO V VDDIO = 3.3V
Voltage
High-Level Input 0.7*
VIH _ VDDIO+0.3 V VDDIO = 3.3V
Voltage VDDIO
IO output characteristics
Low-Level Output
VOL _ _ 0.33 V VDDIO = 3.3V
Voltage
High-Level Output
VOH 2.7 _ _ V VDDIO = 3.3V
Voltage

2.3 Internal Resistor Characteristics

Table 2-3
Internal Internal
General High
Port Pull-Up Pull-Down Comment
Output Drive
Resistor Resistor

PA0~PA12 1、PR0 default input disable


8mA 24mA 10K 10K
PC0~PC5 2、PR1 default output 0
3、PR2 & PR3 default pull up
PB0~PB6 4mA 8mA 10K 10K 4、USBDM & USBDP default pull
PR0-PR3 8mA 10mA 10K 10K down
5、internal pull-up/pull-down
USBDM resistance | accuracy ±20%
4mA _ 1.5K 15K
USBDP

10
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prior written permission of JIELI.
AC6921A Datasheet

2.4 DAC Characteristics

Table 2-4
Parameter Min Typ Max Unit Test Conditions
Frequency Response 20 _ 20K Hz
THD+N _ -69 _ dB 1KHz/0dB
S/N _ 95 _ dB 10Kohm loading
Crosstalk _ -80 _ dB With A-Weighted Filter
Output Swing 1 Vrms
1KHz/-60dB
Dynamic Range 90 dB 10Kohm loading
With A-Weighted Filter
DAC Output Power 11 _ mW 32ohm loading

2.5 ADC Characteristics

Table 2-5
Parameter Min Typ Max Unit Test Conditions
1KHz/-60dB
Dynamic Range 85 dB 10Kohm loading
With A-Weighted Filter
S/N _ 90 _ dB 1KHz/-60dB
THD+N _ -72 _ dB 10Kohm loading
Crosstalk _ -80 _ dB With A-Weighted Filter

2.6 BT Characteristics

2.6.1 Transmitter

Basic Data Rate Table 2-6


Parameter Min Typ Max Unit Test Conditions

RF Transmit Power 0 4 dBm

RF Power Control Range 20 dB 25℃,


20dB Bandwidth 950 KHz
Power Supply
+2MHz -40 dBm
Voltage=5V
Adjacent Channel -2MHz -38 dBm
2441MHz
Transmit Power +3MHz -44 dBm

-3MHz -35 dBm

11
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The information contained herein is the exclusive property of JIELI and shall not be distributed, reproduced, or disclosed in whole or in part without
prior written permission of JIELI.
AC6921A Datasheet

Enhanced Data Rate Table 2-7


Parameter Min Typ Max Unit Test Conditions

Relative Power 1.2 dB

DEVM RMS 6 %
π/4 DQPSK
25℃,
DEVM 99% 10 %
Modulation Accuracy
DEVM Peak 15 % Power Supply

+2MHz -40 dBm Voltage=5V


Adjacent Channel -2MHz -38 dBm 2441MHz
Transmit Power +3MHz -44 dBm

-3MHz -35 dBm

2.6.2 Receiver

Basic Data Rate Table 2-8


Parameter Min Typ Max Unit Test Conditions

Sensitivity -89 dBm

Co-channel Interference Rejection -13 dB


25℃,
+1MHz +5 dB

-1MHz +2 dB Power Supply

Adjacent Channel +2MHz +37 dB Voltage=5V

Interference Rejection -2MHz +36 dB 2441MHz


+3MHz +40 dB

-3MHz +35 dB

Enhanced Data Rate Table 2-9


Parameter Min Typ Max Unit Test Conditions

Sensitivity -89 dBm

Co-channel Interference Rejection -13 dB


25℃,
+1MHz +5 dB

-1MHz +2 dB Power Supply

Adjacent Channel +2MHz +37 dB Voltage=5V

Interference Rejection -2MHz +36 dB 2441MHz


+3MHz +40 dB

-3MHz +35 dB

12
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prior written permission of JIELI.
AC6921A Datasheet

2.7 FM Receiver Characteristics

Table 2-10
Parameter Min Typ Max Unit Test Conditions
Input Frequency 76 108 MHz
dBμV
Usable Sensitivity 3 4 8 (S+N)/N=26dB
EMF
Adjacent Channel Selectivity 48 dB ± 200kHz
dbμV  Δf1=200 kHz,
IIP3 88
EMF  Δf2=400 kHz
Audio Output Voltage 0 3 V Empty Load
Audio Frequency Response 20 20k Hz DacTest
Audio (S+N)/N 52 dB
Stereo Separation 40 dB
Audio Total Harmonic
0.4 %
Distortion (THD)

13
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The information contained herein is the exclusive property of JIELI and shall not be distributed, reproduced, or disclosed in whole or in part without
prior written permission of JIELI.
AC6921A Datasheet

3、Package Information
3.1 LQFP48(7mm*7mm)

Figure 3-1. AC6921A_LQFP48 Package

14
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prior written permission of JIELI.
AC6921A Datasheet

4、Revision History
Date Revision Description
2018.04.20 V1.0 Initial Release

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prior written permission of JIELI.

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