AC6900A规格书V1 2

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AC6900A Datasheet

AC6900A 芯片规格书

珠海市杰理科技有限公司
版本:V1.2

日期:2017.02.08

版权所有,未经许可,禁止外传
AC6900A Datasheet

AC6900A Features
High performance 32-bit RISC CPU
RISC 32-bit CPU
DC-160MHz operation
Support DSP instructions
64Vectored interrupts
4 Levels interrupt priority

Flexible I/O
41 GPIO pins
All GPIO pins can be programmable as input or output individually
All GPIO pins are internal pull-up/pull-down selectable individually
CMOS/TTL level Schmitt triggered input
External wake up/interrupt on all GPIOs

Peripheral Feature
One full speed USB 2.0 OTG controller
One audio interface supports IIS, left adjusted, right adjusted and DSP mode
Four multi-function 16-bit timers, support capture and PWM mode
Four 16-bit PWM generator for motor driving
One 16-bit active parallel port
One full-duplex basic UART
Two full-duplex advanced UART
Two SPI interface supports host and device mode
Two SD Card Host controller
One IIC interface supports host and device mode
Watchdog
2 Crystal Oscillator
16-bit Stereo DAC, SNR > 92dB
3 channels Stereo ADC , SNR > 92dB
1 channel MIC amplifier
Embedded headphone amplifier
3 channels Stereo analog MUX
16 channels 10-bit ADC
2 channels 4 levels Low Voltage Detector
Built in Cap Sense Key controller
Power-on reset
Embedded PMU

Bluetooth Feature
CMOS single-chip fully-integrated radio and baseband
Compliant with Bluetooth V4.2+BR+EDR+BLE specification

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prior written permission of JIELI.
AC6900A Datasheet

Bluetooth Piconet and Scatternet support


Meet class2 and class3 transmitting power requirement
Provides +2dbm transmitting power
receiver with -85dBm sensitivity
Support a2dp\avctp\avdtp\avrcp\hfp\spp\smp\att\gap\gatt\rfcomm\sdp\l2cap profile

FM Tuner
Support worldwide frequency band 76-108MHz
Fully integrated digital low-IF tuner & frequency synthesizer
Autonomous search tuning
Digital auto gain control (AGC)
Digital adaptive noise cancellation
Programmable de-emphasis (50/75 uS)
Receive signal strength indicator (RSSI)
Digital volume control

Power Supply
LDOIN is 4.5V to 5.5V
VBAT is 3.3V to 5.5V
VDDIO is 3.0V to 3.6V

Packages
LQFP64_7x7mm

Temperature
Operating temperature: -40℃ to +85℃
Storage temperature: -65℃ to +150℃

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prior written permission of JIELI.
AC6900A Datasheet

一、引脚定义

1.1 引脚分配

图 1-1 AC6900A_LQFP64 引脚分配图

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prior written permission of JIELI.
AC6900A Datasheet

1.2 引脚描述

表 1-1 AC6900A_LQFP64 引脚描述

PIN I/O Drive


Name Function Other Function
NO. Type (mA)

SEG5:LCD SEG Output5;


UART0TXA:Uart0 Data Out(A);
Touch12:Touch Input Channel 12;
1 PA5 I/O 16 GPIO
ADC2:ADC Input Channel 2;
IIC_SCL_D:IIC SCL(D);
Wakeup9:Port Interrupt /Wakeup 9;
2 PGND P / Ground
3 SW P / DCDC Switch pin
4 VBAT P / LDO Power
5 LDOIN P / Charge Power 5v
6 VDC15 P / BT Power 1.5v
7 VDDIO P / IO Power 3.3v
8 RTCVDD P / RTC Power 3.3v
9 PR1 I/O 16 RTCIO1 ADC12:ADC Input Channel 12;
10 PR2 I/O 16 RTCIO2 ADC13:ADC Input Channel 13;
11 PR3 I/O 16 RTCIO3 OSC12MO
12 OSCI I / OSC32KI
13 PR0 I/O 16 RTCIO0 OSC32KO
14 VSS P / Ground
15 BT_AVDD P / Power 1.5v
16 BT_RF P /
17 AVSS P / Ground
18 BTXOSCI I / OSC In
19 BTXOSCO O / OSC Out
COM0:LCD COM Output 0;
SEG21:LCD SEG Output21;
SD1CLKA:SD1 Clk(A);
20 PC5 I/O 16 GPIO PAPWR:PAP Write;
SPI1DOB:SPI1 Data Out(B);
UART2RXD:Uart2 Data In(D)
IIC_SDA_B:IIC SDA(B);
COM1:LCD COM Output 1;
21 PC4 I/O 16 GPIO
SEG20:LCD SEG Output20;

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prior written permission of JIELI.
AC6900A Datasheet

SD1CMDA:SD1 Command(A);
PAPRD:PAP Read;
SPI1CLKB:SPI1 Clk(B);
UART2TXD:Uart2 Data Out(D);
IIC_SCL_B:IIC SCL(B);
COM2:LCD COM Output 2;
SEG19:LCD SEG Output19;
SD1DAT0A:SD1 Data0(A);
22 PC3 I/O 16 GPIO
PAPD7:PAP Data 7;
SPI1DIB:SPI1 Data In(B);
UART0RXC:Uart0 Data In(C)
COM3:LCD COM Output 3;
SEG18:LCD SEG Output18;
SD1DAT1A:SD1 Data1(A);
23 PC2 I/O 16 GPIO PAPD6:PAP Data 6;
SPI2DIB:SPI2 Data In(B);
UART0TXC:Uart0 Data Out(C);
CAP1:Timer1 Capture;
COM4:LCD COM Output 4;
SEG17:LCD SEG Output17;
SD1DAT2A:SD1 Data2(A);
24 PC1 I/O 16 GPIO
PAPD5:PAP Data 5;
SPI2DOB:SPI2 Data Out(B);
UART1RXB:Uart1 Data In(B);
COM5:LCD COM Output 5;
SEG16:LCD SEG Output16;
SD1DAT3A:SD1 Data3(A);
25 PC0 I/O 16 GPIO
PAPD4:PAP Data 4;
SPI2CLKB:SPI2 Clk(B);
UART1TXB:Uart1 Data Out(B);
SEG15:LCD SEG Output15;
CAP2:Timer2 Capture;
UART0RXD:Uart0 Data In(D)
26 PA15 I/O 16 GPIO LNA_EN:
ALNK_MCLKA:Audio Link
Master Clk(A);
IIC_SDA_B:IIC SDA(B);
SEG14:LCD SEG Output14;
TMR1:Timer1 Clock Input;
UART0TXD:Uart0 Data Out(D);
27 PA14 I/O 16 GPIO
PA_EN:
ALNK_DAT3A:Audio Link
Data3(A);

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The information contained herein is the exclusive property of JIELI and shall not be distributed, reproduced, or disclosed in whole or in part without
prior written permission of JIELI.
AC6900A Datasheet

IIC_SCL_C:IIC SCL(C);
Wakeup4:Port Interrupt /Wakeup 4;
28 VDDIO P / IO Power 3.3v
29 USBDM I/O 4 USB Negative Data ISP_DI:
30 USBDP I/O 4 USB Positive Data ISP_DO:
SEG13:LCD SEG Output13;
SD0CLKA:SD0 Clk(A);
31 PA13 I/O 16 GPIO
ALNK_DAT2A:Audio Link
Data2(A);
SEG12:LCD SEG Output12;
SD0CMDA:SD0 Command(A);
32 PA12 I/O 16 GPIO
ALNK_DAT1A:Audio Link
Data1(A);
SEG11:LCD SEG Output11;
SD0DAT0A:SD0 Data0(A);
33 PA11 I/O 16 GPIO
ALNK_DAT0A:Audio Link
Data0(A);
SEG10:LCD SEG Output10;
SD0DAT1A:SD0 Data1(A);
UART2RXB:Uart2 Data In(B);
ADC5:ADC Input Channel 5;
34 PA10 I/O 16 GPIO
ALNK_LRCKA:Audio Link
Clk(A);
PAPD3:PAP Data3;
Wakeup3:Port Interrupt /Wakeup 3;
SEG9:LCD SEG Output9;
SD0DAT2A:SD0 Data2(A);
UART2TXB:Uart2 Data Out(B);
35 PA9 I/O 16 GPIO ADC4:ADC Input Channel 4;
ALNK_SCLKA:Audio Link
Clk(A);
PAPD2:PAP Data2;
SEG8:LCD SEG Output8;
SD0DAT3A:SD0 Data3(A);
36 PA8 I/O 16 GPIO Touch15:Touch Input Channel 15;
PAPD1:PAP Data1;
Wakeup2:Port Interrupt /Wakeup 2;
SEG7:LCD SEG Output7;
Touch14:Touch Input Channel 14;
37 PA7 I/O 16 GPIO
TMR0:Timer0 Clock Input;
PAPD0:PAP Data0;
38 PA6 I/O 16 GPIO SEG6:LCD SEG Output6;

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prior written permission of JIELI.
AC6900A Datasheet

UART0RXA:Uart0 Data In(A);


Touch13:Touch Input Channel 13;
ADC3:ADC Input Channel 3;
IIC_SDA_D:IIC SDA(D);
SEG5:LCD SEG Output5;
UART0TXA:Uart0 Data Out(A);
Touch12:Touch Input Channel 12;
39 PA5 I/O 16 GPIO
ADC2:ADC Input Channel 2;
IIC_SCL_D:IIC SCL(D);
Wakeup9:Port Interrupt /Wakeup 9;
SEG4:LCD SEG Output4;
AMUX1R:Simulator Channel1
Right;
40 PA4 I/O 16 GPIO Touch11:Touch Input Channel 11;
ADC1:ADC Input Channel 1;
UART2RXA:Uart2 Data In(A);
PWM1:Timer1 PWM Output;
SEG3:LCD SEG Output3;
AMUX1L:Simulator Channel 1
Left;
Touch10:Touch Input Channel 10;
41 PA3 I/O 16 GPIO ADC0:ADC Input Channel 0;
UART2TXA:Uart2 Data Out(A);
ISP_CLK:
Wakeup8:Port Interrupt /Wakeup
8;
SEG2:LCD SEG Output2;
AMUX0R:Simulator Channel0
Right;
42 PA2 I/O 16 GPIO
Touch9:Touch Input Channel 9;
CAP3:Timer3 Capture;
UART1RXC:Uart1 Data In(C);
SEG1:LCD SEG Output1;
AMUX0L:Simulator Channel0
left;
43 PA1 I/O 16 GPIO
Touch8:Touch Input Channel 8;
PWM0:Timer0 PWM Output;
UART1TXC:Uart1 Data Out(C);
44 PA0 I/O 16 GPIO SEG0:LCD SEG Output0;
45 PB13 I/O 16 GPIO MIC
46 DACR O / DAC Right Channel
47 DACL O / DAC Left Channel

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prior written permission of JIELI.
AC6900A Datasheet

48 DACVDD P / DAC Power


49 VCOM P / DAC Reference
50 DACVSS P / DAC Ground
51 FMVSS PI /
52 FMIP I /
53 HPVDD P /
AMUX2R:Simulator Channel2
Right;
NFCRX:NFC Data In
54 PB12 I/O 24 GPIO Touch7:Touch Input Channel 7;
ADC11:ADC Input Channel 11;
SPI1DOA:SPI1 Data Out(A);
SD0CLKB:SD0 Clk(B);
AMUX2L : Simulator Channel2
Left;
NFCTX:NFC Data Out
Touch6:Touch Input Channel 6;
55 PB11 I/O 24 GPIO ADC10:ADC Input Channel 10;
SPI1CLKA:SPI1 Clk(A);
SD0CMDB:SD0 Command(B);
Wakeup13:Port Interrupt /Wakeup
13;
UART2RXC:Uart2 Data In(C);
Touch5:Touch Input Channel 5;
ADC9:ADC Input Channel 9;
56 PB10 I/O 24 GPIO
SPI1_DIA:SPI1 Data In(A);
SD0DAT0B:SD0 Data0(B);
CAP0:Timer0 Capture;
UART2TXC:Uart2 Data Out(C);
ADC8:ADC Input Channel 8;
CLKOUT1:Clk Out1;
57 PB9 I/O 24 GPIO
SD0DAT1B:SD0 Data1(B);
Wakeup12:Port Interrupt /Wakeup
12;
PWM2:Timer2 PWM Output;
SPI0_DAT3AB:SPI0 Data 3(AB);
SFC _DAT3AB:SFC Data 2(AB);
58 PB3 I/O 24 GPIO SD1DAT1B:SD1 Data1(B);
ALNK_DAT1B : Audio Link
Data1(B);
Touch3:Touch Input Channel 3;
59 PB8 I/O 24 GPIO SFC_CLKB:SFC Clock(B);

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prior written permission of JIELI.
AC6900A Datasheet

SPI0_CLKB:SPI0 Clock(B);
ADC7:ADC Input Channel 7;
SD0DAT2B:SD0 Data2(B);

SPI2DIA:SPI2 Data In(A);


SD1CLKB:SD1 Clk(B);
ALNK_DAT0B:Audio Link
60 PB2 I/O 24 GPIO Data0(B);
Touch2:Touch Input Channel 2;
Wakeup11:Port Interrupt /Wakeup
11;
SFC _DOB(0):SFC Data Out0(B);
SPI0_DOB(0):SPI0 Data Out0(B);
UART0RXB:Uart0 Data In(B);
61 PB7 I/O 24 GPIO
ADC6:ADC Input Channel 6;
TMR3:Timer3 Clock Input;
SD0DAT3B:SD0 Data3(B);
TMR2:Timer2 Clock Input;
UART1RXA:Uart1 Data In(A);
SPI2DOA:SPI2 Data Out(A);
62 PB1 I/O 24 GPIO SD1CMDB:SD1 Command(B);
ALNK_LRCKB : Audio Link
Clk(B);
Touch1:Touch Input Channel 1;
SFC _CSB:SFC Chip Select(B);
SPI0_CSB:SPI0 Chip Select(B);
UART0TXB:Uart0 Data Out(B);
63 PB6 I/O 24 GPIO
ALNK_MCLKB : Audio Link
Master Clk(B);

CLKOUT1:Clk Out1;
UART1TXA:Uart1 Data Out(A);
SPI2CLKA:SPI2 Clk(A);
SD1DAT0B:SD1 Data0(B);
64 PB0 I/O 24 GPIO ALNK_SCLKB:Audio Link
Clk(B);
Touch0:Touch Input Channel 0;
Wakeup10:Port Interrupt /Wakeup
10;

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prior written permission of JIELI.
AC6900A Datasheet

二、电气特性

2.1 PMU 电压、电流特性

表 2-1
符号 参数 最小 典型 最大 单位 测试条件
LDOIN Voltage Input 4.5 5 5.5 V _
VBAT Voltage Input 3 3.7 5.5 V
V3.3 _ 3.3 _ V LDO5V = 5V, 100mA loading
Voltage output
V1.2 _ 1.2 _ V LDO5V = 5V, 50mA loading
V1.5 Voltage output 1.5 V LDO5V=5V, 100mA loading
VDACVDD DAC Voltage _ 3.1 _ V LDO5V = 5V, 10mA loading
IL3.3 Loading current _ _ 150 mA LDO5V = 5V

2.2 IO 输入、输出高低逻辑特性

表 2-2
IO 输入特性
符号 参数 最小 典型 最大 单位 测试条件
Low-Level Input
VIL -0.3 _ 0.3* VDDIO V VDDIO = 3.3V
Voltaget
High-Level Input 0.7*
VIH _ VDDIO+0.3 V VDDIO = 3.3V
Voltage VDDIO
IO 输出特性
Low-Level Output
VOL _ _ 0.33 V VDDIO = 3.3V
Voltaget
High-Level Output
VOH 2.7 _ _ V VDDIO = 3.3V
Voltaget

2.3 IO 输出能力、上下拉电阻特性

表 2-3
Port 口 普通输出 强输出 上拉电阻 下拉电阻 备注
PA0~PA15
串接 200 欧
PB13 1、PA3 default pulldown
电阻(寄存 16mA 10K 60K
PC0~PC5 2、PB6 default pullup
器可控制)
PR0-PR3 3、PR0 output 0
PB0~PB12 8mA 24mA 10K 60K 4、内部上下拉阻抗因工艺波动差
USBDM 异,可能存在±20%的偏差
4mA _ 1.5K 15K
USBDP

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prior written permission of JIELI.
AC6900A Datasheet

2.4 DAC 特性

参数 最小 典型 最大 单位 测试条件
Frequency Response 20 _ 200000 Hz
THD+N _ -71 _ dB 1KHz/0dB
S/N _ 93 _ dB 10Kohm loading
Crosstalk _ -90 _ dB With A-Weighted Filter
Output Swing 1.08 Vrms
1KHz/-60dB
Dynamic Range 93 dB 10Kohm loading
With A-Weighted Filter
DAC Output Power _ >11 _ mW 32ohm loading

2.5 ADC 特性

参数 最小 典型 最大 单位 测试条件
1KHz/-60dB
Dynamic Range 93 dB 10Kohm loading
With A-Weighted Filter
S/N _ 92 _ dB 1KHz/-60dB
THD+N _ -75 _ dB 10Kohm loading
Crosstalk _ -80 _ dB With A-Weighted Filter

2.6 BT 特性

表 2-4

参数 最小 典型 最大 单位 测试条件
Maximum Output Power _ 2 _ dBm _
RMS DEVM _ 5.3 _ %
PEAK DEVM _ 12 _ %
Maximum output power
99% DEVM _ 8 _ %
EDR Relative Power _ -1.4 _ dB
BDR Sensitivity _ -84 _ dBm BER=0.001
EDR Sensitivity _ -86 _ dBm BER=0.0001

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prior written permission of JIELI.
AC6900A Datasheet

三、封装

3.1 LQFP64_7*7

图 3-1 AC6900A_LQFP64_7X7mm 封装图

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prior written permission of JIELI.
AC6900A Datasheet

四、版本信息
日期 版本号 描述
2016.12.08 V1.0 原始版本
2016.12.22 V1.1 规范统一蓝牙 4.2 版本格式
2017.02.08 V1.2 修改 FMVDD 为 HPVDD

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prior written permission of JIELI.

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