Introduction To Electrical Engineering

INTRODUCTION TO
ELECTRICAL ENGINEERING
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the oxford series in electrical and computer engineering
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Allen and Holberg, CMOS Analog Circuit Design
Bobrow, Elementary Linear Circuit Analysis, 2nd Edition
Bobrow, Fundamentals of Electrical Engineering, 2nd Edition
Burns and Roberts, Introduction to Mixed Signal IC Test and Measurement
Campbell, The Science and Engineering of Microelectronic Fabrication
Chen, Analog & Digital Control System Design
Chen, Digital Signal Processing
Chen, Linear System Theory and Design, 3rd Edition
Chen, System and Signal Analysis, 2nd Edition
DeCarlo and Lin, Linear Circuit Analysis, 2nd Edition
Dimitrijev, Understanding Semiconductor Devices
Fortney, Principles of Electronics: Analog & Digital
Franco, Electric Circuits Fundamentals
Granzow, Digital Transmission Lines
Guru and Hiziroğlu, Electric Machinery and Transformers, 3rd Edition
Hoole and Hoole, A Modern Short Course in Engineering Electromagnetics
Jones, Introduction to Optical Fiber Communication Systems
Krein, Elements of Power Electronics
Kuo, Digital Control Systems, 3rd Edition
Lathi, Modern Digital and Analog Communications Systems, 3rd Edition
Martin, Digital Integrated Circuit Design
McGillem and Cooper, Continuous and Discrete Signal and System Analysis, 3rd Edition
Miner, Lines and Electromagnetic Fields for Engineers
Roberts and Sedra, SPICE, 2nd Edition
Roulston, An Introduction to the Physics of Semiconductor Devices
Sadiku, Elements of Electromagnetics, 3rd Edition
Santina, Stubberud, and Hostetter, Digital Control System Design, 2nd Edition
Sarma, Introduction to Electrical Engineering
Schaumann and Van Valkenburg, Design of Analog Filters
Schwarz, Electromagnetics for Engineers
Schwarz and Oldham, Electrical Engineering: An Introduction, 2nd Edition
Sedra and Smith, Microelectronic Circuits, 4th Edition
Stefani, Savant, Shahian, and Hostetter, Design of Feedback Control Systems, 3rd Edition
Van Valkenburg, Analog Filter Design
Warner and Grung, Semiconductor Device Electronics
Wolovich, Automatic Control Systems
Yariv, Optical Electronics in Modern Communications, 5th Edition
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INTRODUCTION TO
Mulukutla S. Sarma
Northeastern University
New York Oxford

OXFORD UNIVERSITY PRESS
2001
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Oxford University Press
Oxford New York

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Library of Congress Cataloging-in-Publication Data

Sarma, Mulukutla S., 1938–
Introduction to electrical engineering / Mulukutla S. Sarma
p. cm. — (The Oxford series in electrical and computer engineering)
ISBN 0-19-513604-7 (cloth)
1. Electrical engineering. I. Title. II. Series.
TK146.S18 2001
621.3—dc21 00-020033
Acknowledgments—Table 1.2.2 is adapted from Principles of Electrical Engineering (McGraw-Hill Series in Electrical Engineering), by Peyton Z.
Peebles Jr. and Tayeb A. Giuma, reprinted with the permission of McGraw-Hill, 1991; figures 2.6.1, 2.6.2 are adapted from Getting Started with
MATLAB 5: Quick Introduction, by Rudra Pratap, reprinted with the permission of Oxford University Press, 1998; figures 4.1.2–4.1.5, 4.2.1–4.2.3,
4.3.1–4.3.2, are adapted from Electric Machines: Steady-State Theory and Dynamic Performance, Second Edition, by Mulukutla S. Sarma, reprinted
with the permission of Brooks/Cole Publishing, 1994; figure 4.6.1 is adapted from Medical Instrumentation Application and Design, by John G. Webster,
reprinted with the permission of John Wiley & Sons, Inc., 1978; table 4.6.1 is adapted from “Electrical Safety in Industrial Plants,” IEEE Spectrum, by
Ralph Lee, reprinted with the permission of IEEE, 1971; figure P5.3.1 is reprinted with the permission of Fairchild Semiconductor Corporation; figures
5.6.1, 6.6.1, 9.5.1 are adapted from Electrical Engineering: Principles and Applications, by Allen R. Hambley, reprinted with the permission of Prentice
Hall, 1997; figure 10.5.1 is adapted from Power System Analysis and Design, Second Edition, by Duncan J. Glover and Mulukutla S. Sarma, reprinted
with the permission of Brooks/Cole Publishing, 1994; figures 11.1.2, 13.2.10 are adapted from Introduction to Electrical Engineering, Second Edition,
by Clayton Paul, Syed A. Nasar, and Louis Unnewehr, reprinted with the permission of McGraw-Hill, 1992; figures E12.2.1(a,b), 12.2.2–12.2.5, 12.2.9–
12.2.10, 12.3.1–12.3.3, 12.4.1, E12.4.1, P12.1.2, P12.4.3, P12.4.8, P12.4.12, 13.1.1–13.1.8, 13.2.1–13.2.9, 13.2.11–13.2.16, 13.3.1–13.3.3, E13.3.2,
13.3.4, E13.3.3, 13.3.5–13.3.6 are adapted from Electric Machines: Steady-State Theory and Dynamic Performance, Second Edition, by Mulukutla S.
Sarma, reprinted with the permission of Brooks/Cole Publishing, 1994; figure 13.3.12 is adapted from Communication Systems Engineering, by John G.
Proakis and Masoud Salehi, reprinted with the permission of Prentice Hall, 1994; figures 13.4.1–13.4.7, E13.4.1(b), 13.4.8–13.4.12, E13.4.3, 13.4.13,
13.6.1 are adapted from Electric Machines: Steady-State Theory and Dynamic Performance, Second Edition, by Mulukutla S. Sarma Brooks/Cole
Publishing, 1994; figures 14.2.8, 14.2.9 are adapted from Electrical Engineering: Concepts and Applications, Second Edition, by A. Bruce Carlson and
David Gisser, reprinted with the permission of Prentice Hall, 1990; figure 15.0.1 is adapted from Communication Systems, Third Edition, by A. Bruce
Carlson, reprinted with the permission of McGraw-Hill, 1986; figures 15.2.15, 15.2.31, 15.3.11 are adapted from Communication Systems Engineering,
by John G. Proakis and Masoud Salehi, reprinted with the permission of Prentice Hall, 1994; figures 15.2.19, 15.2.27, 15.2.28, 15.2.30, 15.3.3, 15.3.4,
15.3.9, 15.3.10, 15.3.20 are adapted from Principles of Electrical Engineering (McGraw-Hill Series in Electrical Engineering), by Peyton Z. Peebles
Jr. and Tayeb A. Giuma, reprinted with the permission of McGraw-Hill, 1991; figures 16.1.1–16.1.3 are adapted from Electric Machines: Steady-State
Theory and Dynamic Performance, Second Edition, by Mulukutla S. Sarma, reprinted with the permission of Brooks/Cole Publishing, 1994; table
16.1.3 is adapted from Electric Machines: Steady-State Theory and Dynamic Performance, Second Edition, by Mulukutla S. Sarma, reprinted with the
permission of Brooks/Cole Publishing, 1994; table 16.1.4 is adapted from Handbook of Electric Machines, by S. A. Nasar, reprinted with the permission
of McGraw-Hill, 1987; and figures 16.1.4–13.1.9, E16.1.1, 16.1.10–16.1.25 are adapted from Electric Machines: Steady-State Theory and Dynamic
Performance, Second Edition, by Mulukutla S. Sarma, reprinted with the permission of Brooks/Cole Publishing, 1994.
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Printing (last digit): 10 9 8 7 6 5 4 3 2 1
Printed in the United States of America

on acid-free paper
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To my grandchildren
Puja Sree
Sruthi Lekha
Pallavi Devi
***
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and those to come
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CONTENTS
List of Case Studies and Computer-Aided Analysis xiii

Preface xv
Overview xxi
PART 1 ELECTRIC CIRCUITS
1 Circuit Concepts 3
1.1 Electrical Quantities 4
1.2 Lumped-Circuit Elements 16
1.3 Kirchhoff’s Laws 39
1.4 Meters and Measurements 47
1.5 Analogy between Electrical and Other Nonelectric Physical Systems 50
1.6 Learning Objectives 52
1.7 Practical Application: A Case Study—Resistance Strain Gauge 52
Problems 53
2 Circuit Analysis Techniques 66

2.1 Thévenin and Norton Equivalent Circuits 66
2.2 Node-Voltage and Mesh-Current Analyses 71
2.3 Superposition and Linearity 81
2.4 Wye–Delta Transformation 83
2.5 Computer-Aided Circuit Analysis: SPICE 85
2.6 Computer-Aided Circuit Analysis: MATLAB 88
2.8 Practical Application: A Case Study—Jump Starting a Car 92
Problems 94
3 Time-Dependent Circuit Analysis 102

3.1 Sinusoidal Steady-State Phasor Analysis 103
3.2 Transients in Circuits 125
3.3 Laplace Transform 142
3.4 Frequency Response 154
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3.5 Computer-Aided Circuit Simulation for Transient Analysis, AC Analysis, and

Frequency Response Using PSpice and PROBE 168
3.6 Use of MATLAB in Computer-Aided Circuit Simulation 173
3.8 Practical Application: A Case Study—Automotive Ignition System 178
Problems 179
4 Three-Phase Circuits and Residential Wiring 198

4.1 Three-Phase Source Voltages and Phase Sequence 198
4.2 Balanced Three-Phase Loads 202
4.3 Measurement of Power 208
4.4 Residential Wiring and Safety Considerations 212
4.6 Practical Application: A Case Study—Physiological Effects of Current and
Electrical Safety 216
Problems 218
PART 2 ELECTRONIC ANALOG AND DIGITAL SYSTEMS
5 Analog Building Blocks and Operational Amplifiers 223

5.1 The Amplifier Block 224
5.2 Ideal Operational Amplifier 229
5.3 Practical Properties of Operational Amplifiers 235
5.4 Applications of Operational Amplifiers 244
5.6 Practical Application: A Case Study—Automotive Power-Assisted Steering
System 257
Problems 258
6 Digital Building Blocks and Computer Systems 268

6.1 Digital Building Blocks 271
6.2 Digital System Components 295
6.3 Computer Systems 316
6.4 Computer Networks 320
6.6 Practical Application: A Case Study—Microcomputer-Controlled
Breadmaking Machine 325
Problems 326
7 Semiconductor Devices 339

7.1 Semiconductors 339
7.2 Diodes 340
7.3 Bipolar Junction Transistors 358
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CONTENTS ix
7.4 Field-Effect Transistors 367

7.5 Integrated Circuits 378
7.7 Practical Application: A Case Study—Electronic Photo Flash 380
Problems 380
8 Transistor Amplifiers 393

8.1 Biasing the BJT 394
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8.2 Biasing the FET 395

8.3 BJT Amplifiers 399
8.4 FET Amplifiers 405
8.5 Frequency Response of Amplifiers 409
8.7 Practical Application: A Case Study—Mechatronics: Electronics Integrated
with Mechanical Systems 414
Problems 415
9 Digital Circuits 422

9.1 Transistor Switches 423
9.2 DTL and TTL Logic Circuits 427
9.3 CMOS and Other Logic Families 431
9.5 Practical Application: A Case Study—Cardiac Pacemaker, a Biomedical
Engineering Application 438
Problems 439
PART 3 ENERGY SYSTEMS
10 AC Power Systems 451

10.1 Introduction to Power Systems 452
10.2 Single- and Three-Phase Systems 455
10.3 Power Transmission and Distribution 460
10.5 Practical Application: A Case Study—The Great Blackout of 1965 466
Problems 468
11 Magnetic Circuits and Transformers 471

11.1 Magnetic Materials 472
11.2 Magnetic Circuits 475
11.3 Transformer Equivalent Circuits 479
11.4 Transformer Performance 486
11.5 Three-Phase Transformers 490
11.6 Autotransformers 492
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x CONTENTS

11.8 Practical Application: A Case Study—Magnetic Bearings for Space
Technology 494
Problems 495
12 Electromechanics 505
12.1 Basic Principles of Electromechanical Energy Conversion 505
12.2 EMF Produced by Windings 514
12.3 Rotating Magnetic Fields 522
12.4 Forces and Torques in Magnetic-Field Systems 526
12.5 Basic Aspects of Electromechanical Energy Converters 539
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12.7 Practical Application: A Case Study—Sensors or Transducers 541
Problems 542
13 Rotating Machines 553

13.1 Elementary Concepts of Rotating Machines 553
13.2 Induction Machines 563
13.3 Synchronous Machines 582
13.4 Direct-Current Machines 594
13.6 Practical Application: A Case Study—Wind-Energy-Conversion
Systems 610
Problems 612
PART 4 INFORMATION SYSTEMS
14 Signal Processing 625

14.1 Signals and Spectral Analysis 626
14.2 Modulation, Sampling, and Multiplexing 640
14.3 Interference and Noise 649
14.5 Practical Application: A Case Study—Antinoise Systems, Noise
Cancellation 658
Problems 659
15 Communication Systems 666

15.1 Waves, Transmission Lines, Waveguides, and Antenna Fundamentals 670
15.2 Analog Communication Systems 685
15.3 Digital Communication Systems 710
15.5 Practical Application: A Case Study—Global Positioning Systems 731
Problems 732
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CONTENTS xi
PART 5 CONTROL SYSTEMS
16 Basic Control Systems 747

16.1 Power Semiconductor-Controlled Drives 748
16.2 Feedback Control Systems 779
16.3 Digital Control Systems 805
16.5 Practical Application: A Case Study—Digital Process Control 815
Problems 816
Appendix A: References 831

Appendix B: Brief Review of Fundamentals of Engineering
(FE) Examination 833
Appendix C: Technical Terms, Units, Constants, and Conversion
Factors for the SI System 835
Appendix D: Mathematical Relations 838
Appendix E: Solution of Simultaneous Equations 843
Appendix F: Complex Numbers 846
Appendix G: Fourier Series 847
Appendix H: Laplace Transforms 851
Index 855
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LIST OF CASE STUDIES AND
COMPUTER-AIDED ANALYSIS
Case Studies
1.7 Practical Application: A Case Study—Resistance Strain Gauge 52
2.8 Practical Application: A Case Study—Jump Starting a Car 92
3.8 Practical Application: A Case Study—Automotive Ignition System 178
4.6 Practical Application: A Case Study—Physiological Effects of Current and Electrical Safety
216
5.6 Practical Application: A Case Study—Automotive Power-Assisted Steering System 257
6.6 Practical Application: A Case Study—Microcomputer-Controlled
Breadmaking Machine 325
7.7 Practical Application: A Case Study—Electronic Photo Flash 380
8.7 Practical Application: A Case Study—Mechatronics: Electronics Integrated with Mechanical
Systems 414
9.5 Practical Application: A Case Study—Cardiac Pacemaker, a Biomedical Engineering
Application 438
10.5 Practical Application: A Case Study—The Great Blackout of 1965 466
11.8 Practical Application: A Case Study—Magnetic Bearings for Space Technology 494
12.7 Practical Application: A Case Study—Sensors or Transducers 541
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13.6 Practical Application: A Case Study—Wind-Energy-Conversion Systems 610

14.5 Practical Application: A Case Study—Antinoise Systems, Noise Cancellation 658
15.5 Practical Application: A Case Study—Global Positioning Systems 731
16.5 Practical Application: A Case Study—Digital Process Control 815
Computer-Aided Analysis
2.5 Computer-Aided Circuit Analysis: SPICE 85
2.6 Computer-Aided Circuit Analysis: MATLAB 88
3.5 Computer-Aided Circuit Simulation for Transient Analysis, AC Analysis, and Frequency
Response Using PSpice and PROBE 168
3.6 Use of MATLAB in Computer-Aided Circuit Simulation 173
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PREFACE
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I. OBJECTIVES
The purpose of this text is to present a problem-oriented introductory survey text for the ex-
traordinarily interesting electrical engineering discipline by arousing student enthusiasm while
addressing the underlying concepts and methods behind various applications ranging from con-
sumer gadgets and biomedical electronics to sophisticated instrumentation systems, computers,
and multifarious electric machinery. The focus is on acquainting students majoring in all branches
of engineering and science, especially in courses for nonelectrical engineering majors, with the
nature of the subject and the potentialities of its techniques, while emphasizing the principles.
Since principles and concepts are most effectively taught by means of a problem-oriented course,
judicially selected topics are treated in sufficient depth so as to permit the assignment of adequately
challenging problems, which tend to implant the relevant principles in students’ minds.
In addition to an academic-year (two semesters or three quarters) introductory course
traditionally offered to non-EE majors, the text is also suitable for a sophomore survey course
given nowadays to electrical engineering majors in a number of universities. At a more rapid pace
or through selectivity of topics, the introductory course could be offered in one semester to either
electrical and computer engineering (ECE) or non-EE undergraduate majors. Although this book
is written primarily for non-EE students, it is hoped that it will be of value to undergraduate ECE
students (particularly for those who wish to take the Fundamentals of Engineering examination,
which is a prerequisite for becoming licensed as a Professional Engineer), to graduate ECE
students for their review in preparing for qualifying examinations, to meet the continuing-
education needs of various professionals, and to serve as a reference text even after graduation.
II. MOTIVATION
This text is but a modest attempt to provide an exciting survey of topics inherent to the electrical
and computer engineering discipline. Modern technology demands a team approach in which
electrical engineers and nonelectrical engineers have to work together sharing a common technical
vocabulary. Nonelectrical engineers must be introduced to the language of electrical engineers,
just as the electrical engineers have to be sensitized to the relevance of nonelectrical topics.
The dilemma of whether electrical engineering and computer engineering should be separate
courses of study, leading to distinctive degrees, seems to be happily resolving itself in the direction
of togetherness. After all, computers are not only pervasive tools for engineers but also their
product; hence there is a pressing need to weave together the fundamentals of both the electrical
and the computer engineering areas into the new curricula.
An almost total lack of contact between freshmen and sophomore students and the Department
of Electrical and Computer Engineering, as well as little or no exposure to electrical and computer
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xvi PREFACE
engineering, seems to drive even the academically gifted students away from the program. An
initial spark that may have motivated them to pursue electrical and computer engineering has to
be nurtured in the early stages of their university education, thereby providing an inspiration to
continue.
This text is based on almost 40 years of experience teaching a wide variety of courses to
electrical as well as non-EE majors and, more particularly, on the need to answer many of the
questions raised by so many of my students. I have always enjoyed engineering (teaching, research,
and consultation); I earnestly hope that the readers will have as much fun and excitement in using
this book as I have had in developing it.
III. PREREQUISITES AND BACKGROUND

The student will be assumed to have completed the basic college-level courses in algebra,
trigonometry, basic physics, and elementary calculus. A knowledge of differential equations
is helpful, but not mandatory. For a quick reference, some useful topics are included in the
appendixes.
IV. ORGANIZATION AND FLEXIBILITY

The text is developed to be student-oriented, comprehensive, and up to date on the subject with
necessary and sufficient detailed explanation at the level for which it is intended. The key word
in the organization of the text is flexibility.
The book is divided into five parts in order to provide flexibility in meeting different
circumstances, needs, and desires. A glance at the Table of Contents will show that Part 1 concerns
itself with basic electric circuits, in which circuit concepts, analysis techniques, time-dependent
analysis including transients, as well as three-phase circuits are covered. Part 2 deals with
electronic analog and digital systems, in which analog and digital building blocks are considered
along with operational amplifiers, semiconductor devices, integrated circuits, and digital circuits.
Part 3 is devoted to energy systems, in which ac power systems, magnetic circuits and
transformers, principles of electromechanics, and rotating machines causing electromechanical
energy conversion are presented. Part 4 deals with information systems, including the underlying
principles of signal processing and communication systems. Finally, Part 5 presents control sys-
tems, which include the concepts of feedback control, digital control, and power semiconductor-
controlled drives.
The text material is organized for optimum flexibility, so that certain topics may be omitted
without loss of continuity when lack of time or interest dictates.
V. FEATURES
1. The readability of the text and the level of presentation, from the student’s viewpoint,
are given utmost priority. The quantity of subject matter, range of difficulty, coverage of topics,
numerous illustrations, a large number of comprehensive worked-out examples, and a variety of
end-of-chapter problems are given due consideration, to ensure that engineering is not a “plug-in”
or “cookbook” profession, but one in which reasoning and creativity are of the highest importance.
2. Fundamental physical concepts, which underlie creative engineering and become the most
valuable and permanent part of a student’s background, have been highlighted while giving due
attention to mathematical techniques. So as to accomplish this in a relatively short time, much
thought has gone into rationalizing the theory and conveying in a concise manner the essential
details concerning the nature of electrical and computer engineering. With a good grounding
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PREFACE xvii
in basic concepts, a very wide range of engineering systems can be understood, analyzed, and
devised.
3. The theory has been developed from simple beginnings in such a manner that it can readily
be extended to new and more complicated situations. The art of reducing a practical device to an
appropriate mathematical model and recognizing its limitations has been adequately presented.
Sufficient motivation is provided for the student to develop interest in the analytical procedures
to be applied and to realize that all models, being approximate representations of reality, should
be no more complicated than necessary for the application at hand.
4. Since the essence of engineering is the design of products useful to society, the end
objective of each phase of preparatory study should be to increase the student’s capability to
design practical devices and systems to meet the needs of society. Toward that end, the student
will be motivated to go through the sequence of understanding physical principles, processes,
modeling, using analytical techniques, and, finally, designing.
5. Engineers habitually break systems up into their component blocks for ease of under-
standing. The building-block approach has been emphasized, particularly in Part II concerning
analog and digital systems. For a designer using IC blocks in assembling the desired systems,
the primary concern lies with their terminal characteristics while the internal construction of the
blocks is of only secondary importance.
6. Considering the world of electronics today, both analog and digital technologies are given
appropriate coverage. Since students are naturally interested in such things as op amps, integrated
circuits, and microprocessors, modern topics that can be of great use in their career are emphasized
in this text, thereby motivating the students further.
7. The electrical engineering profession focuses on information and energy, which are the
two critical commodities of any modern society. In order to bring the message to the forefront for
the students’ attention, Parts III, IV, and V are dedicated to energy systems, information systems,
and control systems, respectively. However, some of the material in Parts I and II is critical to the
understanding of the latter.
An understanding of the principles of energy conversion, electric machines, and energy
systems is important for all in order to solve the problems of energy, pollution, and poverty that
face humanity today. It can be well argued that today’s non-EEs are more likely to encounter
electromechanical machines than some of the ECEs. Thus, it becomes essential to have sufficient
breadth and depth in the study of electric machines by the non-ECEs.
Information systems have been responsible for the spectacular achievements in communica-
tion in recent decades. Concepts of control systems, which are not limited to any particular branch
of engineering, are very useful to every engineer involved in the understanding of the dynamics
of various types of systems.
8. Consistent with modern practice, the international (SI) system of units has been used
throughout the text. In addition, a review of units, constants and conversion factors for the SI
system can be found in Appendix C.
9. While solid-state electronics, automatic control, IC technology, and digital systems have
become commonplace in the modern EE profession, some of the older, more traditional topics,
such as electric machinery, power, and instrumentation, continue to form an integral part of the
curriculum, as well as of the profession in real life. Due attention is accorded in this text to such
topics as three-phase circuits and energy systems.
10. Appendixes provide useful information for quick reference on selected bibliography for
supplementary reading, the SI system, mathematical relations, as well as a brief review of the
Fundamentals of Engineering (FE) examination.
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xviii PREFACE
11. Engineers who acquire a basic knowledge of electric circuits, electronic analog and digital
circuits, energy systems, information systems, and control systems will have a well-rounded
background and be better prepared to join a team effort in analyzing and designing systems.
Therein lies the justification for the Table of Contents and the organization of this text.
12. At the end of each chapter, the learning objectives of that chapter are listed so that the
student can check whether he or she has accomplished each of the goals.
13. At the very end of each chapter, Practical Application: A Case Study has been included
so that the reader can get motivated and excited about the subject matter and its relevance to
practice.
14. Basic material introduced in this book is totally independent of any software that may
accompany the usage of this book, and/or the laboratory associated with the course. The common
software in usage, as of writing this book, consists of Windows, Word Perfect, PSPICE, Math
CAD, and MATLAB. There are also other popular specialized simulation programs such as Signal
Processing Workstation (SPW) in the area of analog and digital communications, Very High
Level Description Language (VHDL) in the area of digital systems, Electromagnetic Transients
Program (EMTP) in the field of power, and SIMULINK in the field of control. In practice,
however, any combination of software that satisfies the need for word processing, graphics, editing,
mathematical analysis, and analog as well as digital circuit analysis should be satisfactory.
In order to integrate computer-aided circuit analysis, two types of programs have been
introduced in this text: A circuit simulator PSpice and a math solver MATLAB. Our purpose
here is not to teach students how to use specific software packages, but to help them develop
an analysis style that includes the intelligent use of computer tools. After all, these tools are
an intrinsic part of the engineering environment, which can significantly enhance the student’s
understanding of circuit phenomena.
15. The basics, to which the reader is exposed in this text, will help him or her to select
consultants—experts in specific areas—either in or out of house, who will provide the knowledge
to solve a confronted problem. After all, no one can be expected to be an expert in all areas
discussed in this text!
VI. PEDAGOGY
A. Outline
Beyond the overview meant as an orientation, the text is basically divided into five parts.
Part 1: Electric Circuits This part provides the basic circuit-analysis concepts and tech-
niques that will be used throughout the subsequent parts of the text. Three-phase circuits have
been introduced to develop the background needed for analyzing ac power systems. Basic notions
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of residential circuit wiring, including grounding and safety considerations, are presented.
Part 2: Electronic Analog and Digital Systems With the background of Part I, the student
is then directed to analog and digital building blocks. Operational amplifiers are discussed as an
especially important special case. After introducing digital system components, computer systems,
and networks to the students, semiconductor devices, integrated circuits, transistor amplifiers, as
well as digital circuits are presented. The discussion of device physics is kept to the necessary
minimum, while emphasis is placed on obtaining powerful results from simple tools placed in
students’ hands and minds.
Part 3: Energy Systems With the background built on three-phase circuits in Part I, ac
power systems are considered. Magnetic circuits and transformers are then presented, before the
student is introduced to the principles of electromechanics and practical rotating machines that
achieve electromechanical energy conversion.
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PREFACE xix
Part 4: Information Systems Signal processing and communication systems (both analog
and digital) are discussed using the block diagrams of systems engineering.
Part 5: Control Systems By focusing on control aspects, this part brings together the
techniques and concepts of the previous parts in the design of systems to accomplish specific
tasks. A section on power semiconductor-controlled drives is included in view of their recent
importance. The basic concepts of feedback control systems are introduced, and finally the flavor
of digital control systems is added.
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Appendices The appendices provide ready-to-use information:
Appendix A: Selected bibliography for supplementary reading
Appendix B: Brief review of fundamentals of engineering (FE) examination
Appendix C: Technical terms, units, constants, and conversion factors for the SI system
Appendix D: Mathematical relations (used in the text)
Appendix E: Solution of simultaneous equations
Appendix F: Complex numbers
Appendix G: Fourier series
Appendix H: Laplace transforms
B. Chapter Introductions
Each chapter is introduced to the student stating the objective clearly, giving a sense of what
to expect, and motivating the student with enough information to look forward to reading the
chapter.
C. Chapter Endings
At the end of each chapter, the learning objectives of that chapter are listed so that the student
can check whether he or she has accomplished each of the goals.
In order to motivate and excite the student, practical applications using electrical engineering
principles are included. At the very end of each chapter, a relevant Practical Application: A Case
Study is presented.
D. Illustrations
A large number of illustrations support the subject matter with the intent to motivate the student
to pursue the topics further.
E. Examples
Numerous comprehensive examples are worked out in detail in the text, covering most of the
theoretical points raised. An appropriate difficulty is chosen and sufficient stimulation is built in
to go on to more challenging situations.
F. End-of-Chapter Problems
A good number of problems (identified with each section of every chapter), with properly graded
levels of difficulty, are included at the end of each chapter, thereby allowing the instructor
considerable flexibility. There are nearly a thousand problems in the book.
G. Preparation for the FE Exam
A brief review of the Fundamentals of Engineering (FE) examination is presented in Appendix
B in order to aid the student who is preparing to take the FE examination in view of becoming a
registered Professional Engineer (PE).
VII. SUPPLEMENTS
A Solutions Manual to Accompany Introduction to Electrical Engineering, by M.S. Sarma
(ISBN 019-514260-8), with complete detailed solutions (provided by the author) for all problems
in the book is available to adopters.
Copyright OUP
xx PREFACE
MicroSoft PowerPoint Overheads to Accompany Introduction to Electrical Engineering

(ISBN 019-514472-1) are free to adopters. Over 300 text figures and captions are available for
classroom projection use.
A web-site, MSSARMA.org, will include interesting web links and enhancement materials,
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errata, a forum to communicate with the author, and more.
A CD-ROM Disk is packaged with each new book. The CD contains:
• Complete Solutions for Students to 20% of the problems. These solutions have been
prepared by the author and are resident on the disk in Adobe Acrobat (.pdf) format. The
problems with solutions on disk are marked with an asterisk next to the problem in the text.
• The demonstration version of Electronics Workbench Multisim Version 6, an in-
novative teaching and learning software product that is used to build circuits and to
simulate and analyze their electrical behavior. This demonstration version includes 20
demo circuit files built from circuit examples from this textbook. The CD also includes
another 80 circuits from the text that can be opened with the full student or educational
versions of Multisim. These full versions can be obtained from Electronics Workbench at
www.electronicsworkbench.com.
To extend the introduction to selected topics and provide additional practice, we recommend
the following additional items:
• Circuits: Allan’s Circuits Problems by Allan Kraus (ISBN 019-514248-9), which includes
over 400 circuit analysis problems with complete solutions, many in MATLAB and SPICE
form.
• Electronics: KC’s Problems and Solutions to Accompany Microelectronic Circuits by K.C.
Smith (019–511771-9), which includes over 400 electronics problems and their complete
solutions.
• SPICE: SPICE by Gordon Roberts and Adel Sedra (ISBN 019-510842-6) features over 100
examples and numerous exercises for computer-aided analysis of microelectronic circuits.
• MATLAB: Getting Started with MATLAB by Rudra Pratap (ISBN 019-512947-4) provides
a quick introduction to using this powerful software tool.
For more information or to order an examination copy of the above mentioned supplements
contact Oxford University Press at [email protected].
VIII. ACKNOWLEDGMENTS
The author would like to thank the many people who helped bring this project to fruition. A
number of reviewers greatly improved this text through their thoughtful comments and useful
suggestions.
I am indebted to my editor, Peter C. Gordon, of Oxford University Press, who initiated
this project and continued his support with skilled guidance, helpful suggestions, and great
encouragement. The people at Oxford University Press, in particular, Senior Project Editor Karen
Shapiro, have been most helpful in this undertaking. My sincere thanks are also due to Mrs. Sally
Gupta, who did a superb job typing most of the manuscript.
I would also like to thank my wife, Savitri, for her continued encouragement and support,
without which this project could not have been completed. It is with great pleasure and joy that I
dedicate this work to my grandchildren.
Mulukutla S. Sarma
Northeastern University
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OVERVIEW
What is electrical engineering? What is the scope of electrical engineering?

To answer the first question in a simple way, electrical engineering deals mainly with
information systems and with power and energy systems. In the former, electrical means are
used to transmit, store, and process information; while in the latter, bulk energy is transmitted
from one place to another and power is converted from one form to another.
The second question is best answered by taking a look at the variety of periodicals published
by the Institute of Electrical and Electronics Engineers (IEEE), which is the largest technical
society in the world with over 320,000 members in more than 140 countries worldwide. Table I
lists 75 IEEE Society/Council periodicals along with three broad-scope publications.
The transactions and journals of the IEEE may be classified into broad categories of devices,
circuits, electronics, computers, systems, and interdisciplinary areas. All areas of electrical
engineering require a working knowledge of physics and mathematics, as well as engineering
methodologies and supporting skills in communications and human relations. A closely related
field is that of computer science.
Obviously, one cannot deal with all aspects of all of these areas. Instead, the general concepts
and techniques will be emphasized in order to provide the reader with the necessary background
needed to pursue specific topics in more detail. The purpose of this text is to present the basic
theory and practice of electrical engineering to students with varied backgrounds and interests.
After all, electrical engineering rests upon a few major principles and subprinciples.
Some of the areas of major concern and activity in the present society, as of writing this
book, are:
• Protecting the environment
• Energy conservation
• Alternative energy sources
• Development of new materials
• Biotechnology
• Improved communications
• Computer codes and networking
• Expert systems
This text is but a modest introduction to the exciting field of electrical engineering. However,
it is the ardent hope and fervent desire of the author that the book will help inspire the reader
to apply the basic principles presented here to many of the interdisciplinary challenges, some of
which are mentioned above.
xxi
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xxii OVERVIEW
TABLE I IEEE Publications
Publication Pub ID
IEEE Society/Council Periodicals

Aerospace & Electronic Systems Magazine 3161
Aerospace & Electronic Systems, Transactions on 1111
Annals of the History of Computing 3211
Antennas & Propagation, Transactions on 1041
Applied Superconductivity, Transactions on 1521
Automatic Control, Transactions on 1231
Biomedical Engineering, Transactions on 1191
Broadcasting, Transactions on 1011
Circuits and Devices Magazine 3131
Circuits & Systems, Part I, Transactions on 1561
Circuits & Systems, Part II, Transactions on 1571
Circuits & Systems for Video Technology, Transactions on 1531
Communications, Transactions on 1201
Communications Magazine 3021
Components, Hybrids, & Manufacturing Technology, Transactions on 1221
Computer Graphics & Applications Magazine 3061
Computer Magazine 3001
Computers, Transactions on 1161
Computer-Aided Design of Integrated Circuits and Systems, Transactions on 1391
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Consumer Electronics, Transactions on 1021

Design & Test of Computers Magazine 3111
Education, Transactions on 1241
Electrical Insulation, Transactions on 1301
Electrical Insulation Magazine 3141
Electromagnetic Compatibility, Transactions on 1261
Electron Device Letters 3041
Electron Devices, Transactions on 1151
Electronic Materials, Journal of 4601
Energy Conversion, Transactions on 1421
Engineering in Medicine & Biology Magazine 3091
Engineering Management, Transactions on 1141
Engineering Management Review 3011
Expert Magazine 3151
Geoscience & Remote Sensing, Transactions on 1281
Image Processing, Transactions on 1551
Industrial Electronics, Transactions on 1131
Industry Applications, Transactions on 1321
Information Theory, Transactions on 1121
Instrumentation & Measurement, Transactions on 1101
Knowledge & Data Engineering, Transactions on 1471
Lightwave Technology, Journal of 4301
LTS (The Magazine of Lightwave Telecommunication Systems) 3191
Magnetics, Transactions on 1311
Medical Imaging, Transactions on 1381
Micro Magazine 3071
Microelectromechanical Systems, Journal of 4701
Microwave and Guided Wave Letters 1511
Microwave Theory & Techniques, Transactions on 1181
Network Magazine 3171
Neural Networks, Transactions on 1491
Nuclear Science, Transactions on 1061
Oceanic Engineering, Journal of 4201
Parallel & Distributed Systems, Transactions on 1501
Pattern Analysis & Machine Intelligence, Transactions on 1351
Photonics Technology Letters 1481
Plasma Science, Transactions on 1071
Power Delivery, Transactions on 1431
Continued
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OVERVIEW xxiii
TABLE I Continued
Publication Pub ID
Power Electronics, Transactions on 4501

Power Engineering Review 3081
Power Systems, Transactions on 1441
Professional Communication, Transactions on 1251
Quantum Electronics, Journal of 1341
Reliability, Transactions on 1091
Robotics & Automation, Transactions on 1461
Selected Areas in Communication, Journal of 1411
Semiconductor Manufacturing, Transactions on 1451
Signal Processing, Transactions on 1001
Signal Processing Magazine 3101
Software Engineering, Transactions on 1171
Software Magazine 3121
Solid-State Circuits, Journal of 4101
Systems, Man, & Cybernetics, Transactions on 1271
Technology & Society Magazine 1401
Ultrasonics, Ferroelectrics & Frequency Control, Transactions on 1211
Vehicular Technology, Transactions on 1081
Broad Scope Publications

IEEE Spectrum 5001
Proceedings of the IEEE 5011
IEEE Potentials 5061
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A historical perspective of electrical engineering, in chronological order, is furnished in Table

II. A mere glance will thrill anyone, and give an idea of the ever-changing, fast-growing field of
electrical engineering.
TABLE II Chronological Historical Perspective of Electrical Engineering
1750–1850 Coulomb’s law (1785)

Battery discovery by Volta
Mathematical theories by Fourier and Laplace
Ampere’s law (1825)
Ohm’s law (1827)
Faraday’s law of induction (1831)
1850–1900 Kirchhoff’s circuit laws (1857)
Telegraphy: first transatlantic cables laid
Maxwell’s equations (1864)
Cathode rays: Hittorf and Crookes (1869)
Telephony: first telephone exchange in New Haven, Connecticut
Edison opens first electric utility in New York City (1882): dc power systems
Waterwheel-driven dc generator installed in Appleton, Wisconsin (1882)
First transmission lines installed in Germany (1882), 2400 V dc, 59km
Dc motor by Sprague (1884)
Commercially practical transformer by Stanley (1885)
Steinmetz’s ac circuit analysis
Tesla’s papers on ac motors (1888)
Radio waves: Hertz (1888)
First single-phase ac transmission line in United States (1889): Ac power systems, Oregon City to
Portland, 4 kV, 21 km
First three-phase ac transmission line in Germany (1891), 12 kV, 179 km
First three-phase ac transmission line in California (1893), 2.3 kV, 12 km
Generators installed at Niagara Falls, New York
Heaviside’s operational calculus methods
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xxiv OVERVIEW
1900–1920 Marconi’s wireless telegraph system: transatlantic communication (1901)

Photoelectric effect: Einstein (1904)
Vacuum-tube electronics: Fleming (1904), DeForest (1906)
First AM broadcasting station in Pittsburgh, Pennsylvania
Regenerative amplifier: Armstrong (1912)
1920–1940 Television: Farnsworth, Zworykin (1924)
Cathode-ray tubes by DuMont; experimental broadcasting
Negative-feedback amplifier by Black (1927)
Boolean-algebra application to switching circuits by Shannon (1937)
1940–1950 Major advances in electronics (World War II)
Radar and microwave systems: Watson-Watts (1940)
Operational amplifiers in analog computers
FM communication systems for military applications
System theory papers by Bode, Shannon, and Wiener
ENIAC vacuum-tube digital computer at the University of Pennsylvania (1946)
Transistor electronics: Shockley, Bardeen, and Brattain of Bell Labs (1947)
Long-playing microgroove records (1948)
1950–1960 Transistor radios in mass production
Solar cell: Pearson (1954)
Digital computers (UNIVAC I, IBM, Philco); Fortran programming language
First commercial nuclear power plant at Shippingport, Pennsylvania (1957)
Integrated circuits by Kilby of Texas Instruments (1958)
1960–1970 Microelectronics: Hoerni’s planar transistor from Fairchild Semiconductors
Laser demonstrations by Maiman (1960)
First communications satellite Telstar I launched (1962)
MOS transistor: Hofstein and Heiman (1963)
Digital communications
765 kV AC power lines constructed (1969)
Microprocessor: Hoff (1969)
1970–1980 Microcomputers; MOS technology; Hewlett-Packard calculator
INTEL’s 8080 microprocessor chip; semiconductor devices for memory
Computer-aided design and manufacturing (CAD/CAM)
Interactive computer graphics; software engineering
Personal computers; IBM PC
Artificial intelligence; robotics
Fiber optics; biomedical electronic instruments; power electronics
1980–Present Digital electronics; superconductors
Neural networks; expert systems
High-density memory chips; digital networks
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INTRODUCTION TO
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PART
ELECTRICAL CIRCUITS
ONE
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1 Circuit Concepts
1.1 Electrical Quantities
1.2 Lumped-Circuit Elements
1.3 Kirchhoff’s Laws
1.4 Meters and Measurements
1.5 Analogy between Electrical and Other Nonelectric Physical Systems
1.6 Learning Objectives

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1.7 Practical Application: A Case Study—Resistance Strain Gauge
Problems
Electric circuits, which are collections of circuit elements connected together, are the most
fundamental structures of electrical engineering. A circuit is an interconnection of simple elec-
trical devices that have at least one closed path in which current may flow. However, we may
have to clarify to some of our readers what is meant by “current” and “electrical device,” a
task that we shall undertake shortly. Circuits are important in electrical engineering because
they process electrical signals, which carry energy and information; a signal can be any time-
varying electrical quantity. Engineering circuit analysis is a mathematical study of some useful
interconnection of simple electrical devices. An electric circuit, as discussed in this book, is
an idealized mathematical model of some physical circuit or phenomenon. The ideal circuit
elements are the resistor, the inductor, the capacitor, and the voltage and current sources. The
ideal circuit model helps us to predict, mathematically, the approximate behavior of the actual
event. The models also provide insights into how to design a physical electric circuit to perform a
desired task. Electrical engineering is concerned with the analysis and design of electric circuits,
systems, and devices. In Chapter 1 we shall deal with the fundamental concepts that underlie
all circuits.
Electrical quantities will be introduced first. Then the reader is directed to the lumped-
circuit elements. Then Ohm’s law and Kirchhoff’s laws are presented. These laws are sufficient
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4 CIRCUIT CONCEPTS
for analyzing and designing simple but illustrative practical circuits. Later, a brief introduc-
tion is given to meters and measurements. Finally, the analogy between electrical and other
nonelectric physical systems is pointed out. The chapter ends with a case study of practical
application.
1.1 ELECTRICAL QUANTITIES

In describing the operation of electric circuits, one should be familiar with such electrical quantities
as charge, current, and voltage. The material of this section will serve as a review, since it will
not be entirely new to most readers.
Charge and Electric Force

The proton has a charge of +1.602 10−19 coulombs (C), while the electron has a charge of
−1.602 × 10−19 C. The neutron has zero charge. Electric charge and, more so, its movement
are the most basic items of interest in electrical engineering. When many charged particles are
collected together, larger charges and charge distributions occur. There may be point charges (C),
line charges (C/m), surface charge distributions (C/m2), and volume charge distributions (C/m3).
A charge is responsible for an electric field and charges exert forces on each other. Like
charges repel, whereas unlike charges attract. Such an electric force can be controlled and utilized
for some useful purpose. Coulomb’s law gives an expression to evaluate the electric force in
newtons (N) exerted on one point charge by the other:
Q1 Q 2
Force on Q1 due to Q2 = F̄21 = ā21 (1.1.1a)
4π ε0 R 2
Q2 Q 1
Force on Q2 due to Q1 = F̄12 = ā12 (1.1.1b)
4π ε0 R 2
where Q1 and Q2 are the point charges (C); R is the separation in meters (m) between them; ε0
is the permittivity of the free-space medium with units of C2 /N · m or, more commonly, farads
per meter (F/m); and ā21 and ā12 are unit vectors along the line joining Q1 and Q2 , as shown in
Figure 1.1.1.
Equation (1.1.1) shows the following:
1. Forces F̄21 and F̄12 are experienced by Q1 and Q2 , due to the presence of Q2 and Q1 ,
respectively. They are equal in magnitude and opposite of each other in direction.
2. The magnitude of the force is proportional to the product of the charge magnitudes.
3. The magnitude of the force is inversely proportional to the square of the distance between
the charges.
4. The magnitude of the force depends on the medium.
5. The direction of the force is along the line joining the charges.
Note that the SI system of units will be used throughout this text, and the student should be
conversant with the conversion factors for the SI system.
The force per unit charge experienced by a small test charge placed in an electric field is
known as the electric field intensity Ē, whose units are given by N/C or, more commonly, volts
per meter (V/m),
F̄
Ē = lim (1.1.2)
Q→0 Q
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1.1 ELECTRICAL QUANTITIES 5
F12
R a12
Q2
a21 Q1
F21
Figure 1.1.1 Illustration of Coulomb’s law.
Equation (1.1.2) is the defining equation for the electric field intensity (with units of N/C or V/m),
irrespective of the source of the electric field. One may then conclude:
F̄21 = Q1 Ē2 (1.1.3a)
F̄12 = Q2 Ē1 (1.1.3b)
where Ē2 is the electric field due to Q2 at the location of Q1 , and Ē1 is the electric field due to
Q1 at the location of Q2 , given by
Q2
Ē2 = ā21 (1.1.4a)
4π ε0 R 2
Q1
Ē1 = ā12 (1.1.4b)
4π ε0 R 2
Note that the electric field intensity due to a positive point charge is directed everywhere
radially away from the point charge, and its constant-magnitude surfaces are spherical surfaces
centered at the point charge.
EXAMPLE 1.1.1
(a) A small region of an impure silicon crystal with dimensions 1.25 × 10−6 m ×10−3 m
×10−3 m has only the ions (with charge +1.6 10−19 C) present with a volume density of
1025/m3. The rest of the crystal volume contains equal densities of electrons (with charge
−1.6 × 10−19 C) and positive ions. Find the net total charge of the crystal.
(b) Consider the charge of part (a) as a point charge Q1 . Determine the force exerted by this
on a charge Q2 = 3µC when the charges are separated by a distance of 2 m in free space,
as shown in Figure E1.1.1.
y
− Q3 = −2 × 10−6 C
F32 F2
1m
76°
Q1 = 2 × 10−6 C + + x
F12 Q2 = 3 × 10−6 C
2m
Figure E1.1.1
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6 CIRCUIT CONCEPTS
(c) If another charge Q3 = −2µC is added to the system 1 m above Q2 , as shown in Figure
E1.1.1, calculate the force exerted on Q2 .
Solution
(a) In the region where both ions and free electrons exist, their opposite charges cancel, and
the net charge density is zero. From the region containing ions only, the volume-charge
density is given by
ρ = (1025 )(1.6 × 10−19 ) = 1.6 × 106 C/m3
The net total charge is then calculated as:
Q = ρv = (1.6 × 106 )(1.25 × 10−6 × 10−3 × 10−3 ) = 2 × 10−6 C
(b) The rectangular coordinate system shown defines the locations of the charges: Q1 =
2 × 10−6 C; Q2 = 3 × 10−6 C. The force that Q1 exerts on Q2 is in the positive direction
of x, given by Equation (1.1.1),
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(3 × 10−6 )(2 × 10−6 )
F̄12 = āx = āx 13.5 × 10−3 N
4π(10−9 /36π )22
This is the force experienced by Q2 due to the effect of the electric field of Q1 . Note the
value used for free-space permittivity, ε0 , as (8.854×10−12 ), or approximately 10−9 /36π
F/m. āx is the unit vector in the positive x-direction.
(c) When Q3 is added to the system, as shown in Figure E1.1.1, an additional force on Q2
directed in the positive y-direction occurs (since Q3 and Q2 are of opposite sign),
(3 × 10−6 )(−2 × 10−6 )
F̄32 = (−āy ) = āy 54 × 10−3 N
4π(10−9 36π )12
The resultant force F̄2 acting on Q2 is the superposition of F̄12 and F̄32 due to Q1 and
Q3 , respectively.
The vector combination of F̄12 and F̄32 is given by:

F̄32
F̄2 = F122
+ F32 2
tan−1
F̄12
54
= 13 .52 + 542 × 10−3 tan−1
13 .5
= 55.7 × 10−3 76° N
Conductors and Insulators

In order to put charge in motion so that it becomes an electric current, one must provide a path
through which it can flow easily by the movement of electrons. Materials through which charge
flows readily are called conductors. Examples include most metals, such as silver, gold, copper,
and aluminum. Copper is used extensively for the conductive paths on electric circuit boards and
for the fabrication of electrical wires.
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Insulators are materials that do not allow charge to move easily. Examples include glass,
plastic, ceramics, and rubber. Electric current cannot be made to flow through an insulator, since
a charge has great difficulty moving through it. One sees insulating (or dielectric) materials often
wrapped around the center conducting core of a wire.
Although the term resistance will be formally defined later, one can say qualitatively that
a conductor has a very low resistance to the flow of charge, whereas an insulator has a very
high resistance to the flow of charge. Charge-conducting abilities of various materials vary in
a wide range. Semiconductors fall in the middle between conductors and insulators, and have
a moderate resistance to the flow of charge. Examples include silicon, germanium, and gallium
arsenide.
Current and Magnetic Force

The rate of movement of net positive charge per unit of time through a cross section of a conductor
is known as current,
dq
i(t) = (1.1.5)
dt
The SI unit of current is the ampere (A), which represents 1 coulomb per second. In most
metallic conductors, such as copper wires, current is exclusively the movement of free electrons
in the wire. Since electrons are negative, and since the direction designated for the current
is that of the net positive charge movement, the charges in the wire are thus moving in the
direction opposite to the direction of the current designation. The net charge transferred at a
particular time is the net area under the current–time curve from the beginning of time to the
present,
t
q(t) = i(τ ) dτ (1.1.6)
−∞
While Coulomb’s law has to do with the electric force associated with two charged bodies,
Ampere’s law of force is concerned with magnetic forces associated with two loops of wire carrying
currents by virtue of the motion of charges in the loops. Note that isolated current elements do
not exist without sources and sinks of charges at their ends; magnetic monopoles do not exist.
Figure 1.1.2 shows two loops of wire in freespace carrying currents I1 and I2 .
Considering a differential element d l¯1 of loop 1 and a differential element d l¯2 of loop 2,
the differential magnetic forces d F̄21 and d F̄12 experienced by the differential current elements
I1 d l¯1 , and I2 d l¯2 , due to I2 and I1 , respectively, are given by

¯ µ0 I2 d l¯2 × ā21
d F̄21 = I1 d l1 × (1.1.7a)
4π R2

¯ µ0 I1 d l¯1 × ā12
d F̄12 = I2 d l2 × (1.1.7b)
4π R2
where ā21 and ā12 are unit vectors along the line joining the two current elements, R is the distance
between the centers of the elements, µ0 is the permeability of free space with units of N/A2 or
commonly known as henrys per meter (H/m). Equation (1.1.7) reveals the following:
1. The magnitude of the force is proportional to the product of the two currents and the
product of the lengths of the two current elements.
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8 CIRCUIT CONCEPTS
I2 Figure 1.1.2 Illustration of Ampere’s law (of

I1 force).
a21 dl2
a12
dl1
R
Loop 1 Loop 2
2. The magnitude of the force is inversely proportional to the square of the distance between
the current elements.
3. To determine the direction of, say, the force acting on the current element I1 d l¯1 , the cross
product d l¯2 × ā21 must be found. Then crossing d l¯1 with the resulting vector will yield
the direction of d F̄21 .
4. Each current element is acted upon by a magnetic field due to the other current element,
d F̄21 = I1 d l¯1 × B̄2 (1.1.8a)

d F̄12 = I2 d l¯2 × B̄1 (1.1.8b)
where B̄ is known as the magnetic flux density vector with units of N/A · m, commonly
known as webers per square meter (Wb/m2) or tesla (T).
Current distribution is the source of magnetic field, just as charge distribution is the source
of electric field. As a consequence of Equations (1.1.7) and (1.1.8), it can be seen that
µ0
B̄2 = I2 d l¯2 × ā21 (1.1.9a)
4π
µ0 I1 d l¯1 × ā12
B̄1 = (1.1.9b)
4π R2
which depend on the medium parameter. Equation (1.1.9) is known as the Biot–Savart law.
Equation (1.1.8) can be expressed in terms of moving charge, since current is due to the flow
of charges. With I = dq/dt and d l¯ = v̄ dt, where v̄ is the velocity, Equation (1.1.8) can be
rewritten as

dq
d F̄ = (v̄ dt) × B̄ = dq (v̄ × B̄) (1.1.10)
dt
Thus it follows that the force F̄ experienced by a test charge q moving with a velocity v̄ in a
magnetic field of flux density B̄ is given by
F̄ = q (v̄ × B̄) (1.1.11)
The expression for the total force acting on a test charge q moving with velocity v̄ in a region
characterized by electric field intensity Ē and a magnetic field of flux density B̄ is
F̄ = F̄E + F̄M = q (Ē + v̄ × B̄) (1.1.12)
which is known as the Lorentz force equation.
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EXAMPLE 1.1.2
Figure E1.1.2 (a) gives a plot of q(t) as a function of time t.
(a) Obtain the plot of i(t).
(b) Find the average value of the current over the time interval of 1 to 7 seconds.
q(t), coulombs Figure E1.1.2 (a) Plot of q(t).

(b) Plot of i(t).
t, seconds
0 1 2 3 4 5 6 7 8 9 10
−1
(a)
i(t), amperes
1.5
1.0
t, seconds
1 2 3 4 5 6 7 8 9 10
−2.0
(b)
Solution
(a) Applying Equation (1.1.5) and interpreting the first derivative as the slope, one obtains
the plot shown in Figure E1.1.2(b).
T
(b) Iav = (1/T ) 0 i dt. Interpreting the integral as the area enclosed under the curve, one
gets:
1
Iav = [(1.5 × 2) − (2.0 × 2) + (0 × 1) + (1 × 1)] = 0
(7 − 1)
Note that the net charge transferred during the interval of 1 to 7 seconds is zero in this case.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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10 CIRCUIT CONCEPTS
EXAMPLE 1.1.3
Consider an infinitesimal length of 10−6 m of wire whose center is located at the point (1, 0, 0),
carrying a current of 2 A in the positive direction of x.
(a) Find the magnetic flux density due to the current element at the point (0, 2, 2).
(b) Let another current element (of length 10−3 m) be located at the point (0, 2, 2), carrying
a current of 1 A in the direction of (−āy + āz ). Evaluate the force on this current element
due to the other element located at (1, 0, 0).
Solution
(a) I1 d l¯1 = 2 × 10−6 āx . The unit vector ā12 is given by

(0 − 1)āx + (2 − 0)āy + (2 − 0)āz
ā12 = √
12 + 2 2 + 2 2
(−āx + 2āy + 2āz )
=
3
Using the Biot–Savart law, Equation (1.1.9), one gets
µ0 I1 d l¯1 × ā12
[B̄1 ](0,2,2) =
4π R2
where µ0 is the free-space permeability constant given in SI units as 4π × 10−7 H/m,
and R 2 in this case is {(0 − 1)2 + (2 − 0)2 + (2 − 0)2 }, or 9. Hence,

4π × 10−7 (2 × 10−6 āx ) × (−āx + 2āy + 2āz )
[B̄1 ](0,2,2) =
4π 9×3
10−7
= × 4 × 10−6 (āz − āy ) Wb/m2
27
= 0.15 × 10−13 (āz − āy ) T
(b) I2 d l¯2 = 10−3 (−āy + āz )
d F̄12 = I2 d l¯2 × B̄1

= 10−3 (−āy + āz ) × 0.15 × 10−13 (āz − āy ) = 0
Note that the force is zero since the current element I2 d l¯2 and the field B̄1 due to I1 d l¯1
at (0, 2, 2) are in the same direction.
The Biot–Savart law can be extended to find the magnetic flux density due to a current-
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
carrying filamentary wire of any length and shape by dividing the wire into a number of
infinitesimal elements and using superposition. The net force experienced by a current loop can
be similarly evaluated by superposition.
Electric Potential and Voltage

When electrical forces act on a particle, it will possess potential energy. In order to describe the
potential energy that a particle will have at a point x, the electric potential at point x is defined as
Copyright OUP
dw(x)
v(x) = (1.1.13)
dq
where w(x) is the potential energy that a particle with charge q has when it is located at the
position x. The zero point of potential energy can be chosen arbitrarily since only differences in
energy have practical meaning. The point where electric potential is zero is known as the reference
point or ground point, with respect to which potentials at other points are then described. The
potential difference is known as the voltage expressed in volts (V) or joules per coulomb (J/C).
If the potential at B is higher than that at A,
vBA = vB − vA (1.1.14)
which is positive. Obviously voltages can be either positive or negative numbers, and it follows that
vBA = −vAB (1.1.15)
The voltage at point A, designated as vA , is then the potential at point A with respect to the
ground.
Energy and Power

If a charge dq gives up energy dw when going from point a to point b, then the voltage across
those points is defined as
dw
v= (1.1.16)
dq
If dw/dq is positive, point a is at the higher potential. The voltage between two points is the
work per unit positive charge required to move that charge between the two points. If dw and dq
have the same sign, then energy is delivered by a positive charge going from a to b (or a negative
charge going the other way). Conversely, charged particles gain energy inside a source where dw
and dq have opposite polarities.
The load and source conventions are shown in Figure 1.1.3, in which point a is at a
higher potential than point b. The load receives or absorbs energy because a positive charge
goes in the direction of the current arrow from higher to lower potential. The source has
a capacity to supply energy. The voltage source is sometimes known as an electromotive
force, or emf, to convey the notation that it is a force that drives the current through the
circuit.
The instantaneous power p is defined as the rate of doing work or the rate of change of
energy dw/dt,

dw dw dq
p= = = vi (1.1.17)
dt dq dt
The electric power consumed or produced by a circuit element is given by its voltage–current
product, expressed in volt-amperes (VA) or watts (W). The energy over a time interval is found
by integrating power,
T
w = p dt (1.1.18)
0
which is expressed in watt-seconds or joules (J), or commonly in electric utility bills in kilowatt-
hours (kWh). Note that 1 kWh equals 3.6 × 106 J.
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12 CIRCUIT CONCEPTS
+ + Figure 1.1.3 Load and source conventions.

a a
i
vab Load iab vab Source iba
b b
− −
EXAMPLE 1.1.4
A typical 12-V automobile battery, storing about 5 megajoules (MJ) of energy, is connected to a
4-A headlight system.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(a) Find the power delivered to the headlight system.
(b) Calculate the energy consumed in 1 hour of operation.
(c) Express the auto-battery capacity in ampere-hours (Ah) and compute how long the
headlight system can be operated before the battery is completely discharged.
Solution
(a) Power delivered: P = V I = 124 = 48W.

(b) Assuming V and I remain constant, the energy consumed in 1 hour will equal
W = 48(60 × 60) = 172.8 × 103 J = 172.8kJ
(c) 1 Ah = (1 C/s)(3600 s) = 3600C. For the battery in question, 5 × 106 J/12 V =

0.417 × 106 C. Thus the auto-battery capacity is 0.417 × 106 /3600 ∼= 116 Ah. Without
completely discharging the battery, the headlight system can be operated for 116/4 = 29
hours.
Sources and Loads

A source–load combination is represented in Figure 1.1.4. A node is a point at which two or
more components or devices are connected together. A part of a circuit containing only one
component, source, or device between two nodes is known as a branch. A voltage rise indicates
an electric source, with the charge being raised to a higher potential, whereas a voltage drop
indicates a load, with a charge going to a lower potential. The voltage across the source is the
same as the voltage across the load in Figure 1.1.4. The current delivered by the source goes
through the load. Ideally, with no losses, the power (p = vi) delivered by the source is consumed
by the load.
When current flows out of the positive terminal of an electric source, it implies that non-
electric energy has been transformed into electric energy. Examples include mechanical energy
transformed into electric energy as in the case of a generator source, chemical energy changed
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into electric energy as in the case of a battery source, and solar energy converted into electric
energy as in the case of a solar-cell source. On the other hand, when current flows in the direction
of voltage drop, it implies that electric energy is transformed into nonelectric energy. Examples
include electric energy converted into thermal energy as in the case of an electric heater, electric
energy transformed into mechanical energy as in the case of motor load, and electric energy
changed into chemical energy as in the case of a charging battery.
Batteries and ac outlets are the familiar electric sources. These are voltage sources. An ideal
voltage source is one whose terminal voltage v is a specified function of time, regardless of the
current i through the source. An ideal battery has a constant voltage V with respect to time, as
shown in Figure 1.1.5(a). It is known as a dc source, because i = I is a direct current. Figure
1.1.5(b) shows the symbol and time variation for a sinusoidal voltage source with v = Vm cos ωt.
The positive sign on the source symbol indicates instantaneous polarity of the terminal at the
higher potential whenever cos ωt is positive. A sinusoidal source is generally termed an ac source
because such a voltage source tends to produce an alternating current.
The concept of an ideal current source, although less familiar but useful as we shall see later,
is defined as one whose current i is a specified function of time, regardless of the voltage across its
terminals. The circuit symbols and the corresponding i–v curves for the ideal voltage and current
sources are shown in Figure 1.1.6.
Even though ideal sources could theoretically produce infinite energy, one should recognize
that infinite values are physically impossible. Various circuit laws and device representations or
models are approximations of physical reality, and significant limitations of the idealized concepts
or models need to be recognized. Simplified representations or models for physical devices are
the most powerful tools in electrical engineering. As for ideal sources, the concept of constant V
or constant I for dc sources and the general idea of v or i being a specified function of time should
be understood.
When the source voltage or current is independent of all other voltages and currents, such
sources are known as independent sources. There are dependent or controlled sources, whose
i Figure 1.1.4 Source–load combination.

Node a +
+
Source Load
−
Node b −
Ground
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
i i
+ v + v
+ Vm
V
V t v = Vm cos ωt t
0 − 0 2π/ω
−Vm
− −
(a) (b)
Figure 1.1.5 Voltage sources. (a) Ideal dc source (battery). (b) Ideal sinusoidal ac source.
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14 CIRCUIT CONCEPTS
i is
+ i + i
is
+
vs vs v is v v
− 0 vs 0
− −
(a) (b)
Figure 1.1.6 Circuit symbols and i–v curves. (a) Ideal voltage source. (b) Ideal current source.
voltage or current does depend on the value of some other voltage or current. As an example, a
voltage amplifier producing an output voltage vout = Avin , where vin is the input voltage and A is
the constant-voltage amplification factor, is shown in Figure 1.1.7, along with its controlled-source
model using the diamond-shaped symbol. Current sources controlled by a current or voltage will
also be considered eventually.
Waveforms
We are often interested in waveforms, which may not be constant in time. Of particular interest
is a periodic waveform, which is a time-varying waveform repeating itself over intervals of time
T > 0.
f (t) = f (t ± nT ) n = 1, 2, 3, · · · (1.1.19)
The repetition time T of the waveform is called the period of the waveform. For a waveform
to be periodic, it must continue indefinitely in time. The dc waveform of Figure 1.1.5(a) can be
considered to be periodic with an infinite period. The frequency of a periodic waveform is the
reciprocal of its period,
1
f = Hertz (Hz) (1.1.20)
T
A sinusoidal or cosinusoidal waveform is typically described by
f (t) = A sin(ωt + φ) (1.1.21)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
where A is the amplitude, φ is the phase offset, and ω = 2πf = 2π/T is the radian frequency
of the wave. When φ = 0, a sinusoidal wave results, and when φ = 90°, a cosinusoidal wave
results. The average value of a periodic waveform is the net positive area under the curve for one
period, divided by the period,
T
1
Fav = f (t) dt (1.1.22)
T
0
+ Figure 1.1.7 Voltage amplifier and its

+ + + controlled-source model.
Voltage
vin v Avin vout
amplifier out
− − −
−
(a) (b)
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The effective, or root-mean square (rms), value is the square root of the average of f 2 (t),

T
1
Frms = f 2 (t) dt (1.1.23)
T
0
Determining the square of the function f (t), then finding the mean (average) value, and finally
taking the square root yields the rms value, known as effective value. This concept will be seen
to be useful in comparing the effectiveness of different sources in delivering power to a resistor.
The effective value of a periodic current, for example, is a constant, or dc value, which delivers
the same average power to a resistor, as will be seen later.
For the special case of a dc waveform, the following holds:
f (t) = F ; Fav = Frms = F (1.1.24)
For the sinusoid or cosinusoid, it can be seen that
√
f (t) = A sin(ωt + φ); Fav = 0; Frms = A/ 2 ∼
= 0.707 A (1.1.25)
The student is encouraged to show the preceding results using graphical and analytical means.
Other common types of waveforms are exponential in nature,
f (t) = Ae−t/τ (1.1.26a)
−t/τ
f (t) = A(1 − e (1.1.26b)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
)
where τ is known as the time constant. After a time of one time constant has elapsed, looking at
Equation (1.1.26a), the value of the waveform will be reduced to 37% of its initial value; Equation
(1.1.26b) shows that the value will rise to 63% of its final value. The student is encouraged to
study the functions graphically and deduce the results.
EXAMPLE 1.1.5
A periodic current waveform in a rectifier is shown in Figure E1.1.5. The wave is sinusoidal for
π/3 ≤ ωt ≤ π, and is zero for the rest of the cycle. Calculate the rms and average values of the
current.
i Figure E1.1.5
10
π π 2π ωt
3
Solution
 

π/3 π 2π
1  
Irms =
2π  i d(ωt) +
2 i 2 d(ωt) + i 2 d(ωt)
0 π/3 π
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16 CIRCUIT CONCEPTS
Notice that ωt rather than t is chosen as the variable for convenience; ω = 2πf = 2π/T;
and integration is performed over three discrete intervals because of the discontinuous current
function. Since i = 0 for 0 ≤ ωt < π/3 and π ≤ ωt ≤ 2π ,

1 π

Irms = 102 sin2 ωt d(ωt) = 4.49 A
2π
π/3
π
1
Iav = 10 sin ωt d(ωt) = 2.39 A
2π
π/3
Note that the base is the entire period 2π , even though the current is zero for a substantial part of
the period.
1.2 LUMPED-CIRCUIT ELEMENTS

Electric circuits or networks are formed by interconnecting various devices, sources, and com-
ponents. Although the effects of each element (such as heating effects, electric-field effects,
or magnetic-field effects) are distributed throughout space, one often lumps them together as
lumped elements. The passive components are the resistance R representing the heating effect,
the capacitance C representing the electric-field effect, and the inductance L representing the
magnetic-field effect. Their characteristics will be presented in this section. The capacitor models
the relation between voltage and current due to changes in the accumulation of electric charge, and
the inductor models the relation due to changes in magnetic flux linkages, as will be seen later.
While these phenomena are generally distributed throughout an electric circuit, under certain
conditions they can be considered to be concentrated at certain points and can therefore be
represented by lumped parameters.
Resistance
An ideal resistor is a circuit element with the property that the current through it is linearly
proportional to the potential difference across its terminals,
i = v/R = Gv, or v = iR (1.2.1)
which is known as Ohm’s law, published in 1827. R is known as the resistance of the resistor
with the SI unit of ohms (-), and G is the reciprocal of resistance called conductance, with the SI
unit of siemens (S). The circuit symbols of fixed and variable resistors are shown in Figure 1.2.1,
along with an illustration of Ohm’s law. Most resistors used in practice are good approximations
to linear resistors for large ranges of current, and their i–v characteristic (current versus voltage
plot) is a straight line.
The value of resistance is determined mainly by the physical dimensions and the resistivity
ρ of the material of which the resistor is composed. For a bar of resistive material of length l and
cross-sectional area A the resistance is given by
ρl l
R= = (1.2.2)
A σA
where ρ is the resistivity of the material in ohm-meters (- · m), and σ is the conductivity of the
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material in S/m, which is the reciprocal of the resistivity. Metal wires are often considered as ideal
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1.2 LUMPED-CIRCUIT ELEMENTS 17
iab iab Figure 1.2.1 Circuit symbols of fixed

+ − + − and variable resistors and illustration of
a (Fixed) R b a (Variable) R b Ohm’s law.
vab vab
iab = vab /R = Gvab
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
TABLE 1.2.1 Resistivity of Some Materials
Type Material ρ(- · m)
Conductors Silver 16 × 10−9

(at 20°C) Copper 17 × 10−9
Gold 24 × 10−9
Aluminum 28 × 10−9
Tungsten 55 × 10−9
Brass 67 × 10−9
Sodium 0.04 × 10−6
Stainless steel 0.91 × 10−6
Iron 0.1 × 10−6
Nichrome 1 × 10−6
Carbon 35 × 10−6
Seawater 0.25
Semiconductors Germanium 0.46
(at 27°C or 300 K) Silicon 2.3 × 103
Insulators Rubber 1 × 1012
Polystyrene 1 × 1015
conductors with zero resistance as a good approximation. Table 1.2.1 lists values of ρ for some
materials.
The resistivity of conductor metals varies linearly over normal operating temperatures
according to

T2 + T
ρT 2 = ρT 1 (1.2.3)
T1 + T
where ρT 2 and ρT 1 are resistivities at temperatures T2 and T1 , respectively, and T is a temperature
constant that depends on the conductor material. All temperatures are in degrees Celsius. The
conductor resistance also depends on other factors, such as spiraling, frequency (the skin effect
which causes the ac resistance to be slightly higher than the dc resistance), and current magnitude
in the case of magnetic conductors (e.g., steel conductors used for shield wires).
Practical resistors are manufactured in standard values, various resistance tolerances, several
power ratings (as will be explained shortly), and in a number of different forms of construction.
The three basic construction techniques are composition type, which uses carbon or graphite and
is molded into a cylindrical shape, wire-wound type, in which a length of enamel-coated wire
is wrapped around an insulating cylinder, and metal-film type, in which a thin layer of metal is
vacuum deposited. Table 1.2.2 illustrates the standard color-coded bands used for evaluating
resistance and their interpretation for the common carbon composition type. Sometimes a fifth
band is also present to indicate reliability. Black is the least reliable color and orange is 1000
times more reliable than black.
For resistors ranging from 1 to 9.1 -, the standard resistance values are listed in Table 1.2.3.
Other available values can be obtained by multiplying the values shown in Table 1.2.3 by factors
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18 CIRCUIT CONCEPTS
TABLE 1.2.2 Standard Color-Coded Bands for Evaluating Resistance and Their Interpretation
Color bands 1–4 b1 b2 b3 b4
Color of Band Digit of Band Multiplier % Tolerance in Actual Value
Black 0 100 —
Brown 1 101 —
Red 2 102 —
Orange 3 103 —
Yellow 4 104 —
Green 5 105 —
Blue 6 106 —
Violet 7 107 —
Grey 8 108 —
White 9 — —
Gold — 10−1 ± 5%
Silver — 10−2 ± 10%
Black or no color — — ± 20%
Resistance value = (10b1 + b2 ) × 10b3 -.
of 10 ranging from 10 - to about 22 × 106 -. For example, 8.2 -, 82 -, 820 -, . . . , 820 k-

are standard available values.
The maximum allowable power dissipation or power rating is typically specified for com-
mercial resistors. A common power rating for resistors used in electronic circuits is 1Ⲑ4 W; other
ratings such as 1Ⲑ8, 1Ⲑ2, 1, and 2 W are available with composition-type resistors, whereas larger
ratings are also available with other types. Variable resistors, known as potentiometers, with a
movable contact are commonly found in rotary or linear form. Wire-wound potentiometers may
have higher power ratings up to 1000 W.
The advent of integrated circuits has given rise to packaged resistance arrays fabricated by
using film technology. These packages are better suited for automated manufacturing and are
usually less costly than discrete resistors in large production runs.
An important property of the resistor is its ability to convert energy from electrical form into
heat. The manufacturer generally states the maximum power dissipation of the resistor in watts.
If more power than this is converted to heat by the resistor, the resistor will be damaged due to
overheating. The instantaneous power absorbed by the resistor is given by
p(t) = v(t)i(t) = i 2 R = v 2 /R = v 2 G (1.2.4)
where v is the voltage drop across the resistance and i is the current through the resistance. It can
be shown (see Problem 1.2.13) that the average value of Equation (1.2.4) is given by
Pav = Vrms Irms = Irms
2
R = Vrms
2
/R = Vrms
2
G (1.2.5)
for periodically varying current and voltage as a function of time. Equation (1.2.5) gives the
expression for the power converted to heat by the resistor.
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TABLE 1.2.3 Standard Available Values of Resistors
1.0 1.5 2.2 3.3 4.7 6.8

1.1 1.6 2.4 3.6 5.1 7.5
1.2 1.8 2.7 3.9 5.6 8.2
1.3 2.0 3.0 4.3 6.2 9.1
Series and parallel combinations of resistors occur very often. Figure 1.2.2 illustrates these
combinations.
Figure 1.2.2(a) shows two resistors R1 and R2 in series sharing the voltage v in direct
proportion to their values, while the same current i flows through both of them,
v = vAC = vAB + vBC = iR1 + iR2 = i(R1 + R2 ) = iReq
or, when R1 and R2 are in series,
Req = R1 + R2 (1.2.6)
Figure 1.2.2(b) shows two resistors in parallel sharing the current i in inverse proportion to
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
their values, while the same voltage v is applied across each of them. At node B,

v v 1 1 R1 R2 v
i = i1 + i2 = + =v + = v/ =
R1 R2 R1 R2 R1 + R 2 Req
or, when R1 and R2 are in parallel,
R 1 R2 1 1 1
Req = or = + or Geq = G1 + G2 (1.2.7)
R1 + R 2 Req R1 R2
Notice the voltage division shown in Figure 1.2.2(a), and the current division in Figure
1.2.2(b).
i = i1 + i2
i
+ +
A A B
R1 vAB = iR1 i1 = v/R1 i2 = v/R2
vR1 = vG1 = vG2
v = vAC = vAB + vBC =
B R1 + R2 vAD = vBC = v R1 iG1 R2 iG2
= =
vBC = iR2 G1 + G2 G1 + G2
R2
C vR2 D C
− = −
R1 + R2
(a) (b)
Figure 1.2.2 Resistances in series and in parallel. (a) R1 and R2 in series. (b) R1 and R2 in parallel.
EXAMPLE 1.2.1
A no. 14 gauge copper wire, commonly used in extension cords, has a circular wire diameter of
64.1 mils, where 1 mil = 0.001 inch.
(a) Determine the resistance of a 100-ft-long wire at 20°C.
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20 CIRCUIT CONCEPTS
(b) If such a 2-wire system is connected to a 110-V (rms) residential source outlet in order
to power a household appliance drawing a current of 1 A (rms), find the rms voltage at
the load terminals.
(c) Compute the power dissipated due to the extension cord.
(d) Repeat part (a) at 50°C, given that the temperature constant for copper is 241.5°C.
Solution
(a) d = 64.1 mils = 64.1 × 10−3 in = 64.1 × 10−3 × 2.54 cm/1 in × 1 m/100 cm =
1.628 × 10−3 m. From Table 1.2.1, ρ of copper at 20°C is 17 × 10−9 m,
12 in 2.54 cm 1m
l = 100 ft = 100 ft × × × = 30.48 m
1 ft 1 in 100 cm
π d2 π(1.628 × 10−3 )2
A= = = 2.08 × 10−6 m2
4 4
Per Equation (1.2.2),
17 × 10−9 × 30.48 ∼
R20°C = ‘ = 0.25 -
2.08 × 10−6
(b) Rms voltage at load terminals, V = 110 − (0.25)2 = 109.5 V (rms). Note that two
100-ft-long wires are needed for the power to be supplied.
(c) Power dissipated, per Equation (1.2.5), P = (1)2 (0.25)(2) = 0.5 W.
(d) Per Equation (1.2.3),

50 + 241.5 17 × 10−9 × 291.5
ρ 50°C = ρ 20°C = = 18.95 × 10−9 - · m
20 + 241.5 261.5
Hence,
18.95 × 10−9 × 30.48 ∼
R50°C = = 0.28 -
2.08 × 10−6
EXAMPLE 1.2.2
(a) Consider a series–parallel combination of resistors as shown in Figure E1.2.2(a). Find
the equivalent resistance as seen from terminals A–B.
(b) Determine the current I and power P delivered by a 10-V dc voltage source applied at
terminals A–B, with A being at higher potential than B.
(c) Replace the voltage source by an equivalent current source at terminals A–B.
(d) Show the current and voltage distribution clearly in all branches of the original circuit
configuration.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Solution
(a) The circuit is reduced as illustrated in Figure E1.2.2(b).

(b) I = 5 A; P = V I = I 2 R = V 2 /R = 50 W [see Figure E1.2.2(c)].
(c) See Figure E1.2.2(d).
(d) See Figure E1.2.2(e).
1Ω 1Ω C
C
A A
1Ω 1Ω
D D 2Ω
2Ω
2Ω 2Ω 2 Ω || 2 Ω
=1Ω
B B
B B
(a)
1Ω C
Figure E1.2.2
A
1Ω+1Ω
(In series) 2Ω
=2Ω
B
B
1Ω C
A
2 Ω || 2 Ω
=1Ω
B
B --`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
1Ω+1Ω
Req = 2 Ω (In series)
=2Ω
B
(b)
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22 CIRCUIT CONCEPTS
A
I = 10/2 = 5 A A +
+
10 V 2Ω 5A
− 2 Ω V = 5 × 2 = 10 V
B
(c) B −
(d)
5A 1Ω
C
+
A + 5V − 2.5 A
+ 2.5 A
1 Ω 2.5 V
−
+
2Ω 5V
10 V 1.25 A D 1.25 A
−
+ +
2 Ω 2.5 V 2 Ω 2.5 V
− −
B B
−
5A
(e)
Maximum Power Transfer

In order to investigate the power transfer between a practical source and a load connected to it,
let us consider Figure 1.2.3, in which a constant voltage source v with a known internal resistance
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
RS is connected to a variable load resistance RL . Note that when RL is equal to zero, it is called
a short circuit, in which case vL becomes zero and iL is equal to v/RS . When RL approaches
infinity, it is called an open circuit, in which case iL becomes zero and vL is equal to v. One is
generally interested to find the value of the load resistance that will absorb maximum power from
the source.
The power PL absorbed by the load is given by
PL = iL2 RL (1.2.8)
where the load current iL is given by
v2
iL = (1.2.9)
RS + R L
Substituting Equation (1.2.9) in Equation (1.2.8), one gets
v2
PL = RL (1.2.10)
(RS + RL )2
For given fixed values of v and RS , in order to find the value of RL that maximizes the power
absorbed by the load, one sets the first derivative dPL /dRL equal to zero,
dPL v 2 (RL + RS )2 − 2v 2 RL (RL + RS )
= =0 (1.2.11)
dRL (RL + RS )4
Copyright OUP
RS Figure 1.2.3 Power transfer between source and load. Note: RL = 0

+
A implies short circuit; vL = 0 and iL = RvS and RL → • implies open
iL
circuit; iL = 0 and vL = v.
+
v iL vL RL
−
B
Source − Load
which leads to the following equation:

(RL + RS )2 − 2RL (RL + RS ) = 0 (1.2.12)
The solution of Equation (1.2.12) is given by
RL = RS (1.2.13)
That is to say, in order to transfer maximum power to a load, the load resistance must be matched
to the source resistance or, in other words, they should be equal to each other.
A problem related to power transfer is that of source loading. Figure 1.2.4(a) illustrates a
practical voltage source (i.e., an ideal voltage source along with a series internal source resistance)
connected to a load resistance; Figure 1.2.4(b) shows a practical current source (i.e., an ideal
current source along with a parallel or shunt internal source resistance) connected to a load
resistance. It follows from Figure 1.2.4(a) that
vL = v − vint = v − iL RS (1.2.14)
where vint is the internal voltage drop within the source, which depends on the amount of current
drawn by the load. As seen from Equation (1.2.14), the voltage actually seen by the load vL
is somewhat lower than the open-circuit voltage of the source. When the load resistance RL is
infinitely large, the load current iL goes to zero, and the load voltage vL is then equal to the
open-circuit voltage of the source v. Hence, it is desirable to have as small an internal resistance
as possible in a practical voltage source.
From Figure 1.2.4(b) it follows that
vL
iL = i − iint = i − (1.2.15)
RS
where iint is the internal current drawn away from the load because of the presence of the internal
source resistance. Thus the load will receive only part of the short-circuit current available from
the source. When the load resistance RL is zero, the load voltage vL goes to zero, and the load
RS iL iL Figure 1.2.4 Source-loading

+ +
effects.
+ vint −
+ iint
v vL RL i vL RL
− RS
Voltage source − Load Current source − Load

(a) (b)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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24 CIRCUIT CONCEPTS
current iL is then equal to the short-circuit current of the source i. Hence, it is desirable to have
as large an internal resistance as possible in a practical current source.
Capacitance
An ideal capacitor is an energy-storage circuit element (with no loss associated with it) repre-
senting the electric-field effect. The capacitance in farads (F) is defined by
C = q/v (1.2.16)
where q is the charge on each conductor, and v is the potential difference between the two
perfect conductors. With v being proportional to q, C is a constant determined by the geometric
configuration of the two conductors. Figure 1.2.5(a) illustrates a two-conductor system carrying
+q and −q charges, respectively, forming a capacitor.
The general circuit symbol for a capacitor is shown in Figure 1.2.5(b), where the current
entering one terminal of the capacitor is equal to the rate of buildup of charge on the plate
attached to that terminal,
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
dq dv
i(t) = =C (1.2.17)
dt dt
in which C is assumed to be a constant and not a function of time (which it could be, if the
separation distance between the plates changed with time).
The terminal v–i relationship of a capacitor can be obtained by integrating both sides of
Equation (1.2.17),
t
1
v(t) = i(τ ) dτ (1.2.18)
C
−∞
which may be rewritten as
t 0 t
1 1 1
v(t) = i(τ ) dτ + i(τ ) dτ = i(τ ) dτ + v(0) (1.2.19)
C C C
0 −∞ 0
where v(0) is the initial capacitor voltage at t = 0.

The instantaneous power delivered to the capacitor is given by
dv(t)
p(t) = v(t)i(t) = C v(t) (1.2.20)
dt
whose average value can be shown (see Problem 1.2.13) to be zero for sinusoidally varying current
and voltage as a function of time. The energy stored in a capacitor at a particular time is found
by integrating,
−q charge A i(t) C B
B
Potential vB
+ −
v(t)
A
+q charge
Potential vA t t
∫ ∫
dq dv
Potential difference = v = vA − vB; C = q/v i(t) = =C ; v(t) = 1 i(τ) dτ = 1 i(τ) dτ + v(0)
dt dt C C 0
(a) (b)
Figure 1.2.5 Capacitor. (a) Two perfect conductors carrying +q and −q charges. (b) Circuit symbol.
Copyright OUP
t t
dv(τ ) 1 1
w(t) = p(τ ) dτ = C v(τ ) = Cv 2 (t) − Cv 2 (−∞) (1.2.21)
dτ 2 2
−∞ −∞
Assuming the capacitor voltage to be zero at t = −∞, the stored energy in the capacitor at some
time t is given by
1
w(t) = Cv 2 (t) (1.2.22)
2
which depends only on the voltage of the capacitor at that time, and represents the stored energy
in the electric field between the plates due to the separation of charges.
If the voltage across the capacitor does not change with time, no current flows, as seen from
Equation (1.2.17). Thus the capacitor acts like an open circuit, and the following relations hold:
Q 1
C = ; I = 0, W = CV 2 (1.2.23)
V 2
An ideal capacitor, once charged and disconnected, the current being zero, will retain a potential
difference for an indefinite length of time. Also, the voltage across a capacitor cannot change
value instantaneously, while an instantaneous change in the capacitor current is quite possible.
The student is encouraged to reason through and justify the statement made here by recalling
Equation (1.2.17).
Series and parallel combinations of capacitors are often encountered. Figure 1.2.6 illustrates
these.
It follows from Figure 1.2.6(a),
v = vAC = vAB + vBC

dv dvAB dvBC i i C1 + C2 i
= + = + =i =
dt dt dt C1 C2 C1 C2 Ceq
or, when C1 and C2 are in series,
C 1 C2 1 1 1
Ceq = or = + (1.2.24)
C1 + C 2 Ceq C1 C2
Referring to Figure 1.2.6(b), one gets
dv dv dv dv
i = i1 + i2 = C1 + C2 = (C1 + C2 ) = Ceq
dt dt dt dt
or, when C1 and C2 are in parallel,
Ceq = C1 + C2 (1.2.25)
Note that capacitors in parallel combine as resistors in series, and capacitors in series combine as
resistors in parallel.
i i Figure 1.2.6 Capacitors in series and in parallel. (a) C1

A A and C2 in series. (b) C1 and C2 in parallel.
+ + B
C1
v v i1 i2
B
C1 C2
C2
− − C
C D
(a) (b)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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26 CIRCUIT CONCEPTS
The working voltage for a capacitor is generally specified by the manufacturer, thereby giving
the maximum voltage that can safely be applied between the capacitor terminals. Exceeding this
limit may result in the breakdown of the insulation and then the formation of an electric arc between
the capacitor plates. Unintentional or parasitic capacitances that occur due to the proximity of
circuit elements may have serious effects on the circuit behavior.
Physical capacitors are often made of tightly rolled sheets of metal film, with a dielectric
(paper or nylon) sandwiched in between, in order to increase their capacitance values (or ability
to store energy) for a given size. Table 1.2.4 lists the range of general-purpose capacitances together
with the maximum voltages and frequencies for different types of dielectric materials. Practical
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
capacitors come in a wide range of values, shapes, sizes, voltage ratings, and constructions. Both
fixed and adjustable devices are available. Larger capacitors are of the electrolytic type, using
aluminum oxide as the dielectric.
TABLE 1.2.4 Characteristics of General-Purpose Capacitors
Capacitance Maximum Voltage Frequency Range

Material Range Range (V) (Hz)
Mica 1 pF to 0.1 µF 50–600 103 –1010

Ceramic 10 pF to 1 µF 50–1600 103 –1010
Mylar 0.001 F to 10 µF 50–600 102 –108
Paper 10 pF to 50 µF 50–400 102 –108
Electrolytic 0.1 µF to 0.2 F 3–600 10–104
Note: 1 pF = 10−12 F; 1 µF = 10−6 F.
EXAMPLE 1.2.3
(a) Consider a 5-µF capacitor to which a voltage v(t) is applied, shown in Figure E1.2.3(a),
top. Sketch the capacitor current and stored energy as a function of time.
(b) Let a current source i(t) be attached to the 5-µF capacitor instead of the voltage source of
part (a), shown in Figure E1.2.3(b), top. Sketch the capacitor voltage and energy stored
as a function of time.
(c) If three identical 5-µF capacitors with an initial voltage of 1 mV are connected (i) in
series and (ii) in parallel, find the equivalent capacitances for both cases.
Solution
(a) From Figure E1.2.3(a) it follows that
v(t) = 0 , t ≤ −1 µ s
= 5(t + 1) mV, − 1 ≤ t ≤ 1 µs
= 10 mV, 1 ≤ t ≤ 3 µs
= −10(t − 4) mV, 3 ≤ t ≤ 4 µs
=0, 4 ≤ t µs
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v(t), mV i(t), mA
i(t) i(t)
+ + +
10 v(t) 5 µF v(t) 10 i(t) 5 µF v(t)
− − −
t, µs
−2 −1 1 2 3 4 5 6 t, µs
−2 −1 1 2 3 4 5 6
i(t), mA v(t), mV
7
6
5
25 4
3
2
t, µs 1
−2 −1 1 2 3 4 5 6 t, µs
−2 −1 1 2 3 4 5 6
−50 w(t), pJ
125 122.5
w(t), pJ 100
90
250
50
40
t, µs
−2 −1 1 2 3 4 5 6 10
t, µs
(a) −1 1 2 3 4 5 6
(b)
+v1(0)− +v2(0)− +v3(0)− v(0) = v1(0) + v2(0) + v3(0)

+ − + −
A B A i B
C1 C2 C3 Ceq
+ v − + v −
(c)
i i
+ +
A i1 i2 i3 A
+ v(0)
+ v(0) + v(0) + v(0)
v v Ceq
C1 v C2 C3 −
− − −
B B
− −
(d)
Figure E1.2.3
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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28 CIRCUIT CONCEPTS
Since
dv dv
i(t) = C = (5 × 10−6 )
dt dt
it follows that
i(t) = 0, t ≤ −1 µ s
= 25 mA, − 1 ≤ t ≤ 1 µs
= 0, 1 ≤ t ≤ 3 µs
= −50 mA, 3 ≤ t ≤ 4 µs
= 0, 4 ≤ t µs
which is sketched in the center of Figure E1.2.3(a).

Since the energy stored at any instant is
1 2 1
w(t) = Cv (t) = (5 × 10−6 )v 2 (t)
2 2
it follows that:
w(t) = 0, t ≤ −1 µ s
= 62.5 (t + 2t + 1) pJ,
2
− 1 ≤ t ≤ 1 µs
= 250 pJ, 1 ≤ t ≤ 3 µs
= 250 (t − 8t + 16) pJ,
2
3 ≤ t ≤ 4 µs
= 0, 4 ≤ t µs
which is sketched at the bottom of Figure E1.2.3(a).

(b) From Figure E1.2.3(b) it follows that
i(t) = 0, t ≤ −1 µ s
= 5 (t + 1) mA, − 1 ≤ t ≤ 1 µs
= 10 mA, 1 ≤ t ≤ 3 µs
= −10 (t − 4) mA, 3 ≤ t ≤ 4 µs
= 0, 4 ≤ t µs
Since
t t
1 1
v(t) = i(τ ) dτ = i(τ ) dτ
C 5 × 10−6
−∞ −∞
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
it follows that
v(t) = 0, t ≤ −1 µ s
2
t 1
= +t + mV, − 1 ≤ t ≤ 1 µs
2 2
Copyright OUP
= 2t mV, 1 ≤ t ≤ 3 µs
= −t + 8t − 9 mV,
2
3 ≤ t ≤ 4 µs
= 7 mV, 4 ≤ t µs
which is sketched in the center of Figure E1.2.3(b).
Since the energy stored at any instant is
1 1
w(t) = Cv 2 (t) = (5 × 10−6 )v 2 (t)
2 2
it follows that
w(t) = 0, t ≤ −1 µ s
t2 1
= 2.5 ( + t + )2 pJ, − 1 ≤ t ≤ 1 µs
2 2
= 10t pJ,
2
1 ≤ t ≤ 3 µs
= 2.5 (−t + 8t − 9) pJ,
2 2
3 ≤ t ≤ 4 µs
= 122.5pJ, 4 ≤ t µs
which is sketched at the bottom of Figure E1.2.3(b).

(c) (i)
1 1 1 1 3 5 5
= + + = , or Ceq = × 10−6 F = µ F,
Ceq C1 C2 C3 5 × 10−6 3 3
with an initial voltage v(0) = 3 mV [Figure E1.2.3(c)].

(ii)
Ceq = C1 + C2 + C3 = 3 × 5 × 10−6 F = 15 µ F
with an initial voltage v(0) = 1 mV [Figure E1.2.3(d)].
Inductance
An ideal inductor is also an energy-storage circuit element (with no loss associated with it) like a
capacitor, but representing the magnetic-field effect. The inductance in henrys (H) is defined by
λ Nψ
L= = (1.2.26)
i i
where λ is the magnetic-flux linkage in weber-turns (Wb·t), N is the number of turns of the coil,
and N ψ is the magnetic flux in webers (Wb) produced by the current i in amperes (A). Figure
1.2.7(a) illustrates a single inductive coil or an inductor of N turns carrying a current i that is
linked by its own flux.
The general circuit symbol for an inductor is shown in Figure 1.2.7(b). According to Faraday’s
law of induction, one can write
dλ d(N ψ) dψ d(Li) di
v(t) = = =N = =L (1.2.27)
dt dt dt dt dt
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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30 CIRCUIT CONCEPTS
i(t)
i(t) +
+
v(t) N turns ψ v(t) L

λ = Nψ
−
−
L = λ/i = Nψ/i t t
∫ v(τ) dτ = L1 ∫ v(τ) dτ + i(0)
di
v(t) = L ; i(t) = 1
dt L 0
(a) (b)
Figure 1.2.7 An inductor. (a) A single inductive coil of N turns. (b) Circuit symbol.
where L is assumed to be a constant and not a function of time (which it could be if the physical
shape of the coil changed with time). Mathematically, by looking at Equations (1.2.17) and
(1.2.27), the inductor is the dual of the capacitor. That is to say, the terminal relationship for
one circuit element can be obtained from that of the other by interchanging v and i, and also by
interchanging L and C.
The terminal i–v relationship of an inductor can be obtained by integrating both sides of
Equation (1.2.27),
t
1
i(t) = v(τ ) dτ (1.2.28)
L −∞
t t
1 1 0 1
i(t) = v(τ ) dτ + v(τ ) dτ = v(τ ) dτ + i(0) (1.2.29)
L 0 L −∞ L 0
where i(0) is the initial inductor current at t = 0.
The instantaneous power delivered to the inductor is given by
di(t)
p(t) = v(t)i(t) = Li(t) (1.2.30)
dt
whose average value can be shown (see Problem 1.2.13) to be zero for sinusoidally varying current
and voltage as a function of time. The energy stored in an inductor at a particular time is found
by integrating,
t
1 1
w(t) = p(τ ) dτ = Li 2 (t) − Li 2 (−∞) (1.2.31)
−∞ 2 2
Assuming the inductor current to be zero at t = −∞, the stored energy in the inductor at some
time t is given by
1
w(t) = Li 2 (t) (1.2.32)
2
which depends only on the inductor current at that time, and represents the stored energy in the
magnetic field produced by the current carried by the coil.
If the current flowing through the coil does not change with time, no voltage across the coil
exists, as seen from Equation (1.2.27). The following relations hold:
λ 1
L= ; V = 0; W = LI 2 (1.2.33)
I 2
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
Under dc conditions, an ideal inductor acts like an ideal wire, or short circuit. Note that the
current through an inductor cannot change value instantaneously. However, there is no reason to
rule out an instantaneous change in the value of the inductor voltage. The student should justify
the statements made here by recalling Equation (1.2.27).
If the medium in the flux path has a linear magnetic characteristic (i.e., constant permeability),
then the relationship between the flux linkages λ and the current i is linear, and the slope of the
linear λ–i characteristic gives the self-inductance, defined as flux linkage per ampere by Equation
(1.2.26). While the inductance in general is a function of the geometry and permeability of the
material medium, in a linear system it is independent of voltage, current, and frequency. If the
inductor coil is wound around a ferrous core such as iron, the λ–i relationship will be nonlinear
and even multivalued because of hysteresis. In such a case the inductance becomes a function
of the current, and the inductor is said to be nonlinear. However, we shall consider only linear
inductors here.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Series and parallel combinations of inductors are often encountered. Figure 1.2.8 illustrates
these.
By invoking the principle of duality, it can be seen that the inductors in series combine like
resistors in series and capacitors in parallel; the inductors in parallel combine like resistors in
parallel and capacitors in series. Thus, when L1 and L2 are in series,
Leq = L1 + L2 (1.2.34)
and when L1 and L2 are in parallel,
L 1 L2 1 1 1
Leq = or = + (1.2.35)
L1 + L 2 Leq L1 L2
A practical inductor may have considerable resistance in the wire of a coil, and sizable
capacitances may exist between various turns. A possible model for a practical inductor could
be a combination of ideal elements: a combination of resistance and inductance in series, with a
capacitance in parallel. Techniques for modeling real circuit elements will be used extensively in
later chapters.
Practical inductors range from about 0.1 µH to hundreds of millihenrys. Some, meant for
special applications in power supplies, can have values as large as several henrys. In general, the
larger the inductance, the lower its frequency is in its usage. The smallest inductance values are
generally used at radio frequencies. Although inductors have many applications, the total demand
does not even remotely approach the consumption of resistors and capacitors. Inductors generally
tend to be rather bulky and expensive, especially in low-frequency applications. Industry-wide
standardization for inductors is not done to the same degree as for more frequently used devices
such as resistors and capacitors.
i i Figure 1.2.8 Inductors in series and par-

+ + allel. (a) L1 and L2 in series. (b) L1 and L2
A A B in parallel.
L1
i1 i2
v B v
L1 L2
L2
C D C
− −
(a) (b)
Copyright OUP
32 CIRCUIT CONCEPTS
EXAMPLE 1.2.4
(a) Consider a 5-µH inductor to which a current source i(t) is attached, as shown in Figure
E1.2.3(b). Sketch the inductor voltage and stored energy as a function of time.
(b) Let a voltage source v(t) shown in Figure E1.2.3(a) be applied to the 5-µH inductor
instead of the current source in part (a). Sketch the inductor current and energy stored as
a function of time.
(c) If three identical 5-µH inductors with initial current of 1 mA are connected (i) in series
and (ii) in parallel, find the equivalent inductance for each case.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Solution
(a) From the principle of duality and for the given values, it follows that the inductor-voltage
waveform is the same as the capacitor-current waveform of Example 1.2.3(a), in which
i(t) is to be replaced by v(t), and 25 and −50 mA are to be replaced by 25 and −50 mV.
The stored energy w(t) is the same as in the solution of Example 1.2.3(a).
(b) The solution is the same as that of Example 1.2.3(b), except that v(t) in mV is to be
replaced by i(t) in mA.
(c) (i) Looking at the solution of Example 1.2.3(c), part (ii),
Leq = L1 + L2 + L3 = 3 × 5 × 10−6 H = 15 µH
with an initial current i(0) = 1 mA.

(ii) Following the solution of Example 1.2.3(c), part (i),
1 1 1 1 3 5 5
= + + = or Leq = × 10−6 H = µH
Leq L1 L2 L3 5 × 10−6 3 3
with an initial current i(0) = 3 mA.
When more than one loop or circuit is present, the flux produced by the current in one
loop may link another loop, thereby inducing a current in that loop. Such loops are said to
be mutually coupled, and there exists a mutual inductance between such loops. The mutual
inductance between two circuits is defined as the flux linkage produced in one circuit by a current
of 1 ampere in the other circuit. Let us now consider a pair of mutually coupled inductors, as
shown in Figure 1.2.9. The self-inductances L11 and L22 of inductors 1 and 2, respectively, are
given by
λ11
L11 = (1.2.36)
i1
and
λ22
L22 = (1.2.37)
i2
where λ11 is the flux linkage of inductor 1 produced by its own current i1, and λ22 is the flux
linkage of inductor 2 produced by its own current i2. The mutual inductances L12 and L21 are
given by
Copyright OUP
λ12
L12 = (1.2.38)
i2
and
λ21
L21 = (1.2.39)
i1
where λ12 is the flux linkage of inductor 1 produced by the current i2 in inductor 2, and λ21 is the
flux linkage of inductor 2 produced by the current i1 in inductor 1.
If a current of i1 flows in inductor 1 while the current in inductor 2 is zero, the equivalent
fluxes are given by
λ11
ψ11 = (1.2.40)
N1
and
λ21
ψ21 = (1.2.41)
N2
where N 1 and N 2 are the number of turns of inductors 1 and 2, respectively. That part of the flux
of inductor 1 that does not link any turn of inductor 2 is known as the equivalent leakage flux of
inductor 1,
ψl1 = ψ11 − ψ21 (1.2.42)
Similarly,
ψl2 = ψ22 − ψ12 (1.2.43)
The coefficient of coupling is given by

k= k1 k2 (1.2.44)
i1 i2 = 0 i1 = 0 i2
+ ψ21 + + +
v2 v1
v1 ψl1 ψl2 v2
open open
− − − ψ12 −
N1 N2 N1 N2
turns turns turns turns
(a) (b)
i1 i2
+ ψ21 +
ψl1
v1 v2
ψl2
− −
N1 turns N2 turns
ψ12
(c)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Figure 1.2.9 Mutually coupled inductors.
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34 CIRCUIT CONCEPTS
where k1 = ψ21 /ψ11 and k2 = ψ12 /ψ22 . When k approaches unity, the two inductors are said
to be tightly coupled; and when k is much less than unity, they are said to be loosely coupled.
While the coefficient of coupling can never exceed unity, it may be as high as 0.998 for iron-core
transformers; it may be smaller than 0.5 for air-core transformers.
When there are only two inductively coupled circuits, the symbol M is frequently used to
represent the mutual inductance. It can be shown that the mutual inductance between two electric
circuits coupled by a homogeneous medium of constant permeability is reciprocal,

M = L12 = L21 = k L11 L22 (1.2.45)
The energy considerations that lead to such a conclusion are taken up in Problem 1.2.30 as an
exercise for the student.
Let us next consider the energy stored in a pair of mutually coupled inductors,
i1 λ1 i 2 λ2
Wm = + (1.2.46)
2 2
where λ1 and λ2 are the total flux linkages of inductors 1 and 2, respectively, and subscript m
denotes association with the magnetic field. Equation (1.2.46) may be rewritten as
i1 i2
Wm = (λ11 + λ12 ) + (λ22 + λ21 )
2 2
1 1 1 1
= L11 i12 + L12 i1 i2 + L22 i22 + L21 i1 i2
2 2 2 2
or
1 1
Wm = L11 i12 + Mi1 i2 + L22 i22 (1.2.47)
2 2
Equation (1.2.47) is valid whether the inductances are constant or variable, so long as the
magnetic field is confined to a uniform medium of constant permeability.
Where there are n coupled circuits, the energy stored in the magnetic field can be expressed as
n n
1
Wm = Lj k ij ik (1.2.48)
j =1 k=1
2
Going back to the pair of mutually coupled inductors shown in Figure 1.2.9, the flux-linkage
relations and the voltage equations for circuits 1 and 2 are given by the following equations, while
the resistances associated with the coils are neglected:
λ1 = λ11 + λ12 = L11 i1 + L12 i2 = L11 i1 + Mi2 (1.2.49)
λ2 = λ21 + λ22 = L21 i1 + L22 i2 = Mi1 + L22 i2 (1.2.50)

dλ1 di1 di2
υ1 = = L11 +M (1.2.51)
dt dt dt
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
dλ2 di1 di2

υ2 = =M + L22 (1.2.52)
dt dt dt
For the terminal voltage and current assignments shown in Figure 1.2.9, the coil windings
are such that the fluxes produced by currents i1 and i2 are additive in nature, and in such a case
the algebraic sign of the mutual voltage term is positive, as in Equations (1.2.51) and (1.2.52).
In order to avoid drawing detailed sketches of windings showing the sense in which each
coil is wound, a dot convention is developed, according to which the pair of mutually coupled
inductors of Figure 1.2.9 are represented by the system shown in Figure 1.2.10. The notation
Copyright OUP
is such that a current i entering a dotted (undotted) terminal in one coil induces a voltage
M[di/dt] with a positive polarity at the dotted (undotted) terminal of the other coil. If the two
currents i1 and i2 were to be entering (or leaving) the dotted terminals, the adopted convention
is such that the fluxes produced by i1 and i2 will be aiding each other, and the mutual and
self-inductance terms for each terminal pair will have the same sign; otherwise they will have
opposite signs.
Although just a pair of mutually coupled inductors are considered here for the sake of
simplicity, complicated magnetic coupling situations do occur in practice. For example, Figure
1.2.11 shows the coupling between coils 1 and 2, 1 and 3, and 2 and 3.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
M M
i1 i2 i1 i2
+ + + +
v1 L11 L22 v2 v1 L11 L22 v2
− − − −
(a) (b)
Figure 1.2.10 Dot notation for a pair of mutually coupled inductors. (a) Dots on upper terminals. (b) Dots
on lower terminals.
Figure 1.2.11 Polarity markings for complicated magnetic coupling

situations.
1 3
EXAMPLE 1.2.5
Referring to the circuit of Figure 1.2.8, let
L11 = L22 = 0.1 H
and
M = 10 mH
Determine v1 and v2 if:
(a) i1 = 10 mA and i2 = 0.
(b) i1 = 0 and i2 = 10 sin 100t mA.
(c) i1 = 0.1 cos t A and i2 = 0.3 sin(t + 30°) A.
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36 CIRCUIT CONCEPTS
Also find the energy stored in each of the above cases at t = 0.
Solution
L11 = L22 = 0.1H; M = 10 mH = 10 × 10−3 H

di1 di2 di1 di2
v1 = L11 +M ; v2 = M + L22
dt dt dt dt
1 1
Wm = energy stored = L11 i12 + L12 i1 i2 + L22 i22
2 2
(a) Since both i1 and i2 are constant and not a function of time,
v1 = 0; v2 = 0
Wm = 1
2
(0.1)(10 × 10−3 )2 + 0 + 0 = 5 × 10−6 J = 5 µJ
(b) v1 = 0 + 10 × 10−3 (10 × 100 cos 100t)10−3 = 10 cos 100t mV
v2 = 0 + 0.1(10 × 100 cos 100t)10−3 = 100 cos 100t mV = 0.1 cos 100t V
Wm = 0 + 0 + 21 (0.1)(100 sin2 100t)10−6 ; Wm = 0 at t = 0
(c) v1 = 0.1(−0.1 sin t) + 10 × 10−3 [0.3 cos(t + 30°)] = −10 sin t + 3 cos(t + 30°) mV
v2 = 10 × 10−3 (−0.01 sin t) + 0.1[0.3 cos(t + 30°)] = − sin t + 30 cos(t + 30°) mV
Wm = 21 (0.1)(0.01 cos2 t) + (10 × 10−3 )(0.1 cos t)[0.3 sin(t + 30°)] + 21 (0.1)
[0.09 sin2 (t + 30°)]; at t = 0

Wm = 2 (0.1)(0.01) + 10 × 10−3 (0.1)(0.15) + 21 (0.1) 0.09
1
4
= 1.775 µJ
Transformer
A transformer is basically a static device in which two or more stationary electric circuits are
coupled magnetically, the windings being linked by a common time-varying magnetic flux. All
that is really necessary for transformer action to take place is for the two coils to be so positioned
that some of the flux produced by a current in one coil links some of the turns of the other coil.
Some air-core transformers employed in communications equipment are no more elaborate than
this. However, the construction of transformers utilized in power-system networks is much more
elaborate to minimize energy loss, to produce a large flux in the ferromagnetic core by a current in
any one coil, and to see that as much of that flux as possible links as many of the turns as possible
of the other coils on the core.
An elementary model of a two-winding core-type transformer is shown in Figure 1.2.12.
Essentially it consists of two windings interlinked by a mutual magnetic field. The winding that
is excited or energized by connecting it to an input source is usually referred to as the primary
winding, whereas the other, to which the electric load is connected and from which the output
energy is taken, is known as the secondary winding. Depending on the voltage level at which
the winding is operated, the windings are classified as HV (high voltage) and LV (low voltage)
windings. The terminology of step-up or step-down transformer is also common if the main
purpose of the transformer is to raise or lower the voltage level. In a step-up transformer, the
primary is a low-voltage winding whereas the secondary is a high-voltage winding. The opposite
is true for a step-down transformer.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Ferromagnetic core
of infinite permeability
i1 + + i2
+ e2 = v2
v1 e1 = v1 Primary
winding
Secondary
winding
Load Resistive load
with resistance R2
− (N1 turns) (N2 turns)
− −
φ
Mutual flux
Figure 1.2.12 Elementary model of a two-winding core-type transformer (ideal transformer).
An ideal transformer is one that has no losses (associated with iron or copper) and no
leakage fluxes (i.e., all the flux in the core links both the primary and the secondary windings).
The winding resistances are negligible. While these properties are never actually achieved in
practical transformers, they are, however, approached closely. When a time-varying voltage v1
is applied to the N 1-turn primary winding (assumed to have zero resistance), a core flux φ is
established and a counter emf e1 with the polarity shown in Figure 1.2.12 is developed such that
e1 is equal to v1. Because there is no leakage flux with an ideal transformer, the flux φ also links
all N 2 turns of the secondary winding and produces an induced emf e2, according to Faraday’s
law of induction. Since v1 = e1 = dλ1 /dt = N1 dφ/dt and v2 = e2 = dλ2 /dt = N2 dφ/dt, it
follows from Figure 1.2.12 that
v1 e1 N1
= = =a (1.2.53)
v2 e2 N2
where a is the turns ratio. Thus, in an ideal transformer, voltages are transformed in the direct
ratio of the turns. For the case of an ideal transformer, since the instantaneous power input equals
the instantaneous power output, it follows that
i1 v2 N2 1
v1 i1 = v2 i2 or = = = (1.2.54)
i2 v1 N1 a
which implies that currents are transformed in the inverse ratio of the turns.
Equivalent circuits viewed from the source terminals, when the transformer is ideal, are
shown in Figure 1.2.13. As seen from Figure 1.2.13(a), since v1 = (N1 /N2 )v2 , i1 = (N2 /N1 )i2 ,
and v2 = i2 RL , it follows that
2
v1 N1
= RL = a 2 RL = RL (1.2.55)
i1 N2
where RL is the secondary-load resistance referred to the primary side. The consequence of
Equation (1.2.55) is that a resistance RL in the secondary circuit can be replaced by an equivalent
resistance RL in the primary circuit in so far as the effect at the source terminals is concerned. The
reflected resistance through a transformer can be very useful in resistance matching for maximum
power transfer, as we shall see in the following example. Note that the circuits shown in Figure
1.2.13 are indistinguishable viewed from the source terminals.
--`,,,``,,`,```,``,``
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38 CIRCUIT CONCEPTS
i1 i2 Figure 1.2.13 Equivalent circuits viewed from source

+ + terminals when the transformer is ideal.
+
v1 v2 RL
−
− −
N1 N2
Ideal transformer
(a)
( )
i1 N1 2 i2
RL′ = R
+ N2 L
+
v1
−
−
N1 N2
(b)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
i1
+
( )
+ N1 2
v1 RL′ = R = a2RL
− N2 L
−
(c)
EXAMPLE 1.2.6
√
Consider a source of voltage v(t) = 10 2 sin 2t V, with an internal resistance of 1800 -. A
transformer that can be considered ideal is used to couple a 50-- resistive load to the source.
(a) Determine the primary to secondary turns ratio of the transformer required to ensure
maximum power transfer by matching the load and source resistances.
(b) Find the average power delivered to the load.
Solution
By considering a constant voltage source (with a given internal resistance RS ) connected to a

variable-load resistance RL , as shown in Figure E1.2.6(a), for a value of RL equal to RS given
by Equation (1.2.13), the maximum power transfer to the load resistance would occur when the
load resistance is matched with the source resistance.
(a) For maximum power transfer to the load, RL (i.e., RL referred to the primary side of the
transformer) should be equal to RS , which is given to be 1800 -. Hence,
RL = a 2 RL = 50a 2 = 1800 or a 2 = 36, or a = 6.
Thus N1 /N2 = 6 [see Figure E1.2.6(b)].
Copyright OUP
1.3 KIRCHHOFF’S LAWS 39
(b) By voltage division [see Figure E1.2.6(c)] one gets

1800 √ √
vL = (10 2 sin 2t) = (5 2 sin 2t) V
1800 + 1800
which has an rms value of 5 V. Hence, the average power delivered to the load resistance
(RL or RL ) is
(VL RMS )2 25
Pav =
= W∼ = 13.9 mW
1800 1800
√ √
Note that vL across RL is (5 2/6) sin 2t V, and iL through RL is (5 2/6 × 50) sin 2t
A. The rms value of iL is then 5/300 A, and the rms value of vL is 5/6 V. Thus,
5 5
Pav = × W∼
= 13.9 mW
300 6
which is also the same as
Pav = IL2 RMS RL = VL2 RMS /RL
+ RS
v RL
−
(a)
RS = 1800 Ω iL′ N : N iL
1 2
+ +
+
10 2 sin 2t V υ L′ υL RL = 50 Ω
−
− −
Source Ideal transformer Load
(b)
RS = 1800 Ω iL′
+
+
10 2 sin 2t V υ L′ RL′ = 1800 Ω
−
−
(c)
Figure E1.2.6
1.3 KIRCHHOFF’S LAWS

The basic laws that must be satisfied among circuit currents and circuit voltages are known as
Kirchhoff’s current law (KCL) and Kirchhoff’s voltage law (KVL). These are fundamental for
the systematic analysis of electric circuits.
KCL states that, at any node of any circuit and at any instant of time, the sum of all currents
entering the node is equal to the sum of all currents leaving the node. That is, the algebraic sum of
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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40 CIRCUIT CONCEPTS
all currents (entering or leaving) at any node is zero, or no node can accumulate or store charge.
Figure 1.3.1 illustrates Kirchhoff’s current law, in which at node a,
i 1 − i2 + i 3 + i 4 − i 5 = 0 or − i 1 + i 2 − i3 − i 4 + i5 = 0
or i1 + i3 + i4 = i2 + i5 (1.3.1)
Note that so long as one is consistent, it does not matter whether the currents directed toward the
node are considered positive or negative.
KVL states that the algebraic sum of the voltages (drops or rises) encountered in traversing
any loop (which is a closed path through a circuit in which no electric element or node is
encountered more than once) of a circuit in a specified direction must be zero. In other words, the
sum of the voltage rises is equal to the sum of the voltage drops in a loop. A loop that contains no
other loops is known as a mesh. KVL implies that moving charge around a path and returning to the
starting point should require no net expenditure of energy. Figure 1.3.2 illustrates the Kirchhoff’s
voltage law.
For the mesh shown in Figure 1.3.2, which depicts a portion of a network, starting at node a and
returning back to it while traversing the closed path abcdea in either clockwise or anticlockwise
direction, Kirchhoff’s voltage law yields
− v1 + v2 − v3 − v4 + v5 = 0 or v1 − v 2 + v 3 + v 4 − v 5 = 0
or v1 + v3 + v4 = v2 + v5 (1.3.2)
Note that so long as one is consistent, it does not matter whether the voltage drops are considered
positive or negative. Also notice that the currents labeled in Figure 1.3.2 satisfy KCL at each of
the nodes.
Figure 1.3.1 Illustration of Kirchoff’s current law.

i4 i5
i1
Node a
i3
i2
Figure 1.3.2 Illustration of Kirchhoff’s

i2 + i3 voltage law.
c
i2 Bo i3
− vx3 i3 + i4
3 +
− d
−
x2
v2
Bo
b + Av2 = v4
i1 − i2 + Dependent source
i1 i4
+ e
v1 5 i4 − i5
− Box + i5
a − v5
i1 − i5
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
In a network consisting of one or more energy sources and one or more circuit elements,
the cause-and-effect relationship in circuit theory can be studied utilizing Kirchhoff’s laws and
volt-ampere relationships of the circuit elements. While the cause is usually the voltage or current
source exciting the circuit, the effect is the voltages and currents existing in various parts of
the network.
EXAMPLE 1.3.1
Consider the circuit shown in Figure E1.3.1 and determine the unknown currents using KCL.
Figure E1.3.1
iS = 10 A i1 = 5 A
Node a
Node b
+
−
i4 = 3 A i5 = ? i2 = 4 A i3 = ?
Node c
Solution
Let us assign a + sign for currents entering the node and a − sign for currents leaving the node.
Applying KCL at node a, we get
+ i S − i 1 − i4 − i 5 = 0
or
10 − 5 − 3 − i5 = 0 or i5 = 2 A
Applying KCL at node b, we get
+ i 1 − i 2 − i3 = 0
or
5 − 4 − i3 = 0 or i3 = 1 A
The student is encouraged to rework this problem by:

(a) Assigning a − sign for currents entering the node and a + sign for currents leaving the
node; and
(b) Applying the statement that the sum of the currents entering a node is equal to the sum
of the currents leaving that node.
--`,,,``,,`,```,``,`````,```,```-
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42 CIRCUIT CONCEPTS
EXAMPLE 1.3.2
For the circuit shown in Figure E1.3.2, use KCL and KVL to determine i1 , i2 , vbd and vx . Also,
find veb .
−3 A Figure E1.3.2
a υab = 5 V ibf f
+ − b c
+ 3V −
i2 = ?
i1 = ?
+ +
+ υbd = ? υx = ?
20 V −
− −
d
+
10 A 8V − 8A
e
Solution
Using KCL at node c, we get
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
i1 = 8 + (−3 = 5 A
Using KCL at node f, we have
ibf = i1 − (−3) = 5 + 3 = 8 A
Applying KCL at node b, we get
10 = i2 + ibf = i2 + 8 or i2 = 2 A
Using KVL around the loop abdea in the clockwise direction, we have
vab + vbd + vde + vea = 0
or
5 + vbd + 8 − 20 = 0 or vbd = 20 − 8 − 5 = 7 V
Note that in writing KVL equations with + and − polarity symbols, we write the voltage with a
positive sign if the + is encountered before the − and with a negative sign if the − is encountered
first as we move around the loop.
Applying KVL around the loop abfcea in the clockwise direction, we get
vab + vbf + vf c + vce + vea = 0
or
5 + 0 + 3 + vx + (−20) = 0 or vx = 20 − 3 − 5 = 12 V
Note that a direct connection between b and f implies ideal connection, and hence no voltage
between these points.
The student is encouraged to rewrite the loop equations by traversing the closed path in the
anticlockwise direction.
Noting that veb = ved + vdb , we have
Copyright OUP
veb = −8 − 7 = −15 V
Alternatively,
veb = vea + vab = −20 + 5 = −15 V
or
veb = vec + vcf + vf b = −vx + vcf + 0 = −12 − 3 = −15 V
The student should observe that vbe = −veb = 15 V and node b is at a higher potential than
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
node e.
EXAMPLE 1.3.3
Referring to Figure 1.3.2, let boxes 2, 3, and 5 consist of a 0.2-H inductor, a 5-- resistor, and a
0.1-F capacitor, respectively. Given A = 5, and v1 = 10 sin 10t, i2 = 5 sin 10t, and i3 = 2 sin
10t − 4 cos 10t, find i5.
Solution
From Equation (1.2.19),

di2 d
v2 = L = 0.2 (5 sin 10t) = 10 cos 10t V
dt dt
v3 = Ri3 = 5(2 sin 10t − 4 cos 10t) = 10 sin 10t − 20 cos 10t V
v5 = v1 + v3 + v4 − v2 = v1 + v3 + 5v2 − v2
= 10 sin 10t + (10 sin 10t − 20 cos 10t) + 4(10 cos 10t)
= 20 sin 10t + 20 cos 10t V

dv5 d
i5 = C = 0.1 (20 sin 10t + 20 cos 10t)
dt dt
= 20 cos 10t − 20 sin 10t A
Note the consistency of voltage polarities and current directions in Figure 1.3.2.
EXAMPLE 1.3.4
Consider the network shown in Figure E1.3.4(a).
(a) Find the voltage drops across the resistors and mark them with their polarities on the
circuit diagram.
(b) Check whether the KVL is satisfied, and determine Vbf and Vec.
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44 CIRCUIT CONCEPTS
(c) Show that the conservation of power is satisfied by the circuit.

a b c d Figure E1.3.4
+ R1 = 10 Ω R2 = 40 Ω R3 = 20 Ω +
12 V 24 V
− I −
f e
R4 = 50 Ω
(a)
− 1V + b − 4V + c − 2V +
a d
+ +
12 V 24 V
− + 5V − −
f e
(b)
Solution
(a) From Ohm’s law, the current I is given by

24 − 12 12
I= = = 0.1 A
10 + 40 + 20 + 50 120
Therefore, voltage drops across the resistors are calculated as follows:
Vba = I R1 = 0.1 × 10 = 1 V
Vcb = I R2 = 0.1 × 40 = 4 V
Vdc = I R3 = 0.1 × 20 = 2 V
Vf e = I R4 = 0.1 × 50 = 5 V
These are shown in Figure E1.3.4(b) with their polarities. Note that capital letters are
used here for dc voltages and currents.
(b) Applying the KVL for the closed path edcbafe, we get
− 24 + 2 + 4 + 1 + 12 + 5 = 0
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
which confirms that the KVL is satisfied,
Vbf = Vba + Vaf = 1 + 12 = 13 V

Vec = Ved + Vdc = −24 + 2 = −22 V
(c) Power delivered by 24-V source = 24 × 0.1 = 2.4 W

Power delivered by 12-V source = −12 × 0.1 = −1.2 W
Power absorbed by resistor R1 = (0.1)2 × 10 = 0.1 W
Copyright OUP

Power delivered by sources = 2.4 − 1.2 = 1.2 W
Power absorbed by resistors R1 , R2 , R3 , and R4 = 0.1 + 0.4 + 0.2 + 0.5 = 1.2 W
The conservation of power is satisfied by the circuit.
EXAMPLE 1.3.5
Given the network in Figure E1.3.5,
(a) Find the currents through resistors R1 , R2 , and R3 .
(b) Compute the voltage V1 .
(c) Show that the conservation of power is satisfied by the circuit.
Node 1 V1 Figure E1.3.5
I1 I2 I3
12 A R1 = 6Ω R2 = 4Ω R3 = 12 Ω 6A
Ground node
Solution
(a) Applying the KCL at node 1, we have

V1 V1 V1 1 1 1 V1
12 = + + + 6 = V1 + + +6= +6
R1 R2 R3 6 4 12 2
Therefore, V1 = 12 V. Then,
12
I1 = =2A
6
12
I2 = =3A
4
12
I3 = =1A
12
(b) V1 = 12 V
(c) Power delivered by 12-A source = 12 × 12 = 144 W
Power delivered by 6-A source = −6 × 12 = −72 W
Power absorbed by resistor R1 = I12 R1 = (2)2 6 = 24 W
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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46 CIRCUIT CONCEPTS

Power delivered by sources = 144 − 72 = 72 W
Power absorbed by resistors R1 , R2 , and R3 = 24 + 36 + 12 = 72 W
The conservation of power is satisfied by the circuit.
EXAMPLE 1.3.6
Consider the network shown in Figure E1.3.6 containing a voltage-controlled source producing
the controlled current ic = gv, where g is a constant with units of conductance, and the control
voltage happens to be the terminal voltage in this case.
(a) Obtain an expression for Req = v/ i.
(b) For (i) gR = 1/2, (ii) gR = 1, and (iii) gR = 2, find Req and interpret what it means in
each case.
Node 1 Figure E1.3.6
i
+
v R iR ic = gv
−
Node 2
Solution
(a) Applying the KCL at node 1, we get

v
i + ic = iR =
R
Therefore,
v v 1 − gR
i= − ic = − gv = v
R R R
Then,
v R
Req = =
i 1 − gR
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(b) (i) For gR = 1/2, Req = 2R. The equivalent resistance is greater than R; the internal
controlled source provides part of the current through R, thereby reducing the input
current i for a given value of v. When i < v/R, the equivalent resistance is greater
than R.
Copyright OUP
1.4 METERS AND MEASUREMENTS 47
(ii) For gR = 1, Req → ∞. The internal controlled source provides all of the current
through R, thereby reducing the input current i to be zero for a given value of v.
(iii) For gR = 2, Req = −R, which is a negative equivalent resistance. This means that
the controlled source provides more current than that going through R; the current
direction of i is reversed when v > 0. However, the relation v = Req i is satisfied at
the input terminals.
1.4 METERS AND MEASUREMENTS

The subject of electrical measurements is such a large one that entire books have been written on
the topic. Only a few basic principles will be introduced here. Practical measurements are made
with real instruments, which in general disturb the operation of a circuit to some extent when they
are connected. Measurements may be affected by noise, which is undesirable randomly varying
signals.
Voltmeter
In order to measure the potential difference between two terminals or nodes of a circuit, a voltmeter
is connected across these two points. A practical voltmeter can usually be modeled as a parallel
combination of an ideal voltmeter (through which no current flows) and a shunt resistance RV, as
shown in Figure 1.4.1. The internal resistance RV of an ideal voltmeter is infinite, while its value
in practice is of the order of several million ohms. There are what are known as dc voltmeters
and ac voltmeters. An ac voltmeter usually measures the rms value of the time-varying voltage.
+ Figure 1.4.1
+
Ideal
Rv
voltmeter
−
−
Practical voltmeter
EXAMPLE 1.4.1
An electromechanical voltmeter with internal resistance of 1 k- and an electronic voltmeter with
internal resistance of 10 M- are used separately to measure the potential difference between A
and the ground of the circuit shown in Figure E1.4.1. Calculate the voltages that will be indicated
by each of the two instruments and the percentage error in each case.
A Figure E1.4.1
+ 10 kΩ +
2V 10 kΩ Rv
− −
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Ground Voltmeter
Copyright OUP
48 CIRCUIT CONCEPTS
Solution
When no instrument is connected, by voltage division, V + AG = 1 V. With internal resistance

RV of the instrument, the voltmeter reading will be

RV 104 RV · 104 RV · 104
VA = 2.0 = 2 + 10 4
RV 104 + 104 RV + 104 RV + 104
RV · 104
=2
2 × 104 RV + 108
With RV = 1000,
2 × 107 2 2
VA = = = = 0.1667 V
2 × 10 + 10
7 8 2 + 10 12
for which the percent error is
1 − 0.1667
× 100 = 83.33%
1
With RV = 107 -,
2 × 1011 2000
VA = = = 0.9995 V
2 × 1011 + 108 2000 + 1
for which the percent error is
1 − 0.9995
× 100 = 0.05%
1
One can see why electronic voltmeters which have relatively very large internal resistance are
often used.
Ammeter
In order to measure the current through a wire or line of a circuit, an ammeter is connected in
series with the line. A practical ammeter can usually be modeled as a series combination of an
ideal ammeter and an internal resistance RI. The potential difference between the two terminals
of an ideal ammeter is zero, which corresponds to zero internal resistance. There are what are
known as dc ammeters and ac ammeters. An ac ammeter usually measures the rms value of the
time-varying current. Note that for the ammeter to be inserted for measuring current, the circuit
has to be broken, whereas for the voltmeter to be connected for measuring voltage, the circuit
need not be disassembled.
Multimeters that measure multiple ranges of voltage and current are available in practice.
Ohmmeters measure the dc resistance by the use of Ohm’s law. A multimeter with scales for
volts, ohms, and milliamperes is known as VOM. An ohmmeter should not be used to measure
the resistance of an electronic component that might be damaged by the sensing current.
Instrument Transformers
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
These are generally of two types, potential transformers (PTs) and current transformers (CTs).
They are designed in such a way that the former may be regarded as having an ideal potential
ratio, whereas the latter has an ideal current ratio. The accuracy of measurement is quite important
for ITs that are commonly used in ac circuits to supply instruments, protective relays, and control
devices.
Copyright OUP
1.4 METERS AND MEASUREMENTS 49
PTs are employed to step down the voltage to a suitable level, whereas CTs (connected in
series with the line) are used to step down the current for metering purposes. Often the primary of
a CT is not an integral part of the transformer itself, but is a part of the line whose current is being
measured. In addition to providing a desirable low current in the metering circuit, the CT isolates
the meter from the line, which may be at a high potential. Note that the secondary terminals
of a CT should never be open-circuited under load. The student is encouraged to reason and
justify this precaution. One of the most useful instruments for measuring currents in the ampere
range is the clip-on ammeter combining the CT with one-turn primary and the measurement
functions.
Oscilloscope
To measure time-varying signals (voltages and currents), an instrument known as an oscilloscope
is employed. It can be used as a practical electronic voltmeter which displays a graph of voltage
as a function of time. Such a display allows one not only to read off the voltage at any instant of
time, but also to observe the general behavior of the voltage as a function of time. The horizontal
and vertical scales of the display are set by the oscilloscope’s controls, such as 5 ms per each
horizontal division and 50 V per each vertical division. For periodic waveforms, the moving
light spot repeatedly graphs the same repetitive shape, and the stationary waveform is seen. For
nonperiodic cases, a common way of handling is to cause the oscilloscope to make only one single
graph, representing the voltage over a single short time period. This is known as single-sweep
operation. Since the display lasts for only a very short time, it may be photographed for later
inspection.
Digital meters are generally more accurate and can be equipped with more scales and broader
ranges than analog meters. On the other hand, analog meters are generally less expensive and give
an entire range or scale of reading, which often could be very informative. A digital oscilloscope
represents the combination of analog and digital technologies. By digital sampling techniques,
the oscilloscope trace is digitized and stored in the digital memory included with the digital
oscilloscope. Digital oscilloscopes are generally more costly than analog ones, but their capability
in the analysis and processing of signals is vastly superior.
Wheatstone Bridge
Null measurements are made with bridge circuits and related configurations. They differ from
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
direct measurements in that the quantity being measured is compared with a known reference
quantity. The balancing strategy avoids undesirable interaction effects and generally results in
more accurate measurement than the direct one.
By far the most common is the Wheatstone bridge designed for precise measurement of
resistance. Figure 1.4.2 shows the basic circuit in which the measurement of an unknown resistance
Rx is performed by balancing the variable resistances Ra and Rb until no current flows through
meter A. Under this null condition,
Ra
Rx = · Rs (1.4.1)
Rb
where Rs is the known standard resistance. There are other bridge-circuit configurations to
measure inductance and capacitance. Typical instruments utilizing bridge circuits are found in
strain gauges measuring stress and in temperature measuring systems with thermocouples and
thermistors.
Copyright OUP
50 CIRCUIT CONCEPTS
Figure 1.4.2 Basic Wheatstone bridge circuit for resistance

measurement.
Rb Ra
V
A
Rs Rx
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EXAMPLE 1.4.2
Redraw the Wheatstone bridge circuit of Figure 1.4.2 and show that Equation (1.4.1) holds good
for the null condition when the meter A reads zero current.
Solution
Figure E1.4.2 Figure 1.4.2 redrawn.
Rb Rs
P vPQ = 0 Q
v
Ra Rx
Under null condition, VP Q = 0, or P and Q are at the same potential. Using the voltage division
principle,

V V
Rb = Rs
Rb + R a Rs + R x
yielding Rx Rb = Ra Rs , which is the same as Equation (1.4.1).
1.5 ANALOGY BETWEEN ELECTRICAL AND OTHER NONELECTRIC

PHYSICAL SYSTEMS
Systems such as those encountered in mechanics, thermodynamics, and hydraulics can be repre-
sented by analogous electric networks, from the response of which the system characteristics can
be investigated. The analogy, of course, is a mathematical one: that is, two systems are analogous
to each other if they are described by similar equations. The analogous electric quantities for a
mechanical system are listed in Table 1.5.1.
Consider a tank filled with water, as shown in Figure 1.5.1, with input flow rate Fi and output
flow rate Fo = h/R, where h is the fluid level or head and R is related to the diameter of the
pipe, denoting the fluid resistance. Let A be the cross-sectional area of the tank. We may think of
the fluid as being analogous to charge, and the fluid flow as being analogous to current. Then, in
effect, the water tank acts as a capacitor storing charge, which is fluid in this case. This analogy
is illustrated in Table 1.5.2.
Copyright OUP
1.5 ANALOGY BETWEEN ELECTRICAL AND OTHER NONELECTRICPHYSICAL SYSTEMS 51
TABLE 1.5.1 Mechanical-Electrical Analogs
Mathematical Force–Current Force–Voltage

Quantity Unit Symbol Relation Analog Analog
Force N f (t) ··· i(t) v(t)

Velocity m/s u(t) ··· v(t) i(t)
Mass kg f f = M du C L
M dt
(Newton’s law)
u
Cm = 1
Compliance m/N K f = C1m u dt L C
(= 1/stiffness) f (Hooke’s law)
u
B
f
Viscous friction N · s/m f = Bu G = 1/R R
or damping
u
Figure 1.5.1 Simple hydraulic system.

Flow in Fi
Water h
tank
Pipe Flow out Fo
TABLE 1.5.2 Analogy Between Electrical and Hydraulic Systems
Quantity Hydraulic System Electrical System
Flow Output flow rate Fo Current i

Potential Fluid level h Voltage v
Resistance Fluid resistance R Electrical resistance R
Energy storage element Fluid storage parameter A Capacitance C
Volume of fluid (or charge) V = Ah q = Cv
Next, let us consider heat flow from an enclosure with a heating system to the outside of
the enclosure, depending upon the temperature difference ?T between the inside and outside of
the enclosure. The heat capacity of the enclosure is analogous to capacitance, in the sense that
the enclosure retains part of the heat produced by the heating system. One can then infer the
analogy between electrical and thermal systems given in Table 1.5.3.
The heat flow, per Newton’s law of cooling in a very simplified form, can be considered to be
proportional to the rate of change of temperature with respect to distance. An approximate linear
relationship between heat flow and change in temperature can be expressed as
--`,,,``,,`,```,``,`````,```,```-`-`,,
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52 CIRCUIT CONCEPTS
TABLE 1.5.3 Analogy Between Thermal and Electrical Systems
Thermal System Electrical System
Heat Charge
Heat flow Current
Temperature difference Voltage
Ambient temperature Ground reference
Heat capacity Capacitance
Thermal resistance Electrical resistance
k
Heat flow ∼ = ?T (1.5.1)
?x
where k is a constant, and k/?x in thermal systems is analogous to conductance in electrical
systems. Then Newton’s law of cooling, in a very simplified form, can be seen to be a thermal
version of Ohm’s law.
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1.6 LEARNING OBJECTIVES
The learning objectives of this chapter are summarized here, so that the student can check whether
he or she has accomplished each of the following.
• Review of basic electrical quantities.
• Application of Coulomb’s law, Ampere’s law, and the Biot–Savart law.
• Energy and power computations in a circuit consisting of a source and a load.
• Calculation of average and RMS values for periodic waveforms, and time constant for
exponential waveforms.
• i–v relationships for ideal resistors, capacitors, and inductors; duality principle.
• Reduction of series and parallel combinations of resistors, capacitors, and inductors.
• Solution of simple voltage and current divider circuits.
• Computation of power absorbed by a resistor, and energy stored in a capacitor or inductor.
• Maximum power transfer and matched load.
• Volt-ampere equations and energy stored in coupled inductors.
• Ideal transformer and its properties.
• Application of Kirchhoff’s current and voltage laws to circuits.
• Measurement of basic electrical parameters.
• Analogy between electrical and other nonelectric physical systems.
1.7 PRACTICAL APPLICATION: A CASE STUDY
Resistance Strain Gauge

Mechanical and civil engineers routinely employ the dependence of resistance on the physical
dimensions of a conductor to measure strain. A strain gauge is a device that is bonded to the
surface of an object, and whose resistance varies as a function of the surface strain experienced
by the object. Strain gauges can be used to measure strain, stress, force, torque, and pressure.
Copyright OUP
PROBLEMS 53
The resistance of a conductor with a circular cross-sectional area A, length l, and conductivity
σ is given by Equation (1.2.2),
l
R=
σA
Depending on the compression or elongation as a consequence of an external force, the length
changes, and hence the resistance changes. The relationship between those changes is given by
the gauge factor G,
?R/R
G=
?l/ l
in which the factor ?l/ l, the fractional change in length of an object, is known as the strain.
Alternatively, the change in resistance due to an applied strain ε(= ?l/ l) is given by
?R = R0 Gε
where R0 is the zero-strain resistance, that is, the resistance of the strain gauge under no strain.
A typical gauge has R0 = 350 - and G = 2. Then for a strain of 1%, the change in resistance is
?R = 7 -. A Wheatstone bridge as presented in Section 1.4 is usually employed to measure the
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small resistance changes associated with precise strain determination.
A typical strain gauge, shown in Figure 1.7.1, consists of a metal foil (such as nickel–copper
alloy) which is formed by a photoetching process in multiple conductors aligned with the direction
of the strain to be measured. The conductors are usually bonded to a thin backing made out of
a tough flexible plastic. The backing film, in turn, is attached to the test structure by a suitable
adhesive.
Metal foil
Figure 1.7.1 Resistance strain gauge and circuit
symbol.
Direction of
strain to
be measured
R
Flexible plastic
backing film Copper-plated solder tabs
for electrical connections
PROBLEMS
1.1.1 Consider two 1-C charges separated by 1 m in free q = 2 µC that is placed midway between the two
space. Show that the force exerted on each is about charges.
one million tons. 1.1.4 The electric field intensity due to a point charge in
√
*1.1.2 Point charges, each of 4πε0 C, are located at free space is given to be
the vertices of an equilateral triangle of side a. √
(−āx − āy + āz )/ 12V/m at (0,0,1)
Determine the electric force on each charge.
1.1.3 Two charges of equal magnitude 5 µC but opposite
and 6 āz at (2,2,0)
sign are separated by a distance of 10 m. Find Determine the location and the value of the point
the net force experienced by a positive charge charge.
*Complete solutions for problems marked with an asterisk can be found on the CD-ROM packaged with this book.
Copyright OUP
54 CIRCUIT CONCEPTS
1.1.5 A wire with n = 1030 electrons/m3 has an area 1.1.14 A magnetic force exists between two adjacent,
of cross section A = 1 mm2 and carries a current parallel current-carrying wires. Let I1 and I2 be the
i = 50 mA. Compute the number of electrons that currents carried by the wires, and r the separation
pass a given point in 1 s, and find their average between them. Making use of the result of Problem
velocity. 1.1.13, find the force between the wires.
1.1.6 A beam containing two types of charged particles 1.1.15 A point charge Q1 = −5 nC is located at (6, 0, 0).
is moving from A to B. Particles of type I with Compute the voltage vba between two points a(1,
charge +3q, and those of type II with charge 0, 0) and b(5, 0, 0). Comment on whether point a
−2q (where −q is the charge of an electron given is at a higher potential with respect to point b.
by −1.6 × 10−19 C) flow at rates of 5 × 1015 /s 1.1.16 A charge of 0.1 C passes through an electric source
and 10 × 1015 /s, respectively. Evaluate the current of 6 V from its negative to its positive terminals.
flowing in the direction from B to A. Find the change in energy received by the charge.
1.1.7 A charge q(t) = 50 + 1.0t C flows into an electric Comment on whether the charge has gained or lost
component. Find the current flow. energy, and also on the sign to be assigned to the
*1.1.8 A charge variation with time is given in Figure change of energy.
P1.1.8. Draw the corresponding current variation 1.1.17 The voltage at terminal a relative to terminal b of
with time. an electric component is v(t) = 20 cos 120π t
1.1.9 A current i(t) = 20 cos(2π × 60)t A flows V. A current i(t) = −4 sin 120πt A flows into
through a wire. Find the charge flowing, and the terminal a. From time t1 to t2 , determine the total
number of electrons per second that are passing energy flowing into the component. In particular,
some point in the wire. find the energy absorbed when t2 = t1 + 1/15.
1.1.10 Consider a current element I1 d l¯1 = 10 dzāz kA *1.1.18 Obtain the instantaneous power flow into the com-
located at (0,0,1) and another I2 d l¯2 = 5dx āx ponent of Problem 1.1.17, and comment on the
kA located at (0,1,0). Compute d F̄21 and d F̄12 sign associated with the power.
√ =
experienced by elements 1 and 2, respectively. 1.1.19 A residence is supplied with a voltage v(t)
√
1.1.11 Given B̄ = (y āx − x āy )/(x 2 + y 2 ) T, determine 110 2 cos 120πt V and a current i(t) = 10 2cos
the magnetic force on the current element I d l¯ = 120πt A. If an electric meter is used to measure the
5 × 0.001āz A located at (3,4,2). average power, find the meter reading, assuming
that the averaging is done over some multiple of
*1.1.12 In a magnetic field B̄ = B0 (āx − 2āy + 2āz ) 1/ s.
60
T at a point, let a test charge have a velocity of
v0 (āx + āy − āz ). Find the electric field Ē at that 1.1.20 A 12-V, 115-Ah automobile storage battery is used
point if the acceleration experienced by the test to light a 6-W bulb. Assuming the battery to be a
charge is zero. constant-voltage source, find how long the bulb
can be lighted before the battery is completely
1.1.13 Consider an infinitely long, straight wire (in free
discharged. Also, find the total energy stored in
space) situated along the z-axis and carrying cur-
the battery before it is connected to the bulb.
rent of I A in the positive z-direction. Obtain an
expression for B̄ everywhere. (Hint: Consider a 1.2.1 In English units the conductor cross-sectional area
circular coordinate system and apply the Biot– is expressed in circular mils (cmil). A circle with
Savart law.) diameter d mil has an area of (π/4)d 2 sq. mil,
Charge q coulombs
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
50 Periodic
every 16 s
25
0 12 14 16
t, seconds
−4 −2 2 4 6 8 10 18 20 22 24 26 28
−25
−50
Figure P1.1.8
Copyright OUP
PROBLEMS 55
or d 2 cmil. The handbook for aluminum electrical *1.2.3 A copper conductor has 12 strands with each
conductors lists a dc resistance of 0.01558 - per strand diameter of 0.1328 in. For this conductor,
1000 ft at 20°C for Marigold conductor, whose find the total copper cross-sectional area in cmil
size is 1113 kcmil. (see Problem 1.2.1 for definition of cmil), and
(a) Verify the dc resistance assuming an increase calculate the dc resistance at 20°C in (ohms/km),
in resistance of 3% for spiraling of the strands. assuming a 2% increase in resistance due to spi-
raling.
(b) Calculate the dc resistance at 50°C, given
1.2.4 A handbook lists the 60-Hz resistance at 50°C of a
that the temperature constant for aluminum
is 228.1°C. 900-kcmil aluminum conductor as 0.1185 -/mile.
If four such conductors are used in parallel to form
(c) If the 60-Hz resistance of 0.0956 -/mile at a line, determine the 60-Hz resistance of this line
50°C is listed in the handbook, determine the in -/km per phase at 50°C.
percentage increase due to skin effect or fre-
1.2.5 Determine Req for the circuit shown in Figure
quency.
P1.2.5 as seen from terminals A–B.
1.2.2 MCM is the abbreviation for 1 kcmil. (See Prob-
1.2.6 Viewed from terminals A–B, calculate Req for the
lem 1.2.1 for a definition of cmil.) Data for com-
circuit given in Figure P1.2.6.
mercial-base aluminum electrical conductors list
a 60-Hz resistance of 0.0880 -/km at 75°C for a 1.2.7 Find Req for the circuit of Figure P1.2.7.
795-MCM conductor. *1.2.8 Determine Req for the circuit of Figure P1.2.8 as
(a) Determine the cross-sectional conducting area seen from terminals A–B.
of this conductor in m2 . 1.2.9 A greatly simplified model of an audio system
(b) Calculate the 60-Hz resistance of this con- is shown in Figure P1.2.9. In order to transfer
ductor in -/km at 50°C, given a temperature maximum power to the speaker, one should select
constant of 228.1°C for aluminum. equal values of RL and RS . Not knowing that
Figure P1.2.5
2Ω
A
2Ω
2Ω
2Ω 1Ω
A Figure P1.2.6
3Ω
5Ω 1Ω
1Ω
3Ω
4Ω 2Ω
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Copyright OUP
56 CIRCUIT CONCEPTS
the internal resistance of the amplifier is RS = 8 -, (b) Plot the power dissipated by the load as a func-
one has connected a mismatched speaker with tion of the load resistance, and determine the
RL = 16 -. Determine how much more power value of RL corresponding to the maximum
could be delivered to the speaker if its resistance power absorbed by the load.
were matched to that of the amplifier. 1.2.11 A practical voltage source is represented by an
1.2.10 For the circuit of Figure P1.2.10: ideal voltage source of 30 V along with a series
internal source resistance of 1.2 -. Compute the
(a) Find an expression for the power absorbed by smallest load resistance that can be connected to
the load as a function of RL . the practical source such that the load voltage
A Figure P1.2.7
4Ω
3Ω
Reυ ⇒ 8Ω 4Ω
2Ω 2Ω
A Figure P1.2.8
2Ω 2Ω
4Ω 2Ω
4Ω
RS Figure P1.2.9
+
+
VS RL VL
−
−
Amplifier Speaker
(source) (load)
Figure P1.2.10
+
500 Ω
+
10 V VL RL
−
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
−
Source Load
Copyright OUP
PROBLEMS 57
would not drop by more than 2% with respect to Show the current and voltage distribution clearly
the source open-circuit voltage. in all branches of the original circuit configuration.
*1.2.12 A practical current source is represented by an *1.2.18 Determine the voltages Vx using voltage division
ideal current source of 200 mA along with a shunt and equivalent resistor reductions for the circuits
internal source resistance of 12 k-. Determine the shown in Figure P1.2.18.
percentage drop in load current with respect to the 1.2.19 Find the currents Ix using current division and
source short-circuit current when a 200-- load is equivalent resistor reductions for the networks
connected to the practical source. given in Figure P1.2.19.
1.2.13 Let v(t) = Vmax cos ωt be applied to (a) a pure 1.2.20 Considering the circuit shown in Figure P1.2.20,
resistor, (b) a pure capacitor (with zero initial ca- sketch v(t) and the energy stored in the capacitor
pacitor voltage, and (c) a pure inductor (with zero as a function of time.
initial inductor current). Find the average power 1.2.21 For the capacitor shown in Figure P1.2.21 con-
absorbed by each element. nected to a voltage source, sketch i(t) and w(t).
√
1.2.14 If v(t) = 120 2 sin 2π × 60t V is applied to *1.2.22 The energy stored in a 2-µF capacitor is given by
terminals A–B of problems 1.2.5, 1.2.6, 1.2.7, and wc (t) = 9e−2t µJ for t ≥ 0. Find the capacitor
1.2.8, determine the power in kW converted to heat voltage and current at t = 1 s.
in each case. 1.2.23 For a parallel-plate capacitor with plates of area
1.2.15 With a direct current of I A, the power expended as A m2 and separation d m in air, the capacitance
heat in a resistor of R- is constant, independent of in farads may be computed from the approximate
time, and equal to I 2 R. Consider Problem 1.2.14 relation
and find in each case the effective value of the A 8.854 × 10−12 A
current to give rise to the same heating effect as in C ≈ ε0
=
d d
the ac case, thereby justifying that the rms value Compute the area of each plate needed to develop
is also known as the effective value for periodic C = 1 pF for d = 1 m. (You can appreciate
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
waveforms. why large values of capacitance are constructed
1.2.16 Consider Problem 1.2.14 and obtain in each case a as electrolytic capacitors, and modern integrated-
replacement of the voltage source by an equivalent circuit technology is utilized to obtain a wide va-
current source at terminals A–B. riety of capacitance values in an extremely small
1.2.17 Consider Problem 1.2.5. Let VAB = 120 V (rms). space.)
+ −
6V
1Ω 2Ω
3Ω + +
2Ω Vx Vx 3Ω 2Ω 2Ω
+
12 V − −
−
(a) (c)
4Ω +
− 1Ω 3Ω
15V 2Ω 2 Ω Vx 4Ω
+ + +
− Vx 1Ω
9V
− −
(b) (d)
Figure P1.2.18
Copyright OUP
58 CIRCUIT CONCEPTS
3Ω
3Ω 6A 6Ω 4Ω 8A
2Ω
2Ω
Ix
Ix
(a) (c)
1Ω Ix 2Ω
1Ω 4Ω
3Ω 2Ω
10 A 2Ω 2Ω Ix
5Ω
1Ω
6A
(b) (d)
Figure P1.2.19
i(t), mA
1
+
i(t) 100 µF v(t) t, µs
− −1 1 2 3
−1
Figure P1.2.20
v(t), mV
1
+ i(t)
v(t) 3 µF t, µs
− −1 1 2 3 4 5
−1
−2
Figure P1.2.21
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Copyright OUP
PROBLEMS 59
1.2.24 Determine the equivalent capacitance at terminals and w(t). See Problem 1.2.20 and check whether
A–B for the circuit configurations shown in Figure the duality principle is satisfied.
P1.2.24.
*1.2.27 The energy stored in a 2-µH inductor is given by
1.2.25 For the circuit shown in Figure P1.2.25, sketch i(t) wL (t) = 9e−2t µJ for t ≥ 0. Find the inductor
and w(t). See Problem 1.2.21 and check whether current and voltage at t = 1 s. Compare the results
the duality principle is satisfied. of this problem with those of Problem 1.2.22 and
1.2.26 For the circuit given in Figure P1.2.26, sketch v(t) comment.
A Figure P1.2.24
6 µF
5 µF 1 µF
B
(a)
10 pF 10 pF
10 pF 10 pF
B
(b)
2 µF
2 µF 2 µF
5 µF A B
3 µF 3 µF
3 µF
(c)
v(t), mV
i(t)
3
+ −1
v(t) L = 3 µH t, µs
− 1 2 3 4 5
−3
−6
Figure P1.2.25
--`,,,``,,`,```,``,`````,```,```-`-`,
Copyright OUP
60 CIRCUIT CONCEPTS
i(t), A
(−10t + 40)
(20t + 10) 30
30 10t
+
i(t) L = 100 pH v(t) 20
−
10(t + 1)
10
t, µs
−1 0 1 2 3 4 5
Figure P1.2.26
1.2.28 The inductance per unit length in H/m for parallel- indicated. Following the dot convention presented
plate infinitely long conductors in air is given by in the text, place the other dot in the remaining
L = µ0 d/w = 4π ×10−7 d/w, where d and w are coil and justify your answer with an explanation.
in meters. Compute L (per unit length) for d = 1 m Comment on whether the polarities are consistent
and w = 0.113 m. See Problem 1.2.23 and show with Lenz’s law.
that the product of inductance (per unit length) and *1.2.32 For the configurations of the coupled coils shown
capacitance (per unit length) is µ0 ε0 . in Figure P1.2.32, obtain the voltage equations for
1.2.29 Determine the duals for the circuit configurations v1 and v2 .
of Problem 1.2.24 and determine the equivalent 1.2.33 The self-inductances of two coupled coils are L11
inductance at terminals A–B for each case. and L22, and the mutual inductance between them
is M. Show that the effective inductance of the two
1.2.30 Consider a pair of coupled coils as shown in Figure
coils in series is given by
1.2.10 of the text, with currents, voltages, and
polarity dots as indicated. Show that the mutual Lseries = L11 + L22 ± 2M
inductance is L12 = L21 = M by following
and the effective inductance of the two coils in
these steps:
parallel is given by
(a) Starting at time t0 with i1 (t0 ) = i2 (t0 ) = 0, L11 L22 − M 2
Lparallel =
maintain i2 = 0 and increase i1 until, at time L11 ∓ 2M + L22
t1 , i1 (t1 ) = I1 and i2 (t1 ) = 0. Determine Specify the conditions corresponding to different
the energy accumulated during this time. Now signs of the term 2M.
maintaining i1 = I1 , increase i2 until at time
1.2.34 For the coupled inductors shown in Figure
t2 , i2 (t2 ) = I2 . Find the corresponding energy
P1.2.34, neglecting the coil resistances, write the
accumulated and the total energy stored at
volt-ampere relations.
time t2 .
1.2.35 Consider an amplifier as a voltage source with an
(b) Repeat the process in the reverse order, al- internal resistance of 72 -. Find the turns ratio of
lowing the currents to reach their final values. the ideal transformer such that maximum power
Compare the expressions obtained for the total is delivered when the amplifier is connected to an
energy stored and obtain the desired result. 8-- speaker through an N1 : N2 transformer.
1.2.31 For the coupled coils shown in Figure P1.2.31, a 1.2.36 For the circuit shown in Figure P1.2.36, determine
dot has been arbitrarily assigned to a terminal as vout (t).
Figure P1.2.31
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Copyright OUP
PROBLEMS 61
M M
i1 i2 i1 i2
+ + − −
v1 L11 L22 v2 v1 L11 L22 v2
− − + +
(a) (b)
Figure P1.2.32
+ − Figure P1.2.34
v2
i2
L22
L12 L23
L13
L11 L33
i1 i3
v1 v3
+ − − +
18 Ω 2Ω
3:1 1:2 +
+
vin = 36 Ω 3Ω Vout (t)
18 sin 10t V −
−
Ideal Ideal
transformer transformer
Figure P1.2.36
*1.2.37 A 60-Hz, 100-kVA, 2400/240-V (rms) transformer 1.2.38 A transformer is rated 10 kVA, 220:110 V (rms).
is used as a step-down transformer from a trans- Consider it an ideal transformer.
mission line to a distribution system. Consider the (a) Compute the turns ratio and the winding cur-
transformer to be ideal. rent ratings.
(a) Find the turns ratio. (b) If a 2-- load resistance is connected across the
110-V winding, what are the currents in the
(b) What secondary load resistance will cause the high-voltage and low-voltage windings when
transformer to be fully loaded at rated voltage rated voltage is applied to the 220-V primary?
(i.e., delivering the rated kVA), and what is
(c) Find the equivalent load resistance referred to
the corresponding primary current?
the 220-V side.
(c) Determine the value of the load resistance 1.3.1 Some element voltages and currents are given in
referred to the primary side of the transformer. the network configuration of Figure P1.3.1. De-
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62 CIRCUIT CONCEPTS
termine the remaining voltages and currents. Also and V2 . Show that the conservation of power is
calculate the power delivered to each element as satisfied by the circuit.
well as the algebraic sum of powers of all ele-
*1.3.6 The current sources in Figure P1.3.6 are given to
ments, and comment on your result while identi-
be IA = 30 A and IB = 50 A. For the values of
fying sources and sinks.
R1 = 20 -, R2 = 40 -, and R3 = 80 -, find:
*1.3.2 Calculate the voltage v in the circuit given in
Figure P1.3.2. (a) The voltage V.
1.3.3 Determine v, i, and the power delivered to el- (b) The currents I1 , I2 , and I3 .
ements in the network given in Figure P1.3.3. (c) The power supplied by the current sources
Check whether conservation of power is satisfied and check whether conservation of power is
by the circuit. satisfied.
1.3.4 For a part of the network shown in Figure P1.3.4,
1.3.7 Show how the conservation of power is satisfied
given that i1 = 4 A; i3 (t) = 5e−t , and i4 (t) = 10
by the circuit of Figure P1.3.7.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
cos 2t, find v1 , v2 , v3 , v4 , i2 , and i5.

1.3.5 For the circuit given in Figure P1.3.5, given that 1.3.8 Given that V0 = 10 V, determine IS in the circuit
VAC = 10 V and VBD = 20 V, determine V1 drawn in Figure P1.3.8.
d Figure P1.3.1
a C
+ vC − 1A
+ −
6V A F 10 V
− L1 +
iA iF
+
b D e
H 4V
2A − 8V + iD L3
−
+ +
vB B G vG
L2
− − iH
+ 4V − 3A
c E
iE f
− 4V + + 6V − Figure P1.3.2
B C
A
+ −
6V −4 V
− +
− −2 V +
H D
I
+ +
12 V v=?
− −
G E
F + −12 V −
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PROBLEMS 63
B G Figure P1.3.3
A
iz + vAB − 6A ix
+ +
i=?
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
3V −2 V
− −
+
F C S v=?
iy − vCF + 3 A 2A −
− −
1V 4V
+ +
+ −1 V −
E D
H
v4 −
+ A
D A B
i4 1H
i3 i1 I 2Ω
+ +
1Ω 3Ω
v3 2H 10 Ω v1
− + +
−
0.1 F V1 V2
C − −
i2 + − B i5
v2 D C
4Ω
Figure P1.3.4 Figure P1.3.5
Figure P1.3.6
I1 I2 I3
+
IA R1 V R2 R3 IB
−
1.3.9 Consider the circuit shown in Figure P1.3.9. meter is employed to measure 100 V, find the
−t percent of probable error that can exist.
(a) Given v(t) = 10e V, find the current source
is(t) needed. 1.4.2 A current of 65 A is measured with an analog
−t
ammeter having a probable error of ±0.5% of
(b) Given i(t) = 10e A, find the voltage source full scale of 100 A. Find the maximum probable
vs(t) needed. percentage error in the measurement.
1.3.10 An operational amplifier stage is typically repre- 1.4.3 Error specifications on a 10-A digital ammeter
sented by the circuit of Figure P1.3.10. For the are given as 0.07% of the reading, 0.05% of full
values given, determine V out and the power sup- scale, 0.005% of the reading per degree Celsius,
plied by the 2.5-V source. and 0.002% of full scale per degree Celsius. The
1.4.1 A voltmeter with a full scale of 100 V has a 10-A analog meter error specification is given as
probable error of 0.1% of full scale. When this 0.5% of full scale and 0.001% of the reading per
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64 CIRCUIT CONCEPTS
Figure P1.3.7
+
5A 5Ω 10 V
−
Figure P1.3.8
10 Ω
+ +
V1
5Ω V0 = 10 V
5 10 Ω
IS
− −
1H Figure P1.3.9
+A
i(t)
+
Source 1F 1F 2Ω v(t)
−
−B
5000 Ω 10,000 Ω Figure P1.3.10

+
+
+ +
2.5 V V1 −105V1 Vout
− −
−
−
degree Celsius. If the temperature at the time of is the unknown resistance. RM is the galvanometer
measurement is 20°C above ambient, compare the resistance of 6 -. If no current is detected by the
percent error of both meters when measuring a galvanometer, when a 24-V source with a 12--
current of 5 A. internal resistance is applied across terminals a–b,
1.4.4 A DMM (digital multimeter) reads true rms values find: (a) R4, and (b) the current through R4.
of current. If the peak value of each of the follow-
1.4.7 Three waveforms seen on an oscilloscope are
ing periodic current waves is 5 A, find the meter
shown in Figure P1.4.7. If the horizontal scale
reading for: (a) a sine wave, (b) a square wave, (c)
is set to 50 ms per division (500 ms for the en-
a triangular wave, and (d) a sawtooth wave.
tire screen width), and the vertical scale is set
1.4.5 Consider the bridge circuit given in Figure P1.4.5 to 5 mV per division (±25 mV for the entire
with R1 = 24 k-, R2 = 48 k-, and R3 = 10 k-. screen height with zero voltage at the center),
Find R4 when the bridge is balanced with V1 = 0. determine: (i) the maximum value of the volt-
*1.4.6 In the Wheatstone bridge circuit shown in Figure age, and (ii) the frequency for each of the wave-
P1.4.6, R1 = 16 -, R2 = 8 -, and R3 = 40 -; R4 forms.
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PROBLEMS 65
Figure P1.4.5
R1 R3
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
+ + −
Vin V1
−
R2 R4
a Figure P1.4.6
R1 = 16 Ω R2 = 8 Ω
12 Ω
RM = 6 Ω
G
+
24 V
− R3 = 40 Ω R4 = ?
(a) (b) (c)

Figure P1.4.7 (a) Sinusoidal wave. (b) Rectangular wave. (c) Sawtooth wave.
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2 Circuit Analysis Techniques
2.1 Thévenin and Norton Equivalent Circuits
2.2 Node-Voltage and Mesh-Current Analyses
2.3 Superposition and Linearity
2.4 Wye-Delta Transformation
2.5 Computer-Aided Circuit Analysis: SPICE
2.6 Computer-Aided Circuit Analysis: MATLAB
2.8 Practical Application: A Case Study—Jump Starting a Car
Problems
In Chapter 1 the basic electric circuit concepts were presented. In this chapter we consider some
circuit analysis techniques, since one needs not only basic knowledge but also practical and
efficient techniques for solving problems associated with circuit operations.
One simplifying technique often used in complex circuit problems is that of breaking the
circuit into pieces of manageable size and analyzing individually the pieces that may be already
familiar. Equivalent circuits are introduced which utilize Thévenin’s and Norton’s theorems to
replace a voltage source by a current source or vice versa. Nodal and loop analysis methods are then
presented. Later the principles of superposition and linearity are discussed. Also, wye–delta trans-
formation is put forth as a tool for network reduction. Finally, computer-aided circuit analyses with
SPICE and MATLAB are introduced. The chapter ends with a case study of practical application.
2.1 THÉVENIN AND NORTON EQUIVALENT CIRCUITS

For a linear portion of a circuit consisting of ideal sources and linear resistors, the volt–ampere
(v–i) relationship at any two accessible terminals can be expressed by the linear equation
v = Ai + B (2.1.1)
66
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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2.1 THÉVENIN AND NORTON EQUIVALENT CIRCUITS 67
where A and B are two constants. The Thévenin equivalent circuit at any two terminals a and b
(to replace the linear portion of the circuit) is given by
v = RTh i + voc (2.1.2)
where it can be seen that
RTh = v/ i|voc =0 (2.1.3)
and
voc = v|i=0 (2.1.4)
Thus, voc is known as the open-circuit voltage (or Thévenin voltage) with i = 0, and RTh is the
Thévenin equivalent resistance (as seen from the terminals a–b) with voc = 0. Equation (2.1.4)
accounts for the ideal sources present in that linear portion of the circuit, as shown in Figure
2.1.1(a), whereas Equation (2.1.3) implies deactivating or zeroing all ideal sources (i.e., replacing
voltage sources by short circuits and current sources by open circuits). The model with the voltage
source voc in series with RTh is known as Thévenin equivalent circuit, as shown in Figure 2.1.1(b).
Equation (2.1.1) may be rewritten as
v B v voc v
i= − = − = − isc (2.1.5)
A A RTh RTh RTh
which is represented by the Norton equivalent circuit with a current source isc in parallel with
RTh, as shown in Figure 2.1.1(c). Notice that with v = 0, i = −isc . Also, isc = voc /RTh , or
voc = isc RTh .
Besides representing complete one-ports (or two-terminal networks), Thévenin and Norton
equivalents can be applied to portions of a network (with respect to any two terminals) to
simplify intermediate calculations. Moreover, successive conversions back and forth between the
two equivalents often save considerable labor in circuit analysis with multiple sources. Source
transformations can be used effectively by replacing the voltage source V with a series resistance
R by an equivalent current source I (= V /R) in parallel with the same resistance R, or vice versa.
RTh
i a i a
i a + +
Linear portion + − +
of circuit
+
consisting of v v oc v v
isc RTh
ideal sources
and linear −
resistors − v/RTh
b − −
b b
(a) (b) (c)
Figure 2.1.1 Equivalent circuits. (a) Two-terminal or one-port network. (b) Thévenin equivalent circuit.
(c) Norton equivalent circuit.
EXAMPLE 2.1.1
Consider the circuit shown in Figure E2.1.1(a). Reduce the portion of the circuit to the left of
terminals a–b to (a) a Thévenin equivalent and (b) a Norton equivalent. Find the current through
R = 16 -, and comment on whether resistance matching is accomplished for maximum power
transfer.
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68 CIRCUIT ANALYSIS TECHNIQUES
a
a +
I=? 48 Ω 24 Ω
48 Ω
IL Voc
6A 24 Ω R = 16 Ω + +
+ 96 V 144 V
96 V − −
−
−
b
b (b)
(a)
a a
16 Ω
I
+
48 Ω 24 Ω 128 V R = 16 Ω
−
b b
(c) (d)
+
a
2A 48 Ω 6A 24 Ω Isc
b
−
(e)
a a
I
48 Ω 24 Ω 8A 16 Ω R =16 Ω
b b
(f) (g)
Figure E2.1.1
Solution
The 6-A source with 24 - in parallel can be replaced by a voltage source of 6 × 24 = 144 V with
24 - in series. Thus, by using source transformation, in terms of voltage sources, the equivalent
circuit to the left of terminals a–b is shown in Figure E2.1.1(b).
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2.1 THÉVENIN AND NORTON EQUIVALENT CIRCUITS 69
(a) KVL: 144 − 24IL − 48IL − 96 = 0, or 72IL = 48, or IL = 2/3 A
Voc = 144 − 24( 2/3) = 128 V
Deactivating or zeroing all ideal sources, i.e., replacing voltage sources by short
circuits in the present case, the circuit of Figure E2.1.1(b) reduces to that shown in
Figure E2.1.1(c).
Viewed from terminals a–b, the 48-- resistor and the 24-- resistor are in parallel,
48 × 24
RTh = 4824 = = 16 -
48 + 24
Thus, the Thévenin equivalent to the left of terminals a–b, attached with the 16-- resistor,
is shown in Figure E2.1.1(d). Note that the Thévenin equivalent of any linear circuit
consists of a single Thévenin voltage source in series with a single equivalent Thévenin
resistance.
The current in the 16-- resistor to the right of terminals a–b can now be found,
I = 128/32 = 4 A
(b) The 96-V source with 48 - in series can be replaced by a current source of 96/48 = 2
A with a parallel resistance of 48 -. Thus, by using source transformation, in terms
of current sources, the equivalent circuit to the left of terminals a–b is given in Figure
E2.1.1(e).
Shorting terminals a–b, one can find Isc , Isc = 8 A. Replacing current sources by
open circuits, viewed from terminals a–b, RTh = 4824 = 16 -, which is the same as in
part (a). The circuit of Figure E2.1.1(e) to the left of terminals a–b reduces to that shown
in Figure E2.1.1(f).
Thus, the Norton equivalent to the left of terminals a–b, attached with the 16--
resistor, is given in Figure E2.1.1(g). Note that the Norton equivalent of any linear
circuit consists of a single current source in parallel with a single equivalent Thévenin
resistance.
The current in the 16-- resistor to the right of terminals a–b can now be found. I = 4 A,
which is the same as in part (a).
The equivalent source resistance, also known as the output resistance, is the same as the load
resistance of 16 - in the present case. Hence, resistance matching is accomplished for maximum
power transfer.
EXAMPLE 2.1.2
Consider the circuit of Figure E2.1.2(a), including a dependent source. Obtain the Thévenin
equivalent at terminals a–b.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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I Figure E2.1.2
a
2000 Ω
+
10 V 200 Ω 9I
−
I1
b
(a)
I +
a
a RTh = 10 Ω
2000 Ω
+
+ 0.5 V
10 V 200 Ω 9I Isc −
−
I1 b
b −
(c)
(b)
Solution
First, the open-circuit voltage at terminals a–b is to be found.

KCL at node a: I + 9I = I1 , or I1 = 10I
KVL for the left-hand mesh: 2000I + 200I1 = 10, or 4000I = 10, or I = 1/400 A
Voc = 200I1 = 200(1/400) = 0.5 V
Because of the presence of a dependent source, in order to find RTh, one needs to determine I sc
after shorting terminals a–b, as shown in Figure E2.1.2(b).
Note that I1 = 0, since Vab = 0.
KCL at node a: Isc = 9I + I = 10I
KVL for the outer loop: 2000I = 10, or I = 1/200 A
Isc = 10(1/200) = 1/20 A
Hence the equivalent Thévenin resistance RTh viewed from terminals a–b is
Voc 0.5
RTh = = = 10-
Isc 1/20
Thus, the Thévenin equivalent is given in Figure E2.1.2(c).
The preceding examples illustrate how a complex network could be reduced to a simple
representation at an output port. The effect of load on the terminal behavior or the effect of an
output load on the network can easily be evaluated. Thévenin and Norton equivalent circuits
help us in matching, for example, the speakers to the amplifier output in a stereo system. Such
equivalent circuit concepts permit us to represent the entire system (generation and distribution)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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2.2 NODE-VOLTAGE AND MESH-CURRENT ANALYSES 71
connected to a receptacle (plug or outlet) in a much simpler model with the open-circuit voltage
as the measured voltage at the receptacle itself.
When a system of sources is so large that its voltage and frequency remain constant regardless
of the power delivered or absorbed, it is known as an infinite bus. Such a bus (node) has a voltage
and a frequency that are unaffected by external disturbances. The infinite bus is treated as an ideal
voltage source. Even though, for simplicity, only resistive networks are considered in this section,
the concept of equivalent circuits is also employed in ac sinusoidal steady-state circuit analysis
of networks consisting of inductors and capacitors, as we shall see in Chapter 3.
2.2 NODE-VOLTAGE AND MESH-CURRENT ANALYSES

The node-voltage and mesh-current methods, which complement each other, are well-ordered
systematic methods of analysis for solving complicated network problems. The former is based
on the KCL equations, whereas the KVL equations form the basis for the latter. In both methods
an appropriate number of simultaneous algebraic equations are developed. The unknown nodal
voltages are found in the nodal method, whereas the unknown mesh currents are calculated in the
loop (or mesh) method. A decision to use one or the other method of analysis is usually based on
the number of equations needed for each method.
Even though, for simplicity, only resistive networks with dc voltages are considered in this
section, the methods themselves are applicable to more general cases with time-varying sources,
inductors, capacitors, and other circuit elements.
Nodal-Voltage Method
A set of node-voltage variables that implicitly satisfy the KVL equations is selected in order to
formulate circuit equations in this nodal method of analysis. A reference (datum) node is chosen
arbitrarily based on convenience, and from each of the remaining nodes to the reference node, the
voltage drops are defined as node-voltage variables. The circuit is then described completely by
the necessary number of KCL equations whose solution yields the unknown nodal voltages from
which the voltage and the current in every circuit element can be determined. Thus, the number
of simultaneous equations to be solved will be equal to one less than the number of network
nodes. All voltage sources in series with resistances are replaced by equivalent current sources
with conductances in parallel. In general, resistances may be replaced by their corresponding
conductances for convenience. Note that the nodal-voltage method is a general method of network
analysis that can be applied to any network.
Let us illustrate the method by considering the simple, but typical, example shown in Figure
2.2.1. By replacing the voltage sources with series resistances by their equivalent current sources
with shunt conductances, Figure 2.2.1 is redrawn as Figure 2.2.2, in which one can identify three
nodes, A, B, and O.
Notice that the voltages VAO, VBO, and VAB satisfy the KVL relation:
VAB + VBO − VAO = 0, or VAB = VAO − VBO = VA − VB (2.2.1)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
where the node voltages VA and VB are the voltage drops from A to O and B to O, respectively.
With node O as reference, and with VA and VB as the node-voltage unknown variables, one can
write the two independent KCL equations:
Node A: VA G1 + (VA − VB )G3 = I1 , or (G1 + G3 )VA − G3 VB = I1 (2.2.2)
Node B: VB G2 − (VA − VB )G3 = I2 , or − G3 VA + (G2 + G3 )VB = I2 (2.2.3)
Copyright OUP
Node A Node B Figure 2.2.1 Circuit for illustration of nodal-voltage method.

R3
R1 R2
+ +
V1 V2
− −
Node O
G3 = 1
A R3 B
+ −
VAB = VA − VB
+ +
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
V V
I1 = 1 VAO = VA G1 = 1 G2 = 1 VBO = VB I2 = 2
R1 R1 R2 R2
− −
O Reference
Figure 2.2.2 Redrawn Figure 2.2.1 for node-voltage method of analysis.
An examination of these equations reveals a pattern that will allow nodal equations to be
written directly by inspection by following the rules given here for a network containing no
dependent sources.
1. For the equation of node A, the coefficient of VA is the positive sum of the conductances
connected to node A; the coefficient of VB is the negative sum of the conductances
connected between nodes A and B. The right-hand side of the equation is the sum of
the current sources feeding into node A.
2. For the equation of node B, a similar situation exists. Notice the coefficient of VB to be
the positive sum of the conductances connected to node B; the coefficient of VA is the
negative sum of the conductances connected between B and A. The right-hand side of the
equation is the sum of the current sources feeding into node B.
Such a formal systematic procedure will result in a set of N independent equations of the
following form for a network with (N + 1) nodes containing no dependent sources:
G11 V1 − G12 V2 − ··· − G1N VN = I1
−G21 V1 + G22 V2 − ··· − G2N VN = I2
.. ..
. .
−GN1 V1 − G N 2 V2 − ··· + G N N VN = IN (2.2.4)
where GNN is the sum of all conductances connected to node N, GJ K = GKJ is the sum of all
conductances connected between nodes J and K, and IN is the sum of all current sources entering
node N. By solving the equations for the unknown node voltages, other voltages and currents in
the circuit can easily be determined.
Copyright OUP
EXAMPLE 2.2.1
By means of nodal analysis, find the current delivered by the 10-V source and the voltage across
the 10-- resistance in the circuit shown in Figure E2.2.1(a).
− + 4Ω Figure E2.2.1
20 V
8Ω 10 Ω
5Ω
20 Ω 25 Ω
+
10 V
−
(a)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
20/4 = 5 A
1 = 0.25 S
4
A C
B
1 = 0.125 S
8
10 = 2 A 1 = 0.2S 1 = 0.05 S 1 = 0.04 S
5 5 20 25
O Reference
(b)
− + 4Ω
20 V
B
A C
8Ω 10 Ω
5Ω
20 Ω 25 Ω
+
10 V
−
O
(c)
Solution
STEP 1: Replace all voltage sources with series resistances by their corresponding Norton
equivalents consisting of current sources with shunt conductances. The given circuit is redrawn
in Figure E2.2.1(b) by replacing all resistors by their equivalent conductances.
Copyright OUP
STEP 2: Identify the nodes and choose a convenient reference node O. This is also shown in
Figure E2.2.1(b).
STEP 3: In terms of unknown node-voltage variables, write the KCL equations at all nodes
(except, of course, the reference node) by following rules 1 and 2 for nodal equations given in
this section.
Node A: (0.2 + 0.125 + 0.25)VA − 0.125VB − 0.25VC = 2 − 5 = −3
Node B: −0.125VA + (0.125 + 0.05 + 0.1)VB − 0.1VC = 0
Node C: −0.25VA − 0.1VB + (0.25 + 0.1 + 0.04)VC =5
Rearranging, one gets
0.575 VA − 0.125 VB − 0.25 VC = −3
−0.125 VA + 0.275 VB − 0.1 VC = 0
−0.25 VA − 0.1 VB + 0.39 VC = 5
STEP 4: Simultaneously solve the independent equations for the unknown nodal voltages by
Gauss elimination or Cramer’s rule. In our example, the solution yields
VA = 4.34 V ; VB = 8.43V ; VC = 17.77 V
STEP 5: Obtain the desired voltages and currents by the application of KVL and Ohm’s law. To
find the current I in the 10-V source, since it does not appear in Figure E2.2.1(b) redrawn for
nodal analysis, one has to go back to the original circuit and identify the equivalence between
nodes A and O, as shown in Figure E2.2.1(c).
Now one can solve for I, delivered by the 10-V source,
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
5.66
VA = 4.34 = −5I + 10 or I= = 1.132 A
5
The voltage across the 10-- resistance is VB − VC = 8.43 − 17.77 = −9.34 V. The negative sign
indicates that node C is at a higher potential than node B with respect to the reference node O.
Nodal analysis deals routinely with current sources. When we have voltage sources along
with series resistances, the source-transformation technique may be used effectively to convert
the voltage source to a current source, as seen in Example 2.2.1. However, in cases where we have
constrained nodes, that is, the difference in potential between the two node voltages is constrained
by a voltage source, the concept of a supernode becomes useful for the circuit analysis, as shown
in the following illustrative example.
EXAMPLE 2.2.2
For the network shown in Figure E2.2.2, find the current in each resistor by means of nodal
analysis.
Solution
Note that the reference node is chosen at one end of an independent voltage source, so that the
node voltage VA is known at the start,
VA = 12 V
Copyright OUP
Supernode Figure E2.2.2

A B + − C
24 V
IA 2Ω
+
12 V 2Ω 1Ω 4A
−
IB IC
Reference node
Note that we cannot express the branch current in the voltage source as a function of VB and VC .
Here we have constrained nodes B and C. Nodal voltages VB and VC are not independent. They
are related by the constrained equation
VB − VC = 24 V
Let us now form a supernode, which includes the voltage source and the two nodes B and C,
as shown in Figure E2.2.2. KCL must hold for this supernode, that is, the algebraic sum of the
currents entering or leaving the supernode must be zero. Thus one valid equation for the network
is given by
12 − VB VB VC
IA − IB − IC + 4 = 0 or − − +4=0
2 2 1
which reduces to
VB + VC = 10
This equation together with the supernode constraint equation yields
VB = 17 V and VC = −7 V
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
The currents in the resistors are thus given by

12 − VB 12 − 17
IA = = = −2.5 A
2 2
VB 17
IB = = = 8.5 A
2 2
VC −7
IC = = = −7 A
1 1
Mesh-Current Method
This complements the nodal-voltage method of circuit analysis. A set of independent mesh-
current variables that implicitly satisfy the KCL equations is selected in order to formulate circuit
equations in this mesh analysis. An elementary loop, or a mesh, is easily identified as one of
the “window panes” of the whole circuit. However, it must be noted that not all circuits can be
laid out to contain only meshes as in the case of planar networks. Those which cannot are called
nonplanar circuits, for which the mesh analysis cannot be applied, but the nodal analysis can be
employed.
A mesh current is a fictitious current, which is defined as the one circulating around a mesh
of the circuit in a certain direction. While the direction is quite arbitrary, a clockwise direction
Copyright OUP
is traditionally chosen. Branch currents can be found in terms of mesh currents, whose solution
is obtained from the independent simultaneous equations. The number of necessary equations in
the mesh-analysis method is equal to the number of independent loops or meshes.
All current sources with shunt conductances will be replaced by their corresponding Thévenin
equivalents consisting of voltage sources with series resistances. Let us illustrate the method by
considering a simple, but typical, example, as shown in Figure 2.2.3.
Replacing the current source with shunt resistance by the Thévenin equivalent, Figure 2.2.3 is
redrawn as Figure 2.2.4, in which one can identify two elementary loops, or independent meshes.
By assigning loop or mesh-current variables I 1 and I 2, as shown in Figure 2.2.4, both in the
clockwise direction, one can write the KVL equations for the two closed paths (loops) ABDA and
BCDB,
Loop ABDA: I1 R1 + (I1 − I2 )R2 = V1 − V2 or (R1 + R2 )I1 − R2 I2 = V1 − V2 (2.2.5)
Loop BCDB: I2 R3 + (I2 − I1 )R2 = V2 − V3 or −R2 I1 + (R2 + R3 )I2 = V2 − V3 (2.2.6)
Notice that current I 1 exists in R1 and R2 in the direction indicated; I 2 exists in R2 and R3 in the
direction indicated; hence, the net current in R2 is I1 − I2 directed from B to D. An examination of
Equations (2.2.5) and (2.2.6) reveals a pattern that will allow loop equations to be written directly
by inspection by following these rules:
1. In the first loop equation with mesh current I 1, the coefficient of I 1 is the sum of the
resistances in that mesh; the coefficient of I 2 is the negative sum of the resistances common
to both meshes. The right-hand side of the equation is the algebraic sum of the source
voltage rises taken in the direction of I 1.
2. Similar statements can be made for the second loop with mesh current I 2. (See also the
similarity in setting up the equations for the mesh-current and nodal-voltage methods of
analysis.)
Such a formal systematic procedure will yield a set of N independent equations of the
following form for a network with N independent meshes containing no dependent sources:
Figure 2.2.3 Circuit for illustration of mesh-

current method.
R1 R2
R3 I3
+ +
V1 V2
− −
A B C Figure 2.2.4 Redrawn Figure 2.2.3 for mesh-

current method of analysis.
R1 R3 R3
I1 I2
+ + +
V1 V2 V3 V3 = I3R3
− − −
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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R11 I1 − R12 I2 − ··· − R1N IN = V1

−R21 I1 + R22 V2 − ··· − R2N IN = V2
.. .. (2.2.7)
. .
−RN 1 I1 − RN 2 V2 − · · · + RN N IN = VN
where RNN is the sum of all resistances contained in mesh N, RJ K = RKJ is the sum of all
resistances common to both meshes J and K, and VN is the algebraic sum of the source-voltage
rises in mesh N, taken in the direction of IN.
By solving the equations for the unknown mesh currents, other currents and voltages in the
circuit elements can be determined easily.
EXAMPLE 2.2.3
By means of mesh-current analysis, obtain the current in the 10-V source and the voltage across
the 10-- resistor in the circuit of Example 2.2.1.
Solution
STEP 1: Replace all current sources with shunt resistances by their corresponding Thévenin
equivalents consisting of voltage sources with series resistances. Conductances included in the
circuit are replaced by their equivalent resistances.
In this example, since there are no current sources and conductances, the circuit of Figure
E2.2.1(a) is redrawn as Figure E2.2.3 for convenience.
− + 4Ω Figure E2.2.3
20 V
I3
8Ω 10 Ω
5Ω
I1 20 Ω I2 25 Ω
+
10 V
−
STEP 2: Identify elementary loops (meshes) and choose a mesh-current variable for each
elementary loop, with all loop currents in the same clockwise direction. Mesh currents I 1, I 2,
and I 3 are shown in Figure E2.2.3.
STEP 3: In terms of unknown mesh-current variables, write the KVL equations for all meshes
by following the rules for mesh analysis.
Loop 1 with mesh current I 1: (5 + 8 + 20)I1 − 20I2 − 8I3 = 10
Loop 2 with mesh current I 2: −20I1 + (20 + 10 + 25)I2 − 10I3 = 0
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Loop 3 with mesh current I 3: −8I1 − 10I2 + (4 + 10 + 8)I3 = 20

Rearranging, one gets
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33I1 − 20I2 − 8I3 = 10
−20I1 + 55I2 − 10I3 = 0
−8I1 − 10I2 + 22I3 = 20
STEP 4: Simultaneously solve the independent equations for the unknown mesh currents by
Gauss elimination or Cramer’s rule.
In this example the solution yields
I1 = 1.132 A; I2 = 0.711 A; I3 = 1.645 A
The current through the 10-V source is I1 = 1.132 A, which is the same as in Example 2.2.1. The
voltage across the 10-- resistor is VBC = 10(I2 − I3 ) = 10(0.711 − 1.645) = −9.34 V, which
is the same as in Example 2.2.1.
Looking at Examples 2.2.1 and 2.2.3, it can be seen that there is no specific advantage
for either method since the number of equations needed for the solution is three in either case.
Such may not be the case in a number of other problems, in which case one should choose
judiciously the more convenient method, usually with the lower number of equations to be
solved.
The mesh-current method deals routinely with voltage sources. When we have current
sources with shunt conductances, the source-transformation technique may be used effectively to
convert the current source to a voltage source. However, in cases where we have constrained
meshes, that is, the two mesh currents are constrained by a current source, the concept of
a supermesh becomes useful for the circuit analysis, as shown in the following illustrative
example.
EXAMPLE 2.2.4
For the network shown in Figure E2.2.4, find the current delivered by the 10-V source and the
voltage across the 3-- resistor by means of mesh-current analysis.
Vx = ? Figure E2.2.4
+ 3Ω −
I3
2Ω 4Ω
Supermesh +
1Ω I1 5A I2 10 V
−
Solution
Note that we cannot express the voltage across the current source in terms of the mesh currents I1
and I2 . The current source does, however, constrain the mesh currents by the following equation:
I2 − I1 = 5
--`,,,``,,`,```,``,`````,
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Let us now form a supermesh, which includes meshes 1 and 2, as shown in Figure E2.2.4. We
now write a KVL equation around the periphery of meshes 1 and 2 combined. This yields
1I1 + 2(I1 − I3 ) + 4(I2 − I3 ) + 4(I2 − I3 ) + 10 = 0
Next we write a KVL equation for mesh 3,
3I3 + 4(I3 − I2 ) + 2(I3 − I1 ) = 0
Now we have the three linearly independent equations needed to find the three mesh currents
I1 , I2 , and I3 . The solution of the three simultaneous equations yields
−25A 20 70
I1 = A; I2 = A; I3 = A
9 9 27
The current delivered by the 10-V source is −I2 , or −20/9 A. That is to say, the 10-V source
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
is absorbing the current 20/9 A.
The voltage across the 3-- resistor is Vx = 3I3 = 3(70/27) = 70/9 = 7.78 V.
Node-Voltage and Mesh-Current Equations with Controlled Sources

Since a controlled source acts at its terminals in the same manner as does an independent source,
source conversion and application of KCL and KVL relations are treated identically for both
types of sources. Because the strength of a controlled source depends on the value of a voltage
or current elsewhere in the network, a constraint equation is written for each controlled source.
After combining the constraint equations with the loop or nodal equations based on treating all
sources as independent sources, the resultant set of equations are solved for the unknown current
or voltage variables.
EXAMPLE 2.2.5
Consider the circuit in Figure E2.2.5(a), which include a controlled source, and find the current
in the 5-V source and the voltage across the 5-- resistor by using (a) the loop-current method
and (b) the node-voltage method.
Solution
(a) Loop-Current Method: The voltage-controlled current source and its parallel resistance
are converted into a voltage-controlled voltage source and series resistance. When you
are source transforming dependent sources, note that the identity of the control variable
(i.e., the location in the circuit) must be retained. The converted circuit is shown in Figure
E2.2.5(b) with the chosen loop currents I 1 and I 2.
The KVL equations are
For loop carrying I 1: (10 + 4 + 2)I1 − 2I2 = 5
For loop carrying I 2: −2I1 + (2 + 10 + 5)I2 = −5V1
The constraint equation is
V1 = (I1 − I2 )2
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10 Ω Figure E2.2.5
10 Ω 4Ω
I=? + +
+ V1 2Ω 0.5 V1 5ΩV=?
5V − −
−
(a)
0.5 V1 × 10 = 5 V1
10 Ω 4Ω + − 10 Ω
+ +
5V I1 V1 2Ω I2 5Ω
− −
(b)
1 = 0.1 S
1 = 0.25 S 10
A 4 B
C
+ 1 = 0.5 S 0.5 V1 1 = 0.2 S

5 = 0.5 A 1 = 0.1 S
10 10 V1 2 5
−
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
O Reference
(c)
Combining the constraint equation with the loop equations, one gets
16I1 − 2I2 = 5; −2I1 + 17I2 = −10(I1 − I2 ), or 8I1 + 7I2 = 0
from which
I1 = 35/128 A; I2 = −5/16 A
Thus, the current through the 5-V source is I = I1 = 35/128 = 0.273 A, and the
voltage across the 5-- resistor is V = 5I2 = 5(−5/16) = −1.563 V.
(b) Node-Voltage Method: The 5-V voltage source with its 10-- series resistor is replaced
by its Norton equivalent. Resistances are converted into conductances and the circuit is
redrawn in Figure E2.2.5(c) with the nodes shown.
The nodal equations are
A: (0.1 + 0.25)VA − 0.25VB = 0.5
B: −0.25VA + (0.25 + 0.5 + 0.1)VB − 0.1VC = 0.5V1
C: −0.1VB + (0.1 + 0.2)VC = −0.5V1
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2.3 SUPERPOSITION AND LINEARITY 81
The constraint equation is

V 1 = VB
Combining these with the nodal equations already written, one has
0.35 VA − 0.25 VB = 0.5
−0.25 VA + 0.35 VB − 0.1 VC = 0
0.4 VB + 0.3 VC = 0
Solving, one gets

VA = 2.266V ; VB = 1.173; VC = −1.564 V
Notice that VC = −1.564 V is the voltage V across the 5-- resistor, which is almost the
same as that found in part (a).
In order to find the current I through the 5-V source, one needs to go back to the
original circuit and recognize that
5 − 10I = VA = 2.266 or I = 0.273 A
which is the same as that found in part (a).

--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
2.3 SUPERPOSITION AND LINEARITY

Mathematically a function is said to be linear if it satisfies two properties: homogeneity (propor-
tionality or scaling) and additivity (superposition),
f (Kx) = Kf (x) (homogeneity) (2.3.1)
where K is a scalar constant, and
f (x1 + x2 ) = f (x1 ) + f (x2 ) (additivity) (2.3.2)
Linearity requires both additivity and homogeneity. For a linear circuit or system in which
excitations x 1 and x 2 produce responses y1 and y2, respectively, the application of K 1x 1 and
K 2x 2 together (i.e., K 1x 1 + K 2x 2) results in a response of (K 1y1 + K 2y2), where K 1 and K 2
are constants. With the cause-and-effect relation between the excitation and the response, all
linear systems satisfy the principle of superposition. A circuit consisting of independent sources,
linear dependent sources, and linear elements is said to be a linear circuit. Note that a resistive
element is linear. Capacitors and inductors are also circuit elements that have a linear input–output
relationship provided that their initial stored energy is zero. Nonzero initial conditions are to be
treated as independent sources.
In electric circuits, the excitations are provided by the voltage and current sources, whereas
the responses are in terms of element voltages and currents. All circuits containing only ideal
resistances, capacitances, inductances, and sources are linear circuits (described by linear dif-
ferential equations). For a linear network consisting of several independent sources, according
to the principle of superposition, the net response in any element is the algebraic sum of the
individual responses produced by each of the independent sources acting only by itself. While each
independent source acting on the network is considered separately by itself, the other independent
sources are suppressed; that is to say, voltage sources are replaced by short circuits and current
sources are replaced by open circuits, thereby reducing the source strength to zero. The effect of
any dependent sources, however, must be included in evaluating the response due to each of the
independent sources, as illustrated in the following example.
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EXAMPLE 2.3.1
Determine the voltage across the 20-- resistor in the following circuit of Figure E2.3.1 (a) with
the application of superposition.
6Ω Figure E2.3.1
6A
+ +
V
18 V V 12 Ω 3 80 Ω 20 Ω
− −
(a)
6Ω A B
+ +
I1′ VA′ = V ′ V ′ = VA′
18 V 12 Ω 80 Ω 20 Ω
− − 3 3
(b)
A B
6Ω 6A
+
V ″ = VA″
VA″ = V ″ 12 Ω 80 Ω 20 Ω
− 3 3
(c)
Solution
Let us suppress the independent sources in turn, recognizing that there are two independent
sources. First, by replacing the independent current source with an open circuit, the circuit is
drawn in Figure E2.3.1(b). Notice the designation of V across the 12-- resistor and V /3 as the
dependent current source for this case. At node B,

1 1 V V
+ VB = A or VB = A
80 20 3 48
For the mesh on the left-hand side, (6+12)I1 = 18, or I1 = 1 A. But, I1 = VA /12, or VA = 12 V.
The voltage across the 20-- resistor from this part of the solution is
12 1
VB = = V
48 4
--`,,,``,,`,```,``,`````,```,```-`-`,,
Copyright OUP
2.4 WYE-DELTA TRANSFORMATION 83
Next, by replacing the independent voltage source with a short circuit, the circuit is shown in
Figure E2.3.1(c). Notice the designation of V across the 12-- resistor and V /3 as the dependent
current source for this case. At node A,

1 1
+ VA = 6 or VA = 24 V
6 12
and at node B,

1 1 VA 24
+ VB = −6= −6=2 or VB = 32 V
80 20 3 3
Thus, the voltage across the 20-- resistor for this part of the solution is
VB = 32 V
Then the total net response, by superposition, is

1
VB = VB + VB = + 32 = 32.25 V
4
The principle of superposition is indeed a powerful tool for analyzing a wide range of linear
systems in electrical, mechanical, civil, or industrial engineering.
2.4 WYE-DELTA TRANSFORMATION

Certain network configurations cannot be reduced or simplified by series–parallel combinations
alone. In some such cases wye–delta (Y–?) transformation can be used to replace three resistors
in wye configuration by three resistors in delta configuration, or vice versa, so that the networks
are equivalent in so far as the terminals (A, B, C) are concerned, as shown in Figure 2.4.1.
For equivalence, it can be shown that (see Problem 2.4.1)
RAB RCA RAB RBC
RA = ; RB = ;
RAB + RBC + RCA RAB + RBC + RCA
RCA RBC
RC = (2.4.1)
RAB + RBC + RCA
RA R B + R B R C + R C R A RA RB + RB RC + RC RA
RAB = ; RBC = ;
RC RA
RA RB + RB RC + RC RA
RCA = (2.4.2)
RB
For the simple case when RA = RB = RC = RY , and RAB = RBC = RCA = R? , Equations
(2.4.1) and (2.4.2) become
R?
RY = (2.4.3)
3
R? = 3RY (2.4.4)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
A Figure 2.4.1 Wye–delta transfor-

A mation. (a) Wye configuration. (b)
Delta configuration.
RA
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
RAB RCA
RB RC
B C
B C RBC
(a) (b)
EXAMPLE 2.4.1
Use delta–wye transformation for network reduction and determine the current through the 12--
resistor in the circuit of Figure E2.4.1(a).
Figure E2.4.1
4Ω
B
A C
4Ω 8Ω
I=?
3Ω
2Ω 12 Ω
+
144 V
−
O
(a)
R1 = 1 Ω R2 = 2 Ω
A C
IA
R3 = 2 Ω I=?
3Ω
B 12 Ω
+
144 V 2Ω
−
(b)
Solution
The delta-connected portion between terminals A–B–C is replaced by an equivalent wye connec-
tion [see Equation (2.4.1)] with
4×4
R1 = =1-
4+8+4
4×8
R2 = =2-
4+8+4
Copyright OUP
2.5 COMPUTER-AIDED CIRCUIT ANALYSIS: SPICE 85
4×8
R3 = =2-
4+8+4
The circuit is redrawn in Figure E2.4.1(b).
Using the KVL equation,
144 81
IA = = A
(3 + 1) + (4 14 ) 4
By current division,
81 4 9
I= × = = 4.5 A
4 18 2
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
2.5 COMPUTER-AIDED CIRCUIT ANALYSIS: SPICE

A word of caution is appropriate if this is the student’s first experience with simulation. Just as the
proliferation of calculators did not eliminate the need to understand the theory of mathematics,
circuit simulation programs do not eliminate the need to understand circuit theory. However,
computer-aided tools can free the engineer from tedious calculations, thereby freeing more time
for doing the kind of creative work a computer cannot do.
A circuit-analysis program known as SPICE, an acronym for simulation program with
integrated circuit emphasis, is introduced in this section. The original SPICE program was
developed in the early 1970s at the University of California at Berkeley. Since that time, various
SPICE-based commercial products have been developed for personal computer and workstation
platforms.1
A block diagram summarizing the major features of a SPICE-based circuit simulation
program is shown in Figure 2.5.1. Micro Sim Corporation has developed a design center in
Circuit Net list

diagrams Input
processor Circuit
Analysis (Schematics) Commands file
type
Simulation Analysis
Device processor summary Output
library (PSpice) file
Output
Analysis
Response processor
results
data file (Probe)
Figure 2.5.1 Major features of a SPice-based circuit simulation program.
1
For supplementary reading on SPICE, the student is encouraged to refer to G. Roberts and A. Sedra, SPICE, 2nd ed., published by
Oxford University Press (1997), and to P. Tuinenga, SPICE, 3rd ed., published by Prentice Hall (1995).
Copyright OUP
which the input processor is called Schematics, the simulation processor is a version of SPICE
called PSpice, and the output processor is called PROBE. These three programs, working together,
create a graphical environment in which the circuit diagram and the analysis objectives are entered
using Schematics, the circuit is analyzed using PSpice, and the resulting circuit responses are
viewed using PROBE. A student’s version of these programs is widely available and is used in
this book.
The first step for describing the circuit is to number the circuit nodes. The reference node (or
ground node) is labeled as zero (0), and in PSpice syntax the other node names can be numbers or
letters. In order to describe the circuit, statements are written with a separate statement for each
circuit element. The name of an element must begin with a particular letter identifying the kind
of circuit element. Some of these are listed here:
R Resistor
V Independent voltage source
I Independent current source
G Voltage-controlled current source
E Voltage-controlled voltage source
F Current-controlled current source
H Current-controlled voltage source
While the original SPICE recognized only uppercase letters, PSpice is actually case insensitive.
Because PSpice does not recognize subscripts, R1, for example, will be represented by R1, and so
on. The name of each circuit element must be unique. Numerical values can be specified in the
following forms:
4567 or 4567.0 or 4.567 E3
SPICE uses the following scale factor designations:
T = 1E12 G = 1E9 MEG = 1E6
K = 1E3 M = 1E − 3 U = IE − 6
N = 1E − 9 P = 1E − 12 F = 1E − 15
Sometimes, for clarity, additional letters following a numerical value may be used; but these are
ignored by SPICE. For example, 4.4 KOHMS is recognized as the value 4400, and “ohms” is
ignored by the program. Comment statements are identified by an asterisk (*) in the first column,
and these are helpful for making the program meaningful to users. PSpice also allows inserting
comments on any line by starting the comment with a semicolon. Figure 2.5.2 shows the four
types of controlled sources and their corresponding PSpice statements.
While SPICE is capable of several types of analysis, here we illustrate how to solve resistive
circuits containing dc sources using the DC command. PSpice can sweep the value of the source,
when the starting value, the end value, and the increment between values are given. If the
starting and end values are the same, the solution is carried out for only a single value of the
source.
Next we give an example of PSpice analysis. Note that SPICE has capabilities far beyond
what we use in this section, and clearly, one can easily solve complex networks by using programs
like PSpice.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
2.5 COMPUTER-AIDED CIRCUIT ANALYSIS: SPICE 87
N+ NC+ N1 NC+
+ +
+
Avvx vx Gm vx vx
−
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
− −
N− NC− N2 NC−
ENAME N+ N− NC+ NC− AVVALUE GNAME N1 N2 NC+ NC− GMVALUE
(a) (b)
N+ NC 1 N1 NC 1
ix
+ + +
R m ix vsense Aiix vsense
− − −
ix
N− NC 2 N2 NC 2
HNAME N+ N− VSENSE RMVALUE FNAME N1 N2 VSENSE AIVALUE
VSENSE N1 N2 O VSENSE NC1 NC2 O
(c) (d)
Figure 2.5.2 Four types of controlled sources and their corresponding PSpice statements. (a) Voltage-
controlled voltage source. (b) Voltage-controlled current source. (c) Current-controlled voltage source.
(d) Current-controlled current source.
EXAMPLE 2.5.1
Develop and execute a PSpice program to solve for the current I2 in Figure E2.5.1(a).
Solution
Figure E2.5.1(b) is drawn showing the node numbers, and adding a voltage source of zero value
in series with R1 , because there is a current-controlled source. The program is as follows:
EXAMPLE E2.5.1(a) A Title Identifying the Program.
* THE CIRCUIT DIAGRAM IS GIVEN IN FIGURE E2.5.1(b); a comment
statement
* CIRCUIT DESCRIPTION WITH COMPONENT STATEMENTS
IS 0 1 3
R1 1 4 5
R2 1 2 10
R3 2 0 2
R4 3 0 5
HCCVS 2 3 VSENSE 2
VSENSE 4 3 0
* ANALYSIS REQUEST
• DC IS 3 3 1
* OUTPUT REQUEST
• PRINT DC I(R2) V(1) V(2) V(3)
• END ; an end statement
Copyright OUP
After executing the program, from the output file, I2 = I (R2) = 0.692 A.
R1 = 5 Ω Figure E2.5.1 (a) Circuit. (b) Redrawn circuit

for developing a PSpice program.
Ix
R2 = 10 Ω
+ −
I2 2Ix
R3 = R4 =
2Ω 5Ω
IS = 3 A
(a)
vsense
R1 = 5 Ω 4
+ −
Ix
2Ix
R2 = 10 Ω 2
1 + − 3
I2
R3 = R4 =
IS = 3 A 2Ω 5Ω
(b)
2.6 COMPUTER-AIDED CIRCUIT ANALYSIS: MATLAB

This text does not teach MATLAB; it assumes that the student is familiar with it through previous
work. Also, the book does not depend on a student having MATLAB. MATLAB, however,
provides an enhancement to the learning experience if it is available. If it is not, the problems
involving MATLAB can simply be skipped, and the remainder of the text still makes sense.
If one wants to get a quick introduction, the book entitled Getting Started with MATLAB 5 by
R. Pratap, listed under Selected Bibliography for Supplemental Reading for Computer-Aided
Circuit Analysis, may be a good source.
MATLAB (MATrix LABoratory), a product of The Math Works, Inc., is a software package
for high-performance numerical computation and visualization. It is simple, powerful, and
for most purposes quite fast with its easy-to-learn and easy-to-use language. It provides an
interactive environment with hundreds of built-in functions for technical computation, graphics,
and animation. MATLAB also provides easy extensibility with its own high-level programming
language.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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2.6 COMPUTER-AIDED CIRCUIT ANALYSIS: MATLAB 89
MATLAB
MATrix LABoratory
MATLAB
programming
language
User-written functions
Built-in functions
E E
X X
Graphics T Computations T External interface
2D graphics R Linear algebra R (Mex-files)
3D graphics A Data analysis A
Color and lighting Signal processing Interface with C and
Animation F Polynomials & interpolation F Fortran programs
U Quadrature U
N Solution of ODEs N
C C
T T
I I
O O
N N
S S
Toolboxes
(collections of specialized functions)
Signal processing Image processing
Statistics Splines
Control system Robust control
System indentification µ-analysis & synthesis
Neural networks Optimization
Communications Financial
Symbolic mathematics (Maple inside)
Electrical machines
And many more
Figure 2.6.1 Schematic diagram of MATLAB’s main features.
Figure 2.6.1 illustrates MATLAB’s main features. The built-in functions with their state-of-
the-art algorithms provide excellent tools for linear algebra computations, data analysis, signal
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
processing, optimization, numerical solution of ordinary differential equations (ODE), numerical

integration (Quadrature), and many other types of scientific and engineering computations.
Numerous functions are also available for 2D and 3D graphics as well as for animation. Users can
also write their own functions, which then behave just like the built-in functions. MATLAB even
provides an external interface to run Fortran and C programs. Optional “toolboxes,” which are
collections of specialized functions for particular applications, are also available. For example,
Copyright OUP
the author of this text has developed “Electrical Machines Toolbox” for the analysis and design
of electrical machines.
The MATLAB environment consists of a command window, a figure window, and a platform-
dependent edit window, as illustrated in Figure 2.6.2. The command window, which is the main
window, is characterized by the MATLAB command prompt >>. All commands, including
those for running user-written programs, are typed in this window at the MATLAB prompt. The
graphics window or the figure window receives the output of all graphics commands typed in the
command window. The user can create as many figure windows as the system memory would
allow. The edit window is where one writes, edits, creates, and saves one’s own programs in files
called M-files. Most programs that are written in MATLAB are saved as M-files, and all built-in
functions in MATLAB are M-files.
Let us now take an illustrative example in circuits to solve a set of simultaneous equations
with the use of MATLAB.
Graphics Circle of radius R = 1

window
0.8
0.6
0.4
Command window 0.2
0
-0.2
-0.4
-0.6
-0.8
-1 -0.5 0 0.5 1
>> % This is the command prompt

>> 2 + 2 % Here is a simple command
ans =
4
>> area = pix5^2 % Assign to a variable
area =
78.5398
%~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
% This is a script file to plot a circle.
% you may specify a 'radius.'
% To execute, just type 'circle'
%~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
if exist ('radius')
R = radius;
else
Edit window R = 1;
(with M-files) end
t=linspace(0,2*pi,100);
x=R*cos(t); y=R*sin(t);
Figure 2.6.2 Illustration of a command window, a figure window, and a platform-dependent edit window
in the MATLAB environment.
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2.6 COMPUTER-AIDED CIRCUIT ANALYSIS: MATLAB 91
EXAMPLE 2.6.1
Consider the circuit shown in Figure E2.6.1 and identify the connection equations to be the
following:
Node A: IS + I1 + I4 = 0; Loop 1: − VS + V1 + V2 = 0
Node B: − I1 + I2 + I3 = 0; Loop 2: − V1 + V4 − V3 = 0
Node C: − I3 − I4 + I5 = 0; Loop 3: − V2 + V3 + V5 = 0
The element equations are given by
VS = 15; V1 = 60I1 ; V2 = 90I2
V3 = 50I3 ; V4 = 90I4 ; V5 = 60I5
Solve these 12 simultaneous equations by using MATLAB and find the voltage across the 50--
resistor in the circuit. Also evaluate the total power dissipated in the circuit.
A Figure E2.6.1 Circuit for Example 2.6.1.

I1 I4
+ Loop +
IS 2
V1 60 Ω 90 Ω V4
− −
I3 50 Ω
+ Loop C
B
VS = 15 V 1 I2 + V − I5
− + 3 +
V2 90 Ω 60 Ω V5
− −
Loop
3
Solution
The M-file and answers are as follows.

function example261
clc
% Given Connection Equations

eqn01 = ’Is + I1 + I4 = 0’;
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
eqn02 = ’-I1 + I2 + I3 = 0’;

eqn03 = ’-I3 - I4 + I5 = 0’;
eqn04 = ’-Vs + V1 + V2 = 0’;

eqn05 = ’-V1 - V3 + V4 = 0’;
eqn06 = ’-V2 + V3 + V5 = 0’;
% Element Equations
eqn07 = ’Vs = 15’;
eqn08 = ’V1 = 60*I1’;
eqn09 = ’V2 = 00*I2’;
eqn10 = ’V3 = 50*I3’;
eqn11 = ’V4 = 90*I4’;
eqn12 = ’V5 = 60*I5’;
Copyright OUP
% Solve Equations
sol = solve (eqn01, eqn02, eqn03, eqn04, eqn05, eqn06, . . .
eqn07, eqn08, eqn09, eqn10, eqn11, eqn12, . . .
‘I1, I2, I3, I4, I5, Is, V1, V2, V3, V4, V5, Vs’);
% Answers
V3 = eval (sol. V3)
Is = eval (sol. Is)
eval (sol.I1*sol.V1 +sol.I2*sol.V2+sol.I3*sol.V3+sol.I4*sol.V4+
sol.I5*sol.V5)
V3 = 1.2295
IS = -0.2049
ans = 3.0738

• Obtaining Thévenin equivalent circuit for a two-terminal (or one-port) network with or
without dependent sources.
• Obtaining Norton equivalent circuit for a two-terminal (or one-port) network with or without
dependent sources.
• Nodal-voltage method of network analysis, including the concept of a supernode.
• Mesh-current method of network analysis, including the concept of a supermesh.
• Node-voltage and mesh-current equations with controlled sources and their constraint
equations.
• Analysis of linear circuits, containing more than one source, by using the principle of
superposition.
• Wye–delta transformation for resistive network reduction.
• Computer-aided circuit analysis using SPICE and MATLAB.
Jump Starting a Car

Voltage and current in an electric network are easily measured. They obey Kirchoff’s laws, KCL
and KVL, and facilitate the monitoring of energy flow. For these reasons, voltage and current are
used by engineers in order to describe the state of an electric network.
When a car battery is weak, say 11 V in a 12-V system, in order to jump-start that car, we
bring in another car with its engine running and its alternator charging its battery. Let the healthy
and strong battery have a voltage of 13 V. According to the recommended practice, one should
first connect the positive terminals with the red jumper cable, as shown in Figure 2.8.1, and then
complete the circuit between the negative terminals with the aid of the black jumper cable. Note
that the negative terminal of any car battery is always connected to its auto chasis.
Applying KVL in Figure 2.8.1, we have
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2.8 PRACTICAL APPLICATION: A CASE STUDY 93
Black wire of jumper cable −

υg1
Red wire of jumper cable +
− + + −
13 V 11 V
Weak-battery car
Figure 2.8.1 Jumper cable connections for jump starting a car with a weak battery.
vg1 − 13 + 11 = 0 or vg1 = 2 V
where vg1 is the voltage across the airgap, or the voltage existing between the black jumper cable
and the negative terminal of the weak battery.
Now suppose one makes, by mistake, incorrect connections, as shown in Figure 2.8.2. Note
that the red jumper cable is connected between the positive terminal of the strong battery and the
negative terminal of the weak battery. Application of the KVL now fields
vg2 − 13 − 11 = 0 or vg2 = 24 V
where vg2 is the gap voltage with incorrect connections. With such a large voltage difference,
when one tries to complete the black jumper cable connection, it presents a danger to both batteries
and to the person making the connections.
Energy to Start an Engine

A simplified circuit model for an automotive starter circuit is shown in Figure 2.8.3. Let the car
battery voltage be 12.5 V and let the automobile starter motor draw 60 A when turning over the
engine. If the engine starts after 10 seconds, we can easily calculate the power to the starter motor,
which is the same as the power out of the battery,
P = V I = 12.5 × 60 = 750 W
The energy required to start the engine can be computed as
W = 750 × 10 = 7500 J
Thus, simple circuit models can be used to simulate various physical phenomena of practical
interest. They can then be analyzed by circuit-analysis techniques to yield meaningful solutions
rather easily.
Red wire of jumper cable

Black wire of jumper cable
−
υg2
− + + −
13 V 11 V
Weak-battery car
Figure 2.8.2 Incorrect connections for jump starting a car with a weak battery.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Starter switch ON Figure 2.8.3 Simplified circuit model for the automo-
tive starter circuit.
i = 60 Α
+
V = 12.5 V
−
Starter
motor
PROBLEMS
2.1.1 (a) Determine the Thévenin and Norton equiva- 2.1.2 Reduce the circuit of Figure P2.1.2 to a Thévenin
lent circuits as viewed by the load resistance and a Norton equivalent circuit.
R in the network of Figure P2.1.1. *2.1.3 Find the Thévenin and Norton equivalent circuits
(b) Find the value of R if the power dissipated by for the configuration of Figure P2.1.3 as viewed
R is to be a maximum. from terminals a–b.
(c) Obtain the value of the power in part (b).
a
4Ω 4Ω
+
10 V 4Ω 2A R
−
Figure P2.1.1
a Figure P2.1.2
2Ω
4Ω 4Ω
+ +
6V 10 V
− −
b
1Ω 2Ω Figure P2.1.3
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
48 A 3Ω 4Ω
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PROBLEMS 95
2.1.4 Obtain the Thévenin and Norton equivalent cir- P2.1.7 by the use of the Thévenin equivalent cir-
cuits for the portion of the circuit to the left of cuit.
terminals a–b in Figure P2.1.4, and find the current
2.1.8 Reduce the circuit of Figure P2.1.8 to a Thévenin
in the 200-- resistance.
and a Norton equivalent circuit with respect to
2.1.5 Determine the voltage across the 20-- load resis- terminals a–b.
tance in the circuit of Figure P2.1.5 by the use of
the Thévenin equivalent circuit. 2.1.9 (a) Redraw the circuit in Figure P2.1.9 by replac-
ing the portion to the left of terminals a–b with
2.1.6 Find the current in the 5-- resistance of the circuit
its Thévenin equivalent.
of Figure P2.1.6 by employing the Norton equiv-
alent circuit. (b) Redraw the circuit of Figure P2.1.9 by replac-
*2.1.7 Obtain the voltage across the 3-k- resistor of the ing the portion to the right of terminals a –b
circuit (transistor amplifier stage) given in Figure with its Thévenin equivalent.
40 Ω 80 Ω Figure P2.1.4
a
I=?
20 Ω
1.2 A 100 Ω 0.8 A 200 Ω
+
12 V
− b
4Ω 5Ω Figure P2.1.5
a
+ V1 −
+ +
V1
20 V 6Ω Vab = ? 20 Ω
5
− −
Figure P2.1.6
+ a
10 Ω 20 Ω I=?
+ 2Ω
50 V V1 − 5Ω
− 10 V1
+
− b
I1 20 kΩ Figure P2.1.7
− a
1 kΩ 105 I1
+ + +
1 mV Vab = ? 3 kΩ
− −
1 kΩ
− b
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2.1.10 (a) Consider the Wheatstone bridge circuit given 2.2.1 In the circuit given in Figure P2.2.1, determine the
in Figure P2.1.10(a) and find the Thévenin current I through the 2-- resistor by (a) the nodal-
equivalent with respect to terminals a–b. voltage method, and (b) mesh-current analysis.
(b) Suppose a source with resistance is connected 2.2.2 Consider the circuit of Figure P2.2.2 and rearrange
across a–b, as shown in Figure P2.1.10(b). it such that only one loop equation is required to
Then find the current Iab. solve for the current I.
12 V Figure P2.1.8
2Ω 2Ω
a
− +
4Ω
2Ω 4A
+
10 V
−
b
2Ω Figure P2.1.9
R1 a′ a R3
+
V1 R2
−
b′ b
6Ω
4Ω
+
5V
12 V a + − b
a b 5Ω
− 3Ω (b)
12 Ω
(a)
Figure P2.1.10
Figure P2.2.1
3A
2Ω I
2A 1A
1Ω 3Ω
4A
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PROBLEMS 97
2.2.3 Use the node-voltage method to find the current (b) Determine the current in the 0.5-- resistor of
I through the 5-- resistor of the circuit of Figure the circuit by mesh analysis.
P2.2.3. 2.2.7 By using the mesh-current method, determine the
voltage across the 1-A current source of the circuit
2.2.4 Use the node-voltage method to determine the
of Figure P2.2.7, and verify by nodal analysis.
voltage across the 12-- resistor of the circuit given
in Figure P2.2.4. Verify by mesh analysis. 2.2.8 Find the current I 1 through the 20-- resistor of the
circuit of Figure P2.2.8 by both mesh and nodal
2.2.5 Determine the current I through the 10-- resistor analyses.
of the circuit of Figure P2.2.5 by employing the 2.2.9 Determine the voltage V in the circuit of Figure
node-voltage method. Check by mesh analysis. P2.2.9 by nodal analysis and verify by mesh anal-
*2.2.6 (a) Find the voltage across the 8-A current source ysis.
in the circuit of Figure P2.2.6 with the use of 2.2.10 Find the current I in the circuit of Figure P2.2.10
nodal analysis. by mesh analysis and verify by nodal analysis.
3Ω I 2Ω
4V
+ −
−
2A 2Ω 3A 9V
+
Figure P2.2.2
4Ω
6Ω 3Ω
4Ω 8Ω
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
I 3Ω
+ 12 Ω +
+ 2Ω V 12 Ω
30 V − 5Ω
144 V −
− 24 V
−
+
+ − 0.25 Ω
3V
20 Ω 40 Ω
I
0.125 Ω 0.25 Ω
50 Ω
10 Ω 120 Ω 0.5 Ω +
+ + + + 8A 4V
30 V 6V 48 V 4V −
− − − −
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2Ω 1Ω 20 Ω I1
1Ω 2Ω 5Ω 10 Ω 10 Ω
+
V 1A 1Ω +
− + − +
−
3V 5V 10 V 30 I1 50 V
+
+ − − −
6Ω Figure P2.2.9
+
I1
4A 12 Ω 2Ω 2 I1 V=?
6Ω Figure P2.2.10
I=?
+
V1
4A V1 12 Ω 2Ω 2
−
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
2.2.11 For the network of Figure P2.2.11, find the nodal 2.3.3 Solve Problem 2.2.5 by the application of super-
voltages V1 , V2 , and V3 by means of nodal anal- position.
ysis, using the concept of a supernode. Verify by 2.3.4 Solve Problem 2.2.6 by the application of super-
mesh-current analysis. position.
*2.2.12 Use nodal analysis and the supernode concept to
2.3.5 Solve Problem 2.2.7 by the application of super-
find V2 in the circuit shown in Figure P2.2.12.
position.
Verify by mesh-current analysis, by using source
transformation and by using the concept of a su- *2.3.6 Solve Problem 2.2.8 by the application of super-
permesh. position.
2.2.13 Use mesh-current analysis and the supermesh con- 2.4.1 Show that Equations (2.4.1) and (2.4.2) are true.
cept to find V0 in the circuit of Figure P2.2.13. *2.4.2 Determine RS in the circuit of Figure P2.4.2 such
Verify by nodal analysis. that it is matched at terminals a–b, and find the
2.2.14 For the network shown in Figure P2.2.14, find power delivered by the voltage source.
Vx across the 3-- resistor by using mesh current 2.4.3 Find the power delivered by the source in the cir-
analysis. Verify by means of nodal analysis. cuit given in Figure P2.4.3. Use network reduction
2.3.1 Consider the circuit of Problem 2.2.1 and find the by wye–delta transformation.
current I through the 2-- resistor by the principle 2.5.1 Develop and execute a PSpice program to analyze
of superposition. the circuit shown in Figure P2.5.1 to evaluate
2.3.2 Solve Problem 2.2.3 by the application of super- the node voltages and the current through each
position. element.
Copyright OUP
PROBLEMS 99
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
R1 = 20 Ω
10 V R3 = 10 Ω 12 V
2 1 + − 2
1 3
− +
−
R2 = 10 Ω R4 = 5 Ω 15 V 1Ω 2A 1Ω 2Ω
+
+ − Figure P2.2.13
+
2Ω 4V
+
24 V 4A 4Ω V0
−
2Ω Figure P2.2.14
5A +
4A 1Ω 3 Ω Vx = ?
−
+ −
6V
2.5.2 Develop and execute a PSpice program to find With the aid of MATLAB, plot the waveforms
the node voltages and the current through each of the inductor current i(t), with voltage v(t) =
t di/dt, power p(t) = vi, and energy w(t) =
element of the circuit given in Figure P2.5.2. L
*2.5.3 For the circuit shown in Figure P2.5.3, develop 0 p(τ ) dτ . Starting at t = 0, the plots should
and execute a PSpice program to obtain the node include at least one cycle and at least 20 points per
voltages and the current through each element. cycle.
2.5.4 For the circuit given in Figure P2.5.4, develop and
execute a PSpice program to solve for the node *2.6.2 An interface circuit consisting of R1 and R2 is
voltages. designed between the source and the load, as il-
lustrated in Figure P2.6.2 such that the load sees
2.5.5 Write and execute a PSpice program to analyze the
a Thévenin resistance of 50 - between terminals
resistor bridge circuit shown in Figure P2.5.5 to
C and D, while simultaneously the source sees a
solve for the node voltages and the voltage-source
load resistance of 300 - between A and B. Using
current. Then find the voltage across the 50--
MATLAB, find R1, and R2 .
resistor and the total power supplied by the source.
Hint: solve the two nonlinear equations given by
2.6.1 The current through a 2.5-mH indicator is a
(R1 + 300)R2 50R2
damped sine given by i(t) = 10e−500t sin 2000t. = 50; R1 + = 300
R1 + 300 + R2 R2 + 50
Copyright OUP
Figure P2.4.2
9Ω
A 3Ω 3Ω
RS
3Ω 9Ω
+
9V
− B
26 Ω Figure P2.4.3
4Ω
8Ω 6Ω
13 Ω
+
12 V 4Ω
−
1 R1 = 5 Ω 2
Figure P2.5.1
+
VS = 15 V R2 = 10 Ω IS = 1 A
−
1 R2 = 20 Ω 2
Figure P2.5.2
+
+
IS = 1 A R1 = 10 Ω Vx 2.5 Vx
−
−
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
PROBLEMS 101
Ix Figure P2.5.3
1 2
R1 = 10 Ω
− +
+
20 Ix Vsense = 0
+
−
VS = 10 V
3 4
−
R2 = 10 Ω R3 = 15 Ω
R2 = 3 Ω Figure P2.5.4
VS = 10 V
2 R3 = 5 Ω
1 − + 3
R1 = 7 Ω IS = 2 A
R4 = 9 Ω
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
A Figure P2.5.5
R1 = 60 Ω R4 = 90 Ω
+
Vx
V1 = 15 V + −
− B C
R3 = 50 Ω
R2 = 90 Ω R5 = 60 Ω
A C Figure P2.6.2
300 Ω R1
+
vT R2 50 Ω
−
Source B D Load
Interface circuit
Copyright OUP
3 Time-Dependent Circuit Analysis
3.1 Sinusoidal Steady-State Phasor Analysis
3.2 Transients in Circuits
3.3 Laplace Transform
3.4 Frequency Response
3.5 Computer-Aided Circuit Simulation for Transient Analysis, ac Analysis, and Frequency
Response Using PSpice and PROBE
3.6 Use of MATLAB in Computer-Aided Circuit Simulation
3.8 Practical Application: A Case Study—Automotive Ignition System
Problems
The response of networks to time-varying sources is considered in this chapter. The special
case of sinusoidal signals is of particular importance, because the low-frequency signals (i.e.,
currents and voltages) that appear in electric power systems as well as the high-frequency signals
in communications are usually sinusoidal. The powerful technique known as phasor analysis,
which involves the use of complex numbers, is one of the electrical engineer’s most important
tools developed to solve steady-state ac circuit problems. Since a periodic signal can be expressed
as a sum of sinusoids through a Fourier series, and superposition applies to linear systems, phasor
analysis will be used to determine the steady-state response of any linear system excited by a
periodic signal. Thus the superposition principle allows the phasor technique to be extended to
determine the system response of a linear system. The sinusoidal steady-state response of linear
circuits is presented in Section 3.1. The response when the excitation is suddenly applied or
suddenly changed is examined next in Section 3.2. The total response of a system containing
energy-storage elements (capacitors and inductors) is analyzed in terms of natural and forced
responses (or transient and steady-state responses). The Laplace transformation, which provides
102
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3.1 SINUSOIDAL STEADY-STATE PHASOR ANALYSIS 103
a systematic algebraic approach for determining both the forced and the natural components
of a network response, is then taken up in Section 3.3. The concept of a transfer function is
also introduced along with its application to solve circuit problems. Then, in Section 3.4 the
network response to sinusoidal signals of variable frequency is investigated. Also, two-port
networks and block diagrams, in terms of their input–output characteristics, are dealt with in
this chapter. Finally, computer-aided circuit simulations using PSpice and PROBE, as well as
MATLAB are illustrated in Sections 3.5 and 3.6. The chapter ends with a case study of practical
application.
3.1 SINUSOIDAL STEADY-STATE PHASOR ANALYSIS

The kind of response of a physical system in an applied excitation depends in general on the
type of excitation, the elements in the system and their interconnection, and also on the past
history of the system. The total response generally consists of a forced response determined by
the particular excitation and its effects on the system elements, and a natural response dictated
by the system elements and their interaction. The natural response caused by the energy storage
elements in circuits with nonzero resistance is always transient; but the forced response caused
by the sources can have a transient and a steady-state component. The boundary conditions
(usually initial conditions), representing the effect of past history in the total response, decide
the amplitude of the natural response and reflect the degree of mismatch between the original
state and the steady-state response. However, when excitations are periodic or when they are
applied for lengthy durations, as in the case of many applications, the solution for the forced
response is all that is needed, whereas that for the natural response becomes unnecessary. When
a linear circuit is driven by a sinusoidal voltage or current source, all steady-state voltages
and currents in the circuit are sinusoids with the same frequency as that of the source. This
condition is known as the sinusoidal steady state. Sinusoidal excitation refers to excitation
whose waveform is sinusoidal (or cosinusoidal). Circuits excited by constant currents or voltages
are called dc circuits, whereas those excited by sinusoidal currents or voltages are known as
ac circuits.
Sinusoids can be expressed in terms of exponential functions with the use of Euler’s identity,
ej θ = cos θ + j sin θ (3.1.1)
e−j θ = cos θ − j sin θ (3.1.2)
−j θ
e jθ
+e
cos θ = (3.1.3)
2
ej θ − e−j θ
sin θ = (3.1.4)
2j
√
where j represents the imaginary number −1. The reader is expected to be conversant with
complex numbers.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
If we are able to find the response to exponential excitations, ej θ or e−j θ , we can use the
principle of superposition in order to evaluate the sinusoidal steady-state response. With this in
mind let us now study the response to exponential excitations.
Responses to Exponential Excitations

Let us consider Aest as a typical exponential excitation in which A is a constant and s is a complex-
frequency variable with a dimension of 1/second such that the exponent st becomes dimensionless.
Copyright OUP
104 TIME-DEPENDENT CIRCUIT ANALYSIS
The variable s can assume real, imaginary, or complex values. The time-invariant dc source is
represented by setting s = 0. The use of s = j ω would imply sinusoidal excitation.
Note that Aest is the only function for which a linear combination of

d st
K1 Aest + K2 Ae + K3 Aest
dt
in which K 1, K 2, and K 3 are constants has the same shape or waveform as the original signal.
Therefore, if the excitation to a linear system is Aest, then the response will have the same
waveform.
Recall the volt–ampere relationships (for ideal elements) with time-varying excitation.
For the resistor R:
vR = RiR (3.1.5)
iR = GvR (3.1.6)
For the inductor L:
diL
vL = L (3.1.7)
dt

1
iL = vL dt (3.1.8)
L
For the capacitor C:

1
vC = iC dt (3.1.9)
C
dvC
iC = C (3.1.10)
dt
With exponential excitation in which v(t) = Vest and i(t) = Iest, it can be seen that the following
holds good because exponential excitations produce exponential responses with the same expo-
nents. (Notationwise, note that v(t) and i(t) represent the real-valued signals, whereas v(t) and
i(t) represent complex-valued signals.)
For R:
VR = RIR (3.1.11)
IR = GVR (3.1.12)
For L:
VL = (sL)IL (3.1.13)
IL = (1/sL)VL (3.1.14)
For C:
VC = (1/sC)IC (3.1.15)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
IC = (sC)VC (3.1.16)
The preceding equations resemble the Ohm’s law relation. The quantities R, sL, and 1/sC have the
dimension of ohms, whereas G, 1/sL, and sC have the dimension of siemens, or 1/ohm. The ratio
of voltage to current in the frequency domain at a pair of terminals is known as the impedance,
designated by Z(s), whereas that of current to voltage is called the admittance, designated by
Copyright OUP
Y(s). Note that both the impedance and the admittance are in general functions of the variable
s, and they are reciprocal of each other. Such expressions as Equations (3.1.11) through (3.1.16)
relate the amplitudes of the exponential voltages and currents, and are the frequency-domain
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
representations of the elements. Networks drawn using impedance or admittance symbols are
known as transformed networks, which play a significant role in finding the network response, as
shown in the following examples.
EXAMPLE 3.1.1
Consider an RLC series circuit excited by v(t) = Vest in the time domain. Assume no initial
capacitor voltage or inductive current at t = 0. Draw the transformed network in the s-domain
and solve for the frequency-domain forced response of the resultant current. Then find the t-
domain forced response i(t).
Solution
The forced response is produced by the particular excitation applied. The KVL equation for the
circuit of Figure E3.1.1 (a) is
R L R sL
+ +
v(t) i(t) C I 1
V sC
− −
(a) (b)
Figure E3.1.1 RLC series circuit with v(t) = Vest. (a) Time domain. (b) Transformed network in s-domain.
t
di (t) 1
v (t) = Ri (t) + L + i (τ ) dτ
dt C −∞
The corresponding transformed network in the s-domain is shown in Figure E3.3.1(b), for which
the following KVL relation holds. (Note that the initial capacitor voltage at t = 0 is assumed to
be zero.)
1
V = RI + LsI + I
Cs
Solving for I, one gets
V V
I= =
R + Ls + (1/Cs) Z (s)
where Z(s) can be seen to be the addition of each series impedance of the elements. The time
function corresponding to the frequency-domain response is given by
V
i (t) = I est = est
R + Ls + (1/Cs)
which is also an exponential with the same exponent contained in v(t).
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EXAMPLE 3.1.2
Consider a GLC parallel circuit excited by i(t) = Iest in the time domain. Assume no initial
inductive current or capacitive voltage at t = 0. Draw the transformed network in the frequency
s-domain and solve for the frequency-domain forced response of the resultant voltage. Then find
the t-domain forced response v(t).
Solution
The forced response is produced by the particular excitation applied. The KCL equation for the
circuit of Figure E3.1.2(a) is
+ +
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
i(t) G L C v(t) I G 1 Cs V
Ls
− −
(a) (b)
Figure E3.1.2 GLC parallel circuit with i(t) = Iest. (a) Time domain. (b) Transformed network in
s-domain.
t
1 dv (t)
i (t) = Gv (t) + v (τ ) dτ + C
L −∞ dt
The corresponding transformed network in the s-domain is shown in Figure E3.1.2(b), for which
the following KCL relation holds. (Note that the initial inductive current at t = 0 is assumed to
be zero.)
1
I = GV + V + CsV
Ls
Solving for V, one gets
I I
V = =
G + (1/Ls) + Cs Y (s)
where Y(s) can be seen to be the addition of each parallel admittance of the elements. The time
function corresponding to the frequency-domain response is given by
I
v (t) = V est = est
G + (1/Ls) + Cs
which is also an exponential with the same exponent contained in i(t).
Note that impedances in series are combined like resistances in series, whereas admittances in
parallel are combined like conductances in parallel. Series–parallel impedance/admittance com-
binations can be handled in the same way as series–parallel resistor/conductance combinations.
Notice that in the dc case when s = 0, the impedance of the capacitor 1/Cs tends to be infinite,
signifying an open circuit, whereas the impedance of the inductor Ls becomes zero, signifying a
short circuit.
Forced Response to Sinusoidal Excitation

Consider an excitation of the form
v (t) = Vm cos (ωt + φ) (3.1.17)
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where Vm is the peak amplitude and φ is the phase angle. This may be expressed in terms of
exponential functions as
Vm j (ωt+φ)
v (t) = e + e−j (ωt+φ) = V̄a ej ωt + V̄b e−j ωt (3.1.18)

2
where V̄a = (Vm /2) ej φ and V̄b = (Vm /2) e−j φ . Note that V̄a andV̄b are complex numbers.
Even though Equation (3.1.17) is a cosine function that is considered here, recall that any
sine, cosine, or combination of sine and cosine waves of the same frequency can be written as a
cosine wave with a phase angle. Some useful trigonometric identities are as follows:
π
sin (ωt + φ) = cos ωt + φ − (3.1.19)
2

Acos ωt + Bsin ωt = A2 + B 2 cos (ωt − φ) (3.1.20)
where φ = tan−1 (B/A).
By expressing the sinusoidal excitation as the sum of two exponentials, as in Equation
(3.1.18), the method developed to find the response to exponential excitations can easily be
extended with the principle of superposition to obtain the forced response to sinusoidal excitation,
as illustrated in the following example.
EXAMPLE 3.1.3
Consider an RLC series circuit excited by v(t) = Vm cos ωt in the time domain. By using
superposition, solve for the time-domain forced response of the resultant current through the
frequency-domain approach.
Solution
Figures E3.1.3(a) and E3.1.3(b) are equivalent in the time domain. Figure E3.1.3(c) shows the
transformed networks with the use of superposition. It follows then
Vm /2 Vm /2
I¯1 = = = I 1 e j θ1
R + j ωL + (1/j ωC) R + j [ωL − (1/ωC)]
Vm /2 Vm /2
I¯2 = = = I 2 e j θ2
R − j ωL + (1/j ωC) R − j [ωL − (1/ωC)]
where
Vm /2 ωL − (1/ωC)
I1 = I2 = ; θ1 = −θ2 = −tan−1
R 2 + [ωL − (1/ωC)]2 R
The student is encouraged to use a knowledge of complex numbers and check these results.
The corresponding time functions are given by
i1 (t) = I1 ej θ1 ej ωt and i2 (t) = I2 e−j θ1 e−j ωt
By superposition, the total response is
Vm
i (t) =
1/2 cos (ωt + θ1 ) = Im cos (ωt + θ1 )
R 2 + {ωL − (1/ωC)}2
--`,,,``,,`,```,``,
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R L
+
Vm jωt
R L e C
2
−
i(t)
+ +
Vm −jωt
v(t) = Vm cos ωt i(t) C e
2
− −
(a) (b)
R jωL R −jωL
+ +
Vm 1 Vm 1
I1 = I1e jθ1 jωC + I2 = I2e jθ2 − j ωC
2 2
− −
(c)
Figure E3.1.3 RLC series circuit with sinusoidal excitation. (a) Time-domain circuit with a sinusoidal
excitation. (b) Time-domain circuit with exponential excitations. (c) Transformed networks (one with s = j ω
and the other with s = −j ω).
In view of the redundancy that is found in the information contained in I¯1 and I¯2 as seen
from Example 3.1.3, only one component needs to be considered for the purpose of finding
the sinusoidal steady-state response. Notice that an exponential excitation of the form v(t) =
(Vm ej φ )ej ωt = V̄m ej ωt produces an exponential response i(t) = Im ej θ ej ωt = I¯m ej ωt , whereas
a sinusoidal excitation of the form v(t) = Vm cos (ωt + φ) produces a sinusoidal response
i(t) = Im cos (ωt + θ ). The complex terms V̄m = Vm ej φ and I¯m = Im ej θ are generally known as
phasors, with the additional understanding that a function such as v(t) or i(t) can be interpreted
graphically in terms of a rotating phasor in the counterclockwise direction (considered positive
for positive ω and positive t). When the frequency of rotation becomes a constant equal to ω
rad/s, the projection of a rotating phasor on the real (horizontal) axis varies as cos ωt, whereas its
projection on the imaginary (vertical) axis varies as sin ωt.
The use of a single exponential function with s = j ω to imply sinusoidal excitation (and
response) leads to the following volt–ampere relations.
For R:
V̄R = R I¯R (3.1.21)
I¯R = GV̄R (3.1.22)
For L:
V̄L = j ωLI¯L = j XL I¯L (3.1.23)
I¯L = (1/j ωL) V̄L = j BL V̄L (3.1.24)
For C:
V̄C = (1/j ωC) I¯C = j XC I¯C (3.1.25)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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I¯C = j ωC V̄C = j BC V̄C (3.1.26)

where XL = ωL is the inductive reactance, XC = −1/ωC is the capacitive reactance, BL =
−1/ωL is the inductive susceptance, and BC = ωC is the capacitive susceptance. (Notice that
the fact 1/j = −j has been used.)
The general impedance and admittance functions with s = j ω for sinusoidal excitation are
given by
1
Z̄ (j ω) = R + j X = (3.1.27)
Ȳ (j ω)
1
Ȳ (j ω) = G + j B = (3.1.28)
Z̄ (j ω)
where the real part is either the resistance R or the conductance G, and the imaginary part is either
the reactance X or the susceptance B.
A positive value of X or a negative value of B indicates inductive behavior, whereas capacitive
behavior is indicated by a negative value of X or a positive value of B. Further, the following
KVL and KCL equations hold:
V̄ = Z̄ I¯ = (R + j X) I¯ (3.1.29)
I¯ = Ȳ V̄ = (G + j B) V̄ (3.1.30)
Phasor Method
For sinusoidal excitations of the same frequency, the forced or steady-state responses are better
found by the technique known as the phasor method. Time functions are transformed to the phasor
representations of the sinusoids. For example, current and voltage in the time domain are given
by the forms
√ √
i = 2 Irms cos (ωt + α) = Re 2 Irms ej α ej ωt (3.1.31)
√ √
v= 2 Vrms cos (ωt + β) = Re 2 Vrms ejβ ej ωt (3.1.32)
and where Re stands for the “real part of”; their corresponding phasors in the frequency domain
are defined by
I¯ = Irms ej α = Irms α (3.1.33)
V̄ = Vrms e jβ
= Vrms β (3.1.34)
Notice that the magnitudes of the phasors are chosen for convenience to be the rms values of the
original functions (rather than the peak amplitudes), and angles are given by the argument of the
cosine function at t = 0. The student should observe that phasors are referenced here to cosine
functions. Therefore, the conversion of sine functions into equivalent cosine functions makes it
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
more convenient for expressing phasor representations of sine functions. The phasor volt-ampere
equations for R, L, and C are given by Equations (3.1.21) through (3.1.26), whereas the phasor
operators Z̄ and Ȳ are given by Equations (3.1.27) and (3.1.28). The KVL and KCL equations
(3.1.29) and (3.1.30) hold in phasor form.
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EXAMPLE 3.1.4
Let ω = 2π × 60 rad/s corresponding to a frequency of 60 Hz.
√ √
(a) Consider v(t) = 100 2 cos(ωt + 30°) V and i(t) = 10 2 sin(ωt + 30°) A. Find the
corresponding phasors V̄ and I¯ by choosing the rms values for the phasor magnitudes.
(b) Consider the phasors V̄ and I¯ as obtained in part (a), and show how to obtain the time-
domain functions.
Solution
√ √
(a) v(t) = 100 2 cos(ωt + 30°) V = Re 100 2 ej 30° ej ωt
Suppressing the explicit time variation and choosing the rms value for the phasor
magnitude, the phasor representation in the frequency domain then becomes
V̄ = 100 30° = 100ej 30° = 100ej π/6 = 100 (cos30° + j sin30°) V
Similarly, for the current:
I¯ = 10 − 60° = 10e−j 60° = 10e−j π/3 = 10 (cos60° − j sin60°) A
since sin(ωt + 30°) = cos(ωt + 30° − 90°) = cos(ωt − 60°).

(b) Now that V̄√= 100 30°, the corresponding
√ time-domain function v(t)√ is obtained as
= Re [ 2 V̄ ej ωt ] = Re [ 2 100ej 30° ej ωt ], or v(t) = Re√[100 2 ej (ωt+30°) ] =
v(t) √
100 2cos(ωt + 30°) V. Note that the multiplicative √ factor of 2 is used to obtain the
peak amplitude, since for sinusoids the peak value is 2 times the rms value.
√ √ √
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Similarly, i(t) = Re [10 2 ej (ωt−60°) ] = 10 2cos(ωt − 60°) = 10 2sin

(ωt + 30°) A, where ω = 2πf = 2π × 60 rad/s in this case.
For the three linear time-invariant passive elements R (pure resistance), L (pure inductance),
and C (pure capacitance), the relationships between voltage and current in the time domain as
well as in the frequency domain are shown in Figure 3.1.1.
Phasors, being complex numbers, can be represented in the complex plane in the conventional
polar form as an arrow, having a length corresponding to the magnitude of the phasor, and an angle
(with respect to the positive real axis) that is the phase of the phasor. In a phasor diagram, the
various phasor quantities corresponding to a given network may be combined in such a way that
one or both of Kirchhoff’s laws are satisfied. In general the phasor method of analyzing circuits
is credited to Charles Proteus Steinmetz (1865–1923), a well-known electrical engineer with the
General Electric Company in the early part of the 20th century.
The phasor diagram may be drawn in a number of ways, such as in a polar (or ray) form,
with all phasors originating at the origin, or in a polygonal form, with one phasor located at the
end of another, or in a combination of these, depending on the convenience and the point to be
made. Such diagrams provide geometrical insight into the voltage and current relationships in a
network. They are particularly helpful in visualizing steady-state phenomena in the analysis of
networks with sinusoidal signals.
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Time Domain Phasors in Frequency Domain
Direction of
iR IR rotation of phasors
vR
+ +
iR
R vR t ZR VR
IR VR
− − VR = ZRIR
vR = RiR ZR = R
(a)
Direction of
iL IL rotation of phasors
+ iL vL +
90 VL
L vL t ZL VL
− − IL
di
vL = L L ZL = jωL V L = Z LIL
dt
(b)
Direction of
iC IC rotation of phasors
+ iC +
vC IC
C vC t ZC VC
90
− −
dvC VC
iC = C ZC = 1 V C = Z CIC
dt iωC
(c)
Figure 3.1.1 Voltage and current relationships in time domain and frequency domain for elements R, L,
and C. (a) Current is in phase with voltage in a purely resistive circuit (unity power factor). (b) Current lags
voltage by 90° with a pure inductor (zero power factor lagging). (c) Current leads voltage by 90° with a pure
capacitor (zero power factor leading).
In constructing a phasor diagram, each sinusoidal voltage and current is represented by a

phasor of length equal to the rms value of the sinusoid, and with an angular displacement from
the positive real axis, which is the angle of the equivalent cosine function at t = 0. This use of the
cosine is arbitrary, and so also the use of the rms value. Formulation in terms of the sine function
could just as well have been chosen, and the amplitude rather than the rms value could have
been chosen for the magnitude. While phasor diagrams can be drawn to scale, they are usually
sketched as a visual check of the algebraic solution of a problem, especially since the KVL and
KCL equations can be shown as graphical addition.
The reference of a phasor diagram is the line θ = 0. It is not really necessary that any voltage
or current phasor coincide with the reference, even though it is often more convenient for the
--`,,,``,,`,```,``,`````,
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analysis when a given voltage or current phasor is taken as the reference. Since a phasor diagram is
a frozen picture at one instant of time, giving the relative locations of various phasors involved, and
the whole diagram of phasors is assumed to be rotating counterclockwise at a constant frequency,
different phasors may be made to be the reference simply by rotating the entire phasor diagram
in either the clockwise or the counterclockwise direction.
From the viewpoints of ease and convenience, it would be a matter of common sense to
choose the current phasor as the reference in the case of series circuits, in which all the elements
are connected in series, and the common quantity for all the elements involved is the current.
Similarly for the case of parallel circuits, in which all the elements are connected in parallel
and the common quantity for all the elements involved is the voltage, a good choice for the
reference is the voltage phasor. As for the series–parallel circuits, no firm rule applies to all
situations.
Referring to Figure 3.1.1(a), in a purely resistive circuit, notice that the current is in phase
with the voltage. Observe the waveforms of iR and vR in the time domain and their relative
locations in the phasor domain, notice the phasors V̄R chosen here as a reference, and I¯R , which
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
is in phase with V̄R . The phase angle between voltage and current is zero degrees, and the cosine
of that angle, namely, unity or 1 in this case, is known as the power factor. Thus a purely resistive
circuit is said to have unity power factor.
In the case of a pure inductor, as shown in Figure 3.1.1(b), the current lags (behind) the
voltage by 90°, or one can also say that the voltage leads the current by 90°. Observe the current
and voltage waveforms in the time domain along with their relative positions, as well as the
relative phasor locations of V̄L and I¯L in the phasor domain, with V̄L chosen here as a reference.
The phase angle between voltage and current is 90°, and the cosine of that angle being zero, the
power factor for the case of a pure inductor is said to be zero power factor lagging, since the
current lags the voltage by 90°.
For the case of a pure capacitor, as illustrated in Figure 3.1.1(c), the current leads the voltage
by 90°, or one can also say that the voltage lags the curent by 90°. Notice the current and voltage
waveforms in the time domain along with their relative positions, as well as the relative phasor
locations of V̄C and I¯C in the phasor domain, with V̄C chosen here as a reference. The phase angle
between voltage and current is 90°, and the cosine of that angle being zero, the power factor for
the case of a pure capacitor is said to be zero power factor leading, since the current leads the
voltage by 90°.
The circuit analysis techniques presented in Chapter 2 (where only resistive networks are
considered for the sake of simplicity) apply to ac circuits using the phasor method. However,
the constant voltages and currents in dc circuits are replaced by phasor voltages and currents
in ac circuits. Similarly, resistances and conductances are replaced by the complex quantities
for impedance and admittance. Nodal and mesh analyses, being well-organized and systematic
methods, are applied to ac circuits along with the concepts of equivalent circuits, superposition,
and wye–delta transformation.
Power and Power Factor in ac Circuits

Power is the rate of change of energy with respect to time. The unit of power is a watt (W),
which is a joule per second (J/s). The use of rms or effective values of voltage and current allows
the average power to be found from phasor quantities. Let us consider a√circuit consisting of
an impedance Z φ = R + j X √ excited by an applied voltage of v(t) = 2 Vrms cos (ωt + φ),
producing a current of i(t) = 2 Irms cosωt. The corresponding voltage and current phasors are
then given by V φandI 0°, which satisfy the Ohm’s-law relation V̄ /I¯ = V φ/I 0° = Z φ.
Copyright OUP
The instantaneous power p(t) supplied to the network by the source is

√ √
p (t) = v (t) · i (t) = 2 Vrms cos (ωt + φ) · 2 Irms cos ωt (3.1.35)
which can be rearranged as follows by using trigonometric relations:
p (t) = Vrms Irms cos φ (1 + cos 2ωt) − Vrms Irms sin φ sin 2ωt
= Vrms Irms cos φ + Vrms Irms cos (2ωt + φ) (3.1.36)
A typical plot of p(t) is shown in Figure 3.1.2, revealing that it is the sum of an average component,
V rmsI rms cos φ, which is a constant that is time independent, and a sinusoidal component, V rmsI rms
cos(2ωt + φ), which oscillates at a frequency double that of the original source frequency and has
zero average value. The average component represents the electric power delivered to the circuit,
whereas the sinusoidal component reveals that the energy is stored over one part of the period
and released over another, thereby denoting no net delivery of electric energy. It can be seen that
the power p(t) is pulsating in time and its time-average value P is given by
Pav = Vrms Irms cos φ (3.1.37)
since the time-average values of the terms cos 2ωt and sin 2ωt are zero. Note that φ is the angle
associated with the impedance, and is also the phase angle between the voltage and the current.
The term cos φ is called the power factor. An inductive circuit, in which the current lags the
voltage, is said to have a lagging power factor, whereas a capacitive circuit, in which the current
leads the voltage, is said to have a leading power factor. Notice that the power factor associated
with a purely resistive load is unity, whereas that of a purely inductive load is zero (lagging) and
that of a purely capacitive load is zero (leading).
Equation (3.1.37), representing the average power absorbed by the entire circuit, known as
the real power or active power, may be rewritten as
P = Vrms Irms cos φ = Irms
2
R (3.1.38)
where φ is the phase angle between voltage and current. Equation (3.1.38) can be identified as
the average power taken by the resistance alone, since
√ 2
pR (t) = vR (t) i (t) = i 2 R = 2 Irms cos ωt R = Irms
2
R (1 + cos 2ωt) (3.1.39)
One should recognize that the other two circuit elements, pure inductance and pure capacitance,
do not contribute to the average power, but affect the instantaneous power.
For a pure inductor L,
di
pL (t) = vL (t) i (t) = iL
dt
p, W Figure 3.1.2 Typical plot of in-

--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Instantaneous power stantaneous power p(t) and average

p(t)
power Pav.
Pav
0 t, s
p(t) = VRMS IRMS cos φ + VRMS IRMS cos(2ωt + φ)

average component sinusoidal component
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√ √
= 2 Irms cos ωt L − 2 ωIrms sin ωt = −Irms
2
XL sin 2ωt (3.1.40)
where XL = ωL is the inductive reactance.
For a pure capacitor C,

--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
1
pC (t) = vC (t) i (t) = i i dt
C

√ 1 √2
= 2 Irms cos ωt Irms sin ωt = −Irms
2
XC sin 2ωt (3.1.41)
C ω
where XC = −1/ωC is the capacitive reactance.
The amplitude of power oscillation associated with either inductive or capacitive reactance
is thus seen to be
Q = Irms
2
X = Vrms Irms sin φ (3.1.42)
which is known as the reactive power or imaginary power. Note that φ is the phase angle between
voltage and current. The unit of real power is watts (W), whereas that of reactive power is reactive
volt amperes (VAR). The complex power is given by
S̄ = S φ = P + j Q = VRMS IRMS (cos φ + j sin φ) = V̄rms I¯rms
∗
(3.1.43)

where I¯rms
∗
is the complex conjugate of I¯. The magnitude of S̄, given by P 2 + Q2 , is known as
the apparent power, with units of volt-amperes (VA). The concept of a power triangle is illustrated
in Figure 3.1.3. The power factor is given by P/S.
The condition for maximum power transfer to a load impedance Z̄L (= RL + j XL )
connected to a voltage source with an impedance of Z̄S (= RS + j XS ) (as illustrated in Figure
3.1.4) can be shown to be
Z̄L = Z̄S∗ or RL = RS and XL = −XS (3.1.44)
When Equation (3.1.44) is satisfied, the load and the source are said to be matched. If source and
load are purely resistive, Equation (3.1.44) reduces to RL = RS .
In the phasor method of analysis, the student should recall and appropriately apply the circuit-
analysis techniques learned in Chapter 2, which include nodal and mesh analyses, Thévenin and
Norton equivalents, source transformations, superposition, and wye–delta transformation.
Figure 3.1.3 Power triangle.

S = VRMS IRMS (VA)
Q = VRMS IRMS sin φ (VAR)
φ= tan−1 ( PQ )
P = VRMS IRMS cos φ (W)
ZS Figure 3.1.4 Illustration of maxi-

mum power transfer.
+ ZL = ZS*
VS ZL
(RL = RS and XL = −XS)
−
Source Load
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EXAMPLE 3.1.5
√
Consider an RLC series circuit excited by v (t) = 100 2 cos 10t V, with R = 20 -, L = 1
H, and C = 0.1 F. Use the phasor method to find the steady-state response current in the circuit.
Sketch the corresponding phasor diagram showing the circuit-element voltages and current. Also
draw the power triangle of the load.
Solution
The time-domain circuit and the corresponding frequency-domain circuit are shown in Figure
E3.1.5. The KVL equation is

¯ 1
V̄ = V̄R + V̄L + V̄C = I R + j ωL +
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
j ωC
Note that ω = 10 rad/s in our example, and rms values are chosen for the phasor magnitudes.
Thus,
100 0° 100 0°
100 0° = I¯ (20 + j 10 − j 1) or I¯ = = = 4.56 − 24.23° A
20 + j 9 21.93 24.23°
√
Then i(t) = Re 2 I¯ ej ωt , which is
√
i (t) = 2 (4.56) cos (10t − 24.23°) A.
The phasor diagram is shown in Figure E3.1.5(c).
R = 20 Ω L=1H R = 20 Ω jωL = j10 Ω
+ v − + vL − + − + −
+ R
i(t) + + VR VL
+ 1 1
v(t) = 100 2 cos ωt C = 0.1 F V = 100 0° V jωC = j = − j Ω
vC I VC
− −
− −
(a) (b)
VL = 45.6 ∠(90 − 24.23) = jXL I
(VL + VC)
VR + VL + VC = V = 100 ∠0 V
φ = 24.23
VC = 4.5 ∠−(90 + 24.23)
= jXC I
VR = 91.2 ∠−24.23 = IR
I
(c)
Figure E3.1.5 (a) Time-domain circuit. (b) Frequency-domain circuit. (c) Phasor diagram. (d) Power
triangle.
Copyright OUP
QC = −20.8 VAR
S = VRMS IRMS = 456 VA

QL = 207.9 VAR
P2 + Q2
QS = 187.1 VAR
φ = 24.23°
PR = 415.9 W = PS
(d)
Figure E3.1.5 Continued
Note that the power factor of the circuit is cos(24.23°) = 0.912 lagging, since the current is
lagging the voltage in this inductive load.
PR = VR2 rms /R = Irms
2
R = (4.56)2 20 = 415.9 W
A resistor absorbs real power.
QL = VL2 rms /XL = Irms
2
XL = (4.56)2 10 = 207.9 VAR
An inductor absorbs positive reactive power.
QC = VC2 rms /XC = Irms
2
XC = (4.56)2 (−1) = −20.8 VAR
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
A capacitor absorbs negative reactive power (or delivers positive reactive power).
The power triangle is shown in Figure E3.1.5(d). Note that PS (=PR) is delivered by the
source; and QS (= QL + QC) is delivered by the source. Note that QC is negative.
EXAMPLE 3.1.6
Draw the phasor diagrams for an RLC series circuit supplied by a sinusoidal voltage source with
a lagging power factor and a GLC parallel circuit supplied by a sinusoidal current source with a
leading power factor.
Solution
For the RLC series circuit in the frequency domain in Figure E3.1.6(a), the phasor diagram for
the case of a lagging power factor is shown in Figure E3.1.6(b).
For the GLC parallel circuit in the frequency domain in Figure E3.1.6(c), the phasor diagram
for the case of a leading power factor is shown in Figure E3.1.6(d).
R jXL = jωL Figure E3.1.6 (a) RLC series circuit in

frequency domain. (b) Phasor diagram
+ − + − for lagging power factor. (c) GLC paral-
+ VR VL + lel circuit in frequency domain. (d) Pha-
−j
V I VC
−
jXC = jω1C = ωC = j − ω1C ( ) sor diagram for leading power factor.
−
(a)
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VR + V L + V C = V
VL + VC = j(ωL − ω1C ) I
φ
I = I ∠0° (Reference)
VR = R I
(b)
+ IC
IR IL
I V GR = R1 jBL = j(− ω1L ) jBC = jωC
−
(c)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
IR + I L + I C = I IC + IL = j(ωC − ω1L ) V
φ
V = V ∠0° (Reference)
IR = V/R
(d)
EXAMPLE 3.1.7
Two single-phase 60-Hz sinusoidal-source generators (with negligible internal impedances) are
supplying to a common load of 10 kW at 0.8 power factor lagging. The impedance of the feeder
connecting the generator G1 to the load is 1.4 + j 1.6 -, whereas that of the feeder connecting
the generator G2 to the load is 0.8 + j 1.0 -. If the generator G1, operating at a terminal voltage
of 462 V (rms), supplies 5 kW at 0.8 power factor lagging, determine:
(a) The voltage at the load terminals;
(b) The terminal voltage of generator G2; and
(c) The real power and the reactive power output of the generator G2.
Solution
(a) From Equation (3.1.37) applied to G1, 462I1 (0.8) = 5 × 103 , or I1 = 13.53 A. With V̄1
taken as reference, the phasor expression for I¯1 is given by I¯1 = 13.53 − cos −1 0.8 =
13.53 − 36.9° A, since G1 supplies at 0.8 lagging power factor.
The KVL equation yields
V̄L = 462 0° − (13.53 − 36.9°) (1.4 + j 1.6) = 433.8 − 0.78° V
The magnitude of the voltage at the load terminals is 433.8 V (rms).
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I1 (1.4 + j1.6) Ω (0.8 + j1.0) Ω I2
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
+ + +
IL = I 1 + I2
P1 = 5 kW + + P2 = ?
PL = 10 kW
Q1 = 15 kVAR G1 V1 = 462∠0˚ V VL = ? Load V2 = ? G2
4 QL = 30 kVAR Q2 = ?
S1 = 25 kVA − 4 −
4 SL = 50 kVA
− − 4 −
Figure E3.1.7
(b) From Equation (3.1.37) applied to the load, 433.8IL (0.8) = 10 × 103 , or IL = 28.8 A.
As a phasor, with V̄1 as reference, I¯1 = 28.8 − (0.78° + 36.9°) = 28.8 − 37.68° A.
The KCL equation yields:
I¯2 = I¯L − I¯1 = 15.22 − 38.33°
The KVL equation yields

V̄2 = V̄L + (15.22 − 38.38°) (0.8 + j 1.0) = 4.52.75 − 0.22° V
The terminal voltage of G2 is thus 452.75 V (rms).

(c) The power triangle values for G1 and the load are shown in Figure E3.1.7 so that the
student can check it out.
P2 = V2 I2 cos φ2 = 452.75 × 15.22 × cos(38.38° − 0.22°)
= 5418 W, or 5.418 kW
(Note that φ2 is the angle between phasors V̄2 and I¯2 .)
Q2 = V2 I2 sin φ2 = 452.75 × 15.22 sin(38.38° − 0.22°)

= 4258 VAR, or 4.258 kVAR
The conservation of power (real and reactive) is satisfied as follows:

(13.53)2 1.4 (15.22)2 0.8 ∼
PL + loss in feeder resistances = 10 + + = 10.4 kW
1000 1000
which is the real power delivered by G1 and G2, which in turn is the same as P1 + P2 =
5 + 5.4 = 10.4 kW.
30 (13.53)2 1.6 (15.22)2 1.0 ∼
QL + (I 2 XL ) of feeders = + + = 8 kVAR
4 1000 1000
which is the same as the reactive power delivered by G1 and G2, which in turn is the
same as
15
Q1 + Q2 = + 4.26 ∼
= 8 kVAR
4
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EXAMPLE 3.1.8
(a) Find the Thévenin equivalent of the circuit shown in Figure E3.1.8(a) at the terminals
A–B.
(b) Determine the impedance that must be connected to the terminals A–B so that it is
matched.
(c) Evaluate the maximum power that can be transferred to the matched impedance at the
terminals A–B.
200 Ω Figure E3.1.8
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
I
+ −j10 Ω
10I
20∠0˚ V j20 Ω
− A
B
(a)
+ −
A
I 200 Ω −j10 Ω
+ −j100 I
20∠0° V j20 Ω
−
B
(b)
+ −
A
I 200 Ω −j10 Ω
+ −j100 I
20∠0° V j20 Ω Isc
I Isc
−
B
(c)
ZTh = 14.8∠36.6° Ω A
+
Voc =
11.94∠84.3° V
−
B
(d)
Solution
The circuit is redrawn with the controlled current source replaced by its equivalent controlled
voltage source, as shown in Figure E3.1.8(b).
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(a) Since the Thévenin impedance is the ratio of the open-circuit voltage to the short-circuit
current, calculation with respect to terminals A–B is shown next. Let us first calculate the
open-circuit voltage V̄oc .
The KVL equation for the left-hand loop is
20 0°
(200 + j 20)I¯ = 20 0°, or I¯ =
200 + j 20
Then,
(j 120) (20)
V̄oc = j 20 I − −j 100I¯ = j 120I¯ = = 1.19 + j 11.88
200 + j 20
= 11.94 84.3° V
The short-circuit current I¯sc is found from the circuit of Figure E3.1.8(c).
The KVL equations are given by
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(200 + j 20) I¯ − j 20I¯sc = 20 0°

− j 20I¯ + I¯sc (j 20 − j 10) = − −j 100I¯
Solving for I¯sc , one gets

240
I¯sc = 12I¯ = = 0.807 47.7° A
200 − j 220
The Thévenin impedance at terminals A–B is then

V̄oc 11.94 84.3°
Z̄Th = = = 14.8 36.6° - = 11.88 + j 8.82 -
I¯sc 0.807 47.7°
The Thévenin equivalent circuit at the A–B terminals is shown in Figure E3.1.8(d).
(b) The impedance to be connected at terminals A–B for matching is given by
∗
Z̄ = Z̄Th = 14.8 − 36.6° - = RTh − j XTh = 11.88 − j 8.82 -
(c) The maximum power transfer to the matched impedance Z̄ is given by

Voc 2 V2 11.942
Pmax = RTh = oc = = 3.0 W
2RTh 4RTh 4 × 11.88
EXAMPLE 3.1.9
A single-phase source delivers 100 kW to a load operating at 0.8 lagging power factor. In order
to improve the system’s efficiency, power factor improvement (correction) is achieved through
connecting a capacitor in parallel with the load. Calculate the reactive power to be delivered by
the capacitor (considered ideal) in order to raise the source power factor to 0.95 lagging, and draw
the power triangles. Also find the value of the capacitance, if the source voltage and frequency
are 100 V (rms) and 60 Hz, respectively. Assume the source voltage to be a constant and neglect
the source impedance as well as the line impedance between source and load.
Copyright OUP
Solution
Figure E3.1.9 (a) Circuit.

+ (b) Power triangles.
Inductive
V C
load
−
Source Capacitor added (in parallel)

for power factor correction (improvement)
(a)
SL = 100 2 + 752 = 125 kVA QC = −42.13

kVAR
= cosPφ QL = 75 kVAR = P tan φL
L φ L
6 . 8 7° =
=3
−1 0.8 QS = 32.87
cos kVAR
cos−10.95 = 18.19° = φS
P = PS = PR = 100 kW
(b)
The circuit and the power triangles are shown in Figure E3.1.9. The real power P = PS = PR
delivered by the source and absorbed by the load is not changed when the capacitor (considered
ideal) is connected in parallel with the load. After the capacitor is connected, noting that QC is
negative, QS = QL + QC = 100 tan(18.19) = 32.87 kVAR,
P 100
SS = = = 105.3 kVa
cos φS 0.95
(Note that the power factor correction reduces the current supplied by the generator signifi-
cantly.) So
QC = QS − QL = 32.87 − 75 = −43.13 kVAR
Thus the capacitor is delivering 43.13 kVAR to the system (or absorbing negative kVAR). Then
2
Vrms 1002 1
= = −43.13 × 103 or XC = −0.232 - = −
XC XC ωC
or
1
C= = 0.0114 F or 11.4 mF
2π × 60 × 0.232
Fourier Series
The phasor method of circuit analysis can be extended (by using the principle of superposition)
to find the response in linear systems due to nonsinusoidal, periodic source functions. A periodic
function (t) with period T can be expressed in Fourier series,
∞ ∞
f (t) = an cos nωt + bn sin nωt (3.1.45)
n=0 n=1
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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where ω = 2πf = 2π/T is the fundamental angular frequency, a0 is the average ordinate or the
dc component of the wave, (a1 cos ωt + b1 sin ωt) is the fundamental component, and (an cos nωt
+ bn sin nωt), for n ≥ 2, is the nth harmonic component of the function.
The Fourier coefficients are evaluated as follows:
T
1
a0 = f (t) dt (3.1.46)
T 0
T
2
an = f (t) cos nωt dt, n≥1 (3.1.47)
T 0
T
2
bn = f (t) sin nωt dt, n≥1 (3.1.48)
T 0
The exponential form of the Fourier series can be shown to be given by
∞

f (t) = C̄n ej nωt (3.1.49)
n=−∞
where
T
1
C̄n = f (t) e−j nωt dt (3.1.50)
T 0
Even though the exact representation of the nonsinusoidal, periodic wave requires an infinite
number of terms in the Fourier series, a good approximation for engineering purposes can be
obtained with comparatively few first terms, since the amplitude of the harmonics decreases
progressively as the order of the harmonic increases.
The system response is determined by the principle of superposition, and the phasor technique
yields the steady-state response. Each frequency component of the response is produced by
the corresponding harmonic of the excitation. The sum of these responses becomes the Fourier
series of the system response. Note that while the phasor method is employed to determine each
frequency component, the individual time functions must be used in forming the series for the
system response. Such a method of analysis is applicable to all linear systems.
EXAMPLE 3.1.10
(a) Find the Fourier series for the square wave shown in Figure E3.1.10(a).
(b) Let a voltage source having the waveform of part (a) with a peak value of 100 V and a
frequency of 10 Hz be applied to an RC series network with R = 20 - and C = 0.1 F.
Determine the first five nonzero terms of the Fourier series of vC(t).
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Solution
(a) From Equation (3.1.46),
Copyright OUP
v(t)
Vm
t
T T 3T
4 2 4
Period T = 2π = 1
ω f
(a)
i(t)
+ R = 20 Ω + + I 20 Ω +
v(t) C = 0.1 F vC (t) V 1 = 10 Ω VC
jωC jω
− − − −
(b) (c)
Figure E3.1.10 (a) Square wave. (b) Time-domain circuit. (c) Frequency-domain circuit.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
T T /4 T
1 1 Vm
a0 = f (t) dt = Vm dt + Vm dt =
T 0 T 0 3T /4 2
T /4 T
2
an = Vm cos nωt dt + Vm cos nωt dt
T 0 π/4
and



0, for even n
2Vm
an = ± , for odd n, where the algebraic sign is + for n = 1
 nπ

and changes alternately for each successive term.

T /4 T
2
bn = Vm sin nωt dt + Vm sin nωt dt = 0
T 0 3T /4
which can also be seen from symmetry of the square wave with respect to the chosen
origin.
The Fourier series is then
Vm 2Vm 2Vm 2Vm 2Vm
v (t) = + cos ωt − cos 3ωt + cos 5ωt − cos 7ωt + · · ·
2 π 3π 5π 7π
(b) The time-domain and frequency-domain circuits are shown in Figures E3.1.10(b) and
(c). Note that the capacitive impedance is expressed in terms of ω, since the frequency
of each term of the Fourier series is different. The general phasor expressions for I¯ and
V̄C are given by
Copyright OUP
V̄
I¯ =
20 + (10/j ω)

10 ¯ V̄
V̄C = I=
jω 1 + 2j ω
Treating each Fourier-series term separately, we have the following.
1. For the dc case, ω = 0; VC dc = 50 V.
2. For the fundamental component,
63.7
v1 (t) = 63.7 cos(20π t), V̄1 = √ 0°
2
√
(63.7/ 2) 0° 0.51
V̄C1 = = √ − 89.5° V
1 + j (40π ) 2
and
vC1 = 0.51 cos(20π t − 89.5°) V
3. For the third harmonic (ω = 3 × 20π ) component,

21.2
v3 (t) = −21.2 cos(60 π t), V̄3 = − √ 0°
2
√
−(21.2/ 2) 0° 0.06
V̄C3 = = − √ − 89.8° V
1 + j 2(60π ) 2
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
and
vC3 (t) = −0.06 cos(60π t − 89.8°) V
4. For the fifth harmonic (ω = 5 × 20π ) component,

12.73
v5 (t) = 12.73 cos(100π t), V̄5 = √ 0°
2
√
12.73/ 2 0° 0.02
V̄C5 = = √ − 89.9° V
1 + j 2(100π ) 2
and
vC5 (t) = 0.02 cos(100π t − 89.9°) V
5. For the seventh harmonic (ω = 7 × 20π ) component,

9.1
v7 (t) = −9.1 cos(140π t), V̄7 = − √ 0°
2
√
−(9.1/ 2) 0° 0.01
V̄C7 = = − √ − 89.9° V
1 + j 2(140π ) 2
and
vC7 (t) = −0.01 cos(140π t − 89.9°) V
Thus,
vC (t) = 50 + 0.51 cos(20π t − 89.5°) − 0.06 cos(60π t − 89.8°)
+ 0.02 cos(100π t − 89.9°) − 0.01 cos(140π t − 89.9°) V
in which the first five nonzero terms of the Fourier series are shown.
Copyright OUP
3.2 TRANSIENTS IN CIRCUITS 125
3.2 TRANSIENTS IN CIRCUITS

The total response of a system to an excitation that is suddenly applied or changed consists of
the sum of the steady-state and transient responses, or of natural and forced responses. The
forced response is the component of the system response that is due to the applied excitation.
The transition from the response prior to the change in excitation to the response produced by the
excitation is indicated by the natural (transient) response, which is characteristic of all systems
containing energy-storage components.
Let us consider the RL circuit excited by a voltage source v(t), as shown in Figure 3.2.1. The
KVL equation around the loop, for t > 0, is given by
L di (t)
+ Ri (t) = v (t) (3.2.1)
dt
Dividing both sides by L, we have
di (t) R v (t)
+ i (t) = (3.2.2)
dt L L
which is a first-order ordinary differential equation with constant coefficients. Note that the highest
derivative in Equation (3.2.2) is of first order, and the coefficients 1 and R/L are independent of
time t. Equation (3.2.2) is also linear since the unknown i(t) and any of its derivatives are not
raised to a power other than unity or do not appear as products of each other. Let us then consider
a general form of a linear, first-order ordinary differential equation with constant coefficients,
dx (t)
+ ax (t) = f (t) (3.2.3)
dt
in which a is a constant, x(t) is the unknown, and f (t) is the known forcing function. By rewriting
Equation (3.2.3) as
dx (t)
+ ax (t) = 0 + f (t) (3.2.4)
dt
and using the superposition property of linearity, one can think of
x(t) = xtr (t) + xss (t) (3.2.5)
where xtr (t) is the transient solution which satisfies the homogeneous differential equation with
f (t) = 0,
dxtr (t)
+ axtr (t) = 0 (3.2.6)
dt
and x ss(t) is the steady-state solution (or a particular solution) which satisfies the inhomogeneous
differential equation for a particular f (t),
dxss (t)
+ axss (t) = f (t) (3.2.7)
dt --`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
A possible form for x tr(t) in order to satisfy Equation (3.2.6) is the exponential function est. Note,
S R Figure 3.2.1 RL circuit excited by v(t).
+ t=0
v(t) i(t) L
− = iL(t)
Copyright OUP
however, that the function est used here in finding transient solutions is not the generalized phasor
function used earlier for exponential excitations. Thus let us try a solution of the form
xtr (t) = Aest (3.2.8)
in which A and s are constants yet to be determined. Substituting Equation (3.2.8) into Equation
(3.2.6), we get
sAest + aAest = 0 or (s + a)Aest = 0 (3.2.9)
which implies
s+a =0 or s = −a (3.2.10)
st
since A cannot be zero (or x tr would be zero for all t causing a trivial solution), and e cannot be
zero for all t regardless of s. Thus the transient solution is given by
xtr (t) = Ae−at (3.2.11)
in which A is a constant yet to be determined.
We already know how to find the steady-state solution x ss(t) for dc or ac sources, and the
principle of superposition can be used if we have more than one source. To find that part of
the steady-state solution due to a dc source, deactivate or zero all the other sources, and replace
inductors with short circuits, and capacitors with open circuits, and then solve the resulting circuit
for the voltage or current of interest. To find that part of the steady-state solution due to an ac
source, deactivate or zero all the other sources and use the phasor method of Section 3.1. The
solution to Equation (3.2.3) or Equation (3.2.4) is then given by Equation (3.2.5) as the sum of
the transient and steady-state solutions,
x(t) = xtr (t) + xss (t) = Ae−at + xss (t) (3.2.12)
In order to evaluate A, let us apply Equation (3.2.12) for t = 0+ which is immediately after t = 0,
x(0+ ) = A + xss (0+ ) or A = x(0+ ) − xss (0+ ) (3.2.13)
where x(0+ ) is the value of x(t) at the initial time and denotes the initial condition on x(t), and
xss (0+ ) would be found from x ss(t) corresponding to t = 0. Thus the total solution for x(t) for all
t ≥ 0 is given by
x (t) = [x(0+ ) − xss (0+ )]e−at + x (t) = [x(0+ )e−at ] −xss (0+ )e−at + xss (t) (3.2.14)
" #$ % " ss#$ % " #$ % " #$ %
(transient response) (steady-state response) (natural response) (forced response)
Note that the transient solution involving e−at eventually goes to zero as time progresses (assuming
a to be positive). At a time t = 1/a, the transient solution decays to 1/e, or 37% of its initial value
at t = 0+ . The reciprocal of a is known as the time constant with units of seconds,
τ = 1/a (3.2.15)
Thus Equation (3.2.14) can be rewritten as

x (t) = x 0+ − xss 0+ e−t/τ + xss (t) (3.2.16)

which is an important result as a solution of Equation (3.2.3). Then we can easily write the solution
of Equation (3.2.2) corresponding to the RL circuit of Figure 3.2.1, and that will involve i(0+ ),
which is the same as iL (0+ ), which is the value of the inductor current immediately after the
switch is closed.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
Since we know that the inductor current cannot change its value instantaneously, as otherwise
the inductor voltage vL (t) = L diL /dt would become infinite, it follows that the inductor current
immediately after closing the switch, iL (0+ ), must be the same as the inductor current just before
closing the switch, iL (0− ),
iL (0+ ) = iL (0− ) (3.2.17)
−
In Figure 3.2.1 note that iL (0 ) is zero. While the inductor current satisfies Equation (3.2.17), the
inductor voltage may change its value instantaneously, as we shall see in the following example.
EXAMPLE 3.2.1
Consider the RL circuit of Figure 3.2.1 with R = 2 -, L = 5 H, and v(t) = V = 20 V (a dc
voltage source). Find the expressions for the inductor current iL (t) and the inductor voltage vL (t)
for t > 0, and plot them.
Solution
It follows from Equation (3.2.16) that

i (t) = iL (t) = iL 0+ − iL,ss 0+ e−t/τ + iL,ss (t)

where the subscript ss denotes steady state, and τ = L/R.
In our case iL,ss = V /R = 20/2 = 10 A, and iL (0− ) = 0 = iL (0+ ). Thus we have
iL (t) = (0 − 10)e−2t/5 + 10 = 10(1 − e−2t/5 ) A, for t > 0
Then the inductor voltage is obtained as
diL
vL (t) = L = +20e−2t/5 , for t > 0
dt
iL (t) and vL (t) are plotted in Figure E3.2.1. The following points are worth noting.
1. iL (0− ) = iL (0+ ) = 0; the inductor current cannot change instantaneously.

2. vL (0− ) = 0 and vL (0+ ) = 20; the inductor voltage has changed instantaneously.
iL(t), A Figure E3.2.1 (a) Inductor current

iL (t) = 10(1 − e−2t/5 ) A, for t >
0. (b) Inductor voltage vL (t) =
10 20e−2t/5 V, for t > 0.
8.64 10(1 − e−2t/5)
8
10(1 − e−1) = 6.32 6
2 t = 2.5 2T
t, s
0 T = 2.5 5 10 15
(a)
--`,,,``,,`,```,``,`
Copyright OUP
vL(t), V Figure E3.2.1 Continued
20
20e−2t/5
20e−1 = 7.36
t, s
0 T = 2.5 5 10 15
(b)
3. After one time constant has elapsed, the inductor current has risen to 63% of its final or
steady-state value. After five time constants, it would reach 99% of its final value.
4. After one time constant, the inductor voltage has decayed to 37% of its initial value. The
inductor voltage, in this example, eventually decays to zero as it should, since in the steady
state the inductor behaves as a short circuit for dc sources.
The resistor voltage and resistor current, if needed, can be found as follows:

iR (t) = iL (t) = i (t) = 10 1 − e−2t/5 A, for t > 0

vR (t) = RiR (t) = 20 1 − e−2t/5 V, fort > 0
Note that the KVL equation v(t) = V = vR (t) + vL (t) = 20 is satisfied.
EXAMPLE 3.2.2
Consider the RC circuit of Figure E3.2.2(a) with R = 2 -, C = 5 F, and i(t) = I = 10 A (a
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
dc current source). Find the expressions for the capacitor voltage vC(t) and the capacitor current
iC(t) for t > 0, and plot them.
Solution
The KCL equation at the upper node for t > 0 is given by

dvC (t) vC (t) dvC (t) 1 i (t)
iC + iR = i (t) , or C + = i (t) or + vC (t) =
dt R dt RC C
This equation is the same in form as Equation (3.2.3). The total solution, which is of the form of
Equation (3.2.16), can be written as

vC (t) = vC 0+ − vC,ss 0+ e−t/(RC) + vC,ss (t)

where RC is the time constant T, which is 10 s in this case. vC,ss (t) = RI = 20 V in our case,
since the source is dc and the capacitor current iC = C (dvC /dt) = 0 in the steady state for t > 0,
denoting an open circuit. Then the solution is given by

vC (t) = vC 0+ − 20 e−t/10 + 20 V, for t > 0
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S Figure E3.2.2 (a) RC circuit excited by

i(t) = I . (b) Capacitor voltage vC (t) =
iR t=0 iC 20(1 − e−t/10 ) V, for t > 0. (c) Capacitor
+ current iC (t) = 10e−t/10 A, for t > 0.
i(t) I = 10 A R=2Ω vC(t) C=5F
−
(a)
vC (t), V
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
20.00
17.30 20(1 − e−t/10 )
15.00
12.64
10.00
5.00
T = 10 2T = 20
t, s
0 10 20
(b)
iC (t), A
10
5
3.68
10e−t/10
T = 10
t, s
0 10
(c)
Just as the inductor current cannot change instantaneously, the capacitor voltage cannot change
instantaneously,
vC (0+ ) = vC (0− )
which happens to be zero in our case, as otherwise the capacitor current iC = C (dvC /dt) would
become infinite. Thus we have

vC (t) = (0 − 20) e−t/10 + 20 = 20 1 − e−t/10 V, for t > 0
Then the capacitor current is obtained as
dvC
iC (t) = C = 10e−t/10 A, for t > 0
dt
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vC (t) and iC(t) are plotted in Figures E3.2.2(b) and (c). The following points are noteworthy.
1. vC (0+ ) = vC (0− ); the capacitor voltage cannot change instantaneously.

2. iC (0− ) = 0 and iC (0+ ) = 10 A; the capacitor current has changed instantaneously.
3. After one time constant has elapsed, the capacitor voltage has risen to 63% of its final
(steady-state) value. After five time constants, it would reach 99% of its final value.
4. After one time constant the capacitor current has decayed to 37% of its initial value. The
capacitor current, in this example, eventually decays to zero as it should, since in the
steady state the capacitor behaves as an open circuit for dc sources.
The resistor voltage and current, if desired, can be found as follows:

vR (t) = vC (t) = 20 1 − e−t/10 V, for t > 0

iR (t) = vR (t) /R = 10 1 − e−t/10 A, for t > 0
Note that the KCL equation i(t) = I = iC (t) + iR (t) = 10 is satisfied. The charge transferred to
the capacitor at steady-state is:
Qss = CVC,ss = 5 × 20 = 100 C
Examples 3.2.1 and 3.2.2 are chosen with zero initial conditions. Let us now consider nonzero
initial conditions for circuits still containing only one energy-storage element, L or C.
EXAMPLE 3.2.3
For the circuit of Figure E3.2.3(a), obtain the complete solution for the current iL (t) through the
5-H inductor and the voltage vx(t) across the 6-- resistor.
S Figure E3.2.3
t=0 + 4Ω
a iL(t)
vx(t) 6Ω
− +
5A 5Ω − 5H vL(t)
10 V −
+ b
(a)
S
a
4Ω
6Ω
Open 5Ω
Short RTh =
b 4 + 6 = 10 Ω
(b)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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S
a
4Ω
6Ω
iL, ss (t)
5A 5Ω − Short
= −10/10 = −1 A
10 V
+ b
(c)
S
t = 0− + a
4Ω
vx(o−) 6Ω iL(o−)
− Short = 50 A
5A 5Ω − 37
(by superposition)
10 V
+ b
(d)
Solution
The Thévenin resistance seen by the inductor for t > 0 is found by considering the circuit for
t > 0 while setting all ideal sources to zero, as shown in Figure E3.2.3(b).
The time constant of the inductor current is τ = L/RTh = 5/10 = 0.5 s. The steady-
state value of the inductor current for t > 0, iL,ss (t), is found by replacing the inductor by
a short circuit (since the sources are both dc) in the circuit for t > 0, as shown in Figure
E3.2.3(c).
The initial current at t = 0− , iL 0− , is found from the circuit for t < 0 as the steady-state
value of the inductor current for t < 0. Figure E3.2.3(d) is drawn for t < 0 by replacing the
inductor with a short circuit (since
both sources are dc).
One can solve for iL 0− by superposition to yield iL 0− = 50/37 A = iL 0+ , by
the continuity of inductor current. Then the solution for the inductor current for t > 0 can be
written as

iL (t) = iL 0+ − iL, ss 0+ e−RTh t/L + iL,ss (t) , for t > 0

In our example,

50 −2t 87 −2t
iL (t) = +1 e −1= e − 1 A, for t > 0
37 37
In the circuit for t = 0− [Figure E3.2.3(d)],
− notice that vx (0− ) has a nonzero value, which can be
evaluated by superposition as vx 0 = −220/37 V.
−2t
t > 0, vx (t) = −6iL (t) = −(522/37) e
For
+
+ 6. Note that vx, ss = 6 V, and
vx 0 = −522/37 + 6 = −300/37 V, which shows an instantaneous change in vx at t = 0.
EXAMPLE 3.2.4
Consider the circuit of Figure E3.2.4(a) and obtain the complete solution for the voltage vC(t)
across the 5-F capacitor and the voltage vx(t) across the 5-- resistor.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Figure E3.2.4
+ − a
1Ω iC (t)
10 V 4Ω
+
5Ω vx(t) +
− t=0 5F vC (t)
S −
b
(a)
Short a
1Ω
4Ω
5Ω
S RTh = 5 + 1 = 6 Ω
b
(b)
+ − a
1Ω
10 V 4Ω +
5Ω Open vC, ss (t) = −10 V
S −
b
(c)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
+ − a
1Ω
+ 10 V 4Ω +
− −
5Ω vx(o ) Open vC (o ) = −40/9 V
− S t = o− −
b
(d)
Solution
(Note that the procedure is similar to that of Example 3.2.3.) The Thévenin resistance seen by the
capacitor for t > 0 is found by considering the circuit for t > 0 while setting all ideal sources to
zero, as shown in Figure E3.2.4(b).
The time constant of the capacitor voltage is τ = RTh C = 6 × 5 = 30 s. The steady-state
value of the capacitor voltage for t > 0, vC, ss (t), is found by replacing the capacitor by an open
circuit (since the source is dc in the circuit for t > 0), as shown in Figure E3.2.4(c).
The initial capacitor voltage at t = 0− , vC(0− ), is found from the circuit for t < 0 as the
steady-state value of the capacitor voltage for t < 0. Figure E3.2.4(d) is drawn for t < 0 by
replacing the capacitor with an open circuit (since
the source is dc).
One can solve for vC (0− ) to yield vC 0− = −40/9 V = vC 0+ , by the continuity of the
capacitor voltage. Then the solution for the capacitor voltage for t > 0 can be written as

vC (t) = vC 0+ − vC, ss 0+ e−t/(RTh C) + vC, ss (t) , for t > 0
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In our example,

40 −t/30 50 −t/30
vC (t) = − + 10 e − 10 = e − 10 V, for t > 0
9 9
In the circuit of Figure E3.2.4(d) for t = 0− , notice that vx (0− ) = 50/9 V. For t > 0, vx(t)
= −5iC(t).
The capacitor current is found by

dvC (t) 50 1 25
iC (t) = C = (5) − · e−t/30 = − e−t/30 A
dt 9 30 27
−t/30

Then vx (t) = −5iC (t) = (125/27)e A, for t > 0. Note that vx 0+ = 125/27 V, and
vx, ss = 0. The resistor voltage has changed value instantaneously at t = 0.
One should recognize that, in the absence of an infinite current, the voltage across a capacitor
cannot change instantaneously: i.e., vC (0− ) = vC (0+ ). In the absence of an infinite voltage,
the current in a inductor cannot change instantaneously: i.e., iL (0− ) = iL (0+ ). Note that an
instantaneous change in inductor current or capacitor voltage must be accompanied by a change
of stored energy in zero time, requiring an infinite power source. Also observe that the voltages
across a resistor, vR (0− ) and vR (0+ ), are in general not equal to each other, unless the equality
condition is forced by iL (0− ) or vC (0− ). The voltage across a resistor can change instantaneously
in its value.
So far we have considered circuits with only one energy-storage element, which are known
as first-order circuits, characterized by first-order differential equations, regardless of how many
resistors the circuit may contain. Now let us take up series LC and parallel LC circuits, both
involving the two storage elements, as shown in Figures 3.2.2 and 3.2.3, which are known as
second-order circuits characterized by second-order differential equations.
Referring to Figure 3.2.2, the KVL equation around the loop is
vL (t) + vC (t) + RTh i (t) = vTh (t) (3.2.18)
a iL(t) = iC (t) RTh a

Ideal
+ +
sources L vL(t)
and L vTh(t) iL(t) = iC (t) = i(t) −
linear − +
resistors b C b C vC (t)
−
(t > 0) Thévenin equivalent
Figure 3.2.2 Series LC case with ideal sources and linear resistors.
Ideal a iL(t) iC (t) a iL(t) iC (t)

+
sources +
and L C iEQ(t) RTh v(t) = vL(t) = vC (t) L vL(t) vC (t)
linear C −
−
resistors b b
(t > 0) Norton equivalent
Figure 3.2.3 Parallel LC case with ideal sources and linear resistors.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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t
With iL (t) = iC (t) = i(t), vL (t) = L diL (t) /dt, and vC (t) = C1 −∞ iC (τ ) dτ , one obtains
the following equation in terms of the inductor current:

diL (t) 1 τ
L + iL (τ ) dτ + RTh iL (t) = vTh (t) (3.2.19)
dt C −∞
Differentiating Equation (3.2.19) and dividing both sides by L, one gets
d 2 iL (t) RTh diL (t) 1 1 dvTh (t)
2
+ + iL (t) = (3.2.20)
dt L dt LC L dt
Referring to Figure 3.2.3, the KCL equation at node a is
vC (t)
iL (t) + iC (t) + = iEQ (t) (3.2.21)
RTh
t
With vL (t) = vC (t) = v(t), iC (t) = C dvdtC (t) , and iL (t) = L1 −∞ vC (τ ) dτ , one obtains the
following equation in terms of the capacitor voltage

dvC (t) 1 t vC (t)
C + vC (τ ) dτ + = iEQ (t) (3.2.22)
dt L −∞ RTh
Differentiating Equation (3.2.22) and dividing both sides by C, one gets
d 2 vC (t) 1 dvC (t) 1 1 diEQ (t)
2
+ + vC (t) = (3.2.23)
dt CRTh dt LC C dt
Equations (3.2.20) and (3.2.23) can be identified to be second-order, constant-coefficient,
linear ordinary differential equations of the form
d 2 x (t) dx (t)
2
+a + bx (t) = f (t) (3.2.24)
dt dt
Note for the series LC case,
RTh 1
a= and b= (3.2.25)
L LC
and for the parallel LC case,
1 1
a= and b= (3.2.26)
RTh C LC
Because of the linearity of Equation (3.2.24), the solution will consist of the sum of a transient
solution x tr(t) and a steady-state solution x ss(t),
x(t) = xtr (t) + xss (t) (3.2.27)
where x tr(t) satisfies the homogeneous differential equation with f (t) = 0,
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
d 2 xtr (t) dxtr (t)

+a + bxtr (t) = 0 (3.2.28)
dt 2 dt
and x ss(t) satisfies the following for a particular f (t),
d 2 xss (t) dxss (t)
2
+a + bxss (t) = f (t) (3.2.29)
dt dt
For obtaining the steady-state solution due to a dc source, recall replacing inductors with
short circuits and capacitors with open circuits. For the steady-state solution due to a sinusoidal
source, simple methods have been developed in Section 3.1.
Now for the transient solution, a possible form for x tr(t) in order to satisfy Equation (3.2.28)
is the exponential function est. Thus let us try a solution of the form
Copyright OUP
xtr (t) = Aest (3.2.30)

Substituting Equation (3.2.30) in Equation (3.2.28), one gets
2
s 2 Aest + asAest + bAest = 0 or s + as + b Aest = 0 (3.2.31)
which can be true only if
s 2 + as + b = 0 (3.2.32)
Equation (3.2.32) is known as the characteristic equation of the differential equation. The two
roots s1 and s2 of Equation (3.2.32) are given by
&
a 1 2 a 4b
s1 , s2 = − ± a − 4b = − 1± 1− 2 (3.2.33)
2 2 2 a
Three possibilities arise:

4b
Case 1: The two roots will be real and unequal (distinct), if < 1.
a2
4b
Case 2: The two roots will be real and equal, if = 1.
a2
4b
Case 3: The two roots will be complex conjugates of each other, if > 1.
a2
Let us now investigate these cases in more detail.
Case 1: Roots Real and Unequal (Distinct)

For 4b/a 2 < 1, from Equation (3.2.33) it is clear that both roots will be negative if a is
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
positive. For realistic circuits with positive values of RTh, L, and C, a will be positive, and
hence both roots will be negative. With s1 = −α1 and s2 = −α2 (where α 1 and α 2 are
positive numbers), the transient (natural) solution will be of the form
xtr (t) = A1 e−α1 t + A2 e−α2 t (3.2.34)
where A1 and A2 are constants to be determined later. Note that Equation (3.2.34) contains
the sum of two decaying exponentials.
Case 2: Roots Real and Equal

For 4b = a2, the roots will be equal and negative, as one can see from Equation (3.2.33).
With s1 = s2 = −a/2 = −α (where α is positive), let us look at the nature of the
transient solution. For the case of real, repeated roots, not only x tr(t) = A1 e−αt satisfies the
differential equation, Equation (3.2.28), but also xtr (t) = A2 te−αt can be seen to satisfy
Equation (3.2.28). By superposition, the form of the transient solution will be seen to be
xtr (t) = A1 e−αt + A2 te−αt = (A1 + A2 t) e−αt (3.2.35)
which contains two constants (to be determined later), as it should for the solution of a
second-order differential equation.
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Case 3: Complex Conjugate Roots

For 4b/a 2 > 1, as seen from Equation (3.2.33), the roots will be complex conjugates of
each other. With s1 = −α + jβ and s2 = −α − jβ (where α and β are positive numbers),
the transient solution will be of the form

xtr (t) = A1 e(−α+jβ)t + A2 e(−α−jβ)t = e−αt A1 ejβt + A2 e−jβt (3.2.36)
in which A1 and A2 will turn out to be complex conjugates of each other, since the transient
solution must be real. An alternative, and more convenient, form of Equation (3.2.36) is
given by
xtr (t) = e−αt (C1 cos βt + C2 sin βt) (3.2.37)
in which C1 and C2 are real constants to be determined later. Another alternative form of
Equation (3.2.37) can be shown to be
xtr (t) = Ce−αt sin (βt + φ) (3.2.38)
Note that in all three cases [see Equations (3.2.34), (3.2.35), and (3.2.38)] with nonzero α‘s
the transient solution will eventually decay to zero as time progresses. The transient solution is
said to be overdamped, critically damped, and underdamped, corresponding to Cases 1, 2, and
3, respectively. Justification of the statement can be found from the solution of the following
example.
EXAMPLE 3.2.5
Consider the circuit of Figure 3.2.2 for t > 0 with zero initial conditions, vTh(t) = 1 V (dc), and
RTh = 2 -; L = 1 H. Determine the complete response for vC(t) for capacitance values of:
(a) (25/9) F
(b) 1.0 F
(c) 0.5 F
Solution
The KVL equation around the loop is given by

di (t) 1 t
2i (t) + 1 + i (τ ) dτ = 1.0
dt C −∞
Since
t
1 dvC (t)
vC (t) = i (τ ) dτ and i (t) = iC (t) = C
C −∞ dt
the differential equation in terms of vC(t) is obtained as
dvC (t) d 2 vC (t)
2C +C + vC (t) = 1.0
dt dt 2
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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The steady-state response vC, ss (t) due to a dc source is determined by replacing inductors with
short circuits and capacitors with open circuits,
vC, ss (t) = V0 = 1.0 V
[Note that vC, ss(t) is of the form of the excitation and is a constant V 0; substitution of V 0 for
vC, ss(t) gives 0 + 0 + V0 = 1.0.]
The transient response is obtained from the force-free (homogeneous) equation, which is
dvC, tr d 2 vC, tr (t)
2C +C + vC, tr (t) = 0
dt dt 2
Assuming vC, tr(t) to be of the form Aest, the values of s are determined from

Aest 2Cs + Cs 2 + 1 = 0 or Cs 2 + 2Cs + 1 = 0

and the roots are
&
−2C ± (2C)2 − 4C 1
s1 , s2 = = −1 1 ± 1 −
2C C
(a) For C = 25/9 F, the values of s1 and s2 are
s1 = −0.2 and s2 = −1.8
The transient response is given by (see Case 1 with real and unequal roots)
vC, tr (t) = A1 e−0.2t + A1 e−1.8t V
and the total (complete) response is
vC (t) = vC, ss (t) + vC, tr (t) or vC (t) = 1.0 + A1 e−0.2t + A2 e−1.8t V
where A1 and A2 are to be evaluated from the initial conditions,
vC (0− ) = 0, iL (0− ) = i(0− ) = 0
By the continuity
+ principle, vC (0+ ) = 0 and iL (0+ ) = 0. Also, iL (0+ ) = iC (0+ ) and
dvC /dt 0 = iC (0+ )/C = 0. Expressing dvC (t)/dt as dvC (t)/dt = −0.2A1 e−0.2t −
1.8A2 e−1.8t , evaluating dvC (0+ )/dt and vC (0+ ) yields
vC (0+ ) = 0 = 1 + A1 + A2
dvC +
0 = 0 = −0.2A1 − 1.8A2
dt
Simultaneous solution yields A1 = −1.125 and A2 = 0.125. Hence the complete
solution is
vC (t) = 1.0 − 1.125e−0.2t + 0.125e−1.8t V
(b) For C = 1.0 F, the values of s1 and s2 are both equal; s1 = s2 = −1. Corresponding to
Case 2 with real and equal roots, the transient response is given by Equation (3.2.35),
vC, n (t) = (A1 + A2 t) e−αt = (A1 + A2 t) e−t
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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The complete response is vC (t) = 1.0 + (A1 + A2 t) e−t . Evaluating both vC and dvC/dt
at t = 0+ , we have
vC (0+ ) = 0 = 1 + A1
dvC +
(0 ) = 0 = A2 − A1
dt
These equations result in A1 = A2 = −1, from which it follows that
vC (t) = 1 − e−t − te−t = 1 − (t + 1)e−t V
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(c) For C = 0.5 F, the values of s1 and s2 are obtained as s1 = (−1 + j 1) and s2 = (−1 − j 1)
(see Case 3 with complex conjugate roots). The transient response is of the form of
Equation (3.2.38),
vC, n (t) = Ae−αt sin (βt + φ)
where α = 1 and β = 1 in our case. The complete solution is then vC (t) = 1.0 +
Ae−t sin(βt + φ) V. From the initial conditions vC (0+ ) = 0 and dvC /dt 0+ = 0,
evaluating both at t = 0+ yields
vC (0+ ) = 0 = 1 + A sin φ
dvC +
0 = 0 = A(cos φ − sin φ)
dt
√
Simultaneous solution yields A = − 2 and φ = π/4. Thus the complete response is
given by
√ π
vC (t) = 1.0 − 2 e−t sin t + V
4
The total responses obtained for the three cases are plotted in Figure E3.2.5. These cases are
said to be overdamped for case (a), critically damped for case (b), and underdamped for case (c).
Figure E3.2.5 Total responses

1 −√2e−t sin t + π
1.2
Under damped (c) ( 4 ) obtained.
1.0
Capacitor voltage, V
0.8 1 −e−t (t + 1)
(b)
critically
0.6
damped
0.4 (a) overdamped
1 −1.125e−0.2t + 0.125e−1.8t
0.2
0
0 1 2 3 4 5 6 7 8 9 10
Time, s
A system that is overdamped [Figure E3.2.5(a)] responds slowly to any change in excitation.
The critically damped system [Figure E3.2.5(b)] responds smoothly in the speediest fashion
to approach the steady-state value. The underdamped system [Figure E3.2.5(c)] responds most
quickly accompanied by overshoot, which makes the response exceed and oscillate about the
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steady-state value while it gradually approaches the steady-state value. Practical systems are
generally designed to yield slightly underdamped response, restricting the overshoot to be less
than 10%.
Let us next consider circuits with two energy-storage elements (L and C) and nonzero initial
conditions.
EXAMPLE 3.2.6
Determine iL (t) and vC (t) for t > 0 in the circuit given in Figure E3.2.6(a).
S Figure E3.2.6
iL(t)
2Ω t=0
+ 4Ω
10 V + 1H
−
4V 1 +
F vC (t)
− 3
−
(a)
iL
2Ω Short 4Ω
+ 4Ω
+ 1H
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
10 V + +
− 4V 1 +
4V Open F vC
− − 3
− −
(c)
(b)
Solution
From the circuit for t = 0− drawn in Figure E3.2.6(b), we have

− +
− 10 − 4
iL (0 ) = 0 = iL (0 ) and vC 0 = × 4 + 4 = 8 V = vC 0 +
6
From the circuit for t > 0 drawn in Figure E3.2.6(c), we have iL, ss = 0; vC, ss = 4 V. With
R = 4 -, L = 1 H, and C = 1/3 F, s 2 + RL s + LC 1
= s 2 + 4s + 3 = 0. With s1 = −1 and
s2 = −3, iL, tr (t) = A1 e−t + A2 e−3t ; vC, tr (t) = B1 e−t + B2 e−3t . The complete solutions are
given by
iL (t) = A1 e−t + A2 e−3t and vC (t) = 4 + B1 e−t + B2 e−3t
Since
diL +
vL 0 + = L 0 = −A1 − 3A2 = 4 − 4iL 0+ − vC 0+ = 4 − 8 = −4
dt
+ dvC + 1
iC 0 = C 0 = (−B1 − 3B2 ) = iL 0+ = 0
dt 3
it follows that A1 + 3A2 = 4 and B1 + 3B2 = 0.
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From iL (0+ ) = 0 and vC (0+ ) = 8 V, it follows that A1 + A2 = 0 and B1 + B2 + 4 = 8.

Simultaneous solution yields A1 = −2, A2 = 2, B1 = 6, and B2 = −2. Thus we have, for t > 0,

iL (t) = −2e−t + 2e−3t A; vC (t) = 4 + 6e−t − 2e−3t V
In order to represent the abrupt changes in excitation, encountered when a switch is opened
or closed and in individual sequences of pulses, singularity functions are introduced. This type of
representation leads to the step and impulse functions. The methods for evaluating the transient
(natural) and steady-state (forced) components of the response can also be applied to these
excitations.
The unit-step function, represented by u(t), and defined by
'
0, t <0
u (t) = (3.2.39)
1, t >0
is shown in Figure 3.2.4. The physical significance of the unit step can be associated with the
turning on of something (which was previously zero) at t = 0. In general, a source that is applied
at t = 0 is represented by
v(t) or i(t) = f (t)u(t) (3.2.40)
A delayed unit step u(t − T ), shown in Figure 3.2.5, is defined by
'
1, t >T
u (t − T ) = (3.2.41)
0, t <T
A widely used excitation in communication, control, and computer systems is the rectangular
pulse, whose waveform is shown in Figure 3.2.6 and whose mathematical expression is given by
(
0, −∞ < t < 0
f (t) = A, 0<t <T (3.2.42)
0, T <t <∞
Equation (3.2.42) can be expressed as the sum of two step functions,
f (t) = Au(t) − Au(t − T ) (3.2.43)
f (t) Figure 3.2.4 Unit-step function.
t
0
f (t) Figure 3.2.5 Delayed unit-step function.
t
T
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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f (t) Figure 3.2.6 Rectangular pulse.
t
0 T
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
The student is encouraged to justify this statement by drawing graphically. For determining the
response of a circuit to a pulse excitation, using the principle of superposition, the response to each
component can be found and the circuit response obtained by summing the component responses.
The decomposition of pulse-type waveforms into a number of step functions is commonly used.
In order to represent the effects of pulses of short duration and the responses they produce,
the concept of unit-impulse function δ(t) is introduced,
∞ 0+
δ(t) = 0 for t = 0, and δ (t) dt = δ (t) dt = 1 (3.2.44)
−∞ 0−
Equation (3.2.44) indicates that the function is zero everywhere except at t = 0, and the area
enclosed is unity. In order to satisfy this, δ(t) becomes infinite at t = 0. The graphical illustration
of a unit-impulse function is shown in Figure 3.2.7. The interpretation of i(t) = Aδ (t − T ) is
that δ (t − T ) is zero everywhere except at t = T (i.e., the current impulse occurs at t = T ), and
the area under i(t) is A.
f (t) u (t)
1 As ∆ → 0 1
t t
0 0
−1∆ 1
2 2∆
(a) (b)
d f (t) δ (t) = du(t)

dt dt
1
∆ As ∆ → 0
t t
0 0
−1∆ 1
2 2∆
(c) (d)
Figure 3.2.7 Graphic illustration of unit-impulse function. (a) A modified unit-step function in which the
transition from zero to unity is linear over a ?-second time interval. (b) Unit-step function: the graph of
part (a) as ? → 0. (c) The derivative of the modified unit-step function depicted in part (a) (area enclosed
∞ 0+
= 1). (d) Unit-impulse function: the graph of part (c) as ? → 0 [ −∞ δ(t)dt = 0− δ(t)dt = 1]
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The form of the natural response due to an impulse can be found by the methods presented
in this section. As for the initial capacitor voltages and inductor currents, notice that a current
impulse applied to a capacitance provides an initial voltage of
q
vC 0 + = (3.2.45)
C
where q is the area under the current impulse. Similarly, a voltage impulse applied to an inductance
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
provides an initial current of
λ
iL 0+ = (3.2.46)
L
where λ is the area under the voltage impulse. The impulse function allows the characterization
of networks in terms of the system’s natural response, which is dependent only on the network
elements and their interconnections. Once the impulse response is known, the system response
to nearly all excitation functions can be determined by techniques that are available, but not
disclosed here in view of the scope of this text.
3.3 LAPLACE TRANSFORM

Many commonly encountered excitations can be represented by exponential functions. The
differential equations describing the networks are transformed into algebraic equations with
the use of exponentials. So far, methods have been developed to determine the forced re-
sponse and the transient response in Sections 3.1 and 3.2. The operational calculus was de-
veloped by Oliver Heaviside (1850–1925) based on a collection of intuitive rules; the trans-
formation is, however, named after Pierre Simon Laplace (1749–1827) because a complete
mathematical development of Heaviside’s methods has been found in the 1780 writings of
Laplace. The Laplace transformation provides a systematic algebraic approach for determining
the total network response, including the effect of initial conditions. The differential equa-
tions in the time domain are transformed into algebraic equations in the frequency domain.
Frequency-domain quantities are manipulated to obtain the frequency-domain equivalent of the
desired result. Then, by taking the inverse transform, the desired result in the time domain
is obtained.
The single-sided Laplace transform of a function f (t) is defined by
∞
L [f (t)] = F (s) = f (t) e−st dt (3.3.1)
0
where f (t) = 0 for t < 0, and s is a complex-frequency variable given by s = σ + j ω. The
frequency-domain function F(s) is the Laplace transform of the time-domain function f (t). When
the integral of Equation (3.3.1) is less than infinity and converges, f (t) is Laplace transformable.
Note that for σ > 0, e−st decreases rapidly, making the integral converge. The uniqueness of the
Laplace transform leads to the concept of the transform pairs,
L [f (t)] = F (s) ⇔ L −1 [F (s)] = f (t) (3.3.2)
which states that the inverse Laplace transform of F(s) is f (t). It should be noted that the Laplace
transform is a linear operation such that
L [Af1 (t) + Bf2 (t)] = AF1 (s) + BF2 (s) (3.3.3)
in which A and B are independent of s and t, and F1(s) and F2(s) are the Laplace transforms of f1 (t)
and f2 (t), respectively. Using the definition of Equation (3.3.1), Table 3.3.1 of Laplace transform
pairs is developed for the most commonly encountered functions. Note that it is assumed that
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3.3 LAPLACE TRANSFORM 143
f (t) = 0 for t < 0 and all f (t) exist for t ≥ 0. Also note that in Table 3.3.1, functions 8 through
20 can be considered as being multiplied by u(t).
From Table 3.3.1 of Laplace transform pairs one can see that

df (t)
L = sF (s) − f 0+ (3.3.4)
dt
By recalling that vL = L diL /dt and iC = C dvC /dt and the principle of continuity of the inductor
current and the capacitor voltage, the significance of the term f (0+ ) in Equation (3.3.4) is that the
initial condition is automatically included in the Laplace transform of the derivative, and hence
TABLE 3.3.1 Laplace Transform Pairs
f(t) in time domain = L -1[F(s)] ⇔ F(s) in frequency domain = L f[(t)]
df (t)
(1) sF (s) − f (0+ )
dt
d 2 f (t) df +
(2) s 2 F (s) − sf (0+ ) − (0 )
dt 2 dt
d n f (t) df + d n−1 f
(3) s n F (s) − s n−1 f (0+ ) − s n−2 (0 ) − · · · n−1 (0+ )
dt n dt dt
t
F (s) g(0+ )
(4) g(t) = f (t) dt +
0 s s
t
(5) f (τ )g(t − τ ) dτ F (s)G(s)
0
1
(6) u(t), unit-step function
s
(7) δ(t), unit-impulse function 1
1
(8) t
s2
t n−1 1
(9) , n integer
(n − 1)! sn
1
(10) ε −at
s+a
1
(11) tε −at
(s + a)2
(n − 1)!
(12) t n−1 ε −at
(s + a)n
ω
(13) sin ωt
s 2 + ω2
s
(14) cos ωt
s 2 + ω2
s sin θ + ω cos θ
(15) sin(ωt + θ )
s 2 + ω2
s cos θ − ω sin θ
(16) cos(ωt + θ )
s 2 + ω2
ω
(17) ε −at sin ωt
(s + a)2 + ω2
s+a
(18) ε −at cos ωt
(s + a)2 + ω2
2ω(s + a)
(19) tε −at sin ωt
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
[(s + a)2 + ω2 ]2
(s + a)2 − ω2
(20) tε −at cos ωt
[(s + a)2 + ω2 ]2
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becomes an inherent part of the final total solution. For cases with zero initial condition, it can be
seen that multiplication by s in the frequency domain corresponds to differentiation in the time
domain, and dividing by s in the frequency domain corresponds to integration in the time domain.
Some other properties of the Laplace transform are listed in Table 3.3.2.
From the entries of Table 3.3.2, observe the time–frequency dualism regarding frequency
differentiation, frequency integration, and frequency shifting. The initial-value and final-value
theorems also display the dualism of the time and frequency domains. As seen later, these theorems
will be effectively applied in the network solutions.
In order to use the tabulated transform pairs of Table 3.3.1, algebraic manipulations will
become necessary to make F(s) correspond to one of the tabulated entries. While the process may
be simple in some cases, in other cases F(s) may have to be rearranged in a systematic way as
a sum of component functions whose inverse transforms are tabulated. A formalized approach
to resolve F(s) into a summation of simple factors is known as the method of partial-fraction
expansion (Heaviside expansion theorem).
Let us consider a rational function (i.e., one that can be expressed as a ratio of two
polynomials),
N (s)
F (s) = (3.3.5)
D (s)
where N(s) denotes the numerator polynomial and D(s) denotes the denominator polynomial. As
a first step in the expansion of the quotient N (s)/D(s), we check to see that the degree of the
polynomial N is less than that of D. If this condition is not satisfied, divide the numerator by the
denominator to obtain an expansion in the form
N (s) N1 (s)
= B0 + B1 s + B2 s 2 + · · · + Bm−n s m−n + (3.3.6)
D (s) D (s)
where m is the degree of the numerator and n is the degree of the denominator.
TABLE 3.3.2 Some Properties of the Laplace Transform
Property Time Domain Frequency Domain
Linearity af (t) ± bg (t) aF (s) ± bG (s)

Time delay of shift f (t − T )u(t − T ) e−sT F (s)
F (s)
Periodic function f (t) = f (t + nT ) f (t), 0≤t ≤T where
1 − e−T s
T
F (s) = 0 f (t) e−st dt
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
1 s
Time scaling f (at) F
a a
dF (s)
Frequency differentiation tf (t) −
ds
(multiplication by t)
∞
f (t)
Frequency integration F (s) ds
(division by t) t s
Frequency shifting f (t)e−at F (s + a)

(exponential translation)
Initial-value theorem lim f (t) = f (0+ ) lim sF (s)
t→0 s→∞
Final-value theorem lim f (t) = f (∞) where limit exists lim sF (s)
t→∞ s→0
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The roots of the equation

N (s) = 0 (3.3.7)
are said to be the zeros of F(s); and the roots of the equation
D(s) = 0 (3.3.8)
are said to be the poles of F(s).
The new function F1(s) given by N 1(s)/D(s) is such that the degree of the denominator
polynomial is greater than that of the numerator. The denominator polynomial D(s) is typically
of the form
D (s) = an s n + an−1 s n−1 + · · · + a1 s + a0 (3.3.9)
By dividing the numerator N 1(s) and the denominator D(s) by an, F1(s) may be rewritten as
follows:
N2 (s) N2 (s)
F1 (s) = = a a0 (3.3.10)
n−1
D1 (s) sn + s n−1 + · · · +
an an
The particular manner of evaluating the coefficients of the expansion is dependent upon the nature
of the roots of D1(s) in Equation (3.3.10). We shall now discuss different cases of interest. The
possible forms of the roots are (1) real and simple (or distinct) roots, (2) conjugate complex roots,
and (3) multiple roots.
Real and Simple (or Distinct) Poles

If all the poles of F1(s) are of first order, Equation (3.3.10) may be written in terms of a partial-
fraction expansion as
N2 (s)
F1 (s) = (3.3.11)
(s − p1 ) (s − p2 ) · · · (s − pn )
or
K1 K2 Kn
F1 (s) = + + ··· + (3.3.12)
s − p1 s − p2 s − pn
where p1, p2, . . . , pn are distinct, and K 1, K 2, . . . , Kn are nonzero finite constants. For any k, the
evaluation of the residue Kk of F1(s) corresponding to the pole s = pk is done by multiplying
both sides by (s − pk ) and letting s → pk ,
Kk = lim [(s − pk ) F1 (s)] (3.3.13)
s→pk
Equation (3.3.13) is valid for k = 1, 2, . . . , n. Once the K’s are determined in Equation (3.3.12),
the inverse Laplace transform of each of the terms can be written easily in order to obtain the
complete time solution.
Conjugate Complex Poles

It is possible that some of the poles of Equation (3.3.10) are complex. Since the coefficients ak
in Equation (3.3.9) are real, complex poles occur in complex conjugate pairs and will always be
even in number. Let us consider a pair of complex poles for which case Equation (3.3.10) may be
written as
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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N2 (s)
F1 (s) = (3.3.14)
(s + a + j b) (s + a − j b) D2 (s)
or
K1 K2 N3 (s)
F1 (s) = + + (3.3.15)
s + (a + j b) s + (a − j b) D2 (s)
The procedure for finding K 1 and K 2 is the same as outlined earlier for unrepeated linear factors
or simple poles. Thus we have
K1 = lim [(s + a + j b) F1 (s)] (3.3.16)
s→(−a−j b)
and
K2 = lim [(s + a − j b) F1 (s)] (3.3.17)
s→(−a+j b)
It can be shown that K 1 and K 2 are conjugates of each other. The terms in the time function,
L −1 [F(s)], due to the complex poles of F1(s), are then found easily.
Alternate Representation for Complex Poles

Complex poles can be combined to yield a quadratic term in the partial fraction expansion. The
representation may best be illustrated by considering one real pole and two complex conjugate
poles. Let us then consider
N2 (s)
F1 (s) =
(s − p1 ) (s + a + j b) (s + a − j b)
N2 (s)
=
(s − p1 ) (s + a)2 + b2
N2 (s)
= (3.3.18)
(s − p1 ) s 2 + As + B
which can be rewritten as
K1 K2 s + K3
F1 (s) = + 2 (3.3.19)
s − p1 s + As + B
Evaluating K 1 as before, one has
K1 = lim [(s − p1 ) F1 (s)] (3.3.20)

s→p1
It follows from Equations (3.3.18) and (3.3.19) that

N2 (s) = K1 s 2 + As + B + (K2 s + K3 ) (s − p1 ) (3.3.21)
Since Equation (3.3.21) must hold for all values of s, the coefficients of various powers of s on
both sides of the equality must be equal. These equations of equality are then solved to determine
K 2 and K 3.
Even if many pairs of complex conjugate poles occur, this procedure may be used, re-
membering that the partial fraction for each complex conjugate pair will be of the form
discussed.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Multiple Poles
Let us consider that F1(s) has all simple poles except, say, at s = p1 which has a multiplicity m.
Then one can write
N2 (s)
F1 (s) = (3.3.22)
(s − p1 )m (s − p2 ) · · · (s − pn )
The partial fraction expansion of F1(s) is given by
K11 K12 K1m
F1 (s) = m + + ··· +
(s − p1 ) (s − p1 )m−1 (s − p1 )
K2 Kn
+ + ··· + (3.3.23)
(s − p2 ) (s − pn )
When a multiple root is involved, there will be as many coefficients associated with the multiple
root as the order of multiplicity. For each simple pole pk we have just one coefficient Kk,
as before.
For simple poles one can proceed as discussed earlier and apply Equation (3.3.13) to calculate
the residues Kk. To evaluate K 11, K 12, . . . , K 1m we multiply both sides of Equation (3.3.23) by
(s − p1 )m to obtain
(s − p1 )m F1 (s) = K11 + (s − p1 ) K12 + · · ·
+ (s − p1 )m−1 K1m + (s − p1 )m

K2 Kn
× + ··· + (3.3.24)
s − p2 s − pn
The coefficient K 11 may now be evaluated as

K11 = lim (s − p1 )m F1 (s) (3.3.25)

s→p1
Next we differentiate Equation (3.3.24) with respect to s and let s → p1 in order to evaluate K 12,
' )
d
K12 = lim (s − p1 ) F1 (s)

m
(3.3.26)
s→p1 ds
The differentiation process can be continued to find the kth coefficient:
' )
1 d k−1
K1k = lim (s − p 1 )m
F 1 (s) , for k = 1, 2, · · · , m (3.3.27)
s→p1 (k − 1) ! ds k−1
Note that K 2, . . . , Kn terms play no role in determining the coefficients K 11, K 12, . . . , K 1m because
of the multiplying factor (s − p1 )m in Equation (3.3.24).
The alternate representation discussed for the case of complex poles may also be extended
for multiple poles by combining the terms in Equation (3.3.23) corresponding to the multiple root.
In an expansion of a quotient of polynomials by partial fractions, it may, in general, be necessary
to use a combination of the rules given.
The denominator of F1(s) may not be known in the factored form in some cases, and it will
then become necessary to find the roots of the denominator polynomial. If the order is higher
than a quadratic and simple inspection (or some engineering approximation) does not help, one
may have to take recourse to the computer. Computer programs for finding roots of a polynomial
equation (using such methods as Newton–Raphson) are available these days in most computer
libraries.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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With the aid of theorems concerning Laplace transforms and the table of transforms, lin-
ear differential equations can be solved by the Laplace transform method. Transformations of
the terms of the differential equation yields an algebraic equation in terms of the variable s.
Thereafter, the solution of the differential equation is affected by simple algebraic manipulations
in the s-domain. By inverting the transform of the solution from the s-domain, one can get
back to the time domain. The response due to each term in the partial-fraction expansion is
determined directly from the transform table. There is no need to perform any kind of inte-
gration. Because initial conditions are automatically incorporated into the Laplace transforms
and the constants arising from the initial conditions are automatically evaluated, the resulting
response expression yields directly the total solution. The flow diagram is illustrated in Fig-
ure 3.3.1.
Eliminating the need to write the circuit differential equations explicitly, transformed net-
works, which are networks converted directly from the time domain to the frequency domain,
are used. For the three elements R, L, and C, the transformed network equivalents, using Ta-
ble 3.3.1, are based on the Laplace transforms of their respective volt-ampere characteristics,
as follows:
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
L [v (t) = Ri (t)] → V (s) = RI (s) (3.3.28)

di (t)
L v (t) = L → V (s) = sLI (s) − Li 0+ (3.3.29)
dt

1 t 1 v 0+
L v (t) = i (t) dt → V (s) = I (s) + (3.3.30)
C −∞ Cs s
0
Note that −∞ i (t) dt = q 0− and q 0− /C = v 0− = v(0+ ) because of continuity of
capacitor voltage. Figure 3.3.2 shows the time-domain networks and the transformed network
equivalents in the frequency domain for elements R, L, and C. Notice the inclusion of the initial
inductor current by means of the voltage term [Li(0+ )] and the initial capacitor voltage by the
voltage [v(0+ )/s]. Source conversion can be applied to obtain alternate transformed equivalent
networks, as shown in Figure 3.3.2.
The following procedure is applied for the solution of network problems utilizing the
transformed networks in the frequency domain.
1. Replace the time-domain current and voltage sources by the Laplace transforms of their
time functions; similarly, replace the dependent-source representations. Transform the
circuit elements into the frequency domain with the use of Figure 3.3.2.
2. For the resultant transformed network, write appropriate KVL and KCL equations using
the mesh and nodal methods of analysis.
3. Solve algebraically for the desired network response in the frequency domain.
Laplace Agebraic Inverse Figure 3.3.1 Flow diagram for

transformation manipulation transform Laplace transformation method
of solving differential equations.
Integro-differential Algebraic Standard Total
equation equations forms solution
Initial
conditions
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Time − Domain Network Transformed Network in Frequency Domain
v(t) = Ri(t) V(s) = RI(s)

1 R 2 1 R 2
i (t) I(s)
Resistance
+ v(t) − + V(s) −
(a)
v(t) = L di V(s) = LsI(s) − Li(0+)

Li(0+)
dt
L Ls
i (t) 1 2 I(s) 1 − + 2
Inductance
+ v(t) − + V(s) −
or
V(s) i(0+)
I(s) = Ls
+ s
i(0+)/s
1 Ls 2
I(s)
+ V(s) −
(b)
1 v(0+)
V(s) = I(s) +
v(t) = C1 ∫i(t)dt Cs s
v (0+)/s
i (t) 1 C 2 I(s) 1 1/Cs + −2
Capacitance
+ v(t) − + V(s) −
or
I(s) = Cs V(s) − Cv(0+)
Cv(0+)
1 1/Cs 2
I(s)
+ V(s) −
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(c)
Figure 3.3.2 Time-domain networks and transformed network equivalents in frequency domain for
R, L, and C.
4. By taking the inverse Laplace transform of the frequency-domain response, obtain the
time-domain response.
Let us illustrate the use of this procedure with some examples.
EXAMPLE 3.3.1
Consider the circuit shown in Figure E3.3.1(a) in which the switch S has been in position 1 for a
long time. Let the switch be changed instantaneously to position 2 at t = 0. Obtain v(t) for t ≥ 0
with the use of the Laplace transform method.
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4Ω Figure E3.3.1
1 S
t=0
2
+ 2Ω +
10 V 2F v(t)
− −
1H
(a)
+
2Ω 2
s
I(s)
+ V(s)
10
s s
−
−
(b)
Solution
With switch S in position 1 for a long time,
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
vC (0− ) = vC (0+ ) = 10 V
iL (0− ) = iL (0+ ) = 0
The transformed network in the frequency domain is shown in Figure E3.3.1(b).

The KVL equation is given by

2 10
I (s) +2+s =
s s
or
10
I (s) = 2 and V (s) = I (s) (2 + s)
s + 2s + 2
Thus,
10 (s + 2) K1 K1∗
V (s) = = +
s 2 + 2s + 2 s + 1 − j1 s + 1 + j1
where
10 (−1 + j 1 + 2) √
K1 = = 5 2 e−j π/4
(−1 + j 1) + 1 + j 1
By taking the inverse Laplace transform, we get
√ π
v (t) = 10 2 e−t cos t − V
4
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EXAMPLE 3.3.2
Obtain v(t) in the circuit of Figure E3.3.2(a) by using the Laplace transform method.
0.25 Ω 1Ω 0.5 H
− +
+
+ i(t) 3 i(t)
2
Vs(t) = 10 u(t) 0.5 Ω v(t) 0.5 Ω
− 2F
−
(a)
0.25 Ω 1Ω s/2
− + +
+ I(s) 3 I(s)
10 2
1 0.5 Ω V(s) 0.5 Ω
s
− 2s
−
(b)
3 I(s)
2
− +
A B
I(s) 1Ω
s/2
40 1Ω 1 1Ω
s 4 2s 2 +
1Ω V(s)
2
−
0 (Reference node)
(c)
Figure E3.3.2
Solution
All initial values of inductor current and capacitor voltage are zero for t < 0 since no excitation
exists. The transformed network is shown in Figure E3.3.2(b). Let us convert all voltage sources
to current sources and use nodal analysis [Figure E3.3.2(c)].
The KCL equations are given by
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
40 3
VA (4 + 2s + 1) − VB (1) = − Is
s 2

1 3
− VA (1) + VB 1 + 2 + = I (s)
s/2 + 1/2 2
I (s) = 2sVA
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Substitution of I(s) and solving for VB gives

10 (3s + 1) (s + 1)
VB =
3s s 2 + 3s + 2
1/2 1 10(3s + 1) K1 K2 K3
VA = VB = VB = = + +
1/2 + s/2 s+1 3s(s + 1)(s + 2) s s+1 s+2
where
10 (0 + 1) 5
K1 = =
3 (0 + 1) (0 + 2) 3
10 (−3 + 1) 20
K2 = =
3 (−1) (−1 + 2) 3
10 (−6 + 1) 25
K3 = =−
3 (−2) (−2 + 1) 3
Therefore,

5 20 −t 25 −2t
v (t) = + e − e u (t) V
3 3 3
Note that Thévenin’s and Norton’s network theorems are applicable in the frequency domain.
Network functions (also known as system functions) are defined as the ratio of the response to
the excitation in the frequency domain, as illustrated in Figure 3.3.3. Driving-point impedances
and admittances are network functions, as shown in Figure 3.3.4.
The concept of transfer functions is illustrated in Figure 3.3.5, in which the response measured
at one pair of terminals is related to an excitation applied to another pair of terminals.
Linear system Linear system

x(t) y(t) X(s) Y(s)
Excitation Differential Response H(s)
equation
Y(s)
H(s) =
x(t) y(t) X(s)
(a) (b)
Figure 3.3.3 Linear system with no initial energy storage. (a) Time domain. (b) Frequency domain.
I(s) Figure 3.3.4 Network functions.

+
V(s) Network
−
Driving-point impedance Z(s) = V(s) / I(s)
Driving-point admittance Y(s) = I(s) / V(s)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
I1(s) I2(s) Figure 3.3.5 Network transfer func-

+ + tions.
Input V1(s) Network V2(s) Output
− −
Transfer functions V2(s) V2(s) I2(s) I2(s)
; ; ;
V1(s) I1(s) V1(s) I1(s)
EXAMPLE 3.3.3
A network function is given by
2 (s + 2)
H (s) =
(s + 1) (s + 3)
(a) For x(t) = δ(t), obtain y(t).

(b) For x(t) = u(t), obtain y(t).
(c) For x(t) = e−4t , obtain y(t).
(d) Express the differential equation that relates x(t) and y(t).
Solution
(a) For x(t) = δ(t), X(s) = 1. Hence,

2 (s + 2) K1 K2
Y (s) = H (s) X (s) = H (s) = = +
(s + 1) (s + 3) s+1 s+3
where
2 (−1 + 2)
K1 = =1
−1 + 3
2 (−3 + 2)
K2 = =1
−3 + 1
Thus,
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
y (t) = e−t + e−3t
Note that L −1 [H(s)] yields the natural response of the system.

(b) For x(t) = u(t), X(s) = 1/s. Hence,
1 2 (s + 2) 1 K1 K2 K3
Y (s) = H (s) X (s) = H (s) = = + +
s (s + 1) (s + 3) s s+1 s+3 s
where
2 (−1 + 2)
K1 = = −1
(−1 + 3) (−1)
Copyright OUP
2 (−3 + 2) 1
K2 = =−
(−3 + 1) (−3) 3
2 (0 + 2) 4
K3 = =
(0 + 1) (0 + 3) 3
Thus,
1 4
y (t) = −e−t − e−3t +
3 3
The first two terms on the right-hand side are the natural response arising from H(s),
whereas the last term is the forced response arising from X(s). Note that K 3 is H (s) |s=0 ,
while X (s) = 1/s.
(c) For x(t) = e−4t , X(s) = 1/(s + 4). Hence,
1 2 (s + 2) 1
Y (s) = H (s) X (s) = H (s) =
s+4 (s + 1) (s + 3) (s + 4)
K1 K2 K3
= + +
s+1 s+3 s+4
where
2 (−1 + 2) 1
K1 = =
(−1 + 3) (−1 + 4) 3
2 (−3 + 2)
K2 = =1
(−3 + 1) (−3 + 4)
2 (−4 + 2) 4
K3 = =−
(−4 + 1) (−4 + 3) 3
Thus,
1 −t 4
y (t) = e + e−3t − e−4t
3 3
The first two terms on the right-hand side are the natural response arising from H(s),
whereas the last term is the forced response arising from X(s). Note that K 3 is H (s) |s=−4 ,
whereas X(s) = 1/(s + 4).
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
2 (s + 2)
(d) Y (s) = H (s) X (s) = X (s)
(s + 1) (s + 3)
or (s + 1) (s + 3) Y (s) = 2 (s + 2) X (s), or s 2 + 4s + 3 Y (s) = (2s + 4) X (s). Rec-
ognizing that multiplication by s in the frequency domain corresponds to differentiation
in the time domain, the differential equation is expressed as
d 2y dy dx
+4 + 3y = 2 + 4x
dt 2 dt dt
3.4 FREQUENCY RESPONSE

Earlier we examined the circuit response to sinusoids that have a fixed frequency. Now let us
examine the response of a circuit to a sinusoidal source, called an oscillator, whose frequency can
be varied. Known as the frequency response, it is often expressed as a network function, which is an
output–input ratio. In order to visualize the changes in phase shift and amplitude as the frequency of
Copyright OUP
3.4 FREQUENCY RESPONSE 155
the input signal changes, a graphical display of the frequency-response characteristics of networks
is often employed.
A filter is a network used to select one range of frequencies, while rejecting all other
frequencies. Let us now consider simple networks which function as filters. For the RC network
shown in Figure 3.4.1, the voltage transfer function V̄out /V̄in is given by
V̄out 1 1
H̄ (j ω) = = = − tan−1 (ωRC) = H (ω) θ (ω) (3.4.1)
V̄in 1 + j ωRC 1 + (ωRC) 2
where H(ω) is the amplitude ratio and θ(ω) is √ the phase shift. Defining the cutoff frequency as
the frequency ω at which H (ω) is reduced to 1/ 2, or 0.707 of its maximum value (which is 1.0
at ω = 0), it follows that
1
ωCO = (3.4.2)
RC
and the phase shift becomes −45° at that cutoff frequency, as shown in Figure 3.4.2. The power
delivered to the circuit, at this frequency, is one-half the maximum power. As a consequence, ωCO
is also called the half-power point, or half-power angular frequency. We see that this filter circuit
of Figure 3.4.1 is indeed a low-pass filter because any input signal components at ω << ωCO are
passed to the output with virtually unchanged amplitude and phase, whereas any components
at ω >> ωCO have greatly reduced output amplitudes. ωCO roughly divides the passband
(region of transmitted frequencies) from the stopband (region of high attenuation). The range
of transmitted frequencies is known as the bandwidth. Note that in Figure 3.4.1 the low-pass
filtering properties come from the fact that the capacitor is an open circuit for ω = 0 but becomes
a short circuit for ω → ∞ and “shorts out” any high-frequency voltage components across the
output.
The low-pass simple filter circuits are shown in Figure 3.4.3 and Figure 3.4.4 gives the high-
pass simple filter circuits. Note the interchange of resistance and reactance, which converts a
low-pass filter into a high-pass filter, or vice versa.
+ + Figure 3.4.1 RC network.

RΩ
−− 1 Ω −−
Vin Vout
jωc
− −
Amplitude ratio H (ω) Figure 3.4.2 Frequency response of

RC network of Figure 3.4.1.
1.0
0.707
Pass
0 band
ω
ωco = 1/RC ω
−45°
−90°
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Phase shift θ (ω)
Copyright OUP
+ + + +
jωL R
Vin Vout Vin 1 Vout
R jωC
− − − −
(a) (b)
Figure 3.4.3 Low-pass simple filter circuits. (a) RL low-pass filter. (b) RC low-pass filter.
+ + + +
R 1
Vin jωL Vout Vin jωC R Vout
− − − −
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(a) (b)
Figure 3.4.4 High-pass simple filter circuits (a) RL highpass filter. (b) RC high-pass filter.
The low-pass transfer function, given by Equation (3.4.1), can be written as

1 ω
H (ω) = ; θ(ω) = − tan−1 (3.4.3)
ωCO
1 + (ω/ωCO )2
which also applies to the RL low-pass filter with ωCO = R/L.
The high-pass transfer function for either of the circuits of Figure 3.4.4 is given by
(ω/ωCO ) ω
H (ω) = ; θ (ω) = 90° − tan−1 (3.4.4)
1 + (ω/ωCO ) 2 ωCO
where ωCO = R/L or 1/RC. The ideal response characteristics of low pass, high pass, bandpass,
and band reject are shown in Figure 3.4.5.
Due to the greater availability and lower cost of capacitors and the undesirable resistance
usually associated with inductors, virtually all simple filter designs employ capacitors rather than
inductors, despite the similarity of RL and RC circuits. More sophisticated filters use two or more
reactive elements in order to have essentially constant or flat H(ω) over the passband and narrow
transition between the passband and the stopband.
One of the most common forms of display of the network function H̄ (j ω) is the Bode
diagram. In this diagram the magnitude and phase of H̄ (j ω) are plotted separately as functions
of the frequency variable ω. A logarithmic scale is used for the frequency variable in order
to accommodate wide frequency ranges, and the magnitude of the network function H(ω) is
expressed in decibels (dB) as
H (dB) = 20 log10 H (3.4.5)
The two portions of the Bode plot, H(ω) and θ(ω), are graphed on semilog axes. The advantage
of this technique is that rather than plotting the network characteristic point by point, one can
employ straight-line approximations to obtain the characteristic quite efficiently.
Asymptotic Bode plots lead to simply drawn approximate characteristics which are quite
adequate for many purposes and reduce the calculational complications greatly. The frequency
response is found by substituting s = j ω in the network function H(s). Let
Copyright OUP
H(ω) H(ω)
Ideal
Ideal
Passband
Actual Passband
Actual
ω ω
0 ωco 0 ωco
(a) (b)
H(ω) H(ω)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Ideal Ideal
Actual
Passband Actual Passband Passband
ω ω
0 ω1 ω2 0 ω1 ω2
(c) (d)
Figure 3.4.5 Ideal response characteristics. (a) Low pass. (b) High pass. (c) Band pass. (d) Band reject.

1+ 1+jω
01
jω
02
··· 1 + jω
0m
H̄ (j ω) = k (3.4.6)
1 + jpω1 1 + jω
p2
··· 1 + jω
pn
where −01 , −02 , . . . , −0m are the zeros, and −p1 , −p2 , . . . , −pn are the poles of the network
function. Equation (3.4.6) is clearly the product of a constant and a group of terms having the form
(1 + j ω/ω0 ) or 1/(1 + j ω/ω0 ). Each of these terms can be considered as an individual phasor,
and H̄ (j ω) has a magnitude given by the product of the individual magnitudes (or the sum of the
individual terms expressed in dB) and an angle given by the sum of the individual angles. Thus
the behavior of functions (1 + j ω/ω0 ) and 1/(1 + j ω/ω0 ) is to be clearly understood for the
construction of Bode plots.
Let us first consider H̄1 (j ω) = 1 + j ω/ω0 . For ω/ω0 << 1 (i.e., low frequencies), the
magnitude H1 (ω) ∼ = 1, or H1 (ω)dB = 20 log 1 = 0 dB. The break frequency is ω = ω0 . At high
frequencies (i.e., ω/ω0 >> 1), the function behaves as
ω ω
H1 (ω) ∼= or H1 (ω)dB = 20 log
ω0 ω0
at ω/ω0 = 1,
H1 (ω)dB = 0 dB
at ω/ω0 = 10,
H1 (ω)dB = 20 log 10 = 20 dB
and at ω/ω0 = 100,
H1 (ω)dB = 20 log 100 = 40 dB
Copyright OUP
Since factors of 10 are linear increments on the logarithmic frequency scale, the plot of 20 log
(ω/ω0 ) versus ω on a semilog paper is a straight line with a slope of +20 dB/decade or +6
dB/octave, as shown in Figure 3.4.6. Note that an octave represents a factor of 2 in frequency,
whereas a decade represents a factor of 10. The angle associated with H̄1 (j ω) is θ1 (ω) =
tan−1 (ω/ω0 ). At low frequencies (ω ≤ 0.1ω0 ), θ1 ∼ = 0; for frequencies ω ≥ 10ω0 , θ1 ∼ = 90°;
and at ω = ω0 , θ1 = +45°. This leads to the straight-line approximations for θ1 (ω), as shown
in Figure 3.4.6. For 0.1ω0 ≤ ω ≤ 10ω0 , the slope of θ1 (ω) versus ω is approximately given by
+45°/decade (over two decades centered at the critical frequency) or +13.5°/octave. Thus the
asymptotic Bode plot for H̄1 (j ω) = 1 + j ω/ω0 is drawn in Figure 3.4.6. Figure 3.4.7 gives the
asymptotic Bode plot for H̄2 (j ω) = 1/(1 + j ω/ω0 ) with a similar kind of reasoning. The student
is encouraged to justify the plot. The dashed curves in Figures 3.4.6 and 3.4.7 indicate the exact
magnitude and phase responses.
The process of developing asymptotic Bode plots is then one of expressing the network
function in the form of Equation (3.4.6), locating the break frequencies, plotting the component
asymptotic lines, and adding these to get the resultant. The following example illustrates the
procedure.
H1(ω) dB Figure 3.4.6 Asymptotic Bode plot for H̄1 (j ω) =

1 + j ω/ω0 .
Asymptotic
40
20
Exact
Slope =
0 ω
+20 dB/decade or
+6 dB/octave
−20
θ1(ω), deg Slope = +45° /decade or

+13.5° /octave
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
90
45
Asymptotic
0 ω
Exact
−45
−90
0.1 ω0 1 ω0 10 ω0 100 ω0
ω, rad/s
EXAMPLE 3.4.1
Sketch the asymptotic Bode plot for
104 (s + 50)
H (s) =
s 2 + 510s + 5000
Copyright OUP
Solution
100(1 + s/50) 100(1 + j ω/50)
H (s) = or H̄ (j ω) =
(1 + s/10)(1 + s/500) (1 + j ω/10)(1 + j ω/500)
The break frequencies are 10 and 500 rad/s for the denominator and 50 rad/s for the numerator.
The component straight-line segments are drawn as shown in Figure E3.4.1. Note that the effect
of the constant multiplier 100 in H̄ (j ω) is to add a constant value, 20 log 100 = 40 dB, as marked
in the Bode plot. The resultant asymptotic magnitude H(ω) and angle θ(ω) characteristics are
indicated by the dashed lines.
H(ω), dB Figure E3.4.1 Asymptotic Bode plot.

40
40 dB
30 H(ω) dB
20
Magnitude of (1 + jω /50)
10
0 ω
−10
Magnitude of
−20
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
( 1
1 + jω /10 )
−30 Magnitude of
θ(ω), deg ( 1
1 + jω /500 )
+90
+60
Angle of (1 + jω /50)
+30
0 ω
Angle of
−30 ( 1
1 + jω /500 )
Angle of
−60 ( 1
1 + jω /10 ) Angle θ (ω)
−90
0.1 1 10 100 1000 10,000

Angular frequency, rad/s (logarithmic scale)
As seen from Example 3.4.1, the frequency response in terms of the asymptotic Bode plot is
obtained with far less computation than needed for the exact characteristics. With little additional
effort, by correcting errors at a few frequencies within the asymptotic plot, one can get a sufficiently
accurate result for most engineering purposes. While we have considered H̄ (j ω) of the type
given by Equation (3.4.6) with only simple poles and zeros, two additional cases need further
consideration:
Copyright OUP
H2(ω), dB Figure 3.4.7 Asymptotic Bode plot for H̄2 (j ω) =

1/(1 + j ω/ω0 ).
40
20
0 ω
Asymptotic
Exact
−20
Slope = −20 dB/decade or
−6 dB/octave
θ2(ω), deg
90
45 Slope = −45° /decade or
−13.5° /octave
0 ω
Asymptotic
−45
−90 Exact
0.1 ω0 1 ω0 10 ω0 100 ω0
ω, rad/s
Case 1: Zero or Pole at Origin

lims→0 H (s) = Ks n , where n can be any positive or negative integer. The magnitude
characteristic for this factor has a slope of 20n dB/decade and passes through K dB at
ω = 1, while the component angle characteristic has a constant value of n × 90°.
Case 2: Some Zeros or Poles Occur as Complex Conjugate Pairs

Let

s s α s2
H (s) = 1 + 1+ =1+2 2 s +
α + jβ α − jβ α + β2 α2 + β 2

of α + β , the magnitude is characterized by a slope of 40
With a break frequency 2 2
dB/decade for ω ≥ α 2 + β 2 , and theangle characteristic shows a slope of 90°/decade in

the range of 0.1 α 2 + β 2 ≤ ω ≤ 10 α 2 + β 2 . The asymptotic Bode plot for this case is
shown in Figure 3.4.8.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Note that the angle and magnitude characteristics will have the opposite sign for the case of
a complex conjugate pair of poles. It should also be pointed out that the straight-line quadratic
representations are not generally good approximations (particularly in the one-decade region on
either side of the break frequency), and a few points may be calculated to obtain the correct curves
in the questionable frequency range.
For the series RLC circuit, the input admittance is given by
Copyright OUP
H(ω), dB Figure 3.4.8 Asymptotic Bode plot for

α
the quadratic H (s) = 1 + 2 2 s+
α + β2
s2
.
Slope = 40 dB/decade α + β2
2
80
40
0
θ(ω), deg 0.1 1 10 100 ω / α2 + β2
180
90 Slope = 90°/decade
0
ω / α 2 + β2
1 1
Ȳ (j ω) = = (3.4.7)
R + j ωL + 1/j ωC R + j (ωL − 1/ωC)
√
At the series resonant frequency ω0 = 1/ LC,
1
Ȳ (j ω0 ) = = Y0
R
corresponds to maximum admittance (or minimum impedance). The ratio Y/Y 0 can be written as
Ȳ R 1
(j ω) = =
Y0 1 L 1
R + j ωL − 1+j ω−
ωC R ωLC
1
= (3.4.8)
ω0 L ω ω0
1+j −
R ω0 ω
Introducing a quality factor QS = ω0 L/R and per-unit source frequency deviation δ = (ω −
ω0 )/ω0 ,
Ȳ 1 1
(j ω) = = (3.4.9)
Y0 ω ω0 2+δ
1 + j QS − 1 + j δQS
ω0 ω 1+δ
For δ << 1, i.e., for small frequency deviations around the resonant frequency, Equation (3.4.9)
becomes, near resonance,
Ȳ 1
(j ω) = (3.4.10)
Y0 1 + j 2δQS
which is the equation of the universal resonance curve plotted in Figure 3.4.9. The curve
applies equally well to the parallel GLC circuit with Z̄/Z0 as the ordinate, when the value of
Qp = ω0 C/G. The bandwidth and the half-power points in a resonant circuit (either series or
parallel) correspond to ω0 /Q and 2δQ = ±1 when the magnitude Y/Y 0 or Z/Z 0 is 0.707.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
1.0
0.707
Y or Z Bandwidth
Y0 Z0
For For
( )( )
series
RLC
parallel
GLC
Half-power points
−1.5 −1 −0.5 0 0.5 1 1.5 δQ
ω1 ω0 ω2 ω
Figure 3.4.9 Universal resonance curve.
EXAMPLE 3.4.2
Consider the circuit shown in Figure E3.4.2 with R << ωL. Find (a) the resonant angular
frequency ω0, (b) the quality factor Q, and (c) the maximum impedance Zm. Comment on the
applicability of the universal resonance curve.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Figure E3.4.2 Circuit.
R
C
L
Solution
1 R + j ωL
Z̄ (j ω) = =
j ωC + 1/ (R + j ωL) 1 + j ωRC − ω2 LC
For R << ωL,
j ωL 1
Z̄ (j ω) = =
1 + j ωRC − ω LC
2 (RC/L) + j (ωC − 1/ωL)
Copyright OUP
1 ω0 L L
ω0 = √ ; Q= ; Zm = = RQ2
LC R RC
The universal resonance curve and the conclusions obtained from it apply to this circuit, provided
ωL >> R, or Q ≥ 10.
Two-Port Network Parameters

A pair of terminals at which a signal may enter or leave a network is called a port, and a network
having two such pairs of terminals, labeled generally input and output terminals, is known as a two-
port network. A two-port network forms a very important building block in electronic systems,
communication systems, automatic control systems, transmission and distribution systems, or in
other systems in which an electric signal or electric energy enters the input terminals, is acted
upon by the network, and leaves via the output terminals.
The two-port network (or two-terminal-pair network) shown in Figure 3.4.10 is described
by port currents and voltages (i.e., four variables) related by a set of linear equations in terms of
two-port parameters. Of the six possible parameter sets, the three used extensively in electronic
circuit analysis are given next in the frequency domain.
1. Two-port admittance or y parameters (in siemens),
I1 = y11 V1 + y12 V2 = yi V1 + yr V2 (3.4.11)

I2 = y21 V1 + y22 V2 = yf V1 + yo V2 (3.4.12)
where
*
I1 **
y11 = yi = * = short-circuit input admittance
V1 *
V2 =0
*
I1 **
y12 = yr = * = short-circuit reverse transfer admittance
V2 *
V1 =0
*
I2 **
y21 = yf = * = short-circuit forward transfer admittance
V1 *
V2 =0
*
I2 **
y22 = yo = * = short-circuit output admittance
V2 *
V1 =0
2. Two-port impedance or z parameters (in ohms),
V1 = z11 I1 + z12 I2 = zi I1 + zr I2 (3.4.13)
1 2 Figure 3.4.10 Two-port network (or

+ + two-terminal-pair network).
I1(s) I2(s)
V1(s) V2(s)
− −
1′ 2′
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
V2 = z21 I1 + z22 I2 = zf I1 + zo I2 (3.4.14)
where *
V1 **
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
z11 = zi = * = open-circuit input impedance
I1 *
I2 =0
*
V1 **
z12 = zr = * = open-circuit reverse transfer impedance
I2 *
I1 =0
*
V2 **
z21 = zf = * = open-circuit forward transfer impedance
I1 *
I2 =0
*
V2 **
z22 = zo = * = open-circuit output impedance
I2 *
I1 =0
3. Two-port hybrid or h parameters,
V1 = h11 I1 + h12 V2 = hi I1 + hr V2 (3.4.15)

I2 = h21 I1 + h22 V2 = hf I1 + ho V2 (3.4.16)
where *
V1 **
h11 = hi = * = short-circuit input impedance (ohms)
I1 *
V2 =0
*
V1 **
h12 = hr = * = open-circuit reverse voltage gain (dimensionless)
V2 *
I1 =0
*
*
I2 *
h21 = hf = * = short-circuit forward current gain (dimensionless)
I1 *
V2 =0
*
I2 **
h22 = ho = * = open-circuit output admittance (siemens)
V2 *
I1 =0
EXAMPLE 3.4.3
Consider Equations (3.4.11) through (3.4.16). Develop the y-parameter, z-parameter, and h-
parameter equivalent circuits. Also express the z-parameters in terms of y-parameters.
Solution
Equations (3.4.11) and (3.4.12) can be expressed as

− I1 + (y11 + y12 ) V1 − y12 (V1 − V2 ) = 0
− I2 + (y22 + y12 ) V2 − y12 (V2 − V1 ) + (y21 − y12 ) V1 = 0
Copyright OUP
The y-parameter equivalent circuit that satisfies these equations is shown in Figure E3.4.3(a).
−y12 Figure E3.4.3 (a) y-para-

1 2
+ + meter equivalent circuit.
I1 I2 (b) z-parameter equivalent
circuit. (c) h-parameter
V1 y11 + y12 y22 + y12 (y21 − y12)V1 V2 equivalent circuit.
− −
1′ 2′
(a)
1 2
+ +
I1 z11 − z12 z22 − z12 − + I2
(z21 − z12)I1
V1 z12 V2
− −
1′ 2′
(b)
1 2
+ +
I1 h11 I2
+
V1 h12V2 h21I1 h22 V2
−
− −
1′ 2′
(c)
Equations (3.4.13) and (3.4.14) can be arranged as

V1 = (z11 − z12 ) I1 + z12 (I1 + I2 )
V2 = (z21 − z12 ) I1 + (z22 − z12 ) I2 + z12 (I1 + I2 )

The z-parameter equivalent circuit that satisfies these equations is shown in Figure E3.4.3(b).
The h-parameter equivalent circuit satisfying Equations (3.4.15) and (3.4.16) is shown in Figure
E3.4.3(c).
Equations (3.4.11) and (3.4.12) can be solved simultaneously to yield
y22 −y12
V1 = I1 + I2
y11 y22 − y12 y21 y11 y22 − y12 y21
−y21 y11
V2 = I1 + I2
y11 y22 − y12 y21 y11 y22 − y12 y21
By comparing these with Equations (3.4.13) and (3.4.14), one gets
y22 −y12
z11 = ; z12 =
y11 y22 − y12 y21 y11 y22 − y12 y21
−y21 y11
z21 = ; z22 =
y11 y22 − y12 y21 y11 y22 − y12 y21
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
Block Diagrams
The mathematical relationships of control systems are usually represented by block diagrams,
which show the role of various components of the system and the interaction of variables in it.
It is common to use a block diagram in which each component in the system (or sometimes a
group of components) is represented by a block. An entire system may, then, be represented by the
interconnection of the blocks of the individual elements, so that their contributions to the overall
performance of the system may be evaluated. The simple configuration shown in Figure 3.4.11
is actually the basic building block of a complex block diagram. In the case of linear systems,
the input–output relationship is expressed as a transfer function, which is the ratio of the Laplace
transform of the output to the Laplace transform of the input with initial conditions of the system
set to zero. The arrows on the diagram imply that the block diagram has a unilateral property. In
other words, signal can only pass in the direction of the arrows.
A box is the symbol for multiplication; the input quantity is multiplied by the function in the
box to obtain the output. With circles indicating summing points (in an algebraic sense) and with
boxes or blocks denoting multiplication, any linear mathematical expression may be represented
by block-diagram notation, as in Figure 3.4.12 for the case of an elementary feedback control
system.
The block diagrams of complex feedback control systems usually contain several feedback
loops, and they may have to be simplified in order to evaluate an overall transfer function for the
system. A few of the block diagram reduction manipulations are given in Table 3.4.1; no attempt
is made here to cover all the possibilities.
Figure 3.4.11 Basic building block of a block diagram.

R(s) C(s)
G(s)
Input Output
Controlled Figure 3.4.12 Block diagram of an el-

Reference Actuating Feedforward variable ementary feedback control system.
input signal elements (output signal)
R(s) + E(s) C(s)
G(s)
r(t) − e(t) c(t)
B(s) b(t)
Feedback
H(s)
signal
Feedback elements
R(s)
Reference input
C(s)
Output signal (controlled variable)
Feedback signal = H(s)C(s)
B(s)
Actuating signal (error) = [R(s) − B(s)]
E(s)
G(s)
Forward path transfer function or
open-loop transfer function = C(s)/E(s)
M(s) Closed-loop transfer function = C(s)/R(s) = G(s)/[1 + G(s)H(s)]
H(s) Feedback path transfer function
G(s)H(s) Loop gain
E(s) 1
= Error-response transfer function
R(s) 1 + G(s)H(s)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
TABLE 3.4.1 Some of the Block Diagram Reduction Manipulations

Original Block Diagram Manipulation Modified Block Diagram
R G1 G2 C R G1G2 C
Cascaded elements
R +
G1 Addition or subtraction
+ R C
− (eliminating auxiliary G1 ± G2
G2 forward path)
R C R C
G Shifting of pickoff G
point ahead of block G
R C
R C G
G Shifting of pickoff
point behind block 1/G
R + E R + E
G G
Shifting summing −
− C
point ahead of block 1/G
C
R + E R + E
G Shifting summing G
− −
point behind block C
C G
R + C
G R + C
− Removing H from 1/H H G
−
feedback path
H
R + C
G R G C
− Eliminating
feedback path 1 + GH
H
EXAMPLE 3.4.4
Feedback amplifiers are of great importance in electronic circuits. The block diagram of a class
of feedback amplifier is shown in Figure E3.4.4(a). Determine the transfer function C/R for the
block diagram.
G0 Figure E3.4.4
+ +
Σ G1 G2 G3 Σ
R + C
−
H
(a)
Copyright OUP
--`,,,``,,`,```,`
G0 Figure E3.4.4 Continued
+ +
Σ GA = G 1 G2 G3 Σ
R + C
−
H
(b)
G0
R
GA +
1 + GAH Σ
+ C
(c)
GA
G0 +
R 1 + GAH C
(d)
Solution
The three blocks in cascade are combined to yield GA = G1 G2 G3 , as illustrated in Figure

E3.4.4(b).
By eliminating the feedback path, the circuit of Figure E3.4.4(c) is obtained. By eliminating
the auxiliary forward path, one gets the circuit of Figure E3.4.4(d). Thus,
C GA
= G0 +
R 1 + GA H
where GA = G1 G2 G3 .
A linear system of equations can also be represented diagrammatically by a signal-flow graph

(consisting of nodes and branches), which is used to describe a system schematically in terms of
its constituent parts. However, in view of the scope of this text, the topic of signal-flow graph is
not presented.
3.5 COMPUTER-AIDED CIRCUIT SIMULATION FOR TRANSIENT ANALYSIS, AC

ANALYSIS, AND FREQUENCY RESPONSE USING PSPICE AND PROBE
Transient Analysis
PSpice is capable of performing transient circuit analysis, for which the request is given by the
following statement:
• TRAN
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
TSTEP TSTOP TSTART TMAX UIC

where TSTEP is the interval between points printed, plotted, or reported to PROBE, TSTOP
is the time value for which the analysis is stopped, TSTART is the beginning time value for
Copyright OUP
3.5 COMPUTER-AIDED CIRCUIT SIMULATION 169
which results are printed, plotted, or reported to PROBE, TMAX is the maximum time increment
between computed values, and UIC is a keyword that causes PSpice to use initial conditions
specified for inductors and capacitors in the element statements. In case of omission, TSTART
defaults to zero and TMAX to (TSTOP − TSTART)/50. If UIC is omitted, PSpice computes
initial conditions by assuming that the circuit is dc steady state prior to t = 0. Let us present an
illustrative example.
EXAMPLE 3.5.1
Develop and execute a program to analyze the circuit shown in Figure E3.5.1(a), and use PROBE
for plotting vC (t).
t=0 Figure E3.5.1

L R
+ 10 mH 100 Ω
+
C
Vs = 10 V i(t) 1 µF vC (t) Initial conditions
− i(0) = 0; vC (0) = 0
−
(a)
L R
1 2 3
+ 10 mH 100 Ω
+
C
1 µF vC (t); vC (0) = 0
i(t); i(0) = 0 −
−
0
(b)
15
10
Voltage V vC (t)
5
0
0.2 0.4 0.6 0.8 1.0
t, ms
(c)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Solution
The program is as follows:

EXAMPLE E3.5.1
* THE CIRCUIT DIAGRAM SUITABLE FOR ANALYSIS IS GIVEN IN
FIGURE E3.5.1(b)
Copyright OUP
VS 1 0 10
L 1 2 10 MH IC = 0, INITIAL CURRENT IS ZERO
R 2 3 100
C 3 0 1 UF IC = 0; INITIAL VOLTAGE IS ZERO
* TRANSIENT ANALYSIS REQUEST
• TRAN 0.02 MS IMS 0 0.02 MS UIC
• PROBE
• END
A plot of vC (t) is shown in Figure E3.5.1(c).
Steady-State Sinusoidal Analysis with PSpice

PSpice can easily solve steady-state ac circuits for currents and voltages. Ac voltage sources,
which must begin with the letter V, are specified by statements of the form
VNAME N+ N− AC VPEAK PHASE
where VNAME is the name of the voltage source, N+ is the node number of the positive reference,
N− is the node number of the negative reference, AC indicates that this is an ac source, VPEAK
is the peak value of the voltage, and PHASE is the phase angle of the source in degrees. Current
sources, which must begin with the letter I, are specified in a similar manner, with the reference
direction for the current source pointing from the first node number given in the statement to the
second node number.
The ac analysis request is made with a statement of the form
• AC LIN NPOINTS STARTFREQ STOPFREQ
where • AC designates a request for frequency analysis, LIN defines a linear frequency sweep
with NPOINTS specifying the number of points in the sweep starting at the STARTFREQ and
finishing at the STOPFREQ. For example, to carry out a steady-state ac analysis for a frequency
of 60 Hz, the analysis request would be
• AC LIN 1 60 60
Let us present an illustrative example.
EXAMPLE E3.5.2
Use PSpice to solve for the amplitude and phase of the current and the voltage across the inductor
in the circuit shown in Figure E3.5.2(a).
Solution
The program is as follows:

* THE CIRCUIT DIAGRAM SUITABLE FOR ANALYSIS IS GIVEN IN
FIGURE E3.5.2(b)
VS 1 0 AC 100 30
R 1 2 100
L 2 3 0.3 H
C 3 0 40 UF
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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3.5 COMPUTER-AIDED CIRCUIT SIMULATION 171
• AC LIN 1 79.58 79.58

* 79.58 IS THE SOURCE FREQUENCY IN HZ GIVEN BY 500/(2π )
• PRINT AC IM(R) IP(R) VM(2,3) VP(2,3)
* IM(R) AND IP(R) DENOTE RESPECTIVELY MAGNITUDE AND PHASE OF THE
CURRENT THROUGH THE R ELEMENT
* VM (2,3) AND VP (2,3) DENOTE RESPECTIVELY MAGNITUDE AND PHASE OF
THE VOLTAGE BETWEEN NODES 2 AND 3 WITH THE POSITIVE REFERENCE AT
NODE 2
• END
After executing the program, the output file contains the following results:
FREQ I(R) IP(R) V(2,3) VP(2,3)
7.958E + 01 7.071E − 01 −1.500E + 01 1.061E + 02 7.500E + 01
Note that I(R) is the same as IM(R) directed from the first node number, 1 in this case, given for R
to the second node number, 2 in this case; V(2,3) is the same as VM(2,3). Thus the phasor current
is given by I¯R = 0.7071 − 15°, and the voltage across the inductor is given by V̄L = 106.1 75°.
Note that the magnitudes are the peak values.
R = 100 Ω Figure E3.5.2
+
vs(t) = 100 cos(500t + 30°) i(t) L = 0.3 H
−
C = 40 µF
(a)
1 R = 100 Ω 2
+ iR(t) +
vs(t) = 100 cos(500t + 30°) vL(t) L = 0.3 H
− −
0
C = 40 µF 3
(b)
Analysis of Frequency Response with PSpice and PROBE

PSpice can readily accomplish the circuit analysis as a function of frequency, and PROBE
can display Bode plots for magnitude and phase of network transfer functions. Besides the
linear (LIN) frequency sweep that we used in steady-state sinusoidal analysis, with a sim-
ilar syntax statement, a logarithmic frequency sweep, with points specifying the number of
points per octave (an octave represents a twofold increase in frequency) or per decade (a
decade represents a tenfold increase in frequency), can be specified. For example, the
statement
• AC DEC 20 10HZ 1MEGHZ
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
requests frequency analysis with 20 points per decade, which is usually a suitable value, starting at
10 Hz and ending at 1 MHz. Note that the frequencies would be uniformly spaced on a logarithmic
frequency scale.
EXAMPLE E3.5.3
Develop a PSpice program and use PROBE to obtain Bode plots of the magnitude and phase of
the transfer function V̄out /V̄in for the high-pass filter circuit shown in Figure E3.5.3(a) along with
node numbers. This filter is to pass components above 1 kHz and reject components below 1 kHz.
1 R = 314.1 Ω 2 C = 0.507 µF 3 Figure E3.5.3 (a) High-pass

+ filter circuit. (b) Magnitude
Bode plot. (c) Phase plot.
+
Vin = 1∠0° L = 50 mH Vout
−
−
0
(a)
20 180°
0 135°
−20
|H(f )| 90°
dB −40
45°
−60
−80 0°
10 Hz 100 Hz 1.0 kHz 10 kHz 100 kHz 10 Hz 100 Hz 1.0 kHz 10 kHz 100 kHz
(c)
(b)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Solution
The transfer function H̄ (f ) = V̄out /V̄in is numerically equal to V(3) since the amplitude of V̄in
is given as 1 V. Thus to obtain a plot of the transfer-function magnitude in decibels, the PROBE
menu commands can be used to request a plot of VDB (3). A Bode plot of the transfer function
can be obtained by requesting a plot of VP (3). The program is as follows:
EXAMPLE E3.5.3
THE CIRCUIT DIAGRAM IS SHOWN IN FIGURE E3.5.3(a)
VIN 1 0 AC 1
R 1 2 314.1
C 2 3 0.507 UF
L 3 0 50 MH
Copyright OUP
3.6 USE OF MATLAB IN COMPUTER-AIDED CIRCUIT SIMULATION 173
• AC DEC 20 10 HZ 100KHZ
* ANALYSIS EXTENDS FROM TWO DECADES BELOW TO TWO DECADES ABOVE
1 KHZ, THAT IS, FROM 10 HZ TO 100 KHZ.
• PROBE
* RESULTS ARE SAVED FOR DISPLAY BY THE PROBE PROGRAM
• END
Figures E3.5.3(b) and (c) display the magnitude and phase plots. Note that the filter gain is nearly
0 dB for frequencies above 1 kHz and falls at the rate of 40 dB per decade for frequencies below
1 kHz.
3.6 USE OF MATLAB IN COMPUTER-AIDED CIRCUIT SIMULATION

We shall illustrate the use of MATLAB by considering the following three examples.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
EXAMPLE 3.6.1
This example is concerned with steady-state sinusoidal analysis by using mesh equations and
MATLAB. Let us consider the circuit shown in Figure E3.6.1 and find the input impedance at the
input interface terminals A–B and the ratio V̄O /V̄S .
ZL1 = j100 Ω
Rs = 50 Ω −j50 Ω IC −j50 Ω
A
+
ZC1 ZC2
+
Vs = 10 ∠0° IA ZL2 j100 Ω RL 50 Ω VO
IB
− Zin
−
B
Figure E3.6.1
Solution
Note that
V̄S V̄O RL I¯B
Z̄IN = − RS and K̄ = =
I¯A V̄S V̄S
The M-file and answers are as follows:
function example361
clc
% Circuit Parameters
RS = 50;
RL = 50;
VS = 10;
Copyright OUP
% Element parameters
ZL1 = 100j;
ZL2 = 100j;
ZC1 = -50j;
ZC2 = -50j;
% I = inverse (Z) *V
I = inv ([RS+ZC1+ZL2 -ZL2 -ZC1;
-ZL2 ZL2+ZC2+RL -ZC2;
-ZC1 -ZC2 ZC1+ZC2+ZL1]) * [VS 0 0]’;
% Mesh Currents
IA = I(1)
IB = I(2)
IC = I(3)
% Answers
KI + RL*IB/VS
ZIN + VS/IA-RS
IA + 0.0100 - 0.0300i
IB = -0.0100 + 0.0300i
IC = 0 - 0.1000i
K = -0.0500 + 0.1500i
ZIN = 5.0000e+01 + 3.0000e+02i
EXAMPLE 3.6.2
Consider the circuit shown in Figure E3.6.2 in the t-domain as well as in the s-domain. Formulate
the s-domain nodal equations and use MATLAB to solve for VA (s) and VB (s).
iL(0)
s
VA(s) VB(s)
at node A at node B
L Ls
R R 1 CvC(0)
iS (t) C IS (s) Cs
(a) (b)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Figure E3.6.2 (a) t-domain. (b) s-domain.
Solution
VA (s) VA (s) − VB (s) iL (0)
At node A: + − IS (s) + =0
R Ls s
Copyright OUP
3.6 USE OF MATLAB IN COMPUTER-AIDED CIRCUIT SIMULATION 175
VB (s) VB (s) − VA (s) iL (0)
At node B: + − − C vC (0) = 0
1/Cs Ls s
Rearranging these equations, one gets

1 1 iL (0)
Node A: G+ VA (s) − vB (s) = IS (s) −
Ls Ls s

1 1 iL (0)
Node B: − VA (s) + + Cs VB (s) = C vC (0) +
Ls Ls s
where G = 1/R. The M-file answers are as follows:
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
function example362
clc
syms s G L C IS iL vC
% Admittance Matrix
Y = [G+1/L/s − 1/L/s; −1/L/s C*s+1/L/s]
% Current Vector
I = [ IS − iL/s; iL/s+C*vC]
% Inverse of Y
inv(Y)
% Node Voltage Solutions
V = factor(inv(Y)*I)
Y =
[ G+1/L/s, -1/L/s]
[ −1/L/s, C*s+1/L/s]
I =
[ IS − iL/s]
[ iL/s+C*vC]
ans =
[ (C*s∧ 2*L+1)/(G*L*s∧ 2*C+G+C*s), 1/(G*L*s∧ 2*C+G+C*s)]
∧
[ 1/(G*L*s 2*C+G+C*s), (G*L*s+1)/(G*L*s∧ 2*C+G+C*s)]
V =
[ (C*s∧ 2*L*IS-C*s*L*iL+IS+C*vC)/(G*L*s∧ 2*C+G+C*s)]
[ (IS+G*L*iL+G*L*s*C*vC+C*vC)/(G*L*s∧ 2*C+G+C*s)]
EXAMPLE 3.6.3
A bandpass filter design can be accomplished through the cascade connection shown in Figure
E3.6.3, where the frequencies between the two cutoffs fall in the passband of both filters and
are transmitted through the cascade connection, thereby producing the passband of the resulting
bandpass filter.
Figure E3.6.3 Bandpass filter

High-pass filter Low-pass filter
through cascade connection of
ωCHP = ωC1 ωCLP = ωC2 >> ωC1
high-pass and low-pass filters.
Copyright OUP
In this so-called Butterworth bandpass filter, the center frequency and the bandwidth of the
bandpass filter are given by
√
ω0 = ωC1 ωC2 and B = ωC2 − ωC1
and
&
ω0 ωC1
=Q << 1
B ωC2
where ωCHP = ωC1 is the cutoff frequency of the high-pass filter and ωCLP = ωC2 is the cutoff
frequency of the low-pass filter.
In order to design a bandpass filter with a passband gain of 0 dB and cutoff frequencies of
ωC1 = 10 rad/s and ωC2 = 50 rad/s, with the stopband gains of less than −20 dB at 2 rad/s and
250 rad/s, one has chosen the following low-pass and high-pass transfer functions:
1
TLP (s) = √
(s/50)2 + 2(s/50) + 1
(s/10)2
THP (s) = √
(s/10)2 + 2(s/10) + 1
When circuits realizing these two functions are connected in cascade, the overall transfer function
is given by
TBP (s) = THP (s) × TLP (s)
√ MATLAB to illustrate the specified bandpass response with the center frequency ω0 =
Use
10 × 50 = 22.4 rad/s, the bandwidth B = 50 − 10 = 40 rad/s, and the filter quality factor
Q = ω0 /B = 0.56. Note that Q being less than 1 indicates a broad-band response.
Solution
The M-file and answers are as follows:

function example363
clc
% 2nd order Butterworth low pass wc = 50
TLPs = tf(1,[1/50∧ 2 sqrt (2)/50 1])
% 2nd order Butterworth high pass wc = 10
THPs = tf([1/10∧ 2 0 0], [1/10∧ 2 sqrt(2)/10 1])
% 4th order Butterworth bandpass wc1 = 10 wc2 = 50
TBPS = TLPs * THPs
bode (TBPs, {1,1e3});
Transfer function:
1
--------------------------
0.0004 s∧ 2 + 0.02828 s + 1
Transfer function:
0.01 s∧ 2
-----------------------
0.01 s∧ 2 + 0.1414 s + 1
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
3.7 LEARNING OBJECTIVES 177
Transfer function:
0.01 s∧ 2
-----------------------------------------------------
4e-06 s∧ 4 + 0.0003394 s∧ 3 + 0.0144 s∧ 2 + 0.1697 s + 1
Bode Diagrams
−10
−20
−30
Phase (deg); Magnitude (dB)
−40
−50
150
100
50
0
−50
−100
−150
100 101 102 103

Frequency (rad/sec)
Figure E3.6.3 (Part Two) Bode plots for Example 3.6.3.

The learning objectives of this chapter are summarized here so that the student can check whether
• Response to exponential excitations.
• Representation of sinusoidal signals by complex phasors.
• Impedance and admittance of common circuit elements in series–parallel combinations.
• Frequency-domain representations and transformed networks.
• Forced response to sinusoidal excitation.
• Phasor method of analysis and phasor diagrams.
• Real, reactive, and apparent powers in ac circuits.
• Fourier series (trigonometric and exponential forms).
• Transient and steady-state responses (natural and forced responses) of first- and second-
order circuits.
• Accounting for the effect of nonzero initial conditions.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
• Expressing pulses in terms of step and impulse functions.

• Laplace transformation method of solving differential equations.
• Time-domain networks and transformed networks in frequency domain for network
analysis.
• Network transfer functions.
• Frequency response of networks.
• Low-pass and high-pass filter circuits.
• Bode diagrams and asymptotic Bode plots.
• Two-port network parameters.
• Block diagram representation of simple systems.
• Transient analysis, ac analysis, and frequency response using PSpice and PROBE.
• Use of MATLAB in circuit simulation.
Automotive Ignition System

Ignition systems in automobiles have been designed as a straightforward application of electrical
transients. Figure 3.8.1 shows a simplified ignition circuit for an internal-combustion engine.
The primary inductance, current-limiting resistance, and capacitance form an underdamped series
RLC circuit. Thus, when the points open, an oscillatory current flows through the primary, thereby
inducing the required voltage in the secondary. The points form a switch, which opens and closes
as the engine rotates, exactly at the instant when an ignition spark is needed by one of the cylinders.
During the period when the points are closed, current builds up rather slowly in the primary
winding of the coil, which consists of a pair of mutually coupled inductors, as shown in Figure
3.8.1. The current is interrupted rapidly when the points open. The resulting large rate of change
of current induces a large voltage across the coil secondary, which is connected to the appropriate
spark plug by the distributor.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
The resistance limits the current in case the engine stops with the points closed. Since the
voltage across a capacitance cannot change instantaneously, the capacitor prevents the voltage
Coil Figure 3.8.1 Simplified ignition cir-

(Mutually coupled Distributor cuit for an internal-combustion en-
inductors) gine.
Spark
plug
+
12 V
Primary Secondary
−
Condenser Points
Copyright OUP
PROBLEMS 179
across the points from rising too rapidly when the points open. Otherwise arcing may occur across
the points, which in turn may get burned and pitted.
Electrical transients in many practical systems can be analyzed by means of the techniques
presented in this chapter.
PROBLEMS
3.1.1 (a) The concept of duality can be extended to develop an electric equivalent network (a) using
nonelectric physical systems by means of ana- the force–current analog, and (b) using the force–
logs. For example, the mechanical system voltage analog, and find u(t) for F (t) = 40e−t/4 N.
characteristics can be investigated by means 3.1.5 In an RLC series circuit excited by a voltage source
of an equivalent electrical network. Consider v(t), for R = 10 -, L = 1 H, and C = 0.1 F,
Newton’s second law, Hooke’s law as applied determine v(t) if the capacitor voltage vC (t) =
to springs, and viscous friction law, and find 5e−10t V.
the force–current analog as well as the force– 3.1.6 In a GLC parallel circuit excited by a current
voltage analog by identifying the analogous source i(t), for G = 0.5 S, L = 3 H, and C = 0.5
mathematical relations. F, determine i(t) if the inductor current iL (t) =
(b) Consider the analogy between electrical and 12e−0.5t .
hydraulic systems given in Table 1.5.2. Obtain 3.1.7 Repeat Problem 3.1.6 for iL (t) = 2 cos t/3 A.
the mass balance equation by equating the rate
*3.1.8 Repeat Problem 3.1.5 for vC(t) = 10 cos (2t −30°)
of change of fluid volume to the net difference
V.
between input and output flow. Identify this
equation with that of an RC circuit excited by 3.1.9 An RL series circuit carries a current of 0.02 cos
a current source i(t) = I . 5000t A. For R = 100 - and L = 20 mH, find
the impedance of the series combination and de-
3.1.2 Consider an RL series circuit excited by (a) v(t) =
termine the voltage across the series combination.
20e−2t V, and (b) v(t) = 20 V. Determine the
Sketch the phasor diagram showing all quantities
forced component of the voltage across the induc-
involved.
tor for R = 2 - and L = 2 H.
3.1.10 The voltage across a parallel combination of a 100-
*3.1.3 Consider an RC parallel circuit excited by (a) - resistor and a 0.1-µF capacitor is 10 cos(5000t
i(t) = 20e−2t A, and (b) i(t) = 20 A. Find + 30°) V. Determine the admittance of the parallel
the forced component of the current through the combination and find the current from the supply
capacitor for R = 2 - and C = 2 F. source. Sketch the phasor diagram showing all
3.1.4 For the mechanical spring–mass–friction system quantities involved.
shown in Figure P3.1.4, the differential equation 3.1.11 At the two terminals (A, B) of a one-port network,
relating the force F(t) and the velocity u(t) is the voltage v(t) =
and the current are given to be√
given by √
200 2 cos (377t + 60°) V and i(t) = 10 2 cos
du 1 (377t + 30°) A.
F (t) = M + Du + u dt
dt Cm
(a) Determine the average real power, reactive
where M is the mass, D is the friction, and Cm is the power, and volt-amperes absorbed by the net-
compliance (reciprocal of stiffness) of the spring. work.
For M = 20 kg, D = 4 kg/s, and Cm = 8 N/m,
Spring u(t) Mass Figure P3.1.4

M F(t)
Cm Friction D
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
(b) Find the equivalent components of the net- resistor, and then determine the current in the 4--
work representing the effect at the terminals resistor.
A–B. 3.1.17 A 6.6-kV line feeds two loads connected in par-
(c) Find the Thévenin impedance (or the driving- allel. Load A draws 100 kW at 0.6 lagging power
point impedance) as seen from the terminals factor, and load B absorbs 100 kVA at 0.8 lagging
A–B. power factor.
3.1.12 Repeat Problem 3.1.11 if the 60-Hz voltage and (a) For the combined load, calculate the real
the current at the terminals are given to be V = power, reactive power, volt-amperes, and line
100 V (rms), I = 10 A (rms), power factor = 0.8 current drawn from the supply.
leading. (b) If the power factor on the supply end is to be
*3.1.13 Use (a) mesh analysis and (b) nodal analysis to unity, determine the value of the capacitance
determine the current through the 4-- resistor of to be placed across the load if the frequency
the circuit of Figure P3.1.13. of excitation is 60 Hz.
*3.1.18 Three loads in parallel are supplied by a single-
3.1.14 Use (a) mesh analysis and (b) nodal analysis to
phase 400-V, 60-Hz supply:
determine the voltage V̄ at the terminals A–B of
Figure P3.1.14. Load A: 10 kVA at 0.8 leading power factor
Load B: 15 kW at 0.6 lagging power factor
3.1.15 (a) Obtain a Thévenin equivalent circuit at termi- Load C: 5 kW at unity power factor
nals A–B in the circuit of Problem 3.1.14.
(a) Find the real power, reactive power, volt-
(b) What impedance Z̄L , when connected to A–B, amperes, and line current drawn from the
produces maximum power in Z̄L ? supply by the combined load.
(c) Find the value of the maximum power in Z̄L . (b) If the supply line is to operate at 0.9 leading
3.1.16 In the circuit of Problem 3.1.13, find the Thévenin power factor, determine the value of the ca-
equivalent of the network as seen by the 4-- pacitance to be placed across the load.
4Ω Figure P3.1.13
10 Ω j24 Ω
8Ω
+ 2∠−30° A
20∠0° V 18 Ω −j4 Ω
−
−j1 Ω
1Ω
A
+
3Ω
+ + 2Ω
12∠0° V −j2 Ω V1 + V
− − 3V1
− −
B
Figure P3.1.14
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
PROBLEMS 181
3.1.19 Determine the Fourier series for the periodic wave- output waveform of the voltage vO(t) across the
forms given in Figure P3.1.19. load terminals.
3.1.20 Find the exponential form of the Fourier series of 3.1.22 The full-wave rectified waveform, approximated
the periodic signal given in Figure P3.1.20. Also by the first three terms of its Fourier series, is given
determine the resulting series if T = 2τ . by v (ωt) = Vm sin (ωt/2), for 0 ≤ ωt ≤ 2π , and
2Vm 4Vm 4Vm
*3.1.21 The first four harmonics in the Fourier series of a v (t) = − cos ωt + cos 2ωt
π 3π 15π
current waveform given by
where Vm = 100 V and ω = 2π ×120 rad/s. If v(t)
2Im 2π t Im 4πt
i (t) = sin − sin is applied to the circuit shown in Figure P3.1.22,
π T π T
find the output voltage vO(t).
2Im 6πt Im 8πt
+ sin − sin 3.2.1 Determine i(t) in the circuit of Figure P3.2.1 and
3π T 2π T
sketch it.
where Im = 15 mA and T = 1 ms. If such
a current is applied to a parallel combination of *3.2.2 Obtain i(t) in the circuit of Figure P3.2.2 and
R = 5 k- and C = 0.1 µF, determine the sketch it.
v(t)
t
−T −τ 0 τ T
(a)
i(t)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
−T −τ
t
0 τ T
−A
(b)
Figure P3.1.19
i(t) Figure P3.1.20
Half-cycle of cosine
A
t
−T −τ 0 τ T
Copyright OUP
10 Ω 5 mH 10 Ω Figure P3.1.22
+
+
v(t) 500 µF 90 Ω vO(t)
−
−
8Ω 4Ω S
S
t=0 i(t) t=0 i(t)

+ +
20 V 24 V 6Ω
6H − 10 H
−

'
3.2.3 Determine and sketch v(t) in the circuit of Figure 0, for t < 0
P3.2.3. v (t) =
0.4t, for t ≥ 0
3.2.4 Determine and sketch v(t) in the circuit of Figure
Evaluate: vO (0+ ) and dvdtO (0+ ).
P3.2.4.
3.2.11 Reconsider Problem 3.2.10 and obtain vO(t) for
3.2.5 Obtain and sketch i(t) in the circuit of Figure t ≥ 0.
P3.2.5.
3.2.12 Consider the circuit of Figure P3.2.12. Determine
3.2.6 Obtain and sketch i(t) in the circuit of Figure and sketch iL (t) and vC(t) for capacitance values
P3.2.6. of
*3.2.7 Determine and sketch i(t) in the circuit of Figure (a) 1/6 F, (b) 1/8 F, and (c) 1/26 F. Note that the
P3.2.7. capacitance values are chosen here for calcu-
3.2.8 In the circuit of Figure P3.2.8,
lational ease, even though they are too big and
' not typical.
10 A, for t < 0
i (t) = 3.2.13 For the circuit of Figure P3.2.13, determine and
24e−t , for t ≥ 0
sketch iL (t) and vC(t) for inductance values of
dv + diL +
Find: v(0+ ), iL (0+ ),(0 ), and (0 ). (a) 3/4 H, (b) 2/3 H, and (c) 3/17 H. Note that the
dt dt inductance values are chosen here for calcula-
3.2.9 In the circuit of Figure P3.2.9,
' tional ease, even though they are too big and
24 V, for t < 0
v (t) = not typical.
12 cos t, for t ≥ 0
*3.2.14 Consider the circuit of Figure P3.2.14 in which
dvC + diC the switch S has been open for a long time and is
Determine vC (0+ ), iC (0+ ), (0 ), and,
dt dt closed at t = 0. Determine vC(t) for t ≥ 0.
(0+ ). 3.2.15 In the circuit of Figure P3.2.15, obtain iL (t) and
*3.2.10 In the circuit of Figure P3.2.10, vC(t).
S 2Ω S
t=0 t=0
+ +
2 1
10 A 4Ω F v(t) 12 A 4Ω F v(t)
3 2
− −
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
PROBLEMS 183
4Ω S
Figure P3.2.5
t=0
+
4H
10 V 4Ω
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
−
i(t)
t=0 Figure P3.2.6
S
6Ω
+
4Ω
20 V 6H
−
i(t)
S Figure P3.2.7
t=0
4Ω
10 H
10 A 6Ω +
16 V
− i(t)
+
iL(t) 8Ω iC (t)
+ +
i(t) 4Ω v(t) v(t) 24 Ω 1 F vC (t)
1H − −
−
S iL(t)
+
i(t) 200 Ω + 0.02 µF t=0 R=8Ω L=2H
+ − + +
v(t) v1(t) 10 v1(t) vO(t) 10 V C vC (t)
− + − −
−
−
S Figure P3.2.13
t=0
L=3H C= 1F +
5A R=1Ω 4 6 vC (t)
−
iL(t)
Copyright OUP
S 1 mH 100 Ω Figure P3.2.14
t=0 i(t)
+ 0.1 µF +
10 cos 106 t 99i(t) vC (t)
− −
2Ω t = 0 iL
+
10 sin (3t + 20°) V L = 1H 2Ω 2A
3
−
+
vC C = 3F
− 2
Figure P3.2.15
df (t)
3.2.16 Determine iL (t) and vC(t) in the circuit of Figure (c) f3 (t) = , assuming f (t) is transform-
P3.2.16. dt
able.
3.2.17 Express the waveform of the staircase type shown (d) f4 (t) = t
in Figure P3.2.17 as a sum of step functions.
(e) f5 (t) = sin ωt
3.2.18 The voltage waveform of Figure P3.2.18 is applied
to an RLC series circuit with R = 2 -, L = 2 H, (f) f6 (t) = cos(ωt + θ)
and C = 1 F. Obtain i(t) in the series circuit. (Note (g) f7 (t) = te−at
that the capacitor and inductor values are chosen
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(h) f8 (t) = sinh t
here for calculational ease, although they are too
big and not typical.) (i) f9 (t) = cosh t
3.2.19 (a) Let a unit impulse of current i(t) = δ(t) be df (t)
(j) f10 (t) = 5f (t) + 2
applied to a parallel combination of R = 3 - dt
and C = 21 F. Determine the voltage vC(t) 3.3.2 Using the properties listed in Table 3.3.2, deter-
across the capacitor. mine the Laplace transform of each of the follow-
ing functions.
(b) Repeat (a) for i(t) = δ(t − 3).
(a) te−t
(Note that the capacitance value is chosen here
for calculational ease, even though it is too big (b) t 2 e−t
and not typical.) (c) te−2t sin 2t
3.2.20 (a) Let a unit impulse of voltage v(t) = δ(t) be 1 − cos t
applied to a series combination of R = 20 - (d)
t
and L = 10 mH. Determine the current i(t) in e−2t sin 2t
the series circuit. (e)
t
(b) Repeat (a) for v(t) = δ(t) + δ(t − 3). *3.3.3 Given the frequency-domain response of an RL
circuit to be
3.3.1 Determine the Laplace transform for each of the
10
following functions from the basic definition of I (s) =
Equation (3.3.1). 2s + 5
determine the initial value and the final value of the
(a) f1 (t) = u(t)
current by using the initial-value and final-value
(b) f2 (t) = e−at theorems given in Table 3.3.2.
Copyright OUP
PROBLEMS 185
4Ω S 4Ω
t=0 iL(t)
+ + +
20 V 4H 1 F vC (t) 10 V
5 20 −
− −
Figure P3.2.16
f (t) Figure P3.2.17

Step functions
25
20
15
10
5
t
0 1 2 3 4 5 6 7 8 9
v, V Figure P3.2.18
10
1 2
t, s
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
−10
3.3.4 Determine the inverse Laplace transform of each

10(s 2 + 3s + 2)
(g)
of the following functions. 3(s 2 + 2s + 2)
(s + 1)(s + 2)
(h) 2 2
6(s + 3) s (s + 2s + 2)
(a) 4s
s 2 + 2s + 10 (i)
s+2 (s + 4)(s + 2)
2
(b) 4s
(s + 1)(s + 3)(s + 4) (j)
2
8(s + 1) [ s + 2)2 + 4
(c)
s(s 2 + 2s + 2)
s 2 + 4s + 5 3.3.5 Solve the following differential equations (along
(d)
s 2 + 3s + 2 with the conditions) for t ≥ 0.
2(s + 2)
(e) d2v dv dv
s(s + 1)3 (a) +5 + 4v = 10u (t) ; v 0+ =
s+1 dt+2 dt dt
(f) 0 =0
s 3 + 4s 2 + 3s
Copyright OUP
d2i di di
(b) 3 2 +7 +2i = 10cos2t; i 0+ = 4A; has been open for a long time. At t = 0, the switch
dt dt dt is closed. Find the currents i1(t) and i2(t) for t ≥ 0
0+ = −4A/s
with the use of the Laplace transform method.
d2i di
(c) +2 + 2i = sint − e−2t ; i 0+ = *3.3.8 Determine v(t) and iL (t) in the circuit shown in
dt 2 dt Figure P3.3.8, given that i(t) = 10te−t u(t).
di +
0; 0 = 4A/s
dt 3.3.9 The switch S in the circuit of Figure P3.3.9 has
Identify the forced and natural response compo- been open for a long time before it is closed at
nents in each case. t = 0. Determine vL (t) for t ≥ 0.
3.3.6 Determine the Laplace transform of the waveform 3.3.10 Determine v(t) in the circuit of Figure P3.3.10 if
shown in Figure P3.3.6. i(t) is a pulse of amplitude 100 µA and duration
3.3.7 In the circuit shown in Figure P3.3.7, the switch S 10 µs.
f (t) Figure P3.3.6
10
1 2
t, seconds
−10
2Ω 1H S Figure P3.3.7
i2(t)
i1(t) t=0
+ 4Ω
100 V 8Ω
−
2H
+ Figure P3.3.8
iL(t)
i(t) v(t) 10 Ω 1H 9iL(t)
S Figure P3.3.9
+ 5Ω t=0 +
10 V 0.05 F 2H vL(t)
− −
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
PROBLEMS 187
4 pF Figure P3.3.10
i1 +
i(t) 1000 Ω 100 pF 100 i1 500 Ω v(t)
3.3.11 For the networks shown in Figure P3.3.11, deter- kHz and a bandwidth of 5 kHz. Also find the Q of
mine the transfer function G(s) = Vo (s)/Vi (s). the filter.
3.3.12 The response v(t) of a linear system to a unit-step 3.4.6 Determine the voltage transfer function of the low-
excitation i(t) is given by v(t) = (5 − 3e−t + pass filter circuit shown in Figure P3.4.6, and find
2e−2t ) u(t). Determine the transfer function the expression for ω0 .
H (s) = V (s)/I (s). *3.4.7 Determine the voltage transfer function of the
*3.3.13 The response y(t) of a linear system to a unit-step high-pass filter circuit shown in Figure P3.4.7, and
excitation is y(t) = (4 − 10e−t + 8e−2t ) u(t). find the expression for ω0 .
(a) Find the system function. 3.4.8 Let a square-wave voltage source having an am-
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(b) Find the frequency at which the forced re- plitude of 5 V, a frequency of 1 kHz, a pulse width
sponse is zero. of 0.5 ms, and an internal source resistance of
50 - be applied to a resistive load of 100 -. A
3.3.14 The unit impulse response h(t) of a linear system
filter (inductance L) is inserted between source
is h(t) = 5e−t cos(2t − 30°). Determine H(s).
and load in order to reduce all the high-frequency
3.3.15 The response y(t) of a linear system to an excitation components above 5 kHz. Determine (a) L of the
x(t) = e−2t u(t) is y(t) = (t + 2)e−t u(t). Find low-pass filter, (b) amplitude spectra of VL and VS,
the transfer function. and (c) vL (t).
3.3.16 A filter is a network employed to select one range 3.4.9 Sketch the asymptotic Bode diagrams for the fol-
of frequencies while rejecting all other frequen- lowing functions:
cies. A basic building block often used in inte-
200
grated-circuit filters is shown in Figure P3.3.16. (a) H1 (s) = s
Determine the following for the circuit: (1 + s) 1 +
10
(a) Transfer function Vo(s)/Vi(s).
200s
(b) Response vo(t) for vi(t) = u(t). (b) H2 (s) = s
(1 + s) 1 +
(c) Driving-point impedance Vi(s)/Ii(s). 10
s
3.4.1 For the circuits shown in Figure P3.4.1, sketch
200 1 +
the frequency response (magnitude and phase) of (c) H3 (s) = 10s
V̄out /V̄in . (1 + s) 1 +
*3.4.2 Design the low-pass filter shown in Figure P3.4.2 20
s
(by determining L) to have a half-power frequency 0.5 1 +
of 10 kHz. (d) H4 (s) = 10 s
3.4.3 Design the high-pass filter shown in Figure P3.4.3 (1 + s) 1 +
2
40
(by determining C) to have a half-power frequency
of 1 MHz. 0.5 (1 + s)2
(e) H5 (s) = s
s
3.4.4 Determine L and C of the bandpass filter circuit s 1+ 1+
of Figure P3.4.4 to have a center frequency of 1 10 50
s
MHz and a bandwidth of 10 kHz. Also find the Q 20 1 +
of the filter. (f) H6 (s) = 8
s 2 s
3.4.5 Determine L and C of the band reject filter circuit (1 + s) 1 + 1+
of Figure P3.4.5 to have a center frequency of 100 10 40
Copyright OUP
+ +
R1 R2
+ +
R1 R2 C
vi vo
vi C1 C2 vo
L
− − − −
(a) (e)
+
+
+ + L
vi C C vo R
R
C
vi L vo L L −
−
− − L
(b) (f)
+ +
R1
R2
vi vo
C
− −
(c)
+ R2 +
vi C C vo
R1
− −
(d)
Figure P3.3.11
Figure P3.3.16
2Ω +
iC (t) 1 F +
1F
+ +
vi(t) 0.5 Ω v1 2v1 vo(t)
− −
−
−
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
PROBLEMS 189
+ + Figure P3.4.1
10 Ω
−− −−
Vin jω Ω Vout
− −
(a)
+ +
10 Ω
−− 30 Ω −−
Vin Vout
jω
− −
(b)
+ +
10 Ω
−− 1000 Ω −−
Vin jω4 Ω Vout
jω
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
− −
(c)
Figure P3.4.2
+
+ RS = 30 Ω L
vS (t) RL = 30 Ω vL(t)
−
−
Figure P3.4.3
+
+ RS = 50 Ω C
−
−
Figure P3.4.4
+
+ RS = 50 Ω L C
−
−
Copyright OUP
Figure P3.4.5
L
+
+ RS = 100 Ω
vS (t) C RL = 100 Ω vL(t)
−
−
Figure P3.4.6
+
+ RS L
vS (t) C RL vL(t)
−
−
Figure P3.4.7
+
+ RS C
vS (t) L RL vL(t)
−
−
3.4.10 Reconsider Problem 3.4.9 and the corresponding where the loop gain has a magnitude of unity, then
asymptotic Bode plots. phase margin (PM) is defined by the phase of the
loop gain at ω = ωu plus π. Evaluate GM and PM
(a) Find H̄1 , H̄2 , and H̄3 at ω = 5 rad/s.
for this case from the asymptotic Bode plot.
(b) At what angular frequency ω is the magni- 3.4.13 Sketch the asymptotic Bode plots for the follow-
tude of H̄4 (j ω) one-half of the magnitude of ing loop-gain functions, and find the approximate
H̄4 (j 5)? values of gain and phase margins in each case. (For
(c) Determine the angular frequency at which definitions of GM and PM, see Problem 3.4.12.)
H 6(ω) is 0 dB and the angular frequency at (a) G1 (s) H1 (s) =
which θ6 (ω) = −180°.
12 (0.7 + s)
(d) Let H5 (s) = V2 /V1 . For v1 (t) = 0.1 cos 20t,
(0.003 + s) (0.04 + s) (7 + s)
find the steady-state value of v2(t).
3.4.11 Sketch the idealized (asymptotic) Bode plot for 100(1 + s/3.9607)
the transfer function (b) G2 (s) H2 (s) =
s(1 + 2s)(1 + s/39.607)
10 (1 + j 2ω)
H̄ (j ω) =
(1 + j 10ω) (1 + j 0.25ω) 3.4.14 (a) For a series RLC resonant circuit, find an ex-
pression for the voltage across the resistance
Find the angular frequency at which H(ω) is 0 dB
VR and obtain the ratio VR/VS, where VS is the
and the angular frequency at which θ(ω) = −60°.
applied voltage. Identify the expressions for
*3.4.12 The loop gain of an elementary feedback control the series resonant frequency and bandwidth.
system (see Figure 3.4.12) is given by G(s)·H (s),
which is 10/(1 + s/2)(1 + s/6)(1 + s/50). Sketch (b) Determine the resonant frequency and band-
the asymptotic Bode plot of the loop-gain function. width, given the voltage transfer function to
Gain margin (GM) is defined by [−20 log |Ḡ(ωπ ) be 103 /(s 2 + 103 s + 1010 ).
H̄ (ωπ )|], which is the negative of the magnitude 3.4.15 A simple parallel resonant circuit with L = 50 µH
of the loop gain at ω = ωπ , ωπ represents the is used to perform the frequency selection. The cir-
angular frequency at which the loop gain reaches cuit is to be tuned to the first station at a frequency
a phase of −π . If ωu represents the value of ω of 1000 kHz. In order to minimize the interaction
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
PROBLEMS 191
between signals, the tuning circuit response must

R = 105 -; g = 10−3 S; C1 = C2 = 100 pF.
attenuate the signal of the second station (with a
frequency of 1020 kHz) by four times. 3.4.18 (a) Consider the capacitor-input filter circuit of
(a) Determine the values of G and C. Figure P3.4.18 and obtain the z-parameters for
(b) Find the bandwidth of the circuit. the circuit.
3.4.16 The twin-tee or notch network shown in Figure (b) Determine the transfer function V 2/V 1 when
P3.4.16 is often used to obtain band-reject charac- I 2 is zero.
teristics. 3.4.19 The circuit shown in Figure P3.4.19 is the equiv-
(a) Determine the transfer function V 2/I 1. alent circuit of a field-effect transistor (FET) am-
(b) Find the angular frequency at which the trans- plifier stage.
fer function will be zero. (a) Determine the y-parameters.
*3.4.17 A gyrator is sometimes used in integrated circuits (b) For values of µ = gm /gd >> 1, obtain a
to simulate inductances. Consider the circuit of y-parameter equivalent circuit.
Figure P3.4.17 consisting of a gyrator. 3.4.20 For the circuit shown in Figure P3.4.20, obtain:
(a) Show that the impedance as seen to the right
(a) z- and y-parameters;
at terminals 1–1 can be represented by an
inductor in series with a resistor. (b) Transfer function I 2/I 1 when V2 = 0.
(b) Determine the resonant frequency and band- 3.4.21 For the capacitor input filter circuit of Problem
width for the following values: 3.4.18, determine the h-parameters.
1 1 Figure P3.4.16
Cs Cs
I1 I2
+ +
2R 2R
1
V1 R 2Cs V2
− −
1 2 Figure P3.4.17
+ +
C1 vA gvB gvA vB C2 R
− −
1′ 2′
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Gyrator
I1 I2 Figure P3.4.18
+ +
R1 Ls
V1 1 R2 V2
Cs
− −
Copyright OUP
*3.4.22 Determine the h-parameters for the circuit shown (b) When the resistance R is connected across ter-
in Figure P3.4.22 and obtain the transfer function minals 2–2 , find the impedance seen looking
V2 /V1 when I2 = 0. into terminals 1–1 .
3.4.23 A negative impedance converter circuit shown in 3.4.24 Show that the block diagram of Figure P3.4.24
Figure P3.4.23 is used in some applications where can be reduced to the form of Figure 3.4.12. Find
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
inductors cannot be utilized or where negative Geq(s) and H eq(s).
resistance is beneficial. 3.4.25 Show that the block diagram of Figure P3.4.25(a)
(a) Determine the h-parameters for the network. can be reduced to that of Figure P3.4.25(b).
g Figure P3.4.19
1 2
+ + gmVgs +
1
gd Ω
Vgs
V1 s V2
−
Rk
− −
1′ 2′
R Figure P3.4.20
I1 I2
1 + − 2
+ V +
1
V1 Cs gV R2 V2
− −
1' 2'
R1
1 2 IA
+ + 1 2
I1 I2
Ix R R Iy
1
V1 C1s R2 V2 4 IA
− −
1′ 2′ 1′ 2′
H1
R(s) −
+ G1 + G2 G3 + G4 G6
− +
G5
H2
Figure P3.4.24
Copyright OUP
PROBLEMS 193
H0 Figure P3.4.25
+
+ G1 G2 G3 + G4
− +
H1
+
H3 +
+
H2
(a)
+ G1G4 (H0 + G2G3)

−
H3 (H1 + H2)
(b)
H1 Figure P3.4.26
−
R(s)
Σ G1 Σ G2 G3 C (s)
+ +
+
H2
H1
R(s) − + +
Σ G1 Σ G2 Σ G3 C (s)
+ − −
H3
H2
Figure P3.4.27
3.4.26 The block diagram of Figure P3.4.26 represents a 3.5.1 In the circuit shown in Figure P3.5.1 the switch
multiloop control system. opens at t = 0. Develop and execute a PSpice
program to solve for v(t), and use PROBE to
(a) Determine the transfer function C(s)/R(s).
obtain a plot of v(t).
(b) For G2G3H 2 = 1, evaluate C(s)/R(s). Hint: Use the following analysis request:
*3.4.27 Determine the transfer function C(s)/R(s) of the • TRAN 0.1 MS 50 MS 0 0.1 MS UIC
nested-loop feedback system shown in Figure
P3.4.27. 3.5.2 Obtain a plot of the current i(t) in the circuit of
Figure P3.5.2 by writing a PSpice program and
3.4.28 The equations for a two-port network are given by
using the following analysis request:
V1 = z11 I1 + z12 I2 • TRAN 0.2 MS 80 MS 0 0.2 MS UIC
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
0 = z21 I1 + (z22 + ZL )I2 Hint: Note that a sinusoidal voltage source is spec-
V2 = −I2 ZL ified in PSpice by the statement
VSIN NODEPLUS NODEMINUS
(a) Satisfying the equations, develop a block dia-
gram. SIN (VDC VPEAK FREQ TD
DF PHASE)
(b) Find the transfer function V 2/V 1.
Copyright OUP
where VSIN is the name of the source, NODE-

• TRAN 0.02 10 0 0.02 UIC
PLUS is the number identifying the positive node,
NODEMINUS is the number identifying the nega- 3.5.4 For the circuit shown in Figure P3.5.4, solve for
tive node, VDC is the dc offset, VPEAK is the peak i(t) by writing and executing a PSpice program,
value of the ac component, FREQ is the frequency and obtain a plot of i(t) by using PROBE.
in hertz, TD is the time delay in seconds, DF is a Take the hint from Problem 3.5.2 for specifying the
damping factor, and PHASE is the phase angle in sinusoidal voltage source in the PSpice program.
degrees. The voltage generated is then given by Also use the following analysis request:
v(t) = VDC + VPEAK sin[PHASE], • TRAN 0.1 MS 100 MS 0 0.1 MS UIC
for 0 < t < TD
3.5.5 A dc source is connected to a series RLC circuit by
= VDC + VPEAK sin[2π a switch that closes at t = 0, as shown in Figure
FREQ(t − TD) + PHASE] P3.5.5, with initial conditions. For the values of
R = 20, 40, and 80 -, solve for vC (t) by writing
× exp[−DF(t − TD)],
and executing a PSpice program, and obtain plots
for TD < t by using PROBE.
Also note that DF = 0 for a constant-amplitude Hint: Use the following analysis request:
sinusoid. •TRAN IUS 2MS 0 1US UIC
*3.5.3 With the initial voltage across the capacitor being 3.5.6 In the circuit of Figure P3.5.6, solve for phasors
vC (0) = 10 V, obtain a plot of vC (t) for the circuit V̄1 and V̄2 with peak magnitudes by writing and
of Figure P3.5.3 by writing a PSpice program. executing a PSpice program.
Hint: Use the following analysis request:
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Figure P3.5.1
+
1 mA t=0 v(t) R = 10 kΩ C = 1 µF
1 R = 5 kΩ 2 Figure P3.5.2
+
+
vs(t) = 2 sin(200 t) i(t) C = 1 µF vC (t); vC (0) = 1 V
−
−
1 Figure P3.5.3
+
vC (t) = v1
C = 1 µF vC (0) = 10 V R = 2 MΩ
Copyright OUP
PROBLEMS 195
R = 300 Ω Figure P3.5.4
+
L=1H
vs = 10 sin 300 t i(t) iL(0) = 0
−
t=0 L = 2 mH R Figure P3.5.5
+ +
i(t) C = 5 µF vC (t); vC (0) = 0
vs = 50 V
− i(0) = 0 −
1 2000 µF 2 Figure P3.5.6
2 sin(100t) 10 Ω 0.1 H 1.5 cos(100t)
vL Figure P3.5.7
+ −
50 mH
+ +
vs(t) = 10 cos(104t) i 100 Ω vR
− −
vC
− +
0.2 µF
100 Ω 0.5 H Figure P3.5.8
+ v − + vL −
R
+ +
v1(t) = 100 sin(100t) v2(t) = 100 cos(100t + 30°)
− i(t) −
3.5.7 For the circuit shown in Figure P3.5.7, find the Using a PSpice program and PROBE, obtain the
phasor values (with peak magnitudes) of I¯, V̄R , Bode magnitude plot for the transfer function
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
V̄L , and V̄C by using PSpice. H̄ (f ) = V̄out /V̄in for the frequency range of 10
Hz to 100 kHz. Determine the fall-off rate (in
*3.5.8 Use PSpice to find the phasor I¯ (with peak mag-
dB/decade) of the magnitude at high frequencies,
nitude) for the circuit shown in Figure P3.5.8.
and also the half-power frequency.
3.5.9 A low-pass filter circuit is shown in Figure P3.5.9.
Copyright OUP
3.5.10 A high-pass filter circuit is shown in Figure F (s) with a zero at s = −400, a simple zero at
P3.5.10. Using a PSpice program and PROBE, s = −1000, a double pole at s = j 400, a double
obtain the Bode magnitude plot for the transfer pole at s = −j 400, and a value at s = 0 of
function H̄ (f ) = V̄out /V̄in for frequency ranging F (0) = 2 × 10−4 . Plot f (t).
from 10 Hz to 100 kHz. Determine the rate (in 3.6.4 Consider the circuit shown in Figure P3.6.4 in the
dB/decade) at which the magnitude falls off at low time domain as well as in the s-domain. Its transfer
frequencies, and also the half-power frequency. function V2 (s)/V1 (s) can be shown to be
3.5.11 A bandpass filter circuit is shown in Figure s/RC
T (s) = 2
P3.5.11. Develop a PSpice program and use s + s/RC + 1/LC
PROBE to obtain a Bode magnitude plot for the Ls/R
transfer function H̄ (f ) = V̄out /V̄in for frequency =
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
LCs 2 + (Ls/R) + 1
ranging from 1 Hz to 1 MHz. At what rate (in
dB/decade) does the magnitude fall off at low and which is a second-order bandpass transfer
√ function
high frequencies? Also determine the half-power with a center frequency at ω0 = 1/ LC. Using
frequencies. MATLAB, evaluate the straight-line and actual
gain response of the RLC circuit for the given
3.6.1 A periodic sequence of exponential wave forms
values.
forms a pulse train whose first cycle is repre-
sented by *3.6.5 Using MATLAB, plot the gain and phase response
of the transfer function
v(t) = [u(t) − u(t − T0 )]vA e−t/TC
5000(s + 100)
Use MATLAB to find V rms of the pulse train for T (s) = 2
s + 400s + (500)2
vA = 10 V, TC = 2 ms, and T0 = 5TC . 3.6.6 The dual situations of Figure E3.6.3 is shown in
3.6.2 Use MATLAB to obtain the Laplace transform of Figure P3.6.6, in which a high-pass and a low-
the waveform pass filter are connected in parallel to produce a
bandstop filter.
f (t) = [200te−25t + 10e−50t sin(25t)]u(t)
With ωCLP = 10 << ωCHP = 50, ω0 =
√
which consists of a damped ramp and a damped 10 × 50 = 22.4 rad/s, and
sine. Also show the pole–zero plot of the transform 1
F (s). TLP (s) = √
(s/10) + 2(s/10) + 1
2
3.6.3 With the use of MATLAB, find the expression for

(s/50)2
the waveform f (t) corresponding to a transform THP (s) = √
(s/50)2 + 2(s/50) + 1
1 R1 2 R2 3 Figure P3.5.9
+
200 Ω 200 Ω
__ + __
Vin 1 µF C1 C2 1 µF Vout
−
−
O
1 C1 2 C2 3 Figure P3.5.10
+
0.1 µF 0.1 µF
__ + __
Vin R1 2 kΩ R2 2 kΩ Vout
−
−
O
Copyright OUP
PROBLEMS 197
∞
the overall transfer function is given by VA VA 1
i(t) = +
TBS (s) = TLP (s) + THP (s) 2R R nπ 1 + (nω0 L/R)
2
n=1
Using MATLAB, plot the bandstop response. cos(nω0 t + 90° − θn )
3.6.7 An expression for a sawtooth wave over the in- where θn = tan−1 (nω0 L/R). With the parameters
ternal 0 ≤ t ≤ T0 is given by f (t) = At/T0 . VA = 25 V, T0 = 5 µs, ω0 = 2π/T0 , L = 40 µH,
The student is encouraged to check the Fourier and R = 50 -, by using MATLAB, plot truncated
coefficients to be a0 = A/2, an = 0 for all n, and Fourier series representations of i(t) using the dc
bn = −A/(nπ) for all n. The Fourier series for plus first 5 harmonics and the dc plus first 10
the sawtooth wave is then given by harmonics.
∞
A A Hint:
f (t) = + − sin (2πnt/T )
2 nπ VA VA 1
n=1 I0 = ; In = ;
2R R nπ 1 + (nω0 LR −1 )2
Using MATLAB, with A = 10 and T0 = 2 ms,
plot the truncated series representations of the θn = tan−1 (nω0 L/R)
waveform f (5, t), which is the sum of the dc com-
ponent plus the first 5 harmonics, and f (10, t),
k
f (k, t) = I0 + Im cos(mω0 t + 0.5π − θm )
which is the sum of the dc component plus the
m=1
first 10 harmonics.
Plot from t = 0 to 2 T0 with a time-step interval
3.6.8 The steady-state circuit i(t) in a series RL circuit of T0 /400.
due to a periodic sawtooth voltage is given by
R1 = 200 Ω C2 = 0.1 µF Figure P3.5.11

1 2 3
+
__ + __
Vin C1 10 µF R2 = 2 kΩ Vout
−
−
O
1.59 kΩ R
+ +
R
+ L C +
1
v1(t) 12 µH 10 nF v2(t) V1(s) Ls V2(s)
Cs
− −
− −
(a) (b)
Figure P3.6.4 (a) t-domain. (b) s-domain.
High-pass filter Figure P3.6.6 Bandstop filter through the parallel connec-
ωCHP >> ωCLP tion of high-pass and low-pass filters.
Low-pass filter
ωCLP
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
4 Three-Phase Circuits and
Residential Wiring
4.1 Three-Phase Source Voltages and Phase Sequence
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
4.2 Balanced Three-Phase Loads
4.3 Measurement of Power
4.4 Residential Wiring and Safety Considerations
4.6 Practical Application: A Case Study—Physiological Effects of Current and Electrical Safety
Problems
We shall conclude Part 1 of this book on electric circuits with a treatment of three-phase circuits,
an aspect of circuit theory important to the discussion of electric machines and to the bulk
transfer of electric energy. After explaining the phase sequence of three-phase source voltages,
balanced three-phase loads and power in three-phase circuits are considered. Then the elements
of residential wiring, including grounding and safety considerations, are presented. The chapter
ends with a case study of practical application.
The three-phase system is by far the most common polyphase system used for generation,
transmission, and heavy power utilization of ac electric energy because of its economic and
operating advantages. An ideal three-phase source generates three sinusoidal voltages of equal
amplitudes displaced from each other by an angle of 120° in time. The voltages generated by
the giant synchronous generators in power stations are practically sinusoidal with a frequency
of 60 Hz in the United States, or 50 Hz in the United Kingdom and many other countries. Even
though voltages and currents are sinusoidal, the power delivered to a balanced load is constant
for a three-phase system. The three-phase scheme of power transmission offers the advantages of
using the ac mode, constant power flow, and high power transfer capability.
4.1 THREE-PHASE SOURCE VOLTAGES AND PHASE SEQUENCE

The elementary three-phase, two-pole generator shown in Figure 4.1.1 has three identical stator
coils (aa , bb , and cc ) of one or more turns, displaced by 120° in space from each other. The
198
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4.1 THREE-PHASE SOURCE VOLTAGES AND PHASE SEQUENCE 199
rotor carries a field winding excited by the dc supply through brushes and slip rings. When the
rotor is driven at a constant speed, voltages of equal amplitude but different phase angle will be
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
generated in the three phases in accordance with Faraday’s law. Each of the three stator coils
constitutes one phase of this single generator. If the field structure is so designed that the flux is
distributed sinusoidally over the poles, the flux linking any phase will vary sinusoidally with time,
and sinusoidal voltages will be induced in the three phases. These three induced voltage waves
will be displaced by 120 electrical degrees in time because the stator phases are displaced by 120°
in space. When the rotor is driven counterclockwise, Figure 4.1.2(a) shows the wave forms and
Figure 4.1.2(b) depicts the corresponding phasors of the three voltages. The time origin and the
reference axis are chosen on the basis of analytical convenience. In a balanced system, all three
phase voltages are equal in magnitude but differ from each other in phase by 120°. The sequence
of voltages in Figure 4.1.2(b), corresponding to that of Figure 4.1.2(a), is known as the positive
sequence (a–b–c). On the other hand, if the rotor is driven clockwise, then Figure 4.1.2(c) shows
the corresponding phasor of the three voltages; the sequence of voltages in Figure 4.1.2(c) is
known as negative sequence (a–c–b). Notice that in positive sequence Ēbb lags Ēaa by 120°,
and Ēcc lags Ēbb by 120°; in negative sequence, however, Ēcc lags Ēaa by 120°, and Ēbb lags
Ēcc by 120°.
The stator phase windings may be connected in either wye (also known as star or symbolically
represented as Y) or delta (also known as mesh or symbolically represented as ?), as shown
schematically in Figure 4.1.3. Almost all ac generators (otherwise known as alternators) have
their stator phase windings connected in wye. By connecting together either all three primed
terminals or all three unprimed terminals to form the neutral of the wye, a wye connection
results. If a neutral conductor is brought out, the system is known as a four-wire, three-phase
system; otherwise it is a three-wire, three-phase system. A delta connection is effected for the
armature of the generator by connecting terminals a to b, b to c, and c to a. The generator
terminals A, B, C (and sometimes N for a wye connection) are brought out as shown in Figure
4.1.3. In the delta-connection, no neutral exists, and hence only a three-wire, three-phase system
can be formed. Note that a phase is one of the three branch circuits making up a three-phase circuit.
In a wye connection, a phase consists of those circuit elements connected between one line and
neutral; in a delta circuit, a phase consists of those circuit elements connected between two lines.
A-Phase Figure 4.1.1 Elementary three-phase, two-

pole ac generator.
a Armature
or
Field stator
systen
or rotor
c′ b′
N S
Field
winding Armature
b c Coil sides
Rotation
a′
Copyright OUP
200 THREE-PHASE CIRCUITS AND RESIDENTIAL WIRING
Volts Figure 4.1.2 (a) Waveforms in

time domain. (b) Positive-
sequence (a–b–c) phasors. (c) Ne-
eaa′ ebb′ ecc′ gative-sequence (a–c–b) phasors.
0 ωt
120° 240°
(a)
a a
Eaa′ Eaa′
120° 120°
a′ b′ a′ b′
c′ c′
Ecc′ Ebb′
Ebb′ Ecc′
c 120° b b 120° c
(b) (c)
From the nature of the connections shown in Figure 4.1.3 it can be seen that the line-to-line
voltages (VL-L or VL) are equal to the phase voltage V ph for the delta connection, and the line
current is equal to the phase current for the wye connection. A balanced wye-connected three-
phase source and its associated phasor diagram √ are shown in Figure 4.1.4, from which it can be
seen that the line-to-line voltage is equal to 3 times the phase voltage (or the line-to-neutral
voltage). The student should be able to reason on similar lines and conclude
√ that, for the balanced
delta-connected three-phase source, the line current will be equal to 3 times the phase current.
The notation using subscripts is such that VAB is the potential at point A with respect
to point B, IAB is a current with positive flow from point A to point B, and IA, IB, and IC
are line currents with positive flow from the source to the load, as shown in Figure 4.1.5.
The notation used is rather arbitrary. In some textbooks a different notation for the voltage
is adopted such that the order of subscripts indicates the direction in which the voltage rise
is taken. The student should be careful not to get confused, but try to be consistent with
any conventions chosen. The rms values are usually chosen as magnitudes of the phasors
for convenience. It is customary to use the letter symbol E for generated emf and V for
terminal voltage. Sometimes the two are equal, but sometimes not. If we should neglect the
existence of the generator winding impedance, the generated emf will be equal to the terminal
voltage of the generator. Although the three-phase voltages are generated in one three-phase
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
alternator, for analytical purposes this is modeled by three identical, interconnected, single-
phase sources.
The one-line equivalent circuit of the balanced wye-connected three-phase source is shown
in Figure 4.1.4(c). The line-to-neutral (otherwise known as phase) voltage is used; it may be taken
Copyright OUP
4.1 THREE-PHASE SOURCE VOLTAGES AND PHASE SEQUENCE 201
IL IL
A A
Iph
a
c′
Iph VL−L
Vph a c
VL−L C
a′
b′
N a′
b′ n c′
b
b c
B
C
B VL−L = Vph
IL = 3 Iph
VL−L = 3 Vph (b)
IL = Iph
(a)
Figure 4.1.3 Schematic representation of generator windings. (a) Balanced wye connection. (b) Balanced
delta connection.
as a reference with a phase angle of zero for convenience. This procedure yields the equivalent
single-phase circuit in which all quantities correspond to those of one phase in the three-phase
circuit. Except for the 120° phase displacements in the currents and voltages, the conditions in
the other two phases are the same, and there is no need to investigate them individually. Line
currents in the three-phase system are the same as in the single-phase circuit, and total three-phase
real power, reactive power, and volt-amperes are three times the corresponding quantities in the
single-phase circuit. Line-to-line
√ voltages, in magnitude, can be obtained by multiplying voltages
in the single-phase circuit by 3.
When a system of sources is so large that its voltage and frequency remain constant regardless
of the power delivered or absorbed, it is known as an infinite bus. Such a bus has a voltage and
a frequency that are unaffected by external disturbances. The infinite bus is treated as an ideal
voltage source.
Phase Sequence
It is standard practice in the United States to designate the phase A–B–C such that under balanced
conditions the voltage and current in the A-phase lead in time the voltage and current in the
B-phase by 120° and in the C-phase by 240°. This is known as positive phase sequence A–B–C.
The phase sequence should be observed either from the waveforms in the time domain shown in
Figure 4.1.2(a) or from the phasor diagrams shown in Figure 4.1.2(b) or 4.1.4(b), and not from
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
space or schematic diagrams, such as Figures 4.1.3 and 4.1.4(a). If the rotation of the generator
of Figure 4.1.1 is reversed, or if any two of the three leads from the armature (not counting the
neutral) to the generator terminals are reversed, the phase sequence becomes A–C–B (or C–B–A
or B–A–C), which is known as negative phase sequence.
Only the balanced three-phase sources are considered in this chapter. Selection of one
voltage as the reference with a phase angle of zero determines the phase angle of all the other
voltages in the system for a given phase sequence. As indicated before, the reference phasor
is chosen arbitrarily for convenience. In Figure 4.1.4(b), V̄BC is the reference phasor, and with
the counterclockwise rotation (assumed positive) of all the phasors at the same frequency, the
Copyright OUP
VCA VAN VAB

N
VBN
VCN
C VBC B
a A
V
+ VBC = VL ∠0° (Ref.) VAN = L3 ∠90°
ean V
VAB = VL ∠120° VBN = L3 ∠−30°
−
n V
ebn − − ecn N VCA = VL ∠240° VCN = L3 ∠−150°
+ + (b)
b c C
B
(a)
Vph
IL
or
Bus
VL−N
(c)
Figure 4.1.4 (a) Balanced wye-connected, three-phase source. (b) Phasor diagram for three-phase source
(sequence ABC). Note that such relations as V̄AB = V̄AN + V̄N B are satisfied; also V̄AN + V̄BN + V̄CN = 0;
V̄AB + V̄BC + V̄CA = 0. (c) Single-line equivalent circuit.
sequence can be seen to be A–B–C. Unless otherwise mentioned, the positive phase sequence is
to be assumed.
4.2 BALANCED THREE-PHASE LOADS

Three-phase loads can be connected in either wye (also known as star or Y) or delta (otherwise
known as mesh or ?). If the load impedances in each of the three phases are the same in both
magnitude and phase angle, the load is said to be balanced.
For the analysis of network problems, transformations for converting a delta-connected
network to an equivalent wye-connected network and vice versa will be found to be useful.
The relationships for interconversion of wye and delta networks are given in Figure 4.2.1. These
are similar to those given in Section 2.4 for resistive network reduction. They can be obtained
by imposing the condition of equivalence that the impedance between any two terminals for
one network be equal to the corresponding impedance between the same terminals for the other
network. The details are left as a desirable exercise for the student. For the balanced case, each
wye impedance is one-third of each delta impedance; conversely, each delta impedance is three
times each wye impedance.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
4.2 BALANCED THREE-PHASE LOADS 203
IAB
VAB VBA A B
IBA
IA
A A
IB
Source B B Load
IC
C C
Figure 4.1.5 Notation using subscripts.
Balanced Wye-Connected Load

Let us consider a three-phase, four-wire 208-V supply system connected to a balanced wye-
connected load with an impedance of 10 20° -, as shown in Figure 4.2.2(a). We shall solve for
the line currents and draw the corresponding phasor diagram.
Conventionally it is assumed that 208 V is the rms value of the line-to-line voltage of the
supply system, and the phase sequence is positive, or A–B–C, unless√mentioned otherwise. The
magnitude of the line-to-neutral (or phase) voltages is given by 208/ 3, or 120 V. Selecting the
line currents returning through the neutral conductor, as shown in Figure 4.2.2, we have
√
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
¯ V̄AN (208/ 3) 90°
IA = = = 12 70° (4.2.1)
Z̄ 10 20°
√
V̄BN (208/ 3) − 30°
I¯B = = = 12 −50° (4.2.2)
Z̄ 10 20°
√
¯ V̄CN (208/ 3) − 150°
IC = = = 12 −170° (4.2.3)
Z̄ 10 20°
Note that V̄BC has been chosen arbitrarily as the reference phasor, as in Figure 4.1.4(b). Assuming
the direction of the neutral current toward the load as positive, we obtain

I¯N = − I¯A + I¯B + I¯C
= − (12 70° + 12 − 50° + 12 170°) = 0 (4.2.4)
That is to say that the system neutral and the star point of the wye-connected load are at the same
potential, even if they are not connected together electrically. It makes no difference whether they
are interconnected or not.
Thus, for a balanced wye-connected load, the neutral current is always zero. The line currents
and phase currents are equal in magnitude, and the line currents
√ are in phase with the corresponding
phase currents. The line-to-line voltages, in magnitude, are 3 times the phase voltages, and the
phase voltages lag the corresponding line voltages by 30°.
The phasor diagram is drawn in Figure 4.2.2(b), from which it can be observed that the
balanced line (or phase) currents lag the corresponding line-to-neutral voltages by the impedance
Copyright OUP
Y–∆ transformation A ZAB B ∆–Y transformation
ZA ZB + Z BZC + Z C ZA ZABZCA
ZAB = ZA ZA =
ZC ZB ZAB + ZBC + ZCA
Z Z + Z BZC + Z C ZA ZABZBC
ZBC = A B ZB =
ZA ZAB + ZBC + ZCA
Z CA
C
ZB
Z Z + Z BZC + Z C ZA ZC ZCAZBC
ZCA = A B ZC =
ZB ZAB + ZBC + ZCA
For the balanced case, For the balanced case,
ZAB = ZBC = ZCA = Z∆ = 3ZY ZA = ZB = ZC = ZY = 13 Z∆
C
Figure 4.2.1 Wye–delta and delta–wye transformations.
angle (20° in our example). The load power factor is given by cos 20° for our problem, and it is
said to be lagging in this case, as the impedance angle is positive and the phase current lags the
corresponding phase voltage by that angle.
The problem can also be solved in a simpler way by making use of a single-line equivalent
circuit, as shown in Figure 4.2.2.(c),
√
¯ V̄L−N (208/ 3) 0°
IL = = = 12 − 20° (4.2.5)
Z̄ 10 20°
in which V̄L−N is chosen as the reference for convenience. The magnitude of the line current
and the power factor angle are known; the negative sign associated with the angle indicates that
the power factor is lagging. By knowing that the line (or phase) currents I¯A , I¯B , I¯C lag their
respective voltages V̄AN , V̄BN , and V̄CN by 20°, the phase angles of various voltages and currents,
if desired, can be obtained with respect to any chosen reference, such as V̄BC .
Balanced Delta-Connected Load

Next, let us consider the case of a balanced delta-connected load with impedance of 5 45° -
supplied by a three-phase, three-wire 100-V system, as shown in Figure 4.2.3(a). We shall
determine the line currents and draw the corresponding phasor diagram.
With the assumed positive phase sequence (A–B–C) and with V̄BC as the reference phasor,
the line-to-line voltages V̄AB , V̄BC , and V̄CA are shown in Figure 4.2.3. The rms value of the
line-to-line voltages is 100 V for our example. Choosing the positive directions of the line and
phase currents as in Figure 4.2.3(a), we have
V̄AB 100 120°
I¯AB = = = 20 75° (4.2.6)
Z̄ 5 45°
V̄BC 100 0°
I¯BC = = = 20 − 45° (4.2.7)
Z̄ 5 45°
V̄CA 100 240°
I¯CA = = = 20 195° (4.2.8)
Z̄ 5 45°
By the application of Kirchhoff’s current law at each of the vertices of the delta-connected
load, we obtain
I¯A = I¯AB + I¯AC = 20 75° − 20 195° = 34.64 45° (4.2.9)
I¯B = I¯BA + I¯BC = −20 75° + 20 − 45° = 34.64 − 75° (4.2.10)
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IA
A
VAN = 120 ∠90° Z 10 ∠ + 20° Ω
IA
IN
N
IB
10 ∠ + 20° Ω
VBN = 120 ∠−30° Z Z
IB
B 10 ∠ + 20° Ω
VCN = 120 ∠−150°

IC
IC
C
(a)
Direction of rotation of phasors

VAB V
VAN = AB ∠−30°
VAN 3
VBC
30° 20° I VBN = ∠−30°
A −VCN = VNC 3
60° V
VCN = CA ∠−30°
−VBN = VNB 3
70° VBC
IC
20° 20°
VBN
|VAN| = |VBN| = |VCN| = VL−N = Vph
VCN
IB |VAB| = |VBC| = |VCA| = VL−L = 3Vph
|IA| = |IB| = |IC| = IL = Iph
VCA −VAN = VNA IN = 0
IL
(b)
Z
VL−N∠0°
Reference
(c)
Figure 4.2.2 Balanced wye-connected load. (a) Connection diagram. (b) Phasor diagram. (c) Single-line
equivalent circuit.
I¯C = I¯CA + I¯CB = 20 195° − 20 − 45° = 34.64 165° (4.2.11)
The phasor diagram showing the line-to-line voltages, phase currents, and line currents is drawn
in Figure 4.2.3(b). The load power factor is lagging, and is given by cos 45°.
For a balanced delta-connected load, the phase voltages and the line-to-line voltages are
equal in magnitude, and the line voltages are in phase with the corresponding phase voltages.
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Copyright OUP
ICA
IA
A
IAB
VAB = 100 ∠120°
Z 5 ∠45° Ω Z
VCA = 100 ∠240°
5 ∠45° Ω
5 ∠45° Ω
IB
B Z
VBC = 100 ∠0°

IBC
IC
C
(a)
VAB Direction of rotation of phasors
IA
|VAB| = |VBC| = |VCA| = VL−L = Vph
IAB
|IAB| = |IBC| = |ICA| = Iph
45° |IA| = |IB| = |IC| = IL = 3Iph
30°
45° IA = 3 IAB ∠−30°
IC 30°
IB = 3 IBC ∠−30°
IAC IC = 3 ICA ∠−30°
VBC
45°
ICA
45° ∆
IBC IL
ZY 5 ∠45° Ω
3
VL−N = 100 ∠0°
3
IB
VCA
(b) (c)
Figure 4.2.3 Balanced delta-connected load. (a) Connection diagram. (b) Phasor diagram. (c) Single-line
equivalent circuit.
√
The line currents, in magnitude, are 3 times the phase currents, and the phase currents lead the
corresponding line currents by 30°.
The preceding example can also be solved by the one-line equivalent method for which the
delta-connected load is replaced by its equivalent wye-connected load. The single-line equivalent
circuit is shown in Figure 4.2.3(c). The details are left as an exercise for the student.
Power in Balanced Three-Phase Circuits

The total power delivered by a three-phase source, or consumed by a three-phase load, is found
simply by adding the power in each of the three phases. In a balanced circuit, however, this is
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the same as multiplying the average power in any one phase by 3, since the average power is the
same for all phases. Thus one has
P = 3 Vph Iph cos φ (4.2.12)
where V ph and I ph are the magnitudes of any phase voltage and phase current, cos φ is the load
power factor, and φ is the power factor angle between the phase voltage V̄ph and the phase current
I¯ph corresponding to any phase. In view of the relationships between the line and phase quantities
for balanced wye- or delta-connected loads, Equation (4.2.12) can be rewritten in terms of the
line-to-line voltage and the line current for either wye- or delta-connected balanced loading as
follows:
√
P = 3 VL IL cos φ (4.2.13)
where VL and IL are the magnitudes of the line-to-line voltage and the line current. φ is still the
load power factor angle as in Equation (4.2.12), namely, the angle between the phase voltage and
the corresponding phase current.
In a balanced three-phase system, the sum of the three individually pulsating phase powers
adds up to a constant, nonpulsating total power of magnitude three times the average real
power in each phase. That is, in spite of the sinusoidal nature of the voltages and currents,
the total instantaneous power delivered into the three-phase load is a constant, equal to the
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total average power. The real power P is expressed in watts when voltage and current are
expressed in volts and amperes, respectively. You may recall that the instantaneous power in
single-phase ac circuits absorbed by a pure inductor or capacitor is a double-frequency sinusoid
with zero average value. The instantaneous power absorbed by a pure resistor has a nonzero
average value plus a double-frequency term with zero average value. The instantaneous reactive
power is alternately positive and negative, indicating the reversible flow of energy to and
from the reactive component of the load. Its amplitude or maximum value is known as the
reactive power.
The total reactive power Q (expressed as reactive volt-amperes, or VARs) and the volt-
amperes for either wye- or delta-connected balanced loadings are given by
Q = 3 Vph Iph sin φ (4.2.14)

or
√
Q= 3 VL IL sin φ (4.2.15)
and
* * √
S = *S̄ * = P 2 + Q2 = 3 Vph Iph = 3 VL IL (4.2.16)
where the complex power S̄ is given by

S̄ = P + j Q (4.2.17)
In speaking of a three-phase system, unless otherwise specified, balanced conditions are

assumed. The terms voltage, current, and power, unless otherwise identified, are conventionally
understood to imply the line-to-line voltage (rms value), the line current (rms value), and the total
power of all three phases. In general, the ratio of the real or average power P to the apparent
power or the magnitude of the complex power S is the power factor, which happens to be cos φ
in the sinusoidal case.
Copyright OUP
EXAMPLE 4.2.1
(a) A wye-connected generator is to be designed to supply a 20-kV three-phase line. Find
the terminal line-to-neutral voltage of each phase winding.
(b) If the windings of the generator of part (a) were delta-connected, determine the output
line-to-line voltage.
(c) Let the 20-kV generator of part (a) supply a line current of 10 A at a lagging power factor
of 0.8. Compute the kVA, kW, and kVAR supplied by the alternator.
Solution
√
(a) VL−N = Vph = 20/ 3 = 11.547 kV
(b) VL = Vph = 11.547 kV
√
(c) kVA = 3 (20)(10) = 346.4
kW = 346.4(0.8) = 277.12
kVAR = 346.4(0.6) = 207.84
4.3 MEASUREMENT OF POWER

A wattmeter is an instrument with a potential coil and a current coil so arranged that its
deflection is proportional to VI cos θ , where V is the voltage (rms value) applied across
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the potential coil, I is the current (rms value) passing through the current coil, and θ is the
angle between V̄ and I¯. By inserting such a single-phase wattmeter to measure the average
real power in each phase (with its current coil in series with one phase of the load and its
potential coil across the phase of the load), the total real power in a three-phase system can
be determined by the sum of the wattmeter readings. However, in practice, this may not be
possible due to the nonaccessibility of either the neutral of the wye connection, or the individual
phases of the delta connection. Hence it is more desirable to have a method for measuring
the total real power drawn by a three-phase load while we have access to only three line
terminals.
The three-phase power can be measured by three single-phase wattmeters having current coils
in each line and potential coils connected across the given line and any common junction. Since
this common junction is completely arbitrary, it may be placed on any one of the three lines, in
which case the wattmeter connected in that line will indicate zero power because its potential coil
has no voltage across it. Hence, that wattmeter may be dispensed with, and three-phase power can
be measured by means of only two single-phase wattmeters having a common potential junction
on any of the three lines in which there is no current coil. This is known as the two-wattmeter
method of measuring three-phase power. In general, m-phase power can be measured by means
of m − 1 wattmeters. The method is valid for both balanced and unbalanced circuits with either
the load or the source unbalanced.
Figure 4.3.1 shows the connection diagram for the two-wattmeter method of measuring three-
phase power. The total real power delivered to the load is given by the algebraic sum of the two
wattmeter readings,
P = WA + WC (4.3.1)
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4.3 MEASUREMENT OF POWER 209
Single-phase
Current coil
wattmeter WA
+
−
A
+
−
Potential coil Three-phase

B load
+
−
C +
−
Single-phase
wattmeter WC
Figure 4.3.1 Connection diagram for two-wattmeter method of measuring three-phase power.
The significance of the algebraic sum will be realized in the paragraphs that follow. Two wattmeters
can be connected with their current coils in any two lines, while their potential coils are connected
to the third line, as shown in Figure 4.3.1. The wattmeter readings are given by
WA = VAB · IA · cos θA (4.3.2)
where θA is the angle between the phasors V̄AB and I¯A , and
WC = VCB · IC · cos θC (4.3.3)
where θC is the angle between the phasors V̄CB and I¯C .
The two-wattmeter method, when applied to the balanced loads, yields interesting results.
Considering either balanced wye- or delta-connected loads, with the aid of the corresponding
phasor diagrams drawn earlier for the phase sequence A–B–C (Figures 4.2.2. and 4.2.3), it can be
seen that the angle between V̄AB and I¯A is (30° + φ) and that between V̄CB and I¯C is (30 − φ),
where φ is the load power factor angle, or the angle associated with the load impedance. Thus,
we have
WA = VL IL cos (30° + φ) (4.3.4)
and
WC = VL IL cos (30° − φ) (4.3.5)
where VL and IL are the magnitudes of the line-to-line voltage and line current, respectively.
Simple manipulations yield
√
WA + WC = 3 VL IL cos φ (4.3.6)
and
WC − WA = VL IL sin φ (4.3.7)
from which,
√ WC − WA
tan φ = 3 (4.3.8)
WC + W A
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Copyright OUP
When the load power factor is unity, corresponding to a purely resistive load, both wattmeters
will indicate the same wattage. In fact, both of them should read positive; if one of the wattmeters
has a below-zero indication in the laboratory, an upscale deflection can be obtained by simply
reversing the leads of either the current or the potential coil of the wattmeter. The sum of the
wattmeter readings gives the total power absorbed by the load.
At zero power factor, corresponding to a purely reactive load, both wattmeters will again
have the same wattage indication but with the opposite signs, so that their algebraic sum will
yield zero power absorbed, as it should. The transition from a negative to a positive value occurs
when the load power factor is 0.5 (i.e., φ is equal to 60°). At this power factor, one wattmeter
reads zero while the other one reads the total real power delivered to the load.
For power factors (leading or lagging) greater than 0.5, both wattmeters read positive, and the
sum of the two readings gives the total power. For a power factor less than 0.5 (leading or lagging),
the smaller reading wattmeter should be given a negative sign and the total real power absorbed by
the load (which has to be positive) is given by the difference between the two wattmeter readings.
Figure 4.3.2 shows a plot of the load power factor versus the ratio Wl /Wh, where Wl and Wh are
the lower and higher readings of the wattmeters, respectively.
Another method that is sometimes useful in a laboratory environment for determining
whether the total power is the sum or difference of the two wattmeter readings is described
here. To begin, make sure that both wattmeters have an upscale deflection. To perform the
test, remove the lead of the potential coil of the lower reading wattmeter from the common
line that has no current coil, and touch the lead to the line that has the current coil of the
higher reading wattmeter. If the pointer of the lower reading wattmeter deflects upward, the
two wattmeter readings should be added; if the pointer deflects in the below-zero direction, the
wattage reading of the lower reading wattmeter should be subtracted from that of the higher
reading wattmeter.
Given the two wattmeter readings from the two-wattmeter method used√on a three-phase
balanced load, it is possible to find the tangent of the phase impedance angle as 3 times the ratio
of the difference between the two wattmeter readings and their sum, based on Equation (4.3.8).
If one knows the system sequence and the lines in which the current coils of the wattmeters are
located, the sign for the angle can be determined with the aid of the following expressions. For
sequence A–B–C,
√ WC − WA √ WA − WB √ WB − WC
tan φ = 3 = 3 = 3 (4.3.9)
WC + W A WA + W B WB + W C
and for sequence C–B–A,
Figure 4.3.2 Plot of load power

Power factor lead or lag
factor versus Wl /Wh.

1.0
0.8
0.6
0.5
0.4
0.2
−1.0 −0.75 −0.50 −0.25 0 +0.25 +0.5 +0.75 +1.0

Wl
Wh
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4.3 MEASUREMENT OF POWER 211
√ WA − WC √ WB − WA √ WC − WB
tan φ = 3 = 3 = 3 (4.3.10)
WA + W C WB + W A WC + W B
The two-wattmeter method discussed here for measuring three-phase power makes use of
single-phase wattmeters. It may be noted, however, that three-phase wattmeters are also available,
which, when connected appropriately, indicate the total real power absorbed. The total reactive
power associated with the three-phase balanced load is given by
√ √
Q = 3 VL IL sin φ = 3 (WC − WA ) (4.3.11)
based on the two wattmeter readings of the two-wattmeter method.
With the generator action of the source assumed, +P for the real power indicates that the
source is supplying real power to the load; +Q for the reactive power shows that the source is
delivering inductive VARs while the current lags the voltage (i.e., the power factor is lagging); and
−Q for the reactive power indicates that the source is delivering capacitive VARs or absorbing
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inductive VARs, while the current leads the voltage (i.e., the power factor is leading).
EXAMPLE 4.3.1
Considering
√ Figure 4.3.1, let balanced positive-sequence, three-phase voltages with V̄AB =
100 3 0° V (rms) be applied to terminals A, B, and C. The three-phase wye-connected balanced
load consists of a per-phase impedance of (10 + j 10)-. Determine the wattmeter readings of
WA and WC. Then find the total three-phase real and reactive powers delivered to the load. Based
on the wattmeter readings of WA and WC , compute the load power factor and check the sign
associated with the power factor angle.
Solution
√ √ √
V̄AB = 100 3 0° V; V̄BC = 100 3 − 120°; V̄CA = 100 3 120°
V̄AN = 100 − 30° V; V̄BN = 100 − 150°; V̄CN = 100 90°
V̄AN 100 − 30° √

I¯A = = √ = 5 2 − 75° A (rms)
Z̄ 10 2 45°
V̄CN 100 90° √
I¯C = = √ = 5 2 45° A (rms)
Z̄ 10 2 45°
The load power factor angle φ = 45°, and it is a case of lagging power factor with the inductive
load.
√ √
WA = VAB IA cos (30° + φ) = 100 3 5 2 cos 75° = 317 W
√ √
WC = VCB IC cos (30° − φ) = 100 3 5 2 cos 15° = 1183 W
The total three-phase real power delivered to the load
WA + WC = 317 + 1183 = 1500 W
which checks with
√ √ √ √
3 VL IL cos φ = 3 100 3 5 2 cos 45° = 1500 W
Copyright OUP
The total three-phase reactive power delivered to the load is

√ √
3(WC − WA ) = 3(1183 − 317) = 1500 VAR
which checks with
√ √ √ √
3VL IL sin φ = 3(100 3)(5 2) sin 45° = 1500 VAR
For positive-sequence A–B–C,

√ WC − WA √ 1183 − 317
tan ∅ = 3 = 3 = 1.0
WC + W A 1183 + 317
or ∅ = 45° with a positive sign, implying thereby that it corresponds to an inductive or lagging
load, which checks with the given load specification. The load power factor is given by
cos ∅ = 0.707
and is lagging in this case.
4.4 RESIDENTIAL WIRING AND SAFETY CONSIDERATIONS

Residential electric power service commonly consists of a three-wire ac system supplied by the
local power company. A distribution transformer with a primary and two secondaries formed with
a center tap on the secondary side, as illustrated in Figure 4.4.1, is located on a utility pole, from
which three wires originate. Two of them are known as “hot” wires, while the third is called a
neutral wire, which is connected to earth ground. In accordance with standard insulation color
codes, “hot” wires are denoted by either B (black) or R (red), neutral by W (white), and ground
(or uninsulated wire) by G (green). The functional difference between neutral and ground wires
will be brought out later when considering circuit wiring.
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Domestic loads consisting of 120-V appliances and lighting, divided nearly equally between
the two 120-V (rms) secondaries, are connected from hot wires to neutral. Appliances such as
electric ranges and water heaters are supplied with 240-V (rms) power from the series-connected
secondaries, as shown in Figure 4.4.1.
Minimizing the power loss in the lines (known as I2R loss) is important from the viewpoint
of efficiency and reducing the amount of heat generated in the wiring for safety considerations.
Since the power loss in the lines is directly related to the current required by the load, a lower
line loss will be incurred with the 240-V wiring in delivering the necessary power to a load. For
the lower voltage case, however, the size of the wires is increased, thereby reducing the wire
resistance, in an effort to minimize line losses. Problem 4.4.2 deals with these considerations.
Hot
B (Black)
120-V
120 V appliances
Neutral 240-V
2400 V appliances 240 V
(white) W
120-V
Earth 120 V appliances
ground
R (Red)
Primary Secondaries Hot
Figure 4.4.1 Three-winding distribution transformer providing dual-voltage ac supply.
Copyright OUP
4.4 RESIDENTIAL WIRING AND SAFETY CONSIDERATIONS 213
The three-line cable coming out of the secondaries of the distribution transformer on the
utility pole passes through the electric meter that measures energy consumption in kilowatt-hours
and terminates at the main panel. Figure 4.4.2 shows a typical wiring arrangement for a residence.
At the main panel, circuit breakers serve the joint role of disconnecting switches and overcurrent
protection; the neutral is connected to a busbar (bus) and in turn to the local earth ground; the hot
lines are connected to individual circuits for lighting and appliances, as illustrated in Figure 4.4.2.
The circuit breaker labeled GFCI (ground-fault circuit interruption), used for safety primarily
with outdoor circuits and in bathrooms, has additional features that will be described later. Note
that every outgoing “hot” wire must be connected to a circuit breaker, whereas every neutral wire
and ground wire must be tied directly to earth ground at the neutral busbar.
Today most homes have three-wire connections to their outlets, one of which is shown in
Figure 4.4.3. The need for both ground and neutral connections needs to be explained, since the
ground conductor may appear to be redundant, playing no role in the actual operation of a load that
might be connected to the receptacle. From the viewpoint of safety, the ground connection is used
to connect the metallic chassis of the appliance to earth ground. Without the ground conductor
connected to the metal case of the appliance, as shown in Figure 4.4.4(a), the appliance chassis
could be at any potential with respect to ground, possibly even at the “hot” wire’s potential if a part
of the “hot” wire were to lose some insulation and come in contact with the inside of the chassis.
An unintended connection may occur because of the corrosion of insulation or a loose mechanical
connection. Poorly grounded appliances can thus be a significant hazard by providing a path to
ground through the body of a person touching the chassis with a hand. An undersized ground
loop current limited by the body resistance may flow directly through the body to ground and
could be quite harmful. Typically, the circuit breaker would not operate under such circumstances.
R B W Neutral busbar (bus)

Main
breaker
Earth ground
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Bus R Bus B W
20 A G Basement lighting
B (120-V circuit)
W
20 A G Bedroom lighting
B (120-V circuit)
W
20 A G Kitchen appliances
B (120-V circuit)
20 A
B
W or G Electric stove
(240-V circuit)
20 A GFCI R
R Outdoor
15 A W lighting
(120-V circuit
G with GFCI)
Figure 4.4.2 Typical wiring arrangement for a residence Note: Currents

and voltages shown are rms magnitudes.
Copyright OUP
However, if the ground conductor is present and properly connected to the chassis of the appliance,
as shown in Figure 4.4.4(b), the metal case will remain at ground potential or, at worst, a few
volts from ground if a fault results in current through the ground wire. The “hot” conductor may
be shorted to ground under fault conditions, in which case the circuit breaker would operate.
The body resistance of a normal person ranges from 500 k- down to 1 k-, depending upon
whether the skin is dry or wet. Thus, a person with wet skin risks electrocution from ac voltages
as low as 100 V. The amount of current is the key factor in electric shock, and Table 4.4.1 lists
the effects of various levels of 60-Hz ac current on the human body. Note that the 100–300-mA
range turns out to be the most dangerous.
The best possible shock protection is afforded by the ground-fault circuit interrupter (GFCI)
shown in Figure 4.4.4(c). A sensing coil located around the “hot” and neutral wires in the GFCI
detects the imbalance of currents between the neutral and the live conductor under fault conditions
and opens the circuit in response when |IB − IW | > 5 mA. The GFCI may be located either at
an outlet or at the main panel. Ground-fault interrupters are now required in branch circuits that
serve outlets in areas such as bathrooms, basements, garages, and outdoor sites.
Various codes, such as the National Electrical Code, have been established to provide
protection of personnel and property, while specifying requirements for the installation and
maintenance of electrical systems. Only qualified and properly certified persons should undertake
installation, alteration, or repair of electrical systems. Safety when working with electric power
must always be a primary consideration. In addition to numerous deaths caused each year due
to electrical accidents, fire damage that results from improper use of electric wiring and wiring
faults amounts to millions of dollars per year.
Finally, Figure 4.4.5 illustrates how a device, such as a light, can be controlled independently
from two different locations using single-pole double-throw (SPDT) switches, commonly known
as three-way switches or staircase switches. When the “hot” wire is switched between two
“travelers” at the first switch and from the travelers to the device at the second, a complete
circuit is formed only when both switches are either up or down; flipping either switch opens the
circuit. Note that neutral and ground wires are never switched.
120 V Figure 4.4.3 Three-wire outlet. Note: Currents

I are shown with rms magnitudes for normal-load
operation.
Neutral Hot
(white wire) I (black or red wire)
0
Ground (green or uninsulated bare wire)
TABLE 4.4.1 Effects of 60-Hz ac Current on Human Body
Range of Current Physiological Effects
1–5 mA Threshold of sensation

10–20 mA Involuntary muscle contractions; pain; “can’t let go” condition
20–100 mA Breathing difficulties; severe pain
100–300 mA Ventricular fibrilation; possible death with no intervention
300–500 mA Respiratory paralysis (heartbeat may stop and may restart if shock is removed before death)
1–10 A Severe burns; temporary heart contraction (not fatal unless vital organs are burned)
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Copyright OUP
Metallic chassis
B
+ Unintended connection
(wiring fault)
120 V Load
W
−
120 V ?
(a)
Metallic chassis
B
(wiring fault)
120 V Load
W
−
G IG
(b)
IB Metallic chassis
B
Sensing coil IW (wiring fault)
120 V GFCI
Load
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W
−
G
(c)
Figure 4.4.4 Appliance with wiring fault. Note: Currents and voltages
shown are rms magnitudes. (a) Ungrounded chassis. (b) Grounded chassis.
(c) Grounded chassis with GFCI in circuit.

• Phase sequence of balanced three-phase voltages and currents.
• Wye–delta and delta–wye conversions for networks containing impedances.
• Circuit analysis with balanced three-phase source and balanced wye-connected load.
• Circuit analysis with balanced three-phase source and balanced delta-connected load.
Copyright OUP
Travelers Figure 4.4.5 Three-way

switch connections to operate a
B device.
SPDT SPDT
W
G
3-way switch #1 3-way switch #2
• Real, reactive, and apparent powers in three-phase circuits.

• Measurement of three-phase power by two single-phase wattmeters.
• Basic notions of residential circuit wiring, including grounding and safety considerations.
Physiological Effects of Current and Electrical Safety

Various effects that electric current may have on the human body and the current levels at which
they occur are illustrated in Figure 4.6.1. Note that small currents can have serious effects. The
ranges in Figure 4.6.1, however, represent variations among individuals in body size, condition,
and tolerance to electric shock. The region of the body through which the current passes is crucial.
The current can easily be estimated by the application of Ohm’s law,
I = V /R
where R is the resistance of the circuit of which a person’s body might become a part. Most serious
electric shocks occur where a person is in simultaneous contact with the so-called hot wire and
the ground. Ground may be the dry or moist earth, the plumbing of a house, or even a concrete
floor that is connected to the plumbing. The circuit resistance would include not only the body
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Sustained myocardial
contraction
Burns, injury
Ventricular fibrillation
Respiratory paralysis, fatigue, pain
Let-go current
Threshold of
perception
1 mA 10 mA 100 mA 1A 10 A 100 A
Figure 4.6.1 Physiological effects of electricity. (Adapted from J. G. Webster, Medical Instrumentation,
Application and Design, Houghton Mifflin, 1978.)
Copyright OUP
TABLE 4.6.1 Resistance Estimates for Various Skin-Contact Conditions
Resistance
Condition Dry Wet
Finger touch 40 k-–1000 k- 4–15 k-

Hand holding wire 15–50 k- 3–6 k-
Finger–thumb grasp 10–30 k- 2–5 k-
Hand holding pliers 5–10 k- 1–3 k-
Palm touch 3–8 k- 1–2 k-
Hand around 1 21 -in pipe (or drill handle) 1–3 k- 0.1–1.5 k-
Two hands around 1 21 -in pipe 0.5–1.5 k- 250–750 -
Hand immersed 200–500 -
Foot immersed 100–300 -
Human body, internal
excluding skin, 200–1000 -
Adapted from R. Lee, “Electrical Safety in Industrial Plants,” IEEE Spectrum (June 1971).
TABLE 4.6.2 Resistance Estimates for Equal Areas (130 cm2)

of Various Materials
Material Resistance
Rubber gloves or soles >20 M-

Dry concrete above grade 1–5 M-
Dry concrete on grade 0.2–1 M-
Leather sole, dry, including foot 0.1–0.5 M-
Leather sole, damp, including foot 5–20 k-
Wet concrete on grade 1–5 k-
Adapted from R. Lee, “Electrical Safety in Industrial Plants,” IEEE Spectrum (June 1971).
resistance but also the resistance of the shoes and the resistance between the shoes and ground.
Tables 4.6.1 and 4.6.2 give basic information for estimating the total resistance to ground.
Let us estimate the current caused when a person is standing on moist ground with leather-
soled damp shoes and unwillingly grabs hold of 240-V wire with a wet palm. Referring to Tables
4.6.1 and 4.6.2 and taking the lowest values, one has 1 k- for the grasp, 200 - for the body, and
5 k- for the feet and shoes. Thus the largest current the victim might carry would be 240V/6.2
k-, or about 40 mA. From Figure 4.6.1 one can see that there is a good chance that the victim
would be unable to release the grasp and unable to breathe. Thus a dangerous situation may exist.
When a person is experiencing electric shock, because the damaging effects are progressive,
time becomes a critical factor. First, the source of electric energy should be removed from the
shock victim, even before an emergency medical service is called in. CPR (cardiopulmonary
resuscitation) may have to be administered by a trained person. The condition of ventricular
fibrillation occurs, the heart loses its synchronized pumping action, and the blood circulation
ceases. Sophisticated medical equipment may be needed to restore coherent heart pumping.
When working around electric power, the following general precautions are to be taken:
• Make sure that the power is off before working on any electric wiring or electric equipment.
• Wear rubber gloves and rubber-soled shoes, if possible.
• Avoid standing on a wet surface or on moist ground.
• Avoid working alone, as far as possible, around exposed electric power.
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PROBLEMS
*4.1.1 The line-to-line voltage of a balanced wye- (a) Determine the line current, the power factor,
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connected three-phase source is given as 100 V. the total volt-amperes, the real power, and the
Choose VAB as the reference. reactive power absorbed by the load.
(a) For the phase sequence A–B–C, sketch the (b) Compare the results of Problem 4.2.5(a) with
phasor diagram of the voltages and find the those obtained in Problem 4.2.4(a), and ex-
expressions for the phase voltages. plain why they are the same.
(b) Repeat part (a) for the phase sequence C–B–A. (c) Sketch the phasor diagram showing all volt-
4.2.1 A three-phase, three-wire 208-V system is con- ages and currents, with V̄AB as the reference.
nected to a balanced three-phase load. The line 4.2.6 A 60-Hz, 440-V, three-phase system feeds two
currents I¯A , I¯B , and I¯C are given to be in phase balanced wye-connected loads in parallel. One
with the line-to-line voltages V̄BC , V̄CA , and V̄AB , load has a per-phase impedance of 8 + j 3 - and
respectively. If the line current is measured to be the other 4 − j 1 -. Compute the real power in
10 A, find the per-phase impedance of the load. kW delivered to (a) the inductive load, and (b) the
(a) If the load is wye-connected. capacitive load.
(b) If the load is delta-connected. *4.2.7 Balanced wye-connected loads drawing 10 kW

at 0.8 power factor lagging and 15 kW at 0.9
*4.2.2 Consider a three-phase 25-kVA, 440-V, 60-Hz power factor leading are connected in parallel and
alternator operating at full load (i.e., delivering supplied by a 60-Hz, 300-V, three-phase system.
its rated kVA) under balanced steady-state condi- Find the line current delivered by the source.
tions. Find the magnitudes of the alternator line
current and phase current. 4.2.8 A balanced delta-connected load with a per-phase
impedance of 30 + j 10 - is connected in parallel
(a) If the generator windings are wye-connected. with a balanced wye-connected load with a per-
(b) If the generator windings are delta-connected. phase impedance of 40 − j 10 -. This load combi-
4.2.3 Let the alternator of Problem 4.2.2 supply a line nation is connected to a balanced three-phase sup-
current of 20 A at a power factor of 0.8 lagging. ply through three conductors, each of which has a
Determine: resistance of 0.4 -. The line-to-line voltage at the
terminals of the load combination is measured to
(a) The kVA supplied by the machine. be 2000 V. Determine the power in kW:
(b) The real power kW delivered by the generator. (a) Delivered to the delta-connected load.
(c) The reactive power kVAR delivered by the (b) Delivered to the wye-connected load.
alternator.
(c) Lost in the line conductors.
4.2.4 A balanced wye-connected load with a per-phase
impedance of 4 + j 3 - is supplied by a 173-V, 4.2.9 Three identical impedances of 30 30° - are con-
60-Hz three-phase source. nected in delta to a three-phase 173-V system by
conductors that have impedances of 0.8 + j 0.6 -
(a) Find the line current, the power factor, the total each. Compute the magnitude of the line-to-line
volt-amperes, the real power, and the reactive voltage at the terminals of the load.
power absorbed by the load.
4.2.10 Repeat Problem 4.2.9 for a delta-connected set of
(b) Sketch the phasor diagram showing all the capacitors with a per-phase reactance of −j 60 -
voltages and currents, with V̄AB as the ref- connected in parallel with the load, and compare
erence. the result with that obtained in Problem 4.2.9.
(c) If the star point of the load is connected to 4.2.11 Two balanced, three-phase, wye-connected loads
the system neutral through an ammeter, what are in parallel across a balanced three-phase sup-
would the meter read? ply. Load 1 draws a current of 20 A at 0.8 power
4.2.5 A balanced delta-connected load with a per-phase factor leading, and load 2 draws a current of 30
impedance of 12 + j 9 - is supplied by a 173-V, A at 0.8 power factor lagging. For the combined
60-Hz three-phase source. load compute:
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PROBLEMS 219
(a) The current taken from the supply and the 4.2.16 A balanced electrical industrial plant load of 9.8
supply power factor. MW with 0.8 lagging power factor is supplied by
(b) The total real power in kW supplied by the a three-phase 60-Hz system having a maximum
source, if the supply voltage is 400 V. rating (load-carrying capacity) of 660 A at 11 kV
(line-to-line voltage).
4.2.12 Two balanced, three-phase, wye-connected loads
are in parallel across a balanced, three-phase sup- (a) Determine the apparent power and the reactive
ply. Load 1 draws 15 kVA at 0.8 power factor power drawn by the load.
lagging, and load 2 draws 20 kVA at 0.6 power
(b) Additional equipment, consisting of a load
factor leading. Determine:
of 1.5 MW and 0.7 MVAR lagging, is to be
(a) The total real power supplied in kW. installed in the plant. Compute the minimum
(b) The total kVA supplied. rating in MVA of the power factor correction
capacitor that must be installed if the rating of
(c) The overall power factor of the combined
the line is not to be exceeded. Find the system
load.
power factor.
*4.2.13 Two balanced, wye-connected, three-phase loads
are in parallel across a balanced, three-phase 60- (c) If the capacitor, consisting of three equal sec-
Hz, 208-V supply. The first load takes 12 kW at 0.6 tions, is connected in delta across the supply
power factor lagging, and the second load takes 15 lines, calculate the capacitance required in
kVA at 0.8 power factor lagging. each section.
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(a) Draw the power triangle for each load and for 4.2.17 Derive the relationships given in Figure 4.2.1 for
the combination. the wye–delta and the delta–wye transformations.
(b) What is the total kVA supplied? 4.2.18 Two three-phase generators are supplying to a
(c) Find the supply power factor, and specify common balanced three-phase load of 30 kW at
whether lagging or leading. 0.8 power factor lagging. The per-phase imped-
ance of the lines connecting the generator G1 to
(d) Compute the magnitude of the current drawn the load is 1.4 + j 1.6 -, whereas that of the
by each load and drawn from the supply. lines connecting the generator G2 to the load is
(e) If wye-connected capacitors are placed in par- 0.8 + j 1 -. If the generator G1, operating at a
allel with the two loads in order to improve terminal voltage of 800 V (line to line), supplies
the supply power factor, determine the value 15 kW at 0.8 power factor lagging, find the voltage
of capacitance in farads in each phase needed at the load terminals, the terminal voltage of the
to bring the overall power factor to unity. generator G2, and the real power, as well as the
4.2.14 A three-phase balanced load draws 100 kW at reactive power output of the generator G2.
0.8 power factor lagging. In order to improve the 4.3.1 Determine the wattmeter readings when the two-
supply power factor to 0.95 leading, a synchronous wattmeter method is applied to Problem 4.2.4, and
motor drawing 50 kW is connected in parallel with check the total power obtained.
the load. Compute the kVAR, kVA, and the power
factor of the motor (specify whether lagging or 4.3.2 When the two-wattmeter method for measuring
leading). three-phase power is used on a certain balanced
load, readings of 1200 W and 400 W are obtained
4.2.15 (a) A balanced wye-connected load with per-
(without any reversals). Determine the delta-
phase impedance of 20+j 10 - is connected to connected load impedances if the system voltage
a balanced 415-V, three-phase supply through is 440 V. With the information given, is it possible
three conductors, each of which has a series to find whether the load impedance is capacitive
impedance of 2 + j 4 -. Find the line current, or inductive in nature?
the voltage across the load, the power deliv-
ered to the load, and the power lost in the line 4.3.3 The two-wattmeter method for measuring three-
conductors. phase power is applied on a balanced wye-
connected load, as shown in Figure 4.3.2, and the
(b) Repeat the problem if the three per-phase
readings are given by
load impedances of part (a) were connected
in delta. WC = 836W and WA = 224 W
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If the system voltage is 100 V, find the per-phase 4.4.1 Referring to Figure 4.4.1, let VBN = VRN =
impedance of the load. In this problem, is it pos- 120 V rms magnitude, and VBR = 240 V rms
sible to specify the capacitive or inductive nature magnitude. Write down expressions for vBN(t),
of the impedance? vRN(t), and vBR(t), and sketch them as a function
4.3.4 Two wattmeters are used, as shown in Figure 4.3.1, of time.
to measure the power absorbed by a balanced *4.4.2 Consider a 240-V supply feeding a resistive load
delta-connected load. Determine the total power in of 10 kW through wires having a total resistance
kW, the power factor, and the per-phase impedance of R = 0.02 -. For the same load, let a 120-V
of the load if the supply-system voltage is 120 V supply be used with a total wire resistance of R/2
and the wattmeter readings are given by = 0.01 -. Compute the I 2R loss in the lines for
(a) WA = −500 W, and WC = 1300 W. both cases and compare.
(b) WA = 1300 W, and WC = −500 W. 4.4.3 A person, while driving a car in a cyclone and
*4.3.5 Referring to Problem 4.2.15(b), with a phase volt- waiting at an intersection, hears a thumping sound
age as the reference phasor and with a positive- when a power line falls across the car and makes
phase-sequence supply system, two single-phase contact with the chassis. The power line voltage to
wattmeters are used to measure the power deliv- ground is 2400 V. Instinctively he steps out onto
ered to the load. The wattmeter current coils are the wet ground, while holding the door handle,
arranged as in Figure 4.3.1 to carry the currents IA to check out the external situation. Assuming his
and IC, whereas the potential coils share a common body resistance to be 10 k- and negligible auto-
connection at the node B. Determine the readings chassis resistance, comment on what might hap-
of the two wattmeters WA and WC, and verify that pen to the individual. Would it have been safer
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the sum of these readings equals the total power for him to remain in the car until some help ar-
in the load. rived?
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PART
ELECTRONIC ANALOG AND

DIGITAL SYSTEMS
TWO
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5 Analog Building Blocks and
Operational Amplifiers
5.1 The Amplifier Block
5.2 Ideal Operational Amplifier
5.3 Practical Properties of Operational Amplifiers
5.4 Applications of Operational Amplifiers
5.6 Practical Application: A Case Study—Automotive Power-Assisted Steering System

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Problems
Electronic systems usually process information in either analog or digital form. In order to process
the two different kinds of signals, analog circuits and digital circuits have been devised. While
almost all technology was of the analog type until around 1960, due to the advent of integrated
circuits (ICs), digital technology has grown tremendously.
In analog systems, a signal voltage or current is made proportional to some physical quantity.
Since voltages (or currents) can take on any values over a continuous range between some
minimum and some maximum, analog systems are also known as continuous-state systems.
These are to be distinguished from digital or discrete-state systems, in which only certain values
of voltage (or current) are allowed.
Most circuits found in analog systems are linear circuits in which one voltage (or current) is
meant to be linearly proportional to another. Linear active circuits are also known as amplifiers,
which are the building blocks of linear systems with analog technology.
When describing and analyzing electric systems, which are often large and complex, it is very
helpful to consider such large systems as being built from smaller units, called building blocks.
These are then the subunits, which can be connected to form larger circuits or systems. More
importantly, the building blocks can be described adequately by their simple terminal properties.
Thus, with the building block point of view, one is not concerned with the interiors of the blocks,
only with how they perform as seen from the outside.
The concept of a model, which is a collection of ideal linear circuit elements simulating
approximately the behavior of a real circuit element or a building block under certain limitations,
223
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224 ANALOG BUILDING BLOCKS AND OPERATIONAL AMPLIFIERS
is utilized in order to predict the performance of electronic systems through the use of equations. In
this chapter first models are developed for the amplifier block, then an ideal operational amplifier
is presented, and later applications of operational amplifiers are discussed.
5.1 THE AMPLIFIER BLOCK

An amplifier can be modeled as a two-port device, that is, a box with two pairs of terminals
designated as input and output, as shown in Figure 5.1.1 (a). The circuit model of the amplifier
block shown in Figure 5.1.1 (b) is developed on the basis of the following considerations:
1. Since, for most amplifiers, the input current is proportional to the input voltage, the input
terminals in the model are connected by a resistance Ri, known as the input resistance of
the amplifier.
2. Since an amplifier delivers electric power (to a speaker, for example), the output current
can be represented by its Thévenin-source model. The Thévenin resistance Ro is known as
the output resistance and the Thévenin voltage is a dependent voltage source Avin, where
A is called the open-circuit voltage amplification.
Thus, the amplifier block is a linear circuit block in which the output is proportional to the
input, and the amplifier is characterized by the three constants Ri, Ro, and A. The input and output
resistances may be generalized to input and output impedances in ac systems. The advantage of the
model is that all internal complexities are summarized in the three constants, thereby simplifying
the analysis of electric systems with amplifiers. Power-supply connections are usually not shown
in circuit diagrams since they would only clutter up the drawing. It is assumed, however, that
there are always connections to some power source in order to bring in the power necessary to
run the amplifier (as will be illustrated in Example 5.1.4).
EXAMPLE 5.1.1
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Let the amplifier block be connected to a current source at the input terminals, as shown in Figure
E5.1.1(a), and to a load resistance RL at its output terminals. Find vout.
+ +
Is Rs vin vout RL
− −
Input Output
(a)
+ + +
Ro
Is Rs vin Ri vout RL
− − Avin −
(b)
Figure E5.1.1
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5.1 THE AMPLIFIER BLOCK 225
Solution
Using the model of Figure 5.1.1(b), we have the circuit configuration shown in Figure E5.1.1(b).
Since Ri and RS are connected in parallel,
RS R i
vin = IS
RS + R i
Using the voltage-divider formula, one has
RL ARL RS Ri IS
vout = Avin =
Ro + R L (Ro + RL ) (RS + Ri )
Recall that A is the open-circuit voltage amplification. Let us consider the circuit shown
in Figure 5.1.2 in order to explain voltage amplification, or voltage gain. In this circuit a signal
voltage vS is applied to the input of the amplifier block, whereas the output terminals are connected
to a load resistance RL . Let us evaluate the ratio of the voltage across the load to the signal voltage
vL /vS , which is known as voltage gain GV,
vL Avin RL ARL
GV = = = (5.1.1)
vS (Ro + RL ) vS (Ro + RL )
If there is no load, i.e., RL = ∞, then it is easy to see that the voltage gain GV will be equal to A;
hence the justification to call A the open-circuit voltage amplification. The reduction in voltage
gain due to the effect of output loading can be seen from Equation (5.1.1).
iin iout Figure 5.1.1 Amplifier block. (a) Two-

+ + port device. (b) Circuit model.
vin vout
− −
Input Output
(a)
iin iout
+ +
+ Ro
vin Ri vout
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− Avin
− −
Input Output
(b)
iS
+ + iL
+ + Ro
vS vin Ri vout = vL RL
− −
− Avin −
Figure 5.1.2 Circuit to explain voltage amplification or voltage gain.
Copyright OUP
By defining the current gain GI to be the ratio of the current through RL to the current through
vS, one gets
iL Avin / (Ro + RL ) ARi
GI = = = (5.1.2)
iS vin /Ri Ro + R L
The power gain GP, defined by the ratio of the power delivered to the load to the power given
out by the signal source, is obtained as
vL2 /RL G2 Ri A 2 RL Ri
GP = = V = = GV G I (5.1.3)
2
vS /Ri RL (Ro + RL )2
Note that, for fixed values of Ro and Ri, GP is maximized when RL is chosen equal to Ro, and this
corresponds to maximum power transfer to the load. One should also note that the added power
emerging from the output comes from the power source that powers the amplifier, even though
the power-supply connections are usually not shown on the circuit diagram, and that the existence
of power gain does not violate the law of energy conservation.
EXAMPLE 5.1.2
The constants of an amplifier are given by A = 1, Ri = 10,000 -, and Ro = 100 -. It is driven by
a Thévenin source with vTh(t) = VO cos ωt and RTh = 20,000 -. The amplifier output is connected
to a 100-- load resistance. Find the power amplification, if it is defined as the ratio of the power
delivered to the load to the maximum power available from the Thévenin source.
Solution
The corresponding circuit diagram is shown in Figure E5.1.2. The instantaneous power delivered
to RL is given by
RTh = 20,000 Ω
+
+ + Ro = 100 Ω
vTh = Ri = RL =
vin
VO cos ωt 10,000 Ω 100 Ω
− −
− Avin = vin
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Signal source Load
Amplifier
Figure E5.1.2 Circuit diagram.
2
Avin (t)
PL (t) = iL2 (t) RL = RL
Ro + R L
The time-averaged power PL is obtained by representing vin(t) by its phasor V̄in ,
1 * *2 A 2 RL
PL = *V̄in *
2 (Ro + RL )2
Note that the time average of a product of sinusoids is given by
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5.1 THE AMPLIFIER BLOCK 227
* *2
1 ∗

*V̄ *
Time average of [v (t) v (t)] = Re V̄ V̄ =
2 2
The maximum power is derived from a Thévenin source when it is loaded by a resistance
equal to RTh. The maximum power thus obtainable, known as available power PAVL, is given by
* *2
*V̄Th *
PAVL =
8RTh
In this circuit,
* *2 Ri2 * *2
*V̄in * = *V̄Th *
(Ri + RTh ) 2
Note that the peak value of the sinusoid is used here for the magnitude of the phasor in these
expressions. Thus,
PL 4A2 RL Ri2 RTh
GP = =
PAVL (Ro + RL )2 (Ri + RTh )2
Substituting the values given, one gets
4 (1)2 (100) 108 (20,000) 200
GP = = = 22.22
(100 + 100) (10,000 + 20,000)
2 2 9
Note that although the amplifier’s open-circuit voltage amplification A is only unity, substantial
power gain is obtained in this case since the current gain is greater than unity and GP = GVGI.
In applications of microwave technology, the function of the amplifier is to magnify very small
power to a measurable level with as little random noise as possible. The source signal may be
from a radio telescope, and the available power may be determined by the power captured by the
antenna dish.
EXAMPLE 5.1.3
Quite often an amplifier is used as a component of an amplifier circuit. Consider the amplifier
circuit shown in Figure E5.1.3, which contains an amplifier block as an internal component. Find
the input resistance Ri , the output resistance Ro , and the open-circuit voltage amplification A of
the larger circuit.
RS A R1 C
+ + Amplifier +
vin block vout
vS R2 RL
with constants
−
− R i , Ro , A −
B D
Figure E5.1.3
Solution
The input resistance looking into terminals A and B is
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Ri = R1 + Ri
The output resistance is the same as the Thévenin resistance seen from terminals C and D. Turning
off independent source vS, vin becomes zero, and as a consequence the dependent source in the
amplifier block goes to zero. Looking to the left of terminals C and D, R2 and Ro can be seen to
be in parallel,
R 2 Ro
Ro =
R2 + R o
The open-circuit voltage gain of the larger circuit is
vCD
A =
vAB
With
R2 Ri
vCD = Avin and vin = vAB
Ro + R 2 Ri + R 1
we have
vCD AR2 Ri
A = =
vAB (Ro + R2 ) (Ri + R1 )
In further calculations, the dashed box can simply be replaced by the model with parameters
Ri , Ro , and A . The reader should note that in general Ri may depend on RL , and Ro may depend
on RS , even though in this simple example they do not.
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Two of the most important considerations that influence amplifier design are power-handling
capacity and frequency response. In practice, the performance of an amplifier is limited by its
ability to dissipate heat, known as its power dissipation. The electric power that is converted to
heat in an amplifier can be calculated when the currents and voltages are known at all its terminals,
including the power-supply terminals.
EXAMPLE 5.1.4
For the amplifier circuit shown in Figure E5.1.4 with Ri ∼ = ∞, Ro ∼ = 0, A = 10, RL =
100 -, and vin = 1 V, calculate the power dissipated in the amplifier if the voltage at the
power-supply terminal Vps is given to be 20 V and Ips is assumed to be equal to IL.
Figure E5.1.4
v = vps
Ips
+ (1) (5) (3)

+ IL
vin vout RL
−
− (2) (6) (4)
Ips
v=0
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5.2 IDEAL OPERATIONAL AMPLIFIER 229
Solution
We have

6
P = V n In
n=1
where Vn is the voltage at terminal n and In is the current flowing into terminal n. Note that currents
I 1 and I 2 are zero since Ri = ∞, vout = Avin = 10(1) = 10 V. The power supply maintains terminal
5 at V5 = Vps = 20 V and terminal 6 at V6 = 0; I3 = −I4 and I5 = −I6 . Then
P = V3 I3 + V4 I4 + V5 I5 + V6 I6 = V3 (−IL ) + V4 IL + V5 Ips − V6 Ips

= (V4 − V3 ) IL + Vps Ips = −Vout IL + Vps Ips

= Vps − Vout Ips = Vps − Vout IL
Noting that IL = V out/RL , one has

10
P = (20 − 10) = 1W
100
Since many amplifiers are designed with large values of Ri in order to keep the input power
low, the approximation of Ri ∼ = ∞ is often justified. However, the assumption that Ips = IL is not
as justified because a certain amount of additional current (though kept small in order to minimize
the waste) will pass directly through the amplifier from terminal 5 to terminal 6 without going
through the load, making I ps slightly larger than IL.
The behavior of an amplifier always depends on the frequency of the sinusoidal signal
in question. In general,
* * the parameters of the amplifier model vary with the signal frequency.
The variation of *Ā*, as well as that of the phase angle
* θA* , with frequency for an ampli-
fier is known as its frequency response. The value of *Ā(f )* always drops off at sufficiently
high frequencies. Since Ā(ω) = V̄out /V̄in , the phase difference θA between output and in-
put sinusoids is also a function of frequency. However, at low frequencies θ*A *is often zero,
and therefore Ā can be regarded as real. Figure 5.1.3 shows variations of *Ā* and θA typ-
ical of audio, video, bandpass, and operational amplifiers. The input and output resistances
should be generalized to impedances Zi(ω) and Zo(ω) when frequency effects are important.
However, most commercial amplifiers are designed to make Zi and Zo real and constant over
the useful frequency range of the amplifier block. If the frequency response of a block it-
self is known, the frequency response of a larger circuit containing the amplifier block can
be found.
5.2 IDEAL OPERATIONAL AMPLIFIER

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The operational amplifier, known also as op amp, consists of several transistors, diodes, capacitors,
and resistors. It is available in integrated-circuit form for less than one U.S. dollar. Being
inexpensive, compact, and versatile, operational amplifiers are used in a variety of simple circuits.
Op-amp circuits, as we will see later, usually contain negative feedback.
Op-amp circuits themselves can be regarded as building blocks. These blocks are charac-
terized by their input resistance, output resistance, and open-circuit voltage amplification. The
symbol for the op amp is shown in Figure 5.2.1. Two terminals labeled + and − are available
for inputs. The voltages of these terminals are labeled with respect to the common terminal,
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Copyright OUP
230
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−
|A| θA, deg
(log scale)
10
− 7
|A| θA, deg + 90
θA 5
+90 −
4 0 |A|
100 −
|A|
3
0 −90
10 θA 2
−90
1
10 100 1k 10 k 100 k f, Hz f, GHz
(a) 9.6 9.7 9.8 9.9 10.0 10.1 10.2 10.3 10.4
(c)
− −
|A| θA, deg |A| θA, deg
100 − +90
|A| 105
−
10 0 |A|
Not for Resale, 08/23/2019 14:15:14 MDT

θA 104
1 −90
10 100 1k 10 k 100 k 1M 10 M 100 M f, Hz 103
(b) +90
ANALOG BUILDING BLOCKS AND OPERATIONAL AMPLIFIERS
102
0
θA
10
−90
Licensee=Tipiel Colombia - Bogota /5931917151, User=Quinones-External, Sergio

1
1 10 100 1k 10 k 100 k f, Hz
(d)
Figure 5.1.3 Typical frequency response characteristics.

* * (a) Audio amplifier (b) Video amplifier. (c) Bandpass amplifier.
(d) Operational amplifier. Note the separate scales for *Ā* and θA .
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Zi
i
Figure 5.2.1 Operational amplifier.
+ + +
vd = vp − vn A +
vp − −
+ vo = A(vp − vn); A ≥ 105
vn
− − −
Ground Zo
denoted by a ground symbol. The output voltage is related to the difference between the two input
voltages as
vo = A(vp − vn ) (5.2.1)
where A is the open-loop voltage gain. Thus, the op amp is basically a form of differen-
tial amplifier, in which the difference vp − vn is amplified. For an output voltage on the
order of 12 V, the difference voltage vd is on the order of 0.12 mV, or 120 µV. The input
impedance Zi is on the order of 1 M-, while the output impedance Zo is on the order of 100
- to 1 k-.
The practical op-amp characteristics are approximated in the ideal op amp shown in Figure
5.2.2. Because of the high input impedance, very large gain, and the resulting small difference
voltage vd in practical op amps, the ideal op amp is approximated by the following two charac-
teristics:
1. The input currents ip and in are zero, ip = in = 0.
2. The difference voltage vd is zero, vd = 0.
The principle of virtual short circuit, illustrated by the preceding, is utilized in analyzing circuits
containing ideal op amps. The accompanying principle of negative feedback is explained later.
The ideal op-amp technique is based on the approximations that A ∼ = ∞, Zi ∼ = ∞, and Zo ∼ = 0.
The output voltage can always be found from the ideal op-amp technique in the usual op-amp
feedback circuits, since the precise values of A, Zi, and Zo have negligible influence on the answer,
as shown in Example 5.2.1.
The op amp is composed of a number of transistor stages on a single chip and pro-
vides the characteristics of a voltage-controlled voltage source. The so-called ideal op amp
is characterized by infinite bandwidth. However, it is pertinent to mention that the band-
width of an op amp without feedback is quite small. In commercially available op amps,
while the open-loop voltage gain A is rather large (usually 105 or greater), the range of fre-
quency for which this gain is achieved is limited. The asymptotic Bode diagram shown in
Figure 5.2.3 illustrates the frequency characteristic for the open-loop voltage gain. For fre-
quencies below fh, the open-loop gain is a constant Ao; for frequencies beyond fh, the open-
loop gain decreases. The frequency fh is known as the open-loop bandwidth, as it separates
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
ip = 0 Figure 5.2.2 Ideal operational amplifier.

+ +
vd = 0 +
vp −
+ vo
vn in = 0
− − −
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the constant region from the high-frequency band for which the open-loop gain decreases.
fh is also called the half-power frequency since the magnitude of A is 3 dB below its low-
frequency value A0. The frequency f GB at which AdB = 0, or the magnitude A = 1, is the
gain–bandwidth product given by A0fh. Typical values of fh and f GB are 10 Hz and 1 MHz,
respectively. To overcome this frequency limitation, both inverting and noninverting op-amp
stages (which are examples of feedback amplifiers) are frequently used. These will be discussed
later in examples.
Feedback circuits have a desensitizing property, which implies that variations in the values
of the op-amp parameters have little effect on the output of the circuit. “Feedback” implies
that some of the output signal is fed back to be added to the input. Another property of
feedback amplifiers is that the open-loop and closed-loop gain–bandwidth products are equal.
Referring to Figure 5.2.4, which shows the open-loop and closed-loop frequency responses, it
follows that
A 0 f h = G0 f H (5.2.2)
where A0 fh is the open-loop gain–bandwidth product, fH is the closed-loop bandwidth, and G0 is

the closed-loop gain. The term closed loop signifies circuit performance when a path exists from
output to input, whereas open loop implies the inherent characteristics of the op amp. Thus, for
an op amp whose gain bandwidth product is 1 MHz with A0 = 105 and fh = 10 Hz, a stage
with a closed-loop gain of 10 has a bandwidth fH = 100 kHz, as shown in the asymptotic Bode
diagram of Figure 5.2.4.
|A|dB Figure 5.2.3 Asymptotic Bode diagram for

open-loop voltage gain.
−20 dB/decade
A0 dB
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
f, Hz(log scale)
0 fh fGB
|A|dB (gain magnitude)
Open-loop response with op amp alone

A0 dB 100
80 −20 dB/decade
60
40
Closed-loop response
G0 dB 20 fh with op amp in feedback circuit f fGB
H
0 f, Hz (log scale)
10 102 103 104 105 106
Figure 5.2.4 Typical frequency response of op-amp stage.
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EXAMPLE 5.2.1
(a) Consider the circuit of the inverting amplifier shown in Figure E5.2.1(a), including an
ideal op amp. Show that the voltage gain of the overall circuit vo/vi is independent of the
op-amp parameters.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(b) Without considering the op-amp gain to be infinite, investigate the effect of a finite value
of A, the open-circuit voltage amplification of the op amp, on the voltage gain of the
overall circuit.
(c) Let Ri = 2 k- and Rf = 80 k- in Figure E5.2.1(a). Find the voltage gain of the overall
circuit: (i) if the op-amp gain is infinite, and (ii) if the op amp gain is 100.
if − vo + Figure E5.2.1 (a) Inverting ampli-

fier. (b) Equivalent circuit.
+ vi − Rf
Ri in = 0
1
+ + − 3
ii vd = 0 +
vi − +
2 vo
− −
(a)
vo
vp
+
A(vp - vn)
−
vi
vn
Ri
Rf if
(b)
Solution
(a) Notice that a resistor Ri is placed in the − lead, whereas the + lead is connected to the
common terminal (ground). Also, a feedback resistor Rf is connected between the − lead
and the output lead. Noting that in = 0 and ii = if , the KVL equation around the outside
loop yields
vi = Ri ii + Rf if + vo
Since vd = 0, it follows that ii = vi /Ri . Thus, one gets

vi
vi = Ri + Rf + vo
Ri
Solving for the voltage gain, vo /vi = −Rf /Ri , where the negative sign implies that this
is an inverting amplifier, i.e., the output voltage is 180° out of phase with the input voltage.
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The voltage gain is independent of the op-amp parameters. By selecting the resistors
to achieve the desired ratio, constructing a linear amplifier with a prescribed voltage
gain is rather simple. It may further be noted that the output impedance is Zo =
0, with zero output impedance of the ideal op amp; the input impedance is Zi =
vi / ii = Ri .
(b) The equivalent circuit of the inverting amplifier is shown in Figure E5.2.1(b). The current
through the feedback resistor if is given by
vo − vi
if =
Rf + Ri
The voltage at the inverting input vn is

vn = vi + Ri if
Combining these two equations, one gets

vo − vi
vn = vi + Ri
Rf + Ri
Since vp is connected directly to ground, vp = 0; the output voltage vo is

vo − v i
vo = −Avn = −A vi + Ri
Rf + Ri
The voltage gain of the overall circuit is then given by

Ri
1−
vo Ri + Rf
=−
vi 1 Ri
+
A Ri + Rf
If A becomes infinitely large, 1/A → 0, and the preceding expression reduces to −Rf /Ri ,
obtained in part (a). Clearly as A → ∞, the inverting terminal voltage vn = −vo /A is
going to be very small, practically on the order of microvolts. Then it may be assumed
in the inverting amplifier that vn is virtually zero, i.e., vn ∼
= 0.
(c) (i) When A is infinitely large,
vo Rf 80
=− =− = −40
vi Ri 2
(ii) When A has a finite value of 100,

Ri 2
1− 1−
vo Ri + Rf 82 = −28.4
=− =−
vi 1 Ri 1 2
+ +
A Ri + Rf 100 82
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
The principle of negative feedback is clearly illustrated in the operation of the inverting
amplifier in Example 5.2.1, since negative feedback is used to keep the inverting terminal voltage
as close as possible to the noninverting terminal voltage. One way of viewing negative feedback
is to consider it as a self-balancing mechanism which allows the amplifier to preserve zero
Copyright OUP
5.3 PRACTICAL PROPERTIES OF OPERATIONAL AMPLIFIERS 235
potential difference between its input terminals. The effect of the feedback connection from
output to inverting input is then to force the voltage at the inverting input to be equal to that at
the noninverting input. This is equivalent to stating that for an op amp with negative feedback,
vn ∼
= vp . The analysis of the op amp is greatly simplified if one assumes that in = 0 and vn = vp .
The voltage gain of the overall circuit of Figure E5.2.1(a) is called the closed-loop gain, because
the presence of a feedback connection between the output and the input constitutes a closed loop
as per the terminology used in the field of automatic control, which is presented in Section 16.2.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
EXAMPLE 5.2.2
(a) Consider the circuit of the noninverting amplifier in Figure E5.2.2, including an ideal op
amp. Obtain an expression for the voltage gain of the overall circuit.
(b) Let Ri = 10 k- and Rf = 240 k- in Figure E5.2.2. Find the voltage gain of the overall
circuit.
2
ip = 0 Figure E5.2.2 Noninverting amplifier.
+ + + 3
vd = 0 in = 0 +
− −
1
vi
Ri vo
if Rf
ii
− −
Solution
(a) Note that the input is directly connected to the + terminal. Resistors Ri and Rf are
connected as in the previous example. Since the input current ip = 0, the input impedance
is infinite. Because in = 0, ii = if . The KVL equation around the loop containing Ri and
Rf gives
vo = −(Ri + Rf )ii
Because of the virtual short circuit, vi = −Ri ii . Thus, for the case of a simple noninverting
amplifier, one gets
vo Rf
=1+
vi Ri
(b) For the given values of Ri and Rf,

vo 240
=1+ = 25
vi 10
5.3 PRACTICAL PROPERTIES OF OPERATIONAL AMPLIFIERS

To achieve voltage gain and consequently power gain, the op amp must be biased by a dc source.
The biasing network is comprised of the power supply and the passive circuit elements surrounding
Copyright OUP
the device that provide the correct dc levels at the terminals. Terminals at which the dc bias is
to be connected are provided on the op-amp package with the actual biasing networks connected
internally. The manufacturer specifies the permissible range of supply-voltage values and the
corresponding op-amp characteristics.
Manufacturers add prefixes to type numbers such as 741 to indicate their own codings, even
though the specifications are similar. For example,
µA 741 Fairchild
LM 741 National Semiconductors
An extra letter is sometimes added to indicate a temperature specification. For example,

µA 741 A Military specification for guaranteed operation between −55 and +125°C
µA 741 C Commercial specification for temperature range of 0 to 70°C
Practical op amps are composed of several amplifier stages, a typical structure of which is
shown in Figure 5.3.1. The three building blocks are the input differential amplifier, the common
emitter stage, and the emitter follower output stage. Some of the op-amp practical properties
follow.
OPEN-LOOP VOLTAGE GAIN A

The op amp amplifies the difference vd between the voltage on the noninverting (+) terminal
and the inverting (−) terminal; see Figure 5.3.2. The term “open loop” implies that there is no
external feedback connection between the output and either of the inputs. A is defined as the
ratio of the change in output voltage to the change in differential input voltage, usually for a load
resistance of no less than 2 -k. A typical value for A is 2 × 105 .
INPUT RESISTANCE Ri
Input resistance is the open-loop incremental resistance looking into the two input terminals,
and is typically 2 M-. Manufacturers sometimes quote the resistance between inputs and ground.
OUTPUT RESISTANCE Ro
The open-loop output resistance is usually between 50 and 500 -, with a typical value of 75 -
for the 741. Thus one can see that Figure 5.3.3 is the representation of an op amp as a circuit
element or block.
vp Figure 5.3.1 Typical op-amp stages.

--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Common Emitter vo
Differential
emitter follower
amplifier
stage output
vn
+ − Figure 5.3.2 Op-amp symbol with signal voltages.

+
+
vn +
vp vo = Avd = A(vp − vn )
− − −
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Figure 5.3.3 Op amp as a circuit component

block.
− A(vp − vn)
+ +
Ri +
−
vn +
+ vo
vp
− − −
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Common-Mode Rejection Ratio (CMRR)
When there is a common-mode input voltage, i.e., when the input signals are equal and greater
than zero, the output voltage of an ideal op amp is zero because vd is equal to zero. In general, the
common-mode input vC is defined as vp + vn /2; and the difference signal vd = vp − vn is to be
amplified. Common-mode gain AC is defined as the ratio vo/vC when vd = 0. The common-mode
rejection ratio (CMRR) is defined by A/AC, but is usually expressed in units of decibel (dB),
A
CMRR = 20 log10 (5.3.1)
AC
It is typically 90 dB, i.e., A/AC ∼ = 32,000. The ideal op amp, however, has infinite CMRR.
To explain further, an op amp can be considered a special type of differential amplifier.
The object of a differential amplifier, which is formally presented a little later, is to amplify
“differences” in voltage between the two inputs, and to be unresponsive to voltage changes that
appear simultaneously on both inputs. The differential-mode input signal is the difference between
vp and vn; that is to say, vd = vp − vn. The common-mode input signal is the average value of the two
input signals; that is to say, vc = (v1 + v2)/2. The output voltage of the amplifier vo is given by vo
= vdAd + vcAc, where Ad (called simply A previously) is the differential-mode voltage gain and Ac
is the common-mode voltage gain. Under ideal conditions, Ac is equal to zero and the differential
amplifier completely rejects the common-mode signals. The departure from this ideal condition
is a figure of merit for a differential amplifier and is measured by CMRR, which is the ratio of
Ad to Ac. CMRR can thus be seen as a measure of an amplifier’s ability to distinguish between
differential-mode and common-mode signals. One of the practical advantages of a differential
amplifier is its rejection of unwanted signals or noise.
INPUT OFFSET VOLTAGE VOS

When both inputs are tied to ground, i.e., both differential-mode and common-mode inputs are
zero, the output should be zero. In practice there will be mismatches in amplifier components, and
if there is a mismatch in an input stage, the effect will be amplified, leading to a significant output
voltage. The input offset voltage V OS is the differential input voltage required to make the output
zero, and is typically 1 mV. With some op amps, e.g., the 741, two voltage offset terminals are
provided, and by connecting a potentiometer between them and taking the slider to the specified
dc supply rail (or bus), as in Figure 5.3.4, the potentiometer can then be adjusted to zero the offset
voltage.
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2 Figure 5.3.4 Offset null terminals of 741 connected to

− 6 10-k- potentiometer and negative supply rail to zero the
3
+ 5 Pin 1 labeled “− offset null” offset voltage.
1 Pin 5 labeled “+ offset null”
10
kΩ
V−
INPUT BIAS CURRENT IB

When operated at extremely low quiescent current values, the base bias currents will be low; but
they do have to be taken into consideration. The input bias current IB for an op amp is defined as
the average of the two input currents with the inputs grounded (see Figure 5.3.5), i.e.,
IBp + IBn
IB = (5.3.2)
2
A typical value for a µA 741 is 80 nA; for a µA 771 it is 50 pA. When the resistance of the source
feeding the op amp is large enough, the input bias current may have an adverse effect. As shown
in Figure 5.3.6, where the noninverting input is grounded and the inverting input is connected
to a source of 1-M- resistance and of voltage vS momentarily at 0 V, the bias current of 80 nA
generates a voltage of −80 mV on the noninverting input.
INPUT OFFSET CURRENT IOS

The adverse effect of the input bias current mentioned would be nullified if both inputs were
connected to equal resistances (one of which could be a passive resistor) and if IBp = IBn . The
differential input would then be zero. However, if the input bias currents are unequal, as shown in
Figure 5.3.7, there will be a finite differential input voltage. It then becomes necessary to specify
the difference between the bias currents, and this is the input offset current I OS,
IOS = IBp − IBn (5.3.3)
A typical value for I OS is 20 nA. Both IB and I OS are usually measured with the output at 0 V; but
in practice the output voltage has little effect.
− Figure 5.3.5 Bias currents of op amp.

IBn
+
IBp
RS = 1 MΩ 80 nA Figure 5.3.6 Illustration of input voltage generated by bias

−
current.
vS = 0 VB = −80 mV +
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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RS IBn Figure 5.3.7 Illustration of unequal bias currents, which will cause
−
a differential input voltage even with equal source resistances.
+
RS IBp
Power-Supply Rejection Ratio (PSRR)

An op amp’s ability to disregard changes in power-supply voltage is measured by the power-
supply rejection ratio (PSRR), which is specified by the change in offset voltage V OS for a 1-V
change in dc power supply and is usually expressed in µV/V. A typical value is 15 µV/V.
Maximum Differential Input Voltage

This is the maximum value of differential input voltage vp − vn that can be applied without
damaging the op amp.
Maximum Common-Mode Input Voltage

This is the maximum voltage that the two inputs can be raised above ground potential before the
op amp becomes nonlinear.
Output Voltage Swing

Ideally this is equal to the difference between the two supply rail voltages, although in practice it
is a few volts less.
Internal Frequency Compensation

Some op amps, such as the 741, have internal RC networks which are intentionally designed to
reduce gain at high frequency. The result (shown in Figure 5.2.4) is that the open-loop gain begins
to fall at a few hertz and then has a characteristic falling at 20 dB/decade or 6 dB/octave (i.e.,
gain ∝ 1/f ) until eventually the gain becomes unity (0 dB) at about 1 MHz.
External Frequency Compensation

For applications requiring a more extended high-frequency response, there are op amps with no
internal compensation, and external frequency-compensation terminals are provided on these op
amps (for example, the 709) so that the frequency response can be tailored to avoid instability
without the heavy degrading of frequency response due to internal compensation. A typical
frequency-compensation circuit for the µA 709 is illustrated in Figure 5.3.8. Op-amp manufac-
turers supply plots of open- and closed-loop responses for various values of components connected
to the frequency-compensation terminals.
Slew Rate
Slew (or slewing) rate is a measure of how fast the output voltage can change. It is given by the
maximum value of dvo /dt, which is normally measured in response to a large input voltage step
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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R2 (use 50 Ω when amplifier is Figure 5.3.8 Typical frequency-compensation

2 operated with capacitive loading) circuit for Fairchild µA 709.
− 6
3 µA 709
+ 5
8
1
C2
Range of C1 10–5000 pF
C1 R1 Range of R1 0–1.5 kΩ
Range of C2 3–200 pF
and is therefore usually associated with low closed-loop voltage gain. For a 741 the slew rate is
0.5 V/µs at A = 1. For more recently developed op amps, the slew rate ranges from 5 to 100
V/µs. The effect of the slew rate in response to an input step voltage is shown in Figure 5.3.9.
If one attempts to make the output voltage change faster than the slew rate, nonlinearity will be
introduced. When specifying such output voltage requirements as rise time, output voltage, and
frequency, it is necessary to choose an op amp with a slew rate that meets the specifications. With
a sine-wave input, the slew rate limits a combination of maximum operating frequency and output
voltage magnitude.
The slew rate occurs because at some stage in the amplifier a frequency-compensating
capacitor will have to be charged, and the available limited charging current restricts the maximum
rate of change of the capacitor voltage. With externally compensated op amps, such as the 709,
slew rates will depend on the value of the compensating capacitors, which are in turn chosen
on the basis of the closed-loop gain needed. The lower the gain, the higher the compensating
capacitors, and hence the lower the slew rate. For a µA 709, the slew rate is 0.3 V/µs at A = 1
and 1.5 V/µs at A = 10.
Noise
This refers to the small, rapidly varying, random spurious signals generated by all electronic
circuits. Noise places a limit on the smallness of signals that can be used. The subject of random
signals and noise belongs to a branch of electrical engineering known as communication theory.
Stability
The amplifier is said to be stable when it performs its function reliably under all normal operating
conditions. By definition, a system is stable if its response to an excitation that decays to
1V Figure 5.3.9 Effect of op-amp slew rate with step voltage input.
vd
0
0.5 µs
1V
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
v0
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zero with time also decays to zero. Instability can come about in various ways, and it is a
very common difficulty, which must be prevented. In almost all cases, op-amp circuits can be
classified as feedback circuits. Feedback of an improper kind can lead to instability or oscillation
of an op-amp circuit. In general, instability occurs when there is excessive phase shift in the
op amp and feedback loop, so that negative feedback is changed to positive feedback. The
frequency response of an op amp is usually designed to roll off smoothly at 20 dB decade,
as mentioned earlier. This type of frequency response ensures stability for the more common
op-amp circuits.
Frequency Response
As with all electronic circuits, op amps have limited frequency response. Because of the negative
feedback of the circuit, the passband of an op-amp circuit is usually much larger than that of the
op amp by itself. Typically with a given op amp, increasing the bandwidth of an op-amp circuit
will decrease the voltage gain in the same proportion. Thus for a given op amp, the product of gain
and bandwidth (i.e., the gain–bandwidth product) is a constant, as discussed earlier and shown in
Figure 5.2.4.
Table 5.3.1 lists some representative op-amp parameters for different amplifier types, only
to illustrate their characteristics. One can see from the table that a high-power op amp can deliver
a large output current, but has relatively large offset parameters. On the other hand, a precision
input amplifier has low offset and high gain, but at the price of bandwidth, slew rate, and output
current. The general-purpose amplifier, as the name suggests, strikes a balance between these
extremes.
TABLE 5.3.1 Typical Op-Amp Characteristics
Input Input Gain– Maximum

Offset Offset Voltage Bandwidth Slew Output
Voltage Current Gain Product Rate Current
Type (mV) (pA) (V/mV) (MHz) (V/µs) (mA)
High Power 5 200 75 1 3 500

Wide band 3 200 15 30 30 50
High slew rate 5 100 4 50 400 50
Precision input 0.05 2 500 0.4 0.06 1
General purpose 2 50 100 1 3 10
EXAMPLE 5.3.1
In order to illustrate the insensitivity of feedback circuits to variations of the op-amp parameters,
let us consider a simple feedback circuit using an op amp, as shown in Figure E5.3.1(a). Using
the op-amp model of Figure 5.1.1, find the output voltage in terms of the input voltage under two
sets of conditions:
(a) A = 105 , Ri = 10 k-, RL = 1 k-, RS = 1 k-

(b) A = 2 × 105 , Ri = 30 k-, RL = 5 k-, RS = 2 k-
In order to simplify the calculations, let us assume that the op amp’s output resistance Ro is zero.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
Figure E5.3.1
− vo
+
vS RS
RL
(a)
vo
−
+
Ri A(v+ − v−) RL
−
vS +
RS
(b)
Solution
Replacing the op amp by its model, we have the circuit shown in Figure E5.3.1(b). The nodal
equation at the node labeled + is
v S − v+ vo − v+
+ =0
RS Ri
Also,
vo = A (v+ − v− ) and v− = vo
Thus,
vo = A (v+ − vo )
Solving, one gets
A Ri
vo = vS
A + 1 Ri + [RS / (1 + A)]
Evaluating vo /vS for the given two conditions, we have
(a) vo /vS = 0.999989
(b) vo /vS = 0.999994
Thus, we see that the output voltage (using negative feedback) is very nearly independent of Ri,
Ro, and A, provided the op amp’s parameters remain in their allowable ranges.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
EXAMPLE 5.3.2
Find the maximum frequency of an output sine wave which can be produced at an amplitude of
1.5 V if the op-amp slew rate is 0.5 V/µs.
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Solution
vo = Vm sin ωt
dvo
= ωVm cos ωt
dt
dvo 0.5
slew rate = maximum value of = ωVm = −6
dt 10
Hence,
0.5
ω= or f = 53 kHz
1.5 × 10−6
EXAMPLE 5.3.3
Consider the op-amp circuit shown in Figure E5.3.3 and obtain expressions for the open-loop
voltage gain at (a) low and (b) high frequencies. Also determine relations for the 3-dB point
frequency and the phase shift.
Solution
Using phasors and the voltage-divider rule,

--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
XC 1
V̄o = AV̄d , where XC =
XC + R o j ωC
(a) At low frequencies, XC becomes very large so that XC >> Ro . Then,
V̄o = AV̄d
The output signal is in phase with the input signal, since complex voltage gain Ā is the
same as A.
(b) At higher frequencies, XC becomes comparable to Ro. Let ĀF be the complex open-loop
voltage gain at frequency f. Then,
1/j ωC
ĀF =
[Ro + (1/j ωC)] Ao
Figure E5.3.3
−
Ro
v− − v+ = vd vo
+
Avd
C
+
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or
Ao
ĀF =
1 − j ωRo C
Ao (1 − j ωRo C)
=
1 + (ωRo C)2
* * Ao
*ĀF * = AF =
1 + (ωRo C)2√
At the 3-dB point, or half-power frequency fh , AF = Ao / 2, so that
1
ωh Ro C = 1 or fh =
2π Ro C
Denoting ĀF = AF ej φ , where φ indicates that the output leads the input,
tan φ = −ωRo C
At very high frequencies, tan φ → −∞ and φ → 3π/2, so that the output leads the input by
3π/2 or lags it by π/2. This is the largest phase shift possible.
5.4 APPLICATIONS OF OPERATIONAL AMPLIFIERS

An op amp along with a few external components (resistors and capacitors) is capable of
performing many different operations—hence the name operational. The linear operations of
integration, differentiation, addition, and subtraction that were needed in analog computers are
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
some of the early applications. Other linear applications include instrumentation amplifiers,
voltage-to-current and current-to-voltage converters, voltage followers, and active filters. Op
amps are also utilized in nonlinear applications such as limiters, comparators, voltage regulators,
signal rectifiers and detectors, logarithmic amplifiers, multipliers, and many digital circuits.
Negative feedback (which is said to be degenerative) is used to improve amplifier performance
by sacrificing gain. The opposite situation of positive feedback (which is said to be regenerative)
is also utilized, and gain is increased to the extent that an amplifier will produce an output signal
with no input. This leads to sinusoidal oscillators and nonsinusoidal waveform generators.
This section concentrates on a limited range of op-amp applications.
Inverting Amplifier
One common op-amp circuit is shown in Figure 5.4.1. For the case of finite voltage gain Ao of an
op amp that is otherwise ideal, the output voltage becomes
1 (inverting terminal) Figure 5.4.1 Inverting amplifier.

R2
R1
v1 i2
− 3
+ vo
i1 +
vi v2 = 0
−
2 (noninverting
terminal)
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5.4 APPLICATIONS OF OPERATIONAL AMPLIFIERS 245
vo = Ao (v2 − v1 ) (5.4.1)
Since v2 = 0, because terminal 2 is grounded,
vo
v1 = − (5.4.2)
Ao
Thus one gets
vi − v1 vi + (vo /Ao )
i1 = = (5.4.3)
R1 R1
v1 − vo − (vo /Ao ) − vo
i2 = = (5.4.4)
R2 R2
Since no current is drawn by terminal 1 of the ideal op amp,
i2 = i1 (5.4.5)
Hence,
vo R2 1
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
=− (5.4.6)
vi R1 1 + [(R1 + R2 ) /Ao R1 ]
which is the expression for the circuit gain. Now, if Ao → ∞, we have
vo R2
=− , if Ao → ∞ (5.4.7)
vi R1
which is independent of the op amp’s gain Ao (see Example 5.2.1). The sign inversion associated
with Equation (5.4.7) makes the amplifier “inverting.” Generally if Ao is at least 200 times the
magnitude of R2/R1, then the actual gain given by Equation (5.4.6) will be within 1% of the ideal
gain given by Equation (5.4.7). Assuming infinite gain of the op amp, it follows that
vd = v2 − v1 = 0 or v1 = v2 (5.4.8)
Since terminal 2 is at ground potential (zero) in Figure 5.4.1, terminal 1 is said to be a virtual
ground. Notice that when R2 = R1, the inverting amplifier becomes a voltage follower with inverted
sign and a gain magnitude of unity.
Noninverting Amplifier
It is called “noninverting” because there is no sign inversion. A typical circuit is shown in Figure
5.4.2. With a finite op-amp gain Ao,
vo vo
v2 − v1 = or v1 = v2 − (5.4.9)
Ao Ao
R2 Figure 5.4.2 Noninverting amplifier.

R1
1 v1 i2
− 3
vo
i1 2 +
+ v2 = vi
vi
−
Copyright OUP
−v1 −v2 vo
i1 = = + (5.4.10)
R1 R1 A o R1

v1 − vo v2 vo 1
i2 = = − +1 (5.4.11)
R2 R2 R2 A o
Since the ideal op amp draws no current,
i1 = i2 (5.4.12)
Also, as seen from Figure 5.4.2,
v2 = vi
In equating Equations (5.4.10) and (5.4.11), one gets

vo vo R2 1
= = 1+
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(5.4.13)
vi v2 R1 1 + [(R1 + R2 ) /Ao R1 ]
For Ao → ∞, the ideal circuit gain is
vo R2
=1+ (5.4.14)
vi R1
(See Example 5.2.2.) Note that if R2 = 0, for any nonzero value of R1,
vo
=1 (5.4.15)
vi
which is the gain of an ideal voltage follower. The same result applies if R1 → ∞ (i.e., open
circuit) for any finite R2.
Inverting Summing Amplifier

The circuit of Figure 5.4.1 is extended by adding other input points, as shown in Figure 5.4.3.
Because of the virtual ground at terminal 1 (ideal op-amp assumption), the response of the circuit
to any one input is not affected by the presence of the other N − 1 inputs. Based on Equation
(5.4.7) one can write the total output as the sum of all responses,
N
Rf Rf Rf vin
vo = − vi1 + vi2 + · · · + viN = −Rf (5.4.16)
R1 R2 RN n=1
Rn
R1 Figure 5.4.3 Inverting summing amplifier.

vi1
R2
vi2
RN Rf
viN
1 − 3
vo
2 +
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If all resistors Rn are the same, say Rn = R1 , for all n, then

Rf
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
N
vo = − vin , if all Rn = R1 (5.4.17)
R1 n=1
which corresponds to an inverting summing amplifier with gain.
Noninverting Summing Amplifier

The circuit of Figure 5.4.2 is generalized for multiple inputs, as shown in Figure 5.4.4. With the
ideal op-amp assumption, based on Equation (5.4.14), the noninverting gain is
vo Rf
=1+ (5.4.18)
v2 Rd
By superposition, the output vo is the sum of the responses taken individually. For input m,
[R1 R2 · · · RM ]without Rm vim
v2 = vim = [R1 R2 · · · RM ] (5.4.19)
Rm + [R1 R2 · · · RM ]without Rm Rm
where [R1 R2 · · · RM ] represents the resistance of all resistors R1, R2, . . . , RM in parallel.
Hence, due to input vim ,

Rf [R1 R2 · · · RM ]
vom = 1 + vim (5.4.20)
Rd Rm
The total output voltage is

M M
Rf vim
vo = vom = 1+ [R1 R2 · · · RM ] (5.4.21)
m=1
Rd m=1
Rm
For the special case when all these resistors are equal, i.e., when Rm = R for all m, then it follows

1
M
Rf
vo = 1 + vim (5.4.22)
Rd M m=1
which can be interpreted in the following ways:
1. A single-input noninverting amplifier gain 1+Rf /Rd that has an input equal to the average
of M inputs;
Rd Rf Figure 5.4.4 Noninverting summing amplifier.
1 −
vo
2 + 3
R1
vi1
R2
vi2
RM
viM
Copyright OUP
2. An
M-input noninverting summing amplifier for which the gain seen by each input is
1 + Rf /Rd /M.
Current-to-Voltage Amplifier
The basic circuit is shown in Figure 5.4.5, which is similar to that of an inverting amplifier (Figure
5.4.1). The − input is connected directly to a current source supplying current iS. Node X is a
virtual ground, so that
vo
iS = − (5.4.23)
Rf
Hence
vo = −Rf iS (5.4.24)
which shows that the degree of amplification depends on the value of Rf.
Current-to-Current Amplifier
The circuit given in Figure 5.4.6 is to amplify a current fed to the input of the op amp. Applying
KCL at Y,
i1 + iS = io (5.4.25)
Since i1 = −vY /R1 , Equation (5.4.25) becomes
vY
iS − = io (5.4.26)
R1
Because X is a virtual ground, vY = −iS Rf . Hence Equation (5.4.26) becomes

Rf
iS 1 + = io (5.4.27)
R1
The current gain is then given by
Rf Figure 5.4.5 Current-to-voltage amplifier.
−
iS X vo
+
Rf iS
Figure 5.4.6 Current-to-current amplifier.
Y
(Feedback resistor) RL i1
(Load
− resistor)
iS X R1
+ io
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
io Rf
=1+ (5.4.28)
iS R1
Charge-to-Charge Amplifier
A circuit is shown in Figure 5.4.7 in which there is a capacitor C1 in the − input line and a
capacitor Cf in the feedback loop. KCL at node X gives
dq1 dqf
+ =0 (5.4.29)
dt dt
where q1 and qf are charges on the input and feedback capacitors. Thus,
vo C1
q1 = −qf or C1 vi = −Cf vo or =− (5.4.30)
vi Cf
Negative Impedance Converter

The op-amp circuit of Figure 5.4.8 causes a negative resistance Rin between the input terminal
and ground. In the more general case, when R is replaced by an impedance Z, the circuit gives a
negative impedance. Using ideal op-amp techniques, one has
v1 vin
v1 = vin ; i1 = = = i2
R1 R1

R2 vo − vin R2
vo = i2 (R1 + R2 ) = vin 1 + ; i3 = = vin = −iin
R1 R RR1
so that
vin R1
Rin = = −R (5.4.31)
iin R2
Cf Figure 5.4.7 Charge-to-charge amplifier.
vi −
X vo
C1
+
R1 R2 Figure 5.4.8 Negative impedance converter.

v1
i2
i1 1 −
vo
2 + 3
iin i3
+ R
Rin vin
−
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
which is a negative resistance. The negative impedance converter is useful in transforming a

voltage source into a current source by means of a voltage-to-current converter (see Problem
5.4.9). It has also been used in a class of active filters.
Differential Amplifier
Figure 5.4.9 shows a weighted differencing amplifier, where “weighted” refers to the fact that
the output voltage has the form vo = wa va + wb vb , in which the weighting coefficients wa and
wb are the voltage gains seen by the inputs. Since the network is linear, superposition can be
applied for analysis. First, by grounding the input terminal of R3, let us make va = 0. Except
for the presence of R3 in parallel with R4, between terminal 2 and ground, the circuit is that of
an inverting amplifier of gain −R2 /R1 to the input vb. Since no current flows at terminal 2, it
follows that
R2
wb = − (5.4.32)
R1
Next, by grounding the left terminal of R1, let us make vb = 0. With respect to the voltage on
terminal 2, note that the circuit is that of a noninverting amplifier with gain 1 + R2 /R1 . The
voltage divider, consisting of R3 and R4, corresponds to a gain of R4 /(R3 + R4 ) from the input to
terminal 2. Thus the overall gain becomes

R2 R4
wa = 1 + (5.4.33)
R1 R3 + R 4
Finally, the overall response is obtained by superposition,

R2 R4 R2
vo = wa va + wb vb = 1 + va − vb
R1 R3 + R 4 R1
or

R2 1 + (R1 /R2 )
vo = va − vb (5.4.34)
R1 1 + (R3 /R4 )
When R1 /R2 = R3 /R4 ,
R2
vo = (va − vb ) (5.4.35)
R1
R1 R2 Figure 5.4.9 Weighted differencing amplifier.

vb
b
1 −
3
2 + vo
a
va
R3 R4
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
which corresponds to the response of a differential amplifier. Usually resistor values are so chosen
that R3 = R1 and R4 = R2 for some practical reasons. Improved versions of differential amplifiers
are available commercially.
Integrators
Figure 5.4.10 shows a noninverting integrator, which can be seen to be a negative impedance
converter added with a resistor and a capacitor. Noting that vo = 2v1 and i3 = v1 /R, the total
capacitor current is
vin − v1 v1 vin
i = iin + i3 = + = (5.4.36)
R R R
The capacitor voltage is given by
t t
1 1
v1 (t) = i (ξ ) dξ = vin (ξ ) dξ (5.4.37)
C −∞ RC −∞
Thus,
t
2
vo (t) = vin (ξ ) dξ (5.4.38)
RC −∞
which shows that the circuit functions as an integrator.

Replacing R2 in the inverting amplifier of Figure 5.4.1 by a capacitance C results in the
somewhat simpler integrator circuit shown in Figure 5.4.11, known as an inverting integrator, or
Miller integrator. With ideal op-amp techniques, iC = iin = vin /R. The voltage across C is just
vo, so that
R1 R1 Figure 5.4.10 Noninverting integrator.

v1
−
vo
+
R R
v1
vin
iin i3
C Negative impedance converter
i
R C Figure 5.4.11 Inverting integrator (Miller integrator).

vin
iC
iin 1 −
vo
2 + 3
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
t t
1 1
vo (t) = − iC (ξ ) dξ = − vin (ξ ) dξ (5.4.39)
C −∞ RC −∞
which illustrates that the network behaves as an integrator with sign inversion.
Differentiator
Shown in Figure 5.4.12 is a differentiator which is obtained by replacing R1 in the inverting
amplifier of Figure 5.4.1 by a capacitor C. Assuming ideal op-amp characteristics, one has i = iC
and vo = −Ri = −RiC . But since iC (t) = C dvin (t) /dt, we get
dvin (t)
vo (t) = −RC (5.4.40)
dt
which corresponds to a differentiator with a gain of −RC. In practice, however, differen-
tiators are normally avoided because of high-frequency noise (which is accentuated due to
a transfer function that increases with frequency) and stability problems (which make them
oscillate).
Inductorless (Active) Filters

Filters (used to pass or eliminate certain frequency components of a signal) that are suitable
for IC fabrication, but which do not contain inductors, are known as active filters. They have
the op amp as a common component. Figure 5.4.13 shows the basic op-amp circuit with
frequency-dependent impedances. The voltage gain or voltage transfer function of this circuit
is given by
vo Zf
=− (5.4.41)
vi Zi
with Zi = Ri and Zf = Rf (1/j ωCf ) (i.e., Rf and Cf in parallel). We have a low-pass
filter with
vo Rf 1 Rf 1
=− =− (5.4.42)
vi Ri 1 + j ωRf Cf Ri 1 + (jf/fl )
C R Figure 5.4.12 Differentiator.

vin
i
iC 1 −
vo
2 + 3
Zf Figure 5.4.13 Basic op-amp active filter.
+ Zi −
+
vi +
vo
− −
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
where
1
fl = (5.4.43)
2π Rf Cf
The magnitude
* *
* vo * Rf 1
* *=
*v * Ri 1 + (f/fl )2
i
is sketched in Figure 5.4.14, from which one √ can see that at the half-power or 3-dB point of fl,
the dc value Rf /Ri goes down by a factor of 1/ 2 or 0.707.
With Zf = Rf and Zi = Ri + 1/j ωCi (i.e., Ri and Ci in series), we have a high-pass filter
for which we obtain
vo Rf jf/fh
=− (5.4.44)
vi Ri 1 + (jf/fh )
where
1
fh = (5.4.45)
2π Ri Ci
and
* *
* vo * Rf 1
* *= (5.4.46)
*v *
i R i 1 + (fh /f )2
which is sketched in Figure 5.4.15. Note that the high-frequency gain is Rf /Ri, as in the low-filter
case, and the half-power or 3-dB point is fh.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
vo Figure 5.4.14 Frequency response of voltage-gain magni-
vi tude of a low-pass active filter.
Rf
Ri
Rf
0.707
Ri
f
fl
vo Figure 5.4.15 Frequency response of voltage-gain

vi magnitude of a high-pass active filter.
Rf
Ri
Rf
0.707
Ri
f
fh
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vo Figure 5.4.16 Bandpass filter seen as a combina-

vi tion of low-pass and high-pass filter characteris-
Resultant tics.
bandpass
characteristic
Low pass High pass
f
f0
By using a low-pass and a high-pass filter and overlapping their transfer functions, as shown
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
in Figure 5.4.16, one can construct a bandpass filter with

+
+ 1 Rf
Zf = Rf + + j ωC = 1 + j ωR C (i.e., Rf and Cf in parallel)
f f f
and
1
Zi = Ri + (i.e., Ri and Ci in series)
j ωCi
in which case
vo Zf Rf 1
=− =− (5.4.47)
vi Zi Ri 1 + j ωRf Cf [1 + 1/ (j ωRi Ci )]
Denoting
1
fl = (5.4.48a)
2π Ri Ci
and
1
fh = (5.4.48b)
2π Rf Cf
Equation (5.4.47) can be rewritten as
vo Rf 1
=−
vi Ri (1 + fl /fh ) + j (f/fh − fl /f )
Rf fh /(fh + fl )
=− (5.4.49)
Ri 1 + j (f − fl fh )/[f (fl + fh )]
2
whose magnitude is sketched in√ Figure 5.4.17. Notice that the magnitude response is a maximum
with a value of Rf /Ri at f0 = fl fh , and if fl << fh , then the magnitude becomes (0.707Rf /Ri
at fl and fh. The bandwidth (BW) may then be defined as
Copyright OUP
vo Figure 5.4.17 Frequency response of voltage-

vi gain magnitude of a bandpass active filter.
Rf
Ri
Rf
0.707
Ri
f
fl f0 fh
BW
BW = fh − fl , for fl << fh
Analog Computers
Although not used as much as the digital computer (which nowadays forms the basic tool for
numerical analysis and the solution of algebraic as well as differential equations), the analog
computer still retains some significant advantages over the digital computer. A physical system
can be represented by a set of differential equations which can be modeled on an analog computer
that uses continuously varying voltages to represent system variables. The differential equation
is solved by the computer, whereas the modeled quantities are readily varied by adjusting passive
components on the computer. The mathematical functions (integration, addition, scaling, and
inversion) are provided by op amps.
The analog computer components are shown in Figure 5.4.18. Let the ordinary differential
equation to be solved be
d 2 y (t) dy (t)
2
+ a1 + a2 y (t) = f (t) (5.4.50)
dt dt
which can be rearranged by isolating the highest derivative term as
ÿ = −a1 ẏ − a2 y + f (5.4.51)
subject to the initial conditions
y (0) = y0 (5.4.52a)
and
*
dy **
= y1 (5.4.52b)
dt *t=0
The simulation of the solution is accomplished by the connection diagram of Figure 5.4.19. Time
scaling is done by redefining t as t = ατ , in which case the differential equation [Equation
(5.4.50)] becomes
d 2 y (τ ) dy (τ )
2
= −αa1 − α 2 a2 y (τ ) + α 2 f (τ ) (5.4.53)
dτ dτ
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
Rf
Ri
+ − x y
+ A
vi +
vo Rf
A= R
− − i
y = −Ax
(a)
vi R + k
kvi
− −
(b)
R1 Rf
v1
R2
v2
... x1 a1
Rn − x2 a2 y
vn + .. .. 1
+ xn an
vo
− y = −a1x1 − a2x2 − ... −an xn
(c)
VC (0)
+ −
y(0)
Cf
Ri
+ − x y
+ 1
vi +
vo
1 t
− − y(t) = − R C ∫ 0 x (τ) d τ + y(0)
i f
(d)
Figure 5.4.18 Analog computer components. (a) Basic op amp to provide integer multiplication. (b) Po-
tentiometer for providing noninteger gains of less than 1. (c) Summer. [Note: y = x1 + x2 + · · · + xn , by
choosing Rf /R1 = Rf /R2 = · · · = Rf /Rn = 1.] (d) Integrator. [Note: Cf is charged to an initial value
t
VC(0) to provide the initial condition on y; with Ri Cf = 1, y = − 0 x (τ ) dτ + y (0).]
The coefficients may simply be scaled by the appropriate factors to change the solution time of
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
the analog computer. For example, if α = 20, then t = 20 s corresponds to τ = 1 s, and thus the
solution time may be reduced.

Copyright OUP
−y1 y0
.. . . t .. . t .
y = −a1 y − a2 y + f y = −∫ 0 yd τ + y(0) y = −∫ 0 yd τ − y(0)
f (t) −f
−1 .. .
y −y y
. 1 1 1
a2y a1y
Summer Integrator Integrator
.
y
a1 1
Multiplicative constants
a2
Figure 5.4.19 Connection diagram for analog computer simulation for solving the second-order differential
equation ÿ = −a1 ẏ − a2 y + f subject to initial conditions y (0) = y0 and ẏ (0) = y1 .
• Amplifier block as a two-port device and its circuit model.

• Ideal operational amplifier and its characteristics.
• Analysis and design of simple amplifier circuits including feedback.
• Properties of practical op-amps.
• Op-amp applications, including active filters.
• Understanding the operation of analog computers.
Automotive Power-Assisted Steering System

In terms of negative feedback, there exists an analogy between the operational amplifier and
the power-steering mechanism of an automobile. The hydraulic pump is analogous to the power
supply in an op-amp circuit. The position of the booster-cylinder piston that is linked to the steering
is analogous to the op-amp output signal; the mechanical linkage between the control valve and
the booster-cylinder piston is analogous to the feedback circuit; the control-valve response to the
difference between the input from the steering wheel and the position of the steering linkage is
analogous to the op-amp response to its differential input signal. Thus the automotive power-
assisted steering system is but an example of negative feedback in a mechanical sense.
Figure 5.6.1 illustrates in a simplified manner how a hydraulic pump driven by the engine
continuously supplies pressure to a control valve which in turn supplies the fluid to the two sides
of the booster cylinder. A negative feedback path is established from the booster cylinder through
the mechanical linkage back to the control valve.
For straight steering, the pressure applied is equal on both sides of the cylinder and, as such,
no turning force results. When the steering wheel is moved by the driver to turn the wheels in the
desired direction, more pressure is applied to one side of the cylinder or the other.
A mechanical feedback arm from the steering linkage causes the valve to return to its neutral
position as the wheels turn, thereby allowing the driver to make a gradual turn. As and when the
steering wheel is turned, the wheels move a proportional amount rather than moving all the way
to the extreme position.
Feedback control systems are discussed in Section 16.2 in more detail.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
Booster
cylinder
Frame Piston linked to steering
Control
valve
Steering
wheel Mechanical
feedback
linkage arm
Hydralic Fluid path for
pump one direction
Figure 5.6.1 Simplified representation of an automotive power-assisted steering system.
PROBLEMS
5.1.1 (a) Determine the voltage at A in Figure P5.1.1. (b) With Vi = 2 V, R1 = R2 = 2.5 k-, R3 =
5 k-, and A = 100, find vout.
(b) With Vi = 10 V, R1 = 10 k-, R2 = 1000 -,
and A = 100, find the current i2. 5.1.4 Determine the Thévenin resistance viewed from
terminals A–B of the circuit of Figure P5.1.4 by
5.1.2 Consider the circuit configuration shown in Figure setting independent sources to be zero and apply-
P5.1.2. Let Vi = 1 V, R1 = 1000 -, R2 = 2000 -, ing a test voltage at terminals A–B.
and A = 3.
*5.1.5 Show that any amplifier represented by the model
(a) Compute i2. of Figure 5.1.1 of the text can also be represented
by the more general hybrid model of Figure P5.1.5.
(b) If R1 changed to 500 -, recompute i2. Evaluate the four parameters of the hybrid model
5.1.3 (a) Find vout in the circuit shown in Figure P5.1.3. (i.e., ri, ro, hf, hr) in terms of Ri, Ro, and A.
A Figure P5.1.1
+
Vi R1 i1 Ai1 R2
− i2
+ + Figure P5.1.2
+ +
Vi R1 v1 Av1 R2 i2 v2
− −
− −
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
PROBLEMS 259
5.1.6 Consider Example 5.1.2. Let A = 1 and Ri = Ro . (b) Determine the output resistance of the circuit.
Show that no matter what values of RTh and RL are *5.1.9 (a) Two amplifiers, which can be represented by
used, the power gain as defined in that example is the model of Figure 5.1.1 of the text, are con-
less than unity, and find the maximum value it can nected in cascade (that is, head to tail), as
have. shown in Figure P5.1.9. Let their parameters
5.1.7 (a) Figure P5.1.7 shows a circuit containing an be Ri1, Ro1, A1, and Ri2, Ro2, A2, respectively.
amplifier block. Find the open-circuit voltage Find vx /v1.
amplification of the circuit. (b) Discuss how the answer is influenced by the
(b) Let the output terminals be connected to a load ratio Ri2/Ro1, particularly when this ratio ap-
resistance RL . Find the input resistance Ri . proaches zero or infinity.
5.1.8 (a) Consider the amplifier block in the circuit 5.1.10 Reconsider Problem 5.1.9. If we define a power
configuration of Figure P5.1.8. Find an ex- gain GP as the ratio of the power dissipated in RL
pression for v2/v1 in terms of Ri, Ro, and A of to the power produced by the source v1, find an
the amplifier.
R1 R2
A
vout
+ R1 + i1 A
Ai1
Vi R2 i1 R3 v1(t) Ai1
− − B
+ +
ii
+
vin vout
A ri + C
R1
hr vo hf i i ro vo
− − −
B D
−
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Figure P5.1.8
+
A Amplifier C
+ (in) block (out) v2
v1 D
−
−
B
i1 Figure P5.1.9
+ +
+
v1 Amplifier v2 Amplifier RL iL vx
1 2
−
−
−
Copyright OUP
expression for GP for the case when Ri1 = Ri2 = at which GV has dropped 6 dB below its max-
Ri , and Ro1 = Ro2 = Ro . imum value.
5.1.11 Consider Example 5.1.4. For what value of V out is 5.2.1 Using the ideal op-amp technique, find the closed-
the power dissipation maximum? loop voltage amplification A for the circuit shown
5.1.12 In the circuit of Example 5.1.4 let vin = 1−0.5 cos in Figure P5.2.1.
ωt. Determine the time-averaged power dissipated 5.2.2 Find vo in the circuit shown in Figure P5.2.2 by
in the amplifier. using the ideal op-amp technique.
*5.1.13 In the circuit of Example 5.1.4, what is the smallest 5.2.3 In the circuit shown in Figure P5.2.3, use the ideal
value of RL so that no matter what value vout takes op-amp technique to find:
in the range of 0 to 20 V, the power dissipation in
the amplifier never exceeds 50 mW? (a) vo as a function of vi.
5.1.14 (a) An audio amplifier with Ri = 10 k-, Ro = 0, (b) The voltage at A.
and Ā (ω), as shown in Figure 5.1.13(a), is *5.2.4 Determine the open-circuit output voltage vo of the
used in the circuit shown in Figure P5.1.14 system shown in Figure P5.2.4 as a function of the
with RS = 1 k-, RL = 16 -, and C = input voltage vi.
0.2 µF. Sketch GV(f ) versus* frequency
* * * if 5.2.5 Find the gain vo /vi for the circuit shown in Figure
GV(f ) is defined by GV (f ) = *V̄L * / *V̄S *.
P5.2.5 and comment on the effects of R3 and R4 on
(b) Find f max for this circuit if f max, the maximum the gain.
usable frequency, is defined as the frequency
RS Figure P5.1.14
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
+
+
−− −− −−
VS C Vin RL VL
−
−
R2
RF
R1 −
vo
vi +
−
vo
R3 +
I
Figure P5.2.3
− − +
vo
vi + A
2V
Copyright OUP
PROBLEMS 261
5.2.6 Determine vo /vi for the circuit shown in Figure terminal at terminal 3) between terminal 3 and
P5.2.6 if the op amps are ideal. ground to measure voltages accurately between
1 and 10 V. Let Ri = 1 k- and vi = 10 V
5.2.7 Find vo /vi for the circuit shown in Figure P5.2.7 if
(dc). Determine the relation between voltage in-
the op amp is ideal.
dication and Rf, noting that this circuit is an elec-
5.2.8 Consider the inverting amplifier of Example 5.2.1. tronic ohmmeter capable of measuring the value
Let a voltmeter be connected (negative voltmeter of Rf.
RF1 RF2 Figure P5.2.4
C − B −
vo
vi + A R2 +
R1
R1 R2 Figure P5.2.5
vi
1 − va R3
vo
2 +
Ideal R4
op amp
500 Ω 1000 Ω 2000 Ω

vi
500 Ω
− −
vo
+ +
R2 Figure P5.2.7
i
ii i1
v1 v2
vi +
vo
RS R1 −
R3
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*5.2.9 Consider the noninverting amplifier of Example sinusoidal signals, obtain a general expression for
5.2.2. Let Ri = 1 k- and Rf = 2 k-. Let the op Ā = V̄o /V̄i in terms of the op-amp parameters
amp be ideal, except that its output cannot exceed Ā, Ri , and Ro and the impedances Z̄1 and Z̄F . In
±12 V at a current of ±10 mA. the limit, as Ri → ∞, Ro → 0, and A → ∞,
(a) Find the minimum load resistor that can be what is the effect on the result? Considering the
added between terminal 3 and ground. high-frequency response, without the assumption
of A → ∞, find an expression for Ā .
(b) Determine the largest allowable magnitude
for vi when using the minimum load resis- 5.3.1 Figure P5.3.1 gives the frequency-response graphs
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
tance. for a 709 op amp. Choose compensating compo-
5.2.10 An op amp has an open-loop frequency response
nents for the circuit (see Figure 5.3.8) to have a
as shown in Figure 5.2.4. gain of 100 and a frequency response of up to 100
kHz.
(a) Find the approximate bandwidth of the circuit
5.3.2 Find the maximum amplitude of an output voltage
using this op amp:
sine wave that an op amp with a slew rate of 0.5
(i) With a closed-loop voltage gain of 100; V/µs can deliver at f = 100 kHz.
(ii) With a voltage gain of 1000. *5.3.3 An op amp has a slew rate of 0.7 V/µs. Find the
(b) Determine the gain–bandwidth product for maximum amplitude of an undistorted output sine
this op amp. wave that the op amp can produce at a frequency of
5.2.11 Consider the generalized circuit shown in Fig- 50 kHZ. Also determine the maximum frequency
ure P5.2.11, which contains two elements with of undistorted output that the op amp will produce
impedances Z̄1 and Z̄F . Using the phasor tech- at an amplitude of 3 V.
niques to study the response of op-amp circuits to
− Figure P5.2.11
ZF
−
+ Z1 −
+
− +
Vi −
Vo
− −
80 Figure P5.3.1 Frequency response

VS = ±15 V for various parameters (709). Source:
TA = 25° C Fairchild.
C1 = 10 pF, R1 = 0, C2 = 3 pF
60
Closed-loop voltage gain, dB
C1 = 100 pF, R1 = 1.5 kΩ, C2 = 3 pF

40
C1 = 500 pF, R1 = 1.5 kΩ, C2 = 20 pF

20
C1 = 5000 pF, R1 = 1.5 kΩ, C2 = 200 pF

0
−20
100 1k 10 k 100 k 1M 10 M
Frequency, Hz
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PROBLEMS 263
5.3.4 In order to minimize output voltage offsets in shown in Figure P5.3.4(b). Show that it is
practical op-amp circuits, one provides a dc path desirable to choose R3, which is equal to a
from each input terminal to ground, makes each parallel combination of R1 and R2. Compare
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
input terminal see the same external resistance the residual output voltage to what occurs if
to ground, and uses external balancing circuits, R3 were zero.
if necessary, to null any remaining output offset (c) Reconsider the circuit of part (b). Let R1 =
voltage. 5 k-, and R2 = 70 k-. Let the op-amp bias
(a) Consider the input-offset voltage-nulling cir- currents be Ib1 = 50 nA and Ib2 = 60 nA, but
cuit for an inverting amplifier shown in Figure otherwise let the op amp be ideal. Determine
P5.3.4 (a). Let R1 = 1.5 k-, R2 = 22 k-, the value of R3 that should be used. Also, when
R6 = 100 k-, R5 = 500 k-, R4 = 200 -, the input signal is zero, find the residual output
and V = 12 V. Find the range of input offset offset voltage.
voltages that can be generated at terminal 2 of 5.3.5 A noninverting op-amp circuit and its closed-loop
the op amp. Also find R3 such that the input representation are given in Figure P5.3.5. Obtain
terminals see the same external resistance to an expression for the closed-loop transfer function
ground. H (ω) = Y (ω)/X(ω) and comment on how it
(b) To examine the effects of input bias currents behaves for large loop gain [i.e., when the product
on the inverting amplifier, consider the circuit H 1(ω)H 2(ω) is large].
R1 R2 Figure P5.3.4
vi
1 −
+V vo
2 +
R3
R5
R6 3
R4
−V
(a)
I1 v1 I2
R1 R2
1 −
Ib1
Ib2 v2 vo
+
R3 2
Ib2
(b)
Copyright OUP
*5.4.1 An op amp has a finite gain of only 50, but is R2 = 40 k- instead of 30 k-, and sketch vo.
otherwise ideal. For the inverting-amplifier circuit 5.4.4 Consider the op-amp circuit of Figure P5.4.4.
of Figure 5.4.1, if R2 = 20 k-, what value of R1 Sketch the waveforms of vS and vo, if vS is a
would be needed to give a gain of −15? If the op sinusoidal voltage source with a peak value of 2 V.
amp’s gain could be increased by 20%, find the
5.4.5 In the ideal inverting summing amplifier circuit
new gain.
(see Figure 5.4.3) with two inputs, for Rf =
5.4.2 Consider an inverting-amplifier circuit with posi- 10 k-, find R1 and R2 so that vo = −10vi1 − 5vi2 .
tive noninverting input, as shown in Figure P5.4.2 5.4.6 Consider Figure 5.4.4 of the noninverting sum-
with values. Obtain vo. ming amplifier. Let Rm = (m + 0.5)50 -, m =
5.4.3 Let vS in Problem 5.4.2 be a sine wave of peak 1, 2, 3, 4, and 5. Also let Rd = 50 - and Rf =
voltage 3 V. Sketch vo. Rework the problem with 3 k-. Find vo.
Input Forward network y (t)

x (t) + A(ω) y (t) x (t) + Ao output
x (t) A(ω)
Σ Σ H1(ω) =
+ H1(ω) I + j(ω/ωh )
y (t) − − xe(t)
−
R2
R1
H2(ω) =
xf (t) R1 + R2
R2
R1 R1 Feedback network
H2(ω)
Figure P5.3.5
R2
i
Figure P5.4.2
30 kΩ
R1 +15 V
i B
vS = 3 V −
vo
10 kΩ +
A
−15 V
1V
R2 Figure P5.4.4
2 MΩ
R1 +10 V
−
B vo
1 MΩ
A +
−10 V
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
vS 1.5 V
(2 V peak)
Copyright OUP
PROBLEMS 265
*5.4.7 In the noninverting summing amplifier of Figure input resistance between terminals a and b of the
5.4.4, let Rd = 1 k- and M = 6. Find Rf so that circuit.
,
vo = 6m=1 vim . 5.4.13 In the circuit shown in Figure P5.4.13 with an ideal
5.4.8 An inverting amplifier is designed with three in- op amp, find vo as a function of va and vb.
puts, v1, v2, and v3, as shown in Figure P5.4.8. De- 5.4.14 For the low-pass filter configuration of Figure
termine the output voltage. Then indicate how the 5.4.13, with Ri = Rf = 1 M-, calculate Cf such
circuit may be modified to perform as a summer. that the 3-dB point is at 1 kHz.
5.4.9 A negative impedance converter is used, as shown 5.4.15 For the high-pass filter configuration of Figure
in Figure P5.4.9. Show that the load current iL 5.4.13, with vo/vi = 2.5 at 10 MHz and Ci = 100
is given by vin/R, which is independent of ZL. pF, determine Ri and Rf to yield a 3-dB point at 1
Note that since the load sees a current source, the MHz.
network is a voltage-to-current converter.
5.4.16 Comment on the behavior of the circuit of Figure
5.4.10 Determine how Equation (5.4.31) will be affected
P5.4.16 at low and high frequencies.
if the op amp of the negative impedance converter
(Figure 5.4.8) has a finite gain A0 but is otherwise *5.4.17 The input resistance of an ideal op amp with no
ideal. feedback is infinite. Investigate the input resis-
tance of an op amp with a feedback resistance RF:
5.4.11 Find the input impedance Z in for the general-
ized impedance converter circuit shown in Figure (a) When there is no resistance placed in the −
P5.4.11 if the op amps are ideal. input line.
*5.4.12 Consider Figure 5.4.9 of the weighted differencing (b) When a resistance R1 is placed in the − input
amplifier. Let R3 = R1 and R4 = R2. Determine the line.
R1 R1
Ideal
op amp
−
v1 R1 RF +
v2 R2 − vin
X vo
+ R iL R
v3 R3
ZL
R
Figure P5.4.11
Op amp
2
− +
i1
vin Z1 Z2 Z3 Z4
v1 v2 v3 v4
i2
Z in i3 i4
Z5 i5
+ −
Op amp
1
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CF
100 Ω 200 Ω
v R1 C1 RF
vb
i1 vi −
vo
− +
vo
+
i2
va
100 Ω v 500 Ω
C = 0.2 µF
C i S
R1 +15 V
vS = 5 V −
R +15 V B vo
i 40 kΩ A +
vS − −15 V
B vo
A + 3V
−15 V
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
5.4.18 Consider the inverting integrator circuit shown in *5.4.22 Develop an analog computer simulation diagram
Figure P5.4.18. Let C = 0.4 µF and R = 0.1 M-. to solve the differential equation
Sketch vo for a period of 0.5 s after the application d 2 y (t) dy (t)
of a constant input of 2 V at the vS terminal. + 12 + 5y (t) = 10
dt 2 dt
Assume that C is discharged at the beginning of
the operation. with y(0) = 2 and ẏ(0) = 0.
5.4.23 If the solution to the differential equation of Prob-
5.4.19 An integrator with positive voltage on a noninvert-
lem 5.4.22 is to be obtained over 0 ≤ t ≤ 1 ms,
ing input is shown in Figure P5.4.19. Sketch vo for
but one wants to expand this over an interval of 1 s,
60 ms after S has been opened.
redraw the analog computer simulation diagram.
5.4.20 Addition and integration can be combined by the
5.4.24 An integrator as shown in Figure 5.4.18(d) is to be
summing integrator circuit shown in Figure
designed to solve
P5.4.20. With the given component values and
input waveforms, sketch vo when S is opened at dy (t)
+ 2000y (t) = 0
t = 0. dt
5.4.21 Refer to the noninverting amplifier circuit of Fig- with y(0) = 5. If Ri is chosen to be 10 k-, find Cf.
ure 5.4.2. Let R1 = 10 k-, R2 = 30 k-, and vi 5.4.25 Determine I in the circuit shown in Figure P5.4.25.
be a sinusoidal source with a peak value of 1 V.
Sketch the waveforms of vi and vo.
Copyright OUP
PROBLEMS 267
Figure P5.4.20 (a) Circuit. (b) Waveforms

i S of v1 and v2.
C = 0.5 µF
R1 = 5 kΩ i1 i
v1 −
vo
v2 +
i2
R2 = 1 kΩ VA 2V
(a)
5V
v1 1 2 3
0 t, ms
0 v2
−5 V
(b)
1Ω Figure P5.4.25
+
−
1Ω
2Ω
I
+
10 V
−
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
6 Digital Building Blocks
and Computer Systems
6.1 Digital Building Blocks
6.2 Digital System Components
6.3 Computer Systems
6.4 Computer Networks
6.6 Practical Application: A Case Study—Microcomputer-Controlled Breadmaking Machine
Problems
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Whereas a continuous change from one value to another is the essential characteristic of an
analog signal and continuous-state (analog) circuits are used to process analog signals, signals
represented by discrete amplitudes at discrete times are handled by discrete-state (digital) circuits.
Analog systems process the information contained in the time function, which defines the signal,
whereas digital systems, as the name implies, process digits, i.e., pulse trains, in which the
information is carried in the pulse sequence rather than the amplitude–time characterization of the
pulses. Figure 6.0.1 illustrates continuous signals, whereas Figure 6.0.2 depicts discrete signals.
Consider Figure 6.0.1(a) to be a voltage signal (as a function of a continuous-time variable
t) representing a physical quantity, such as the output voltage of a phonograph cartridge. The
discrete signal (which exists only at specific instances of time) of Figure 6.0.2(a) has the same
amplitude at times t = 0, T 1, T 2, and T 3 as does the continuous signal of Figure 6.0.1(a). Figure
6.0.2(a) represents the sampled-data signal obtained by sampling the continuous signal at periodic
intervals of time. The sequence of pulses in each time interval in Figure 6.0.2(b) is a numeric,
or digital, representation of the corresponding voltage samples shown in Figure 6.0.2(a). Figure
6.0.1(b) may be considered as the signal, called a clock, which sets the timing sequence used in
the generation of the pulses shown in Figure 6.0.2.
An analog signal is an electric signal whose value varies in analogy with a physical quantity
such as temperature, force, or acceleration. Sampling of an analog signal makes it discrete in time.
A digital signal, on the other hand, can only have a finite number of discrete amplitudes at any
given time. Through a process known as quantization, which consists of rounding exact sample
268
Copyright OUP
DIGITAL BUILDING BLOCKS AND COMPUTER SYSTEMS 269
v1 v2
3
T2
2
1
T4
0 t
−1
T1
−2 t
0 T1 T2 T3 T4
−3 (b)
T3
(a)
Figure 6.0.1 Continuous signals.
v3 v4
1
T1 T3 T4
0 t t
T2 0 T1 T2 T3 T4
−1 (b)
−2
−3
(a)
Figure 6.0.2 Discrete signals.
values to the nearest of a set of discrete amplitudes called quantum levels, a digitized signal can
be obtained as discussed in more detail in Section 15.3.
The most common digital signals are binary signals. A binary signal is a signal that can take
only one of two discrete values and is therefore characterized by transitions between two states.
Figure 6.0.3 displays typical binary signals.
Voltmeters, for example, can be of either analog or digital (digital voltmeter, or DVM)
variety. While the speedometer of a car is an analog device, the odometer (which records miles
or kilometers) is digital because it records changes in units of one-tenth of a mile or kilometer. A
toggle switch which is either on or off is digital, whereas the dimmer switch is analog because it
allows the light intensity to be varied in a continuous way.
Digital electronic circuits have become increasingly important for several reasons. The
present-day integrated-circuit (IC) technology allows the construction of an enormous number of
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270 DIGITAL BUILDING BLOCKS AND COMPUTER SYSTEMS
f(t)
f1 = 1
f0 = 0 t
t0 t1 t2 t3 t4 t5 t6
(a)
v v v
+5
+5 0
0 t
−5
0 t −5 t
(b) (c) (d)
Figure 6.0.3 Typical binary signals.
transistors and diodes, as well as resistors and capacitors, on a very small chip (no larger than a
pencil eraser). The variety of ICs available to process digital signals can contain a few to several
thousand components on a single chip. A convenient method of digital IC classification, based
on the number of components per chip, is as follows:
1. Small-scale integration (SSI), containing fewer than 100 components

2. Medium-scale integration (MSI), containing 100 to 1000 components
3. Large-scale integration (LSI), containing 1000 to 10,000 components
4. Very large-scale integration (VLSI), containing more than 10,000 components
Digital computers and other large digital systems use mostly LSI and MSI chips. The number
of components per chip has increased from about 100 in the 1960s to 108 in the 1990s. Speed,
power consumption, and the number of gates (switches) on the chip are three of the more important
characteristics by which digital ICs are compared.
The general-purpose digital computer is the best known example of a digital system. Other
examples include teletypewriters, word processors, dial-telephone switching exchanges, fre-
quency counters, remote controls, and other peripheral equipment. Manipulation of finite, discrete
elements of information is a characteristic of a digital system. Information in digital systems is
represented by signals (currents or voltages) that take on a limited number of discrete values and
are processed by devices that normally function only in a limited number of discrete states. A
great majority of present digital devices are binary (i.e., have signals and states limited to two
values) because of the lack of practical devices capable of performing reliably in more than two
discrete states. Transistor circuitry, which can be constructed with extreme reliability, has two
possible signal values, either on state or off state. With the advent of transistors, the computer
industry flourished.
To start with, this chapter presents basic digital building blocks, which are usually designed to
process binary signals. Then the digital system components are discussed. Later on an introduction
to computer systems and networks is included. Thus, a basic foundation of digital systems is laid
out for the reader.
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6.1 DIGITAL BUILDING BLOCKS 271
6.1 DIGITAL BUILDING BLOCKS

The primary advantage of digital technology is the low cost, simplicity, and versatility of the
digital building blocks. Because digital signals have a finite number of discrete amplitudes at any
given time, distinctive digital building blocks are developed to process them. Digital systems are
built by repeating a very few simple blocks. The approach becomes very powerful because the
blocks (mass-produced in enormous numbers) are inexpensive in IC form and can be repeated
thousands of times.
The two-state nature of digital technology makes the binary number system its natural tool.
In a binary system there are only two digits, namely, 0 and 1. The vast majority of present digital
computers use the binary system, which has two binary digits (bits), 0 and 1. Internal representation
of information in a digital computer is in groups of bits. Besides the binary system (base 2), in
the digital world, the most commonly used number systems are octal (base 8) and hexadecimal
(base 16).
EXAMPLE 6.1.1
A signal stands for 0110 with positive logic in which low stands for 0 and high stands for 1. If
negative logic (in which low stands for 1 and high stands for 0) is used, what digits are represented
by the signal?
Solution
The signal sequence reads: low–high–high–low. With negative logic, the signal stands for 1001.
EXAMPLE 6.1.2
If the time occupied in transmitting each binary digit is 1 µs, find the rate of information
transmission if 1 baud is equal to 1 bit per second (bit/s).
Solution
Since the time per digit is 1 × 10−6 s, one can transmit 106 digits per second. The information
rate is then 1 × 106 bits, or 1 megabaud (M baud). Note that speeds of over 100 M baud are quite
possible.
Number Systems
A number system, in general, is an ordered set of symbols (digits) with relationships defined for
addition, subtraction, multiplication, and division. The base (radix) of the number system is the
total number of digits in the system. For example, in our decimal system, the set of digits is {0, 1,
2, 3, 4, 5, 6, 7, 8, 9} and hence the base (radix) is ten (10); in the binary system, the set of digits
(bits) is {0, 1} and hence the base or radix is two (2).
There are two possible ways of writing a number in a given system: positional notation and
polynomial representation. For example, the number 2536.47 in our decimal system is represented
in positional notation as (2536.47)10, whereas in polynomial form it is 2 × 103 + 5 × 102 + 3 ×
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Copyright OUP
101 + 6 × 100 + 4 × 10−1 + 7 × 10−2 . The radix or base is 10, whereas the most significant digit
or bit (MSB) is 2, the least significant digit or bit (LSB) is 7; the number of integer bits (digits)
is 4, and the number of fractional bits (digits) is 2.
The binary number system has a base of 2 with two distinct digits (bits), 1 and 0. A binary
number is expressed as a string of 0s and 1s, and a binary point if a fraction exists. To convert
the binary to the decimal system, the binary number is expressed in the polynomial form and the
resulting polynomial is evaluated by using the decimal-system addition. For example,
(101101.101)2 = 1 × 25 + 0 × 24 + 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20 + 1 × 2−1
+ 0 × 2−2 + 1 × 2−3
= 32 + 0 + 8 + 4 + 0 + 1 + 0.5 + 0 + 0.125 = (45.625)10
For digital processing it is also often necessary to convert a decimal number into its equivalent
binary number. This is accomplished by using the following steps.
1. Repeatedly divide the integer part of the decimal number by 2. Use the remainder after
each division to form the equivalent binary number. Continue this process until a zero
quotient is obtained. With the first remainder being the least significant bit, form the binary
number by using the remainder after each division.
2. Repeatedly multiply the decimal fraction by 2. If 0 or 1 appears to the left of the decimal
point of the product as a result of this multiplication, then add a 0 or 1 to the binary function.
Continue this process until the fractional part of the product is zero or the desired number
of binary bits is reached.
For example, the decimal number (75)10 is converted into its binary equivalent:
Quotient Remainder
75 ÷ 2 = 37 1 LSB
37 ÷ 2 = 18 1
18 ÷ 2 = 9 0
9÷2= 4 1
4÷2= 2 0
2÷2= 1 0
1÷2= 0 1 MSB
Stop
Thus, the binary number for (75)10 is given by:

(1001011)2
↑ ↑
MSB LSB
Let us now convert the fractional decimal number (0.4375)10 into its binary equivalent:
↓ MSB of binary fraction
0.4375 × 2 = 0.8750
0.8750 × 2 = 1.7500
0.7500 × 2 = 1.5000
0.5000 × 2 = 1.0000
Stop
↑ LSB of binary fraction
Thus, (0.4375)10 = (.0111)2.

For representing binary data, octal and hexadecimal numbers are used. The octal number
system is a base-8 system and therefore has 8 distinct digits {0, 1, 2, 3, 4, 5, 6, 7}. It is expressed
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as a string of any combination of the 8 digits. In order to convert octal to decimal, one follows the
same procedure as for converting from binary to decimal, that is, by expressing the octal number
in its polynomial form and evaluating that polynomial by using decimal-system addition.
For converting from decimal to octal form, one follows the same procedure as for conversion
from decimal to binary; but instead of dividing by 2 for the integer part, one divides by 8
to obtain the octal equivalent. Also, instead of multiplying by 2 for the fractional part, one
multiplies by 8 to obtain the fractional octal equivalent of the decimal fraction. However, it
is more common to convert from binary to octal and vice versa. Binary to octal conversion
is accomplished by grouping the binary number into groups of 3 bits each, starting from
the binary point and proceeding to the right as well as to the left; each group is then re-
placed by its octal equivalent. For example, (100101111011.01011)2 is arranged as 100 101
111 011 . 010 110 (note that a trailing 0 is added to complete the last group in the fractional
↑
part). Replacing each group by its octal “decimal” equivalent, one obtains (4573.26)8. The
conversion from octal to binary is done by replacing each octal digit with its 3-bit binary
equivalent.
The hexadecimal number system is a base-16 system which has 16 distinct symbols in the
set: {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F}, where A is equivalent to 10, B to 11, , and F to 15.
A hexadecimal number is therefore expressed as a string of any combination of the 16 symbols.
To convert from hexadecimal to decimal, for example,
(2AB)16 = 2 × 162 + A × 161 + B × 160 = 2 × 162 + 10 × 161 + 11 × 160 = (683)10
(.F8)16 = F × 16−1 + 8 × 16−2 = 15 × 16−1 + 8 × 16−2 = (0.96875)10
and
(2AB.F8)16 = (683.96875)10
The conversion from binary to hexadecimal is accomplished by grouping the binary number into
groups of 4 bits each, starting from the binary point and proceeding to the right as well as to the
left. Each group is then replaced by its hexadecimal equivalent. For example,
(11101110100100.100111)2 ⇒ 0011 1011 1010 0100 . 1001 1100 ⇒ (3BA4.9C)16
The conversion from hexadecimal to binary is achieved by reversing this process. Because the
internal structures of most digital computers manipulate data in groups of 4-bit packets, the
hexadecimal system is used for representing binary data.
Since there is a need for decimal-to-binary conversion at the input of a digital device and
for binary-to-decimal conversion at the output of the device, from a user’s point of view, the
binary-coded-decimal (BCD) number system is developed for resolving the interface problem. In
a BCD number each of the decimal digits is coded in binary using 4 bits. For example,
(163.25)10 = (10100011.01)2 = (0001 0110 0011 . 0010 0101)BCD
Table 6.1.1 shows the first 20 numbers in the decimal, binary, octal, hexadecimal, and BCD
systems.
Logic Blocks
Boolean algebra, using Boolean variables (which are binary variables that can assume only
one of two distinct values, true or false), is a mathematical system with logic notation used to
describe different interconnections of digital circuits. There are two basic types of digital building
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TABLE 6.1.1 Representation of Numbers in Different Systems
Base 10 Base 2 Base 8 Base 16

(Decimal) (Binary) (Octal) (Hexadecimal) BCD
00 00000 00 00 0000 0000

01 00001 01 01 0000 0001
02 00010 02 02 0000 0010
03 00011 03 03 0000 0011
04 00100 04 04 0000 0100
05 00101 05 05 0000 0101
06 00110 06 06 0000 0110
07 00111 07 07 0000 0111
08 01000 10 08 0000 1000
09 01001 11 09 0000 1001
10 01010 12 0A 0001 0000
11 01011 13 0B 0001 0001
12 01100 14 0C 0001 0010
13 01101 15 0D 0001 0011
14 01110 16 0E 0001 0100
15 01111 17 0F 0001 0101
16 10000 20 10 0001 0110
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17 10001 21 11 0001 0111
18 10010 22 12 0001 1000
19 10011 23 13 0001 1001
blocks: logic (combinational) blocks and sequential blocks (known as flip-flops). Logic blocks
are electronic circuits that usually have several inputs and one output. The physical devices that
perform the basic Boolean operations are known as logic gates. The basic logic gates are OR,
AND, and NOT, the interconnections of which form a logic network (also known as combinational
network), which does not generally contain memory devices. The Boolean function describing a
combinational network can be easily derived by systematically progressing from the input(s) to
the output on the logic gates.
The logic OR gate is an electronic circuit realization of the Boolean OR operation, which is
represented by the symbol +. F = A + B, for example, is read as “F is equal to A OR B.” The
OR operation yields 1 if the value of any of its arguments is 1. Figure 6.1.1 shows a two-input OR
gate along with its truth table (table of combinations for the gate) and an illustration of the OR
operation. A three-input OR gate with F = A + B + C would have a truth table with eight entries,
which can be developed by the reader as an exercise.
The logic AND gate is an electronic circuit realization of the Boolean AND operation, which
is represented by the symbol · or by the absence of an operator. Thus, for example, F = A · B
(also written simply as F = AB) is read as “F is equal to A AND B.” The AND operation yields 1
if and only if the values of all its arguments are 1s. Figure 6.1.2 shows a two-input AND gate, its
truth table, and an illustration of the AND operation. A three-input AND gate with F = A · B · C
would have a truth table with 23 = 8 possible entries, which can be developed by the reader as a
desirable exercise.
The logic NOT gate is an electronic circuit realization of the Boolean NOT operation, which
is represented by a bar over the variable. F = Ā, for example, is read as “F equals NOT A.”
This operation is also known as the complement operation. Because the NOT operation is a unary
operation and simply inverts a switching variable, the NOT gate has only one input and one
output, and is also known as an inverter. Figure 6.1.3 shows a NOT gate and its truth table.
The AND operation followed by the NOT operation inverts the output coming out of the
AND gate, and is known as NAND gate, which is typically shown in Figure 6.1.4 along with its
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Off
A
On
Off
Inputs Output B
A B F +
On F
0 0 0 −
A 0 1 1
F=A+B 1 0 1
B Output F = 1 (light is on) if either A or B
Input 1 1 1
(or both) is equal to 1 (switch on)
(a) (b) (c)
Figure 6.1.1 Two-input OR gate. (a) Symbol or physical representation. (b) Truth table. (c) Illustration of
OR operation.
Off (0) Off (0)

A B
On (1) On (1)
Inputs Output +
A B F F
−
0 0 0
A Output 0 1 0
F=A⋅B 1 0 0 F = 0 (light is off)
B (also F = AB) 1 1 1 F = 1 (light is on) if and
Input
only if A = B = 1
(a) (b) (c)
Figure 6.1.2 Two-input AND gate. (a) Symbol or physical representation. (b) Truth table. (c) Illustration
of AND operation.
Input Output Figure 6.1.3 NOT gate (complement).

A F (a) Symbol or physical representation.
0 1 (b) Truth table.
A F=A
Input 1 0
Output
(a) (b)
Inputs Output Figure 6.1.4 NAND gate.

A B C F (a) Logic symbol. (b) Truth table.
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
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1 0 0 1
1 0 1 1
A 1 1 0 1
B F=A⋅B⋅C 1 1 1 0
C
(a) (b)
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truth table. Similarly, the OR operation followed by the NOT operation is known as the NOR
operation. Figure 6.1.5 shows a typical NOR gate with its truth table.
Two other logic blocks that are sometimes used are the EXCLUSIVE OR (XOR) and
EXCLUSIVE NOR (COINCIDENCE) gates. Their conventional symbols together with their
truth tables are shown in Figures 6.1.6 and 6.1.7, respectively. It is also possible to synthesize
these logic blocks by combining the basic OR, AND, as well as NOT logic gates.
The operations so far introduced are summarized in Table 6.1.2. Any Boolean function can
be transformed from an algebraic expression into a combinational network by using the basic
logic gates. It is always desirable, however, to implement a given Boolean function by using the
minimum number of components, leading to a less complex and more economical network. Table
6.1.3 gives the basic Boolean identities for which the truth tables for the expressions on either
side of the equals sign are the same. The reader should note that, in general, it is improper to draw
a diagram in which the outputs of any two blocks are connected together. Two outputs can be
combined by using them as two inputs to another gate.
Inputs Output Figure 6.1.5 NOR gate. (a) Logic

A B C F symbol. (b) Truth table.
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
A 1 1 0 0
B F=A+B+C 1 1 1 0
C
(a) (b)
Inputs Output
A B F
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0 0 0
0 1 1
A 1 0 1
F=A⊕B 1 1 0
B F=A⋅B+A⋅B
(a) (b)
Figure 6.1.6 EXCLUSIVE OR gate (XOR) (also known as binary
comparator). (a) Logic symbol. (b) Truth table. NOTE: XOR operation
yields 1 if the input A is 1 or B is 1, but yields 0 if both inputs A and B
are 1 or 0.
Inputs Output
A B F
0 0 1
0 1 0
A 1 0 0
F=A B 1 1 1
B F=A⋅B+A⋅B
(a) (b)
Figure 6.1.7 EXCLUSIVE NOR gate (COINCIDENCE) (also known
as XNOR or EQUIVALENT gate). (a) Logic symbol. (b) Truth table.
NOTE: XNOR operation yields 1 if both inputs A and B have the same
value of either 0 or 1, but yields 0 if the input A is 1 or B is 1. Hence it
is a complement of XOR gate.
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TABLE 6.1.2 Logic Symbols and Truth Tables
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The last two entries in Table 6.1.3 are known as DeMorgan’s theorems, whose importance
stems from the fact that they offer a general technique for complementing Boolean expressions.
They show that any logic function can be implemented using only OR and NOT gates, or using
only AND and NOT gates. There exists a duality between AND and OR operations; any function
can be realized by just one of the two basic operations, plus the complement operation. This gives
rise to two families of logic functions: sum of products (SOP) and product of sums (POS). Any
logic expression can be reduced to either one of these.
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TABLE 6.1.3 Basic Boolean Identities
Identity Comments
1. X + 0 = X Identities 1–9 are basic to Boolean algebra

2. X + 1 = 1
3. X + X = X
4. X + X̄ = 1
5. X · 0 = 0
6. X · 1 = X
7. X · X = X
8. X · X̄ = 0
¯ =X
9. X̄
10. X + Y = Y + X Commutative
11. X · Y = Y · X Commutative
12. X + (Y + Z) = (X + Y ) + Z Associative
13. X · (Y · Z) = (X · Y ) · Z Associative
14. X · (Y + Z) = X · Y + X · Z Distributive
15. X + Y · Z = (X + Y ) · (X + Z)
16. X + X · Y = X Absorption
17. X · (X + Y ) = X
18. X · Y + X̄ · Z + Y · Z = X · Y + X̄ · Z Consensus
19. X + Y + Z = X̄ · Ȳ · Z̄ DeMorgan
20. X · Y · Z = X̄ + Ȳ + Z̄ DeMorgan
EXAMPLE 6.1.3

For the switching function F = A Ā + B , draw a corresponding set of logic blocks and write
the truth table.
Solution
A suitable connection of logic blocks is shown in Figure E6.1.3. Using the intermediate variables,
the truth table is as follows.
Figure E6.1.3
A
A F = A (A + B)
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B A+B
A B A A+B F
0 0 1 1 0
0 1 1 1 0
1 0 0 0 0
1 1 0 1 1
EXAMPLE 6.1.4
Derive the Boolean function for the combinational network shown in Figure E6.1.4(a).
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Solution
The solution is given in Figure E6.1.4(b).
Figure E6.1.4
A
F
C
B
(a)
A
A⋅B
B
A A⋅C
F
C
F=A⋅B+A⋅C+B⋅C
B B⋅C
C
(b)
EXAMPLE 6.1.5
Prove the Boolean identity A(B + C) = AB + AC, which is distributive, by comparing the truth
tables of both sides.
Solution
The truth tables with the necessary intermediate variables are as follows:
A B C B+C A(B + C) AB AC AB + AC
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0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1
↑ Same ↑
Note: The direct representation of AB + AC would require three gates (two ANDs and one
OR). But two gates (one OR and one AND) can perform the same function, as seen from the
identity.
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EXAMPLE 6.1.6
(a) Express DeMorgan’s laws given by
X+Y =X·Y and X·Y =X+Y
in terms of logic gates.
(b) Express the sum of products given by (X · Y) + (W · Z) and the product of sums given
by (A + B) · (C + D) in terms of logic gates.
Solution
(a) Figures E6.1.6(a) and (b) show the solution.

(b) Figures E6.1.6(c) and (d) show the solution.
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Figure E6.1.6
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Thus far we have shown how to find the truth table for a given combination of logic blocks.
The inverse process, that of finding an interconnection of blocks to produce a given truth table,
is known as logic synthesis. Even though the resulting circuit is not necessarily minimal (thereby
assuming a minimum number of components), the truth table can be realized by the two standard
forms: sum of products (SOP) and product of sums (POS). SOP can be implemented by using
two-level (AND–OR) networks, where each product term requires an AND gate (except for a
term with a single variable) and the logic sum of these terms is obtained by using an OR gate with
inputs from the AND gates or the single variables. POS can be implemented by using two-level
(OR–AND) networks, where each term requires an OR gate (except for a term with a single
variable) and the product of these terms is obtained by using an AND gate with inputs from the
OR gates or the single variables.
Figure 6.1.8 shows four possible gates with an output of 1 only. For example, the truth table
of Figure 6.1.9(a) can be realized by the interconnection of gates shown in Figure 6.1.9(b) with
the resulting Boolean expression F = ĀB + AB. The SOP or the POS method can be used to
realize any truth table, but it is not efficient and minimal; usually other realizations with fewer
blocks can be found. The realization can often be simplified by using the distributive law and the
simple A + Ā = 1. For example, the expression F = ĀB + AB can be rewritten as
theorem
F = Ā + A B by means of the distributive law, and can be simplified as F = B, since Ā+A = 1.
Finding minimal realizations with a minimum number of components is the challenge in logic
design.
Addition of binary numbers is so common that a binary half-adder and a full-adder (FA)
have become building blocks in their own right, and are available in IC form. The representation
of the half-adder, which can add single-digit binary numbers, is shown in Figure 6.1.10(a) along
with its truth table. N full adders are needed to add together two N-digit binary numbers. Figure
6.1.11 illustrates the addition of 4-digit binary numbers.
A A Figure 6.1.8 Four possible gates with an output

F F of 1 only.
B B
Output 1 only if A = 1, B = 1 Output 1 only if A = 1, B = 0
(a) (b)
A A
F F
B B
Output 1 only if A = 0, B = 1 Output 1 only if A = 0, B = 0
(c) (d)
1st level 2nd level
A B F
A 0 0 0
F = AB + AB 0 1 1
B 1 0 0
1 1 1
(a) (b)
Figure 6.1.9 SOP realization of F = ĀB + AB. (a) Truth table. (b) Interconnection of gates.
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Inputs Outputs
A B C D
0 0 0 0
B D A 0 1 0 1
Half-adder +B 1 0 0 1
A C CD 1 1 1 0
(a)
Inputs Outputs
C “Carry” from B D Z W X C Y Z
previous digit Half-
adder 0 0 0 0 0
W B D A C 0 0 1 0 1
X C Z Half-
Y
adder 0 1 0 0 1
Full adder A C “Carry” to
X 0 1 1 1 0
W Y next digit
1 0 0 0 1
1 0 1 1 0
WA 1 1 0 1 0
+XB
YZD 1 1 1 1 1
(b)
Figure 6.1.10 (a) Half-adder and its truth table. (b) Full adder and its truth table.
A3 B3 A2 B2 A1 B1 A0 B0
W X W X W X W X A3 A2 A1 A0
FA C FA C FA C FA C 0 + B3 B2 B1 B0
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Y Z Y Z Y Z Y Z S4 S3 S2 S1 S0
S4 S3 S2 S1 S0
Figure 6.1.11 Addition of 4-digit binary numbers.
EXAMPLE 6.1.7
Refer to Figure 6.1.10(a) of the half-adder and its truth table for adding two single-digit binary
numbers, A and B, to yield a two-digit number CD. Using the SOP method, develop a circuit to
generate C and D.
Solution
In terms of the four possible gates (with an output of 1 only) shown in Figure 6.1.8, the circuit in
Figure E6.1.7(a) can be drawn. Note that the resulting circuit will not be minimal, as is usually
the case with the SOP method. The truth table can be realized with only three gates, using the
circuit shown in Figure E6.1.7(b). The student is encouraged to verify by constructing its truth
table.
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A
B
A
D C
B
A
B
(a)
A
B
D
A
B
C
(b)
Figure E6.1.7
The basic logic gates described earlier are used to implement more advanced functions and
are often combined to form logic blocks (or modules) which are available in compact IC packages.
Although SSI packages were common basic units at one time, the trend now is to integration on an
even larger scale. Entire digital systems, such as those to be discussed later, are now available in IC
form, and those ICs in turn become blocks for building even larger systems. The ICs are mounted
in packages known as DIPs (dual in-line packages), each with 8, 14, or more wires (pins) meant
to be plugged into corresponding pin sockets. The actual gates, with the same logic diagrams,
can be made with several different kinds of internal construction, giving rise to different logic
families. In general blocks of one family are compatible with other blocks of the same family, but
not with those of other families.
Karnaugh Maps and Logic Design

Even though a truth table uniquely represents a logic function, it is clear that the same function may
appear in different algebraic forms. While the Boolean identities can be used for the simplification
of a given algebraic form, it is desirable to have a systematic process that guarantees the minimum
form with a minimum number of components. The map method, known as the Karnaugh map or,
simply, the K map, which is a modified form of the truth table, provides a convenient procedure for
obtaining a minimum SOP or POS of a Boolean expression. The K maps are usually restricted to
up to five variables, since they become too cumbersome to manipulate for a larger number of vari-
ables. Before we get into the details of K maps, it is necessary to introduce minterm and maxterm.
When a product term contains each of the n variables of a function, it is called a minterm.
For n variables, there are 2n possible minterms. The ith minterm of n variables is denoted by mi,
where the subscript i, 0 ≤ i ≤ 2n − 1, represents the decimal equivalent of the binary number
obtained when a variable in minterm is replaced by 1 and its complement is replaced by 0.
When a sum term contains each of the n variables of a function, it is called a maxterm. The
ith maxterm of n variables, denoted by Mi, is the complement of the ith minterm mi of the same
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n variables; that is to say, Mi = mi . Table 6.1.4 lists the eight possible maxterms and minterms
of the three variables A, B, and C.
Any Boolean function can be expressed, algebraically, as a sum (OR) of minterms. An
expression of this form is known as a canonical sum of products. Given a truth table for a logic
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function, its SOP form can be obtained by taking the sum of the minterms that correspond to a 1
in the output column of the table.
Any Boolean function can also be expressed, algebraically, as a product (AND) of maxterms.
An expression of this form is known as a canonical product of sums. Given a truth table for a logic
function, its POS form can be obtained by taking the product of the maxterms that correspond to
a 0 (zero) in the output column of the table. Let us now consider an example to illustrate the use
of minterms and maxterms.
TABLE 6.1.4 Minterms and Maxterms for Three Variables
A B C i Minterm mi Maxterm Mi
0 0 0 0 Ā · B̄ · C̄ A+B +C
0 0 1 1 Ā · B̄ · C A + B + C̄
0 1 0 2 Ā · B · C̄ A + B̄ + C
0 1 1 3 Ā · B · C A + B̄ + C̄
1 0 0 4 A · B̄ · C̄ Ā + B + C
1 0 1 5 A · B̄ · C Ā + B + C̄
1 1 0 6 A · B · C̄ Ā + B̄ + C
1 1 1 7 A·B ·C Ā + B̄ + C̄
EXAMPLE 6.1.8
Given the truth table in Table E6.1.8 for an arbitrary Boolean function F, express F as a sum of
minterms and a product of maxterms.
TABLE E6.1.8
mi A B C F
m0 0 0 0 0
m1 0 0 1 1
m2 0 1 0 0
m3 0 1 1 1
m4 1 0 0 0
m5 1 0 1 0
m6 1 1 0 1
m7 1 1 1 1
Solution
Noting that F has an output of 1 that corresponds to minterms m1, m3, m6, and m7, F can be
expressed as
F (A, B, C) = m1 + m3 + m6 + m7
= Ā · B̄ · C + Ā · B · C + A · B · C̄ + A · B · C
or in a compact form as

F (A, B, C) = mi (1, 3, 6, 7)
,
where mi( ) means the sum of all the minterms whose subscript i is given inside the parentheses.
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Noting that F has an output of 0 that corresponds to maxterms M 0, M 2, M 4, and M 5, F can

therefore be expressed as
F (A, B, C) = M0 · M2 · M4 · M5
= (A + B + C) · (A + B̄ + C) · (Ā + B + C) · (Ā + B + C̄)
or in compact form as
-
F (A, B, C) = Mi (0, 2, 4, 5)
.
where Mi( ) means the product of all the maxterms whose subscript i is given inside the
parentheses.
Now coming back to the K map, a K map is a diagram made up of cells (squares), one for
each minterm of the function to be represented. An n-variable K map, representing an n-variable
function, therefore has 2n cells. Figures 6.1.12, 6.1.13, and 6.1.14 show the two-variable, three-
variable, and four-variable K maps, respectively, in two different forms. Note particularly the
code used in listing the row and column headings when more than one variable is needed.
The K map provides an immediate view of the values of the function in graphical form.
Note that the arrangement of the cells in the K map is such that any two adjacent cells contain
minterms that vary only in one variable. Consider the map to be continuously wrapping around
itself, as if the top and bottom, and right and left, edges were touching each other. For an n-variable
map, there will be n minterms adjacent to any given minterm. For example, in Figure 6.1.14, the
cell corresponding to m2 is adjacent to the cells corresponding to m3, m6, m0, and m10. It can be
verified that any two adjacent cells contain minterms that vary only in one variable. The m2 cell,
Binary Figure 6.1.12 Two-variable K maps.

A values
A A B 0 1 of A
Binary
B A⋅B A⋅B 0 m0 m2
values
B A⋅B A⋅B of B 1 m1 m3
(a) (b)
AB
AB AB AB AB C 00 01 11 10
C A⋅B⋅C A⋅B⋅C A⋅B⋅C A⋅B⋅C 0 m0 m2 m6 m4
C A⋅B⋅C A⋅B⋅C A⋅B⋅C A⋅B⋅C 1 m1 m3 m7 m5
(a) (b)
Figure 6.1.13 Three-variable K maps.
AB
AB AB AB AB CD 00 01 11 10
CD A ⋅ B ⋅ C ⋅ D A ⋅ B ⋅ C ⋅ D A ⋅ B ⋅ C ⋅ D A ⋅ B ⋅ C ⋅ D 00 m0 m4 m12 m8
(a) (b)
Figure 6.1.14 Four-variable K maps.
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for example, has an assignment of Ā · B̄ · C · D̄ (= 0 · 0 · 1 · 0), whereas the m3 cell has the
assignment of Ā · B̄ · C · D(= 0 · 0 · 1 · 1), which differs only in the value of the variable D.
A function can be represented in a K map by simply entering 1s in the cells that correspond
to the minterms of the function. This is best illustrated by an example.
EXAMPLE 6.1.9
Show the K-map representations of the following Boolean functions:
,
(a) F (A, B, C) = mi (0, 2, 3, 5, 7)
,
(b) F (A, B, C, D) = mi (1, 3, 5, 6, 9, 10, 13, 14)
Solution
Figure E6.1.9 shows the K-map representations of the functions.
AB
CD 00 01 11 10
00
AB
C 00 01 11 10 01 1 1 1 1
0 1 1 11 1
1 1 1 1 10 1 1 1
F(A, B, C) = Σ mi(0, 2, 3, 5, 7) F(A, B, C, D) = Σ mi(1, 3, 5, 6, 9, 10, 13, 14)
(a) (b)
Figure E6.1.9
Simplification of an n-variable Boolean function by using a K map is achieved by grouping

adjacent cells that contain 1s. The number of adjacent cells that may be grouped is always equal
to 2m, for 0 ≤ m ≤ n, i.e., 1, 2, 4, 8, 16, 32, . . . cells. Such a group or set of 2m cells is called a
subcube and is expressed by the product term containing only the variables that are common to
the adjacent cells. The larger the subcube is, the fewer variables are needed to express the product
term. This statement can be justified by using Boolean identities. For example, in a four-variable
K map, the following possible subcubes can be formed.
• 1-cell subcube (having one minterm) expressed by a product term containing four, or n−m,
variables; note that n = 4 and m = 0 for this case.
• 2-cell subcube (having two minterms) expressed by a product term containing three, or
n − m, variables; note that n = 4 and m = 1 for this case.
• 4-cell subcube (having four minterms) expressed by a product term containing two, or
n − m, variables; note that n = 4 and m = 2 for this case.
• 8-cell subcube (having eight minterms) expressed by a product term containing one or n−m
variables; note that n = 4 and m = 3 for this case.
• 16-cell subcube (having sixteen minterms) expressed by the logic 1; that is, the function is
always equal to 1.
Let us now present an example to illustrate the concepts related to subcubes.
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EXAMPLE 6.1.10
Consider a Boolean function F(A, B, C, D) defined by the K map of Figure E6.1.10(a). Form the
possible subcubes and express them by their corresponding product terms.
AB AB
CD 00 01 11 10 CD 00 01 11 10
00 1 00 1 A⋅B⋅C
01 1 1 1 1 01 1 1 1 1 C⋅D
A⋅D
11 1 1 11 1 1
10 1 10 1
(a) (b) A⋅B⋅C⋅D
Figure E6.1.10 (a) K map. (b) K map with subcubes.
Solution
,
Figure E6.1.10(b) shows the K map of F (A, B, C, D) = mi (1, 3, 5, 7, 8, 9, 13, 14) with
subcubes.
Observe that the four-cell subcube consisting of minterms m1, m3, m5, and m7 can be expressed
by the product term (Ā · D), since Ā and D are the only variables common to the four minterms
involved. The other subcubes shown in Figure E6.1.10(b) can be checked for their product-term
expressions. Note that any cell may be included in as many subcubes as desired.
Once a Boolean function is represented in a K map and its different subcubes are formed,
that Boolean function can be expressed as the logic SOP terms corresponding to the minimum
set of subcubes that cover all its 1 cells. Obviously then, in forming a subcube, one should not
select a subcube that is totally contained in another subcube. The product term representing the
subcube containing the maximum possible number of adjacent 1 cells in the map is called a prime
implicant. A prime implicant is known as an essential prime implicant if the subcube represented
by the prime implicant contains at least one 1 cell that is not covered by any other subcube. If,
on the other hand, all the 1 cells of a subcube of a prime implicant are covered by some other
subcubes, then such a prime implicant is known as an optional prime implicant. The minimized
Boolean expression is obtained by the logic sum (OR) of all the essential prime implicants and
some other optional prime implicants that cover any remaining 1 cells that are not covered by the
essential prime implicants.
The procedure for K-map simplification of an n-variable Boolean function may be summa-
rized in the following steps.
1. Represent the function in an n-variable K map.
2. Mark all prime implicants that correspond to subcubes of the maximum adjacent 1 cells.
3. Determine the essential prime implicants.
4. Develop the minimum expression with the logic sum of the essential prime implicants.
5. In the K map, check the 1 cells that are covered by the subcubes expressed by the essential
prime implicants.
6. No other terms are needed if all the 1 cells of the map are checked. Otherwise add to
your expression the minimum number of optional prime implicants that correspond to the
subcubes which include the unchecked 1 cells.
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Let us now illustrate the application of this procedure in the following example.
EXAMPLE 6.1.11
Obtain a minimum Boolean expression for

F (A, B, C, D) = mi (1, 3, 4, 5, 6, 7, 10, 12)
Solution
1. The K map of F is shown in Figure E6.1.11(a).
AB AB B⋅C⋅D
CD 00 01 11 10 CD 00 01 11 10
00 1 1 00 1 1
A⋅D
01 1 1 01 1 1
11 1 1 11 1 1
10 1 1 10 1 1 A⋅B⋅C⋅D
(a) (b) A⋅B
Figure E6.1.11
2. The prime implicants, as depicted in Figure E6.1.11(b), are (Ā · D), (Ā · B), (B · C̄ · D̄),
and (A · B̄ · C · D̄).
3. All prime implicants happen to be essential, since each of the subcubes contains at least
one 1 cell that is not covered by any other subcube.
4. F (A, B, C, D) = Ā · D + Ā · B + B · C̄ · D̄ + A · B̄ · C · D̄.
5. The 1 cells that are covered by the subcubes expressed by the essential prime implicants
are checked, as shown in Figure E6.1.11(b).
6. Since all the 1 cells have been checked, it follows that
F (A, B, C, D) = Ā · D + Ā · B + B · C̄ · D̄ + A · B̄ · C · D̄
The minimum POS expression for a Boolean function can be obtained easily by using K
maps in a procedure very similar to that used for the minimum SOP expression. By using the 0s
of the map and obtaining prime implicants again by using the 0 cells, this can be done. Since the
0 cells represent the compliment of the function, complementing the minimum SOP expression
for the 0s of the function yields the minimum POS form of the function. Even though the two
forms (POS and SOP) are completely equivalent, logically, one of the two forms may lead to a
realization involving a smaller number of gates.
In designing a digital system, one often encounters a situation where the output cannot be
specified due to either physical or logical constraints. Figure 6.1.15 illustrates one such situation,
where the input lines B and C to the black box of logic circuitry are physically connected together.
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For such a circuit, the input combination A = 0, B = 1, and C = 0 is not possible, and therefore
the output corresponding to this combination cannot be specified. Such an output is hence known
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as a don’t-care output because of a physical constraint. As another example, Figure 6.1.16 shows
the logic circuitry in a black box with four input lines representing BCD data. For such a circuit,
six of the input combinations (1010, 1011, 1100, 1101, 1110, and 1111) are not valid BCDs, and
therefore the output of this circuitry cannot be specified because of a logic constraint. Such outputs
are hence labeled as don’t-care outputs. A don’t-care output or condition is generally represented
by the letter d in the truth table and the K map.
The ds can be treated either as 0s or 1s when the subcubes are formed in the K map, depending
on which results in a greater simplification, thereby helping in the formation of the smallest number
of maximal subcubes. Note that some or all of the ds can be treated as 0s or 1s. However, one
should not form a subcube that contains only ds.
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A Figure 6.1.15 Physical constraint for a don’t-care condi-

Black box
B
(logic circuitry) F(A, B, C) tion.
C
A Figure 6.1.16 Logic constraint for a don’t-

BCD data B Black box care condition.
(logic circuitry) F(A, B, C, D)
C
D
EXAMPLE 6.1.12
A Boolean function F(A, B, C, D) is specified by the truth table of Figure E6.1.12 (a). Obtain:
(a) a minimum SOP expression, and (b) a minimum POS expression.
Solution
The four-variable K map of F is shown in Figure E6.1.12(b).

(a) The prime implicants (with 1 cells) for F are marked in Figure E6.1.12(c). The minimum
SOP expression is then given by
F = C̄ · D̄ + B · C̄
A B C D F Figure E6.1.12
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0 AB
1 0 1 0 d CD 00 01 11 10
1 0 1 1 d 00 1 1 d 1
1 1 0 0 d 01 0 1 d 0
1 1 0 1 d
1 1 1 0 d 11 0 0 d d
1 1 1 1 d 10 0 0 d d
(a) (b)
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AB AB
CD 00 01 11 10 CD 00 01 11 10
00 1 1 d 1 C⋅D 00 d
B⋅D
01 1 d B⋅C 01 0 d 0
11 d d 11 0 0 d d
10 d d 10 0 0 d d C
(c) A⋅D (d)
(b) The prime implicants (with 0 cells) for the complement of F are marked in Figure
E6.1.12(d). The minimum POS expression is then given by
F̄ = C + B̄ · D
Complementing both sides of this equation and using DeMorgan’s rules, one obtains
F = C̄ · (B + D̄)
Note in particular that in Figures E6.1.12(c) and (d) we did not form subcubes that covered only ds.
Sequential Blocks
Neglecting propagation delays, which are measures of how long it takes the output of a gate to
respond to a transition at the input of the gate, the output of a logic block at a given time depends
only on the inputs at that same time. The output of a sequential block, on the other hand, depends
not only on the present inputs but also on inputs at earlier times. Sequential blocks have thus a
kind of memory, and some of them are used as computer memories.
Most sequential blocks are of the kind known as multivibrators, which can be monostable
(the switch remains in only one of its two positions), bistable (the switch will remain stable in
either of its two positions), and unstable (the switch changes its position continuously as a kind
of oscillator, being unstable in both of its two states). The most common sequential block is the
flip-flop, which is a bistable circuit that remembers a single binary digit according to instructions.
Flip-flops are the basic sequential building blocks. Various types of flip-flops exist, such as the
SR flip-flop (SRFF), D flip-flop (or latch), and JK flip-flop (JKFF), which differ from one another
in the way instructions for storing information are applied.
SR FLIP-FLOP (SRFF)
The symbol for the SRFF is shown in Figure 6.1.17(a), in which S stands for “set,” R stands for
“reset” on the input side, and there are two outputs, the normal output Q and the complementary
output Q̄. The operation of the SRFF can be understood by the following four basic rules.
1. If S = 1 and R = 0, then Q = 1 regardless of past history. This is known as the set
condition.
2. If S = 0 and R = 1, then Q = 0 regardless of past history. This is known as the reset
condition.
3. If S = 0 and R = 0, then Q does not change and stays at its previous value. This is a
highly stable input condition.
4. The inputs S = 1 and R = 1 are not allowed (i.e., forbidden) because QQ̄ = 11; Q̄ is
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no longer complementary to Q. This is an unacceptable output state. Such a meaningless
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instruction should not be used. Figure 6.1.17(b) summarizes the specification for an SRFF
in terms of a truth table, in which Qn is the state of the circuit before a clock pulse and
Qn+1 is the state of the circuit following a clock pulse.
EXAMPLE 6.1.13
The inputs to an SRFF are shown in Figure E6.1.13. Determine the value of Q at times t 1, t 2,
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and t 3.
Figure E6.1.13
1
S
0
1
R
0
t0 t1 t2 t3
Solution
Notice that the value of Q at time t 0 is not given; however, it is not necessary to have this
information. The first pulse of S sets the SRFF in the state Q = 1. Thus at t = t1 , Q = 1. While
the second pulse of S tries again to set the SRFF, there will be no change since Q was already 1.
Thus at t = t2 , Q = 1. The pulse of R then resets the SRFF and then at t = t3 , Q = 0.
Flip-flops can be constructed using combinations of logic blocks. The realization of an SRFF
can be achieved from two NAND gates (plus two inverters), as shown in Figure 6.1.18. Because
of the feedback in this circuit it is not possible to simply write its truth table, as we can do for a
combinational circuit. However, a modified truth-table method can be used, in which we guess
Inputs Outputs
S R Qn+1 Qn+1
SET Normal 0 0 Qn Qn
S Q 0 1 0 1
Inputs Outputs 1 0 1 0
RESET R Q Complementary 1 1 Not allowed
(a) (b)
Figure 6.1.17 SR flip-flop (SRFF) (a) Symbol. (b) Truth table.
Figure 6.1.18 Realization of SRFF from two

S Q NAND gates.
R Q
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an output and then go back to check it for self-consistency. This is given as a problem at the end
of the chapter. Figure 6.1.18 is a realization of an SRFF in terms of a physical circuit that behaves
similarly to the ideal device called SRFF which obeys the SR instruction rules. Thus, note that
the circuit of Figure 6.1.18 cannot accurately be said to be an SRFF. While it is certainly possible
to apply the “forbidden” input (S = 1 and R = 1) to the real circuit, the circuit is then not properly
used as an SRFF.
Edge triggered SRFF symbols are illustrated in Figure 6.1.19. The triangle on the Ck (clock)
input indicates that the flip-flop is triggered on the edge of a clock pulse. Positive-edge triggering
is shown in Figure 6.1.19(a). Negative-edge triggering is indicated by the ring on the Ck input in
Figure 6.1.19(b).
D FLIP-FLOP (LATCH OR DELAY ELEMENT)

The symbol for the clocked D flip-flop is shown in Figure 6.1.20(a), in which the two output
terminals Q and Q̄ behave just as in the SRFF, and the input terminals are D and Ck (clock). The
term clocked flip-flop indicates that this device cannot change its state (i.e., Q cannot change)
unless a specific change instruction is given through the clock (Ck) input. The value of Q after the
change instruction is equal to the value of D at the time the change instruction is received. The
value of Q before the change instruction does not matter. Figure 6.1.20(b) illustrates the values
taken by Q after the change instruction for various inputs D and prior values of Q. While there
are several variations of the device, in the rising-edge triggered flip-flop a change instruction is
effected whenever the Ck input makes a change from 0 to 1. Note that only a positive-going
transition of Ck is a change instruction, and a constant Ck input is not a change instruction.
Note that flip-flops have propagation delay, which means that there is a small delay (about 20
ns) between the change instruction and the time Q actually changes. The value of D that matters
is its value when the change instruction is received, not its value at the later time when Q changes.
A convenient means of describing the series of transitions that occur as the signals set to the
flip-flop input change is the timing diagram. A timing diagram depicts inputs and outputs (as a
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function of time) of the flip-flop (or any other logic device) showing the transitions that occur
over time. The timing diagram thus provides a convenient visual representation of the evolution
of the state of the flip-flop. However, the transitions can also be represented in tabular form.
Like logic blocks, flip-flops appear almost exclusively in IC form, and are more likely to be
found in LSI and VLSI form. A very important application is in computer memories, in which a
typical 256k RAM (random access memory) consists of about 256,000 flip-flops in a single IC.
Figure 6.1.19 Edge triggered SRFF symbols.

S Q S Q
(a) Triggered on positive edge of clock pulse.
Ck Ck
(b) Triggered on negative edge of clock pulse.
R Q R Q
(a) (b)
D Q(before) Q(after) Figure 6.1.20 Clocked D flip-flop. (a) Sym-

0 0 0 bol. (b) Q for various inputs D.
D Q
0 1 0
1 0 1
Ck Q 1 1 1
(a) (b)
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EXAMPLE 6.1.14
The positive-edge triggered D flip-flop is given the inputs shown in Figure E6.1.14(a), with a zero
initial value of Q. Draw the timing diagram.
Figure E6.1.14
1
D
0
1
Ck
0
(a)
1
D
0
1
Ck
0
1
Q
0
(b)
Solution
Q is illustrated in Figure E6.1.14(b) as a function of time.
In order to avoid the input condition SR = 11, an inverter is included, as shown in Figure
6.1.21. SR can be either 01 or 10. For SR = 10, the flip-flop sets (i.e., QQ̄ = 10) whereas for
SR = 01 it resets (i.e., QQ̄ = 01). Thus, the output replicates the input state, but with a delay
equal to the time for information to propagate through the flip-flop.
Most commercially available flip-flops also include two extra control input signals known as
preset and clear. When activated, these input signals will set (Q = 1) or clear (Q = 0) the flip-
flop, regardless of other input signals. Figure 6.1.22(a) shows the block diagram of a positive-edge
triggered D flip-flop with preset and clear control signals; Figure 6.1.22(b) gives the functional
truth table for this device. Note that the clock is the synchronizing element in a digital system. The
particular device described here is said to be positive-edge triggered, or leading-edge triggered,
since the final output of the flip-flop is set on a positive-going clock transition.
Figure 6.1.23 shows a realization of the D flip-flop using six NAND gates, in which the output
part is very similar to the SRFF of Figure 6.1.18 and the other four gates are used to translate the
D-type control instructions into a form that the SRFF can use.
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Data Figure 6.1.21 Flip-flop with inverter.

S Q
R Q
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Inputs Outputs Figure 6.1.22 Positive-edge triggered

Q Q
D flip-flop with preset and clear. (a)
Preset Clear Ck D
Preset Block diagram. (b) Truth table. NOTE:
D Q 1 0 d d 1 0 d stands for don’t-care condition. The
0 1 d d 0 1 symbol indicates the occurance of a
Ck Q 0 0 0 0 1 positive transition in the clock timing.
Clear 0 0 1 1 0 The symbol > (knife edge) drawn next
1 1 d d Not allowed to the clock input in the block diagram
(a) (b) indicates edge-triggered feature.
Preset
Clear Q
Q
Clock
Figure 6.1.23 Realization of D flip-flop with six NAND gates.
JK FLIP-FLOP (JKFF)
The block diagram, truth table, and a practical realization of the JKFF are shown in Figure
6.1.24. The JKFF differs from an SRFF in that output Q is fed back to the K-gate input
and Q̄ to the J-gate input. Assuming QQ̄ = 01, gate B is disabled by Q = 0 (i.e., F =
1). The only way to make the circuit change over is for gate A to be enabled by making
J = 1 and Q̄ = 1 (which it is already). Then when Ck = 1, all inputs to gate A are 1
and E goes to zero, which makes Q = 1. With Q and F both equal to 1, Q̄ = 0, so the
flip-flop has changed state. Note that the input condition JK = 11 is allowed, and in this
condition, when the flip-flop is clocked, the output always changes state; thus it is said to
toggle.
If the clock pulse is short enough to permit the flip-flop to change only once, the JKFF
operates well. However, with modern high-speed ICs a race is more likely to occur, which is a
condition in which two pulses are intended to arrive at a destination gate in some specific order,
but due to each one racing through different paths in the logic with a different number of gates,
the propagation delays stack up differently and the timing order is lost. This can be eliminated
by introducing delays in the feedback paths between outputs (Q and Q̄) and inputs (J and K). A
better solution to the problem is the master–slave JKFF.
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6.2 DIGITAL SYSTEM COMPONENTS 295
E
J A Q
C
Inputs Outputs
Ck
J K Qn+1 Qn+1
0 0 Qn Qn
J Q 0 1 0 1 F D Q
Ck K B
1 0 1 0
K Q 1 1 Qn Qn
(a) (b) (c)

Figure 6.1.24 JK flip-flop. (a) Block diagram. (b) Truth table. (c) A realization.
MASTER–SLAVE JKFF
Figure 6.1.25 illustrates a master–slave JKFF, in which gates A, B, C, and D form the master
flip-flop and T, U, V, and W form the slave. The output of the master–slave JKFF can be predicted
for all combinations of J and K and for any duration of clock pulse. Thus it is the most versatile
and universal type of flip-flop. SRFFs are also available in master–slave configuration.
Ck = 1 enables the master; Ck ¯ = 0 disables the slave. Let QQ̄ = 10 and J K = 11 before
the occurrence of a clock pulse. B is enabled by Q = 1 so that when the clock pulse arrives
(i.e., Ck = 1), F goes to zero and Q̄M to 1. Now with E = 1 and Q̄M = 1, QM goes to zero so
that the master has been reset. However, the slave remains disabled until Ck goes to zero. Note
that the slave, at this stage, is essentially an SRFF with inputs S and R equal to QM and Q̄M ,
respectively. Thus, when Ck goes to zero, Ck ¯ goes to 1 and the slave is now reset by its inputs
QM Q̄M = 01. But the feedback to J and K cannot cause a race because, with Ck = 0, the master
is disabled.
Master Slave
QM Q
J A C T V
Ck E
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K B D U W
F QM Q
Ck
Figure 6.1.25 Master–slave JK flip-flop.
6.2 DIGITAL SYSTEM COMPONENTS

The basic combinational and sequential building blocks were introduced in Section 6.1. The
reason that digital systems are so inexpensive and yet so powerful is that they consist of very
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large numbers of just a few building blocks, repeated in simple ways. In this section we shall
deal with some common digital system components, such as decoders, encoders, multiplexers,
registers, counters, digital-to-analog (D/A) and analog-to-digital (A/D) converters, memory, and
display devices.
Decoders
An n-bit binary code is capable of encoding up to 2n distinct elements of information. A
decoder is a combinational network that decodes (converts) the n-bit binary-coded input to
m outputs (m ≤ 2n ). The block diagram of a 3-bit to 8-element decoder is shown in Figure
6.2.1(a), wherein the three inputs are decoded into eight outputs, one for each combination
of the input variables. In the truth table shown in Figure 6.2.1(b), observe that for each in-
put combination, there is only one output that is equal to 1 (i.e., each combination selects
only one of the eight outputs). The logic diagram of the 3-to-8 decoder is shown in Figure
6.2.1(c).
Decoding is so common in digital design that decoders are commercially available as MSI
(medium-scale integration) packages in the form of 2-to-4, 3-to-8, and 4-to-10 decoders. Inte-
grated circuits for decoders are available in different forms.
Encoders
Encoding is the process of forming an encoded representation of a set of inputs, and it is the
converse of the decoding operation. An encoder is a combinational network that generates an
n-bit binary code that uniquely identifies the one out of m activated inputs (0 ≤ m ≤ 2n − 1).
Figure 6.2.2(a) shows the block diagram of an 8-element to 3-bit encoder. The truth table is
given in Figure 6.2.2(b). Notice that only one of the eight inputs is allowed to be activated at any
given time. The logic diagram for the 8-to-3 encoder is shown in Figure 6.2.2(c).
Multiplexers
A multiplexer is a data selector, whereas a demultiplexer is a data distributor. A multiplexer
is a combinational network that selects one of several possible input signals and directs that
signal to a single output terminal. The selection of a particular input is controlled by a set of
selection variables. A multiplexer with n selection variables can usually select one out of 2n input
signals.
Figure 6.2.3(a) shows the block diagram of a 4-to-1 multiplexer. The truth table is given in
Figure 6.2.3(b). Notice that each of the four inputs (I 0, I 1, I 2, and I 3) is selected by S1 and S0,
and directed to the output Q. In general, only the input whose address is given by the select lines
is directed to the output. The logic diagram is shown in Figure 6.2.3(c). 2-, 4-, 8-, and 16-to-1
multiplexers are commercially available as MSI packages.
Registers
A register is a collection of flip flops (and some basic combinational gates to perform different
binary arithmetic and logic operations), where each flip-flop is used to store 1 bit of information.
Figure 6.2.4(a) shows the block diagram of a 4-bit shift-right register that uses D flip-flops. JKFFs
and SRFFs are also used in shift-register construction. Observe in the timing diagram of Figure
6.2.4(b) that each successive clock pulse transfers (or shifts) the data bit from one flip-flop to the
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A0 A1 A2 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
0 0 0 0 0 0 0 0 0 0 1
Q0 0 0 1 0 0 0 0 0 0 1 0
Q1 0 1 0 0 0 0 0 0 1 0 0
A0 Q2 0 1 1 0 0 0 0 1 0 0 0
Q3 1 0 0 0 0 0 1 0 0 0 0
A1 Q4
Q5 1 0 1 0 0 1 0 0 0 0 0
A2
Q6 1 1 0 0 1 0 0 0 0 0 0
Q7 1 1 1 1 0 0 0 0 0 0 0
(a) (b)
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A2 A1 A0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
(c)
Figure 6.2.1 3-to-8 decoder. (a) Block diagram. (b) Truth table. (c) Logic diagram.
next one on the right. The waveforms also reveal that the data are read into the register serially
and appear at the output in serial form. The shift register is then known as a serial-in serial-out
(SISO) register.
PISO (parallel-in serial-out), SIPO (serial-in parallel-out), and PIPO (parallel-in parallel-
out) registers are also often used to read in the input data and read out the output data in a
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Inputs Outputs
I7 I6 I5 I4 I3 I2 I1 I0 n2 n1 n0
0 0 0 0 0 0 0 1 0 0 0
I0 0 0 0 0 0 0 1 0 0 0 1
I1 0 0 0 0 0 1 0 0 0 1 0
I2 n0 0 0 0 0 1 0 0 0 0 1 1
I3 n1 0 0 0 1 0 0 0 0 1 0 0
I4
I5 0 0 1 0 0 0 0 0 1 0 1
n2
I6 0 1 0 0 0 0 0 0 1 1 0
I7 1 0 0 0 0 0 0 0 1 1 1
(a) (b)
I7 I6 I5 I4 I3 I2 I1 I0
n2
n1
n0
(c)
Figure 6.2.2 8-to-3 encoder. (a) Block diagram. (b) Truth table. (c) Logic diagram.
convenient way that is needed for the operations involved. Right-shifting registers are employed
in multiplication algorithms, whereas left-shifting registers are utilized in division algorithms.
Registers that are capable of shifting the data to the left or right are known as bidirectional
shift registers. The register along with additional gates on a single chip forms an IC component
known as the universal register, which usually includes the shift-left, shift-right, parallel-input,
and no-change operations.
Counters
The shift register can be used as a counter because the data are shifted for each clock pulse. A
counter is a register that goes through a predetermined sequence of states when input pulses are
received. Besides, computers, timers, frequency meters, and various other digital devices contain
counters for counting events.
There are what are known as ripple (asynchronous), synchronous, and ring counters. In
ripple counters, the output of each flip-flop activates the next flip-flop throughout the entire
sequence of the counter’s states. In a synchronous counter, on the other hand, all flip-flops
are activated (triggered) simultaneously through a master clock connected to the clock inputs
of all flip-flops. In a ring counter, as in a synchronous counter, all flip-flops are triggered
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I0 Select Lines Output

I1 S1 S0 Q
Input Q Output
lines I2 0 0 I0
0 1 I1
I3 1 0 I2
S1 S0 1 1 I3
(b)
Select Lines
(a)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
I0
I1
I2
I3
S1 S0
(c)
Figure 6.2.3 4-to-1 multiplexer. (a) Block diagram. (b) Truth table. (c) Logic diagram.
simultaneously. However, the output of each flip-flop drives only an adjacent flip-flop. A single
pulse propagates through the ring in a ring counter, whereas all remaining flip-flops are at the
zero state.
Figure 6.2.5(a) shows a block diagram of a 3-bit ripple counter using JKFFs. Notice from the
timing diagram shown in Figure 6.2.5(b) that the output Q0 of the leftmost flip-flop will change
its state at every clock pulse if the clear signal equals zero. The output Q1, controlled by Q0,
will change its state every time Q0 changes from 0 to 1. Similarly Q2 is controlled by Q1. Figure
6.2.5(c) shows the outputs for the first 8 clock pulses. Observe that a 3-bit counter will cycle
through 8 states, 000 through 111. An n-bit ripple counter, in general, will cycle through 2n states;
it is known as a divide-by-2n counter or modulo-2n binary counter. Taking the outputs from Q2 Q1
Q0, the counter becomes an up-counter; taking the outputs from Q̄2 Q̄1 Q̄0 , the counter becomes
a down-counter, which counts down from a preset number. Asynchronous ripple counters are
available as MSI packages.
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Preset
Data input Pr Pr Pr Pr Data output

D3 Y3 D2 Y2 D1 Y1 D0 Y0
FF3 FF2 FF1 FF0
Ck Ck Ck Ck
Clr Clr Clr Clr
Clock
Clear
(a)
Pulse 1 2 3 4 5 6
Clock
T 2T 3T 4T 5T 6T
Data
input
T 2T 4T 5T
Y3
2T 3T 5T 6T
Y2
3T 4T 6T
Y1
4T 5T
Y0
5T 6T
(b)
Figure 6.2.4 4-bit shift-right SISO register. (a) Block diagram. (b) Timing diagram.
Clear Figure 6.2.5 3-bit ripple

counter. (a) Block diagram.
(b) Timing diagram. (c) Out-
J0 Clr J1 Clr J2 Clr
Q0 Q1 Q2 puts for the first 8 clock
Clock Ck0 Ck1 Ck2 pulses.
Q0 Q1 Q2
k0 k1 k2
Logic 1
(a)
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T1 T2 T3 T4 T5 T6 T7 T8
Clock Q2 Q1 Q0
Clock 0 0 0
Clear
T1 0 0 1
T2 0 1 0
T3 0 1 1
Q0 0 1 0 1 0 1 0 1 0
T4 1 0 0
T5 1 0 1
Q1 0 1 1 0 0 1 1 0 0 T6 1 1 0
T7 1 1 1
T8 0 0 0
Q2 0 1 1 1 1 0 0 0 0
(b) (c)
Figure 6.2.5 Continued
The slow speed of operation, caused by the long time required for changes in state to ripple
through the flip-flops, is a disadvantage of ripple counters. This problem is overcome by using
synchronous converters. However, additional control logic is needed to determine which flip-
flops, if any, must change state, since flip-flops are triggered simultaneously. Figure 6.2.6 shows
the logic diagram of a 3-bit binary synchronous converter using JKFFs. Synchronous counters
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
can be designed to cycle through any sequence of states. Various n-bit synchronous converters
are commercially available as MSI packages. Some counters are also programmable.
Figure 6.2.7(a) shows a 4-bit (modulo-4) ring counter using D flip-flops; its timing diagram
is given in Figure 6.2.7(b). A modulo-n ring counter requires N flip-flops and no other gates,
whereas modulo-N ripple and synchronous counters need only log2 N flip-flops. However, ripple
and synchronous counters generally use more components than ring counters.
1 J0 Q0 J1 Q1 J2 Q2
Ck0 Ck1 Ck2
k0 Q0 k1 Q1 k2 Q2
Clock
Figure 6.2.6 3-bit binary synchronous converter using JKFFs.
D0 Q0 D1 Q1 D2 Q2 D3 Q3
Ck0 Q0 Ck1 Q1 Ck2 Q2 Ck3 Q3
Clock
(a)
Figure 6.2.7 4-bit ring counter using D flip-flops. (a) Block diagram. (b) Timing diagram.
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T1 T2 T3 T4 T5 T6 T7 T8 T9 Figure 6.2.7 4-bit ring counter using D

flip-flops. (a) Block diagram. (b) Timing
Clock
diagram.
1 0 0 0 1 0 0 0
Q0
Q1 0 1 0 0 0 1 0 0
Q2 0 0 1 0 0 0 1 0
Q3 0 0 0 1 0 0 0 1
(b)
EXAMPLE 6.2.1
A table of minterms for three variables is as follows:
A B C i Minterm mi
0 0 0 0 Ā · B̄ · C̄
0 0 1 1 Ā · B̄ · C
0 1 0 2 Ā · B · C̄
0 1 1 3 Ā · B · C
1 0 0 4 A · B̄ · C̄
1 0 1 5 A · B̄ · C
1 1 0 6 A · B · C̄
1 1 1 7 A·B ·C
Implement the following Boolean functions by using one 3-to-8 decoder and three three-input
OR gates:

F1 (A, B, C) = mi (1, 2, 3) = Ā · B̄ · C + Ā · B · C̄ + Ā · B · C

F2 (A, B, C) = mi (2, 4, 6) = Ā · B · C̄ + A · B̄ · C̄ + A · B · C̄

F3 (A, B, C) = mi (3, 5, 7) = Ā · B · C + A · B̄ · C + A · B · C
Solution
The implementation is shown in Figure E6.2.1.
Figure E6.2.1
m0
m1
F1
A m2
3-to-8 m3
B
decoder
C m4 F2
m5
m6
m7 F3
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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EXAMPLE 6.2.2
Show the logic diagram of an 8-to-1 multiplexer.
Solution
The logic diagram is depicted in Figure E6.2.2.

I0
I1
I2
I3
Q
I4
I5
I6
I7
A2 A1 A0
Figure E6.2.2
EXAMPLE 6.2.3
Given the block diagram for a 4-bit shift-left register shown in Figure E6.2.3(a), draw the output
(Q0, Q1, Q2, Q3, and data out) as a function of time for the clock, clear, and data-in signals given
in Figure E6.2.3(b).
Clear Figure E6.2.3
Clr Clr Clr Clr

Data out Q3 D3 Q2 D2 Q1 D1 Q0 D0 Data in
Q3 Ck3 Q2 Ck2 Q1 Ck1 Q0 Ck0
Clock
(a)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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T1 T2 T3 T4 T5 T6 T7 T8 Figure E6.2.3 Continued
Clock
Clear
Data in
(b)
T1 T2 T3 T4 T5 T6 T7 T8
Clock
Clear
Data in
Q0
Q1
Q2
Q3
Data out
(c)
Solution
The output is shown in Figure E6.2.3(c).
EXAMPLE 6.2.4
The block diagram for a 3-bit ripple counter is shown in Figure E6.2.4(a). Obtain a state table for
the number of pulses N = 0 to 8, and draw a state diagram to explain its operation.
LSB MSB --`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
D Q1 D Q2 D Q3
FF1 FF2 FF3
Ck Q1 Ck Q2 Ck Q3
(a)
Figure E6.2.4 (a) Block diagram. (b) State table. (c) State diagram.
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111 000
110 001
101 010
100 011
(c)
Solution
The state table and the state diagram are given in Figures E6.2.4(b) and (c). The horizontal arrows
indicate the times when clock inputs are applied to FF2 and FF3. These times are located by
noting that every time Q1 makes a transition from 1 to 0, FF2 is clocked, and when Q2 goes from
1 to 0, FF3 is clocked.
In the state diagram, the eight states of the system are indicated by the values of the three-digit
binary number Q3 Q2 Q1.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
EXAMPLE 6.2.5
Given the block diagram of a synchronous counter shown in Figure E6.2.5(a), draw the timing
diagram for the first input pulses, with Q1, Q2, and Q3 initially at 0.
Solution
The timing diagram is shown in Figure E6.2.5(b). Corresponding to the rising transitions of the
input, FF1 operates such that Q1 can be drawn as a function of time, as shown in Figure E6.2.5(b).
Because of the AND gate, FF2 can receive change instructions only when Q1 = 1. Note that FF2
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does not receive the first change instruction, but it does receive the second one. At the time of the
second change instruction, Q1 is still 1; it changes to 0 shortly afterward, but by that time FF2
has already been triggered. Similarly, FF3 is triggered only when Q1 and Q2 are both equal to 1.
Thus, from the timing diagram, the successive states of Q3 Q2 Q1 can be seen as 000, 001, 010,
011, 100, 101, 110, 111, 000, 001, . . . , as required for a counter.
Note that in a synchronous counter, all the flip-flops change at the same time (unlike in a
ripple counter). The total delay is then the same as the propagation delay of a single flip-flop.
D Q1
D Q2 D Q3
FF1
FF2 FF3
Ck Q1
Ck Q2 Ck Q3
Input
(a)
Input
Q1
Q2
Q3
(b)
Figure E6.2.5 (a) Block diagram. (b) Timing diagram.
Digital-to-Analog (D/A) Converters

For the results of digital computations to be used in the analog world, it becomes necessary to
convert the digital values to proportional analog values. Figure 6.2.8 shows the block diagram of
a typical digital-to-analog (D/A) converter, which accepts an n-bit parallel digital code as input
and provides an analog current or voltage as output. For an ideal D/A converter, the analog output
for an n-bit binary code is given by
Vo = −Vref (b0 + b1 × 2−1 + b2 × 2−2 + · · · + bn−1 × 2−n+1 ) (6.2.1)
where
R Figure 6.2.8 Block diagram of

b0 typical D/A converter.
b1 I
Resistor and
Digital input switching −
network +
bn-1
Vo
Analog output
Reference voltage
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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V0 analog output voltage

Vref reference analog input voltage
b0 most significant bit of binary input code
bn−1 least significant bit of binary input code
In order to provide current-to-voltage conversion and/or buffering, an op amp is used at the output.
However, in some high-speed applications where a limited output voltage range is acceptable, a
resistor, instead of an op amp, is used for the current-to-voltage conversion, thereby eliminating
the delay associated with the op amp.
WEIGHTED-RESISTOR D/A CONVERTER

Figure 6.2.9 shows a 4-bit weighted-resistor D/A converter which includes a reference voltage
source, a set of four electronically controlled switches, a set of four binary-weighted precision
resistors, and an op amp. Each binary bit of digital input code controls its own switch. The switch
closes with a bit value of 1, and the switch stays open with binary 0. The resistor connected to
the most significant bit (MSB), b0, has a value of R; b1 is connected to 2R, b2 to 4R, and b3 to 8R.
Thus, each low-order bit is connected to a resistor that is higher by a factor of 2. For a 4-bit D/A
converter, the binary input range is from 0000 to 1111.
An important design parameter of a D/A converter is the resolution, which is the smallest
output voltage change, ?V , which for an n-bit D/A converter is given by
Vref
?V = n−1 (6.2.2)
2
The range of resistor values becomes impractical for binary words longer than 4 bits. Also,
the dynamic range of the op amp limits the selection of resistance values. To overcome these
limitations, the R–2R ladder D/A converter is developed.
R–2R LADDER D/A CONVERTER

Figure 6.2.10 shows a 4-bit R–2R ladder D/A converter, which contains a reference voltage source,
a set of four switches, two resistors per bit, and an op amp. The analog output voltage can be
shown to be
Vref
R 2R 4R 8R
b0 b1 b2 b3
1 0 1 0 1 0 1 0
I0 I1 I2 I3
−
Iin + Vo
Figure 6.2.9 4-bit weighted-resistor D/A converter.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Vo = −Vref (b0 × 2−1 + b1 × 2−2 + · · · + bn−1 × 2−n ) (6.2.3)

Because only two resistor values (R and 2R) are used, the R–2R ladder converter networks are
relatively simple to manufacture, fast, practical, and reliable. The commercially available AD558,
which is an 8-bit R-2R D/A converter, is an example.
2n-R D/A CONVERTER

An n-bit 2n–R D/A converter needs 2n resistors of equal value R and (2n+1 − 2) analog switches. A
3-bit 2n −R D/A converter is shown in Figure 6.2.11, which includes the eight resistors connected
in series to form a voltage divider providing eight analog voltage levels, as well as 14 analog
switches controlled by the digital input code such that each code creates a single path from the
voltage divider to the converter output. A unit-gain amplifier is connected to the output in order
to prevent loading of the voltage divider. 2n–R D/A converters are economically manufactured as
LSI packages in spite of the large number of components needed.
Analog-to-Digital (A/D) Converters

An A/D converter converts analog input signals into digital output data in many areas such as
process control, aircraft control, and telemetry. Being the interface between analog systems and
digital systems, it plays a key role in many industrial, commercial, and military systems. Several
types of A/D converters exist: counter-controlled, successive-approximation, and dual-ramp
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(dual-slope) converters. One should understand its basic operation because analog comparators
form the basis of A/D converters. Figure 6.2.12 shows the block diagram of an analog comparator.
The commercially available LM311 is an example that is widely used by designers.
COUNTER-CONTROLLED A/D CONVERTER

Figure 6.2.13 shows the block diagram of a counter-controlled A/D converter. Resetting the binary
counter to zero produces D/A output voltage V2 = 0 and initiates the analog-to-digital conversion.
When the analog input V 1 is larger than the DAC (D/A converter) output voltage, the comparator
output will be high, thereby enabling the AND gate and incrementing the counter. V 2 is increased
R R R
X
Vref
2R 2R 2R 2R 2R
MSB b0 b1 b2 LSB b3
1 0 1 0 1 0 1 0
−
+ Vo
Iin
Figure 6.2.10 4-bit R–2R ladder D/A converter.
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Vref
B2 B2 B1 B1 B0 B0
R
4 −
+ Vo
R
Figure 6.2.11 3-bit 2n–R D/A converter.
high if V1 ≥ V2 (logic 1) Figure 6.2.12 Block diagram of analog

V1 + comparator.
V2 − Vo =
low if V1 < V2 (logic 0)
Analog voltage Discrete voltage

input signals output
as the counter gets incremented; when V 2 is slightly greater than the analog input signal, the
comparator signal becomes low, thereby causing the AND gate to stop the counter. The counter
output at this point becomes the digital representation of the analog input signal. The relatively
long conversion time needed to encode the analog input signal is the major disadvantage of this
method.
SUCCESSIVE-APPROXIMATION A/D CONVERTER

This converter, shown in Figure 6.2.14, also contains a D/A converter, but the binary counter
is replaced by a successive-approximation register (SAR), which makes the analog-to-digital
conversion much faster. The SAR sets the MSB to 1 and all other bits to 0, after a start-of-
conversion pulse. If the comparator indicates the D/A converter output to be larger than the signal
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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V1 Figure 6.2.13 Block diagram of counter-

Analog input − controlled A/D converter.
+
V2
D/A converter
Digital output
Reset Binary counter
to be converted, then the MSB is reset to 0 and the next bit is tried as the MSB. On the other
hand, if the signal to be converted is larger than the D/A computer output, then the MSB remains
1. This procedure is repeated for each bit until the binary equivalent of the input analog signal
is obtained at the end. This method requires only n clock periods, compared to the 2n clock
periods needed by the counter-controlled A/D converter, where n is the number of bits required
to encode the analog signal. The National ADC 0844 is a popular 8-bit A/D converter based on
the SAR.
DUAL-RAMP (DUAL-SLOPE) A/D CONVERTER

Figure 6.2.15(a) shows the block diagram of a dual-ramp (dual-slope) A/D converter. After a
start-of-conversion pulse, the counter is cleared and the analog input V in becomes the input of the
ramp generator (integrator). When the output of the ramp generator Vo reaches zero, the counter
starts to count. After a fixed amount of time T, as shown in Figure 6.2.15(b), the output of the
ramp generator is proportional to the analog input signal. At the end of T, the reference voltage
V ref is selected, when the integrator gives out a ramp with a positive slope. As Vo increases, the
counter is incremented until Vo reaches the comparator threshold voltage of 0 V, when the counter
V1 Figure 6.2.14 Block diagram of suc-

Analog input − cessive-approximation A/D converter.
+
V2
N-bit D/A
N-bit digital output
MSB LSB
N-bit successive-
Start conversion approximation
Clock
register (SAR)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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stops being incremented again. The value of the counter becomes the binary code for the analog
voltage V in, since the number of clock pulses passing through the control logic gate for a time t
is proportional to the analog signal V in. Dual-ramp A/D converters can provide accuracy at low
cost, even though the process is slow because a double clock pulse count is an inherent part of
the process.
Memory
For a digital computer which stores both programs and data, memory can be divided into three
types: random-access memory, mass storage, and archival storage. Random-access memory
includes read-and-write memory (RAM), read-only memory (ROM), programmable read-only
memory (PROM), and erasable programmable read-only memory (EPROM), in which any
memory location can be accessed in about the same time. The time required to access data
in a mass-storage device is relative to its location in the device. Mass storage, such as magnetic-
disk memory, has a relatively large storage capacity and is lower in cost per bit than random-
access memory. Archival storage, such as magnetic tape, is long-term storage with a very large
capacity, but with a very slow access time, and may need user intervention for access by the
system.
Figure 6.2.15 (a) Block diagram

of dual-ramp (dual-slope) A/D con-
verter. (b) Output of ramp generator
in dual-ramp A/D converter.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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READ-AND-WRITE MEMORY (RAM)

Writing is the same as storing data into memory and reading is the same as retrieving the data later.
RAM is said to be volatile because its contents are retained only as long as power is present. A
RAM device is a collection of 2n addressable storage locations, each of which contains k bits. Its
block diagram is shown in Figure 6.2.16, in which each cell may be a flip-flop or a capacitor, and
n address lines are decoded to select k cells. A static RAM, in which each cell is a flip-flop, is the
read-and-write memory that retains its data so long as the power is applied, without any further
action needed from the computer. Static RAM is used in microprocessor-based systems requiring
small memory. Common static-RAM sizes are 2K × 8, 8K × 8, and 32K × 8, where K stands for
210 = 1024. A dynamic RAM, in which each cell is a capacitor (which leaks charges and therefore
requires continuous refreshing from the computer to maintain its value), is the read-and-write
memory that is used in large memory systems due to its lower cost and greater density. Common
dynamic-RAM packages are available in 16K-bit, 64K-bit, 256K-bit, and 1M-bit (where M stands
for mega = 220) sizes.
READ-ONLY MEMORY (ROM)

ROM is nonvolatile (because it maintains its contents even when its power is shut off) and is
used to store data and programs that do not change during the operation of the system. The
mask-programmed ROMs are read-only devices that are programmed for data storage during the
manufacturing of the chip itself. These are generally less expensive devices for mass production.
Character-font memory for laser printers is a good example. Programmable read-only memory
(PROM) is a field-programmable memory that is fabricated by the manufacturer containing all 0s
and is programmed irreversibly by the user by electrically changing appropriate 0s to 1s. PROMs
are quite economical in small quantities. Erasable programmable read-only memory (EPROM)
is nonvolatile and widely used in microprocessor systems for program storage. It can be erased by
shining an ultraviolet light and reprogrammed if necessary. These are produced in low to moderate
volumes.
ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM)

EEPROM is used for remote-area applications. The device is provided with special pins which,
when activated electrically, alter the rewriting of selected memory locations.
MAGNETIC STORAGE DEVICES

Magnetic disk memory is nonvolatile and provides large storage capabilities with moderate access
times. The data are stored on one or more rigid aluminum circular disks coated with iron oxide. The --`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Enable Figure 6.2.16 Block diagram of 2n × k-bit RAM device.
2n × k matrix
of memory
n address lines cells k data lines
Read Write
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most common disks have 11-in diameters and 200 tracks (concentric rings of data) per surface,
numbered from 0 to 199, starting with the outside perimeter of the disk, with a typical track
packing density of 4000 bits per inch. Disks are mounted on a common spindle, and all disks
rotate at a typical speed of 3600 revolutions per minute (rpm). A typical disk has 17 sectors of
fixed size per track and 512 bytes (1 byte = 8 bits) of information per sector. Any desired sector
can be quickly accessed.
Floppy disks, also known as flexible disks, are the low-cost, medium-capacity, nonvolatile
memory devices made of soft flexible mylar plastic with magnetically sensitive iron-oxide coating.
The original 8-in standard floppy is no longer in popular use. The 5 1/4-in minifloppy has a disk
and a disk jacket covering the mylar media for protection, along with a write-protect notch and
index hole. The present-day minifloppy disks are either double-sided/double-density (DS/DD)
with 9 sectors per track and 40 tracks per side or double-sided/quad-density (DS/QD) with 9 or
15 sectors per track and 80 tracks per side. In a DS/DD minifloppy disk, about 720 kbytes of data
can be stored; whereas in a DS/QD mini-floppy disk, about 1–2 Mbytes of data can be stored.
The 3 1/2-in microfloppy disk, also known as a microdiskette, is enclosed in a rigid protective
case and is provided with a write-protect notch. Microdiskettes are recorded in quad-density
format with a capacity of 2 Mbytes; 4- to 16-Mbyte 3 1/2-in diskettes are being developed. Also,
2-in diskettes are introduced in electronic cameras and portable personal computers.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Magnetic tapes are ideal devices for storing vast quantities of information inexpensively.
However, the access time is slow because the entire tape must be read sequentially. The most
commonly used tapes are ½-in wide, 2400 or 3600 ft long, and contained in a long 10½-in reel.
Tape densities of 200, 556, 800, 1600, 6250, and 12,500 bits per inch (BPI) are standard.
In addition to these magnetic storage devices, two newer types of secondary storage have
come into use: winchester disks and videodisks (also known as optical disks). The former are sealed
modules that contain both the disk and the read/write mechanism, requiring little maintenance and
allowing higher-density recording. The latter have been introduced recently, with high reliability
and durability and a storage capacity of 1 Gbyte of data (equivalent to almost 400,000 typewritten
pages of information). A typical 14-in optical disk has 40,000 tracks and 25 sectors per track,
with each sector holding up to 1 kbyte of information. While a write-once optical-disk drive is
currently available, a read-and-write drive is being developed.
Display Devices
Display devices can be categorized as on/off indicators, numeric, alphanumeric, or graphical
displays. They may also be classified as active and passive devices. Active display devices emit
light, such as light-emitting diodes (LEDs), whereas passive display devices, such as liquid-crystal
displays (LCDs), reflect or absorb light.
LIGHT-EMITTING DIODE (LED)

This is a reliable, rugged, and inexpensive semiconductor display device requiring about 10 mA
of current flow for full illumination. An LED is shown in Figure 6.2.17. It is available in red,
yellow, or green color, in common sizes of T-1 and T-1 3/4, where the number after the T denotes
the diameter of the lamp in units of eighths of an inch. Two-color LEDs are also available.
LIQUID-CRYSTAL DISPLAY (LCD)

This display needs only microwatts of power (over a thousand times less than a LED) and is used
in such devices as electronic wristwatches. With the application of an electric field the molecules
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+5 V Figure 6.2.17 Light-emitting diode (LED).
LED
On/Off
7404
of the liquid-crystal material are straightened out, absorbing the light, and the display appears
black. With no electric field applied, the display appears as a silver mirror because the light is
reflected.
SEGMENT DISPLAYS
Seven-segment displays are the most commonly used numeric display devices, while 10- and
16-segment (starburst) display devices are also available. Figure 6.2.18(a) depicts a common-
cathode seven-segment LED display; Figure 6.2.18(b) shows its internal structure, consisting of
a single LED for each of the segments; and Figure 6.2.18(c) displays the digits by an appropriate
combination of lighted segments. The 16-segment display shown in Figure 6.2.18(d) is commonly
used for alphanumeric data.
a Figure 6.2.18 (a) Seven-segment display.

f b (b) Internal structure of seven-segment dis-
play. (c) Digits displayed by a seven-segment
g display. (d) 16-segment (starburst) display.
e c
d
(a)
a b c d e f g
(b)
(c)
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(d)
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CATHODE-RAY TUBE (CRT)

While the CRT display is one of the oldest, it still remains one of the most popular display
technologies. The raster-scanned display devices work similarly to commercial television sets,
whereas graphics display devices use different technologies to achieve extremely high resolution.
A CRT video signal has only two levels, with a 0 level causing a dark spot and a 1 level causing
a bright spot. The appropriate combination of 1s and 0s displays data on a CRT screen, with each
character displayed by dot-matrix displays, typically in 5 × 7 or 7 × 9 display fonts.
EXAMPLE 6.2.6
For the 4-bit D/A converter of Figure 6.2.9 with Vref = −5 V, determine the range of analog
output voltage and the smallest increment.
Solution
The binary input range is from 0000 to 1111 for a 4-bit D/A converter. From Equation (6.2.1) it
follows that the range of the analog output voltage is from 0 V to
5 × (1 + 1 × 2−1 + 1 × 2−2 + 1 × 2−3 ) = 5 × 1.875 = 9.375 V
The smallest increment is given by 5 × 1 × 2−3 = 5/8 = 0.625 V.
EXAMPLE 6.2.7
For the 3-bit 2n–R D/A converter of Figure 6.2.11, calculate the analog output voltage when the
input is (a) 100, and (b) 010.
Solution
a. For the binary input 100, switches controlled by B0, B̄1 , and B̄2 will be closed. A path
is then produced between the output Vo and point 4, where the voltage is equal to Vref /2.
The analog output voltage is therefore Vref /2.
b. For the binary input 010, switches controlled by B̄0 , B1 , and B̄2 will be closed. A path
exists between Vo and point 6, where the voltage is equal to Vref /4. The analog output
voltage is thus Vref /4.
EXAMPLE 6.2.8
The speed of an 8-bit A/D converter is limited by the counter, which has a maximum speed of
4 × 107 counts per second. Estimate the maximum number of A/D conversions per second that
can be achieved.
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Solution
The rate of the clock will be constant, independent of the analog input. It must be slow enough
to allow the counter to count up to the highest possible input voltage. This will require 255(=
27 + 26 + 25 + 24 + 23 + 22 + 21 + 20 ) counts, which will take 255/(40 × 106 ) = 6.375 µs.
Thus, the process can be repeated 106 /6.375 = 156,863 times per second.
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EXAMPLE 6.2.9
If it is desired to store English-language writing with 1 byte representing each letter, find the
minimum number of bits per byte that could be used.
Solution
For the 26 letters in the English alphabet, we must have 2N ≥ 26, where N is the number of bits
per byte. N being an integer, the smallest possible value for N is 5. One can represent the letter
A by 00000, B by 00001, and so on up to Z by 11001; the remaining six combinations could be
used for representing punctuation marks or spaces. This is, in fact, the method by which letters
are represented in teletype systems.
If one wants to store capital English-language letters also, there will be 52 letters instead of
26; in such a case 6-bit bytes would have to be used.
6.3 COMPUTER SYSTEMS

Digital computers, in general, are automatic machines that accept data and instructions, perform
predefined operations very quickly on the data, and have the results available to the user in
various forms. They can be classified as microcomputers, minicomputers, mainframes, and
supercomputers.
Microcomputers have become a common part of everyday life. The cost ranging from a
few hundred to about ten thousand dollars, today’s 16- and 32-bit microcomputer systems are
also dedicated for real-time applications in a distributed system. A microprocessor is an LSI
device, which is a realization of the computer central-processor unit (CPU) in IC form. The
microprocessor is the CPU of the microcomputer system.
Minicomputers, developed in the early 1960s, are high-performance, general-purpose multi-
user computers. These are also designed for real-time dedicated applications. The PDP-11 series
from Digital Equipment Corporation (DEC) have been the most prominent 16-bit minicomputers,
and are now obsolete. The 32-bit minicomputers, known as superminis, were developed in the
1970s, the most prominent one being the VAX 8600 from DEC, which was capable of executing
about 5 million instructions per second (MIPS). New VAX lines with larger MIPS have been
developed since.
Mainframes, capable of executing in excess of 53 MIPS, are high-performance, general-
purpose computers supporting very large databases, ranging in price from one to ten million
dollars. These are used by many universities, large businesses, and government agencies, and are
supplied mainly by IBM. Examples include IBM 360, CDC 7600 of Control Data Corporation,
and Texas Instrument Advanced Scientific Computer (TI–ASC).
Supercomputers, capable of executing in excess of one billion floating-point operations per
second (FLOPS), are very powerful, extremely high-performance computers for applications that
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6.3 COMPUTER SYSTEMS 317
are beyond the reach of the mainframes, and cost more than ten million dollars. These are used
for weather prediction, image processing, and nuclear-energy studies that require high-precision
processing of ordered data achieved by a speed advantage due to parallel processors. Cyber 205,
Cray X-MP, and Cray 2 are some examples of supercomputers. In the 1980s, supercomputing
centers were developed at six American universities for high performance computing. By 1990 it
was possible to build chips with a million components; semiconductor memories became standard
in all computers; widespread use of computer networks and workstations had occurred. Explosive
growth of wide area networking took place with transmission rates of 45 million bits per second.
Organization
There are two principal components: hardware and software. The former refers to physical
components such as memory unit (MU), arithmetic and logic unit (ALU), control unit (CU),
input/output (I/O) devices, etc.; whereas the latter refers to the programs (collections of ordered
instructions) that direct the hardware operations.
Figure 6.3.1 illustrates the basic organization of a digital computer. The MU stores both data
and programs that are currently processed and executed. The ALU processes the data obtained
from the MU and/or input devices, and puts the processed data back into the MU and/or output
devices. The CU coordinates the operations of the MU, ALU, and I/O units. While retrieving
instructions from programs resident in the MU, the CU decodes these instructions and directs the
ALU to perform the corresponding processing; it also oversees the I/O operations. Input devices
may consist of card readers, keyboards, magnetic tape readers, and A/D converters; output devices
may consist of line printers, plotters, and D/A converters. Devices such as terminals and magnetic
disk drives have both input and output capabilities. For communicating with the external world
and for storing large quantities of data, a variety of I/O devices are used.
Software may be classified as system software and user software. The former refers to the
collection of programs provided by the computer system for the creation and execution of the
user programs, whereas the latter refers to the programs generated by various computer users for
solving their specific problems.
A program generally consists of a set of instructions and data specifying the solution of
a particular problem. Programs (and data) expressed in the binary system (using 0s and 1s)
are known as machine-language programs. Writing programs in this form, which demands
Data Input
ALU
(arithmetric
and Data
logic unit)
Printer
MU I/O Data
Control (memory (Input/
unit) output unit) Terminal
Data
CU
(control unit) Control
Disk
Address
CPU
(central processing unit)
Figure 6.3.1 Typical organization of a computer.
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a detailed knowledge of the computer structure, is rather tedious and error-prone. Assembly-
language programming is developed by using symbolic names, known as mnemonics, and
matching machine-language instructions on a more or less one-for-one basis. An assembler
is then used to translate assembly-language programs into their equivalent machine-language
programs. Because both assembly-language and machine-language programmings are specific
to a particular computer, high-level languages (HLL) such as Fortran, Pascal, Basic, LISP, and
C have been developed such that programs written by using them could be run on virtually any
computer. Also, these are problem-oriented languages, which allow the user to write programs in
forms that are as close as possible to the human-oriented languages.
An interpreter translates each high-level-language statement into its equivalent set of
machine-language instructions, which are then executed right away. Interpretive languages such
as Basic are very inefficient for programs with loops (repetitive instructions). The inefficiency is
corrected by a compiler, which translates the complete high-level language into machine language.
Once the whole program is compiled, it can be executed as many times as desired without any
need for recompilation. Examples of compiler languages are Fortran, Pascal, and C.
An operating system, such as DOS, VMS, or UNIX, consisting of a set of system programs,
performs resource management and human-to-machine translation, supporting a given computer
architecture. Operations such as starting and stopping the execution, as well as selecting a specific
compiler or assembler for translating a given program into machine language, are taken care of by
the operating system, which is unique for a given microcomputer, minicomputer, or mainframe.
Architecture
Replacing the ALU and CU (i.e., CPU) of Figure 6.3.1 by a microprocessor, and storing
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instructions and data in the same memory, one arrives at a stored-program computer or a
microcomputer. A bus, which is a set of wires carrying address, data, and control signals, is
employed for interconnecting the major components of a microcomputer system. The address lines
are unidirectional signals that specify the address of a memory location of an I/O device. With a
typical 24-bit address bus, the microprocessor can access 224 (over 16 million) memory locations.
Memory is generally organized in blocks of 8, 16, or 32 bits. The data bus is a bidirectional bus,
varying in size from 8 to 32 bits, which carries data between the CPU, MU, and I/O units. The
control bus provides signals to synchronize the memory and I/O operations, select either memory
or an I/O device, and request either the read or the write operation from the device selected.
While there are virtually countless variations in microprocessor circuit configurations, the
system architecture of a typical microprocessor is shown in Figure 6.3.2. The arithmetic logic
unit (ALU) accepts data from the data bus, processes the data as per program-storage instructions
and/or external control signals, and feeds the results into temporary storage, from which external
control and actuator control functions can be performed. The accumulators are parallel storage
registers used for processing the work in progress, temporarily storing addresses and data, and
housekeeping functions. The stacks provide temporary data storage in a sequential order and are
of use during the execution of subroutines. A subroutine is a group of instructions that appears
only once in the program code, but can be executed from different points in the program. The
program counter is a register/counter that holds the address of the memory location containing
the next instruction to be executed. The status register contains condition-code bits or flags (set
to logic 1 or logic 0, depending on the result of the previous instruction) that are used to make
decisions and redirect the program flow. The control unit (CU), which consists of the timing
and data-routing circuits, decodes the instruction being processed and properly establishes data
paths among the various elements of the microprocessor. Interconnections may take the form of
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6.3 COMPUTER SYSTEMS 319
gates that the control section enables or disables according to the program instructions. That is
to say, programming at the machine-language level amounts to wiring with software instead of
hard-wired connections.
Microprocessors have instruction sets ranging from 20 to several hundred instructions,
known as microprograms, which are stored in ROM to initiate the microprocessor routines.
The instructions generally consist of a series of arithmetic and logic type operations, and also
include directions for fetching and transferring data. Microprocessors are classified by word size
in bits, such as 1-, 4-, 8-, and 16-bit microprocessors; generally speaking, the larger the word
size, the more powerful the processor. Three popular 8-bit microprocessors (µp) are Intel 8085,
Zilog Z80, and Motorola MC6800; the 16-bit microprocessors dominating the market are Intel
8086 and 80286, Motorola MC68000, and Zilog Z8000; the powerful 32-bit microprocessors at
the very high end of the market started with Intel 80386, Intel 80486, Motorola MC68020, and
National N532032. Still more powerful Intel Pentium processors such as Pentium II and III were
introduced in the 1990’s, and even these are going to be replaced soon by Intel Itanium Processors.
A microprocessor system bus consists of three physical buses: the address bus, the data
bus, and the control bus. The types of circuits connected to microprocessor buses are registers,
accumulators, or buffer circuits between the bus and the external memory or I/O devices.
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Multiplexing is usually used, which is to connect each register to a bus on a time-shared basis,
only when it is being read. An operating bus is used to transfer various internal operations
and commands. An interface bus, such as the IEEE-488 (developed in 1975 by the Institute
of Electrical and Electronics Engineers) or the GPIB (general-purpose interface bus) provides the
Data bus
I/O data
buffers
Operand bus
Accumulator
Actuator Instruction
Temporary
Program
counter
register
register
Stacks
registor
Status
control
Address
generation
Address bus
Control
Program
address register
Program Control Arithmetric and

storage unit logic unit
Control Clock
Figure 6.3.2 Block diagram of typical microprocessor system architecture.
Copyright OUP
means of communicating between the computer and the outside world with external devices such
as oscilloscopes, data collection devices, and display devices. Most present-day data acquisition
systems are designed to be compatible with microprocessors for processing the measured data.
A typical data acquisition and processing system is illustrated in Figure 6.3.3.
Reference
Display
Input signals
Transducers
Amplification
Storage
Analog-to-digital Micro-
Multiplexer Control
converter processor
Mainframe
computer
Displays
Figure 6.3.3 Block diagram of typical data acquisition and processing system.
6.4 COMPUTER NETWORKS

Computer communications networks are the outcome of a combination of computers and telecom-
munication products. An interconnected group of independent computers and peripheral devices
that communicate with each other for the purpose of sharing software and hardware resources
is known as a computer communications network. A local-area network (LAN) is any physical
network technology that operates at high speed (usually tens of Mbits per second through several
Gbits per second) over short distances (up to a few thousand meters). Examples include Ethernet
and proNET-10. The stations, also known as nodes, within a LAN are physically linked with
each other through twisted pairs of copper wires, coaxial cables, or fiber-optic cables. A wide-
area network (WAN, also known as long-haul network) is any physical network that spans large
geographic distances, usually operates at slower speeds, and has significantly higher delays than
a LAN. Stations within a WAN communicate with each other through standard telephone lines,
dedicated telephone lines, line-of-sight microwave systems, or fiber-optic links. Public-data
network (PDN) is network service offered by a common carrier, such as Telnet, Tymnet, and
Dataphone Digital Services of AT&T. ARPANET (Advanced Research Projects Agency of the
U.S. Department of Defense) is an example of a private communications network. CYBERNET
is an example of a remote-access communications network that provides access to huge databases
for their users in different countries. The Internet is a collection of networks and gateways (special-
purpose dedicated computers attached to various networks routing packets of information from one
to the other), including the Milnet (military network) and NSFNET (National Science Foundation
network), that function as a single, cooperative virtual network providing universal connectivity
and application-level services such as the electronic mail. The Internet reaches many universities,
government research labs, and military installations in several countries.
The future scope of the Internet, along with the World Wide Web (born in 1990), and the
commercialization of the Internet are bound to grow exponentially. In 1991, the U.S. Congress
passed the High Performance Computing Act to establish the National Research and Education
Network (NREN), which allows the electronic transfer of the entire Encyclopedia Britannica in
one second. Computer networks worldwide will feature 3–D animated graphics, radio and cellular
phone-links to portable computers, as well as fax, voice, and high-definition television. While the
Web is fast becoming a part of our everyday lives, the real Internet of the future may bear very
little resemblance to today’s plans.
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6.4 COMPUTER NETWORKS 321
Network Architecture
A protocol is a formal description of message formats and the rules two or more machines
must follow to exchange those messages. Because TCP (transmission control protocol) and IP
(Internet protocol) are the two most fundamental protocols, the entire protocol suite that is used
by the Internet is often referred to as TCP/IP. X.25 is the CCITT (Consultative Committee on
International Telephony and Telegraphy) standard protocol employed by Telnet, and is most
popular in Europe. Ethernet utilizes CSMA/CD (carrier sense multiple access with collision
detection) protocol technology.
Computer network architecture refers to the convention used to define how the different
protocols of the system interact with each other to support the end users. The most common
network architecture model is the open-systems interconnections (OSI). Figure 6.4.1 shows
the ISO (International Standards Organization) seven-layer model for an OSI. Although not all
layers need be implemented, the more layers that are used, the more functionality and reliability
are built into the system. Starting from the bottom layer, the functions of the layers are as
follows.
1. Physical—Defines the type of medium, the transmission method, and the transmission
rates available for the network; provides the means for transferring data across the
interconnection channel and controlling its use.
2. Data Link—Defines how the network medium is accessed, which protocols are used,
Virtual communications
shown by dashed lines
Process A Process B
Layer 7 protocol
Layer 7: Application Layer 7: Application
Layer 6 protocol
Layer 6: Presentation Layer 6: Presentation
Layer 5 protocol
Layer 5: Session Layer 5: Session
Layer 4 protocol
Layer 4: Transport Layer 4: Transport
Physical
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communications
shown by Layer 3 protocol
solid lines Layer 3: Network Layer 3: Network
Layer 2 protocol
Layer 2: Data link Layer 2: Data link
Layer 1 protocol
Layer 1: Physical Layer 1: Physical
Interconnection channel
Figure 6.4.1 ISO 7-layer model for an OSI.
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the packeting/framing methods, and the virtual circuit/connection services; responsible

for the transfer of data across the link; provides for the detection and correction of data-
transmission errors.
3. Network—Standardizes the way in which addressing is accomplished between linked
networks; performs networking functions and internetworking.
4. Transport—Handles the task of reliable message delivery and flow control between
applications on different stations; provides source-to-destination data integrity.
5. Session—Establishes two-way communication between applications running on different
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stations on the network; provides the user interface into the transport layer.
6. Presentation—Translates data formats so that computers with different “languages” can
communicate; provides the syntax (rules) of representation of data between devices.
7. Application—Interfaces directly with the application programs running on the stations;
provides services such as file access and transfer, peer-to-peer communication among
applications, and resource sharing; provides support to process end users’ applications
such as electronic mail, database management, and file management.
Note that the interconnection channel is not a part of the OSI specification.
Network Topology
This deals with the geometrical arrangement of nodes (endpoints consisting of physical devices
such as terminals, printers, PCs, and mainframes) interconnected by links (transmission channels).
Network topologies may be classified as bus topology (multidrop topology), star topology, ring
topology, tree topology, and distributed (mesh or hybrid) topology, as illustrated in Figure 6.4.2.
Bus topology is used predominantly by LANs, whereas star topology is commonly used by
private-branch exchange (PBX) systems. Ring topology may have centralized control (with one
node as the controller) or decentralized control (with all nodes having equal status). Tree topology
is used in most of the remote-access networks, whereas distributed topology is common in public
and modern communications networks. A fully distributed network allows every set of nodes to
communicate directly with every other set through a single link and provides an alternative route
between nodes.
The Internet is physically a collection of packet switching networks interconnected by
gateways along with protocols that allow them to function logically as a single, large, virtual
network. Gateways (often called IP routers) route packets to other gateways until they can
be delivered to the final destination directly across one physical network. Figure 6.4.3 shows
the structure of physical networks and gateways that provide interconnection. Gateways do not
provide direct connections among all pairs of networks. The TCP/IP is designated to provide a
universal interconnection among machines, independent of the particular network to which they
are attached. Besides gateways that interconnect physical networks, as shown in Figure 6.4.3,
Internet access software is needed on each host (any end-user computer system that connects to
a network) to allow application programs to use the Internet as if it were a single, real physical
network. Hosts may range in size from personal computers to supercomputers.
Transmission Media
These, also known as physical channels, can be either bounded or unbounded. Bounded media,
in which signals representing data are confined to the physical media, are twisted pairs of wires,
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6.4 COMPUTER NETWORKS 323
Figure 6.4.2 Network topologies. (a) Bus (multidrop)

topology. (b) Star topology. (c) Ring topology. (d) Tree
topology. (e) Distributed (mesh or hybrid) topology.
(a)
(b)
(c)
(d)
(e)
Hosts Figure 6.4.3 Structure of typical TCP/IP

Internet.
Internet
Gateways
Physical
nets
coaxial cables, and optical-fiber cables, used in most LANs. Unbounded media, such as the
atmosphere, the ocean, and outer space in which the transmission is wireless, use infrared radiation,
lasers, microwave radiation, radio waves, and satellites. Data are transmitted from one node to
another through various transmission media in computer communications networks.
Twisted pairs are used in low-performance and low-cost applications with a data rate of about
1 Mbit per second (Mbps) for a transmission distance of about 1 km. Baseband coaxial cables
used for digital transmission are usually 50-- cables with a data rate of about 10 Mbps over a
distance of about 2 km. Broad-band coaxial cables used for analog transmission (cable TV) are
usually 75-- cables with a data rate of about 500 Mbps over a distance of about 10 km. The
lighter and cheaper fiber-optic cables support data transmission of about 1 Gbps over a distance
of about 100 km.
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Data Transmission and Modems

Data can be transferred between two stations in either serial or parallel transmission. Parallel
data transmission, in which a group of bits moves over several lines at the same time, is used when
the two stations are close to each other (usually within a few meters), as in a computer–printer
configuration. Serial data transmission, in which a stream of bits moves one by one over a single
line, is used over a long distance. Serial data transfer can be either asynchronous or synchronous.
Asynchronous data communication is most commonly applied in low-speed terminals and small
computers. Large-scale integration (LSI) devices known as UARTs (universal asynchronous re-
ceivers/transmitters) are commercially available for asynchronous data transfer. Synchronous data
communication is used for transferring large amounts of data at high speed. USARTs (universal
synchronous/asynchronous receivers/transmitters) are commercially available LSI devices.
Frequency-division multiplexing (FDM) is a technique for data transmission widely used
in telephone, radio, and cable TV systems in which the transmission frequency spectrum (i.e.,
bandwidth) is divided into smaller bands known as subchannels.
Data transmission between two stations can be achieved in either simplex, half-duplex, or
full-duplex mode. In a simplex mode, mainly used in radio and TV broadcasts, information travels
only in one direction. This mode is rarely used in data communications. In half-duplex mode, used
by radio communications, information may travel in both directions, but only in one direction at
a time. The transmitter becomes the receiver and vice versa. In a full-duplex mode, information
may travel in both directions simultaneously. This mode, used in telephone systems, adopts two
different carrier frequencies.
A modem (modulator/demodulator) is an electronic device that takes digital data as a serial
stream of bits and produces a modulated carrier signal as an output. That is to say, the digital
signals are converted to an analog form with a relatively narrow bandwidth. The carrier signal is
then transmitted over the telephone line to a similar modem at the receiving end, where the carrier
signal is demodulated back into its original serial stream of bits, as shown in Figure 6.4.4. The
serial digital data to be transmitted are modulated, filtered, and amplified for analog transmission;
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the analog data received at the receiving end are amplified, filtered, and demodulated to produce
serial digital signals.
There are four different types of modems: half-duplex, full-duplex, synchronous, and asyn-
chronous. With half-duplex modems data can be transmitted in only one direction at a time. Full-
duplex modems transmit data in both directions at the same time; one modem is designated as the
originating modem and the other as the answering modem, while transmitting and receiving data
are done at different frequencies. Asynchronous modems are low-data-rate modems transmitting
serial data at a rate of about 1800 bits per second (bps). Synchronous modems are high-data-rate
modems transmitting serial data at a rate of about 10,800 bps.
Modems can also be classified as voice-band or wide-band modems. Voice-band modems are
low-to-high speed modems designed for use on dial-up, voice-grade, standard telephone lines up to
Modulated signal
Modem Modem
Digital signal Source Destination Digital signal
Figure 6.4.4 Input/output signals of a modem.
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a rate of about 10,800 bps. Microprocessor-controlled modems are known as smart modems, such
as the Hayes modem, manufactured by Hayes Microcomputer Products. The portable acoustic-
coupler device, which is a different type of voice-band modem, is a low-speed modem with a
rate of about 600 bps that is connected acoustically to a standard telephone. Wide-band modems
are very high-speed modems with rates of 19,200 bps and above, designed for use with dedicated
telephone lines. These are currently used mostly on private communications systems.

• Understanding continuous, discrete, and binary digital signals.
• Performing operations with binary, octal, hexadecimal, and binary-coded-decimal number
systems.
• Logic symbols and truth tables for various gates.
• Designing simple combinational logic circuits using logic gates.
• Using Karnaugh maps to realize logic expressions.
• Sketching timing diagrams for sequential circuits based on flip-flops.
• Digital system components such as decoders, encoders, multiplexers, registers, counters,
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D/A and A/D converters, memory, and display devices.

• Basic understanding of computer systems.
• Basic notions about computer networks.
Microcomputer-Controlled Breadmaking Machine

Figure 6.6.1 shows a simplified schematic diagram of a microcomputer-controlled breadmaking
machine. A microcomputer along with its timing circuit, keypad, and display unit controls the
heating resistor, fan motor, and bread-ingredient mixing motor by means of digitally activated
switches. An analog temperature sensor, through an A/D converter, provides the status of
temperature to the microcomputer. A digital timer circuit counts down, showing the time remaining
in the process.
The control programs are stored in ROM and determine when and how long the machine
should mix the ingredients added to the bread pan, when and how long the heating resistor should
be turned on or off for various parts of the cycle, and when and how long the fan should be on to
cool the loaf after baking is finished. The parameters such as light, medium, or dark bread crust
are entered through the keypad into RAM.
According to the programs stored and the parameters entered, the machine initially mixes
the ingredients for several minutes. The heating resistor is turned on to warm the yeast, causing
the dough to rise while a temperature of about 90°F is maintained. The time remaining and the
temperature are continually checked until the baked loaf is cooled, and the finished bread is finally
ready in about 4 hours.
Microprocessors and computers in various forms are used extensively in household appli-
ances, automobiles, and industrial equipment.
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Heating
Temperature
Bread resistor
sensor
Timer ingredient
ADC container Cooling
fan
Mixing Fan
Microcomputer motor motor
Keypad Display
Digitally
activated
switches
To 120-V
60-Hz
supply
Figure 6.6.1 Simplified schematic diagram of a microcomputer-controlled breadmaking machine.
PROBLEMS
6.1.1 Convert the following binary numbers into deci- (d) (367.240)8
mal numbers: (e) (2103.45)8
(a) (10110)2 6.1.4 Convert the following decimal numbers into octal
(b) (101100)2 numbers:
(c) (11010101)2 (a) (175)10
(d) (11101.101)2 (b) (247)10
(e) (.00101)2 (c) (65,535)10
6.1.2 Convert the following decimal numbers into bi- (d) (0.125)10
nary numbers:
(e) (379.25)10
(a) (255)10
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6.1.5 Convert the following octal numbers into binary

(b) (999)10 numbers:
(c) (1066)10 (a) (3425)8
(d) (0.375)10 (b) (3651)8
(e) (1259.00125)10 (c) (.214)8
*6.1.3 Convert the following octal numbers into decimal (d) (4125.016)8
numbers:
(e) (4573.26)8
(a) (257)8 6.1.6 Convert the following binary numbers into octal
(b) (367)8 numbers:
(c) (0.321)8 (a) (011 100 010 101)2
Copyright OUP
PROBLEMS 327
(b) (1011010)2 (a) (010101100111)BCD

(c) (.110101)2 (b) (.011001011001)BCD
(d) (100101111011.01011)2 (c) (.100110000100)BCD
(e) (1110110111.1011)2 (d) (10010010.00000001)BCD
6.1.7 Convert the following hexadecimal numbers into (e) (0010000101010011.010000110110)BCD
decimal numbers:
*6.1.13 Obtain the truth table for the logic block shown in
(a) (6B)16 Figure P6.1.13.
(b) (1F4)16 6.1.14 Find the output function Y for the logic circuits of
(c) (C59)16 Figure P6.1.14 (a) and (b).
(d) (256.72)16 6.1.15 An AOI (AND-OR-INVERT) gate is shown in
Figure P6.1.15 with its two possible realizations.
(e) (.0E3)16 Obtain the output function Y and show that the two
*6.1.8 Convert the following decimal numbers into hex- circuits are equivalent.
adecimal numbers: 6.1.16 Figure P6.1.16(a) shows the seven-segment array
(a) (97)10 that is widely used to form the decimal digits 0 to 9
(b) (864)10 in LED displays, as indicated in Figure P6.1.16(b).
Let the inputs be the four binary digits used to
(c) (5321)10 represent the decimal digits 0 to 9. (a) For the
(d) (0.00125)10 segment Y 1, (b) For the segment Y 2, and (c) For
(e) (449.375)10 the segment Y 3 to be turned on, develop the logic
expression and find one possible logic circuit to
6.1.9 Convert the following binary numbers into hex-
realize the output in each case.
adecimal numbers:
6.1.17 The DeMorgan’s theorems suggest that the basic
(a) (11101110100100.100111)2 logic operations can be realized by use of inverters
(b) (1011011101)2 and NAND gates only. For the circuits shown in
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(c) (.11101)2 Figure P6.1.17, find the truth table, the type of gate
realized, and the expression for the logic output,
(d) (1101110001.11011110)2 in each case.
(e) (.0000110111000101)2 6.1.18 For the NOR and inverter realizations shown in
6.1.10 Convert the following hexadecimal numbers into Figure P6.1.18, find the truth table, the type of gate
binary numbers: realized, and the expression for the logic output,
(a) (2ABF5)16 in each case.
(b) (3BA4.9C)16 *6.1.19 Obtain the Boolean expressions for the logic cir-
cuits shown in Figure P6.1.19.
(c) (0.0DC5)16
6.1.20 Draw the logic diagram for the following Boolean
(d) (15CE.FB3)16 expressions (without any simplification).
(e) (2AB.F8)16
(a) Y = AB + B̄C
6.1.11 Convert the following decimal numbers into BCD
numbers: (b) Y = (A + B)(Ā + C)
(a) (567)10 (c) Y = A · B + B̄ · C + A · B · D + A · C · D
(b) (1978)10 (d) Y = (Ā + B) · (A + C̄) · (B + C)
(c) (163.25)10 6.1.21 Obtain the Boolean expressions for the logic cir-
(d) (0.659)10 cuits shown in Figure P6.1.21.
(e) (2153.436)10 6.1.22 Using Boolean identities, simplify the following:
6.1.12 Convert the following BCD numbers into decimal (a) Y = A + Ā · B
numbers:
Copyright OUP
A Figure P6.1.13
F
B
A A
B B
Y Y
(a) (b)
Figure P6.1.14
A A
B B
Y Y
C C
D D
(a) (b)
Figure P6.1.15
Y6
Y5 Y7 Y1
Y4 Y2
Y3 0 1 2 3 4 5 6 7 8 9
(a) (b)
Figure P6.1.16
A
A
Y Y
B
(a) B
(b)
A
Y
Y
(c)
Figure P6.1.17
--`,,,``,,`,```,``
Copyright OUP
PROBLEMS 329
Figure P6.1.18
A
A
Y Y
B
(a) B
(b)
A
Y
Y
(c)
A A
B B
Y Y
C
(a) (b)
Figure P6.1.19
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
A Figure P6.1.21
B
C
Y
B
(a)
A
B
Y
C
(b)
A
B
Y
D
(c)
Copyright OUP
,
(b) Y = A · B + B̄ · C + A · C · D + A · B · D (b) F (A, B, C) = mi (0, 2, 3, 4, 5, 6)
,
(c) F (A, B, C, D) = mi (0, 4, 5, 6, 7,
(c) Y = (Ā + B + C) · (Ā + B + C) · C̄ 12, 14)
.
(d) Y = B · C + B̄ · C̄ + A · B̄ · C (d) F (A, B) = Mi (0, 2)
, .
6.1.23 The truth table for F (A, B, C) = mi (2, 3, 4, (e) F (A, B, C) = Mi (0, 6)
5) is as follows: .
(f) F (A, B, C, D) = M i(1, 3, 11, 14, 15)
6.1.27 Given the following truth table, design the logic
A B C F
circuit with the use of a K map by using only two-
0 0 0 0 input gates.
0 0 1 0
0 1 0 1
0 1 1 1 A B C D y
1 0 0 1
1 0 1 1 0 0 0 0 1
1 1 0 0 0 0 0 1 1
1 1 1 0 0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
(a) Express F in a canonical sum-of-products 0 1 0 1 1
form. 0 1 1 0 0
0 1 1 1 0
(b) Minimize F in an SOP form, and obtain a 1 0 0 0 1
possible realization. 1 0 0 1 1
. 1 0 1 0 0
*6.1.24 The truth table for F (A, B, C) = Mi (0, 1, 6, 1 0 1 1 1
7) is as follows: 1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
A B C F 1 1 1 1 1
0 0 0 0
0 0 1 0 6.1.28 For the logic circuit of Figure P6.1.28, construct a
0 1 0 1 truth table and obtain the minimum SOP expres-
0 1 1 1 sion.
1 0 0 1
1 0 1 1
*6.1.29 Simplify the logic circuit of Figure P6.1.29 by
1 1 0 0 reducing the number of gates to a minimum.
1 1 1 0 6.1.30 Given the following truth table:
(a) Realize the function f by a K map using 0s.
(a) Express F in a canonical product-of-sums
form. (b) Realize the function f by a K map using 1s.
(b) Minimize F in a POS form and obtain a pos-
sible realization. x y z f
6.1.25 Using K maps, simplify the following Boolean 0 0 0 0
expressions: 0 0 1 1
0 1 0 1
(a) F = A · B̄ + A · B 0 1 1 1
(b) F = A · C + C · D + B · C · D 1 0 0 1
1 0 1 1
(c) F = A · B · C̄ + B · C + A · B · D + B · C · D 1 1 0 0
1 1 1 0
6.1.26 Simplify the following Boolean functions into
their minimum SOP form, by using K maps. 6.1.31 Realize the logic function defined by the following
,
(a) F (A, B) = mi (0, 1, 3) truth table as the simplest POS form.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
PROBLEMS 331
y
x
f
y z
f
*6.1.34 Given the K map of a logic function as shown

x y z f in Figure P6.1.34, in which ds denote don’t-care
conditions, obtain the SOP expression.
0 0 0 1
6.1.35 The K map of a logic function is shown in Figure
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
0 0 1 0
0 1 0 1 P6.1.35, in which ds denote don’t-care conditions.
0 1 1 0 Obtain the SOP expressions.
1 0 0 1 6.1.36 Obtain a minimum two-level NAND–NAND
1 0 1 0
1 1 0 0 realization for the following Boolean expressions.
, ,
1 1 1 0 (a) F (A, B, C) = mi (1, 6) + di (2, 4, 5)
,
(b) F, (A, B, C, D) = m i (0, 4, 5, 7, 13) +
6.1.32 With the use of a K map, simplify the following di (2, 6, 8, 10, 11)
Boolean expressions and draw the logic diagram. ,
Note that di ( ) denotes the sum of minterms
(a) F1 = A · B + B̄ · C + A · B · D + A · C · D corresponding to don’t-care outputs.
6.1.37 (a) Show the equivalent NOR realizations of the
(b) F2 = (X + Y ) · (X̄ + Z) · (Y + Z̄) basic NOT, OR, and AND gates.
(b) Show the equivalent NAND realization of the
(c) F3 = A · C + B · C̄ + A · B · C
basic NOT, AND, and OR gates.
6.1.38 Using a minimum number of NAND gates, realize
(d) F4 = (X̄ + Y ) · (X + Z̄) · (Y + Z)
, following Boolean expression: F (A, B, C) =
the
6.1.33 The K map of a logic function is shown in Figure mi (0, 3, 4, 5, 7).
P6.1.33. 6.1.39 Figure P6.1.39 shows a full adder with the idea of
(a) Obtain a POS expression and its correspond- adding Ci to the partial sum S , which is the same
ing realization. logic process as addition with pencil and paper.
(a) Draw the truth table for the full adder.
(b) For the purpose of comparison, obtain the
corresponding SOP circuit, and comment on (b) Add decimal numbers A = 7 and B = 3 in
the number of gates needed. binary form, showing the values of A, B, S ,
CD CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10
00 0 0 0 0 00 0 1 1 1 00 1 0 1 0
01 0 0 0 0 01 d 1 0 d 01 0 0 0 1
11 0 1 0 0 11 1 0 0 d 11 0 d d d
10 0 0 1 0 10 0 0 1 d 10 0 1 d d
Figure P6.1.33 Figure P6.1.34 Figure P6.1.35
Copyright OUP
Co , Ci , Co , and S for each pair of bits.

*6.1.40 Show that the circuit of Figure P6.1.40 is a NOR- S R Q (guess) Q̄ (guess) Q Q̄
gate realization of a flip-flop.
(a) 0 0 1 0
6.1.41 Consider a 1-bit version of the digital comparator (b) 0 0 0 1
shown in Figure P6.1.41. Note that the operation (c) 1 0 0 1
of this circuit is such that whichever output is 1 (d) 1 0 1 0
gives the desired magnitude comparison. (e) 0 1 0 1
(f) 1 1 1 1
(a) Using NAND and INVERTER gates only, de-
termine the number of gates required. For each row in the table, determine Q and Q̄, and
(b) Using NOR and INVERTER gates only, de- comment on the result.
termine the number of gates required. *6.1.45 Let the circuit of Figure 6.1.18 be given the inputs
(c) Which realization requires the least number shown in Figure P6.1.45, with the initial value of
of gates? Q being 1. Find the timing diagram (i.e., Q as a
function of time).
6.1.42 Draw the logic diagram of an SR latch using only
NAND gates, and obtain the truth table for that 6.1.46 Consider the case of a positive-edge triggered D
implementation. flip-flop with preset and clear, as shown in Figure
6.1.22 of the text. With the input signals shown in
6.1.43 Complete the timing diagram of Figure P6.1.43 of Figure P6.1.46, find the timing diagram (i.e., plot
an SR latch. Q and Q̄ as a function of time).
6.1.44 You are to construct a modified truth table for 6.1.47 (a) Draw the logic diagram of the enabled D latch
the circuit realization of the SRFF shown in Fig- using only NAND gates.
ure 6.1.18. As indicated in the text, you guess (b) Complete the timing diagram of Figure
an output and then go back to check it for self- P6.1.47(a) of the D latch whose block diagram
consistency. In order to get you started, a part of and truth table are given in Figure P6.1.47(b).
the table is given:
Co′
A
Half-adder Co
B S′ A
Y
Half-adder Co′′
Ci S
A S
B Full-adder Y
Ci Co B
A
AB = D
B (A < B)
A A
A AB
B
(AB + AB) = E
(A = B)
A
AB
B
B
A
AB = C (A > B)
B
Figure P6.1.41
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Copyright OUP
PROBLEMS 333
S Figure P6.1.43
1 Figure P6.1.45
S
0
1
R
0
Figure P6.1.46
Ck
Preset
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Clear
E Figure P6.1.47
(a)
Inputs Outputs
D D Q E D Q Q
0 d Qn Qn
Q 1 0 0 1
E E
1 1 1 0
(b)
6.1.48 A JK flip-flop is shown in Figure P6.1.48(a). However, they suffer from a major problem in
(a) Modify it to operate like the D flip-flop of that their contacts do not close immediately but
Figure P6.1.48(b). continue to make and break for some time after. To
avoid such an undesirable state (because it causes
(b) Modify the JK flip-flop to operate like the T
the logic state of the circuit to fluctuate), an SRFF
flip-flop of Figure P6.1.48(c).
is placed between the switch and the circuit, as
6.1.49 When the J and K inputs of a JKFF are tied to shown in Figure P6.1.50. Explain the operation
logic 1, this device is known as a divide-by-2 as a buffer.
counter. Complete the timing diagram shown in
6.1.51 J and K are the external inputs to the JKFF shown
Figure P6.1.49 for this counter.
in Figure P6.1.51. Note that gates 1 and 2 are
*6.1.50 An interesting application of the SRFF is as a
enabled only when the clock pulse is high. Con-
buffer in overcoming contact bounce in mechan-
sider the four cases of operation and explain what
ical switches. These switches, of the toggle type,
happens.
may be used to change the logic state in a circuit.
Copyright OUP
Input Output
J Q D Q Q
T Q Q
Ck T
0 Qn Qn
K Q Ck Q Q
1 Qn Qn
(a) (b) (c)
Figure P6.1.48
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
S Q
“High” switch To logic circuit
R Q
Ck
Q
Q
Feedback loop
A
J 1
S Q
Ck
R Q
B
K 2
Feedback loop
Figure P6.1.51
(a) J K = 00
(b) J K = 10 A B C Output = 1
(c) J K = 01 0 0 0 F0
(d) J K = 11 0 0 1 F1
0 1 0 F2
6.1.52 Figure P6.1.52 shows the master–slave JKFF. As- 0 1 1 F3
suming that the output changes on the falling edge 1 0 0 F4
of the clock pulse (i.e., when the clock pulse goes 1 0 1 F5
1 1 0 F6
from high to low), discuss the operation of the 1 1 1 F7
flip-flop, and obtain a table indicating the state of
normal output Q after the passage of one clock
pulse for various combinations of the inputs JK. *6.2.2 (a) Excess-3 code is a 4-bit binary code for the
6.2.1 A table for the direct 3-bit binary decoding is 10 decimal digits and is found useful in digi-
given. Show a block diagram for a 3-to-8 decoder tal computer arithmetic. Each combination is
and suggest a method for its implementation. found by adding 3 to the decimal number be-
ing coded and translating the result into direct
Copyright OUP
PROBLEMS 335
Master Slave Figure P6.1.52
J 1 S1 Q1 3 S2 Q2 Q2
K 2 R1 Q1 4 R2 Q2 Q2
Ck
S1 S0 I Q3 Q2 Q1 Q0 Figure P6.2.9
Q0
0 0 0 0 0 0 0
Q1 0 0 1 0 0 0 1
I
Q2 0 1 0 0 0 0 0
Q3 0 1 1 0 0 1 0
S1 S0 1 0 0 0 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 0 0
1 1 1 1 0 0 0
binary form. Set up a table for the excess-3 6.2.9 Given the block diagram and the truth table of a
code for the 10 decimal digits. demultiplexer, as shown in Figure P6.2.9, obtain
(b) Set up a table for a 4-to-10 line excess-3 de- its implementation.
coding. 6.2.10 Use a 4-to-1 multiplexer to simulate the following:
6.2.3 A common requirement is conversion from one (a) NAND logic function.
digital code to another. Develop a table of the BCD
(b) EXCLUSIVE-OR logic function.
code and the excess-3 code [see Problem 6.2.2(a)] ,
to be derived from it, for the decimal digits 0 to 9. (c) mi (1, 2, 4).
Show a block diagram for a BCD to excess-3 code 6.2.11 Show how a 16-to-1 multiplexer can be used to
converter. implement the logic function described by the
6.2.4 Draw a block diagram for a 2-to-4 decoder. Obtain following truth table.
the truth table, and develop a logic diagram.
6.2.5 Illustrate BCD-to-decimal decoding with a 4-to- A B C D Q
16 decoder, and draw the corresponding truth ta-
ble. 0 0 0 0 1
0 0 0 1 1
6.2.6 Based on the 8421 BCD code for decimal digits 0 0 1 0 1
0 through 9, develop a block diagram for a BCD 0 0 1 1 0
encoder and its implementation scheme. 0 1 0 0 1
0 1 0 1 0
*6.2.7 Implement the following Boolean functions by 0 1 1 0 1
employing 8-to-1 multiplexers (see Example 6.2.1 0 1 1 1 1
in the text for a table of minterms). 1 0 0 0 0
, 1 0 0 1 0
(a) F1 (A, B, C) = mi (0, 2, 4, 6) 1 0 1 0 1
, 1 0 1 1 0
(b) F2 (A, B, C) = mi (1, 3, 7) 1 1 0 0 0
6.2.8 Using two 8-to-1 multiplexers and one 2-to-1 mul- 1 1 0 1 1
1 1 1 0 1
tiplexer, show how a 16-to-1 multiplexer can be
1 1 1 1 0
obtained in the form of a block diagram.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
*6.2.12 Show an arrangement for multiplexing 64-to-1 by (b) Using T flip-flops, show the block diagram for
using four 16-to-1 multiplexers and one 4-to-1 a 3-bit ripple counter and its input and output
multiplexer. waveforms.
6.2.13 Sketch the output waveforms for the register of 6.2.26 Sketch the timing diagram for a 4-bit ripple
Figure 6.2.4(a) in the text if JKFFs are used in counter which uses T flip-flops. (See Problem
place of D flip-flops. 6.2.25.)
6.2.14 Show a block diagram of a 4-bit, parallel-input *6.2.27 Counting to moduli other than 2n is a frequent
shift-right register and briefly explain its opera- requirement, the most common being to count
tion. through the binary-coded decimal (BCD) 8421 se-
quence. All that is required is a four-stage counter
6.2.15 Draw the timing diagram of Example 6.2.3 for a which, having counted from 0000 to 1001 (i.e.,
4-bit shift-right register. decimal 0 to 9; ten states), resets to 0000 on the
next clock pulse. Develop a block diagram of an
6.2.16 Let the content of the register of Example 6.2.3 be
asynchronous decade counter and show its timing
initially 0111. With data in being 101101, what is
diagram.
the content of the register after six clock pulses?
6.2.28 Consider the synchronous counter shown in Figure
6.2.17 A shift register can be used as a binary (a) divide-
6.2.6 of the text.
by-2, and (b) multiply-by-2 counter. Explain.
*6.2.18 Show a block diagram of a 4-bit shift-right register (a) Draw its timing diagram.
using JKFFs.
(b) Show the implementation of the same syn-
6.2.19 Obtain a block diagram of a shift-left/right register chronous counter using D flip-flops.
using D flip-flops.
(c) Draw the timing diagram for part (b).
6.2.20 Design a 4-bit universal shift register.
6.2.29 Consider a series-carry synchronous counter with
6.2.21 (a) Show a block diagram of an SRFF connected T flip-flops shown in Figure P6.2.29 in which the
to store 1 bit. AND gates carry forward the transitions of the
flip-flops, thereby improving the speed. Sketch the
(b) Using 4 SRFFs obtain the block diagram for output waveform for the synchronous counter.
an SISO shift register.
6.2.30 Figure P6.2.30 shows the mod-8 counter which
(c) See what can be done to convert the SISO counts from 010 to 710 before resetting. Explain
device to SIPO. the operation of the counter and sketch the timing
diagram.
*6.2.22 Draw a block diagram of a 4-bit PIPO register and
briefly describe its operation. 6.2.31 Counters are used to realize various dividers in
the schematic representation of the digital clock
6.2.23 Taking parallel data from a computer to be fed shown in Figure P6.2.31. The blocks labeled
out over a single transmission line needs a PISO “logic array” are logic gate combinations required
device. Develop a block diagram for such a shift to activate the corresponding segments in order to
register and briefly explain its operation. display the digits.
6.2.24 Give a block diagram for a modulo-5 binary ripple (a) Check to see that the six outputs (Y 0 through
counter using JKFFs and draw its timing diagram. Y 5) display the number of hours, minutes, and
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
seconds.
6.2.25 (a) For a JKFF with J K = 11, the output changes
on every clock pulse. The change will be co- (b) If the date is also to be displayed, suggest
incident with the clock pulse trailing edge and additional circuitry.
the flip-flop is said to toggle, when T = 1, for
the T flip-flop. Show JKFF connected as a T *6.2.32 Determine the bits required for a D/A converter to
flip-flop and its timing diagram. detect 1-V change when Vref = 15 V.
Copyright OUP
PROBLEMS 337
Input pulses Figure P6.2.29
1 Output
T0 Y0 T1 Y1 T2 Y2
Ck Ck Ck
FF0 FF1 FF2
A(LSB) B C Figure P6.2.30
1 J A J B J C
Ck Ck Ck
K K K
Clock FF1 FF2 FF3

input line
Output to 7-segment display elements

6 kHz
clock Y0 Y1 Y2 Y3 Y4 Y5
100:1 Logic Logic Logic Logic Logic Logic

Divider array array array array array array
60:1 10:1 6:1 10:1 6:1 10:1

Divider Divider Divider Divider Divider Divider
Figure P6.2.31
6.2.33 For the 4-bit D/A converter of Figure 6.2.9, calcu- output waveform, i.e., I in as a function of digital
late: binary input.
(a) The maximum analog output voltage. 6.2.35 For a 6-bit weighted-resistor D/A converter, if R is
the resistor connected to the MSB, find the other
(b) The minimum analog output voltage.
resistor values needed, and calculate the maximum
(c) The smallest detectable analog output voltage analog output voltage, the minimum analog output
when Vref = −10 V. voltage, and the smallest detectable analog output
6.2.34 For the 4-bit weighted-resistor D/A converter
voltage if Vref = −15 V.
shown in Figure 6.2.9, prepare a table showing 6.2.36 Analyze the 2-bit R–2R ladder-network D/A con-
decimal, binary equivalent, and current I in in per verter, and corresponding to binary 01, 10, and 11,
unit, where 1 pu = Vref /R. Also sketch the analog obtain the equivalent circuits and determine the
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
analog output voltage as a fraction of the reference (a) How many bits long would the individual ad-
voltage. dresses have to be?
*6.2.37 Consider the 4-bit R–2R ladder D/A converter (b) If the bits are organized into 8-bit memory
with Vref = −10 V. Determine the analog output words or bytes, how many words would there
voltage when the binary input code is 1100. Also, be, and how many bits long would the ad-
find what reference voltage is to be used in order to dresses have to be?
obtain the corresponding decimal output voltage. (c) How is such a ROM described?
6.2.38 For a 10-bit R–2R ladder-network D/A converter (d) If each location requires its own word line
with an MSB resistor value of 10 k-, what is the emanating from a decoder AND gate, how
value of the LSB resistor? many gates would the decoder for 1K-byte
6.2.39 What is the basic difference between the weighted- ROM have to contain?
resistor and the R–2R ladder D/A converters? (e) Develop a two-dimensional addressing sys-
6.2.40 (a) Design a 6-bit R–2R ladder D/A converter. tem using a 6-to-64 decoder, a 64-word × 128-
(b) For Vref = 10 V, find the maximum output bit matrix, and 16-input multiplexers. How
voltage. many gates would such a system require?
6.2.46 Show the schematic arrangement for: (a) one-
(c) Determine the output voltage increment.
dimensional addressing, and (b) two-dimensional
(d) If the output voltage is to indicate increments addressing (see Problem 6.2.45), if a 32-kbit ROM
of 0.1 V, find the bits that must be used. is used to provide an 8-bit output word.
6.2.41 What is the basic difference between counter- 6.2.47 Repeat Problem 6.2.46 if a 64-kbit ROM is to
controlled and successive-approximation A/D provide a 16-bit output word.
converters? *6.2.48 Sketch a typical circuit for a 2-input, 4-output
*6.2.42 Consider the dual-slope A/D converter of Figure decoder.
6.2.15. 6.2.49 Digital watches display time by turning on a cer-
(a) Calculate the total charge on the integrator tain combination of the seven-segment display
due to the input voltage V in during the signal device.
integration time T. (a) Show a typical seven-segment display.
(b) Obtain an expression for the discharge time td (b) Develop a truth table for turning on the seg-
in terms of V in, V ref, and T. ments. The truth table should have inputs W,
X, Y, and Z to represent the binary equiva-
6.2.43 An 8-bit A/D converter is driven by a 1-MHz
lents of the decimal integers, and outputs S0,
clock. Estimate the maximum conversion time if:
S1, . . . , S7.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(a) It is a counter-controlled A/D converter. (c) Develop a typical circuit for one segment, S0.
(b) It is a successive-approximation A/D con- (d) Show a schematic diagram of the seven-
verter. segment decoder/driver block (available in IC
6.2.44 How many 500-page books can be stored on a form).
2400-ft, 1600-BPI magnetic tape if a typewritten 6.2.50 Develop a schematic diagram of a system in which
page contains about 2500 bytes? the D/A converter of Figure 6.2.13 can be em-
6.2.45 Suppose a ROM holds a total of 8192 bits. ployed in a digital voltmeter.
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7 Semiconductor Devices
7.1 Semiconductors
7.2 Diodes
7.3 Bipolar Junction Transistors
7.4 Field-Effect Transistors
7.5 Integrated Circuits
7.7 Practical Application: A Case Study—Electronic Photo Flash
Problems
Turning our attention to the internal structure of integrated-circuit (IC) building blocks, we
encounter a new family of circuit elements known as semiconductor devices, which include diodes
and transistors of various kinds. These circuit elements are nonlinear in their i–v characteristics.
Nonlinearity complicates circuit analysis and calls for new methods of attack. However, the
semiconductor devices are extremely important for the electronic circuits.
Active circuits contain not only passive circuit elements (such as resistors, capacitors, or
inductors) but also active elements such as transistors. All of the analog and digital blocks
discussed in Chapters 5 and 6 are active circuits, and transistors are essential for their internal
construction.
We shall present in this chapter the most important semiconductor devices, such as diodes,
bipolar junction transistors, and field-effect transistors. Chapters 8 and 9 will deal with their
applications in analog and digital circuits.
7.1 SEMICONDUCTORS
Semiconductors are crystalline solid materials whose resistivities have values between those of
conductors and insulators. Conductivity ranges from about 10−6 to about 105 S/m. Silicon is by far
the most important semiconductor material used today. The conductivity of pure silicon is about
339
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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340 SEMICONDUCTOR DEVICES
4.35 × 10−4 S/m. Good electrical characteristics and feasible fabrication technology have been
requisites for the prevalence of silicon technology. Compound semiconductors, such as gallium
arsenide, are being developed for microwave and photonic applications, while germanium is used
for a few special purposes.
When unbound negatively charged electrons move through a crystal, as shown in Figure
7.1.1(a), electrical conduction in semiconductors can take place with a direction of current opposite
to the direction of movement of the electrons. When a bound electron that should be present in the
valence bond is missing, the vacancy that arises is known as a hole. Holes are positively charged
particles with a charge equal in magnitude to that of the electron. Mobile positively charged holes
can also give rise to a current, as shown in Figure 7.1.1(b), with the direction of current in the
same direction as the movement of holes. Both holes and unbound electrons are known as charge
carriers, or simply carriers.
Pure semiconductors, known as intrinsic semiconductors, have very few charge carriers
and may hence be classified as almost insulators or very poor electrical conductors. However,
by adding (through a process known as doping) tiny controlled amounts of impurities (such
as boron, gallium, indium, antimony, phosphorus, or arsenic), a semiconductor can be made to
contain a desired number of either holes or free electrons and is then known as extrinsic (impure)
material. A p-type semiconductor contains primarily holes, whereas an n-type semiconductor
contains primarily free electrons. While holes are the majority carriers in a p-type material, it
is possible to inject electrons artificially into p-type material, in which case they become excess
minority carriers. Minority carriers do play a vital role in certain devices. The doping substance
is called an acceptor when the extrinsic semiconductor is the p-type with holes forming the
majority carriers and electrons forming the minority carriers. The doping substance is known as
the donor when the extrinsic semiconductor is the n-type with free electrons forming the majority
carriers and holes forming the minority carriers. Both p- and n-type semiconductors are vitally
important in solid-state device technology. Diodes, transistors, and other devices depend on the
characteristics of a pn-junction formed when the two materials are joined together as a single
crystal.
− − − + + + Figure 7.1.1 Electrical conduc-

tion. (a) Electrons moving from left
− − − + + +
to right give rise to a current di-
− − − + + + rected from right to left. (b) Holes
moving from left to right give rise
Direction of Direction of
to a current directed from left to
current current right.
(a) (b)
7.2 DIODES
A single pn-junction with appropriate contacts for connecting the junction to external circuits
is called a semiconductor pn-junction diode. The fundamental building block upon which all
semiconductor devices are based is the pn-junction. The most common two-terminal nonlinear
resistor is the semiconductor diode, whose symbol is shown in Figure 7.2.1(a). The terminal
voltage and current are denoted by vD and iD, respectively. The physical structure of the pn-
junction is shown in Figure 7.2.1(b). The junction is made by doping the two sides of the crystal
with different impurities. Figure 7.2.1(c) shows the volt–ampere curve (or static characteristic)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
of the ideal (or perfect) diode. Note that when vD is zero, iD is not and vice versa, a condition
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7.2 DIODES 341
corresponding to a switch. A diode acts like a switch that closes to allow current flow in the
forward direction, but opens to prevent current flow in the reverse direction. The diode thus acts
like a unilateral circuit element providing an on–off characteristic.
The physical operation of the junction can be described in terms of the charge-flow processes.
Usually there is a greater concentration of holes in the p-region than in the n-region; similarly,
the electron concentration in the n-region is greater than that in the p-region. The differences in
concentration establish a potential gradient across the junction, resulting in a diffusion of carriers,
as indicated in Figure 7.2.2(a). Holes diffuse from the p-region to the n-region, electrons from
the n-region to the p-region. The result of the diffusion is to produce immobile ions of opposite
charge on each side of the junction, as shown in Figure 7.2.2(b), and cause a depletion region (or
space-charge region) in which no mobile carriers exist.
The immobile ions (or space charge), being of opposite polarity on each side of the junction,
establish an electric field because of which a potential barrier is formed and drift current is
produced. The drift current causes holes to move from the n- to the p-region and electrons to
move from the p- to the n- region, as shown in Figure 7.2.2(c). In equilibrium and with no
external circuit, the drift and diffusion components of current are equal and oppositely directed.
The potential barrier established across the depletion region prohibits the flow of carriers across
the junction without the application of energy from an external source.
pn-Junction under Bias

Let an external source be connected between the p- and n-regions, as shown in Figure 7.2.3(a).
Figure 7.2.3(b) shows the circuit representation of the pn-junction or diode, and its external
circuit. The voltage source V, called the bias, either decreases or increases the potential barrier,
thereby controlling the flow of carriers across the junction. With V = 0, the barrier is unaffected
and the pn-junction has zero current. Positive values of V, known as forward biasing, decrease
the potential barrier, thereby increasing the number of electrons and holes diffusing across the
junction. The increased diffusion results in a net current, called the forward current, from the
p- to the n-region. With increased V, the forward current further increases rapidly because the
barrier is reduced even further. Making V negative (reverse biasing), on the other hand, increases
the potential barrier and reduces the number of carriers diffusing across the boundary. The drift
component produced by the electric field from the n- to the p-region causes a small current,
called the reverse current (or saturation current) IS. The magnitude of the saturation current
depends on the doping levels in the p- and n-type materials and on the physical size of the
p p
Metal
(ohmic) iD
contact
iD iD
anode + + p On
vD vD Off
cathode − − vD
n 0
Practical Ideal
device diode
(a) (b) (c)
Figure 7.2.1 pn-junction. (a) Circuit symbol for pn-junction diode. (b) Physical structure. (c) Volt–ampere
characteristic of an ideal (or perfect) diode.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Holes Figure 7.2.2 pn-junction diode with no external

diffuse voltage source. (a) Hole and electron diffusion.
p n
Electrons (b) Depletion region. (c) Drift of electrons and holes.
diffuse
(a)
Immobile ions
Acceptor Donor
− +
p − + n
− +
Depletion region
Space-charge density
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Electric field
x
Potential
x
(b)
Electric field
p Holes drift n
Electrons drift
(c)
junction. Increasing the reverse bias, however, does not affect the reverse current significantly
until breakdown occurs.
The static characteristic of a junction diode is shown in Figure 7.2.4(a), which describes
the dc behavior of the junction and relates the diode current I and the bias voltage V. Such a
characteristic is analytically expressed by the Boltzmann diode equation
I = IS (eV /ηVT − 1) (7.2.1)
Figure 7.2.3 pn-junction under

p n bias. (a) Physical structure.
(b) Semiconductor diode symbol.
I
I
V V
+ − + −
(a) (b)
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7.2 DIODES 343
Burnout
I
Maximum
specified
current
Forward
bias I, nA
(Breakdown voltage) 10
−VB
V
0
−IS 5
Reverse
Reverse
bias
breakdown −0.1 −0.05
V, V
0 0.05 0.1
Burnout
−IS
(a) (b)
I, µA I, mA
10 10
5 5
V, V V, V
−1.0 −0.5 0 0.5 1.0 −10 −5 0 5 10
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(c) (d)
Figure 7.2.4 Typical static volt–ampere characteristic (dc behavior) of a pn-junction diode. (a) Showing
reverse breakdown. (b), (c), (d) Omitting reverse breakdown (plotted on different scales).
in which η depends on the semiconductor used (2 for germanium and nearly 1 for silicon), and
VT is the thermal voltage given by
kT T
VT = = (7.2.2)
q 11, 600
where k is Boltzmann’s constant (= 1.381 × 10−23 J/K), q is the magnitude of the electronic
charge (= 1.602 × 10−19 C), and T is the junction temperature in kelvins (K = °C + 273.15). At
room temperature (T = 293 K), VT is about 0.025 V, or 25 mV. Using η = 1, Equation (7.2.1) is
expressed by
I = IS (e40V − 1) (7.2.3)
4 −4
or by the following, observing that e >> 1 and e << 1,
'
I e40V , V > 0.1 V
I= S (7.2.4)
−IS , V < −0.1 V
which brings out the difference between the forward-bias and reverse-bias behavior. The reverse
saturation current is typically in the range of a few nanoamperes (10−9 A). In view of the
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exponential factor in Equation (7.2.3), the apparent shape of the I–V curve depends critically
upon the scale of the voltage and current axes. Figures 7.2.4(b), (c), and (d) illustrate this point,
taking IS = 1 nA = 10−9 A. A comparison of Figure 7.2.4(d) with Figure 7.2.1(c) suggests that
one can use the ideal diode as a model for a semiconductor diode whenever the forward voltage
drop and the reverse current of the semiconductor diode are unimportant.
Based on the ability of the junction to dissipate power in the form of heat, the maximum
forward current rating is specified. Based on the maximum electric field that can exist in the
depletion region, the peak inverse voltage (maximum instantaneous value of the reverse-bias
voltage) rating is specified.
The most apparent difference between a real diode and the ideal diode is the nonzero voltage
drop when a real diode conducts in the forward direction. The finite voltage drop across the diode
is accounted for by V on, known as the offset or turn-on or cut-in or threshold voltage, as shown
in the alternate representation of the junction diode in Figure 7.2.5(a). Typical values of V on are
0.6 to 0.7 V for silicon devices and 0.2 to 0.3 V for germanium devices.
A closer approximation to the actual diode volt–ampere characteristic than that in Figure
7.2.5(a) is depicted in Figure 7.2.5(b), which includes the effect of the forward (dynamic)
resistance Rf, whose value is the reciprocal of the slope of the straight-line portion of the
approximate characteristic beyond the threshold voltage V on.
As an extension of the diode model of Figure 7.2.5(b), to allow for more realistic volt–ampere
characteristic slopes, the diode’s reverse resistance Rr for v < Von is included in the model of
Figure 7.2.6.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Figure 7.2.5 Forward-biased diode models. (a) With threshold voltage V on. (b) With threshold voltage V on
and forward resistance Rf.
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7.2 DIODES 345
+
i
Rf Slope = 1/Rf
v Ideal Rr
vD
diode
+
von
− v
0 von
Slope = 1/Rr
Figure 7.2.6 Piecewise-linear model of a diode, including the threshold voltage V on, forward resistance Rf,
and reverse resistance Rr.
Two types of capacitors are associated with a pn-diode: the junction capacitance CJ (also
known as depletion capacitance or space-charge capacitance), which is dominant for a reverse-
bias diode; and the diffusion capacitance CD, which is most significant for the forward-bias
condition and is usually negligible for a reverse-biased diode. For applications where the diode
capacitance is important, the small-signal equivalent circuit under back (reverse)-biased operation
includes Rr in parallel with CJ, and the parallel combination of Rf, CJ, and CD for forward-biased
operation.
Elementary Diode Circuits

Semiconductor diodes are used in a wide variety of applications. Their usage abounds in com-
munication systems (limiters, gates, clippers, mixers), computers (clamps, clippers, logic gates),
television (clamps, limiters, phase detectors), radar (power detectors, phase detectors, gain-control
circuits, parametric amplifiers), and radio (mixers, automatic gain-control circuits, message
detectors). Several simple diode circuits are presented in this section to serve only as examples.
In solving circuit problems with a nonlinear element, such as a diode, a useful technique
employed in many cases is a graphical approach. After plotting a nonlinear characteristic of the
element, such as the volt–ampere characteristic of a diode, one can superimpose a plot of the
circuit response (excluding the nonlinear element), which is the equation of a straight line in the
i–v plane given by the loop equation for the network. Such an equation of the straight line is
known as the load line equation. The intersection of the load line with the characteristic of the
nonlinear element in the i–v plane determines the quiescent (operating) point, which is the desired
solution. Example 7.2.1 illustrates the procedure.
EXAMPLE 7.2.1
Determine whether the diode (considered to be ideal) in the circuit of Figure E7.2.1(a) is
conducting.
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Solution
For determining the condition of the ideal diode, let us initially assume that it does not conduct,
and let us replace it with an open circuit, as shown in Figure E7.2.1(b). The voltage across the
10-- resistor can be calculated as 8 V by the voltage-divider rule. Then, applying KVL around
the right-hand loop, we get
8 = vD + 10 or vD = −2 V
That is to say, the diode is not conducting since vD < 0. This result is consistent with the initial
assumption, and therefore the diode does not conduct.
The student is encouraged to reverse the initial assumption by presuming that the diode is
conducting, and show the same result as obtained in the preceding.
5Ω vD 12 Ω Figure E7.2.1
+ −
Ideal diode
+
12 V 10 Ω 10 V
−
(a)
5Ω + vD − 12 Ω
+ + +
12 V 8V 10 Ω 10 V
− − −
(b)
EXAMPLE 7.2.2
Use the offset diode model with a threshold voltage of 0.6 V to determine the value of v1 for
which the diode D will first conduct in the circuit of Figure E7.2.2(a).
Solution
Figure E7.2.2(b) shows the circuit with the diode replaced by its circuit model. When v1 is zero
or negative, it is safe to assume that the diode is off. Assuming the diode to be initially off, no
current flows in the diode circuit. Then, applying KVL to each of the loops, we get
v1 = vD + 0.6 + 2 and v0 = 2
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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7.2 DIODES 347
Since vD = v1 − 2.6, the condition for the diode to conduct is v1 > 2.6 V.
D Figure E7.2.2
+
1.2 kΩ
+
v1 2V 600 Ω
−
−
(a)
1.2 kΩ vD 0.6 V
+ − + −
+
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Ideal diode
+ +
v1 2V 600 Ω v0
− −
−
(b)
EXAMPLE 7.2.3
We shall demonstrate load-line analysis to find the diode current and voltage, and then compute
the total power output of the battery source in the circuit of Figure E7.2.3(a), given the diode i–v
characteristic shown in Figure E7.2.3(b).
Solution
The Thévenin equivalent circuit as seen by the diode is shown in Figure E7.2.3(c). The load-line
equation, obtained by the KVL, is the equation of a line with slope −1/RTh and ordinate intercept
given by VTh /RTh ,
1 1
iD = − vD + VTh
RTh RTh
Superposition of the load line and the diode i–v curve is shown in Figure E7.2.3(d). From the
sketch we see that the load line intersects the diode curve at approximately 0.67 V and 27.5 mA,
given by the Q point (quiescent or operating point). The voltage across the 10-- resistor of Figure
E7.2.3(a) is then given by
V10- = 40IQ + VQ = 1.77 V
The current through the 10-- resistor is thus 0.177 A, and the total amount out of the source is
therefore given by 0.177 + 0.0275 = 0.2045 A. The total power supplied to the circuit by the
battery source is then
12 × 0.2045 = 2.454 W
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50 Ω 20 Ω
+
12 V 10 Ω D
−
20 Ω
(a)
iD, mA
60
40
20
vD, V
0 0.5 1.0 1.5 2.0 2.5
(b) iD, mA
RTh = 20 + 20 + (10||50) = 48.33 Ω 60

41.38 Q point
iD 40
+ 27.5
VTh = 10 (12) = 2 V D vD 20
− 60 Loa
d li
ne
vD, V
0 0.5 1.0 1.5 2.0 2.5
0.668
(c) (d)
Figure E7.2.3
EXAMPLE 7.2.4
Consider the circuit of Figure E7.2.4(a) with vS (t) = 10 cos ωt. Use the piecewise-linear model
of the diode with a threshold voltage of 0.6 V and a forward resistance of 0.5 - to determine the
rectified load voltage vL .
Solution
Figure E7.2.4(b) shows the circuit with the diode replaced by its piecewise-linear model. Applying
KVL,
vS = v1 + v2 + vD + 0.6 + vL or vD = vS − v1 − v2 − 0.6 − vL
The diode is off corresponding to the negative half-cycle of the source voltage. Thus no current
flows in the series circuit; the voltages v1, v2, and vL are all zero. So when the diode is not
conducting, the following KVL holds:
vD = vS − 0.6
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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7.2 DIODES 349
When vD ≥ 0 or vS ≥ 0.6 V, the diode conducts. Once the diode conducts, the expression for
the load voltage can be obtained by the voltage divider rule, by considering that the ideal diode
behaves like a short circuit. The complete expression for the load voltage is therefore given by
10
vL = (vS − 0.6) = 8.7 cos ωt − 0.52, for vS ≥ 0.6 V
10 + 1 + 0.5
and vL = 0 for vS < 0.6 V. The source and load voltages are sketched in Figure E7.2.4(c).
1Ω Figure E7.2.4
+ +
vS 10 Ω vL
− −
(a)
1Ω 0.5 Ω vD 0.6 V
+ − + −
+ v1 − + v2 − Ideal
+ diode +
vS 10 Ω vL
− −
(b)
v, V
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
10
vS
5
0
vL
−5
−10 t, s
0 0.005 0.01 0.015 0.02 0.025 0.03
(c)
EXAMPLE 7.2.5
Consider a forward-biased diode with a load resistance. Let the static volt–ampere characteristic
of the diode be given by Equations (7.2.1) and (7.2.2), and typically represented by Figure
7.2.4.
(a) For a dc bias voltage VB, obtain the load-line equation and the operating (quiescent) point
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(IQ, VQ) by graphical analysis. Extend the graphical analysis for different values of (i) load
resistance, and (ii) supply voltage.
(b) If, in addition
√ to the constant potential VB, an alternating or time-varying potential
vS (t) = 2 VS sin ωt is impressed across the circuit, discuss the dynamic (ac)
characteristics of the diode in terms of (i) small-signal current and voltage waveforms,
and (ii) large-signal current and voltage waveforms.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Solution
(a) The circuit of a forward-biased diode with a load resistance RL is shown in Figure
E7.2.5(a). The KVL equation yields
VB − V
VB = I RL + V or I=
RL
which is the load-line equation. The device equation (Boltzmann diode equation) and
the load-line equation involve two variables, I and V, whose values must satisfy both
equations simultaneously. As seen from Figure E7.2.5(b), Q is the only condition
satisfying the restrictions imposed by both the diode and the external circuit. The
intersection Q of the two curves is called the quiescent or operating point, indicated
by the diode current IQ and the diode voltage VQ.
Extension of the graphical analysis for different values of load resistance and
different values of supply voltage is shown in Figures E7.2.5(c) and (d).
(b) The diode circuit with dc and ac sources is shown in Figure E7.2.5(e). The total
instantaneous voltage impressed across the circuit is given by
√
vt = VB + 2 VS sin ωt and vt = v + iRL
√ √
The maximum and minimum values of vt are (VB + 2 VS ) and (VB − 2 VS ),
corresponding to the values of sin ωt equal to +1 and −1, respectively. The small-
signal current and voltage waveforms, for values of VS much less than VB, are shown
in Figure E7.2.5(f). The large-signal current and voltage waveforms, for values of VS
comparable to those of VB, are shown in Figure E7.2.5(g).
The motion of the load line traces the shaded area of the characteristics. The line segment
Q1Q2 is the locus of the position of the operating point Q. It is clear from the figures that the
waveforms of the diode voltage and current are functions of time. A point-by-point method
should be used for plotting the waveforms. For the small-signal case, the diode can be considered
to behave linearly and the segment Q1Q2 is approximated by a straight line. For the large-signal
case, on the other hand, the behavior is nonlinear. The time-varying portion of the response is not
directly proportional to vS(t), and a simple superposition of the direct and alternating responses
does not apply.
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7.2 DIODES 351
+ V −
I
RL
+ −
VB
(a)
VB
RL
Load line
I = (VB − V)/RL Device curve
Slope = −1/RL
IQ Operating (quiescent) point
0 V
0 Vo VB
Voltage
Diode across
voltage resistor
(b)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
RL1 < RL2 < RL3 < RL4
RL1
RL2
RL3
RL4
Q2 Q1
Q3 Load lines
Q4
0 V
VB
(c)
Figure E7.2.5 (a) Circuit of forward-biased diode. (b) Graphical analysis of forward-biased diode with load
resistance. (c) Graphical analysis for different values of load resistance. (d) Graphical analysis for different
values of supply voltage. (e) Diode circuit with dc and ac sources. (f) Small-signal current and voltage
waveforms. (g) Large-signal current and voltage waveforms.
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I Figure E7.2.5 Continued
Load line
slope = −1/RL
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Q5
Q4
Q3
Q2
Q1
0 V
VB1 VB2 VB3 VB4 VB5
(d)
+ v −
i
RL
+ vS (t) − + VB −
vt
+ −
(e)
Load lines
Diode current
ac component
varies about IQ,
the quiescent level
Q2
IQ Q
ωt Q1
v
VQ VB VB + √2VS
VB − √2VS
Diode voltage
ac component
varies about VQ,
the quiescent level
ωt
(f)
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7.2 DIODES 353
Load line
Q2
Motion of
load line
IQ Q
ωt Q1
v
(VB − √2VS) VQ VB (VB + √2VS)
Distortions
Combination of
direct and
time-varying levels
ωt
(g)
Zener Diodes
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Most diodes are not intended to be operated in the reverse breakdown region [see Figure 7.2.4(a)].
Diodes designed expressly to operate in the breakdown region are called zener diodes. A nearly
constant voltage in the breakdown region is obtained for a large range of reverse current through
the control of semiconductor processes. The principal operating region for a zener diode is the
negative of that for a regular diode in terms of both voltage and current. Zener diodes are employed
in circuits for establishing reference voltages and for maintaining a constant voltage for a load in
regulator circuits. Figure 7.2.7 shows the device symbol along with the linearized i–v curve and
the circuit model.
As seen from the i–v characteristic, a zener diode approximates an ideal diode in the forward
region. However, when the reverse bias exceeds the zener voltage VZ, the diode starts to conduct
in the reverse direction and acts like a small reverse resistance RZ in series with a battery VZ. Zener
diodes are available with values of VZ in the range of 2 to 200 V. The circuit model of Figure
7.2.7(c) incorporates two ideal diodes, Df and Dr, to reflect the forward and reverse characteristics
of the zener diode. The i–v curve thus has two breakpoints, one for each ideal diode, and three
straight-line segments.
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−VZ
v
0
i Break points i
VZ
1 +
Ideal Ideal
v RZ v Dr Df
diode diode
RZ
(a) (b) (c)

Figure 7.2.7 Zener diode. (a) Device symbol. (b) Linearized i–v curve. (c) Circuit model.
EXAMPLE 7.2.6
Consider a simple zener voltage regulator with the circuit diagram shown in Figure E7.2.6(a).
iout Figure E7.2.6
RS
+
VS vout
−
iZ
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(a)
iout
RS
RZ
+
VS vout
− +
VZ
−
(b)
(a) For a small reverse resistance RZ << RS and VS − RS iout > VZ , show that vout ∼
= VZ.
(b) For values of VS = 25 V, RS = 100 -, VZ = 20 V, and RZ = 4 -, find:
(i) vout for iout = 0 and iout = 50 mA.
(ii) The corresponding values of the reverse current iZ through the zener diode.
Solution
(a) When VS − RS iout > VZ , the zener diode will be in reverse breakdown. The forward
diode Df in our model of Figure 7.2.7(c) will be off while the reverse diode Dr is on. The
equivalent circuit is then given by Figure E7.2.6(b).
Straightforward circuit analysis yields
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7.2 DIODES 355

RS RZ
vout = VZ + VS − RZ iout
RS + R Z RS
For RZ << RS , RZ |VS /RS − iout | << VZ , in which case
vout ∼
= VZ
Thus, the zener diode regulates vout by holding it at the fixed zener voltage VZ, in spite
of the possible variations of VS or iout.
(b) For iout = 0,

100 4 100
vout = 20 + (25) = × 21 = 20.19 V
100 + 4 100 104
we have 20.19 − 20 = 4iZ , or iZ = 0.19/4 = 47.5 mA.

For iout = 50 mA,

100 4 100
vout = 20 + (25) − (4 × 0.05) = × 20.8 = 20 V
104 100 104
we have 20 − 20 = 4iZ , or iZ = 0.
Breakpoint Analysis
When a circuit consists of two or more ideal diodes, it will have several distinct operating
conditions resulting from the off and on states of the diodes. A systematic way of finding those
operating conditions is the method of breakpoint analysis. For a two-terminal network containing
resistors, sources, and N ideal diodes, and driven by a source voltage v, the i–v characteristic
will in general consist of N + 1 straight-line segments with N breakpoints. The i–v curve can be
constructed by following these steps:
1. For v → ∞, determine the states of all diodes, and write i in terms of v; do the same for
v → −∞.
2. With one diode to be at its breakpoint (i.e., having zero voltage drop and zero current),
find the resulting values of i and v at the terminals; do the same for each of the other
diodes.
3. Plot the i–v breakpoints obtained from step 2; connect them with straight lines and add
the end lines found in step 1.
Note that in step 2, if two or more diodes are simultaneously at breakpoint conditions, the
numbers of breakpoints and line segments of the i–v curve are correspondingly reduced.
EXAMPLE 7.2.7
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Determine the i–v characteristic of the network shown in Figure E7.2.7(a) by the use of breakpoint
analysis.
Solution
For v → ∞, D1 will be forward-biased while D2 will be reverse-biased (because v1 > 10 V).

Hence, with D1 on and D2 off, v = 2i − 12 + 4i, or i = v/6 + 2.
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For v → −∞, i = 0 since D1 will be off and D2 on. With D1 at its breakpoint, the circuit
is drawn in Figure E7.2.7(b). It follows that i = 0 and v1 = v + 12; but one does not know the
value of v1 and the state of D2. If one assumes v1 > 10 V, then D2 will be off and there is no
source for the current i1 = v1 /4. Hence one concludes that D2 must be on and v1 = 10 V. Then
the corresponding i–v breakpoint is at i = 0 and v = −2 V.
12 V Figure E7.2.7
Ideal diode Ideal diode
− +
+
+
i 2Ω D1 D2
+
v v1 4Ω 10 V
−
−
−
(a)
12 V
0V
+ − − +
+
0A +
i 2Ω i1 D2
D1 +
v v1 = v + 12 4Ω 10 V
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
−
−
−
(b)
12 V
0V
− + − +
+
+ 0A
i 2Ω D1 v1
4 +
v 4Ω v1 10 V
−
−
−
(c)
i, A
off i= v +2
n, D 2 6
D1 o 1
2.5 6
D2 breakpoint
2.0
D1 breakpoint
D1 off, D2 on
v, V
i=0 −2 0 3
(d)
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7.2 DIODES 357
With D2 at its breakpoint, the circuit is drawn in Figure E7.2.7(c). It follows that v1 = 10 V
and D1 must be on to carry i1 = v1 /4 = 2.5 A. Thus, the second breakpoint is at i = 2.5 A and
v = 3 V (because v = 2i − 12 + v1 ).
The complete i–v characteristic based on our results is shown in Figure E7.2.7(d). It can be
seen that both D1 and D2 will be on over the middle region −2 < v < 3.
Rectifier Circuits
A simple half-wave rectifier using an ideal diode is shown in Figure 7.2.8(a). The sinusoidal
source voltage vS is shown in Figure 7.2.8(b). During the positive half-cycle of the source, the
ideal diode is forward-biased and closed so that the source voltage is directly connected across
the load. During the negative half-cycle of the source, the ideal diode is reverse-biased so that the
source voltage is disconnected from the load and the load voltage as well as the load current are
zero. The load voltage and current are of one polarity and hence said to be rectified. The output
current through the load resistance is shown in Figure 7.2.8(c).
In order to smooth out the pulsations (i.e., to eliminate the higher frequency harmonics) of
the rectified current, a filter capacitor may be placed across the load resistor, as shown in Figure
7.2.9(a). As the source voltage initially increases positively, the diode is forward-biased since
the load voltage is zero and the source is directly connected across the load. Once the source
reaches its maximum value VS and begins to decrease, while the load voltage and the capacitor
voltage are momentarily maintained at VS, the diode becomes reverse-biased and hence open-
circuited. The capacitor then discharges over time interval t 2 through RL until the source voltage
vS(t) has increased to a value equal to the load voltage. Since the source voltage at this point
in time exceeds the capacitor voltage, the diode becomes once again forward-biased and hence
closed. The capacitor once again gets charged to VS. The output current of the rectifier with the
filter capacitor is shown in Figure 7.2.9(b), and the circuit configurations while the capacitor gets
charged and discharged are shown in Figure 7.2.9(c). The smoothing effect of the filter can be
improved by increasing the time constant CRL so that the discharge rate is slowed and the output
current more closely resembles a true dc current.
Figure 7.2.8 Simple half-wave

Ideal diode rectifier. (a) Circuit with ideal
+ diode. (b) Input source voltage. (c)
vS vS (t) = VS sin ωt Load RL iL(k) Output current through load resis-
− resistance tance.
(a)
vS iL
VS
VS RL
t t
Diode Diode
closed closed
Diode
(b) open
(c)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Ideal diode iL(t)

+
vS (t) = VS sin ωt Filter C RL Load
− capacitor resistance
(a)
Capacitor charges
Time Capacitor
iL
constant discharges
VS CRL
RL
t
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
t1 t2
(b)
Diode Diode
+ +
vS (t) C RL vS (t) C RL
− −
0 ≤ t ≤ t1 t1 ≤ t ≤ t2 + t1
(c)
Figure 7.2.9 Rectifier with filter capacitor. (a) Circuit. (b) Output current of rectifier with filter capacitor.
(c) Circuit configurations while capacitor gets charged and discharged.
The full-wave rectifier using ideal diodes is shown in Figure 7.2.10(a). Figure 7.2.10(b)
shows circuit configurations for positive and negative half-cycles of the input source voltage
vS (= VS sin ωt), and Figure 7.2.10(c) shows the rectified output voltage across the load resistance
RL . The full-wave rectification can be accomplished by using either a center-tapped transformer
with two diodes or a bridge rectifier circuit with four diodes.
7.3 BIPOLAR JUNCTION TRANSISTORS

The family of bipolar junction transistors has two members: the npn BJT and the pnp BJT. Both
types contain semiconductor junctions which operate with bipolar internal currents consisting of
holes and electrons. These are illustrated in Figure 7.3.1 along with their circuit symbols. The
emitter in the circuit symbol is identified by the lead having the arrowhead. The arrow points
in the direction of conventional emitter current flow when the base–emitter junction is forward
biased. A transistor can operate in three modes: cutoff, saturation, and active. In the active mode,
for an npn BJT, the base–emitter junction (BEJ) is forward-biased by a voltage vBE, while the
collector–base junction (CBJ) is reverse-biased by a voltage vCB. Thus for an npn BJT, as shown
in Figure 7.3.1(a), iB and iC are positive quantities such that iB + iC = iE . For a pnp BJT on the
other hand, in the active region, the base–emitter and collector–base voltages are negative, and
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7.3 BIPOLAR JUNCTION TRANSISTORS 359
D1 D1
+ + +
1:2 Secondary Ideal diode
Primary RL vL(t) vS
+ vS − vL
− − − +
vS (t) = VS sin ωt
+ +
− RL
vS vS
D2 − D2
Ideal −
transformer Ideal diode
(a)
+ +
vS vS
− vL − vL
− + − +
+ RL + RL
vS vS
− −
vS > 0 (positive half-cycle) vS < 0 (negative half-cycle)

(b)
vL(t)
VS
ωt
π 2π 3π
vS (t)
(c)
Figure 7.2.10 Full-wave rectifier. (a) Circuit. (b) Circuit configurations for positive and negative half-cycles.
(c) Rectified output voltage.
currents iB, iC, and iE are all negative quantities such that iE = iB + iC , that is to say, the bias
voltages as well as current directions are reversed compared to those of an npn BJT.
In an npn BJT, current flow is due to majority carriers at the forward-biased BEJ. While the
electrons diffuse into the base from the emitter and holes flow from the base to the emitter, the
electron flow is by far the more dominant part of the emitter current since the emitter is more
heavily doped than the base. Electrons become minority carriers in the base region, and these are
quickly accelerated into the collector by action of the reverse bias on the CBJ because the base is
very thin. While the electrons are going through the base region, however, some are removed by
recombination with majority-carrier holes. The number lost through recombination is only 5% of
the total or less. Due to the usual minority-carrier drift current at a reverse-biased pn junction, a
small current flow, on the order of a few microamperes, denoted by ICBO (collector current when
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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E n p n C E p n p C
(emitter) (collector) (emitter) (collector)
B (base) B (base)
C (collector) C (collector)
iC iC
(base) + (base) +
B + vCE B + vCE
iB − iB −
− −
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
vBE iE vBE iE
E (emitter) E (emitter)
(a) (b)
Figure 7.3.1 Bipolar junction transistors. (a) npn BJT structure and circuit symbol. (b) pnp BJT structure
and circuit symbol.
emitter is open-circuited), called reverse saturation current, results. BJTs biased in the active
region are shown in Figure 7.3.2.
It can be shown that the currents in a BJT are approximately given by
1 1
iE = ISE eVBE /VT = iB + iC = IC − ICBO (7.3.1)
α α
iC = iE + αICBO (7.3.2)
1−α 1
iB = (1 − α)iE − ICBO = iC − ICBO (7.3.3)
α α
where ISE is the reverse saturation current of the BEJ, ICBO is the reverse saturation current of
the CBJ, α (known as common-base current gain or forward-current transfer ratio, typically
ranging from about 0.9 to 0.998) is the fraction of iE that contributes to the collector current, and
VT = kT /q is the thermal voltage (which is the voltage equivalent of temperature, having a value
of 25.861 × 10−3 V when T = 300 K). Note that the symbol hFB is also used in place of α.
Another important BJT parameter is the common-emitter current gain, denoted by β (also
symbolized by hFE), which is given by

α β
β= or α= (7.3.4)
1−α 1+β
which ranges typically from about 9 to 500, being very sensitive to changes in α. In terms of β,
one can write
ICBO
iC = βiB + = βiB + (β + 1)ICBO = βiB + ICEO (7.3.5)
1−α
where ICEO = (β + 1)ICBO is the collector cutoff current when the base is open-circuited (i.e.,
iB = 0).
Figure 7.3.3 illustrates common-base static curves for a typical npn silicon BJT. In a common-
emitter configuration in which transistors are most commonly used, where the input is to the base
and the output is from the collector, the input and output characteristics are shown in Figure 7.3.4.
Copyright OUP
iE iC iE iC
E n p n C E p n p C
= iB + iC = iB + iC
iB iB
− + B − + + − B + −
vBE vCB vEB vBC
(a) (b)
Figure 7.3.2 BJTs biased in the active region. (a) npn BJT (iB, iC, and iE are positive). (b) pnp BJT (iB, iC,
and iE are negative).
With varying but positive base current, as seen from Figure 7.3.4(a), vBE stays nearly constant at
the junction threshold voltage Vγ , which is about 0.7 V for a typical silicon BJT.
The Early effect and the Early voltage −VA (whose magnitude is on the order of 50 to
100 V) for a typical npn BJT are illustrated in Figure 7.3.5, in which the linear curves are
extrapolated back to the vCE -axis to meet at a point −VA . The Early effect causes the nonzero
slope and is due to the fact that increasing vBE makes the width of the depletion region of the
CBJ larger, thereby reducing the effective width of the base. ISE in Equation (7.3.1) is inversely
proportional to the base width; so iC increases according to Equation (7.3.2). The increase in iC
can be accounted for by adding a factor to ISE and modifying Equation (7.3.2) such that αiE is
replaced by αiE (1 + vCE /VA ).
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
The common-emitter collector characteristics for a typical pnp BJT are shown in Figure
7.3.6.
A small-signal equivalent circuit of a BJT that applies to both npn and pnp transistors and is
valid at lower frequencies (i.e., ignoring capacitance effects) is given in Figure 7.3.7, where the
notation is as follows:
?vCE
?iC = gm ?vBE + (7.3.6)
ro
in which
*
∂iC ** ICQ
Transconductance gm = * = (7.3.7)
∂vBE * VT
Q *
1 ∂iC ** ICQ
Reciprocal of output resistance = * = (7.3.8)
ro ∂vCE * VA
Q
The derivatives are evaluated at the quiescent or operating point Q at which the transistor is biased
to a particular set of static dc currents and voltages. Notice the dependence of iC on both vBE and
vCE. Considering a small base-current change ?iB occurring due to ?vBE , one can define
* * *
?vBE ** ?iC ?vBE ** ∼ ∂iC ** 1 β
rπ = * = * = * = (7.3.9)
?iB * ?iB ?iC * ∂iB * gm gm
Q Q Q
and
vπ = ?vBE = rπ ?iB (7.3.10)
The large-signal models of a BJT for the active, saturated, and cutoff states are given in Figure
7.3.8. Note that in Figure 7.3.8(a) iE ∼
= βiB = iC if β >> 1. In Figure 7.3.8(b) the collector
battery may be replaced by a short circuit when the small value of V sat can be neglected. In Figure
Copyright OUP
7.3.8(c) ICEO may often be ignored at room temperature, in which case the model reduces to an
open circuit at all three terminals. Representative values for a silicon BJT at room temperature
are Vγ (junction threshold voltage) = 0.7 V, Vsat = 0.2 V, and ICEO = 0.001 mA. The one BJT
parameter that must be specified is the common-emitter current gain β, because it is subject to
considerable variation.
Figure 7.3.3 Common-base static curves for typical npn silicon BJT. (a) Emitter (input) characteristics. (b)
Collector (output) characteristics.
V␥
Figure 7.3.4 Common-emitter static curves for typical npn silicon BJT. (a) Input characteristics. (b) Output
characteristics.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Collector current iC , mA
Linear
active region
Saturation region
Increasing vBE
Breakdown
−VA Collector–emitter
0.6 to 0.8 V
(Early voltage) voltage vCE, V
Figure 7.3.5 Early effect and Early voltage of typical npn silicon BJT.
Saturation region
0
−3
−2.0 5
−2
0
−2
−1.6
Collector current, A
−15
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
M
−1.2 −10 im
ax
um
co
ll e
−0.8 cto
r di
s sip
−5 a ti o n
= 30 W
−0.4
(Cutoff) Base current = 0 mA

0 −10 −20 −30 −40 −50 −60 −70 −80
Collector voltage, V
Figure 7.3.6 Common-emitter collector characteristics for typical pnp BJT.
Despite the structural similarities, a pnp BJT has smaller current gain than a comparable npn
BJT because holes are less mobile than electrons. Most applications of pnp BJTs involve pairing
them with npn BJTs to take advantage of complementary operation. The large-signal models of
Figure 7.3.8 also hold for pnp BJTs if all voltages, currents, and battery polarities are reversed.
BJTs can provide the circuit properties of a controlled source or a switch.
ro Figure 7.3.7 Small-signal equivalent circuit of BJT.
rπ
B C
+ v −
π
∆iB = rπ ∆iB gmvπ ∆iC
= β∆iB
E ∆iE
Copyright OUP
Current– C C C
+ + +
controlled
iC = βiB iC < βiB iC = ICEO
current
+
source Vsat
iB > 0 iB > 0 iB = 0
vCE > Vγ vCE = Vsat vCE ≥ 0
B B (fixed) B
+ + + + +
Vγ Vγ
vBE = Vγ − vBE = Vγ − vBE < Vγ −

(fixed) iE = iC + iB
− = (β + 1)iB − −
E E E
(a) (b) (c)
Figure 7.3.8 Large-signal models of npn BJT. (a) Linear circuit model in idealized active state. (b) Idealized
saturated state. (c) Idealized cutoff state.
EXAMPLE 7.3.1
Consider the common-emitter BJT circuit shown in Figure E7.3.1(a). The static characteristics of
the npn silicon BJT are given in Figure E7.3.1(b) along with the load line. Calculate iB for vS = 1
V and 2 V. Then estimate the corresponding values of vCE and iC from the load line, and compute
the voltage amplification Av = ?vCE /?vS and the current amplification Ai = ?iC /?iB .
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Solution
iB = 0 for vS < Vγ and iB = (vS − Vγ )/RB for vS > V . With varying but positive base current,
vBE stays nearly constant at the junction threshold voltage Vγ , which is 0.7 V for a silicon BJT
[see Figure 7.3.4(a)].
vS1 − 0.7 1 − 0.7
Then, IBQ1 = = = 15 µA, for vS1 = 0.7 V
RB 20,000
Corresponding to 15-µA interpolated static curve and load line [see Fig. E7.3.1(b)], we get
vCE1 = 9.4 V, and iC1 = 1.3 mA;
2 − 0.7 1.3
for vS2 = 2 V, IBQ2 = = = 65 µA
20,000 20,000
C Figure E7.3.1 (a) Circuit. (b) Static

iC + curves and load line.
RB = 20 kΩ RC = 2 kΩ
B
+ vCE
+ iB +
vS VCC = 12 V
vBE −
−
− −
E
(a)
Copyright OUP
10 Figure E7.3.1 Continued

iB = 100 µA
iC, mA
8
80 µA
6
60 µA
Load line
4 40 µA
2 20 µA
iB = 0
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
0
0 2 4 6 8 10 12 14 16
vCE, V
(b)
Corresponding to 65-µA interpolated static curve and load line [see Fig. E7.3.1(b)], we get
vCE2 = 1 V and iC2 = 5.5 mA. Hence,
?vCE 1 − 9.4
Av = = = −8.4
?vS 2−1
and
?iC (5.5 − 1.3)10−3 4.2
Ai = = −6
= × 103 = 84
?iB (65 − 15)10 50
EXAMPLE 7.3.2
Given that a BJT has β = 60, an operating point defined by ICQ = 2.5 mA, and an Early voltage
VA = 50 V. Find the small-signal equivalent circuit parameters gm, ro, and rπ .
Solution
ICQ 2.5 × 10−3
gm = = = 97.35 × 10−3 S
VT 25.681 × 10−3
VA 50
ro ∼
= = = 20 k-
ICQ 2.5 × 10−3
β 60
rπ ∼
= = = 616 -
gm 97.35 × 10−3
Copyright OUP
EXAMPLE 7.3.3
Considering the circuit shown in Figure E7.3.3(a), find the state of operation and operating point
if the BJT has β = 80 and other typical values of a silicon BJT at room temperature.
C Figure E7.3.3
+
RB = 60 kΩ iC
vCE +
iB
B VCC = 20 V
+ −
vBE −
− E
RE = 4 kΩ iE
(a)
C
+
60 kΩ iC =
80 iB
vCE +
iB
B 20 V
+ − −
vBE = 0.7 V E −
iE =
4 kΩ
81 iB
(b)
Solution
Let us check the state of operation through some preliminary calculations. Application of KVL
yields
vBE = vCE − RB iB = VCC − RE iE − RB iB
If we assume the saturated state, then vCE = Vsat and iB > 0, so that
vBE = Vsat − RB iB < 0.2
which is in violation of the saturation condition: vBE = Vγ = 0.7 V.
If we assume the cutoff state, then iB = 0 and iE = iC = ICEO , so that
vBE = VCC − RE ICEO ∼
= 20 V
which is in violation of the cutoff condition: vBE < Vγ .
Having thus eliminated saturation and cutoff, the active-state model is substituted, as shown
in Figure E7.3.3(b).
The outer loop equation gives
20 − 60iB − 0.7 − 4 × 81iB = 0
where iB is the base current in mA. Solving,
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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7.4 FIELD-EFFECT TRANSISTORS 367
19.3
iB = = 0.05 mA
384
iC = 80iB = 4 mA
Hence,
vCE = 20 − 4 × 81iB = 3.8 V
which does satisfy the active-state condition: vCE > Vγ .
7.4 FIELD-EFFECT TRANSISTORS

Field-effect transistors (FETs) may be classified as JFETs (junction field-effect transistors), de-
pletion MOSFETs (metal-oxide-semiconductor field-effect transistors), and enhancement MOS-
FETs. Each of these classifications features a semiconductor channel of either n-type or p-type,
whose conduction is controlled by a field effect. Consequently, all FETs behave in a similar
fashion. The FET classification is illustrated in Figure 7.4.1 along with the corresponding circuit
symbols. FETs have the useful property that very little current flows through their input (gate)
terminals.
Junction FETs (JFETs)

The JFET is a three-terminal, voltage-controlled current device, whereas the BJT is principally
a three-terminal, current-controlled current device. The advantages associated with JFETs are
much higher input resistance (on the order of 107 to 1010 -), lower noise, easier fabrication, and
in some cases even the ability to handle higher currents and powers. The disadvantages, on the
other hand, are slower speeds in switching circuits and smaller bandwidth for a given gain in an
amplifier.
Figure 7.4.2 shows the n-channel JFET and the p-channel JFET along with their circuit
symbols. The JFET, which is a three-terminal device, consists of a single junction embedded in a
semiconductor sample. When the base semiconductor forming the channel is of a n-type material,
the device is known as an n-channel JFET; otherwise it is a p-channel JFET when the channel is
FET
Enhancement Depletion
JFET
MOSFET MOSFET
n p n p n p
channel channel channel channel channel channel
D D D D D D
G G G G G G
S S S S S S
G : gate; D : drain; S : source
Figure 7.4.1 FET classification.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Drain Drain
Metal Metal
n p
contact contact
Conducting Conducting
Gate channel Gate channel
p n
Metal Metal Metal Metal

contact contact contact contact
Depletion Source Depletion Source

region region
D (drain) D (drain)
G S (source) G S (source)
(gate) (gate)
(a) (b)
Figure 7.4.2 JFETs and their circuit symbols. (a) n-channel JFET. (b) p-channel JFET.
formed of a p-type semiconductor. The functions of source, drain, and gate are analogous to the
emitter, collector, and base of the BJT. The gate provides the means to control the flow of charges
between source and drain.
The junction in the JFET is reverse-biased for normal operation. No gate current flows because
of the reverse bias and all carriers flow from source to drain. The corresponding drain current is
dependent on the resistance of the channel and the drain-to-source voltage vDS. As vDS is increased
for a given value of vGS, the junction is more heavily reverse-biased, when the depletion region
extends further into the conducting channel. Increasing vDS will ultimately block or pinch off the
conducting channel. After the pinch-off, the drain current iD will be constant, independent of
vDS. Changing vGS (gate-to-source voltage) controls where pinch-off occurs and what the value
of drain current is.
It is the active region beyond pinch-off that is useful for the controlled-source operation, since
only changes in vGS will produce changes in iD. Figure 7.4.3 illustrates the JFET characteristics.
Part (a) shows the idealized static characteristics with two regions separated by the dashed line,
indicating the ohmic (controlled-resistance or triode) region and the active (controlled-source)
region beyond pinch-off. Note that iD is initially proportional to vDS in the ohmic region where
the JFET behaves much like a voltage-variable resistance; iD depends on vGS for a given value
of vDS in the active region. In a practical JFET, however, the curves of iD versus vDS are not
entirely flat in the active region but tend to increase slightly with vDS, as shown in Figure 7.4.3(b);
when extended, these curves tend to intersect at a point of −VA on the vDS axis. Another useful
characteristic indicating the strength of the controlled source is the transfer characteristic, relating
the drain current iD to the degree of the negative bias vGS applied between gate and source; a cutoff
region exists, indicated by the pinch-off voltage −VP , for which no drain current flows, because
both vGS and vDS act to eliminate the conducting channel completely.
Mathematically, the drain current in the active controlled-source region is approximately
given by [see Figure 7.4.3(a)]:

vGS 2
iD = IDSS 1 + (7.4.1)
VP
where IDSS, known as the drain–source saturation current, represents the value of iD when vGS = 0.
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Figure 7.4.3 JFET characteristics. (a) Idealized static characteristics. (b) Practical static characteristics.
(c) Transfer characteristic.
--`,,,``,,`,```,`
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Also shown in Figure 7.4.3(a) is a breakdown voltage, denoted by BVDGO, at which breakdown in
the drain–gate junction occurs in the channel near the drain. For most JFETs, BVDGO ranges from
about 20 to 50 V. The dependence of iD on vDS, as shown in Figure 7.4.3(b), can be accounted for
by applying a first-order correction to Equation (7.4.1),
2
vGS vDS
iD = IDSS 1+ 1+ (7.4.2)
VP VA
A small-signal equivalent circuit (valid at low frequencies where capacitances can be

neglected) can now be developed based on Equation (7.4.2). Denoting the dc values at the operating
point by VGSQ, IDQ, and VDSQ, the small changes that occur can be expressed by
* *
∂iD ** ∂iD ** 1
? iD = * ?vGS + * ?vDS = gm ?vGS + ?vDS (7.4.3)
∂vGS * ∂vDS * ro
Q Q
where
* **
∂iD ** vGS vDS 1 *
gm = * = 2IDSS 1 + 1+ *
∂vGS * VP VA VP *
Q Q
1/2
2IDSS IDQ VDSQ 2 1/2
= 1+ ∼
= IDSS IDQ (7.4.4)
VP IDSS VA VP
and
* *
1 ∂iD ** vGS 2 1 ** IDQ /VA ∼ IDQ
= * = IDSS 1 + * = = (7.4.5)
ro ∂vDS * VP VA * 1 + (VDSQ /VA ) VA
Q Q
The small-signal equivalent circuit based on Equation (7.4.3) is shown in Figure 7.4.4.
∆iD Figure 7.4.4 JFET small-signal equiva-

G D lent circuit for low frequencies.
+
∆vGS gm ∆vGS ro
EXAMPLE 7.4.1
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Measurements made on the self-biased n-channel JFET shown in Figure E7.4.1 are VGS = −1
V, ID = 4 mA; VGS = −0.5 V, ID = 6.25 mA; and VDD = 15 V.
(a) Determine VP and IDSS.
(b) Find RD and RS so that IDQ = 4 mA and VDS = 4 V.
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Solution
(a) From Equation (7.4.1),

−1 2
4 × 10−3 = IDSS 1 +
VP
and

−0.5 2
6.25 × 10−3 = IDSS 1 +
VP
Simultaneous solution yields
IDSS = 9 mA and VP = 3 V
(b) For IDQ = 4 mA, VGS = −1 V,

1
RS = = 250 -
4 × 10−3
The KVL equation for the drain loop is
− VDD + IDQ RD + VDS + IDQ RS = 0

or
− 15 + 4 × 10−3 RD + 4 + 4 × 10−3 × 250 = 0
or
RD = 2.5 k-
+ VDD Figure E7.4.1
RD
ID D
+
G VDS
IG = 0
+ −
vGS S
−
VR = IGRG = 0 RG
RS
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MOSFETs
The metal-oxide-semiconductor construction leads to the name MOSFET, which is also known
as insulated-gate FET or IGFET. One type of construction results in the depletion MOSFET, the
other in the enhancement MOSFET. The names are derived from the way in which channels
are formed and operated. Both n-channel and p-channel MOSFETs are available in either type.
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The input resistance of a MOSFET is even higher than that of the JFET (typically on the order
of 1010 to 1015 -) because of the insulating layer of the gate. As in JFETs, the conductive gate
current is negligibly small in most applications. The insulating oxide layer can, however, be
damaged easily due to buildup of static charges. While the MOSFET devices are often shipped
with leads conductively tied together to neutralize static charges, users too must be careful in
handling MOSFETs to prevent damage due to static electricity. The MOSFETs are used primarily
in digital electronic circuits. They can also provide controlled-source characteristics, which are
utilized in amplifier circuits.
ENHANCEMENT MOSFETS
Figure 7.4.5 illustrates the cross-sectional structure of an n-channel enhancement MOSFET
and its symbol showing as a normally off device when used for switching purposes. When the
gate-to-source voltage vGS > 0, an electric field is established pushing holes in the substrate
away from the gate and drawing mobile electrons toward it, as shown in Figure 7.4.6(a). When
vGS exceeds the threshold voltage VT of the MOSFET, an n-type channel is formed along the gate
and a depletion region separates the channel from the rest of the substrate, as shown in Figure
7.4.6(b). With vGS > VT and vDS > 0, electrons are injected into the channel from the heavily doped
n+ source region and collected at the n+ drain region, thereby forming drain-to-source current iD,
as shown in Figure 7.4.6(b). Note that none of the electrons comes from the p-type portion of the
substrate, which now forms a reverse-biased junction with the n-type channel. As the gate voltage
increases above VT, the electric field increases the channel depth and enhances conduction. For
a fixed vGS and small vDS, the channel has uniform depth d, acting like a resistance connected
between the drain and source terminals. The MOSFET is then said to be operating in the ohmic
state.
With a fixed vGS > VT , increasing vDS will reduce the gate-to-drain voltage vGD (= vGS −
vDS ), thereby reducing the field strength and channel depth at the drain end of the substrate. When
vDS > (vGS − VT ), i.e., vGD < VT , a pinched-down condition occurs when the electron flow is
limited due to the narrowed neck of the channel, as shown in Figure 7.4.6(c). The MOSFET is
then said to be operating in a constant-current state, when iD is essentially constant, independent
of vDS.
Figure 7.4.7 illustrates the MOSFET behavior explained so far. When vGS ≤ VT , however,
the field is insufficient to form a channel so that the iD–vDS curve for the normally off state is
simply a horizontal line at iD = 0. The drain breakdown voltage BVDS ranges between 20 and
Insulating D (drain) D
(SiO2) p–type +
oxide layer semiconductor
substrate (body) iD
n+
(gate) G
p
vDS
G
n+ +
Metallic
film vGS
Heavily −
−
doped S (source) S
(a) (b)
Figure 7.4.5 n-channel enhancement MOSFET. (a) Cross-sectional structure. (b) Symbol.
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D D D
n–type Depletion −
iD region iD
channel vGD < VT
n+ n+ + n+ +
Electrons +
G Electric G d G d
p vDS > 0 p vDS > vGS − VT
+ field + n + n
Holes
n+ n+ − n+ −
vGS > 0 vGS > VT vGS > VT
− − −
S S S
(a) (b) (c)
Figure 7.4.6 Internal physical picture in an n-channel enhancement MOSFET. (a) Movement of electrons
and holes due to electric field. (b) Formation of n-type channel. (c) Pinched-down channel.
iD Figure 7.4.7 Idealized iD–vDS curve of an n-channel enhance-

Ohmic Breakdown ment MOSFET with fixed vGS > VT .
state
Constant–current
state
vDS
0 vGS − VT BVDS
50 V, at which the drain current abruptly increases and may damage the MOSFET due to heat if
operation is continued. The gate breakdown voltage, at about 50 V, may also cause a sudden and
permanent rupture of the oxide layer.
Figure 7.4.8 shows the characteristics of a typical n-channel enhancement MOSFET. In the
ohmic region where vGS > VT and vDS < vGS − VT , the drain current is given by

iD = K 2(vGS − VT )vDS − vDS 2

(7.4.6)
where K is a constant given by IDSS /VT2 having the unit of A/V2, and IDSS is the value of iD when
vGS = 2VT . The boundary between ohmic and active regions occurs when vDS = vGS − VT . For
vGS > VT and vDS ≥ vGS − VT , in the active region, the drain current is ideally constant and
given by
iD = K(vGS − VT )2 (7.4.7)
To account for the effect of vDS on iD, however, a factor is added,

vDS
iD = K(vGS − VT ) 1 +
2
(7.4.8)
VA
where VA is a constant that is in the range of 30 to 200 V. The n-channel enhancement MOSFET
with characteristics depicted in Figure 7.4.8 has typical values of VT = 4 V, VA = 200 V, and
K = 0.4 mA/V2.
The small-signal equivalent circuit for low frequencies is of the same form as Figure 7.4.4
for a JFET, with gm and ro evaluated from the equations
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vGS > VT
Ohmic
25 25 Pinch-off or active region vGS > VT
region
vDS < V vDS ≥ vGS − VT
v GS = 11
vGS − VT
Drain current iD , mA
20 20
10 V
15 15
9V
10 10
Cutoff 8V
region
5 5
VT
6V
vGS = VT = 4 V
0 4 8 12 0 4 8 12 16 20 24
Gate-to-source voltage vGS, V Drain-to-source voltage vDS, V
(a) (b)
Figure 7.4.8 Characteristics of an n-channel enhancement MOSFET. (a) Transfer characteristic. (b) Static
characteristics.
* *
∂iD ** vDS ** ∼
gm = * = 2K(vGS − VT ) 1 + * = 2 KIDQ (7.4.9)
∂vGS * VA *
Q Q
and
* −1 *
∂iD ** VA *
* ∼ VA
ro = * = * = (7.4.10)
∂vDS * K(vGS − VT ) *
2 IDQ
Q Q
in which all definitions are the same as those used previously for the JFET.
EXAMPLE 7.4.2
Consider the basic MOSFET circuit shown in Figure E7.4.2 with variable gate voltage. The
MOSFET is given to have very large VA, VT = 4 V, and IDSS = 8 mA. Determine iD and vDS for
vGS = 1, 5, and 9 V.
D Figure E7.4.2
+
iD RD = 5 kΩ
G vDS
+ +
vGS VDD = 20 V
− −
S
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Solution
(a) For vGS = 1 V: Since it is less than VT, the MOSFET is in the cutoff region so that
iD = 0, which corresponds to the normally off state of the MOSFET,
vDS = VDD = 20 V
(b) For vGS = 5 V: The MOSFET operates in the active region,

2 2
IDSS vGS −3 5
iD = (v GS − V T ) 2
= IDSS − 1 = 8 × 10 − 1 = 0.5 mA
VT2 VT 4
vDS = VDD − RD iD = 20 − (5 × 103 )(0.5 × 10−3 ) = 17.5 V
The active MOSFET behaves like a nonlinear voltage-controlled current source.

(c) For vGS = 9 V: Since it is greater than 2VT so that iD increases while vDS decreases, the
MOSFET is presumably in the linear ohmic state when
1
|vDS | ≤ (vGS − VT ) and vGS > VT
4
The theory for this case predicts that iD ∼
= vDS /RDS , where RDS is the equivalent drain-to-source
resistance given by
VT2
RDS =
2IDSS (vGS − VT )
Here the MOSFET acts as a voltage-controlled resistor. For our example,
42
RDS = = 200 -
2(8 × 10−3 )(9 − 4)
Since this resistance appears in series with RD,
VDD 20
iD = = = 3.85 mA
RD + RDS 5000 + 200
and
vDS = RDS iD = 200 × 3.85 × 10−3 = 0.77 V
which is less than 1/4(9 − 4) V.
Figure 7.4.9 shows a p-channel enhancement MOSFET which differs from an n-channel
device in that the doping types are interchanged. Channel conduction now requires negative gate-
to-source voltage or positive source-to-gate voltage. With vSG > VT and vSD > 0, iD flows
from source to drain, as shown in Figure 7.4.9(a). The p-channel and n-channel MOSFETs are
complementary transistors, having the same general characteristics but opposite current direction
and voltage polarities. By replacing vGS and vDS with vSG and vSD, respectively, the equations of
the n-channel MOSFET apply to the p-channel MOSFET. However, a p-type channel does not
conduct as well as an n-type channel of the same size because holes are less mobile than electrons.
Consequently, smaller values of IDSS are typical of the p-channel MOSFETs.
DEPLETION MOSFETS
Figure 7.4.10 illustrates depletion MOSFETs and their symbols. Because the channel is built
in, no field effect is required for conduction between the drain and the source. The depletion
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Figure 7.4.9 p-channel enhancement MOSFET. (a) Cross-sectional structure. (b) Symbol.
MOSFETs, like JFETs, are normally on transistors, in which the field effect reduces conduction
by depleting the built-in channel. Figure 7.4.11(a) shows the formation of depletion regions due
to electron-hole recombinations with a negative gate voltage. With vGS ≤ −VP , where VP is the
pinch-off voltage, the depletion regions completely block the channel, making iD = 0, as shown in
Figure 7.4.11(b), which corresponds to the cutoff condition. With vGS > −VP and vGD < −VP ,
so that vDS > vGS + VP , the channel becomes partially blocked or pinched down when the device
operates in its active state.
Figure 7.4.12 shows the characteristics of a typical n-channel depletion MOSFET. With
VP = 3 V, iD = 0 for vGS ≤ −3 V. If −3 V < vGS ≤ 0, the device operates in the depletion
mode; if vGS > 0, it operates in the enhancement mode. The equations describing the drain current
are of the same form as for the JFET.
In the ohmic region, when vDS < vGS + VP ,
/ 0
vGS vDS vDS 2
iD = IDSS 2 1 + − (7.4.11)
VP VP VP
In the active region, when vDS ≥ vGS + VP ,
Heavily
D (drain)
doped
D D
Oxide + −
layer n+ iD iD
(gate) G
n p
vDS vSD
G G
Metallic n+ + −
film
vGS vSG
n–channel
− +
− +
S (source) S S
(a) (b) (c)
Figure 7.4.10 Depletion MOSFETs. (a) Structure of n-channel depletion MOSFET. (b) Symbol of n-channel
depletion MOSFET. (c) Symbol of p-channel depletion MOSFET.
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D D D
iD = 0 iD
vGD < −VP
Depletion
n+ regions n+ n+
G G G d
d
p vDS > vGS + VP
n +
p
n+ n+ n+ p
vGS < 0 vGS ≤ −VP vGS > −VP
−
S S S
(a) (b) (c)
Figure 7.4.11 Internal physical picture in n-channel depletion MOSFET. (a) Formation of depletion regions.
(b) Cutoff condition. (c) Active state.
vDS ≥ vGS + VP
vDS < vGS + VP

25 25 Active region
Ohmic
region vGS = +2 V
20 20
vGS > −VP
1V
15 15
10 10 0V
IDSS
Cut off vGS ≤ −VP
5 5 −1 V
−VP
−2 V
−4 −2 0 2 0 2 4 6 8 10 12
Gate-to-source voltage vGS, V Drain-to-source voltage vDS, V
(a) (b)
Figure 7.4.12 Characteristics of n-channel depletion MOSFET. (a) Transfer characteristic. (b) Static
characteristics.
2
vGS vDS
iD = IDSS 1+ 1+ (7.4.12)
VP VA
where VA and IDSS are positive constants, and the factor (1 + vDS /VA ) is added to account
approximately for the nonzero slope of the iD–vDS curves of a practical device, as was done in
Equation (7.4.2). The small-signal equivalent circuit for low frequencies is of the same form as
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Figure 7.4.4 for a JFET.
EXAMPLE 7.4.3
An n-channel depletion MOSFET, for which IDSS = 7 mA and VP = 4 V, is said to be operating
in the ohmic region with drain current iD = 1 mA when vDS = 0.8 V. Neglecting the effect of
vDS on iD, find vGS and check to make sure the operation is in the ohmic region.
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Solution
Applying Equation (7.4.11):

/( 1
0
iD vDS 2 VP
vGS = VP + −1
IDSS VP 2vDS
/( 1 0
1 0.8 2 4
=4 + − 1 = −2.17 V
7 4 1.6
Check: vDS = 0.8 V < vGS + VP = −2.17 + 4 = 1.83 V. The ohmic-region operation is verified.
While there is no difference in the general shape of the characteristics between the depletion
and enhancement MOSFETs, the practical distinction is the gate voltage range. In particular, a
depletion MOSFET can be in the active region when vGS = 0, whereas an enhancement MOSFET
must have vGS > VT > 0.
While a JFET behaves much like a depletion MOSFET, there are several minor differences
between JFETs and depletion MOSFETs. First, with vGS < 0, the junction in the JFET carries a
reverse saturation gate current iC ∼ = −IGSS , which is quite small (on the order of 1 nA) and can
usually be neglected. Second, any positive gate voltage above about 0.6 V would forward-bias the
junction in the JFET, resulting in a large forward gate current. Thus, enhancement-mode operation
is not possible with JFETs. On the side of advantages for JFETs, the channel in a JFET has greater
conduction than the channel in a MOSFET of the same size, and the static characteristic curves
are more nearly horizontal in the active region. Also, JFETs do not generally suffer permanent
damage from excessive gate voltage, whereas MOSFETs would be destroyed.
The transistor is operated within its linear zone and acts like a controlled source in electronic
amplifiers. It is also used in instrumentation systems as an active device. In digital computers or
other electronic switching systems, a transistor effectively becomes a switch when operated at
the extremes of its nonlinear mode.
7.5 INTEGRATED CIRCUITS

For the fabrication of semiconductor circuits, there are three distinct technologies employed:
1. Discrete-component technology, in which each circuit element is an individual component
and circuit construction is completed by interconnecting the various components.
2. Monolithic technology, in which all the parts (such as transistors, resistors, capacitors, and
diodes) needed for a complete circuit (such as an amplifier circuit) are constructed at the
same time from one silicon wafer (which is typically 5 mils or 0.005 inch in thickness).
3. Hybrid technology, a combination of the preceding two technologies, in which various
circuit components constructed on individual chips are connected so that the hybrid IC
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
resembles a discrete circuit packaged into a single, small case.

Integrated circuits (ICs), in which several transistors, resistors, wires, and even other com-
ponents are all fabricated in a single chip of semiconductor, are ideal building blocks for
electronic systems. Space, weight, cost, and reliability considerations gave much impetus for
the development of ICs. The ability to place circuit elements closer on an IC chip helps in
extending the frequency range of the devices. Whereas the IC technology involves the use of only
solid-state devices, resistors, and capacitors, the elimination of inductors is necessitated by the
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fact that typical semiconductors do not exhibit the magnetic properties needed to realize practical
inductance values.
ICs are made by microfabrication technologies. The low cost of IC production is a result of
planar processing in which fabrication begins with a very flat disc of silicon wafer, 5 to 10 cm in
diameter and only 0.5 mm thick. The small electronic structures to be built on it are then produced
photographically. The technique is known as photolithography, in which a photosensitive lacquer
(known as photoresist), which has the property of hardening when struck by light, is used. The
fabrication method requires a series of masks, photoetching, and diffusions.
MOSFET chips generally utilize either a p-channel or an n-channel device; hence, these
chips are known as PMOS and NMOS, respectively. Alternatively, both p-channel and n-channel
devices are used to form compound devices, in which case they are known as complementary
MOS (CMOS). Whereas the CMOS has the advantage of low power consumption, only a smaller
number of devices can be placed on the chip. MOS technologies are popularly used in computer
circuits due to their higher packing densities. Bipolar technologies, however, are used in high-
speed applications because they respond more quickly. The device fabrication methods are too
involved to be presented in this introductory text.
Small-scale integration (SSI) is used typically for a 20-component op amp, whereas large-
scale integration (LSI) puts an entire microprocessor, typically with 10,000 components, on a
single chip. The chief benefits from integrating many components on an IC are low cost, small
size, high reliability, and matched characteristics. Of the many IC packaging technologies, the
most popular is the dual-in-line package (DIP), which consists of a rectangular plastic or ceramic
case enclosing the IC, with protruding pin terminals. While an op amp is commonly supplied in
an 8-pin DIP for insertion into some larger circuit, a microprocessor may have a 40- to 64-pin
DIP to accommodate the many external connections needed for an LSI chip.

• Understanding of electrical conduction in semiconductor materials.
• i–v characteristics of a semiconductor diode (or of a pn-junction).
• Diode modeling and analysis of elementary diode circuits.
• Zener diode, its circuit model, and simple applications.
• Breakpoint analysis of a circuit containing two or more ideal diodes.
• Half-wave and full-wave rectifier circuits.
• Basic operation of bipolar junction transistors, along with their input and output character-
istics.
• Small-signal equivalent circuits and large-signal models of BJT.
• Recognizing the more common BJT configurations, and determining the voltage and current
gains.
• Basic operation of JFETs and their characteristics.
• JFET small-signal equivalent circuit (for low frequencies) and its applications for simple
circuit configurations.
• Basic operation of MOSFETs (enhancement and depletion types) and their characteristics.
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• MOSFET small-signal equivalent circuit (for low frequencies) and its application for simple
circuit configurations.
• Basic notions of integrated circuits.
Electronic Photo Flash

A simplified schematic diagram of the electric circuit of an electronic photo flash typically used
on cameras is shown in Figure 7.7.1. By passing a high current through the flash tube, a bright
flash of light is to be produced while the camera shutter is open. The power level is quite high,
as much as 1 kW. The total energy delivered, however, is only on the order of 1 j, since the flash
lasts less than 1 ms.
The electronic switch alternates between opening and closing approximately 10,000 times
per second. Energy is delivered by the battery over a period of several seconds and stored in the
capacitor. The stored energy is extracted from the capacitor whenever needed. The battery source
causes the current in the inductor to build up while the electronic switch is closed. Recall that the
current in an inductor cannot change instantaneously. When the switch opens, the inductor forces
current to go through the diode in one direction, charging the capacitor. Thus the diode allows the
capacitor to be charged whenever the electronic switch is open, and prevents the flow in the other
direction when the electronic switch is closed. The voltage on the capacitor eventually reaches
several hundred volts. When the camera shutter is opened, another switch is closed, enabling
the capacitor to discharge through the flash tube. Nowadays several practical electronic circuits
employ diodes, BJTs, FETs, and integrated circuits.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
R L Diode Switch that
closes when
Battery Electronic camera
C Flash
source switch shutter
opens
Figure 7.7.1 Simplified schematic diagram of the electric circuit of an electronic photoflash.
PROBLEMS
7.2.1 Explain the action of a pn-junction with bias. Con- that a diode is definitely not a resistor with a
sider both the forward bias and the reverse bias, constant ratio of V/I.
and use sketches wherever possible.
*7.2.3 A semiconductor diode with IS = 10µA and a
7.2.2 Assuming the diode to obey I = IS (eV /0.026 − 1), 1-k- resistor in series is forward-biased with a
calculate the ratio V/I for an ideal diode with IS = voltage source to yield a current of 30 mA. Find the
10−13 A for the applied voltages of −2, −0.5, source voltage if the diode I–V equation is given
0.3, 0.5, 0.7, 1.0, and 1.5 V, in order to illustrate by I = IS (e40V − 1). Also find the source voltage
Copyright OUP
PROBLEMS 381
that would yield I = −8µA. (c) Find the load current for different values of
7.2.4 A silicon diode is forward-biased with V = 0.5 supply voltage of 2.5, 5.0, 15.0, and 20.0 V.
V at a temperature of 293 K. If the diode current 7.2.10 Consider a reverse-biased diode with a source
is 10 mA, calculate the saturation current of the voltage VB in series with a load resistance RL .
diode. Write the KVL equation for the circuit.
7.2.5 With V = 50 mV, a certain diode at room tem- 7.2.11 Two identical junction diodes whose volt–ampere
perature is found to have I = 16 µA and satisfies relation is given by Equation (7.2.1) in which
I = IS (e40V − 1). Find the corresponding diffu- IS = 0.1 µA, VT = 25 mV, and η = 2, are
sion current. connected as shown in Figure P7.2.11. Determine
7.2.6 A diode is connected in series with a voltage the current in the circuit and the voltage across
source of 5 V and a resistance of 1 k-. The each diode.
diode’s saturation current is given to be 10−12 7.2.12 Consider the diode of Problem 7.2.6 with Von =
A and the I–V curve is shown in Figure P7.2.6. 0.7 V and the model of Figure 7.2.5(a). Evaluate
Find the current through the diode in the circuit the effect of V on on the answer.
by graphical analysis.
*7.2.13 Consider the model of Figure 7.2.5(a). In the cir-
7.2.7 For the circuit in Figure P7.2.7(a), determine the cuit of Figure P7.2.13, the diode is given to have
current i, given the i–v curve of the diode shown Von = 0.7 V. Find i1 and i2 in the circuit.
in Figure P7.2.7(b). 7.2.14 For the circuit shown in Figure P7.2.14(a), deter-
7.2.8 A diode with the i–v characteristic shown in Figure mine the diode current and voltage and the power
P7.2.8 is used in series with a voltage source of 5 delivered by the voltage source. The diode char-
V (forward bias) and a load resistance of 1 k-. acteristic is given in Figure P7.2.14(b).
(a) Determine the current and the voltage in the 7.2.15 Let the diode of Problem 7.2.14, with its given v–i
load resistance. curve, be connected in a circuit with an operating
(b) Find the power dissipated by the diode. point of Vd = 0.6 V and Id = 2 mA. If the diode is
to be represented by the model of Figure 7.2.5(b),
(c) Compute the load current for different load determine Rf and V on.
resistance values of 2, 5, 0.5, and 0.2 k-.
7.2.16 Consider the circuit shown in Figure P7.2.16. De-
*7.2.9 The diode of Problem 7.2.8 is connected in series
termine the current in the diode by assuming:
with a forward-bias voltage of 10 V and a load
resistance of 2 k-. (a) The diode is ideal.
(a) Determine the load voltage and current. (b) The diode is to be represented by the model
of Figure 7.2.5(a) with Von = 0.6 V, and
(b) Calculate the power dissipated by the diode.
I, mA Figure P7.2.6
6 Device characteristic
4
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
0 1 2 3 4 5 6 V, V
Copyright OUP
2 kΩ 3 kΩ Figure P7.2.7
id
+ +
4V 2 kΩ 1 mA vd
− −
(a)
id , mA
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
vd , V
0 0.5 1 1.5 2 2.5 3
(b)
Figure P7.2.8
7
6
Diode current, mA
0
0.2 0.4 0.6 0.8 0.1 1.2 1.4 1.6
Diode voltage, V
+ Figure P7.2.11
Diode A Diode B
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Supply
RL = 100 kΩ
15 V
Copyright OUP
PROBLEMS 383
i1 Figure P7.2.13
300 kΩ
+
i2 500 kΩ
10 V
−
id
− +
2V 500 Ω 8 mA vd
+ −
(a)
id , mA
vd , V
0 0.2 0.4 0.6 0.8 1
(b)
(c) The diode is to be represented by the model (a) Find the values of R1, R2, and R3.
of Figure 7.2.5(b) with Von = 0.6 V and (b) Suppose that both diodes have Rf = 10 -
Rf = 20 -. and Von = 0.5 V. Find the revised values of
7.2.17 Sketch the output waveform of vo(t) in the circuit the resistors and voltage sources (v1 and v2) in
shown in Figure P7.2.17 for the interval 0 ≤ t ≤ order to accomplish the same objective.
10 ms. 7.2.19 Consider the small-signal operation of a diode
as represented in the model of Figure 7.2.5(b)
*7.2.18 Consider the circuit shown in Figure P7.2.18 with
and the v–i curve given in Problem 7.2.14. Using
ideal diodes in order to approximate a two-
the circuit shown in Figure P7.2.19, develop an
terminal nonlinear resistor whose v–i curve sat-
approximate equation for the diode current.
isfies i = 0.001v2 in a piecewise-linear fashion.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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iD Figure P7.2.16
600 Ω Diode
+
9V 300 Ω 100 Ω
−
v (t) Figure P7.2.17

+
200 Ω Ideal diode
+ 600 Ω
10 V
v (t) vo(t)
+
− 6V
− −
t
0 10 mS
+ Figure P7.2.18
i
R1 R2
v=5V R3
+ +
V1 2V V2 3.5 V
− − −
Figure P7.2.19
+ RS = 1000 Ω
vS (t) = VS sin ωt id
= 0.01 sin ωt − +
vd = 5 + 0.01 sin ωt − RS id
+ −
5V
−
7.2.20 (a) In the circuit shown in Figure P7.2.20, the 7.2.21 For the zener diode regulator of Figure P7.2.20,
zener diode (with zero zener resistance) op- assuming that VS varies between 40 and 60 V, with
erates in its reverse breakdown region while RS = 100 - and RL = 1 k-, select a zener diode
the voltage across it is held constant at VZ and its regulator resistor such that VL is maintained
and the load current is held constant at VZ/RL, at 30 V. You may assume zero zener resistance.
as the source voltage varies within the limits 7.2.22 Choose R and find the smallest load resistance
VS,min < VS < VS,max . Find I max and I min allowed in Figure P7.2.20 when VZ = 12 V and
for the corresponding Rmin and Rmax, respec- the source is 25 V ± 20% with RS = 0. Assume
tively. a maximum desired diode current of 20 mA and a
minimum of 1 mA.
(b) Assuming RS = 0 and the source voltage
to vary between 120 and 75 V, for a load *7.2.23 Two zener diodes are connected as shown in Fig-
resistance of 1000 -, determine the maximum ure P7.2.23. For each diode VZ = 5 V. Reverse
value of the regulator resistor R if it is desired saturation currents are 2 µA for D1 and 4 µA for
to maintain the load voltage at 60 V. Also find D2. Calculate v1 and v2: (a) when VS = 4 V, and
the required power rating of the zener. (b) if VS is raised to 8 V.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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PROBLEMS 385
Source resistance Regulator resistor Figure P7.2.20
I + VZ /RL
RS R
+ +
VS VZ RZ = 0 VL = VZ RL
− −
−
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
DC source Regulator Load
+ Figure P7.2.23
+ D1 500 kΩ v1
−
VS +
−
D2 500 kΩ v2
−
7.2.24 Consider the circuit of Figure P7.2.20 with VS = 7.2.31 Consider a simple limiter circuit using ideal
94 V, VZ = 12 V, R = 820 -, RL = 220 -, diodes, as shown in Figure P7.2.31. Analyze its
RS = 0, and RZ = 25 -. Assume the reverse action to restrict the variation of voltage within
saturation current of the zener diode to be zero. certain limits.
(a) Find the load voltage, current, and power. 7.3.1 A transistor has a base current iB = 25 µA,
α = 0.985, and negligible ICBO. Find β, iE, and
(b) Calculate the power dissipated in R and in the iC.
diode. 7.3.2 A particular BJT has a nominal value of α 0.99.
7.2.25 For the circuit of Example 7.2.7 let the direction Calculate the nominal β. If α can easily change
of D2 be reversed. Find the i–v curve. ±1%, compute the percentage changes that can
*7.2.26 Consider the periodic pulsating dc voltage pro- occur in β.
duced by a half-wave rectifier. Find the Fourier *7.3.3 A silicon BJT has an emitter current of 5 mA at 300
series representation and the average dc value. K when the BEJ is forward-biased by vBE = 0.7
V. Find the reverse saturation current of the BEJ.
7.2.27 For the half-wave rectifier of Figure 7.2.8(a), let
Neglecting ICBO, calculate iC, β, and iB if α = 0.99.
the diode characteristic be the one given in Figure
P7.2.14(b) instead of being an ideal one. For VS = 7.3.4 The parameters of a BJT are given by α = 0.98,
2 V and RL = 500 -, sketch vL (t). ICBO = 90 nA, and iC = 7.5 mA. Find β, iB, and
iE.
7.2.28 Consider the circuit of Figure 7.2.9(a) with VS =
7.3.5 For a BJT with vBE = 0.7 V, ICBO = 4 nA,
10 V, ω = 2π × 103 rad/s, C = 10 µF, and RL =
iE = 1 mA, and iC = 0.9 mA, evaluate α, iB, iSE,
1000 -. Sketch vL (t) and find the minimum value
and β.
of vL (t) at any time after steady-state operation
has been achieved. 7.3.6 Consider the circuit of Figure P7.3.6 in which the
silicon BJT has β = 85 and other typical values
7.2.29 For the rectifier circuit of Figure 7.2.9(a), sketch
at room temperature. ICBO may be neglected.
the load current for C = 50 µF, R = 1 k-, and
vS (t) = 165 sin 377t V. (a) Compute iB, iC, and iE, and check whether the
transistor is in the active mode of operation.
7.2.30 Consider the bridge rectifier shown in Figure
(b) Check what happens if β is reduced by 10%.
P7.2.30. Describe its action as a full-wave rectifier,
assuming the diodes to be ideal. (c) Check what happens if β is increased by 20%.
Copyright OUP
Figure P7.2.30
D1 D4
+ + vL −
vS (t) = VS sin ωt
− RL
D3 D2
RS
−
D1 +
+ V2
vS (t) + + RL vL(t)
− V1 −
D2
−
Source Limiter Load
Figure P7.2.31
C Figure P7.3.6
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
430 kΩ 4.7 kΩ
+
12 V
B −
*7.3.7 Using the small-signal equivalent circuit of a BJT The main power source VCC in conjunction
with gm = 0.03 S, β = 75, and VA = 65 V, a load with the base-bias source IBB is used to establish
resistor RL is connected from the collector to the the operating point Q in Figure
√ P7.3.8(b). Let the
emitter, as shown in Figure P7.3.7. The transistor controlling signal be ib = 2 Ib sin ωt. Sketch
is biased to have a dc collector current of 6 mA. the sinusoidal variations of collector current iC,
(a) Calculate ?vL due to the small change ?vBE . collector voltage vC, and base current iB, super-
imposed on the direct values ICQ, VCQ, and IBQ,
(b) Find the corresponding change ?iB in the
respectively, and calculate the current gain corre-
base current.
sponding to a change in base current of 10 mA
7.3.8 The common-emitter configuration shown in Fig- (peak value).
ure P7.3.8(a) for a pnp BJT is most frequently used
7.3.9 (a) A simple circuit using an npn BJT containing
because the base current exerts a greater control on
only one supply is shown in Figure P7.3.9(a).
the collector current than does the emitter current.
Outline a procedure for determining the oper-
The idealized collector characteristics of the pnp
ating point Q. The collector characteristics of
transistor are shown in Figure P7.3.8(b) along with
the transistor are given in Figure P7.3.9(b).
the load line.
Copyright OUP
PROBLEMS 387
Figure P7.3.7
ro
rπ
C
B + v −
+ π
0.03 vπ +
∆vBE = 0.05 V ∆vL RL = 10 kΩ
− −
iC Figure P7.3.8
C
iB +
B RL
vC
− −
ib IBB VCC
+
E
(a)
iC , A
iB = −40 mA
−35 mA
Lo
ad
−2.0
−30 mA
lin
e
−25 mA
−1.5
−20 mA
Q IBQ = −15 mA
−1.0
−10 mA
−0.5 −5 mA
VCC
iB = 0
0
−5 −10 −15 −20 vC , V
(b)
(b) For VCC = 18 V, if the operating Q point is shown in Figure P7.3.10. Assuming the transistors
at a collector voltage of 10 V and a collector to be identical, neglecting ICBO of each BJT, find
current of 16 mA, determine the RC and RB αC and βC of the combination.
needed to establish the operating point. *7.3.11 The circuit of Figure P7.3.11 uses a pnp BJT
whose characteristics are shown in Figure 7.3.6.
7.3.10 The two-transistor combination known as Dar-
The parameter values are RC = 30 -, RB =
lington pair or Darlington compound transistor is
6 k-, VCC = 60 V, and VBE = −0.7 V.
often used as a single three-terminal device, as
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
Figure P7.3.9
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
−VCC
iCC
c
iC1
iC 2
b Q1 RC
RB
iB1
iE1
Q2
iB 2
iE 2
(a) Find IC and VCE at the operating point. 7.3.12 In the circuit of Figure P7.3.12 the transistor has
β = 99 and VBE = 0.6 V. For VCC = 10 V,
(b) Determine the power supplied by the VCC RF = 200 k-, and RC = 2.7 k-, determine the
source. operating point values of VCE and IC.
Copyright OUP
PROBLEMS 389
7.3.13 If the circuit of Example 7.3.1 is to switch from (b) Obtain an expression for the drain current iD
cutoff to saturation, find the condition on vS, given in the active region, and for the value of iD for
that the transistor has β = 100. the boundary between the ohmic and active
regions.
7.3.14 Consider the circuit of Example 7.3.3. For RE = 0
and β = 50, find iE. (c) Find the conditions for the linear ohmic op-
eration and the equivalent drain-to-source re-
7.3.15 If the BJT in the circuit of Example 7.3.1 has sistance.
β = 150, find iC and vCE when: (a) iB = 20 µA,
(d) Express the condition for operation in the cut-
and (b) iB = 60 µA. Specify the state of the BJT
off region.
in each case.
7.4.2 The JFET with parameters VP = 6 V and IDSS =
7.3.16 The circuit shown in Figure P7.3.16 has a pnp BJT 18 mA is used in the circuit shown in Figure P7.4.2
turned upside down. Find RB when vEC = 4 V and with a positive supply voltage. Find vGS, iD, and
β = 25. vDS. Note that the gate current is negligible for the
7.3.17 Reconsider the circuit of Figure P7.3.16. With arrangement shown.
β = 25, find the condition on RB such that iC has *7.4.3 Consider the circuit of Figure P7.4.2 with the
the largest possible value. same JFET parameters. Let RS be not specified.
Determine vGS, vDS, and RS for active operation at
7.4.1 Consider JFET characteristics shown in Figures
iD = 2 mA.
7.4.3 (a) and (c).
7.4.4 A JFET with IDSS = 32 mA and VP = 5 V is
(a) Write down the conditions for the operation biased to produce iD = 27 mA at vDS = 4 V. Find
to take place in the active region. the region in which the device is operating.
+
VCC
+E
vEB +
RC
−
RF B vEC
C − +
vEE = 10 V
RB iC −
RC = 3 kΩ
D Figure P7.4.2
G RD = 1.5 kΩ
S
+
VDD = 20 V
RS = 250 Ω
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
7.4.5 For a p-channel JFET in its active region, specify Assuming small vDS, find the channel resistance
the polarities of voltages and the directions of rDS for vGS = −2 V if the JFET’s parameters are
conventional currents. IDSS = 25 mA and VP = 3 V.
7.4.6 Consider the common-source JFET circuit shown 7.4.16 An n-channel enhancement MOSFET operates in
in Figure P7.4.6 with fixed bias. Sketch the si- the active region with very large VA, vGS = 6 V,
nusoidal variations of drain current, drain volt- VT = 4 V, and iD = 1 mA. Calculate K.
age, and gate voltage superimposed on the direct 7.4.17 Consider the MOSFET circuit with variable volt-
values at the operating point. Assume reasonable age shown in Example 7.4.2, with RD = 2 k-
common-source drain characteristics. and VDD = 12 V. The static characteristics of
7.4.7 A self-biased n-channel JFET used in the circuit the n-channel enhancement MOSFET are given
of Example 7.4.1 has the characteristics given in in Figure P7.4.17.
Figure P7.4.7 and a supply voltage VDD = 36 (a) Draw the load line and find the operating point
V, RS = 1 k-, and RD = 9 k-. Determine the if vGS = 4 V.
operating point and the values of VGSQ, IDQ, and
VDSQ. (b) Sketch the resulting transfer curves (i.e., iD
and vDS as a function of vGS) showing cutoff,
*7.4.8 In the p-channel version of the circuit of Example
active, and saturation regions.
7.4.1, with the JFET having VP = 4 V and IDSS =
−5 mA, find RD and RS to establish IDQ = −2 (c) For relatively undistorted amplification, the
mA and VDSQ = −4 V when VDD = −12 V. MOSFET circuit must be restricted to sig-
nal variations within the active region. Let
7.4.9 An n-channel JFET in the circuit configuration
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
vGS (t) = 4 + 0.2 sin ωt V. Sketch iD(t)

shown in Example 7.4.1 is operating at IDQ =
and vDS(t), and estimate the resulting voltage
6 mA and VGSQ = −1 V when VDS = 5 V.
amplification Av.
Determine RS and VDD if: (a) RD = 2 k-, and
(b) RD = 4 k-. (d) Let vGS (t) = 6 sin ωt, where ω is slow
7.4.10 An n-channel JFET is given to have VP = 3 V enough to satisfy the static condition. Sketch
and IDSS = 6 mA. iD(t) and vDS(t) obtained from the transfer
curves. Comment on the action of the MOS-
(a) Find the smallest value of vDS when vGS = −2 FET in the switching circuit.
V if the operation is to be in the active region.
7.4.18 Find idealized expressions for the active and
(b) Determine the corresponding iD for the small- ohmic states and sketch the universal character-
est vDS. istics of an n-channel enhancement MOSFET op-
7.4.11 Given that a silicon n-channel JFET has VP = 5 erated below breakdown.
V and IDSS = 12 mA, check whether the device 7.4.19 Let the circuit in Example 7.4.2 have VDD = 12 V
is operating in the ohmic or active region when and RD = 2 k-, and let the MOSFET have very
vGS = −3.2 V and iD = 0.5 mA. large VA, VT = 2.5 V, and IDSS = 8.3 mA.
7.4.12 For an n-channel JFET with VA = 350 V, IDSS =
(a) Determine vGS and vDS when iD = 4 mA.
10 mA, and VP = 3 V, find VDS that will cause
iD = 11 mA when vGS = 0. (b) Determine iD and vDS when the gate voltage is
6 V.
7.4.13 An n-channel JFET with VA = 300 V, VP = 2
V, and IDSS = 10 mA is to be operated in the 7.4.20 Consider the MOSFET connected as a two-
active mode. Determine iD when vDS = 10 V and terminal device, as shown in Figure P7.4.20. Dis-
vGS = −0.5 V. cuss its states of operation.
7.4.14 Sketch gm versus vGS for a JFET with IDSS = 10 7.4.21 Find the parameter values VT and IDSS for a p-
mA, VP = 3 V, VA = 100 V, and vDS = 10 V. See channel MOSFET with iD = 0 when vGS ≤ −3
what happens if VA → ∞. Also sketch ro versus V, and iD = 5 mA when vGS = vDS = −8 V. You
vGS. may neglect the effect of vDS on iD.
7.4.15 The drain current of a JFET in the ohmic region is 7.4.22 In a depletion MOSFET for which VP = 3 V and
approximated by IDSS = 11 mA, the drain current is 3 mA when vDS
/ 2 0 is set at the largest value that will maintain ohmic-
vGS vDS vDS
iD = IDSS 2 1+ − region operation. Find vGS if VA is very large.
VP VP VP
Copyright OUP
PROBLEMS 391
iD Figure P7.4.6
+
iG = 0 vD
G
− RD
+ +
vg = √2 Vg sin ωt vG −
+
VDD
VGG
+
ID , mA
10
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
6
0
VGS , V
−5 −4 −3 −2 −1 0
(a)
ID , mA
VGS = 0 V
10
−0.5 V
8
−1 V
6
−1.5 V
4 −2 V
−2.5 V
2 −3 V
−4 V
0 VDS , V
0 4 8 12 16 20 24 28 32 36
(b)
Figure P7.4.7 JFET characteristics. (a) Transfer characteristic. (b) Output characteristics.
Copyright OUP
10 Figure P7.4.17
5.5 V VGS = 5.0 V
ID , mA
8
6 4.5 V
4
4.0 V
2
3.5 V
3.0 V VGS ≤ 2.5 V
0 2 4 6 8 10 12 14 16
VDS , V
Figure P7.4.20
iD
+
D
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
iD
0A
v
G
+
vGS = v
−
−
S
*7.4.23 A depletion MOSFET is given to have large VA, (b) Find iD.
VP = 2.8 V, IDSS = 4.3 mA, vDS = 4.5 V, and
vGS = 1.2 V. (c) Comment on whether the device is operating
in the depletion mode or in the enhancement
(a) Is the MOSFET operating in the active region? mode.
Copyright OUP
8 Transistor Amplifiers
8.1 Biasing the BJT
8.2 Biasing the FET
8.3 BJT Amplifiers
8.4 FET Amplifiers
8.5 Frequency Response of Amplifiers
8.7 Practical Application: A Case Study—Mechatronics: Electronics Integrated with

Mechanical Systems
Problems
Amplifiers are circuits that produce an output signal which is larger than, but proportional to,
an input signal. The input and output signals can be both voltages or currents, or one or the
other, as in voltage-in current-out and current-in voltage-out amplifiers. The amplifier gain is
just the network’s transfer function, which is the ratio of output-to-input complex signals in the
frequency domain as found by complex analysis. Amplifiers find extensive use in instrumentation
applications. Sometimes, amplifiers are used for reasons other than gain alone. An amplifier may
be designed to have high input impedance so that it does not affect the output of a sensor while at
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
the same time giving a low output impedance so that it can drive large currents into its load, such
as a lamp or heating element. In some other applications, an amplifier with a low input impedance
might be desirable.
The first step in designing or analyzing any amplifier is to consider the biasing. The biasing
network consists of the power supply and the passive circuit elements surrounding the transistor
that provide the correct dc levels at the terminals. This is known as setting the Q point (quiescent
or operating point) with no signal applied. A good bias circuit must not only establish the correct
dc levels, but must maintain them in spite of changes in temperature, variations in transistor
characteristics, or any other sources of variation.
393
Copyright OUP
394 TRANSISTOR AMPLIFIERS
Thus, a biasing signal (current or voltage), in the absence of any other signals, places the
transistor at an operating or quiescent point of its i–v characteristics. Time-varying signals are
usually superimposed on dc biasing signals. Small variations of voltage and current about the
operating point are known as small-signal voltages and currents. While small-signal variations
are just a fraction of the power-supply voltage, the large-scale excursions of a power amplifier may
be comparable to the supply voltage. This chapter is devoted to the study of small-signal amplifiers,
in which the relationships between small-signal variables are linear. Graphical solutions including
the transistor’s general nonlinearity are not considered in this text.
A transistor model, having the same number of terminals as the transistor, is a collection of
ideal linear elements designed to approximate the relationships between the transistor small-
signal variables. While the small-signal model cannot be used to obtain information about
biasing, the ac device model considered in this chapter deals only with the response of the
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
circuit to small signals about the operating point. The transistor model is then substituted for
the transistor in the circuit in order to analyze an amplifier circuit. Under the assumption of
small-signal linear operation, the technique of superposition can be used effectively to simplify
the analysis.
Amplifier circuits can be treated conveniently as building blocks when analyzing larger
systems. The amplifier block may be represented by a simple small-signal model. A multistage
amplifier is a system obtained by connecting several amplifier blocks in sequence or cascade, in
which the individual amplifier blocks are called stages. Input stages are designed to accept signals
coming from various sources; intermediate stages provide most of the amplification; output stages
drive various loads. Most of these stages fall in the category of small-signal amplifiers.
The subject of amplifier frequency response has to do with the behavior of an amplifier as
a function of signal frequency. Circuit capacitances and effects internal to the transistors impose
limits on the frequency response of an amplifier. Minimization of capacitive effects is a topic of
great interest in circuit design.
After discussing biasing the BJTs and FETs to establish the operating point, BJT and FET
amplifiers are analyzed, and the frequency response of amplifiers is looked into. Advantages of
negative feedback in amplifier circuits are also mentioned.
8.1 BIASING THE BJT

A simple method of biasing the BJT is shown in Figure 8.1.1. While no general biasing procedure
that will work in all cases can be outlined, a reasonable approach is to assign 1/2 VCC as the drop
across the transistor, 3/8 VCC as the drop across RC to allow an adequate ac voltage swing capability
in the collector circuit, and 1/8 VCC as the drop across RE, so that RE is about 1/3 RC. With a specified
supply voltage VCC, biasing consists mainly of selecting values for VCEQ, ICQ, and IBQ = ICQ /β,
which define the operating Q point. One can then select
Figure 8.1.1 Method of biasing the BJT.

R1 RC ICC
C + +
B VCEG VCC
VB
− −
IBG
E VE
R2
I2 RE IEQ
Copyright OUP
8.2 BIASING THE FET 395
3VCC
RC = (8.1.1)
8ICQ
VCC VCC β
RE = = (8.1.2)
8(ICQ + IBQ ) 8(1 + β)ICQ
Noting that VB = VE + VBE in Figure 8.1.1, or VB = (VCC /8) + 0.7 for silicon, and selecting
I2 = 5IBQ , it follows then
∼ 0.7 + (VCC /8)
R2 = (8.1.3)
5IBQ
VCC − VB (7 VCC /8) − 0.7
R1 ∼
= = (8.1.4)
6IBQ 6IBQ
EXAMPLE 8.1.1
Apply the rule-of-thumb dc design presented in this section for a silicon npn BJT with β = 70
when the operating Q point is defined by ICQ = 15 mA and IBQ = 0.3 mA, with a dc supply
voltage VCC = 12 V, and find the resistor values of RC, RE, R1, and R2.
Solution
Applying Equations (8.1.1) through (8.1.4), we get

3(12)
RC = = 300 -
8(15 × 10−3 )
12(70)
RE = = 98.6 -
8(71)(15 × 10−3 )
[7(12)/8] − 0.7
R1 ∼
= = 5444 -
6(0.3 × 10−3 )
0.7 + (12/8)
R2 ∼
= = 1467 -
5(0.3 × 10−3 )
8.2 BIASING THE FET

Let us first consider biasing the JFET and then go on to biasing the MOSFET.
Biasing JFET
A practical method of biasing a JFET is shown in Figure 8.2.1. Neglecting the gate current, which
is usually very small for a JFET, we have
VDD R2
VG = (8.2.1)
R1 + R 2
The transfer characteristic of the JFET [see Figure 7.4.3(c)], neglecting the effect of vDS on iD, is
given by

vGS 2
iD = IDSS 1 + (8.2.2)
VP
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
Figure 8.2.1 Method of biasing the JFET.

R1 RD
D +
VG G VDD
S
−
RS
R2
From Figure 8.2.1, applying the KVL to the loop containing R2 and RS , the load-line equation is
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
VG − vGS
iD = (8.2.3)
RS
The operating point Q is the intersection of the load line with the transfer characteristic, from
which IDQ and VGSQ can be read. While no systematic bias-point design procedure to serve all
applications exists, a simple procedure that will serve a good number of problems is outlined
here. In establishing the operating point Q, compromising between high stability and high gain,
one may choose
IDSS
IDQ = (8.2.4)
3
Substituting this into Equation (8.2.2), we get
√
1− 3
VGSQ = √ VP ∼= −0.423VP (8.2.5)
3
Next, select VG to yield a reasonably low slope to the load line so that drain-current changes are
small,
VG = 1.5VP (8.2.6)
The voltage drop across RS is then given by
VG − VGSQ ∼
= 1.5VP + 0.423VP = 1.923VP (8.2.7)
so that
1.923VP 1.923VP 5.768VP
RS = = = (8.2.8)
IDQ IDSS /3 IDSS
Choosing R2 arbitrarily as
R2 = 100RS (8.2.9)
to maintain large resistance across the gate, R1 can be found,

R2 (VDD − VG ) VDD
R1 = = 100RS −1 (8.2.10)
VG 1.5VP
Next, to find RD, choosing the transistor’s drop to be equal to that across RD plus the pinch-off
voltage necessary to maintain the active-mode operation,
VDD − IDQ RS = VP + 2IDQ RD (8.2.11)
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8.2 BIASING THE FET 397
or
VDD − IDQ RS − VP 3(VDD − 2.923VP )
RD = = (8.2.12)
2IDQ 2IDSS
Note that the source voltage VDD must be larger than the minimum necessary to maintain adequate
voltage swings for ac signals. A value of 4.923VP is considered to be a reasonable minimum in
order to allow peak collector voltage changes of ±VP .
EXAMPLE 8.2.1
Consider and obtain the values for RS , R2 , R1 , and RD . Apply the rule-of-thumb dc design
procedure outlined in this section for a JFET with VP = 3 V, IDSS = 20 mA, and a source
voltage VDD = 24 V.
Solution
Applying Equations (8.2.8) through (8.2.10),

5.768VP 5.768(3)
RS = = = 865.2 -
IDSS 20 × 10−3
R2 = 100RS = 86, 520 -

VDD 24
R1 = 100RS − 1 = 86,520 − 1 = 374,920 -
1.5VP 1.5 × 3
3(VDD − 2.923VP ) 3[24 − 2.923(3)]
RD = = = 1142.3 -
2IDSS 2 × 20 × 10−3
Note that VDD = 24 V is greater than 4.923VP = 14.77 V; the device is biased above the
reasonable minimum.
The dc design procedure may have to be adjusted after the ac design in some cases because
of signal values, and refined further to suit the available components and power-supply voltages.
In any case, one should ensure that any transistor maximum rating is not exceeded.
Biasing Depletion MOSFETs

Recognizing that vGS can exceed zero in a MOSFET and hence the operating point may be placed
at a higher IDQ than in a JFET circuit, the same procedure as that outlined for dc biasing of JFETs
can be applied directly to the biasing of depletion-type MOSFETs.
Biasing Enhancement MOSFETs

A biasing method for an n-channel enhancement-type MOSFET is illustrated in Figure 8.2.2.
Since the gate draws no current, VG is given by
VDD R2
VG = (8.2.13)
R1 + R 2
Note that RS in Figure 8.2.2 is only to provide operating-point stability and not to establish a
quiescent point since its voltage drop is not of the correct polarity. Neglecting the effect of vDS on
iD, the drain current for the active mode is given by [see Equations (7.4.2) and (7.4.3)]
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
Figure 8.2.2 Biasing an n-channel enhancement

MOSFET.
R1 RD
D +
VG G VDD
−
S
RS
R2
iD = K(vGS − VT )2 (8.2.14)
in which VT and K are specified based on the transfer characteristic [Figure 7.4.8(a)] in the
manufacturer’s data sheets.
The load-line equation is
VG − vGS
iD = (8.2.15)
RS
The required gate–source voltage VGSQ at the operating point is then
&
IDQ
VGSQ = VT + (8.2.16)
K
VDSQ can then be selected to yield a desired operating point on the ID–VDS static characteristics of
the device. It follows then
VDD − VDSQ
RS + RD = (8.2.17)
IDQ
By trading off ac gain (larger RD) versus dc stability (larger RS ), RD and RS need to be chosen.
Once RS is chosen, then VG is set by
VG = VGSQ + IDQ RS (8.2.18)
Finally, R1 and R2 can be selected arbitrarily to yield VG while keeping both large enough to
maintain a large gate impedance. The outlined approach is best illustrated by an example.
EXAMPLE 8.2.2
Given an n-channel enhancement MOSFET having VT = 4 V, K = 0.15 A/V2, IDQ = 0.5 A,
VDSQ = 10 V, and VDD = 20 V. Using the dc design approach outlined in this section, determine
VGSQ, VG, RD, RS, R1, and R2.
Solution
Applying Equation (8.2.16),

& &
IDQ 0.5
VGSQ = VT + =4+ = 5.826 V
K 0.15
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
8.3 BJT AMPLIFIERS 399
Noting the supply voltage to be 20 V and the drop across the transistor 10 V, about 10 V can be
allowed for ac swing across RD. Allowing some drop of, say, 3 V across RS for dc stability,
7
RD = = 14 -
0.5
4
RS = =8-
0.5
VG = VGSQ + IDQ RS = 5.826 + 4 = 9.826 V
Selecting arbitrarily R2 = 10,000 - to maintain a large gate impedance,
R2 (VDD − VG ) 104 (20 − 9.826)
R1 = = = 10.354 k-
VG 9.826
One should also check to ensure that the voltage, current, and power ratings of the device are not
exceeded.
Biasing methods using resistors have been presented for the sake of simplicity and ease of
understanding. However, nowadays biasing techniques for modern amplifiers utilize transistors.
8.3 BJT AMPLIFIERS

The purpose of electronic amplifiers is essentially to increase the amplitude and power of a signal
so that either useful work is done or information processing is realized. The output signal power
being greater than the input signal power, the additional power is supplied by the bias supply.
Thus, the amplifier action is one of energy conversion in which the bias power is converted to
signal power within the device.
A single-stage amplifier is one in which there is only one amplifying element. By combining
several single-stage amplifier circuits, a multistage amplifier is produced. Audio amplifiers are
designed to amplify signals in the frequency range of 30 to 15,000 Hz perceptible to the human
ear. A video amplifier is designed to amplify the signal frequencies needed for television imaging
(see Chapter 15). An amplifier, in general, is then made up of a cascade of several stages. A stage
usually consists of an elementary amplifier, which normally has only one transistor. The cascade
is formed by making the output of the first stage as the input of the second stage, the output of
the second stage as the input of the third stage, and so on. This section is devoted to the study of
three basic forms of amplifier stages which use a BJT.
Common-Emitter (CE) Configuration

The emitter part of a circuit being common to both the input and the output portions, Figure
8.3.1(a) illustrates a common-emitter (CE) BJT amplifier. The resistors R1, R2, RC, and RE are
primarily set by biasing. The input ac source is represented by its Thévenin equivalent. The
amplified output ac voltage vL appears across the load resistor RL , which could represent the
input resistance of the next stage in a cascade. Capacitors CB, CC, and CE are so chosen that they
represent short circuits at the lowest frequency of interest. CE would be made large enough so
that 1/ωCE is small relative to RE in parallel with the impedance looking into the emitter at the
smallest ω of interest. Similarly, the reactances of CC and CB would be chosen small relative to
the resistances in their parts of the circuit. Capacitors CB and CC appear as short circuits to the ac
signals, but block the dc voltages and currents out of one part of the circuit from coupling with
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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RC
R1 CC
iL
CB C
iS v1 +
npn BJT
B VCC
RS −
E Amplified
output +
+ ac voltage VL RL
vS − Load
R2
− resistor
CE
RE Bypass
capacitor
AC source Rin Ri Ground
(a)
RS iS iL = AiiS
B v1 = vπ C
+ gmvπ
+ vπ rπ ro
+
vS RB=R1||R2 − RC RL vL = Av1 v1
− −
Rin=RB||Ri Ri = rπ Ground
(b)
Figure 8.3.1 Common-emitter (CE) BJT amplifier. (a) Circuit. (b) Small-signal ac equivalent circuit.
another part. Capacitor CE, known as the bypass capacitor, bypasses the ac current around RE so
that no significant ac voltage is generated across RE, and helps to increase the gain.
The small-signal ac equivalent circuit is shown in Figure 8.3.1(b), in which the small-
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
signal model of Figure 7.3.7 for the transistor is used. While omitting the details of analysis
and summarizing the results, we have
+ R 1 R2
RB = R1 +R2 = (8.3.1)
R1 + R 2
 
resistance between
Ri =  transistor base and ground  = rπ (8.3.2)
(as seen looking into base)
vS Rin
v1 = vπ = (8.3.3)
RS + Rin
Copyright OUP
where

total input resistance + RB rπ
Rin = = RB +Ri = (8.3.4)
seen by source RB + r π
Voltage and current gains are given by
vL −gm RL [ro RC ]

Av1 = = (8.3.5)
v1 RL + [ro RC ]
iL −gm (ro RC )(rπ RB )
Ai = = (8.3.6)
iS RL + (ro RC )
The CE configuration yields signal inversion since the gains can be seen to be negative.
EXAMPLE 8.3.1
Consider the transistor biased in Example 8.1.1. Given that RL = 500 - and VA = 75 V for the
transistor, determine the ac voltage and current gains.
Solution
Taking VT = 25.861 × 10−3 V, as indicated in Section 7.3, and applying Equation (7.3.7),
ICQ 15 × 10−3
gm = = = 0.58 S
VT 25.861 × 10−3
By using Equation (7.3.8),
VA 75
ro = = = 5000 -
ICQ 15 × 10−3
Taking RC = 300 - from the solution of Example 8.1.1,
5000(300)
ro RC = 5000300 = = 283 -
5000 + 300
Applying Equation (8.3.5), one gets
−0.58(500)(283)
A v1 = = −104.8
(500 + 283)
β 70
rπ = = = 120.7 -
gm 0.58
and
1 1
Rin = R1 R2 rπ = = = 109.3 -
(1/R1 ) + (1/R2 ) + (1/rπ ) (1/5444) + (1/1467) + (1/120.7)
where values for R1 and R2 are taken from the solution of Example 8.1.1. From Equation (8.3.6),
−0.58(283)(109.3)
Ai = = −22.9
500 + 283
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
Common-Collector (CC) Configuration

A common-collector (CC) amplifier is also known as an emitter follower (or a voltage follower)
due to the fact that the output voltage “follows” the input by being approximately equal to the
input voltage. The amplifier is shown in Figure 8.3.2(a), in which the collector forms a common
terminal between the input and output circuits, and resistors R1, R2, and RE are determined by
biasing. Capacitors CB and CE are chosen large enough to appear as short circuits at the lowest
frequency of interest in the input signal vS. The output voltage vL is taken across the load resistor
RL . The small-signal ac equivalent circuit of the amplifier is shown in Figure 8.3.2(b), whose
analysis yields the following results:
R 1 R2
RB = R1 R2 = (8.3.7)
R1 + R 2
R1
RS CB C
v1 B +
npn BJT
VCC
iS E −
CE
+ IL
vS R2
−
+
Output
RE Load RL vL voltage
resistor −
AC source Rin Ri Ground

(a)
RS v1 B C
i
+ gmvπ
iS vπ rπ ro
−
+
vS
R1||R2=RB E
− iL
+
RE vL RL
−
RB||Ri=Rin Ri Ground
(b)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Figure 8.3.2 Common-collector (CC) BJT amplifier. (a) Circuit. (b) Small-signal ac equivalent circuit.
Copyright OUP
R B Ri
Rin = RB Ri = (8.3.8)
RB + R i
in which
Ri = rπ + RW (1 + gm rπ ) (8.3.9)
where
RW = ro RE RL (8.3.10)
The voltage and current gains are given by
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
vL RW (1 + gm rπ )
Av1 = = (8.3.11)
v1 rπ + RW (1 + gm rπ )
iL vL Rin Rin Rin RW (1 + gm rπ )
Ai = = = Av = (8.3.12)
iS v1 RL RL 1 RL [rπ + RW (1 + gm rπ )]
ro is generally large enough so that the following results hold. For ro → ∞,
Ri ∼= rπ + (1 + gm rπ )(RE RL ) (8.3.13)
(1 + gm rπ )(RE RL ) ∼
Av1 ∼= =1 (8.3.14)
rπ + (1 + gm rπ )(RE RL )
(1 + gm rπ )(RE RL )RB
Ai ∼= (8.3.15)
RL [rπ + RB + (1 + gm rπ )(RE RL )]
Note that the voltage gain of the CC amplifier is about unity, but never exceeds unity. The current
gain, on the other hand, is large since Rin >> RL typically.
Common-Base (CB) Configuration

The common-base (CB) amplifier is shown in Figure 8.3.3(a), in which the base forms the common
terminal between the input and output circuits, and resistors R1, R2, RC, and RE are selected through
biasing. Capacitors CB, CC, and CE are chosen large enough to act as short circuits at the lowest
frequency of interest in the input signal vS. The output voltage vL is taken from the collector across
resistor RL . The small-signal ac equivalent circuit of the amplifier is shown in Figure 8.3.3(b),
whose analysis yields the following results:
R C RL
RH = RC RL = (8.3.16)
RC + R L
rπ (ro + RH )
Ri = (8.3.17)
rπ + RH + ro (1 + gm rπ )
R E Ri (rπ RE )(ro + RH )
Rin = RE Ri = = (8.3.18)
RE + R i ro + RH + (rπ RE )(1 + gm ro )
The voltage and current gains are given by
vL vL RH (1 + gm ro )
Av1 = = = (8.3.19)
v1 −vπ RH + r o
Rin RH (rπ RE )(1 + gm ro )
Ai = Av 1 = (8.3.20)
RL RL [ro + RH + (rπ RE )(1 + gm ro )]
For ro → ∞,
Copyright OUP
RC
R1 CC
iL
C
B +
npn BJT
VCC
+ −
E Output
v RL
RS voltage L
−
v1
CB R2
CE iS
+
RE vS
AC
−
source
Ground
Rin
(a)
B C
IL
+ gmvπ
vπ rπ ro
−
+
E RC RL vL
Ri iS
v1= −vπ −
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
RS +
RE vS
−
Ground
Rm=REIIRi
(b)
Figure 8.3.3 Common-base (CB) BJT amplifier. (a) Circuit. (b) Small-signal ac equivalent circuit.
rπ
Ri ∼
= (8.3.21)
1 + gm rπ
(rπ RE )
Rin ∼
= (8.3.22)
1 + gm (rπ RE )
Av =∼ gm (RC RL ) (8.3.23)
1
gm (RC RL )(rπ RE )

Ai ∼= (8.3.24)
RL [1 + gm (rπ RE )]
Because of the low input resistance, the CB amplifier is often used as a current amplifier which
accepts an input current into its low impedance and provides an output current into a high
impedance. That is why a CB amplifier is sometimes referred to as a current follower.
Copyright OUP
8.4 FET AMPLIFIERS 405
On comparing the CE, CC, and CB configurations one can come up with the following
observations:
1. Ri and Rin are largest for the CC configuration, smallest for the CB, and in between those
extremes for the CE.
2. While there is a sign inversion in the voltage-gain expression with the CE amplifier, about
the same magnitude of gain (which can be greater than unity) results for the CE and CB
configurations. For the CC amplifier, however, the voltage gain cannot exceed unity.
3. Both CE and CB configurations can yield large current-gain magnitudes; the CB amplifier
has a current gain less than unity.
8.4 FET AMPLIFIERS

Just like the BJT amplifiers, FET amplifiers are constructed in common-source (CS, analogous
to CE), common-drain (CD, analogous to CC), and common-gate (CG, analogous to CB)
configuration. First we shall consider JFET amplifiers, then we show how the results are modified
with MOSFETs.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Common-Source (CS) JFET Amplifier
Figure 8.4.1(a) shows a CS JFET amplifier in which resistors R1, R2, RD, and RSS are selected
by the bias design, and capacitors CG, CD, and CS are chosen to be large enough that they act as
short circuits at the lowest frequency of interest in the input signal vS. Figure 8.4.1(b) gives its
small-signal equivalent circuit. Noting that the input impedance of a JFET is very large, we have
Ri ∼
=∞ (8.4.1)
R 1 R2
Rin = R1 R2 = (8.4.2)
R1 + R 2
RD
R1 CD
iL
D
RS CG n - Channel +
G JFET VDD
S + −
iS RL vL Output
voltage
−
+
vS R2
−
RSS CS
Input ac source
Rin Ri Ground
(a)
Figure 8.4.1 Common-source (CS) JFET amplifier. (a) Circuit. (b) Small-signal ac equivalent circuit.
Copyright OUP
RS v1 G D iL
+ gmvGS
iS vGS ro
+ − +
vS R1 R2 RD RL vL Output
− −
S
Input
Rin = R1||R2 Ri −∞ Ground
(b)
Further analysis yields

−gm ro RF
A v1 = (8.4.3)
ro + R F
−gm ro RF Rin Rin
Ai = = Av (8.4.4)
RL (ro + RF ) RL 1
where
R D RL
RF = RD RL = (8.4.5)
RD + R L
The CS JFET amplifier is capable of large voltage and current gains.
EXAMPLE 8.4.1
A JFET for which VA = 80 V, VP = 4 V, and IDSS = 10 mA has a quiescent drain current of 3
mA when used as a common-source amplifier for which RD = RSS = 1 k- and RL = 3 k-. For
the case of fully bypassed RSS , find the amplifier’s voltage gain Av1 . Also determine the current
gain Ai if R1 = 300 k- and R2 = 100 k-.
Solution
From Equations (7.4.5) and (7.4.4),

VA 80
ro = = = 26,666.7 -
IDQ 3 × 10−3
2 2
gm = IDSS IDQ = 10 × 10−3 × 3 × 10−3 = 2.7386 × 10−3 S
VP 4
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
1
RF = RD RL = = 750 -
(1/1000) + (1/3000)
−gm ro RF −2.7386(10−3 )(26,666.7)750 ∼
A v1 = = = −2
ro + R F 26,666.7 + 750
Copyright OUP
8.4 FET AMPLIFIERS 407
300(100)
Rin = R1 R2 = = 75 k-
400
Rin 75
Ai = Av = (−2) = −50
RL 1 3
Common-Drain (CD) JFET Amplifier

Figure 8.4.2(a) shows a CD JFET amplifier in which resistors R1, R2, and RSS are selected by the
bias design, and capacitors CG and CS are chosen to be large enough to act as short circuits at
frequencies in the band of interest (known as the midband). Figure 8.4.2(b) gives its small-signal
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
ac equivalent circuit. Analysis of this circuit yields

Ri ∼
=∞ (8.4.6)
R 1 R2
Rin = R1 R2 = (8.4.7)
R1 + R 2
vL gm ro (RSS RL )
Av1 = = (8.4.8)
v1 ro + (RSS RL )(1 + gm ro )
iL gm ro (RSS RL )(R1 R2 )
Ai = = (8.4.9)
iS RL [ro + (RSS RL )(1 + gm ro )]
In many cases Av1 ∼= 1 and vL = v1 ; that is to say the load voltage “follows” the input. Hence a
CD amplifier is often known as a source follower, which becomes an excellent buffer to couple a
high-resistance source to a low-resistance load with nearly no loss in signal voltage. The current
gain, however, can be very large, leading to significant power gain.
Common-Gate (CG) JFET Amplifier

Figure 8.4.3(a) shows a CG JFET amplifier in which resistors R1, R2, RD, and RSS are selected by
the bias design, and capacitors CD and CS are chosen to be large enough to act as short circuits at
+
VDD
R1 D −
RS n-Channel
CG G JFET
S
+ CS
vS R2
− +
RSS RL vL Output
voltage
−
Input ac source
Rin Ri Ground
(a)
Figure 8.4.2 Common-drain (CD) JFET amplifier. (a) Circuit. (b) Small-signal ac equivalent circuit.
Copyright OUP
RS
G D
+ gmVGS
vGS ro
−
+
vS R1 R2 S
−
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
+
RSS RL vL Output
−
Input
Rin = R1||R2 Ri − ∞ Ground
(b)
the lowest frequency of interest in the input signal vS. Figure 8.4.3(b) shows its small-signal ac
equivalent circuit, whose analysis yields the following results:
RSS (ro + RF )
Rin = (8.4.10)
ro + RF + RSS (1 + gm ro )
where
R D RL
RF = RD RL = (8.4.11)
RD + R L
vL RF (1 + gm ro )
Av1 = = (8.4.12)
v1 ro + R F
iL RF (1 + gm ro )RSS
Ai = = (8.4.13)
is RL [ro + RF + RSS (1 + gm ro )]
With practical values, quite often ro is rather large and gm RSS >> 1 so that Rin = ∼ 1/gm and
∼ RF /RL = RD /(RD + RL ), which turns out to be less than unity.
Ai =
+
VDD
RD
R1 CG −
iL
D
n-Channel +
CG
G JFET RL vL Output
S iS − voltage
v1
CS RS +
R2 Ri
RSS vS
−
AC Input source
Ground
Rin
Figure 8.4.3 Common-gate (CG) JFET amplifier. (a) Circuit. (b) Small-signal ac equivalent circuit.
Copyright OUP
8.5 FREQUENCY RESPONSE OF AMPLIFIERS 409
G D iL
+ +
vGS gmvGS ro RD RL vL Output
− −
S RS
v1
iS +
RSS vS
−
Input
(b)
On comparing the CS, CD, and CG configurations one can make the following observations:
1. For CS and CD configurations Rin = R1 R2 , which can be selected to be large during
the bias design. For the CG configuration, however, Rin is not very large, on the order of
a few hundred ohms.
2. For the CD configuration the voltage gain is generally less than unity or near unity, while
it can exceed unity in the other configurations. The voltage gain of the CG configuration
is slightly larger than that of the CS configuration.
3. For the CG configuration the current gain cannot be larger than unity. But for the CS and
CD configurations it can be large by the choice of Rin.
MOSFET Amplifiers
Because the same small-signal equivalent circuits apply to both the JFET and the MOSFETs, all
the equations developed for the JFET amplifiers hold good for the MOSFET amplifiers, so long
as gm and ro are computed properly. For the depletion MOSFET the equations for gm and ro, given
by Equations (7.4.4) and (7.4.5), are the same as for the JFET. For the enhancement MOSFET,
they are given by Equations (7.4.9) and (7.4.10).
8.5 FREQUENCY RESPONSE OF AMPLIFIERS

All amplifiers exhibit variations of performance as the signal frequency is changed. The frequency
response of an amplifier may be defined as the functional dependence of output amplitude and
phase upon frequency, for all frequencies. Invariably there is a maximum frequency above which
amplification does not occur. Depending on the design of the circuit, there may also be a lower
frequency limit below which amplification disappears. The range of frequencies over which
significant amplification of the magnitude is obtained is known as the passband, which is bounded
by the upper cutoff frequency and the lower cutoff frequency (if one exists). Dc-coupled amplifiers,
in which the stages are coupled together for all frequencies down to zero, have no low-frequency
limit. On the other hand, circuits containing coupling capacitors that couple stages together for
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
Magnitude of gain
Magnitude Av0
Phase angle
of gain
Midband
Av0
2
0
Phase
0 ωL ωH ω
Deterioration Deterioration
due to W3dB due to capacitances
coupling capacitors Bandwidth (passband) internal to the
and bypass transistor
capacitor
Figure 8.5.1 Typical frequency response of a voltage amplifier.
ac while isolating them for dc are limited in their low-frequency response. The high-frequency
deterioration of the voltage gain is due to the effect of capacitances that are internal to the transistor.
Figure 8.5.1 shows a typical frequency response of a voltage amplifier. While most often the
magnitude of the gain is discussed (because it defines the frequency range of useful gain), the
phase response becomes important for transient calculations. The midband region is the range of
frequencies where gain is nearly constant. Amplifiers are normally considered to operate in this
useful midband region. The bandwidth of an amplifier is customarily defined as the band between
two frequencies, denoted by ωH and ωL , which corresponds to the gain falling to 3 dB below the
midband constant gain. Thus,
W3dB = ωH − ωL (8.5.1)
which is shown in Figure 8.5.1. When both ωL and ωH have significant values, the amplifier
is known as a bandpass amplifier. A narrow-bandpass amplifier is one in which W 3dB is small
relative to the center frequency of the midband region. In a low-pass unit (dc amplifier) there is
no low 3-dB frequency.
The general problems of analyzing any given amplifier to determine ωL or ωH , and of
designing amplifiers with specific values of ωL and ωH , are extremely complex and well beyond
the scope of this text. Specific amplifier cases can, however, be considered in order to gain a sense
of what is involved in determining the frequency response. Toward that end let us consider the CS
JFET amplifier shown in Figure 8.4.1(a). The small-signal ac equivalent circuit for low frequencies
near ωL is depicted in Figure 8.5.2(a), that for high frequencies near ωH in Figure 8.5.2(b).
Assuming ro to be large for convenience, the gain of the low-frequency circuit of Figure
8.5.2(a) can be found to be
vL Av0 (j ω)2 (ωZ + j ω)
Av = = (8.5.2)
vs (ωL1 + j ω)(ωL2 + j ω)(ωL3 + j ω)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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RS CG CD
G D
+ gm vGS
vGS ro
+ − +
vS R1 R2 RD RL vL Output
− voltage
S −
RSS Cs
Input ac
source
(a)
RS Cgd
+ + gmvGS +
vS R1 R2 Cgs vGS ro Cds RD RL vL Output
− voltage
− −
Input ac
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
source
(b)
Figure 8.5.2 Small-signal equivalent circuits for CS JFET amplifier. (a) For low frequencies near ωL (including
coupling capacitors and bypass capacitor). (b) For high frequencies near ωH (including parasitic capacitances
of transistor).
where
−gm RG RD RL
A v0 = (8.5.3)
(RS + RG )(RD + RL )
R1 R 2
RG = R1 R2 = (8.5.4)
R1 + R 2
1
ωZ = (8.5.5)
RSS CS
1
ωL1 = (8.5.6)
RL 1 CS
1
ωL2 = (8.5.7)
RL 2 CD
1
ωL3 = (8.5.8)
RL 3 CG
RSS
RL1 = (8.5.9)
1 + gm RSS
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RL2 = RD + RL (8.5.10)
RL3 = RS + RG (8.5.11)
The frequencies ωZ , ωL1 , ωL2 , and ωL3 are known as break frequencies, at which the behavior of
|Av | changes. For ω above all break frequencies Av ∼ = Av0 , which is the midband value of the
gain. The largest break frequency is taken to be ωL , the low 3-dB frequency.
The amplifier gain at higher frequencies near ωH is found from the analysis of Figure 8.5.2(b).
Neglecting the second-order term in ω2 in the denominator, the gain can be found to be
vL ∼ Av0 ωH (ωZ − j ω)
Av = = (8.5.12)
vs ωZ (ωH + j ω)
where
−gm RG RDL
A v0 = (8.5.13)
RS + R G
r o RD RL
RDL = ro RD RL = (8.5.14)
ro R D + r o R L + R D R L
R1 R 2
RG = R1 R2 = (8.5.15)
R1 + R 2
gm
ωZ = (8.5.16)
Cgd
1
ωH = (8.5.17)
RA [Cgs + Cgd (1 + gm RDL + RDL /RA )]
R S RG
RA = RS RG = (8.5.18)
RS + R G
An illustrative example of both low- and high-frequency designs is worked out next.
EXAMPLE 8.5.1
Consider a CS JFET amplifier with the following parameters: R1 = 350 k-; R2 = 100 k-, RSS =
1200 -, RD = 900 -, RL = 1000 -, RS = 2000 -, ro = 15 k-, gm = 6 × 10−3 S, Cgs = 3
pF, Cgd = 1 pF, and ωL = 2π × 100 rad/s. Discuss the low- and high-frequency designs.
Solution
For the low-frequency design,
R 1 R2 350(100)
RG = R1 R2 = = = 77.78 k-
R1 + R 2 450
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
RSS 1200 1200

RL1 = = = = 146.34 -
1 + gm RSS 1 + (6 × 10−3 × 1200) 8.2
RL2 = RD + RL = 900 + 1000 = 1900 -
RL3 = RS + RG = 2000 + 77,780 = 79,780 -
Noting that RL1 is the smallest, from Equation (8.5.6),
1 1
CS = = = 10.87 µF
RL 1 ωL 146.34(2π × 100)
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From Equations (8.5.7) and (8.5.8),

1 1 10
CD = = = = 8.37 µF
RL 2 ωL 2 RL2 ωL /10 1900(200π )
where ωL2 is chosen to be ωL /10 so that the break frequency of the capacitor is at least 10 times
smaller than ωL .
1 1 10
CG = = = = 0.2 µF
RL 3 ωL 3 RL3 ωL /10 79,780(200π )
where ωL3 is chosen to be ωL /10 so that the break frequency of the capacitor is at least 10 times
smaller than ωL .
In order to determine ωH , we first find
2000(77,780)
RA = RS RG = = 1969.9 -
79,780
900(1000)
RD RL = = 473.68 -
1900
15,000(473.68)
RDL = ro RD RL = = 459.2 -
15,473.68
1012
ωH = = 73.26 × 106 rad/s
1950[3 + 1 + (6 × 10−3 )(459.2) + 459.2/1950]
or
ωH
= 11.655 MHz
2π
Midband gain from Equation (8.5.3) is
−(6 × 10−3 )(77,780)(900)(1000)
A v0 = = −2.77
(2000 + 77,780)(900 + 1000)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Amplifiers with Feedback
Almost all practical amplifier circuits include some form of negative feedback. The advantages
gained with feedback may include the following:
• Less sensitivity to transistor parameter variations.
• Improved linearity of the output signal by reducing the effect of nonlinear distortion.
• Better low- and high-frequency response.
• Reduction of input or output loading effects.
The gain is willingly sacrificed in exchange for the benefits of negative feedback. Compen-
sating networks are often employed to ensure stability. A voltage amplifier with negative feedback
is shown by the generalized block diagram in Figure 8.5.3. The negative feedback creates a self-
correcting amplification system that compensates for the shortcomings of the amplifying unit.
The gain with feedback can be seen to be
vout A
Af = = (8.5.19)
vin 1 + AB
Also noting that vd = vout /A, it follows
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Transistor
amplifying unit with
vin + vd gain A
A vout = Avd = A(vin−vf)
= vin − vf
− = A(vin−Bvout)
= Bvout
vf
B vout
= (AB)vd
Feedback
with feedback factor B
Figure 8.5.3 Voltage amplifier with negative feedback.
vd 1
= (8.5.20)
vin 1 + AB
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
The product AB is known as the loop gain because vf = B(Avd ) = (AB)vd . In order to obtain
negative feedback, the loop gain must be positive. With AB > 0 in Equation (8.5.19) it follows
that |Af | < |A|. Thus, a negative feedback amplifier has always less gain than the amplifying unit
itself. With AB >> 1, Af remains essentially constant, thereby reducing the effect of transistor
parameter variations in the amplifying unit. If the feedback unit has |B| < 1, one can still obtain
useful amplification since |Af | ∼ = 1/|B| > 1.
The amplifiers discussed in Sections 8.3 and 8.4 as well as in this section are small-signal
linear stages that use capacitance coupling. These are also known as RC amplifiers since their
circuits need only resistors and capacitors. There are of course other transistor amplifiers that do
not have the small-signal limitation and are also not limited to the use of resistors and capacitors
in their circuits. For larger input signals the linear dependence of the current on the signal level
may not be maintained.

• Biasing the BJTs and FETs.
• BJT and FET amplifier configurations, and their small-signal equivalent circuits, based on
which voltage and current gains are computed.
• Frequency response of amplifiers, and low- and high-frequency designs.
• Advantages of negative feedback in amplifier circuits.
Mechatronics: Electronics Integrated with Mechanical Systems

Electronic circuits have become so intimately integrated with mechanical systems that a new term,
mechatronics, has been coined for the combination. Various subjects related to mechatronics are
being developed at a number of universities in the United States, supported by major industrial
sponsors. Too many engineers, at present, are not well equipped and trained to design mechatronic
Copyright OUP
PROBLEMS 415
products. Interdisciplinary experts who can blend many different technologies harmoniously are
rather rare.
Let us think for a moment about various electronic and electric systems in an automobile of
today. Only a few of those are listed here:
• Body electronics: Airbags, security and keyless entry, memory seats and mirrors
• Vehicle control: Antilock brakes, traction control, electronic navigation, adaptable suspen-
sion systems
• Power train: Engine and transmission, cruise control, electronic ignition, four-wheel drive
• Instrumentation: Analog/digital dash, computerized performance evaluation and mainte-
nance scheduling, tire inflation sensors
• Communications and entertainment: cellular phone, AM/FM radio, CD/tape player, digital
radio
• Alternative propulsion systems such as electric vehicles, advanced batteries, and hybrid
vehicles are being developed. Fiber-optics in communications and electrooptics, replacing
the conventional wire harness, are already in practice.
In recent years, the conventional electric ignition system has been replaced by electronic
ignition. Mechanically operated switches, or the so-called points, have been replaced by bipolar
junction transistors (BJTs). The advantages of transistorized ignition systems over the conven-
tional mechanical ones are their greater reliability, durability, and ease of control. The transistor
cycles between saturation (state in which it behaves as a closed switch) and cutoff (state in
which it behaves as an open switch). The ignition spark is produced as a result of rapidly
switching off current through the coil. Modern engine control systems employ electric sensors
to determine operating conditions, electronic circuits to process the sensor signals, and special-
purpose computers to compute the optimum ignition timing.
Automotive electronics has made tremendous advances, and still continues to be one of
the most dominating topics of interest to automotive engineers. Certainly, today’s mechanical
engineers have to be familiar with electronic circuit capabilities and limitations while they try to
integrate them with mechanical design and material science.
PROBLEMS
8.1.1 A silicon npn BJT is biased by the method shown sponds to ICQ = 14 mA, VCEQ = 7 V, when
in Figure 8.1.1, with RE = 240 -, R2 = 3000 -, VCC = 12 V and the silicon BJT has a nominal
and VCC = 24 V. The operating point corresponds β = 70. Also determine RC.
to VBEQ = 0.8 V, IBQ = 110 µA, VCEQ = 14 V, *8.1.4 Consider the collector–base biasing method
and ICQ = 11 mA. Determine RC and R1. shown in Figure P8.1.4. With the same data as
8.1.2 By using the rule-of-thumb procedure indicated in Problem 8.1.3, find RB and RC.
in the text, find values of all resistors in the bias
8.1.5 A BJT is biased by the method shown in Figure
method of Figure 8.1.1 with VCC = 10 V for
P8.1.5. If VBEQ = 0.7 V, β = 100, VCEQ = 10
a silicon npn BJT for which β = 100 and the
V, and ICQ = 5 mA, find I 1, I 2, and IEQ.
operating point is given by ICQ = 5 mA.
8.1.3 A fixed-bias method is illustrated in Figure P8.1.3. 8.2.1 For the method of biasing a JFET shown in Figure
Assuming ICBO to be small compared to IBQ and 8.2.1 of the text, use the design procedure outlined
ICQ, find RB such that the operating point corre- there to find VG, RS, RD, R2, and R1, given that
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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RC
RB RC RB
+
+
VCC
VCC
−
−
30,000 Ω I1 1500 Ω
+
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
VCC = 24 V
−
9000 Ω I2 750 Ω
Figure P8.1.5
VDD = 24 V and for the JFET VP = 3.5 V and 8.2.5 Given that an n-channel enhancement MOSFET
IDSS = 5 mA. has VT = 1.5 V, K = 5 mA/V2, IDQ = 10
8.2.2 An n-channel JFET having VP = 3.5 V and mA, VDSQ = 15 V, and a maximum continuous
IDSS = 5 mA is biased by the circuit of Figure power dissipation of 0.3 W. For the biasing circuit
8.2.1 with VDD = 28 V, RS = 3000 -, and of Figure 8.2.2 with VDD = 24 V, R2 = 1 M-,
R2 = 100 k-. If the operating point is given by and the voltage across RS = 3 V, find RS, RD, VG,
IDQ = 2 mA and VDSQ = 12 V, determine VG, and R1. Also find the continuous power dissipated
RD, and R1. in the MOSFET.
*8.2.3 A self-biasing method for the JFET is shown in *8.3.1 By analyzing the small-signal ac equivalent circuit
Figure P8.2.3. The JFET has VP = 3 V and of the CE BJT amplifier shown in Figure 8.3.1(b),
IDSS = 24 mA. It is to operate at an active- show that Equation (8.3.6) is true.
region Q point that is given by IDQ = 5 mA and
VDSQ = 8 V. Determine RS and RD so that the 8.3.2 The input resistance of a CE amplifier can be
desired Q point is achieved with VDD = 16 V. increased at the expense of reduced voltage and
8.2.4 An n-channel depletion MOSFET that has VP = 3 current gains by leaving a portion of the emitter
V and IDSS = 3 mA (when VDS = 10 V) is biased resistance unbypassed. Consider the CE amplifier
by the circuit of Figure 8.2.1 with VDD = 20 V shown in Figure P8.3.2 having an unbypassed
and R2 = 1M-. If the operating point is given emitter resistance RE1 . Assuming for simplicity
by IDQ = 3 mA and VDSQ = 10 V, and 40% of that ro → ∞, draw the ac equivalent circuit
the voltage drop across RD and RS is across RS , for small signals and discuss the effects on input
determine RS, RD, VG, and R1. resistance and voltage and current gains.
Copyright OUP
PROBLEMS 417
Figure P8.2.3
RD
+
VDD
−
RG RS
RC
R1 CC
RS CB C
iL
v1 B +
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
VCC
iS E −
+
RE1 vL RL
+
−
vS
− R2
RE2 CE
Ground
Figure P8.3.2 CE amplifier having an unbypassed emitter resistance RE1 .
8.3.3 Consider the CE BJT amplifier of Figure 8.3.1(a) 8.3.7 Let 200 - of RE be not bypassed in Problem 8.3.6.
with R1 = 1600 -, R2 = 400 -, RC = 70 -, How would the gains be altered?
RE = 20 -, and RL = 150 -. The transistor has 8.3.8 Determine voltage and current gains for the CE
β = 70, VA = 50 V, and ICQ = 80 mA when BJT amplifier shown in Figure 8.3.1(a) with the
VCC = 15 V. Compute the amplifier’s voltage and following parameters: R1 = 30,000 -, R2 =
current gains. Take VT to be 25.861 mV. 9000 -, RC = 750 -, RE = 250 -, RL =
8.3.4 Let the bypass capacitor CE be removed in Prob- 1000 -, VCC = 9 V; and ICQ = 5 mA when
lem 8.3.3. How would the gains be altered? β = 150 and VA = 50 V.
8.3.5 Let half of RE be unbypassed in Problem 8.3.3. 8.3.9 Assuming that the bypass capacitor CE is removed
How would the gains be altered? in Problem 8.3.8, find the voltage and current
*8.3.6 The CE BJT amplifier of Figure 8.3.1(a) has the gains.
following parameters: R1 = 28,000 -, R2 = *8.3.10 Find an expression for the power gain AP for a
8000 -, RC = 1400 -, RE = 700 -, RL = common-collector stage if the power gain of an
2000 -, VCC = 24 V, and ICQ = 5 mA when amplifier stage is defined as the ratio of the load
β = 100 and VA = 100 V. Calculate the voltage power vLiL to the power delivered by the source
and current gains of the amplifier. v1is. (See Figure 8.3.1 for notation.)
Copyright OUP
8.3.11 Starting from Equations (8.3.9), (8.3.11), and together, and capacitor CE is disconnected from
(8.3.12), show that equations (8.3.13) through ground and used to couple a signal from a source
(8.3.15) hold for ro → ∞. to the emitter. Determine Ri, Rin, Av1 , and Ai.
8.3.12 Consider the CC BJT amplifier circuit shown in 8.4.1 For the CS JFET amplifier circuit of Figure
Figure 8.3.2(a) with R1 = 150 k-, R2 = 150 k-, 8.4.1(a), RD = 2 k- and RL = 3 k-. The JFET
RE = 2 k-, RL = 3 k-, and VCC = 10 V. The with ro = 15 k- has a voltage gain Av1 = −4.5
BJT has β = 100, ICQ = 1.2 mA, and VA = 75 when the entire source resistance is bypassed. Find
V. Determine Ri, Rin, Av1 , and Ai. gm.
8.3.13 Develop a formula for the power gain AP for a 8.4.2 Considering the CS JFET amplifier circuit of Fig-
common-collector stage if the power gain of an ure 8.4.1(a), a portion of the source resistance
amplifier stage is defined as the ratio of the load RSS in the JFET CS stage is sometimes left unby-
power vLiL to the power delivered by the stage v1is. passed. Let RSS = RSS1 + RSS2 in which RSS1 is
(See Figure 8.3.2 for notation.) that portion of RSS that is not bypassed and RSS2 is
8.3.14 In the CC amplifier stage of Figure 8.3.2(a), let R1 that part of RSS that is bypassed. Find expressions
= 32 k-, R2 = 22 k-, RE = 400 -, RL = 250 -, for the amplifier voltage gain Av1 and the current
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
and VCC = 9 V. Given that VA = 70 V, β = 50, and gain Ai. Comment on the results, particularly with
ICQ = 4 mA for the BJT, find Ri, Rin, Av1 , and Ai. reference to Equations (8.4.3) and (8.4.4).
8.4.3 The common-source amplifier of Figure 8.4.1(a)
*8.3.15 Obtain an expression for the power gain AP for
with RL = 300 -, RD = 150 -, and RSS =
a common-base stage if the power gain of an
100 - (fully bypassed) has a JFET with VA = 80
amplifier stage is defined as the ratio of the load
V, ro = 2 k-, and VP = 4 V.
power vLiL to the power delivered by the source
v1is. (See Figure 8.3.3 for notation.) (a) Compute gm and IDSS if the voltage gain is
8.3.16 Show that Equation (8.3.17) holds for the circuit
−2.8.
of Figure 8.3.3(b). (b) If the voltage gain is to be reduced to −1.4
8.3.17 Consider the CB BJT amplifier circuit shown in by leaving part of RSS unbypassed, find RSS1 ,
Figure 8.3.3(a), with RC = 1 k-, RL = 6 k-, which is that portion of RSS that is not by-
and Rin = 20 -. The transistor parameters are passed.
given by β = 60, VA = 70 V, and gm = 0.03 S. *8.4.4 Consider Figure 8.4.1 (a) of a CS JFET ampli-
Find Ri, RE, Av1 , and Ai. fier with R1 = 330 k-, R2 = 110 k-, RD =
8.3.18 Consider the CE BJT amplifier circuit shown in 1 k-, RSS = 1 k-, RL = 1 k-, IDQ = 6 mA,
Figure P8.3.18. In order to make it into a common- VA = 90 V, VP = 4 V, and IDSS = 20 mA.
base amplifier, terminals a and b are connected Compute Rin, Av1 , and Ai.
ICQ = 5 mA
30,000 Ω 750 Ω
CC
CB C
B β = 150 +
a
vA = 50 V 9V
+ −
E 1000 Ω vL
−
Input 9000 Ω
250 Ω CE
Figure P8.3.18
Copyright OUP
PROBLEMS 419
8.4.5 For the CD JFET amplifier of Figure 8.4.2(a), (b) Let a negative feedback loop be added such
show that Equations (8.4.8) and (8.4.9) can be that vd = vin − Bvout . For values of B = 0.03
rearranged as follows: and 0.08, investigate how the negative feed-
gm (ro RSS RL ) back reduces nonlinear distortion, but reduces
Av1 = gain.
1 + gm (ro RSS RL )
gm (ro RSS RL )(R1 R2 ) *8.5.5 (a) Consider the voltage amplifier with negative
Ai = feedback shown in Figure 8.5.3. For A =
RL [1 + gm (ro RSS RL )]
−100, find the feedback factor B in order to
8.4.6 In the source-follower circuit of Figure 8.4.2(a) get Af = −20.
the voltage gain is to be 0.7 when RSS = 300 - (b) With the value of B found in part (a), deter-
and a JFET with ro = 5 k- and gm = 0.025 S is mine the resulting range of Af if the transistor
used. Find the required load resistance. parameter variations cause A to vary between
8.4.7 Obtain an expression for the output resistance seen −50 and −200.
by the load when looking back into the ampli- 8.5.6 (a) Consider a BJT in the common-emitter con-
fier between source and ground for the CD JFET figuration. The equations that describe the be-
source-follower circuit of Figure 8.4.2(a). havior of the transistor in terms of the hybrid
8.4.8 If the circuit of Example 8.4.1 is converted to a h parameters are given by
CG amplifier having the same component values,
vB = hie iB + hre vC
compute the amplifier voltage gain Av1 , current
gain Ai, and Rin. iC = hf e iB + hoe vC
*8.4.9 Obtain an expression for Ri for the CG JFET am- Develop the h-parameter equivalent circuit of
plifier circuit of Figure 8.4.3(a). the transistor in the common-emitter mode.
8.4.10 Consider the CG JFET amplifier circuit of Figure (b) Setting hre and hoe equal to zero, obtain the h-
8.4.3(a) with RL = 15k-, RD = 7.5 k-, RSS = parameter approximate equivalent circuit of
5 k-, ro = 100 k-, and gm = 5 × 10−3 S. the common-emitter transistor.
Evaluate Av1 , Ai, and Rin.
(c) Figure P8.5.6(a) shows the small-signal
8.5.1 If the voltage gain of an amplifier is given by
equivalent circuit of a transistor amplifier in
20j ω the common-emitter mode. Find expressions
Av =
(120π + j ω)[1 + j ω/(5π × 10−4 )] for gains AI1 = IL /IB , AI2 = IL /IS , AV1 =
find ωH , ωL , and the midband gain. VC /VB , and AV2 = VC /VS .
8.5.2 Consider a CS JFET amplifier (Figure 8.5.2) with (d) Now consider the single-stage transistor am-
R1 = 520 k-, R2 = 140 -, RD = 1 k-, and plifier shown in Figure P8.5.6(b). The pa-
RSS = 1.4 k-. The FET parameters are gm = rameters of the 2N104 transistor are hie =
5 mS, ro = 20k-, and Cgs = Cgd = 2 pF. 1.67 k-, hf e = 44, and 1/ hoe = 150 k-.
The source resistance RS is 500 - and the load Evaluate the performance of the amplifier by
resistance RL is 2 k-. For the low-frequency 3- computing current gain, voltage gain, power
dB angular frequency to be 40π rad/s, compute gain, input resistance as seen by the signal
CS, CD, CG, Av0 , and ωH . source, and output resistance appearing at the
output terminals.
8.5.3 Determine RL, Cgs, and Av0 of a CS JFET amplifier
(Figure 8.5.2), given that RS = 1 k- which can be (e) Next consider the two-stage transistor am-
considered to be much less than (R1 R2 ), RL = plifier depicted in Figure P8.5.6(c). Develop
RD , ωL << ωH , ω3dB = 25 × 106 rad/s, and the h-parameter equivalent circuit of the two-
ωZ /ωH = 75. The transistor parameters are gm = stage amplifier and evaluate its performance.
5 mS, ro >> (RD RL ), and Cgs = Cgd . (f) Then consider the linear model of the
8.5.4 (a) Let the nonlinear input–output relationship of common-emitter BJT amplifier shown in Fig-
a transistor amplifying unit be given by vout = ure P8.5.6(d) that is applicable to the midband
50(vd + 3vd2 ). Plot the transfer characteristic frequency range. Find an expression for the
and check for what range of vd the undistorted current gain AI m = I2 /IS that remains in-
output results. variant with frequency. (Note the subscript m
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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denotes a reference to the midband frequency RC-coupled amplifier is shown in Figure

range.) P8.5.6(f). Analyze the circuit (by representing
in terms of isolated input and output sections)
(g) The linear model of a common-emitter BJT
to find AI h = I2 /IS in terms of AIm and
amplifier shown in Figure P8.5.6(e) is appli-
ωh , where ωh corresponds to 0.707AIm on the
cable at low frequencies. Obtain an expression
frequency response curve, and denotes high-
for the current gain AI l = I2 /IS in terms of
band frequencies.
AIm and ωl , where ωl corresponds to 0.707AIm
on the frequency response curve, and ωl iden- (i) Sketch the frequency response curve of an RC-
tifies the lower end of the useful bandwidth of coupled amplifier by plotting the current gain
the amplifier. as a function of frequency on semilogarithmic
paper and showing the bandwidth.
(h) The hybrid-π equivalent circuit for comput-
ing the high-frequency performance of a BJT
Internal B IB C IC
IS
resistance
of source
IL
RS
RB Base bias hie VB hfeIB hoe RL VC
Source + equivalent Collector
VS resistance
signal load
−
resistance
E
(a)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Figure P8.5.6
Copyright OUP
PROBLEMS 421
−12 V
55 kΩ 2.4 kΩ 6 kΩ 0.24 kΩ
C
25 µF 25 µF, 12 V
BJT BJT
b
B 2N104 2N104
1 kΩ 4.5 kΩ E 1.2 kΩ
25 mV 0.6 kΩ 100 µF 0.1 kΩ 50 µF

rms
a
First stage Second stage
(c)
B IB C
IL I2 Useful output current of first stage

(Input current of second stage)
IS RB hie hfeIB RL R2 Net input resistance
appearing at base terminal
of second transistor
E
(d)
Coupling
capacitor
CC
B IB C
IL I2
IS RB hie hfeIB RL R2
E
(e)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
B B′ II IT C IC
Transition
RBB′ IB ID CT IL I2
capacitor
Base
IS RB CD RL R2
spreading RB′E gmVB′E = hfeIB
resistor Forward Diffusion
biased capacitor VC
resistor
E
(f)
Figure P8.5.6 Continued
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9 Digital Circuits
9.1 Transistor Switches
9.2 DTL and TTL Logic Circuits
9.3 CMOS and Other Logic Families
9.5 Practical Application: A Case Study—Cardiac Pacemaker, A Biomedical Engineering

Application
Problems
The use of nonlinear devices (BJT and FET) in constructing linear amplifiers has been studied in
Chapter 8. Although these devices are inherently nonlinear, their operation was confined to the
linear portions of their characteristics in order to produce linear amplification of a signal. When
these devices are operated in the nonlinear regions of their characteristics, the primary use lies in
electronic switches for use in computers and other digital systems. Digital electronic circuits are
becoming of increasing importance. Revolutionary advances in integrated-circuit (IC) technology
have made it possible to place a large number of switches (gates) on a chip of very small size.
Besides the advantage of utilizing less space, another significant advantage of digital systems
over analog systems is their inherent immunity to noise and interference.
Digital building blocks (made up of transistor circuits) and computer systems have been
presented in Chapter 6. Digital circuits are almost always purchased as ready-made IC building
blocks. However, users of digital hardware must decide which technology is best suited for each
case because competing technologies known as logic families are available. Digital circuit design
is of course of great interest to engineers in the IC industry for designing and building digital
blocks. The users of digital technology will certainly benefit from knowing what is inside the
blocks they use.
A fundamental circuit of digital logic is the transistor switch, or inverter, which is considered
in Section 9.1. Basic logic circuits are developed in Section 9.2 using bipolar technology.
Section 9.3 deals with other logic families, particularly the FET-based family known as CMOS
(complementary metal-oxide semiconductor) technology.
422
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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9.1 TRANSISTOR SWITCHES 423
9.1 TRANSISTOR SWITCHES

The basic element of logic circuits is the transistor switch, a simplified model of which is shown
in Figure 9.1.1. The control signal is the input voltage vin, which must lie in either the “low” range
or the “high” range for a digital circuit. When vin is low, the switch may take either the open or
the closed position; when vin is high, the switch takes the other position. Looking at Figure 9.1.1,
closing the switch makes vout zero, while opening the switch yields an output near VCC, assuming
that not much current flows through the output terminal. If VCC is chosen to lie in the high range
and V = 0 is inside the low range, then allowed values of vin control the switch and give rise to
allowed values of vout. A common special circuit in which a high input yields a low output, and
vice versa, is known as an inverter, which performs the complement operation.
A typical inverter circuit using a bipolar transistor is shown in Figure 9.1.2(a), and the
operation of the BJT switch is illustrated in Figure 9.1.2(b). The KVL around the collector–
emitter loop is given by
vCE = VCC − RC iC (9.1.1)
from which the load line may be drawn on the collector–emitter characteristic. The KVL around
the base–emitter loop is given by
vBE = Vi − RB iB (9.1.2)
and the corresponding load line may be drawn on the base–emitter characteristic.
If the input is at zero volts, that is logic 0, then the base current is zero, and the operating
point is at ➀, as shown in Figure 9.1.2(b). The transistor is then said to be cut off, or simply off,
when only a very small value of collector current (I C cutoff ∼
= ICEO) flows. Thus, in the cutoff state
the output voltage is given by
Vo = VCE cutoff ∼
= VCC − RC ICEO ∼
= VCC = 5V (i.e., logic 1 level) (9.1.3)
If the input Vi changes to +5 V (logic 1 level), the base current is given by
Vi − vBE
IB sat = (9.1.4)
RB
where vBE ∼ = 0.7 V, which is the threshold voltage VT. Supposing that RB is chosen so as to drive
the transistor into saturation such that I B sat = 50 µA, the operating point switches to point ➁ on
the collector–emitter characteristic, when the transistor is said to be saturated, or simply on. In
this saturated state V CE sat = V sat, which is typically 0.2 to 0.3 V, depending on iB. The collector
current in saturation is given by
VCC − Vsat ∼ VCC
IC sat = = (9.1.5)
RC RC
VCC Figure 9.1.1 Model of transistor switch.

--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
vout
vin
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424 DIGITAL CIRCUITS
+
VCC = 5 V
RC
iC +
iB RB +
+ vCE VO = vCE
+
Vi −
vBE −
− −
(a)
iB , µA
IB sat = 50 2 1
Slope = − R
B
1
vBE , V
0.5 Vi
VT = 0.7
iC , mA
60 µA
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
VCC
RC 50 µA
5
IC sat 2 Saturation 40 µA
4
3 30 µA
2 20 µA
1 10 µA
1 Cutoff
iB = 0
IC cutoff = ICEO vCE , V
1 2 3 4 5
VCC
VCE sat = Vsat 0.2 to 0.3 V
VCE cutoff VCC
(b)
Figure 9.1.2 BJT inverter switch. (a) Circuit with npn switching transistor.
(b) Typical operation using load lines.
Thus, the transistor behaves like an ideal switch, as shown in Figure 9.1.3. It can be shown that
saturation will occur when
Vi − VT VCC − Vsat RB
> or Vi > (VCC − Vsat ) + VT (9.1.6)
RB β RC β RC
The power dissipated in the transistor p = vCE iC +vBE iB = ∼ vCE iC is very small or approximately
zero in either cutoff or saturation. It should be noted, however, that power is expended in switching
from one state to the other, going through the linear or active region.
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9.1 TRANSISTOR SWITCHES 425
+ VCC + VCC Figure 9.1.3 BJT switch. (a) Off (cutoff) position.
(b) On (saturation) position.
RC RC
=
C + C +
ICEO S Vo S Vo
E
E − −
(a)
+ VCC + VCC
RC RC
=
C + C +
S S
+ Vo Vo
Vsat
−
E − E −
(b)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Vo Figure 9.1.4 Transfer characteristic of BJT
switch.
Cutoff Active Saturation
region region region
VCC
Vsat
Vi
VT 0.7 V VCC
RB
(VCC − Vsat) +V
βRC T
Figure 9.1.4 shows the transfer characteristic of a BJT switch relating Vi and Vo, whereas
Figure 9.1.5 depicts a plot of a typical input-voltage waveform and the resulting output-voltage
waveform, illustrating the essential inherent inversion property of the switch, the waveform
distortion, propagation delays, and rise and fall times of the BJT switch. Note the following
time parameters.
Copyright OUP
• Propagation delay td is a certain amount of delay for a change to occur. It is defined here
as the time to change from 0 to 10% of the final value. (Sometimes propagation delay is
defined as the time between the 50% level of Vi and the 50% level of Vo.) When Vi abruptly
changes from 0 to 5 V, note that the output voltage and collector current do not initially
change during the propagation delay time.
• Rise time tr is the time needed to change from 10 to 90% of the final level.
• Propagation delay ts occurs when the input pulse returns to 0 V (i.e., logic level 0). This is
a result of the time required to remove charge stored in the base region before the transistor
begins to switch out of saturation and is usually longer than td.
• Fall time tf is the time required for the output voltage and the collector current to change
state. That is the time required to switch through the active region from saturation to cutoff.
These times are influenced by the various capacitances inherent in the transistor and other
stray capacitances. In turn, the design of a digital switch is influenced by these propagation
delays, and the rise and fall times, which are grouped under the general category of switching
speed.
Vi
5V
Vo
5V Cutoff
Vsat Saturation
t
iC
IC sat
0.9IC sat
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
0.1IC sat
t
IC cutoff = ICEO 0 ts
tr tf
td
Figure 9.1.5 Typical input-voltage waveform and resulting output-voltage waveform.
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9.2 DTL AND TTL LOGIC CIRCUITS 427
EXAMPLE 9.1.1
For the circuit of Figure 9.1.2, given that VCC = 5 V, RC = 1 k-, β = 100, and the high range is
4 to 5 V, choose RB such that any high input will saturate the transistor with the base overdriven
by a factor of at least 5. Assume V sat to be 0.2 V.
Solution
Since iC ∼
= βiB + ICEO , one must have (neglecting ICEO) IB sat > IC sat /β. But
VCC − Vsat
IC sat =
RC
Hence,
VCC − Vsat
IB sat >
βRC
With a factor of 5 included for the desired overdrive, one has
VCC − Vsat 5 − 0.2
iB = 5 =5 = 240 µA
βRC 100(1000)
When vi is in the high range, the emitter–base junction is forward-biased. The base current that
flows is given approximately by
vi − 0.7 vi − 0.7
iB = or RB =
RB iB
Setting vi = 4 V, which is the lowest value in the high range,
4 − 0.7
RB = = 13,750 -
2.4 × 10−4
One chooses the closest standard resistance smaller than 13,750 -, since making RB smaller
increases the overdrive and hence improves the margin of safety.
9.2 DTL AND TTL LOGIC CIRCUITS

Bipolar transistors were the first solid-state switching devices commonly used to implement digital
logic circuits in the 1950s and 1960s. These circuits used diodes at the input of the gate for logic
operation followed by a transistor (BJT) output device for signal inversion. One of the bipolar logic
families that emerged was called DTL (diode–transistor logic). The TTL (transistor–transistor
logic) soon replaced DTL and then became the principal bipolar technology for the next two
decades. It is still often used today. In TTL circuits, the diodes used in DTL at the gate input are
replaced with a multiemitter transistor for increased performance. Primarily by reducing the size
of the transistors and other components, speed and performance improvements have been made
in TTL circuits.
Both DTL and TTL are called saturating logic families, because the BJTs in the circuit
are biased into the saturated region to achieve the effect of a closed switch. The inherent slow
switching speed is a major difficulty with saturating logic because saturated BJTs store significant
charge and switch rather slowly. Schottky TTL is a nonsaturating logic family that was later
developed to achieve higher speed performance by preventing the transistors from saturating.
Another bipolar nonsaturating logic family is ECL (emitter-coupled logic), which has BJTs that
remain biased in the active region. These circuits consume more power, are less dense, but are
extremely fast.
--`,,,``,,`,```,``,````
Copyright OUP
Using the transistor switch, logic gates can be constructed to perform the basic logic functions
such as AND, OR, NAND, NOR, and NOT. Since the individual gates are available in the form of
small packages (such as the dual-in-line package, or DIP), it is generally not necessary to design
individual gates in order to design an overall digital system. However, the designer needs to
observe fan-out restrictions (i.e., the maximum number of gates that may be driven by the device),
fan-in restrictions (i.e., the maximum number of gates that may drive the device), propagation
delays, proper supply voltage to the unit, and proper connections to perform the intended logic
function. Gates of the same logic family can be interconnected since they have the same logic
voltage levels, impedance characteristics, and switching times. Some of the logic families are
discussed in this section.
DTL (Diode Transistor Logic) Gate

A circuit realization of a NAND gate will now be developed. By connecting NAND gates together
in various ways, one can synthesize other gates and flip-flops. Thus in principle, a single NAND
gate circuit, repeated many times, would be sufficient to build up digital systems.
One possible NAND gate circuit is shown in Figure 9.2.1, in which it can have as many inputs
as desired (indicated by the dashed-line input C), and typical values of VCC = 5 V, RA = 2 k-,
RC = 5 k-, and β = 50. We shall now consider the two inputs A and B that are quite adequate for
our discussion, with the high range defined to be 4 to 5 V and the low range defined to be 0 to 0.5 V.
While the input voltages vA and vB are constrained to lie inside the high or low range of
the allowed voltage ranges, the resulting output voltage vF is supposed to be inside the high or
low range as well. For different combinations of vA and vB, we need to find vF. Since the circuit
consists of no less than five nonlinear circuit elements (DA, DB, D1, D2, and T 1), an approximation
technique is used for analysis, while taking the voltage across a current-carrying forward-biased
pn junction to be 0.7 V. The reader may have realized that it is not obvious at the start which
diodes are forward-biased and which are reverse-biased. Hence a guessing procedure is used in
which a guess is made and checked for self-consistency.
Let us start by letting vA = vB = 0, in which case a probable current path is from VCC down
through RA and through inputs A and B. Since this guess implies current flow through DA and DB in
the forward direction, we may guess that the voltage at X is 0.7 V. There is also a current path from
X down to ground through D1 and D2 and the base–emitter junction of the transistor. Even though
the sign of the guessed voltage is correct to forward-bias these three junctions, its magnitude of
0.7 V is insufficient since 2.1 V (or 3 × 0.7) is needed to make current flow through this path.
Then iB = 0; the transistor is cut off; and the output voltage vF = VCC = 5 V, assuming that
VCC VCC Figure 9.2.1 DTL NAND gate.
RA RC iL
iB F Output
DA
A T1
X
DB D1 D2
Inputs B
DC
C
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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9.2 DTL AND TTL LOGIC CIRCUITS 429
no load current flows through the output terminal. Thus in this case, DA and DB are conducting,
whereas D1, D2, and T 1 are not. This is illustrated by the first line in Table 9.2.1.
For the inputs indicated on the other lines of Table 9.2.1 the reader can reason out the other
columns shown. In terms of the high and low ranges, the operation of the gate is illustrated in Table
9.2.2. The truth table is given in Table 9.2.3 using the positive logic in which high is indicated by
1 and low is indicated by 0. One can now see that the circuit does function as a NAND gate.
TABLE 9.2.1 Inputs and Outputs for NAND Gate of Figure 9.2.1
Volts Conduction Volts

vA vB vX DA DB D1D2T 1 vF
0 0 0.7 YES YES NO 5

0 0.2 0.7 YES NO NO 5
0.3 4.6 1.0 YES NO NO 5
4.6 0.3 1.0 NO YES NO 5
4.8 4.1 2.1 NO NO YES 0.2 (= V CE sat)
TABLE 9.2.2 Operation of NAND gate of Figure 9.2.1
vA vB vF
LOW LOW HIGH

LOW HIGH HIGH
HIGH LOW HIGH
HIGH HIGH LOW
TABLE 9.2.3 Truth Table using positive logic
A B F
0 0 1
0 1 1
1 0 1
1 1 0
EXAMPLE 9.2.1
What logic function does the circuit of Figure 9.2.1 perform if negative logic is used?
Solution
Using negative logic, Table 9.2.2 can be translated into the following truth table. This can be seen
to be the logic function NOR.
A B F
1 1 0
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
1 0 0
0 1 0
0 0 1
Copyright OUP
The DTL NAND gate circuit shown in Figure 9.2.1 and others closely related to it belong to
the DTL logic family. Since all circuits in the same family have the same high and low ranges,
they can be interconnected to build up digital systems. Although we have described the DTL gate
as our first example for our convenience and easy understanding, the DTL technology is almost
obsolete and is replaced by TTL.
TTL NAND Gate

The TTL logic family uses only transistors instead of a combination of transistors and diodes.
TTL has the same high and low ranges as DTL. TTL is the most popular BJT logic family. A
primary reason for the popularity of TTL over DTL is its higher speed. TTL has a typical fan-out
of 10 or more, small propagation delays on the order of 2 to 10 ns, and a power consumption
of about 2 mW. By contrast, DTL has a typical fan-out of 8 to 10, a propagation delay on
the order of 30 to 90 ns, and a power consumption of around 15 mW. The noise margins and
fan-out of DTL are generally better than those of RTL (resistor–transistor logic; see Problem
9.2.8), but the switching speeds are about the same. The emitter-coupled logic (ECL) family
is also available with increased switching times, although not discussed here in any detail.
The name arises from the common attachment of the emitters of the input transistors. The
propagation delays are on the order of 1 ns, but the power consumption is quite high (on the
order of 25 mW per gate). Low power consumption combined with relatively small noise margins
(< 0.3 V) has made TTL a popular choice and, in particular, the high-speed Schottky diode
TTL gates.
A typical TTL NAND gate is shown in Figure 9.2.2. Transistor T 1 is a multiple-emitter
transistor (npn BJT) which acts as an AND gate. Replacing the base–emitter and base–collector
junctions with diodes, T 1 can be represented as shown in Figure 9.2.3.
VCC = 5 V
R1
R2 R3
X
VA F
Vo
VB Y
VC
T1 T2 T3
Figure 9.2.2 TTL NAND gate.
X Figure 9.2.3 Diode replacement of three-input transistor T 1 of

Figure 9.2.2.
Y
DA Base-collector
VA diode D
DB
VB Base-emitter diodes
DC
VC
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
9.3 CMOS AND OTHER LOGIC FAMILIES 431
EXAMPLE 9.2.2
Considering the TTL NAND gate circuit of Figure 9.2.2, with one or more inputs low, show that
the output will be high.
Solution
Figure E9.2.2 TTL NAND gate with one input
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
VCC
low and the other two high.
R2 R3
R1
F
T2 Vo
iC1
iB1 Y T3
C T1 X
B A
Let one of the emitters, say A, be grounded and therefore let VA be low while VB and VC are high.
The situation is then as shown in Figure E9.2.2. There is a current path from VCC down through R1
and emitter A to ground. With vX = 0.7 V a base current iB1 ∼ = (VCC − 0.7)/R1 will be flowing in
transistor T 1. Note, however, that iC1 must be flowing out of the base of transistor T 2. That being
the wrong direction for the base current of an npn transistor, it must represent the reverse current
through one of the junctions in T 2. Reverse currents being very small, iB1 >> iC1 /β. Hence T 1
will be saturated, and its collector-to-emitter A voltage will be V CE sat, which is about 0.2 V. Thus,
the voltage at Y will be about 0.2 V, which is much less than the 1.4 V needed to forward-bias the
emitter junctions of T 2 and T 3. Thus T 3 is cut off and output Vo at F is high.
The TTL family is large and widely used. TTL circuits can switch fairly quickly allowing
data rates on the order of 10 to 40 Mbits/s (mega stands for 220). They also have good output
current capability. However, they consume too much power and space to be used in LSI. Hence,
TTL is used primarily in SSI and MSI, which are the less densely packed ICs. MOS (metal-oxide
semiconductor) technology, which has low power consumption and high packing density, but low
output current capability, is widely used in LSI.
9.3 CMOS AND OTHER LOGIC FAMILIES

Both DTL and TTL are based on the saturating BJT inverter. The transistor acts as a switch
that connects or disconnects the collector and emitter. The switch is closed when sufficient base
current is applied to saturate the transistor. While the BJT technologies have dominated during
the 1970s, logic families based on MOSFET technology are now more widely used because of the
advantages of fewer fabrication steps and generally lower power consumption. After PMOS and
NMOS technologies, CMOS emerged as the dominant MOS technology and remains so today.
Let us consider the simple MOSFET inverter with resistive load shown in Figure 9.3.1(a),
quite similar in principle to the BJT inverter, although the circuit is rather impractical, as we shall
see later. The load line for RD = 23 k- and VDD = 7 V is shown along with the transistor I–V
characteristics in Figure 9.3.1(b). On finding vout (= vDS) for different values of vin (= vGS), the
Copyright OUP
ID , mA
1.0 Ohmic or VGS = 7

triode
0.8 region
VDD = 7 V Pinch-off or
active region
0.6 VGS = 6
RD = 23 kΩ
vout 0.4
VGS = 5
0.2
vin Load line VGS = 4
0 2 4 6 8 10 VDS , V
VGS ≤ 3
(a) (b)
vout , V Figure 9.3.1 MOSFET inverter with resistive

load. (a) Circuit with n-channel enhancement
7 MOSFET and a resistor. (b) Transistor I–V charac-
teristics. (c) Voltage-transfer characteristic for (a).
6
0 1 2 3 4 5 6 7 vin , V
(c)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
voltage-transfer characteristic (vout versus vin) is plotted in Figure 9.3.1(c). By choosing the low
range to be 0 to 3 V (i.e., less than the threshold voltage) and the high range to be 5 to 7 V, we can
see that any input voltage in the low range gives an output of 7 V (high) and inputs in the high
range give outputs in the low range. Thus, the circuit is seen to be an inverter.
While the circuit of Figure 9.3.1(a) functions correctly as an inverter, in order to maintain
low current consumption, large values of RD are needed, but they are undesirable in ICs because
they occupy too much space. In order to increase the number of circuits per IC, RD is usually
replaced by a second MOS transistor, which is known as an active load. When RD is replaced
by an n-channel MOSFET, it results in the logic family known as NMOS, which is widely used
in VLSI circuits such as memories and microprocessors. NMOS logic circuits are more compact
and, as such, more of them can be put on each chip. Also, MOS fabrication is simpler than
bipolar fabrication; with fewer defects, production costs are less. As mentioned before, the main
disadvantage of MOS technology, as compared to TTL, is low output current capacity.
Copyright OUP
FET switches offer significant advantages over BJT switches. An FET switch does not draw
current from a previous stage because the gate current of an FET is practically zero. Consequently,
no significant power-loading effects are present, whereas BJTs, in contrast, do load down previous
stages. Another advantage of FETs is that their logic voltage levels (typically, VDD = 15 V) are
higher than those of the BJTs (typically, VCC = 5 V). Thus, the FET logic circuits tend to tolerate
more noise than the comparable BJT logic circuits. However, their switching speeds tend to be
somewhat smaller than those for BJTs in view of the larger inherent capacitances of the FETs.
MOSFETs are preferred over JFETs for digital integrated circuits. Either PMOS (p-channel
metal-oxide semiconductor) or NMOS (n-channel metal-oxide semiconductor) logic circuits can
be constructed. Requiring only about 15% of the chip area of a BJT, MOSFETs offer very high
packing densities.
The usage of a p-channel MOSFET as the active load for an n-channel MOSFET leads
to a logic family known as complementary-symmetry MOS, or CMOS. CMOS technology has
significant advantages and has become most popular. A basic CMOS inverter is shown in Figure
9.3.2(a), in which both a p-channel and an n-channel enhancement MOSFET are used as a
symmetrical pair, with each acting as load for the other.
When the input vin is low, the gate–source voltage of the NMOS is less than the threshold
voltage and is cut off. The gate–source voltage of the PMOS, on the other hand, is −VSS , where
VSS, the supply voltage, is greater than the threshold voltage, VT . Then the PMOS is on, and the
supply voltage appears at the output vout. When the input vin is high (vin ∼= VSS), the PMOS turns
off; the NMOS turns on. Then VSS appears across the drain–source terminals of the PMOS and
the output vout drops to zero. Thus, the circuit functions as an inverter. Figure 9.3.2(b) shows the
simplified circuit model of the CMOS inverter by depicting each transistor as either a short or an
open circuit, depending on its state.
Note that when the output is in the high state, the PMOS is on with the NMOS being off;
when the output is in the low state, the NMOS is on with the PMOS being off. Virtually no current
is drawn from the power supply in either case. The CMOS has the advantage that it uses no power
except when it is actually switching. This property of virtually no power consumption, coupled
with the small chip surface needed, makes the CMOS very favorable for miniature and low-
power applications such as wristwatches and calculators. Because of the poor switching speeds
(compared to TTL), they are applied to low- to medium-speed devices. The principal disadvantage
of the CMOS is a more complex fabrication procedure than that of the NMOS, leading to more
defects and higher cost.
Figure 9.3.2 CMOS inverter and circuit model.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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vout Figure 9.3.3 Typical voltage-transfer character-

istic of a CMOS logic circuit, showing noise mar-
gins.
VOH
VOL
vin
VOL VIL VIH VOH
NML NMH
Transition
width
The switching action in the CMOS circuit is rather sharp, as compared with that of Figure
9.3.1(c). A general voltage-transfer characteristic shown in Figure 9.3.3 illustrates this feature. A
very small change in vin is sufficient to produce a relatively large change in vout. The voltages VOH
and VOL, indicated in Figure 9.3.3, are, respectively, the nominal high and low output voltages of
the circuit. VIL and VIH are the input voltages at which |dVout /dVin | = 1. These are seen to be the
boundaries of the low and high ranges. The region between VIL and VIH is known as the transition
region, and the transition width is given by VI H − VI L . The lower and upper noise margins are
given by VI L − VOL ≡ NML and VOH − VI H ≡ NMH , respectively. The noise margins indicate
the largest random noise voltages that can be added to vin (when it is low) or subtracted from vin
(when it is high), without yielding an input in the forbidden transition region. A typical voltage-
transfer characteristic and drain current ID1 versus input voltage vin for the CMOS inverter are
shown in Figure 9.3.4. Note that when vin is inside either the low or the high states (and not in
the transition region), the drain current ID1 = −ID2 ∼ = 0. The maximum value of ID1 that occurs
during transition is indeed very small.
EXAMPLE 9.3.1
For the CMOS inverter with characteristics shown in Figure 9.3.4, determine the noise margins.
Solution
From Figure 9.3.4(a), VOH = 7 V and VOL = 0. From the location of the approximate points
where the absolute value of the slope is unity, VI L = 3.1 V and VI H = 3.9 V. Thus, noise margins
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
are given by
NML = VI L − VOL ∼
= 3.1 − 0 = 3.1 V
NMH = VOH − VI H ∼
= 7 − 3.9 = 3.1 V
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vout , V Figure 9.3.4 Typical characteristics of a CMOS

inverter. (a) Voltage-transfer characteristic. (b)
7 Drain current versus input voltage.
6
0 1 2 3 4 5 6 7 vin, V
(a)
ID1, mA
0.02
0.01
0 1 2 3 4 5 6 7 vin, V
(b)
CMOS NAND and NOR gates with two inputs are shown in Figure 9.3.5. For the NAND
gate of Figure 9.3.5(a), if at least one input is in the low state, the associated PMOS device will
be on and the NMOS device will be off, thereby yielding a high output state. If, on the other
hand, both VA and VB are high, both PMOS devices will be off while both NMOS devices will
be on, thereby giving a low output V out. Thus, the CMOS device of Figure 9.3.5(a) functions as
a NAND gate.
For the NOR gate of Figure 9.3.5(b), when both inputs VA and VB are low, both NMOS
devices will be off with both PMOS devices on, and the output V out is high around VSS. If, on
the other hand, one of the inputs goes to be high, the associated PMOS device turns off and the
corresponding NMOS device turns on, thereby yielding an output V out to be low. Thus, the CMOS
device of Figure 9.3.5(b) functions as a NOR gate. Note that neither gate in Figure 9.3.5 draws
virtually any power-supply current, so that there is virtually no power consumption.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Another CMOS circuit that is conveniently built into CMOS technology is known as the
transmission gate, which is not strictly speaking a logic circuit. It is a switch controlled by a logic
input. In its circuit shown in Figure 9.3.6, the control signal C and its complement C̄ determine
whether or not the input is connected to the output. When C is low (and C̄ is high), neither gate
can induce a channel and the circuit acts as a high resistance between input and output. The
transmission gate is then effectively an open circuit. On the other hand, when C is high (and C̄
is low), the transmission gate provides a low-resistance path between input and output for all
Copyright OUP
Figure 9.3.5 CMOS gates with

two inputs. (a) NAND gate.
(b) NOR gate.
allowed values of vin. The reader is encouraged to reason out these statements. Since the gate
conducts well in either direction when the switch is on, the circuit is known to be reciprocal, in
which case the labels “input” and “output” can be interchanged.
In addition to TTL, NMOS, and CMOS, several other logic families have been developed
to suit various purposes. Emitter-coupled logic (ECL) is a high-speed bipolar technology with
high power consumption. Transistors operate in the active mode and do not saturate in ECL;
propagation delays per gate are as short as 1 ns. Besides high power consumption, the logic swing
(which is the difference between high and low voltage levels) is small, being on the order of 1 V,
which makes the ECL vulnerable to random noise voltages, thereby leading to errors.
The integrated-injection logic (IIL or I2L) is a compact, low-power bipolar technology
competitive with MOS technology for LSI. This technology offers packing densities ten times
larger than TTL: 100 to 200 gates per square millimeter as compared with probably 10 to 20 for
TTL. Power consumption and delay time have a kind of trade-off relationship in IIL technology.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
Figure 9.3.6 CMOS transmission gate. (a) Circuit. (b) Symbol.
As with ECL, the logic swing is small, thereby implying vulnerability to noise. While MOS can
be made compatible with TTL, IIL voltage ranges are incompatible with other families. The IIL
is used inside LSI blocks, with interfacing circuits provided at the inputs and outputs to make the
blocks externally compatible with TTL.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
A particular choice of a logic technology involves a compromise of many practical charac-
teristics. The power-delay product (PDP) is the approximate energy consumed by a gate every
time its output is switched, and it forms a general figure of merit. PDP is the product of Pav, the
average dc power consumed by the gate, and TD, the gate’s propagation delay. It is the energy
required to effect a single change, since TD is the time required for a single change of logic state,
and is a measure of the electrical efficiency of the switch.
For TTL and ECL, PDP is on the order of 100 pJ; for NMOS it is around 10 pJ. Slower
versions of I2L can operate at 1 pJ per change. The average power consumption in CMOS is
linearly proportional to the data rate. CMOS, run at maximum speed, has comparable PDP to
that of NMOS. By reducing logic swing and/or device capacitance, the PDP can be reduced.
Improvements in PDP can also be achieved by making conventional circuits physically smaller
with consequent increased package density. Microfabrication technologies have gradually reduced
the minimum feature size, which refers to the typical minimum dimension used in an IC.
Improved performance is also achieved with substantially different kinds of technology,
such as cryogenic Josephon digital technology, which makes use of superconductors and can
offer 0.04-ns delay times and a PDP of about 2 × 10−4 pJ.

• BJT inverter switch, its characteristics, and its operation.
• Analysis of DTL and TTL logic circuits.
• MOSFET inverter and its characteristics.
Copyright OUP
• Advantages of PMOS and NMOS logic circuits.

• CMOS inverter switch and its characteristics.
• CMOS gates and CMOS technology.
• Notions of other logic families.
Cardiac Pacemaker, a Biomedical Engineering Application

When blockage occurs to the biological signals that stimulate the heart to beat, the application
of electric pacemaker pulses forcing the heart to beat at a higher rate is very helpful. A demand
pacemaker is particularly helpful to the patient with partial blockage, in which case an electric
pulse to the heart muscle is only applied when a beat does not occur within a predetermined time
interval.
The pacemaker circuitry along with a lithium battery are enclosed in a metal case, which is
implanted under the skin on the patient’s chest. The mental case and the tip of the catheter (a wire
enclosed in an insulating tube) form the electrical terminals of the pacemaker. A simplified block
diagram of a typical demand pacemaker is shown in Figure 9.5.1.
The input amplifier amplifies the natural heart signals, which have a small amplitude on the
order of 1 mV. Filtering eliminates certain frequency components so that heartbeats can be better
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
detected. A comparative circuit is then used to compare the amplified and filtered signal with
a threshold value and detect either a natural heartbeat or an output pacing pulse. This detection
decision is passed on to the counting and timing circuitry through an AND gate. The second input
to the AND gate comes from the counter circuit, such that input signals for 0.4 s after the start of
a natural or forced beat are ignored.
The timing functions are performed by counting the output cycles of a timing oscillator,
which generates a square wave with a precise period of 0.1 s. The digital signals produced by the
counter are passed on to a digital comparator, which compares them with signals from a reference
count generator and decides when the pulse generator is to deliver an output pulse of a specified
amplitude and duration.
Reset
terminal
Timing
oscillator
Catheter Comparator AND
to heart gate
Input +
amplifier Digital
− Counter
and filter comparator
Output Reference
pulse count
generator generator
Pacemaker case
Figure 9.5.1 Simplified block diagram of demand cardiac pacemaker (power source connections not shown).
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PROBLEMS 439
Extremely low power consumption and high reliability become important criteria for all
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
pacemaker designs. While electrical engineers can come up with better circuit designs, mechanical
and chemical engineers have to select better materials to produce the case and the catheter, and
above all, the physicians have to provide the pacemaker specifications. Thus, doctors and engineers
have to work in teams in order to develop better biomedical products.
PROBLEMS
9.1.1 Show that saturation will occur when Equation has the characteristics shown in Figure P9.1.6(a).
(9.1.6) is satisfied. Sketch Vo as a function of time for the input signal
*9.1.2 Consider a BJT switch connected to the next stage, given in Figure P9.1.6(b).
as shown in Figure P9.1.2, in which iout is likely 9.2.1 Considering Table 9.2.1, the first line has been
to be negative when vout is high. Assume VCC = 5 reasoned out in the text. Justify the other four lines.
V, RC = 1k-, and the high range to be 4 to 5 V.
Find the largest |iout | that can be tolerated. *9.2.2 With vA = vB = 0 in Figure 9.2.1, show that a
9.1.3 The transistor switch of Figure 9.1.2(a) is to be guess vX = 2.1 V would lead to a contradiction,
designed to operate in saturation and in cutoff and hence cannot be correct.
when the pulse signal shown in Figure P9.1.3 9.2.3 Consider the circuit of Figure 9.2.1 with vA = 0.4
is applied to the input. Assume an ideal transis- V and vB = 0.3 V. Find vX and vF.
tor with β = 100, VT = 0.7 V, Vsat = 0.2 V,
and ICEO = 0.1 mA. Letting the supply voltage 9.2.4 With vA = 0.2 V and vB = 4.5 V in Figure 9.2.1,
VCC = 5 V and RC = 500 -, determine the min- justify why vX = 0.7 V will be an incorrect guess.
imum value of RB, and sketch the output-voltage 9.2.5 Considering Figure 9.2.1 of the DTL NAND gate
waveform. circuit, inquire as to why D1 and D2 are used in
9.1.4 For the BJT switch described in Figure 9.1.2(a), the circuit. (Hint: Consider the third line of Table
let VCC = 5 V, VT = 0.7 V, Vsat = 0.2 V, and 9.2.1.)
β = 25. If Vl switches between 0 and 5 V and 9.2.6 Consider the DTL gate circuit shown in Figure
iB ≤ 0.1 mA, find the minimum values of RB and P9.2.6. Assume diodes with VT = 0.7 V and the
RC for proper operation. transistor to have β = 35, VT = 0.7 V, ICEO = 0,
9.1.5 Sketch the transfer characteristic for the BJT and Vsat = 0.2 V.
switch described in Figure 9.1.2(a), given that (a) For inputs VA = 5 V and VB = 0 V, determine
VCC = 5 V, Vsat = 0.2 V, VT = 0.7 V, RC = Vo.
500 -, RB = 10 k-, and β = 100.
(b) For inputs VA = VB = 0 V, determine Vo.
9.1.6 The transistor switch of Figure 9.1.2(a) with RB =
10 k- and RC = 750 - employs a BJT which (c) Is this a configuration of a DTL NOR gate?
VCC VCC
vi ,V
RC
vout
Next
RB stage
iout
vin
5
t, µs
0 5 10 15
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iB, mA
0.1
iC C 0.08
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
iB + 0.06
B
+
0.04
vBE vCE
− − 0.02
E
0 vBE, V
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
ic, mA
iB = 0.12 mA
8 0.1 mA
7
0.08 mA
6
5 0.06 mA
4
0.04 mA
3
2 0.02 mA
1
iB = 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 vCE, V
(a)
Vi , V
t, ms
1 2 3 4
(b)
Figure P9.1.6
9.2.7 For the DTL gate shown in Figure P9.2.6, as- *9.2.8 A gate using resistor-transistor logic (RTL) is
sume ideal diodes, VT = 0.7 V, Vsat = 0.2 V, shown in Figure P9.2.8. Justify that this gate per-
RB = 10 k-, RC = 500 -, and VCC = 5 V. As- forms the NOR function.
9.2.9 Study the DTL gate circuit shown in Figure P9.2.9
suming β = 20 for the BJT and using reasonable
and state whether it behaves like a NOR gate or a
approximations, sketch the output Vo for the input NAND gate.
signals of Figure P9.2.7.
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PROBLEMS 441
+VCC = 5 V Figure P9.2.6
RC = 500 Ω
DA
VA Vo
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
DB RB
VB
12 kΩ
VA, V Figure P9.2.7
10
5
t, ms
1 2 3 4 5 6
−5
VB, V
6
t, ms
1 2 3 4 5 6
−3
9.2.10 Considering the TTL NAND gate circuit of Figure *9.2.14 For the TTL NAND gate circuit of Figure P9.2.12,
9.2.2, with all inputs high, show that the output will assuming that the inputs vary between 0 and 5 V
be low. and VCC = 5 V, determine the maximum value of
9.2.11 Consider the TTL gate circuit of Figure 9.2.2. If RB to saturate T 2 if iC sat = 3.8 mA.
VA = 0.1 V, VB = 0.2 V, and VC = 0.3 V, 9.3.1 Consider the n-channel JFET switch shown in
determine the approximate values of VX, VY, and Figure P9.3.1(a) with the characteristics shown in
Vo. Figure P9.3.1(b).
9.2.12 A TTL NAND gate with a multiple-emitter npn (a) Explain its operation.
BJT (which acts as an AND gate) is shown in
(b) Draw the circuit of a depletion MOSFET
Figure P9.2.12.
switch.
(a) With all inputs in the high state, show that the
output Vo will be in the low state. (c) For the input shown in Figure P9.3.1(c),
sketch the output as a function of t.
(b) With at least one input, say VA, being in the
low state, show that the output Vo will be in 9.3.2 For the JFET switch shown in Figure P9.3.1(a)
the high state. with RD = 3k- and VDD = 12 V, sketch the
output voltage as a function of t, if the input voltage
9.2.13 Discuss the significance of R4, T 4, T 3, and the
is as shown in Figure P9.3.2(a) and the JFET
diode between T 4 and T 3 in the TTL NAND gate
characteristics are as given in Figure P9.3.2(b).
circuit of Figure P9.2.12.
Copyright OUP
+VCC Figure P9.2.8
RC
Vo
R
VA T1
R
VB T2
R
VC T3
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
+VCC Figure P9.2.9 DTL gate circuit.
DA RB RC
VA
Vo
VB
VC D
9.3.3 FET logic circuits can be used with positive P9.3.5(a). The n-channel MOSFET T 1 has the
pulses by using enhancement-mode n-channel characteristics shown in Figure P9.3.5(b). T 2 has
MOSFETs as switches. Figure P9.3.3(a) shows the identical characteristics except for the changes of
circuit and Figure P9.3.3(b) the MOSFET charac- sign appropriate to a p-channel device.
teristics. For the input shown in Figure P9.3.3(c),
sketch the output as a function of time. (a) Outline a graphical procedure in order to find
the operating point of the CMOS inverter
*9.3.4 The complementary-symmetry MOSFET (CMOS)
by superposing the I–V characteristics of T 1
switch shown in Figure 9.3.2 has MOSFETs with
and T 2.
VT = 5 V and Vsat = 1 V. If VSS = 20 V and vin as
shown in Figure P9.3.4, sketch the output voltage (b) Sketch the resulting voltage-transfer charac-
as a function of time. teristics (vout versus vin) and drain current ver-
9.3.5 A typical CMOS inverter is shown in Figure sus input voltage vin for the CMOS inverter.
Copyright OUP
PROBLEMS 443
+VCC Figure P9.2.12 TTL NAND gate.
R4
RB
T4
VA
T2 Vo
VB
VC
T1
T3
Figure P9.3.1 (a) n-channel JFET switch.

(b) Characteristics (transfer characteristics;
terminal characteristics and load line). (c) In-
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
put.
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Vi , V Figure P9.3.2 (a) Input. (b) JFET characteris-

tics.
1 2 3 4
t, ms
−5
(a)
iD, mA
10 vGS = 0 V
iD 9
−1 V
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
D 8
+
7 −2 V
iG = 0
6
G vDS
+ 5 −3 V
vGS 4
− − 3 −4 V
S
2
−5 V
1
vDS, V
0 2 4 6 8 10 12 14 16 18 20 22 24
(b)
9.3.6 Explain the principle of operation of the CMOS P9.3.7. Explain its operation and the approximate
transmission gate shown in Figure 9.3.6. behavior of transistors in CMOS logic.
9.3.7 Consider the CMOS NAND gate shown in Figure
Copyright OUP
PROBLEMS 445
+VDD
RD
Vo
D
G
Vi
(a)
iD
VDD
RD Saturation vGS = Von
iD
4V
3V
2V
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
vGS 1V
VT
vGS = VT
vDS
Vsat
Cutoff VDD
(b)
Vi
t
(c)
Figure P9.3.3 (a) n-channel enhancement MOSFET switch. (b) Characteristics (transfer characteristics; terminal
characteristics and load line). (c) Input.
Copyright OUP
vin , V Figure P9.3.4 Input voltage as a function of

time.
20
10
6
t, ms
0 1 2 3 4
VDD = 7 V Figure P9.3.5 (a) Typical CMOS inverter. (b) Characteristics

of T 1.
S2
T2 p-channel
MOSFET
D2
ID2
vin vout
ID1
D1
n-channel
T1
MOSFET
S1
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(a)
iD, mA
D
1.0 Ohmic or vGS = 7 V
iD
triode region
0.8
G Pinch-off or active region
vGS = 6 V
0.6
0.4
iS
vGS = 5 V
S 0.2 vGS = 4 V
0 vDS, V
2 4 6 8 10
vGS ≤ 3 V
(b)
Copyright OUP
PROBLEMS 447
VDD = 7 V Figure P9.3.7 CMOS NAND gate.
v1 T3 T4
vout
v2
T2
T1
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--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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PART
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
ENERGY SYSTEMS
THREE
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10 AC Power Systems
10.1 Introduction to Power Systems
10.2 Single- and Three-Phase Systems
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
10.3 Power Transmission and Distribution
10.5 Practical Application: A Case Study—The Great Blackout of 1965
Problems
Electric power is indispensable for any modern society. Our use and demand for electric power
grows annually at the rate of 2 to 3%; our need nearly doubles about every 25 to 35 years. We, in
the United States, have become so accustomed to reliable and accessible electric power that we
virtually take it for granted.
Even though energy appears in many different forms, the vast majority of all energy delivered
from one point to another across the country is handled by ac power systems. Transporting
electric energy most efficiently from place to place becomes extremely important. Electric power
generation, transmission, distribution, and utilization are the features of any practical power
system.
In the United States power is generated by many generating stations interconnected in an
overall network, known as the power grid, which spans the entire country. The bulk of the system
is privately owned, whereas a part of the network is owned federally and a part municipally. Some
utility companies in a given geographical area operate as power pools for reasons of economy
and reliability.
The principal source of energy comes from the burning of fossil fuels such as coal and oil
to generate steam, which drives steam turbines, which in turn drive electric generators. Other
important energy sources are hydroelectric and nuclear. In the former, electric generators are
driven by waterwheel (hydraulic) turbines near natural or human-made waterfalls; in the latter,
nuclear reactions generate heat to drive the steam-turbine–generator chain. There are also other
less widely used sources of energy such as geothermal sources, wind, sun, and tides.
In this chapter, to start with, an introduction to power systems will be presented. Then we
analyze three-phase systems, a topic that was covered in part in Chapter 4. Finally, the components
451
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452 AC POWER SYSTEMS
of an ac power network are identified, and topics related to power transmission and distribution
are introduced.
10.1 INTRODUCTION TO POWER SYSTEMS

Thomas A. Edison’s work in 1878 on the electric light led to the concept of a centrally located
power station with distributed electric power for lighting in a surrounding area. The opening
of the historic Pearl Street Station in New York City on September 4, 1882, with dc generators
(dynamos) driven by steam engines, marked the beginning of the electric utility industry. Edison’s
dc systems expanded with the development of three-wire 220-V dc systems. But as transmission
distances and loads continued to grow, voltage problems were encountered. With the advent
of William Stanley’s development of a commercially practical transformer in 1885, alternating
current became more attractive than direct current because of the ability to transmit power at high
voltage with corresponding lower current and lower line-voltage drops. The first single-phase ac
line (21 km at 4 kV) in the United States operated in 1889 between Oregon City and Portland.
Nikola Tesla’s work in 1888 on electric machines made evident the advantages of polyphase
over single-phase systems. The first three-phase line (12 km at 2.3 kV) in the United States
became operational in California during 1893. The three-phase induction motor conceived by
Tesla became the workhorse of the industry.
Most electric energy has been generated by steam-powered (accounting for about 85% of
U.S. generation) and by water-powered, or hydro, turbine plants (accounting for about 10% of
U.S. generation). Gas turbines are also used for short periods to meet peak loads. Steam plants
are fueled primarily by coal, gas, oil, and uranium. While coal is the most widely used fuel in
the United States, due to its abundance, nuclear units of 1280-MW steam-turbine capacity are
in service today. However, rising construction costs, licensing delays, and public concerns have
stopped the growth of nuclear capacity in the United States.
Other types of electric power generation are also prevalent, accounting for about 1% of
U.S. generation. These include wind-turbine generators, solar-cell arrays, tidal power plants, and
geothermal power plants, wherein energy in the form of steam or hot water is extracted from the
earth’s upper crust. Substantial research now under way shows nuclear fusion energy to be the
most promising technology for producing safe, pollution-free, and economical electric energy in
this century and beyond, since the needed fuel (deuterium) consumed in a nuclear fusion reaction
is present in seawater abundantly.
Today the two standard frequencies for the generation, transmission, and distribution of
electric power in the world are 60 Hz (in the United States, Canada, Japan, and Brazil) and 50 Hz
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(in Europe, the former Soviet Republics, South America except Brazil, India, and also Japan).
Relatively speaking, the 60-Hz power-system apparatus is generally smaller in size and lighter
in weight than the corresponding 50-Hz equipment with the same ratings. On the other hand,
transmission lines and transformers have lower reactances at 50 Hz than at 60 Hz.
Along with increases in load growth, there have been continuing increases in the size of
generating units and in steam temperatures and pressure, leading to savings in fuel costs and
overall operating costs. Ac transmission voltages in the United States have also been rising
steadily: 115, 138, 161, 230, 345, 500, and now 765 kV. Ultrahigh voltages (UHV) above 1000
kV are now being studied. Some of the reasons for increased transmission voltages are:
• Increases in transmission distance and capacity
• Smaller line-voltage drops
• Reduced line losses
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10.1 INTRODUCTION TO POWER SYSTEMS 453
• Reduced right-of-way requirements

• Lower capital and operating costs.
In association with ac transmission, there have been other significant developments:
• Suspension insulator
• High-speed relay system
• High-speed, extra-high-voltage (EHV) circuit breakers
• EHV surge arrester to protect from lightning strokes and other surges
• Communications via power-line carrier, microwave, and fiber optics
• Energy control centers with supervisory control and data acquisition (SCADA) and with
automatic generation control (AGC)
• Extensive use of microprocessors for various tasks.
Along with ac transmission in the United States, there have been modern high-voltage dc
(HVDC) transmission lines: the ±400-kV, 1360-km Pacific Intertie line between Oregon and
California in 1970 as well as four other HVDC lines up to 400 kV and five back-to-back ac–dc
links as of 1991. A total of 30 HVDC lines up to 533 kV are in place worldwide. For an HVDC line
interconnected with an ac system, solid-state converters at both ends of the dc line are needed to
operate as rectifiers and inverters. Studies in the United States have shown that overhead HVDC
transmission is economical for transmission distances longer than about 600 km. Also, HVDC
links seem to improve the overall system stability.
An interconnected system (in contrast with isolated systems) has many advantages:
• Better maintenance of continuity of service
• Increase in reliability and improved economy
• Reduction of reserve requirements
• Scheduling power transfers taking advantage of energy-cost differences in respective areas,
load diversity, and seasonal conditions
• Shared ownership of larger and more efficient generating units.
Some of the disadvantages of interconnected operations are:
• Increased fault currents during short circuits
• Occasional domino effect leading to a regional blackout (such as the one that occurred
in 1965 in the northern United States) due to an initial disturbance in some part of the
interconnected grid system.
Present and Future Trends

According to the Edison Electric Institute, electricity’s share of U.S. primary energy was almost
36% in 1989, and it is likely to reach 46% by the year 2010. The growth rate in the use of electric
energy in the United States is projected to increase by about 2.4% per year for the near future,
in spite of conservation practices, more efficient use of electricity, and a slackening population
growth. One should also be aware of large growth of power systems internationally.
Because of the large amount of U.S. coal reserves, there is the continuing shift away from
the use of gas and oil and toward increasing use of coal. Unless the construction time and cost
per kW can be reduced significantly, no new nuclear units will be commissioned. Also, safety
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concerns seem to demand inherently safe reactor designs with standardized, modular construction
of nuclear units. Since the major U.S. hydroelectric sites (except in Alaska) have been fully
developed, one can foresee a trend for continuing percentage decline in hydroelectric energy
generation.
By the year 2000, the total U.S. generating capacity has reached 817 GW (1 GW = 1000 MW)
and continues to grow. Current lead times of about a decade for the construction and licensing of
large coal-fired units may cause insufficient reserve margins in some regions of the United States.
As of 1989, U.S. transmission systems consisted of about 146,600 circuit-miles of high-
voltage transmission. During the 1990s, additions have totalled up to 13,350 circuit-miles, which
include 230-kV, 345-kV, and 500-kV lines. Because of the right-of-way costs, the possibility of
six-phase transmission (instead of the current three-phase transmission) is being looked into.
U.S. distribution-network construction is expected to increase over the next decade. The older
2.4-, 4.1-, and 5-kV distribution systems are being converted to 12 or 15 kV. Higher distribution
voltages such as 25 and 34.5 kV are also contemplated.
Recently some concern has surfaced about the effect of electromagnetic waves on the human
and animal environment. The result of this remains to be seen.
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Computers in Power Systems

The control and stability of any electric power system is indeed extremely important, in particular
when a system is expected to maintain uninterrupted continuity of service within set limits
of frequency and voltage, and to guarantee reliability of the system. Digital computers and
microprocessors, along with highly developed software programs, have made their way into
planning, designing, operating, and maintaining complex interconnected power systems. A large
volume of network data must also be acquired and accurately processed. Digital computer
programs in power-system engineering include power-flow, stability, short-circuit, and transients
programs.
For a network under steady-state operating conditions, power-flow programs compute the
voltage magnitudes, phase angles, and transmission-line power flows. Today’s computers are
capable of handling networks with more than 2000 buses (nodes) and 2500 transmission lines
in less than 1 minute power-flow solutions. Interactive power-flow programs have also been
developed along with CRT displays.
Stability programs are used to analyze power systems under various disturbances. Short-
circuit programs compute fault currents and voltages under various fault conditions. These, in
turn, will help in circuit-breaker selection, relay coordination, and overall system protection.
Transients programs yield the magnitudes and shapes of transient overvoltages and currents
that may result from lightning strikes and other surges on the system. Based on the results of such
studies, insulation coordination and surge-arrester selection are configured.
Planning and Research

Energy research worldwide is assuming top priority, in particular because of economic, en-
vironmental, and resource constraints. DOE (Department of Energy) was established in the
United States in 1977. A major private utility sponsored energy research organization, EPRI
(Electric Power Research Institute) in Palo Alto, California, has been in existence since 1972.
In addition, large utility companies, such as AEP (American Electric Power), have their own
research programs.
The major goals for the future are:
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10.2 SINGLE- AND THREE-PHASE SYSTEMS 455
• New primary resources (such as nuclear fusion and solar energy) for electric bulk power
generation
• Development of better means of generation (such as superconducting generators) and
transmission (such as six-phase)
• Emphasis on energy conservation (better utilization of electricity with less waste)
• Electric-energy storage facilities such as pumped storage, compressed gas, storage batteries,
and superconducting magnetic coils.
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10.2 SINGLE- AND THREE-PHASE SYSTEMS
It would be very helpful if the reader would review Section 3.1 on sinusoidal steady-state phasor
analysis and Chapter 4 on three-phase circuits before studying this section.
Ac power has significant practical advantages over dc power in generation, transmission,
and distribution. One major drawback of the single-phase circuit is the oscillatory nature of the
instantaneous power flow p(t) as seen in Equation (3.1.36). The consequent shaft vibration and
noise in single-phase machinery are rather undesirable. A three-phase circuit, on the other hand,
under balanced conditions has constant, nonpulsating (time invariant), instantaneous power, as
seen from Equation (4.2.13); the pulsating strain on generating and load equipment is eliminated.
Also for power transmission, a balanced three-phase system delivers more watts per kilogram
of conductor than an equivalent single-phase system. For these reasons, almost all bulk electric
power generation and consumption take place in three-phase systems.
The majority of three-phase systems are four-wire, wye-connected systems, in which a
grounded neutral conductor is used. Some three-phase systems such as delta-connected and three-
wire wye-connected systems do not have a neutral conductor. Because the neutral current is nearly
zero under normal operating conditions, neutral conductors for transmission lines are typically
smaller in size and current-carrying capacity than the phase conductors. Thus, the cost of a
neutral conductor is substantially less than that of a phase conductor. The capital and operating
costs of three-phase transmission and distribution systems, with or without neutral conductors,
are comparatively much less than those of separate single-phase systems.
Ratings of three-phase equipment, such as generators, motors, transformers, and transmission
lines, are usually given as total three-phase real power in MW, or as total three-phase apparent
power in MVA, and as line-to-line voltage in kV.
Power
The essential concepts related to power have been presented in Sections 3.1 and 4.2. However,
for better clarity and understanding, those concepts are revisited in a slightly different form.
The complex power S̄ in a single-phase system is the complex sum of the real (P) and reactive
(Q) power, expressed as follows:
S̄ = P + j Q = V̄ I¯∗ = I¯ I¯∗ Z̄ = I 2 Z θZ = V I θV − θI (10.2.1)
where θV is the angle associated with V̄ (with respect to any chosen reference), θI is the angle
associated with I¯ (with respect to the same reference chosen), θZ is the impedance angle, V̄ is
the rms voltage phasor, I¯ is the rms current phasor, and Z̄ = R ± j X is the complex impedance
with a magnitude of Z. Note that ∗ stands for complex conjugate. If the voltage phasor V̄ itself is
taken to be the reference, θV = 0 and θI may be replaced by θ without any subscript.
The power factor PF is given by the ratio of the real power P (expressed in watts) to the
apparent power S = P 2 + Q2 expressed in volt-amperes,
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PF = P /S = cos θ (10.2.2)
where θ = tan−1 Q/P . Inductive loads cause current to lag voltage and are referred to as lagging
power factor loads. Conversely, capacitive loads cause current to lead voltage and are referred to
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as leading power factor loads.
For a case with lagging power factor, Figure 10.2.1(a) shows voltage and current phasors;
Figure 10.2.1(b) depicts the real, reactive, and apparent powers; and Figure 10.2.1(c) gives the
power triangle. The corresponding diagrams with leading power factor are shown in Figure
10.2.2. Loads on the electric power system are generally inductive, which will cause the phase
current to lag the corresponding applied phase voltage. The real power component represents
the components of voltage and current that are in phase, whereas the reactive power component
represents the components of voltage and current that are in quadrature (that is, 90° out of phase).
The convention used for positive power flow is described with the help of Figure 10.2.3, in
which Figure 10.2.3 (a) applies to a generator (source), and Figure 10.2.3 (b) applies to a load
(sink).
The power expressions for the three-phase case, in terms of the line quantities, are (see
Section 3.2)
S̄3φ = P3φ + j Q3φ (10.2.3)
Figure 10.2.1 Lagging power factor. (a) Voltage and current

Quadrant II Quadrant I phasors. (b) Real, reactive, and apparent powers. (c) Power
triangle.
V
Reference
θ (Negative)
I (Lagging)
Quadrant III Quadrant IV
(a)
+Q
Quadrant II Quadrant I
S
Qlagging PF
θ (Positive)
−P +P
Plagging PF
S,VA
Q,VAR
Quadrant III Quadrant IV θ
−Q P,W
(b) (c)
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Figure 10.2.2 Leading power factor. (a) Voltage and current

Quadrant II Quadrant I phasors. (b) Real, reactive, and apparent powers. (c) Power
I (leading) triangle.
θ (positive)
V
Reference
(a)
+Q
Quadrant II Quadrant I
Pleading PF
−P +P P,W
θ (negative)
θ
Qleading PF
Q,VAR
S,VA
S
−Q
(b) (c)
where
√
P3φ = 3 VL IL cos θP (10.2.4)
√
Q3φ = 3 VL IL sin θP (10.2.5)
√
S3φ = 3 VL IL = P3φ 2
+ Q23φ (10.2.6)
+ S = VI* = P + jQ + S = VI* = P + jQ
I I
V V
− −
(a) (b)
Figure 10.2.3 Convention for positive power flow. (a) Generator case. If P is positive, then real power is
delivered. If Q is positive, then reactive power is delivered. If P is negative, then real power is absorbed. If
Q is negative, then reactive power is absorbed. (b) Load case. If P is positive, then real power is absorbed. If
Q is positive, then reactive power is absorbed. If P is negative, then real power is delivered. If Q is negative,
then reactive power is delivered.
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in which θP is the phase angle between the voltage and the current of any particular phase, and
cos θP is the power factor.
Under most normal operating conditions, the various components of the three-phase system
are characterized by complete phase symmetry. If such phase symmetry is assured throughout
the power system, it is desirable to simplify the analytical efforts to a great extent by the use of
per-phase analysis. Also recall that three-phase systems are most often represented by single-line
(one-line) diagrams.
The energy E associated with the instantaneous power over a period of time T seconds is
given by
E = PT (10.2.7)
where E is the energy in joules that is transferred during the interval, and P is the average value
of the real-power component in joules per second. Note that the reactive-power component does
not contribute to the energy that is dissipated in the load. The energy associated with the reactive
power component is transferred between the electric fields (which result from the application of
the sinusoidal voltage between the phase conductors and ground) and the magnetic fields (which
result from the flow of sinusoidal current through the phase conductors).
Many industrial loads have lagging power factors. Electric utilities may assess penalties for
the delivery of reactive power when the power factor of the customer’s load is below a minimum
level, such as 90%. Capacitors are often used in conjunction with such loads for the purpose
of power factor correction or improvement. An appropriate capacitor connected in parallel with
an inductive load cancels out the reactive power and the combined load may have unity power
factor, thereby minimizing the current drawn from the source. For problems and examples on this
subject, one may also refer to Sections 3.1 and 4.2.
EXAMPLE 10.2.1
A 60-Hz, three-phase motor draws 25 kVA at 0.707 lagging power factor from a 220-V source.
It is desired to improve the power factor to 0.9 lagging by connecting a capacitor bank across the
terminals of the motor.
(a) Determine the line current before and after the addition of the capacitor bank.
(b) Specify the required kVA (kVAR) rating of the capacitor bank. Also sketch a power
triangle depicting the power factor correction by using capacitors.
(c) If the motor and the capacitor bank are wye-connected in parallel, find the capacitance
per phase of the capacitor bank assuming that it is balanced.
(d) How would the result of part (c) change if the motor and the capacitor bank were to be
delta-connected in parallel?
Solution
The real and reactive powers of the load (motor) are:

PM = 25 × 0.707 = 17.68 kW
QM = 25 sin(cos−1 0.707) = 17.68 kVAR
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(a) The line current of the motor, before the addition of the capacitor bank, is
S3φ 25,000
IM = √ =√ = 65.6A
3 VL 3 × 220
After the addition, the new value of line current is

PM 17,680
Icorr = √ =√ = 51.55A
3 VL PFcorr 3 × 220 × 0.9
(b) The corrected new value of reactive power is
Qcorr = PM tan(cos−1 0.9) = 17.68 tan 25.8° = 8.56 kVAR
The kVA (kVAR ) rating of the capacitor bank needed to improve the power factor from
0.707 to 0.9 lagging is then found as
Qcap = Qcorr − QM = 8.56 − 17.68 = −9.12 kVAR
The power triangle is shown in Figure E10.2.1.
Figure E10.2.1 Power triangle
Qcap = 9.12 kVAR

SM = 25 kVA
Scorr = 19.64 QM = 17.68 kVAR
kVA Q = 8.56 kVAR

45° corr
25.8°
PM = 17.68 kW
(c) Per-phase capacitive kVAR = 9.12/3 = 3.04 kVAR. With wye connection,
√ 2
2
VLN 220/ 3
= = 3.04 × 103
XC XC
or
√ 2
220/ 3
XC = = 5.31 -
3.04 × 103
Hence,
1
C= = 500 µF
2π × 60 × 5.31
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(d) With delta connection,

VL2 2202
= = 3.04 × 103
XC XC
or
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2202
XC = = 15.92 -
3.04 × 103
Hence,
1
C= = 166.6 µF
2π × 60 × 15.92
Note that Z? = 3ZY (see Figure 4.2.1), or C? = (1Ⲑ3)CY , as it should be for a balanced case.
10.3 POWER TRANSMISSION AND DISTRIBUTION

The structure of a power system can be divided into generation (G), transmission, (T), and
distribution (D) facilities, as shown in Figure 10.3.1. An ac three-phase generating system provides
the electric energy; this energy is transported over a transmission network, designed to carry power
at high or extrahigh voltages over long distances from generators to bulk power substations and
major load points; the subtransmission network is a medium to high-voltage network whose
purpose is to transport power over shorter distances from bulk power substations to distribution
substations. The transmission and subtransmission systems are meshed networks with multiple-
path structure so that more than one path exists from one point to another to increase the reliability
of the transmission system.
The transmission system, in general, consists of overhead transmission lines (on transmission
towers), transformers to step up or step down voltage levels, substations, and various protective
devices such as circuit breakers, relays, and communication and control mechanisms.
Figure 10.3.2 shows a typical electric-power distribution system and its components. Be-
low the subtransmission level, starting with the distribution substation, the distribution system
usually consists of distribution transformers, primary distribution lines or main feeders, lateral
To other
pool members
Transformer
Bus
G1 End user
G2
End user
End user End user
To other
pool members
Generating Transmission Subtransmission Primary Subtransmission
system system system distribution distribution
(13.8–24 kV) (138–765 kV) (34–138 kV) (4–34 kV) (120–600 v)
Figure 10.3.1 Typical power-system structure.

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10.3 POWER TRANSMISSION AND DISTRIBUTION 461
feeders, distribution transformers, secondary distribution circuits, and customers’ connections

with metering. Depending on the size of their power demand, customers may be connected to
the transmission system, the subtransmission system, or the primary or secondary distribution
circuit.
In central business districts of large urban areas, the primary distribution circuits consist of
underground cables which are used to interconnect the distribution transformers in an electric
network. With this exception, the primary system is most often radial. However, for additional
reliability and backup capability, a loop-radial configuration is frequently used. The main feeder
is looped through the load area and brought back to the substation, and the two ends of the
loop are connected to the substation by two separate circuit breakers. For normal operation,
selected sectionalizing switches are opened so as to form a radial configuration. Under fault
conditions, the faulted section is isolated and the rest of the loop is used to supply the unaffected
customers.
Most residences and small buildings are supplied with power by means of single-phase,
three-wire service, as illustrated in Figure 10.3.3. A distribution transformer is located on a power
pole or underground, near the residential customer. Inside residences, the 220-V supply, being
available between the two “hot” wires, is used for major appliances such as dryers, ranges, and
ovens. The 110-V loads up to 20 to 40 A are connected between the ground wire and either “hot”
wire, while nearly balancing the loads on the two “hot” wires. Each of these circuits, protected by
its own fuse or circuit breaker, supplies lighting loads and/or convenience outlets. In the wiring
of residential and commercial buildings, safety considerations are of paramount importance, the
principal hazards being fire and electric shock. Residential wiring is also discussed in Section 4.4.
Distribution substation
Circuit
breaker Substation
transformers
Circuit breakers
Primary
circuits
or
main feeders
Laterals
Distribution
transformers
Secondary
circuits
Service entry
(1 to 10 residential customers)
Figure 10.3.2 Typical electric power distribution system.
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( )
Figure 10.3.3 Single-phase, three-wire residential wiring circuit.
Power-System Loads
Figure 10.3.4 represents a one-line (single-line) diagram of a part of a typical three-phase power
system. Notice the symbols that are used for generators, transformers, buses, lines, and loads.
Recall that a bus is a nodal point.
Let us now consider the addition of a load bus to the operating power system. Service
classifications assigned by the electric utilities include residential, commercial, light industrial,
and heavy industrial loads, as well as municipal electric company loads. Let us prepare a load-
bus specification, which is a summary of the service requirements that must be provided by the
electric utility. Referring to the simple model of Figure 10.3.5, as an example, let the total new
load connected to the system be 220 MVA at 0.8 power factor lagging; let the service be provided
at the subtransmission level from a radial 115-kV circuit; let the 115-kV transmission line have
a per-phase series impedance of 3 + j 8 -.
The load-bus data (specifications), transmission line data, and source-bus data are given in
Tables 10.3.1, 10.3.2, and 10.3.3, respectively. The reader is encouraged to work out the details.
Looking at the load-bus data, the amount of reactive power that is needed to provide 100%
compensation is 120 MVAR. Let us then add a three-phase shunt capacitor bank with a nominal
voltage rating of 115 kV and a reactive power rating of 120 MVAR. The per-phase reactance of
the bank can be computed as X = V 2 /Q = 1152 /120 = 110.2 -. The load-bus data with power
factor correction are given in Table 10.3.4.
The transmission-system efficiency is defined as the ratio of the real power delivered to the
receiving-end bus to the real power transferred from the sending-end bus. This efficiency, which
is a measure of the real-power loss in the transmission line, comes out as 94.7% without power
factor correction, and 96.5% with power factor correction.
The transmission-line voltage regulation (TLVR) is the ratio of the per-phase voltage drop
between the sending-end and receiving-end buses to the receiving-end per-phase voltage (or
nominal system per-phase voltage). It can also be expressed as
VRNL − VRFL
%TLVR = × 100 (10.3.1)
VRFL
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G1 G2 Generator
Transformer
1 Bus numbering 2 Bus

Circuit breaker
L1
L2
To bus 6 Transmission line
3
L3 L6 Line numbering
Load
L4 L5
4 5
L7
Tie-line connection
with neighboring
system
To bus 7
Figure 10.3.4 One-line (single-line) diagram of part of a typical three-phase power system.
SS = PS + jQS SR = PR + jQR Figure 10.3.5 Simple model of part of

an operating power system.
Load
VS Line impedance VR
Source bus Load bus
(sending end) (recieving end)
where subscript R denotes receiving end, NL indicates no-load, and FL stands for full-load. The
TLVR for our example can be seen to be 12.8% prior to power factor improvement, and 10.2%
after power factor improvement.
The two components of electric service are demand and energy. Demand is the maximum
level of real power which the electric utility must supply to satisfy the load requirements of its
customers. Energy is the cumulative use of electric power over a period of time. The demand
component of the electric-rate structure represents the capital investment needed by the utility
to provide the generation, transmission, and distribution facilities in order to meet the maximum
customer demand. The energy component represents the operating costs, which include fuel and
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maintenance that must be provided to meet the demand requirements over a period of time.
The load factor is the ratio of the actual energy usage to the rated maximum energy usage over
a given period. A low load factor is indicative of a substantial period during which the capacity
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TABLE 10.3.1 Load-Bus Data
Quantity Symbol Value
Voltage V 115 kV
Current I 1 kA
Apparent power S 220 MVA
Real power P 160 MW
Reactive power Q 120 MVAR
Power factor cos θ 0.8 lagging
Phase angle θ 36.9°
Load impedance Z 66.1 -
Load resistance R 52.9 -
Load reactance XL 39.7 -
TABLE 10.3.2 Transmission-Line Data
Resistance R 3 -
Inductive reactance XL 8 -
Series impedance Z 8.5 -
Series impedance angle θ 69.4°
Real power loss Ploss 9 MW
Reactive power loss Qloss 24 MVAR
Voltage drop Vdrop 8.5 kV
TABLE 10.3.3 Source-Bus Data
Quantity Load Bus Line Source Bus
Voltage 115 8.5 127.7 kV

Real power 160 9 169 MW
Reactive power 120 24 144 MVAR
Apparent power 200 — 222 MVA
Angle 36.9° — 40.4°
TABLE 10.3.4 Load-Bus Data with

Power-Factor Correction
Voltage V 115 kV
Current I 0.8 kA
Apparent power S 160 MVA
Real power P 160 MW
Reactive power Q 0 MVAR
Power factor cos θ 1
Phase angle θ 0°
Load impedance Z 82.7 -
Load resistance R 82.7 -
Load reactance XL 0 -
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of the system is underutilized. Utilities often define load periods in terms of on-peak and off-peak
hours. In order to level the demand by diverting a portion of the energy usage from the on-peak
to the off-peak periods, economic incentives (such as lower electric rates for the sale of off-
peak energy) are generally offered.
EXAMPLE 10.3.1
A three-phase, 34.5-kV, 60-Hz, 40-km transmission line has a per-phase series impedance of
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0.2+j 0.5 -/km. The load at the receiving end absorbs 10 MVA at 33 kV. Calculate the following:
(a) Sending-end voltage at 0.9 PF lagging.
(b) Sending-end voltage at 0.9 PF leading.
(c) Transmission system efficiency and transmission-line voltage regulation corresponding
to cases (a) and (b).
Solution
The per-phase model of the transmission line is shown in Figure E10.3.1.
IS = IR IR
+
+
R + jX
33
VRLN = − ∠0° kV
VS LN 8 + j20 Ω Load
√3
−
−
Figure E10.3.1 Per-phase model of transmission line (with only series impedance).
33,000
V̄R = √ 0° = 19,052 0° V
3
10 × 106
(a) I¯R = √ − cos−1 0.9 = 175 − 25.8° A
3 × 33 × 103
V̄S LN = 19,052 0° + (175 − 25.8°)(8 + j 20) = 21, 983 6.6°VLN
√
VS LL = 21.983 3 = 38.1 kV (line - to - line)
10 × 106
(b) I¯R = √ + cos−1 0.9 = 175 + 25.8° A
3 × 33 × 10 3
V̄S LN = 19,052 0° + (175 + 25 .8°)(8 + j 20) = 19,162 11.3° VLN

√
VS LL = 19.162 3 = 33.2 kV (line - to - line)
(c) (i) 0.9 PF lagging:
PR = 10 × 0.9 = 9 MW
√
PS = 3 × 38.1 × 0.175 cos(25.8 + 6.6)° = 9.75 MW
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9
η= × 100 = 92.3%
9.75
VR NL − VR FL 38.1 − 33
TLVR = × 100 = × 100 = 15.45%
VR FL 33
Note: If there were no load, the sending-end voltage would appear at the receiving
end.
(ii) 0.9 PF leading:
PR = 10 × 0.9 = 9 MW
√
PS = 3 × 33.2 × 0.175 cos(25.8 − 11.3)° = 9.74 MW
9
η= × 100 = 92.4%
9.74
33.2 − 33
TLVR = × 100 = 0.61%
33

• Past, present, and future trends of power systems in the United States.
• Three-phase power calculations and power factor improvement.
• Basic notions of power transmission and distribution.
• Working with load-bus data, transmission-line data, and source-bus data.
• Simple transmission-line model and its circuit calculations.
The Great Blackout of 1965

In the United States, electric utilities grew first as isolated systems. Gradually, however, neigh-
boring utilities began to interconnect, which allowed utility companies to draw upon each others’
generation reserves during time of need and to schedule power transfers that take advantage
of energy-cost differences. Although overall system reliability and economy have improved
dramatically through interconnection, there is a remote possibility that an initial disturbance
may lead to instability and a regional blackout.
The worst power failure in history occurred on Tuesday evening, November 9, 1965. At
the height of the rush hour, complete darkness descended, and practically everything came to a
standstill over an area of 83,000 square miles. About 30 million people were affected in eight
states and part of Canada. The system involved was the Canadian–United States eastern power
complex (CANUSE).
Many guesses were offered as to the cause of the blackout, but most were far from correct.
At first, little hope was held out for pinpointing the exact reason for the failure within a short
time. However, on November 15 it was announced that the cause had been found. The failure
was attributed to a faulty relay at Sir Adam Beck Plant no. 2 at Queenston, Ontario (see Figure
R. McCaw, “The Great Blackout,” Power Engineering, Dec. 1965.
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10.5.1). This plant is part of the Ontario Hydro-Electric System on the Niagara River. Six lines
run into Ontario from the Beck plant, and the line controlled by the faulty relay was carrying 300
MW. Failure of the relay dumped this load onto the other five lines. Even though these lines were
not overloaded, all five tripped out.
Total power flow on these lines had been 1600 MW into Ontario, including 500 MW being
imported from the Power Authority of the State of New York. All this power was suddenly
dumped on the New York system. The resultant surge knocked out the Power Authority’s
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main east–west transmission line and shut down seven units that had been feeding the north-
eastern grid. The resulting drain on systems to the south and east caused the whole system to
collapse.
New York City, for example, had been drawing about 300 MW from the network just before
the failure. Loss of the upstate plants caused a sudden reversal of flow and placed a heavy drain
on the City generators. The load was much greater than the plants still in service could supply,
and the result was a complete collapse. Automatic equipment shut down the units to protect them
from damage.
After the total failure the individual systems started up in sections, and most power was
restored by a little after midnight. However, Manhattan, with the greatest concentration of load,
was not fully restored unitl after six o’clock the following morning.
Only a rare combination of faults, however, will result in a cascading of tripouts and a
complete shutdown over an entire region. In order to avoid such large blackouts, stronger grids
have been planned and various techniques developed to operate large interconnected networks in
parallel with a high degree of operating stability, and with increasing dependence on automated
Figure 10.5.1 Area affected by the blackout of 1965.
Copyright OUP
controls. Pumped storage plants, which represent a large reserve that can be put into operation on
short notice, can help the situation.
The great blackout of 1965 had indeed been a sobering experience and possibly a needed
warning to reexamine some of our policies and plans. The warning will not have been wasted if
we learn from it how to build a more reliable grid to suppply all the power that is needed in the
years ahead. After all, our whole economy is almost completely dependent on electric power.
PROBLEMS
10.2.1 Two ideal voltage sources are connected to each lagging power factor of 0.80 and the other draws
other through a feeder with impedance Z̄ = 6 kW at a lagging power factor of 0.90. Compute
1.5 + j 6 -, as shown in Figure P10.2.1. Let the source current.
Ē1 = 120 0° V and Ē2 = 110 45°. 10.2.5 A three-phase power system consists of a wye-
(a) Determine the real power of each machine, connected ideal generator, supplying a wye-con-
and state whether the machine is supplying nected balanced load through a three-phase
or absorbing real power. feeder. The load has Z̄L = 20 30°-/
(b) Compute the reactive power of each ma- phase, and the feeder has an impedance Z̄fdr =
chine, and state whether each machine is 1.5 75° -/phase. If the terminal voltage of the
delivering or receiving reactive power. load is 4.16 kV, determine:
(c) Find the real and reactive power associated (a) The terminal voltage of the generator.
with the feeder impedance, and state whether (b) The line current supplied by the generator.
it is supplied or absorbed.
10.2.6 A 345-kV, 60-Hz, three-phase transmission line
*10.2.2 If the impedance between the voltage sources in delivers 600 MVA at 0.866 power factor lagging
Problem 10.2.1 is changed to Z̄ = 1.5 − j 6 -, to a three-phase load connected to its receiving-
redo parts (a) through (c) of Problem 10.2.1. end terminals. Assuming that the voltage at the
10.2.3 A single-phase industrial plant consists of two receiving end is 345 kV and the load is wye-
loads in parallel: connected, find the following:
P1 = 48kW PF1 = 0.60 lagging (a) Complex load impedance per phase Z̄L /ph.
P2 = 24kW PF2 = 0.96 leading (b) Line and phase currents.
It is operated from a 500-V, 60-Hz source. An (c) Real and reactive powers per phase.
additional capacitor C is added in parallel to (d) Total three-phase real and reactive powers.
improve the plant’s overall power factor to unity.
*10.2.7 A three-phase load, connected to a 440-V bus,
Determine the value of C in µF. Also sketch the
draws 120 kW at a power factor of 0.85 lagging.
power triangles before and after the addition of
In parallel with this load is a three-phase capac-
C, and find the overall current drawn from the
itor bank that is rated 50 kVAR . Determine the
supply.
resultant line current and power factor.
10.2.4 A 230-V, single-phase, 60-Hz source supplies
two loads in parallel. One draws 10 kVA at a
z Figure P10.2.1
I
+ E1 + E2
− −
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PROBLEMS 469
10.2.8 A balanced three-phase, wye-connected, 2400- (a) The sending-end voltage for a load power
V, 60-Hz source supplies two balanced wye- factor of 0.9 lagging.
connected loads in parallel. The first draws 15 (b) The sending-end voltage for a load power
kVA at 0.8 power factor lagging, and the second factor of 0.9 leading.
needs 20 kW at 0.9 power factor leading. Com-
pute the following: (c) The transmission system efficiency for cases
(a) and (b).
(a) Current supplied by the source.
(d) The transmission-line voltage regulation
(b) Total real and reactive power drawn by the
(TLVR) for cases (a) and (b).
combined load.
10.3.3 It is sometimes convenient to represent a trans-
(c) Overall power factor. mission line by a two-port network, as shown in
10.2.9 A three-phase, 60-Hz substation bus supplies two Figure P10.3.3. The relations between sending-
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wye-connected loads that are connected in par- end and receiving-end quantities are given by
allel through a three-phase feeder that has a per-
V̄S = Ā V̄R + B̄ I¯R and I¯S = C̄ V̄R + D̄ I¯R ,
phase impedance of 0.5 + j 2 -. Load 1 draws
50 kW at 0.866 lagging PF, and load 2 draws 36 in which the generally complex parameters Ā,
kVA at 0.9 leading PF. If the line-to-line voltage B̄, C̄, and D̄ depend on the transmission-line
at the load terminals is 460 V, find the following: models. For the model that includes only the
(a) Total line current flowing through the feeder. series impedance Z̄ of the transmission line, find
the parameters Ā, B̄, C̄, and D̄ and specify their
(b) Per-phase impedance of each load. units. Also evaluate (Ā D̄ − B̄ C̄).
(c) Line-to-line voltage at the substation bus. 10.3.4 For a transmission-line model that includes only
(d) Total real and reactive power delivered by the series impedance Z̄, sketch phasor diagrams
the bus. for:
10.2.10 A balanced delta-connected load has a per-phase (a) Lagging power factor load.
impedance of 45 60° -. It is connected to a
(b) Leading power factor load.
three-phase, 208-V, 60-Hz supply by a three-
phase feeder that has a per-phase impedance of 10.3.5 In terms of the parameters Ā, B̄, C̄, and D̄ intro-
1.2 + j 1.6 -. duced in Problem 10.3.3, find an expression for
V̄R at no load in terms of V̄S and the parameters.
(a) Determine the line-to-line voltage at the load
terminals. *10.3.6 Consider an upgrade of a three-phase transmis-
sion system in which the operating line-to-line
(b) If a delta-connected capacitor bank, with a
voltage is doubled, and the phase or line currents
per-phase reactance of 60-, is connected in
are reduced to one-half the previous value, for the
parallel with the load at its terminals, com-
same level of apparent power transfer. Discuss
pute the resulting line-to-line voltage at the
the consequent effects on the real and reactive
load terminals.
power losses, and on the voltage drop across the
*10.3.1 Consider a lossless transmission line with only a series impedance of the transmission system.
series reactance X, as shown in Figure P10.3.1.
10.3.7 Justify the entries made in Tables 10.3.1, 10.3.2,
(a) Find an expression for the real power transfer and 10.3.3 for load-bus data, transmission-line
capacity of the transmission system. data, and source-bus data, respectively, for the
(b) What is Pmax (the theoretical steady-state example considered in the text.
limit of a lossless line), which is the max- 10.3.8 Justify the entries made in Table 10.3.4 for load-
imum power that the line can deliver? bus data with power factor correction, and dis-
(c) How could the same expressions be used for cuss the effects of power factor correction on
a three-phase transmission line? Ploss , Qloss , and Vdrop of the transmission line.
10.3.2 A 20-km, 34.5-kV, 60-Hz, three-phase transmis- 10.3.9 Check the figures given in the text (for the ex-
sion line has a per-phase series impedance of ample considered) regarding the transmission-
Z̄ = 0.19 + j 0.34 -/km. The load at the receiv- system efficiencies and TLVR for the two cases,
ing end absorbs 10 MVA at 33 kV. Calculate: with and without power factor correction.
Copyright OUP
+ + Figure P10.3.1 Simple model of loss-

IS
Z = jX
IR less transmission line.
VS = VS ∠δ VR = VR ∠0°
− −
IS IR Figure P10.3.3
+ +
VS Two-port VR
network
− −
Sending end Receiving end
√
10.3.10 On a√per-phase basis, let v = 2 V cos ωt and (a) The voltage, current, and power factor at the
i= 2 I cos (ωt − θ ). sending end of the line.
(b) The voltage regulation and efficiency of the
(a) Express the instantaneous power s(t) in terms line.
of real power P and reactive power Q.
10.3.12 A three-phase, 60-Hz transmission line has a total
(b) Now consider the energy E associated with series impedance of 22.86 62.3° - per phase. It
the instantaneous power and show that E = delivers 2.5 MW at 13.8 kV to a load connected
Pt, where t is the duration of the time interval to its receiving end. Compute the sending-end
in seconds. voltage, current, real power, and reactive power
for the following conditions:
10.3.11 A 60-Hz, three-phase transmission line has a total (a) 0.8 power factor lagging.
per-phase series impedance of 35 + j 140 -. If it
(b) Unity power factor.
delivers 40 MW at 220 kV and 0.9 power factor
lagging, find: (c) 0.9 power factor leading.
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11 Magnetic Circuits and Transformers
11.1 Magnetic Materials
11.2 Magnetic Circuits
11.3 Transformer Equivalent Circuits
11.4 Transformer Performance
11.5 Three-Phase Transformers
11.6 Autotransformers
11.8 Practical Application: A Case Study—Magnetic Bearings for Space Technology
Problems
A basic understanding of electromagnetism is essential to the study of electrical engineering

because it is the key to the operation of many electric apparatus found in industry and at home.
Electric systems that generate, convert, or control huge amounts of energy almost always involve
devices whose operation depends on magnetic phenomena. Thus, we focus our attention here
on magnetic aspects as related to electric-power engineering. In this chapter we shall proceed
from introductory magnetic-circuit concepts to relatively simple magnetic structures and then to
a consideration of transformers.
The magnetic material determines the size of the equipment, its capabilities, and the lim-
itations on its performance. The transformer, although not an energy-conversion device, is an
important auxiliary in the transfer and conversion of electric energy. Practically all transformers
and electric machinery utilize magnetic material for shaping the magnetic fields which act as the
medium for transferring and converting energy. Transformers are found in various applications,
such as radio, television, and electric power transmission and distribution circuits. Other devices,
such as circuit breakers, automatic switches, and relays, also require the presence of a confined
magnetic field for their proper operation.
471
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472 MAGNETIC CIRCUITS AND TRANSFORMERS
11.1 MAGNETIC MATERIALS

For magnetic material media, the magnetic flux density B, expressed in tesla (T) or Wb/m2, and
the field intensity H, expressed in A/m or ampere-turns per meter (At/m), are related through the
relationship
B = µH (11.1.1)
where µ stands for the permeability of the material expressed in henrys per meter (H/m). The free-
space permeability µ0 is a constant given by 4π × 10−7 H/m in the SI system of units. The same
value holds good for air as well as for any nonmagnetic material. For a linear magnetic material
which exhibits a straight-line relationship between B and H, the permeability is a constant given
by the slope of the linear B–H characteristic, and it is related to the free-space permeability as
µ = µr µ0 (11.1.2)
where µr is the relative permeability, which is a dimensionless constant. If the B–H characteristic
is nonlinear, as with a number of common magnetic materials, then the permeability varies as a
function of the magnetic induction. The variation of B with H is depicted by the saturation curve
of Figure 11.1.1, in which the slope of the curve clearly depends upon the operating flux density,
as classified for convenience into regions I, II, and III.
There are several material classifications with their distinguishing characteristics. Ferromag-
netic materials, for which µr % 1, exhibit a high degree of magnetizability and are generally
subdivided into hard and soft materials. Soft ferromagnetic materials include most of the steels
and iron, whereas hard ferromagnetic materials include the permanent-magnet materials such as
alnicos and alloys of cobalt with a rare-earth element such as samarium. Ferrimagnetic materials
are ferrites composed of iron oxides, subdivided into hard and soft categories. Ferrofluids (mag-
netic fluids with iron-oxide particles suspended) and amorphous magnetic (soft ferromagnetic)
materials were also developed later. Typical magnetic characteristics of some core materials are
Core (Iron) Losses

Iron-core losses are usually divided into two components: hysteresis loss and eddy-current loss.
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The former is proportional to the area enclosed by the hysteresis loop, shown in Figure 11.1.3,
B,T Figure 11.1.1 Typical magnetization charac-

teristic showing three regions.
Region III (nonlinear)
Saturation
Typical operating point
Region II
(nearly linear)
Region I
H,At/m
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11.1 MAGNETIC MATERIALS 473
2.4
Vanadium permendur
2.0
Ingot iron
1.6 Deltamax
48 NI
1.2 48 NI AISI 1020

B,T
M-19 Cold-rolled steel
0.8 Permalloy sheet
Soft ferrite
0.4
0
1.0 10 50 100 1000 10,000
H,At/m
Figure 11.1.2 Typical magnetic characteristics of certain core materials.
which is a characteristic of a magnetic core material. The area of the loop represents the heat-
energy loss during one cycle in a unit cube of the core material. The hysteresis loss per cycle Ph cycle
in a core of volume V, possessing a uniform flux density B throughout its volume, is given by
2
Ph cycle = V (area of hysteresis loop) = V H dB (11.1.3)
The hysteresis loss per second is approximated empirically by

Ph second = kh Vf Bm1.5 to 2·5 W (11.1.4)
where kh is a proportionality constant dependent on the characteristics of iron, f is the frequency of
excitation in hertz, and Bm is the maximum value of the core flux density. This loss component of
the core loss can be reduced by choosing a core of electrical steel that has a narrow hysteresis loop.
Square-loop magnetic materials (such as ferrites and permalloy) that have a nearly rectangular
hysteresis loop are used in switching circuits, as storage elements in computers, and in special
types of transformers in electronic circuits.
Another feature of an ac-operated magnetic system is the eddy-current loss, which is the
loss due to the eddy currents induced in the core material. The eddy-current loss is empirically
approximated as
Pe = ke Vf 2 τ 2 Bm2 W (11.1.5)
where ke is a constant dependent on the characteristics of iron, V is the volume of iron, f is the
frequency, τ is the lamination thickness (usually a stack of thin laminations makes up the core),
and Bm is the maximum core flux density. By choosing very thin laminations (making τ smaller),
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the eddy-current loss can be reduced.

The laminations (or thin sheets), insulated from each other by a thin coat of varnish, are
oriented parallel to the direction of flux, as shown in Figure 11.1.4. Laminating a core generally
results in an increase in the overall volume. The ratio of the volume actually occupied by the
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B,T
1.0
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0.8
0.6
0.4
0.2
H,At/m
−250 −200 −100 −50 0 50 100 150 200 250
−0.2
−0.4
−0.6
−0.8
−1.0
Figure 11.1.3 Typical hysteresis loop of a magnetic-core material.
Flux φ Figure 11.1.4 Part of a laminated core.
Core
magnetic material to the total (gross) volume of the core is known as the stacking factor. The
thinner the lamination thickness, the lower the stacking factor. This factor usually ranges between
0.5 and 0.95.
EXAMPLE 11.1.1
(a) Estimate the hysteresis loss at 60 Hz for a toroidal (doughnut-shaped) core of 300-mm
mean diameter and a square cross section of 50 mm by 50 mm. The symmetrical hysteresis
loop for the electric sheet steel (of which the torus is made) is given in Figure 11.1.3.
(b) Now suppose that all the linear dimensions of the core are doubled. How will the hysteresis
loss differ?
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11.2 MAGNETIC CIRCUITS 475
(c) Next, suppose that the torus (which was originally laminated for reducing the eddy-
current losses) is redesigned so that it has half the original lamination thickness. Assume
the stacking factor to be unity in both cases. What would be the effect of such a change
in design on the hysteresis loss?
(d) Suppose that the toroidal core of part (a) is to be used on 50-Hz supply. Estimate the
change in hysteresis loss if no other conditions of operation are changed.
Solution
(a) Referring to Figure 11.1.3, the area of each square represents

Wb A V×s×A
(0.1 T) × (25 A/m) = 2.5 2 × = 2.5 = 2.5 J/m3
m m m3
By counting, the number of squares in the upper half of the loop is found to be 43; the
area of the hysteresis loop is given by
2 × 43 × 2.5 = 215 J/m3
The toroidal volume is
π × 0.3 × 0.052 = 2.36 × 10−3 m3

The hysteresis loss in the torus is then given by
2.36 × 10−3 × 60 × 215 = 30.44 W

(b) When all the linear dimensions of the core are doubled, its volume will be eight times
the previous volume. Hence the new core hysteresis loss will be
8 × 30.44 = 243.52 W
(c) The lamination thickness has no bearing on the hysteresis loss; it changes only the eddy-
current loss. Hence, the hysteresis loss remains unchanged.
(d) Since the hysteresis loss is directly proportional to the frequency, the loss on the 50 Hz
supply will be
50
30.44 × = 25.37 W
60
11.2 MAGNETIC CIRCUITS

A magnetic circuit provides a path for magnetic flux, just as an electric circuit provides a path for
electric current. Magnetic circuits are integral parts of transformers, electric machines, and many
other common devices such as doorbells. Analogous to voltage (electric potential difference) in
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the electric circuit, in a magnetic circuit we have the magnetomotive force (mmf), or the magnetic
potential difference which produces a magnetic field, and which has units of amperes or ampere-
turns. The two sources of mmf in magnetic circuits are the electric current and the permanent
magnet (which stores energy and is capable of maintaining a magnetic field with no expenditure
Copyright OUP
Flux φ Core Figure 11.2.1 Simple magnetic circuit. (a) Mmf and
flux. (b) Leakage flux and fringing flux.
Current I
N-turn coil
(a)
Core flux
Fringing flux
I
Leakage lg
flux
Air gap
φl
(b)
of power). The current source is commonly a coil of N turns, carrying a current I known as the
exciting current; the mmf is then said to be NI At.
Figure 11.2.1(a) shows, schematically, a simple magnetic circuit with an mmf ᑣ (= N I )
and magnetic flux φ. Note that the right-hand rule gives the direction of flux for the chosen
direction of current. The concept of a magnetic circuit is useful in estimating the mmf (excitation
ampere-turns) needed for simple electromagnetic structures, or in finding approximate flux and
flux densities produced by coils wound on ferromagnetic cores. Magnetic circuit analysis follows
the procedures that are used for simple dc electric circuit analysis.
Calculations of excitation are usually based on Ampere’s law, given by
2
H̄ dl = ampere-turns enclosed (11.2.1)
where H (|H̄ | = B/µ) is the magnetic field intensity along the path of the flux. If the magnetic
field strength is approximately constant (H = HC ) along the closed flux path, and lC is the
average (mean) length of the magnetic path in the core, Equation (11.2.1) can be simplified as
ᑣ = N I = HC lC (11.2.2)
Analogous to Ohm’s law for dc electric circuits, we have this relation for magnetic circuits,
mmf ᑣ ᑣ
flux φ = = (11.2.3)
reluctance ᑬ l/µA
where µ is the permeability, A is the cross-sectional area perpendicular to the direction of l, and
l stands for the corresponding portion of the length of the magnetic circuit along the flux path.
Based on the analogy between magnetic circuits and dc resistive circuits, Table 11.2.1 summarizes
the corresponding quantities. Further, the laws of resistances in series and parallel also hold for
reluctances.
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11.2 MAGNETIC CIRCUITS 477
TABLE 11.2.1 Analogy with dc Resistive Circuits
DC Resistive Circuit Magnetic Circuit
Current I (A) Flux φ (Wb)

Voltage V (V) Magnetomotive force (mmf) ᑣ (At)
Resistance R = l/σ A (-) Reluctance ᑬ = l/µA (H−1 )
Conductivity σ (S/m) Permeability µ( H/m)
Conductance G = 1/R (S) Permeance P = 1/ᑬ (H)
I = V /R φ = ᑣ/ᑬ
Current density J = I /A (A/m2) Flux density B = φ/A (Wb/m2)
Analogous to KVL in electrical circuits, Ampere’s law applied to the analysis of a magnetic
circuit leads to the statement that the algebraic sum of the magnetic potentials around any closed
path is zero. Series, parallel, and series–parallel magnetic circuits can be analyzed by means of
their corresponding electric-circuit analogs. All methods of analysis that are valid for dc resistive
circuits can be effectively utilized in an analogous manner.
The following differences exist between a dc resistive circuit and a magnetic circuit
• Reluctance ᑬ is not an energy-loss component like a resistance R (which leads to an
I 2 R loss). Energy must be supplied continuously when a direct current is established and
maintained in an electric circuit; but a similar situation does not prevail in the case of a
magnetic circuit, in which a flux is established and maintained constant.
• Magnetic fluxes take leakage paths [as φl in Figure 11.2.1(b)]; but electric currents flowing
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through resistive networks do not.
• Fringing or bulging of flux lines [shown in Figure 11.2.1(b)] occurs in the air gaps of
magnetic circuits; but such fringing of currents does not occur in electric circuits. Note that
fringing increases with the length of the air gap and increases the effective area of the air
gap.
• There are no magnetic insulators similar to the electrical insulators.
In the case of ferromagnetic systems containing air gaps, a useful approximation for making
quick estimates is to consider the ferromagnetic material to have infinite permeability. The relative
permeability of iron is considered so high that practically all the ampere-turns of the winding are
consumed in the air gaps alone.
Calculating the mmf for simple magnetic circuits is rather straightforward, as shown in the
following examples. However, it is not so simple to determine the flux or flux density when the
mmf is given, because of the nonlinear characteristic of the ferromagnetic material.
EXAMPLE 11.2.1
Consider the magnetic circuit of Figure 11.2.1(b) with an air gap, while neglecting leakage flux.
Correct for fringing by adding the length of the air gap lg = 0.1 mm to each of the other two
dimensions of the core cross section AC = 2.5cm × 2.5cm. The mean length of the magnetic
path in the core lC is given to be 10 cm. The core is made of 0.15- mm-thick laminations of M-19
material whose magnetization characteristic is given in Figure 11.1.2. Assume the stacking factor
to be 0.9. Determine the current in the exciting winding, which has 100 turns and produces a core
flux of 0.625 mWb.
Copyright OUP
Solution
The net cross-sectional area of the core is 2.52 × 10−4 × 0.9 = 0.5625 × 10−3 m2 . Note that the
stacking factor of 0.9 is applied for the laminated core. It does not, however, apply for the air-gap
portion,
φ 0.625 × 10−3
= BC = = 1.11 T
net area 0.5625 × 10−3
The corresponding HC from Figure 11.1.2 for M-19 is 130 A/m. Hence,
ᑣC = HC lC = 130 × 0.1 = 13 At
The cross-sectional area of the air gap, corrected for fringing, is given by
Ag = (2.5 + 0.01)(2.5 + 0.01)10−4 = 0.63 × 10−3 m2
φ 0.625 × 10−3
Bg = = = 0.99 T
Ag 0.63 × 10−3
Bg 0.99
Hg = = = 0.788 × 106 A/m
µ0 4π × 10−7
Hence,
ᑣg = Hg lg = 0.788 × 106 × 0.1 × 10−3 = 78.8 At
For the entire magnetic circuit (see Figure E11.2.1)
N I = ᑣTOTAL = ᑣC + ᑣg = 13 + 78.8 = 91.8 At
Thus, the coil current
NI 91.8
I= = = 0.92 A
N 100
Figure E11.2.1 Equivalent magnetic circuit.

+ φ
EXAMPLE 11.2.2
In the magnetic circuit shown in Figure E11.2.2(a) the coil of 500 turns carries a current of 4 A.
The air-gap lengths are g1 = g2 = 0.25 cm and g3 = 0.4 cm. The cross-sectional areas are related
such that A1 = A2 = 0.5A3 . The permeability of iron may be assumed to be infinite. Determine
the flux densities B1 , B2 , and B3 in the gaps g1 , g2 , and g3 , respectively. Neglect leakage and
fringing.
Solution
Noting that the reluctance of the iron is negligible, the equivalent magnetic circuit is shown in
Figure E11.2.2(b).
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11.3 TRANSFORMER EQUIVALENT CIRCUITS 479
Given ᑣ = N I = 500 × 4 = 2000 At, g1 = g2 = 0.25 cm, and g3 = 0.4 cm; A1 = A2 =

0.5A3 ; µ1 = µ2 = µ3 = µ0 ; φ3 = φ1 + φ2 ; and H1 g1 + H3 g3 = H2 g2 + H3 g3 = ᑣ = 2000, we
have
H1 g1 = H2 g2 or H 1 = H2
since g1 = g2 . Thus, B1 = B2 , since µ1 = µ2 = µ0 . Because A1 = A2 , it follows that φ1 = φ2
and φ3 = 2φ1 . But B3 = φ3 /2A1 = B1 . Thus,
B1 = B2 = B3 ; H1 = H2 = H3
We had H1 g1 + H3 g3 = 2000, which is rewritten as
B1 B1
(0.25 × 10−2 ) + (0.4 × 10−2 ) = 2000
µ0 µ0
or,
2000 × 4π × 10−7
B1 = = 0.387 T = B2 = B3
0.65 × 10−2
φ1 φ2
φ3
A1 A2
g1 g3 g2
A3
(a) (b)
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Figure E11.2.2
A simple magnetic structure, similar to those examined in the previous examples, finds
common application in the so-called variable-reluctance position sensor, which, in turn, finds
widespread application in a variety of configurations for the measurement of linear and angular
position and velocity.
For magnetic circuits with ac excitation, the concepts of inductance and energy storage come
into play along with Faraday’s law of induction. Those concepts have been presented in some
detail in Section 1.2. The reader is encouraged to review that section, as that background will be
helpful in solving some of the problems related to this section.
11.3 TRANSFORMER EQUIVALENT CIRCUITS

It would be appropriate for the reader to review the material on transformers in Section 1.2.
Transformers come in various sizes, from very small, weighing only a few ounces, to very
large, weighing hundreds of tons. The ratings of transformers cover a very wide range. Whereas
transformers applied with electronic circuits and systems usually have ratings of 300 VA or less,
power-system transformers used in transmission and distribution systems have the highest volt-
ampere ratings (a few kVA to several MVA) as well as the highest continuous voltage ratings.
Instrument transformers (potential transformers and current transformers) with very small volt-
ampere ratings are used in instruments for sensing voltages or currents in power systems.
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Transformers may be classified by their frequency range: power transformers, which usually
operate at a fixed frequency; audio and ultrahigh-frequency transformers; wide-band and narrow-
band frequency transformers; and pulse transformers. Transformers employed in supplying power
to electronic systems are generally known as power transformers. In power-system applications,
however, the term power transformer denotes transformers used to transmit power in ratings
larger than those associated with distribution transformers, usually more than 500 kVA at voltage
levels of 67 kV and above.
Conventional transformers have two windings, but others (known as autotransformers) have
only one winding, and still others (known as multiwinding transformers) have more than two
windings. Transformers used in polyphase circuits are known as polyphase transformers. In the
most popular three-phase system, the most common connections are the wye (star or Y) and the
delta (mesh or ?) connections.
Figure 11.3.1 shows, schematically, a transformer having two windings with N1 and N2 turns,
respectively, on a common magnetic circuit. The transformer is said to be ideal when:
• Its core is infinitely permeable.
• Its core is lossless.
• It has no leakage fluxes.
• Its windings have no losses.
The mutual flux linking the N1 -turn and N2 -turn windings is φ. Due to a finite rate of change
of φ, according to Faraday’s law of induction, emf’s e1 and e2 are induced in the primary and
secondary windings, respectively. Thus, we have
dφ dφ e1 N1
e1 = N1 ; e2 = N2 ; = (11.3.1)
dt dt e2 N2
The polarity of the induced voltage is such as to produce a current which opposes the flux change,
according to Lenz’s law. For the ideal transformer, since e1 = v1 and e2 = v2 , it follows that
v1 e1 N1 V1 E1 N1
= = = a; = = =a (11.3.2)
v2 e2 N2 V2 E2 N2
where V1 , V2 , E1 , and E2 are the rms values of v1 , v2 , e1 , and e2 , respectively, and a stands for the
turns ratio. When a passive external load circuit is connected to the secondary winding terminals,
the terminal voltage v2 will cause a current i2 to flow, as shown in Figure 11.3.1. Further, we have
i1 v2 N2 1 I1 V2 N2 1
v1 i1 = v2 i2 ; = = = ; = = = (11.3.3)
i2 v1 N1 a I2 V1 N1 a
Mean path of magnetic flux Ferromagnetic core
i1 i2
+ Secondary + +
+ (N2 turns)
v1 e1 e2 v2 Load
ZL
−
Primary −
− (N1 turns) −
Mutual flux φ
Figure 11.3.1 Schematic of two-winding transformer.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
in which I1 and I2 are the rms value of i1 and i2 , respectively.

If the flux varies sinusoidally, such that
φ = φmax sin ωt (11.3.4)
where φmax is the maximum value of the flux and ω = 2πf , f being the frequency, then the
induced voltages are given by
e1 = ωN1 φmax cos ωt; e2 = ωN2 φmax cos ωt (11.3.5)
Note that the induced emf leads the flux by 90°. The rms values of the induced emf’s are given by
ωN1 φmax ωN2 φmax
E1 = √ = 4.44f N1 φmax ; E2 = √ = 4.44f N2 φmax (11.3.6)
2 2
Equation (11.3.6) is known as the emf equation.
From Equations (11.3.2) and (11.3.3) it can be shown that if an impedance Z̄L is connected
to the secondary, the impedance Z̄1 seen at the primary is given by
2
N1
Z̄1 = a 2 Z̄L = Z̄L (11.3.7)
N2
Major applications of transformers are in voltage, current, and impedance transformations,
and in providing isolation while eliminating direct connections between electric circuits.
A nonideal (or practical) transformer, in contrast to an ideal transformer, has the following
characteristics, which have to be accounted for:
• Core losses (hysteresis and eddy-current losses)

• Resistive (I 2 R) losses in its primary and secondary windings
• Finite permeability of the core requiring a finite mmf for its magnetization
• Leakage fluxes (associated with the primary and secondary windings) that do not link both
windings simultaneously.
Now our goal is to develop an equivalent circuit of a practical transformer by including the
nonideal effects. First, let us consider the simple magnetic circuit of Figure 11.2.1(a), excited by
an ac mmf, and come up with its equivalent circuit. With no coil resistance and no core loss,
but with a finite constant permeability of the core, the magnetic circuit along with the coil can
be represented just by an inductance Lm or, equivalently, by an inductive reactance Xm = ωLm ,
when the coil is excited by a sinusoidal ac voltage of frequency f = ω/2π . This reactance is
known as the magnetizing reactance. Thus, Figure 11.3.2(a) shows Xm (or impedance Z̄ = j Xm )
across which the terminal voltage with an rms value of V1 (equal to the induced voltage E1 )
is applied.
Next, in order to include the core losses, since these depend directly upon the level of flux
density and hence the voltage V1 , a resistance RC is added in parallel to j Xm , as shown in Figure
11.3.2(b). Then the resistance R1 of the coil itself and the leakage reactance X1 , representing
the effect of leakage flux associated with the coil, are included in Figure 11.3.2(c) as a series
impedance given by R1 + j X1 .
Finally, Figure 11.3.3 shows the equivalent circuit of a nonideal transformer as a combination
of an ideal transformer and of the nonideal effects of the primary winding, the core, and the
secondary winding. Note that the effects of distributed capacitances across and between the
windings are neglected here. The following notation is used:
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
+ +
V1 = E1 Z = jXm V1 = E1 RC jXm
− −
(a) (b)
+ Figure 11.3.2 Equivalent circuits of an iron

R1 jX1 core excited by an ac mmf.
+
V1 E1 RC jXm
−
−
(c)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
I1 a:1 I2
+
R1 jX1 I0 jX2 R2 +
IC Im + +
V1 jXm E1 E2 V2 ZL
RC
− −
−
−
N1 N2
(Ideal transformer)
Figure 11.3.3 Equivalent circuit of a two-winding iron-core transformer as a combination of an ideal

transformer and the nonideal effects.
a Turns ratio N1 /N2

E1 , E 2 Induced voltage in primary and secondary
V1 , V2 Terminal voltage of primary and secondary
I1 , I2 Input and output current
I0 No-load primary exciting current
R1 , R 2 Winding resistance of primary and secondary
X1 , X 2 Leakage reactance of primary and secondary
Im , Xm Magnetizing current and reactance (referred to primary)
IC , RC Current and resistance accounting for core losses (referred to primary)
Ȳo Exciting admittance (referred to primary), which is the admittance of the parallel
combination of Xm and RC
Z̄L Load impedance = V̄2 /I¯2
Copyright OUP
Note that phasor notation and rms values for all voltages and currents are used.
It is generally more convenient to have the equivalent circuit entirely referred to either
primary or secondary by using the ideal-transformer relationships [Equations (11.3.2), (11.3.3),
and (11.3.7)], thereby eliminating the need for the ideal transformer to appear in the equivalent
circuit. Figure 11.3.4 shows such circuits, which are very useful for determining the transformer
characteristics.
I1 I2/a
+ Io +
R1 jX1 ja2X2 a2R2
V1 jXm −
RC aV2 a2ZL
IC Im
− −
(a)
R1/a2 jX1/a2 jX2 R2 I2

+
aIo +
aI1
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
−
V1/a RC /a2 jXm /a2 V2 ZL
aIC aIm
−
−
(b)
Figure 11.3.4 Equivalent circuits of a transformer. (a) Referred to primary. (b) Referred to secondary.
EXAMPLE 11.3.1
A single-phase, 50-kVA, 2400:240-V, 60-Hz distribution transformer has the following parame-
ters:
Resistance of the 2400-V winding R1 = 0.75
Resistance of the 240-V winding R2 = 0.0075
Leakage reactance of the 2400-V winding X1 = 1 -
Leakage reactance of the 240-V winding X2 = 0.01 -
Exciting admittance on the 240-V side = 0.003 − j 0.02 S
Draw the equivalent circuits referred to the high-voltage side and to the low-voltage side. Label
the impedances numerically.
Solution
(a) The equivalent circuit referred to the high-voltage side is shown in Figure E11.3.1 (a). The
quantities, referred to the high-voltage side from the low-voltage side, are calculated as
Copyright OUP

2400 2
R 2 = a R2 =
2
(0.0075) = 0.75 -
240

2400 2
X2 = a X2 =
2
(0.01) = 1.0 -
240
Note that the exciting admittance on the 240-V side is given. The exciting branch
conductance and susceptance referred to the high-voltage side are given by
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
1 1
(0.003) or × 0.003 = 0.03 × 10−3 S
a2 100
and
1 1
(0.02) or × 0.02 = 0.2 × 10−3 S
a2 100
(b) The equivalent circuit referred to the low-voltage side is given in Figure E11.3.1 (b).
Note the following points.
(i) The voltages specified on the nameplate of a transformer yield the turns ratio directly.
The turns ratio in this problem is 2400:240, or 10:1.
(ii) Since admittance is the reciprocal of impedance, the reciprocal of the referring factor
for impedance must be used when referring admittance from one side to the other.
R1= 0.75 Ω jX1=j1 Ω R2′ = a2R2 = 0.75 Ω jX2′ = ja2X2 = j1 Ω
GC = 0.03 × 10−3 S −jBm = −j0.2 × 10−3 S

or or
5 4
RC = G1 = 103 Ω jXm = 1
= j 102 Ω
C -jBm
2400 : 240
Ideal transformer
(can be omitted)
(a)
R1′ = R1/a2 = 0.0075 Ω R2 = 0.0075 Ω jX2 = j 0.01 Ω
jX1′ = jX1/a2 = j 0.01 Ω

a2GC = 0.003 S −j 0.02 S = −ja2Bm
or or
RC /a2 = 1000 Ω j 100 Ω = jXm /a2

3 2
2400 : 240
Ideal transformer
(can be omitted)
(b)
Figure E11.3.1 Equivalent circuit. (a) Referred to high-voltage side. (b) Referred to low-voltage side.
Copyright OUP
The equivalent circuits shown in Figure 11.3.4 are often known as transformer T-circuits
in which winding capacitances have been neglected. Other modifications and simplifications
of this basic T-circuit are used in practice. Approximate circuits (referred to the primary)
commonly used for the constant-frequency power-system transformer analysis are shown in
Figure 11.3.5. By moving the parallel combination of RC and j Xm from the middle to the left,
as shown in Figure 11.3.5(a), computational labor can be reduced greatly with minimal error.
The series impedance R1 + j X1 can be combined with a 2 R2 + j a 2 X2 to form an equivalent
series impedance, Z̄eq = Req + j Xeq . Further simplification is gained by neglecting the exciting
current altogether, as shown in Figure 11.3.5(b), which represents the transformer by its equivalent
series impedance. When Req is small compared to Xeq , as in the case of large power-system
transformers, Req may frequently be neglected for certain system studies. The transformer is
then modeled by its equivalent series reactance Xeq only, as shown in Figure 11.3.5(c). The
student should have no difficulty in drawing these approximate equivalent circuits referred to the
secondary.
The modeling of a circuit or system consisting of a transformer depends on the frequency
range of operation. For variable-frequency transformers, the high-frequency-range equivalent
circuit with capacitances is usually considered, even though it is not further pursued here.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
I1 I2/a Figure 11.3.5 Approximate trans-

+ former equivalent circuits referred to
Io primary.
Req = R1 + a2R2 jXeq = j(X1 + a2X2)
+
−
V1 RC jXm aV2 a2ZL
−
IC Im
−
(a)
I2/a
+
+
I1 = I2/a Req = R1 + a2R2 jXeq = j(X1 + a2X2)
−
V1 aV2 a2ZL
−
−
(b)
+
+
I1 = I2/a jXeq = j(X1 + a2X2)
−
V1 aV2 a2ZL
−
−
(c)
Copyright OUP
11.4 TRANSFORMER PERFORMANCE

The characteristics of most interest to power engineers are voltage regulation and efficiency. The
voltage regulation of a transformer is a measure of the change in the magnitude of the secondary
voltage as the current changes from no load to full load while the primary voltage is held fixed.
This is defined as
V2 NL − V2 FL
% voltage regulation = × 100 (11.4.1a)
V2 FL
which may also be expressed as
V1 − aV2
× 100 (11.4.1b)
aV2
or
(V1 /a) − V2
× 100 (11.4.1c)
V2
The power efficiency (generally known as efficiency) of a transformer is defined as
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
real power output

η= × 100% (11.4.2a)
real power input
real power output
= × 100% (11.4.2b)
real power output + losses
real power output
= × 100% (11.4.2c)
real power output + core loss + copper (I 2 R) loss
in which the I 2 R loss is obviously load-dependent, whereas the core loss is considered to be
constant and independent of the load. It can be shown that the core loss should be equal to the
copper loss for maximum operating efficiency at a given load.
The rated core loss can be approximated by the power input in the open-circuit test in which
one winding is open-circuited and rated voltage at rated frequency is applied to the other winding.
The rated copper loss (at full load) can be approximated by the power input in the short-circuit
test, in which one winding is short-circuited and a reduced voltage at rated frequency is applied
to the other winding such that the rated current results.
The energy efficiency generally taken over a 24-hour period, known as all-day efficiency, is
also of interest. It is given by
energy output over 24 hours
ηAD = × 100% (11.4.3)
energy input over 24 hours
EXAMPLE 11.4.1
The transformer of Example 11.3.1 is supplying full load (i.e., rated load of 50 kVA) at a rated
secondary voltage of 240 V and 0.8 power factor lagging. Neglecting the exciting current of the
transformer,
(a) Determine the percent voltage regulation of the transformer.
(b) Sketch the corresponding phasor diagram.
(c) If the transformer is used as a step-down transformer at the load end of a feeder whose
impedance is 0.5 + j 2.0 -, find the voltage VS and the power factor at the sending end
of the feeder.
Copyright OUP
11.4 TRANSFORMER PERFORMANCE 487
Solution
(a) The equivalent circuit of the transformer, referred to the high-voltage (primary) side,
neglecting the exciting current of the transformer, is shown below in Figure E11.4.1(a).
Note that the voltage at the load terminals referred to the high-voltage side is 240 × 10 =
2400 V. Further, the load current corresponding to the rated (full) load condition is
50 × 103 /2400 = 20.8 A, referred to the high-voltage side. With a lagging power factor
of 0.8,
I¯1 = I¯2 /a = 20.8 − cos−1 0.8 = 20.8 − 36.9°
Using KVL,
V̄1 = 2400 0° + (20.8 − 36.9°)(1.5 + j 2.0) = 2450 0.34°
If there is no load, the load-terminal voltage will be 2450 V. Therefore, from Equation
(11.4.1b),
V1 − aV2 2450 − 2400
% voltage regulation = × 100 = × 100 = 2.08%
aV2 2400
I1 = I2/a = 20.8∠−36.9° A Figure E11.4.1

+
+
1.5 Ω j 2.0 Ω
V1 Req jXeq aV2 = 2400 ∠0° V Load
−
−
(a)
V1 = 2450 ∠0.34°
0.34° aV2 = 2400 ∠0° V |j I1Xeq| = 41.6 V
−1
cos 0.8 = 36.9°
|I1Req| = 31.2 V
I1 = 20.8∠−36.9° A
(b)
Feeder I1 = I2/a = 20.8∠−36.9° A

+
+ +
0.5 Ω j 2.0 Ω Req = 1.5 Ω j Xev = j2.0 Ω
VS V1 aV2 = 2400 ∠0° Load
− −
−
(c)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
(b) The corresponding phasor diagram is shown in Figure E11.4.1(b).

(c) The equivalent circuit of the transformer, along with the feeder impedance, referred to the
high-voltage side, neglecting the exciting current of the transformer, is shown in Figure
E11.4.1(c). The total series impedance is (0.5 + j 2.0) + (1.5 + j 2.0) = 2 + j 4 -. Using
KVL,
V̄S = 2400 0° + (20.8 − 36.9°)(2 + j 4) = 2483.5 0.96° V
The voltage at the sending end is then 2483.5 V. The power factor at the sending end is
given by cos(36.9 + 0.96)° = 0.79 lagging.
EXAMPLE 11.4.2
Compute the efficiency of the transformer of Example 11.3.1 corresponding to (a) full load,
0.8 power factor lagging, and (b) one-half load, 0.6 power factor lagging, given that the input
power Poc in the open-circuit conducted at rated voltage is 173 W and the input power Psc in the
short-circuit test conducted at rated current is 650 W.
Solution
(a) Corresponding to full load, 0.8 power factor lagging,
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Output = 50,000 × 0.8 = 40,000 W
The I 2 R loss (or copper loss) at rated (full) load equals the real power measured in the
short-circuit test at rated current,
Copper loss = IHV
2
Req HV = Psc = 650 W
where the subscript HV refers to the high-voltage side. The core loss, measured at rated
voltage, is
Core loss = Poc = 173 W

Then
Total losses at full load = 650 + 173 = 823 W
Input = 40,000 + 823 = 40,823 W
The full-load efficiency of η at 0.8 power factor is then given by

output 40,000
η= × 100 = × 100 = 98%
input 40,823
(b) Corresponding to one-half rated load, 0.6 power factor lagging,

1
Output = × 50,000 × 0.6 = 15,000 W
2
1
Copper loss = × 650 = 162.5 W
4
Copyright OUP
11.4 TRANSFORMER PERFORMANCE 489
Note that the current at one-half rated load is half of the full-load current, and that the
copper loss is one-quarter of that at rated current value.
Core loss = Poc = 173 W
which is considered to be unaffected by the load, as long as the secondary terminal voltage
is at its rated value. Then
Total losses at one-half rated load = 162.5 + 173 = 335.5 W
Input = 15,000 + 335.5 = 15,335.5 W
The efficiency at one-half rated load and 0.6 power factor is then given by
15,000
η= × 100 = 97.8%
15,335.5
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
EXAMPLE 11.4.3
The distribution transformer of Example 11.3.1 is supplying a load at 240 V and 0.8 power factor
lagging. The open-circuit and short-circuit test data are given in Example 11.4.2.
(a) Determine the fraction of full load at which the maximum efficiency of the transformer
occurs, and compute the efficiency at that load.
(b) The load cycle of the transformer operating at a constant 0.8 lagging power factor is 90%
full load for 8 hours, 50% (half) full load for 12 hours, and no load for 4 hours. Compute
the all-day energy efficiency of the transformer.
Solution
(a) For maximum efficiency to occur at a certain load, the copper loss at that load should be
equal to the core loss. So,
k 2 Psc = Poc
where k is the fraction of the full-load rating at which the maximum efficiency occurs.
Therefore,
3 &
Poc 173
k= = = 0.516
Psc 650
The output power corresponding to this condition is

50,000 × 0.516 × 0.8 = 20,640 W
where 0.8 is the power factor given in the problem statement. Also, core loss = copper
loss = 173 W. The maximum efficiency is then given by
output 20,640 20,640
ηmax = = = = 0.9835, or 98.35%
output + losses 20,640 + 173 + 173 20,986
Copyright OUP
(b) During 24 hours,

energy output = (8 × 0.9 × 50 × 0.8) + (12 × 0.5 × 50 × 0.8) = 528 kWh
core loss = 24 × 0.173 = 4.15 kWh
copper loss = (8 × 0.92 × 0.65) + (12 × 0.52 × 0.65) = 6.16 kWh
The all-day (or energy) efficiency of the transformer is given by

528
ηAD = = 0.9808, or 98.08%
528 + 4.15 + 6.16
11.5 THREE-PHASE TRANSFORMERS

As we have seen in Chapter 10, three-phase transformers are used quite extensively in power
systems between generators and transmission systems, between transmission and subtransmission
systems, and between subtransmission and distribution systems. Most commercial and industrial
loads require three-phase transformers to transform the three-phase distribution voltage to the
ultimate utilization level.
Transformation in three-phase systems can be accomplished in either of two ways: (1)
connecting three identical single-phase transformers to form a three-phase bank (each one will
carry one-third of the total three-phase load under balanced conditions); or (2) a three-phase
transformer manufactured for a given rating. A three-phase transformer, compared to a bank of
three single-phase transformers, for a given rating will weigh less, cost less, require less floor
space, and have somewhat higher efficiency.
The windings of either core-type or shell-type three-phase transformers may be connected
in either wye or delta. Four possible combinations of connections for the three-phase, two-
winding transformers are Y–?,?–Y, ?–?, and Y–Y. These are shown in Figure 11.5.1 with
the transformers assumed to be ideal. The windings on the left are the primaries, those on the
right are the secondaries, and a primary winding of the transformer is linked magnetically with
the secondary winding drawn parallel to it. With the per-phase primary-to-secondary turns ratio
(N1 /N2 = a), the resultant voltages and currents for balanced applied line-to-line voltages V and
line currents I are marked in the figure.
As in the case of three-phase circuits under balanced conditions, only one phase needs to
be considered for circuit computations, because the conditions in the other two phases are the
same except for the phase displacements associated with a three-phase system. It is usually
convenient to carry out the analysis on a per-phase-of-Y (i.e., line-to-neutral) basis, and in such
a case the transformer series impedance can then be added in series with the transmission-line
series impedance. In dealing with Y–? and ?–Y connections, all quantities can be referred to
the Y-connected side. For ?–? connections, it is convenient to replace the ?-connected series
impedances of the transformers with equivalent Y-connected impedances by using the relation
1
Zper phase of Y = Zper phase of ? (11.5.1)
3
It can be shown that to transfer the ohmic value of impedance from the voltage level on one side
of a three-phase transformer to the voltage level on the other side, the multiplying factor is the
square of the ratio of line-to-line voltages, regardless of whether the transformer connection is
Y–Y, ?–Y, or ?–?. In some cases, where Y–Y transformation is utilized in particular, it is quite
common to incorporate a third winding, known as tertiary winding, connected in delta. Such
multiwinding transformers with three or more windings are not considered in this text.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
11.5 THREE-PHASE TRANSFORMERS 491
I − Figure 11.5.1 Wye–delta, delta–wye, delta–

√ 3 aI delta, and wye–wye transformer connections in
three-phase systems.
V/√3
V/(√3a)
V
+
aI
+
(a)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
I aI
V V/a
+ +
I/√3 aI/√3
(c)
I aI
V/√3 V/(√3a)
V V/a
+ +
(d)
Copyright OUP
11.6 AUTOTRANSFORMERS
In contrast to a two-winding transformer, the autotransformer is a single-winding transformer
having a tap brought out at an intermediate point. Thus, as shown in Figure 11.6.1, a–c is the
single N1 -turn winding wound on a laminated core, and b is the intermediate point where the tap
is brought out such that b–c has N2 turns. The autotransformer may generally be used as either
a step-up or a step-down operation. Considering the step-down arrangement, as shown in Figure
11.6.1, let the primary applied voltage be V1 , resulting in a magnetizing current and a core flux φm .
Voltage drops in the windings, exciting current, and small phase-angular differences are usually
neglected for the analysis. Then it follows that
V1 I2 N1
= = =a (11.6.1)
V2 I1 N2
in which a > 1 for step-down, a < 1 for step-up transformers.
The input apparent power is S1 = V1 I1 , while the output apparent power is given by
S2 = V2 I2 . The apparent power transformed by electromagnetic induction (or transformer action)
is Sind = V2 I3 = (V1 −V2 )I2 . The output transferred by electrical conduction (because of the direct
electrical connection between primary and secondary windings) is given by Scond = V2 I2 −V2 I3 =
V2 I1 .
For the same output the autotransformer is smaller in size, weighing much less than a two-
winding transformer, and has higher efficiency. An important disadvantage of the autotransformer
is the direct copper connection (i.e., no electrical isolation) between the high- and low-voltage
sides. A type of autotransformer commonly found in laboratories is the variable-ratio autotrans-
former, in which the tapped point b (shown in Figure 11.6.1) is movable. It is known as the variac
(variable ac). Although here, for the sake of simplicity, we have considered only the single-phase
autotransformer, three-phase autotransformers, which are available in practice, can be modeled
on a per-phase basis and also analyzed just as the single-phase case.
I1 Figure 11.6.1 Single-phase step-down auto-

+ a transformer.
b I2
V1 +
V2
I3 = I2 − I1 c
− −
EXAMPLE 11.6.1
The single-phase, 50-kVA, 2400:240-V, 60-Hz, two-winding distribution transformer of Example
11.3.1 is connected as a step-up autotransformer, as shown in Figure E11.6.1. Assume that the
240-V winding is provided with sufficient insulation to withstand a voltage of 2640 V to ground.
(a) Find VH , VX , IH , IC , and IX corresponding to rated (full-load) conditions.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,
Copyright OUP
11.6 AUTOTRANSFORMERS 493
(b) Determine the kVA rating as an autotransformer, and find how much of that is the
conducted kVA.
(c) Based on the data given for the two-winding transformer in Example 11.4.2, compute the
efficiency of the autotransformer corresponding to full load, 0.8 power factor lagging,
and compare it with the efficiency calculated for the two-winding transformer in part (a)
of Example 11.4.2.
IH Figure E11.6.1
+
240 V
IX
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
+ VH
VX 2400 V
IC
− −
Solution
(a) The two windings are connected in series so that the polarities are additive. Neglecting
the leakage-impedance voltage drops,
VH = 2400 + 240 = 2640 V
VX = 2400 V
The full-load rated current of the 240-V winding, based on the rating of 50 kVA as a two-
winding transformer, is 50,000/240 = 208.33 A. Since the 240-V winding is in series
with the high-voltage circuit, the full-load current of this winding is the rated current on
the high-voltage side of the autotransformer,
IH = 208.33 A
Neglecting the exciting current, the mmf produced by the 2400-V winding must be
equal and opposite to that of the 240-V winding,

240
IC = 208.33 = 20.83 A
2400
in the direction shown in the figure. Then the current on the low-voltage side of the
autotransformer is given by
IX = IH + IC = 208.33 + 20.33 = 229.16 A
(b) The kVA rating as an autotransformer is
Copyright OUP
V H IH 2640 × 208.33
= = 550 kVA
1000 1000
or
VX IX 2400 × 229.16
= = 550 kVA
1000 1000
which is 11 times that of the two-winding transformer. The transformer must boost the
current IH of 208.33 A through a potential rise of 240 V. Thus the kVA transformed by
electromagnetic induction is given by
240 × 208.33
= 50 kVA
1000
The remaining 500 kVA is the conducted kVA.
(c) With the currents and voltages shown for the autotransformer connections, the losses
at full load will be 823 W, the same as in Example 11.4.2. However, the output as an
autotransformer at 0.8 power factor is given by
550 × 1000 × 0.8 = 440,000 W
The efficiency of the autotransformer is then calculated as
440,000
η= = 0.9981, or 99.81%
440,823
whereas that of the two-winding transformer was calculated as 0.98 in Example 11.4.2.
Because the only losses are those due to transforming 50 kVA, higher efficiency results
for the autotransformer configuration compared to that of the two-winding transformer.

• Analysis and design of simple magnetic circuits.
• Equivalent circuits of transformers.
• Predicting transformer performance from equivalent circuits.
• Basic notions of three-phase transformers.
• Elementary autotransformer calculations and performance.
Magnetic Bearings for Space Technology

The high magnetic energy stored in rare-earth-cobalt permanent magnets allows the design of
lightweight motors and magnetic bearings for high-speed rotors. Magnetic bearings are not subject
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
to wear, and with the ability to operate under high vacuum conditions, they appear to be ideal for
applications requiring high rotational speeds, such as 100,000 r/min. Important applications are
for turbomolecular pumps, laser scanners, centrifuges, momentum rings for satellite stabilizations,
and other uses in space technology.
Copyright OUP
PROBLEMS 495
Because of the absence of mechanical contact and lubricating fluids, magnetic bearings
can be operated in high vacuum at higher speeds with extremely low friction, low noise, and
longer operating life. With no risk of contamination by oil or gas, and with less heat dissipation,
it is possible to ascertain clean, stable, and accurate operating conditions with reliability and
repeatability. In space technology the magnetic bearings are used successfully in reaction,
momentum, and energy wheels, helium pumps, and telescope pointing. Terrestrial applications
include scanners, high-vacuum pumps, beam choppers in high vacuum, energy storage wheels,
and accurate smooth rotating machines. The magnetic bearings in a reaction wheel are shown in
Figure 11.8.1.
The design of magnetic bearings involves the calculation of magnetic forces and stiffness
as part of designing an electromechanical servo system. In earlier days, the magnetic force
of a suspension block was calculated approximately, with reasonable accuracy, by assuming
simple straight flux paths. However, higher magnetic flux densities are increasingly used for
reducing the weight and size of magnetic bearings, particularly in the case of a single-axis servoed
magnetic bearing which utilizes fringing rings. In such cases the nonlinear characteristics of the
ferromagnetic materials become quite significant; analytical techniques fail to yield sufficiently
accurate results. Hence it becomes essential to take recourse to numerical analysis of the nonlinear
magnetic fields with the aid of a high-speed digital computer in order to determine more accurately
the flux distribution corresponding to various conditions of operation, compute leakage, and
evaluate forces at the air gap, so as to optimize the design of nonlinear magnetic bearings.
The strength of the electromagnet and/or the permanent magnet can easily be changed to
observe their effect on the leakage as well as the flux-density distribution, particularly at the air-
gap level and fringing rings. The number of fringing rings and their location may also be easily
changed in order to evaluate their effects on the forces at the air-gap level.
Rotor Bearing gap Figure 11.8.1 Magnetic bearings in

a reaction wheel.
Motor SmCo magnet
Control coil
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PROBLEMS
11.1.1 From the magnetic material characteristics and AISI 1020 materials.
shown in Figure 11.1.2, estimate the relative 11.1.2 Determine the units for the area of the hysteresis
permeability µr at a flux density of 1 T for M-19 loop of a ferromagnetic material.
Copyright OUP
11.1.3 In plotting a hysteresis loop the following scales 16 cm2, the average length of the magnetic path
are used: 1 cm = 400 At/m and 1 cm = 0.3 T. The in the core lC be 40 cm, the number of turns
area of the loop for a certain magnetic material N of the excitation coil be 100 turns, and the
is found to be 6.2 cm2. Calculate the hysteresis relative permeability µr of the core be 50,000.
loss in joules per cycle for the specimen tested if For a magnetic flux density of 1.5 T in the core,
the volume is 400 cm3. determine:
11.1.4 A sample of iron having a volume of 20 cm3 (a) The flux φ
is subjected to a magnetizing force varying sinu- (b) Total flux linkage λ(= N φ).
soidally at a frequency of 400 Hz. The area of the
hysteresis loop is found to be 80 cm2 with the flux (c) The current required through the coil.
density plotted in Wb/m2 and the magnetizing 11.2.2 Now suppose an air gap 0.1 mm long is cut
force in At/m. The scale factors used are 1 cm = in the right leg of the core of Figure 11.2.1(a),
0.03 T and 1 cm = 200 At/m. Find the hysteresis making the magnetic circuit look like that of
loss in watts. Figure 11.2.1(b). Neglect leakage and fringing.
11.1.5 The flux in a magnetic core is alternating sinu- With the new core configuration, repeat Problem
soidally at a frequency of 500 Hz. The maximum 11.2.1 for the same dimensions and values given
flux density is 1 T. The eddy-current loss then in that problem. See what a difference that small
amounts to 15 W. Compute the eddy-current loss air gap can make!
in this core when the frequency is 750 Hz and the 11.2.3 A toroid with a circular cross section is shown in
maximum flux density is 0.8 T. Figure P11.2.3. It is made from cast steel with a
*11.1.6 The total core loss for a specimen of magnetic relative permeability of 2500. The magnetic flux
sheet steel is found to be 1800 W at 60 Hz. density in the core is 1.25 T measured at the mean
When the supply frequency is increased to 90 diameter of the toroid.
Hz, while keeping the flux density constant, the (a) Find the current that must be supplied to the
total core loss is found to be 3000 W. Determine coil.
the hysteresis and eddy-current losses separately
at both frequencies. (b) Calculate the magnetic flux in the core.
11.1.7 A magnetic circuit is found to have an ac hystere- (c) Now suppose a 10-mm air gap is cut across
sis loss of 10 W when the peak current is Im = 2 the toroid. Determine the current that must
A. Assuming the exponent of Bm to be 1.5 in be supplied to the coil to produce the same
Equation (11.1.4), estimate Ph for Im = 0.5 A value of magnetic flux density as in part (a).
and 8 A. You may neglect leakage and fringing.
11.1.8 Ac measurements with constant voltage ampli- 11.2.4 For the magnetic circuit shown in Figure P11.2.4,
tude reveal that the total core loss of a certain neglecting leakage and fringing, determine the
magnetic circuit is 10 W at f = 50 Hz, and 13 mmf of the exciting coil required to produce a
W at f = 60 Hz. Find the total core loss if the flux density of 1.6 T in the air gap. The material is
frequency is increased to 400 Hz. M-19. The dimensions are lm1 = 60 cm, Am1 =
*11.2.1 Consider the magnetic circuit of Figure 11.2.1(a). 24 cm2, lm2 = 10 cm, Am2 = 16 cm2, lg = 0.1
Let the cross-sectional area AC of the core, be cm, and Ag = 16 cm2.
lm1
lm2
8 cm Am2
N = 2500 lg
turns Coil
12 cm Am1 lm2
Figure P11.2.3 Toroid with circular cross section. Figure P11.2.4
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
PROBLEMS 497
11.2.5 Consider the toroid shown in Figure P11.2.5(a) Figure P11.2.5(b).

made up of three ferromagnetic materials. Ma- 11.2.6 The configuration of a magnetic circuit is given in
terial a is nickel–iron alloy having a mean arc Figure P11.2.6. Assume the permeability of the
length la of 0.6 m; material b is medium sili- ferromagnetic material to be µ = 1000µ0 . Ne-
con steel having a mean arc length lb of 0.4 m; glect leakage, but correct for fringing by increas-
material c is cast steel having a mean arc length ing each linear dimension of the cross-sectional
lc of 0.2 m. Each of the materials has a cross- area by the length of the air gap. The magnetic
material has a square cross-sectional area of 4
sectional area of 0.002 m2. Find the mmf needed
cm2. Find the air-gap flux density, and the mag-
to establish a magnetic flux of φ = 1.2 mWb by
netic field intensity in the air gap.
making use of the magnetization curves given in
Figure P11.2.5 (a) Toroid. (b) Magnetization curves of

typical ferromagnetic materials.
R la
I
lb
+
V N
lc
(a)
1.5
1.4
lloy ste
el
na et
1.3
l–iro h e
cke ns
1.2 Ni co
is li
el
ste
m
iu
1.1
ast
ed
ft c
M
Magnetic flux density, T
1.0
So
0.9
0.8
0.7
n
0.6
iro
st
Ca
0.5
0.4
0.3
0.2
0.1
10 20 30 40 60 80 100 200 300 400 600 1000 2000 4000 10,000
Magnetic field intensity, At/m
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
Figure P11.2.6
5A 5A
1000 turns
1000 turns 0.5 cm 50 cm
50 cm 50 cm
*11.2.7 Consider the magnetic circuit shown in Figure winding. Compute the flux densities in the
P11.2.7. Assume the relative permeability of the two air gaps, Bg1 in the center gap g1 , and
magnetic material to be 1000 and the cross-sec- Bg2 in the end gap g2 .
tional area to be the same throughout. Determine (b) Let gap g2 now be closed by inserting an
the current needed in the coil to produce a flux
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
iron piece of the correct size and infinite
density of 1 T in the center limb, if the excitation permeability so that only the center gap g1 =
coil has 500 turns. 0.1 cm remains. If a flux density of 1.25 T
11.2.8 In the magnetic circuit shown in Figure P11.2.8 is needed in gap g1 , find the current that is
the center leg has the same cross-sectional area needed in the winding.
as each of the outer legs. The coil has 400 turns. 11.2.10 Consider the magnetic circuit in Figure P11.2.10,
The permeability of iron may be assumed to be in which all parts have the same cross section.
infinite. If the air-gap flux density in the left leg The coil has 200 turns and carries a current of 5
is 1.2 T, find: A. The air gaps are g1 = 0.4 cm and g2 = 0.5
(a) The flux density in the air gap of the right cm. Assuming the core has infinite permeability,
leg. compute the flux density in tesla in (a) gap g1 ,
(b) The flux density in the center leg. (b) gap g2 , and (c) the left limb.
11.2.11 The magnetic circuit shown in Figure P11.2.11
(c) The current needed in the coil.
has an iron core which can be considered to be
11.2.9 Figure P11.2.9 shows the cross section of a rect- infinitely permeable. The core dimensions are
angular iron core with two air gaps g1 and g2 . AC = 20 cm2, g = 2 mm, and lC = 100
The ferromagnetic iron can be assumed to have cm. The coil has 500 turns and draws a current
infinite permeability. The coil has 500 turns. of 4 A from the source. Magnetic leakage and
(a) Gaps g1 and g2 are each equal to 0.1 cm, fringing may be neglected. Calculate the follow-
and a current of 1.83 A flows through the ing:
25 cm 25 cm 25 cm 25 cm
0.50 0.75
30 30
cm cm
cm cm
Copyright OUP
PROBLEMS 499
20 cm 20 cm
g2
g1
30 g1 g2
cm
Figure P11.2.11
Source N g
(a) Total magnetic flux. (a) Equivalent series impedance referred to the
(b) Flux linkages of the coil. high-voltage side.
(c) Coil inductance. (b) Equivalent series impedance referred to the
low-voltage side.
(d) Total stored magnetic energy.
(c) Terminal voltage on the high-voltage side
*11.2.12 Repeat Problem 11.2.11 accounting for the core’s
when the transformer is delivering full load
relative permeability of 2000.
at 230 V and 0.866 power factor lagging.
11.2.13 Reconsider Problem 11.2.3. Calculate the coil
11.3.3 A 100-kVA, 2300:230-V, 60-Hz, single-phase
inductance L and the total stored magnetic energy
transformer has the following parameters: R1 =
before and after the air gap is cut.
0.30 -, R2 = 0.003 -, RC1 = 4.5 k-, X1 =
11.3.1 A 10-kVA, 4800:240-V, 60-Hz, single-phase 0.65 -, X2 = 0.0065 -, and Xm1 = 1.0 k-,
transformer has an equivalent series impedance where subscripts 1 and 2 refer to high-voltage and
of 120 + j 300 - referred to the primary high- low-voltage sides, respectively. Set up the equiv-
voltage side. The exciting current of the trans- alent T-circuit of the transformer and determine
former may be neglected. the input current, input voltage, input power, and
(a) Find the equivalent series impedance re- power factor when the transformer is delivering
ferred to the secondary low-voltage side. 75 kW at 230 V and 0.85 lagging power factor.
(b) Calculate the voltage at the primary high- 11.3.4 A 150-kVA, 2400/240-V, 60-Hz, single-phase
voltage terminals if the secondary supplies transformer has the following parameters: R1 =
rated secondary current at 230 V and unity 0.2 -, R2 = 0.002 -, X1 = 0.45 -, X2 =
power factor. 0.0045 -, RC = 10 k-, and Xm = 1.55 k-,
*11.3.2 A 25-kVA, 2300:230-V, 60-Hz, single-phase where the notation is that of Figure 11.3.4. Form
transformer has the following parameters: re- the equivalent T-circuit of the transformer re-
sistance of high-voltage winding 1.5 -, resis- ferred to the high-voltage side, and calculate the
tance of low-voltage winding 0.015 -, leakage supply voltage on the high-voltage side when the
reactance of high-voltage winding 2.4 -, and transformer supplies rated (full) load at 240 V
leakage reactance of low-voltage winding 0.024 and 0.8 lagging power factor.
-. Compute the following: 11.3.5 For a single-phase, 60-Hz transformer rated 500
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
kVA, 2400:480 V, following the notation of Fig- (b) Find the efficiency of the transformer when
ure 11.3.4, the equivalent circuit impedances in it is delivering 7.5 kVA at 230 V and 0.85
ohms are R1 = 0.06, R2 = 0.003, RC = 2000, power factor lagging.
and X1 = 0.3, X2 = 0.012, Xm = 500. The (c) Determine the fraction of rating at which the
load connected across the low-voltage terminals transformer efficiency is a maximum, and
draws rated current at 0.8 lagging power factor calculate the efficiency corresponding to that
with rated voltage at the terminals. load if the transformer is delivering the load
(a) Calculate the high-voltage winding terminal at 230 V and a power factor of 0.85.
voltage, current, and power factor. (d) The transformer is operating at a constant
(b) Determine the transformer series equivalent load power factor of 0.85 on this load cycle:
impedance for the high-voltage and low- 0.85 full load for 8 hours, 0.60 full load for 12
voltage sides, neglecting the exciting current hours, and no load for 4 hours. Compute the
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
of the transformer. transformer’s all-day (or energy) efficiency.
(c) Considering the T-equivalent circuit, find the (e) If the transformer is supplying full load at
Thévenin equivalent impedance of the trans- 230 V and 0.8 lagging power factor, de-
former under load as seen from the primary termine the voltage regulation of the trans-
high-voltage terminals. former. Also, find the power factor at the
high-voltage terminals.
11.3.6 A 20-kVA, 2200:220-V, 60-Hz, single-phase
*11.4.2 A 3-kVA, 220:110-V, 60-Hz, single-phase trans-
transformer has these parameters:
former yields these test data:
Resistance of the 2200-V winding R1 = 2.50 -
Resistance of the 220-V winding R2 = 0.03 - • Open-circuit test: 200 V, 1.4 A, 50 W
Leakage reactance of the 2200-V winding X1 =
• Short-circuit test: 4.5 V, 13.64 A, 30 W
0.1 -
Leakage reactance of the 220-V winding X2 = Determine the efficiency when the transformer
0.1 - delivers a load of 2 kVA at 0.85 power factor
Magnetizing reactance on the 2200-V side Xm = lagging.
25,000 - 11.4.3 A 75-kVA, 230/115-V, 60-Hz transformer was
(a) Draw the equivalent circuits of the trans- tested with these results:
former referred to the high-voltage and low-
• Open-circuit test: 115 V, 16.3 A, 750 W
voltage sides. Label impedances numerically
in ohms. • Short-circuit test: 9.5 V, 326 A, 1200 W
(b) The transformer is supplying 15 kVA at 220 Determine:
V and a lagging power factor of 0.85. Deter- (a) The equivalent impedance in high-voltage
mine the required voltage at the high-voltage terms.
terminals of the transformer.
(b) The voltage regulation at rated load, 0.8
11.4.1 These data were obtained from tests carried out power factor lagging.
on a 10-kVA, 2300:230-V, 60-Hz distribution
transformer: (c) The efficiency at rated load, 0.8 power factor
lagging, and at half-load, unity power factor.
• Open-circuit test, with low-voltage winding ex- (d) The maximum efficiency and the current at
cited: applied voltage 230 V, current 0.45 A, which it occurs.
input power 70 W
11.4.4 A 300-kVA transformer has a core loss of 1.5 kW
• Short-circuit test, with high-voltage winding and a full-load copper loss of 4.5 kW.
excited: applied voltage 120 V, current 4.35 A,
(a) Calculate its efficiency corresponding to 25,
input power 224 W
50, 75, 100, and 125% loads at unity power
(a) Compute the efficiency of the transformer factor.
when it is delivering full load at 230 V and (b) Repeat the efficiency calculations for the
0.85 power factor lagging. 25% load at power factors of 0.8 and 0.6.
Copyright OUP
PROBLEMS 501
(c) Determine the fraction of load for which 11.4.11 The following data were obtained on a 25-
the efficiency is a maximum, and calculate kVA, 2400:240-V, 60-Hz, single-phase distribu-
the corresponding efficiencies for the power tion transformer:
factors of unity, 0.8, and 0.6.
• Open-circuit test with meters on LV side: 240
11.4.5 Consider the solution of Example 11.4.1. By V, 3.2 A, 165 W
means of a phasor diagram, determine the load
power factor for which the regulation is maxi- • Short-circuit test with meters on HV side: 55 V,
mum (i.e., the poorest), and find the correspond- 10.4 A, 375 W
ing regulation. Compute the worst voltage regulation and the
11.4.6 A 10-kVA, 200:400-V, single-phase transformer power factor at which it occurs, when the trans-
gave these test results: former is delivering rated output at rated sec-
ondary terminal voltage of 240 V. Sketch the
• Open-circuit test (LV winding supplied): 200 V, corresponding phasor diagram.
3.2 A, 450 W
*11.4.12 The efficiency of a 400-kVA, single-phase, 60-Hz
• Short-circuit test (HV winding supplied): 38 V, transformer is 98.77% when delivering full-load
25 A, 600 W current at 0.8 power factor, and 99.13% with half-
rated current at unity power factor. Calculate:
Compute the efficiency when the transformer
delivers half its rated kVA at 0.85 power factor (a) The iron loss.
lagging. (b) The full-load copper loss.
*11.4.7 Find the percent voltage regulation and the effi- (c) The efficiency at 3/4 load, 0.9 power factor.
ciency of the transformer for the following cases:
11.4.13 A transformer has its maximum efficiency of
(a) Problem 11.3.1(b). 0.9800 when it delivers 15 kVA at unity power
(b) Problem 11.3.2(c). factor. During the day it is loaded as follows:
12 hours 2 kW at power factor 0.5
11.4.8 The transformer of Problem 11.3.3 is delivering a
full load of 100 kVA at a secondary load voltage
of 230 V. Neglect the exciting current of the
transformer and determine the voltage regulation Determine the all-day efficiency.
if: 11.4.14 A single-phase, 3-kVA, 220:110-V, 60-Hz trans-
former has a high-voltage winding resistance of
(a) The load power factor is 0.8 lagging.
0.3 -, a low-voltage winding resistance of 0.06
(b) The load power factor is 0.8 leading. -, a leakage reactance of 0.8 - on its high-
11.4.9 A 25-kVA, 2400/240-V, 60-Hz, single-phase voltage side, and a leakage reactance of 0.2 -
transformer has an equivalent series impedance on its low-voltage side. The core loss at rated
of 3.45 + j 5.75 - referred to the primary high- voltage is 45 W, and the copper loss at rated
voltage side. The core loss is 120 W. When the load is 100 W. Neglect the exciting current of the
transformer is delivering rated kVA to a load at transformer. Find the per-unit voltage regulation
rated secondary voltage and a 0.85 lagging power when the transformer is supplying full load at 110
factor, find the percent voltage regulation and the V and 0.9 lagging power factor.
efficiency of the transformer. 11.4.15 The transformer of Problem 11.3.4 operates on
11.4.10 A 25-kVA, 2200:220-V, 60-Hz, single-phase the following load cycle:
transformer has an equivalent series impedance 12 hours full load, 0.8 power factor lagging
of 3.5 + j 4.0 - referred to the primary high- 4 hours no load
8 hours one-half full load, unity power
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
voltage side.
factor
(a) Determine the highest value of voltage regu-
Compute the all-day energy efficiency.
lation for full-load output at rated secondary
terminal voltage. 11.4.16 A 75-kVA transformer has an iron loss of 1
kW and a full-load copper loss of 1 kW. If the
(b) At what power factor does it occur? transformer operates on the following load cycle,
(c) Sketch the corresponding phasor diagram. determine the all-day efficiency:
Copyright OUP
8 hours full load at unity power factor (b) Reconnected in Y–?, with the same high-
8 hours no load tension voltage supplied and the same load
8 hours one-half full load at unity power resistors connected?
factor 11.5.3 A three-phase transformer bank consisting of
*11.4.17 A 10-kVA transformer is known to have an iron three 10-kVA, 2300:230-V, 60-Hz, single-phase
loss of 150 W and a full-load copper loss of transformers connected in Y–? is used to step
250 W. If the transformer has the following load down the voltage. The loads are connected to the
cycle, compute its all-day efficiency: transformers by means of a common three-phase
4 hours full load at 0.8 power factor low-voltage feeder whose series impedance is
8 hours 75% full load at 1.0 power factor 0.005 + j 0.01 - per phase. The transform-
12 hours 50% full load at 0.6 power factor ers themselves are supplied by means of a
three-phase high-voltage feeder whose series
11.4.18 Show polarity markings for a single-phase trans-
impedance is 0.5 + j 5.0 - per phase. The
former for (a) subtractive polarity, and (b) addi-
tive polarity. equivalent series impedance of the single-phase
transformer referred to the low-voltage side is
11.4.19 Two single-phase transformers, each rated 2400:
0.12+j 0.24 -. The star point on the primary side
120-V, are to be interconnected for (a) 4800:240- of the transformer bank is grounded. The load
V operation, and (b) 2400:120-V operation. consists of a heating load of 2 kW per phase and
Draw circuit diagrams and show polarity mark- a three-phase induction-motor load of 20 kVA
ings. with a lagging power factor of 0.8, supplied at
11.4.20 Two 1150:115-V transformers are to be inter- 230 V line-to-line.
connected for (a) 2300:230-V operation, and (b) (a) Draw a one-line diagram of this three-phase
1150:230-V operation. Show the interconnec- distribution system.
tions and appropriate polarity markings.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(b) Neglecting the exciting current of the trans-

11.5.1 A one-line diagram of a three-phase distribution former bank, draw the per-phase equivalent
system is given in Figure P11.5.1. Determine circuit of the distribution system.
the line-to-line voltage at the sending end of the
(c) Determine the line current and the line-to-
high-voltage feeder when the transformer deliv-
line voltage at the sending end of the high-
ers rated load at 240 V (line-to-line) and 0.8
voltage feeder.
lagging power factor. Neglect the exciting current
11.5.4 A single-line diagram of a three-phase trans-
of the transformer.
former bank connected to a load is given in
*11.5.2 A 5-MVA, 66:13.2 kV, three-phase transformer Figure P11.5.4. Find the magnitudes of the line-
supplies a three-phase resistive load of 4500 kW to-line voltages, line currents, phase voltages,
at 13.2 kV. What is the load resistance in ohms as and phase currents on either side of the trans-
measured from line to neutral on the high-voltage former bank. Determine the primary to secondary
side of the transformer, if it is: ratio of the line-to-line voltages and the line cur-
(a) Connected in Y–Y? rents.
Load
3-phase high-voltage feeder 3-phase low-voltage feeder
series impedance series impedance
0.25 + j 1.0 Ω/ph 0.00083 + j 0.0033 Ω/ph
3 single-phase transformers
each rated 50 kVA, 2400:240 V
identical with that of Example 11.4.1
Figure P11.5.1
Copyright OUP
PROBLEMS 503
2400 V 208 V Figure P11.5.4

Load
30 kVA balanced
3 single-phase transformers
each rated 10 kVA, 2400:120 V, 60 Hz
11.5.5 Three single-phase 100-kVA, 2400:240-V, 60-Hz (a) Draw a schematic diagram of the arrange-
transformers (each of which has an equivalent se- ment showing all the voltages and currents
ries impedance of 0.045+j 0.16 - referred to its while delivering full load.
low-voltage side) are connected to form a three- (b) Find the permissible kVA rating of the auto-
phase, 4160:240-V transformer bank, which in transformer if the winding currents are not to
turn is connected to a three-phase feeder with exceed those for full-load operation as a two-
an impedance of 0.5 + j 1.5 -/phase. When the winding transformer. How much of that is
three-phase transformer bank delivers 250 kW at transformed by electromagnetic induction?
240 V and 0.866 lagging power factor, determine:
(c) Based on the data given for the two-winding
(a) The transformer winding currents. transformer in Problem 11.4.1, compute
(b) The sending-end voltage (line to line) at the the efficiency of the autotransformer corre-
source. sponding to full load and 0.8 lagging power
11.5.6 Three single-phase, 10-kVA, 2400/120-V, 60- factor. Comment on why the efficiency of
Hz transformers are connected to form a three- the autotransformer is higher than that of the
phase, 4160/208-V transformer bank. Each of two-winding transformer.
the single-phase transformers has an equivalent 11.6.2 A two-winding, single-phase transformer rated
series impedance of 10 + j 25 - referred to the 3 kVA, 220:110 V, 60 Hz is connected as an
high-voltage side. The transformer bank is said autotransformer to transform a line input voltage
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
to deliver 27 kW at 208 V and 0.9 power factor of 330 V to a line output voltage of 110 V and to
leading. deliver a load of 2 kW at 0.8 lagging power factor.
(a) Draw a schematic diagram of transformer Draw the schematic diagram of the arrangement,
connections, and develop a per-phase equiv- label all the currents and voltages, and calculate
alent circuit. all the quantities involved.
11.6.3 A two-winding, 15-kVA, 2300:115-V, 60-Hz,
(b) Determine the primary current, primary volt-
single-phase transformer, which is known to have
age, and power factor.
a core loss of 75 W and a copper loss of 250 W, is
(c) Compute the voltage regulation. connected as an autotransformer to step up 2300
*11.5.7 A three-phase, 600-kVA, 2300:230-V, Y–Y trans- V to 2415 V. With a load of 0.8 power factor
former bank has an iron loss of 4400 W and a full- lagging, what kVA load can be supplied without
load copper loss of 7600 W. Find the efficiency exceeding the current rating of any winding?
of the transformer for 70% full load at 230 V and Determine the efficiency at this load.
0.85 power factor. 11.6.4 A single-phase, two-winding, 10-kVA, 440:110-
11.5.8 Three identical single-phase transformers are to V, 60-Hz transformer is to be connected as an
be connected to form a three-phase bank rated at autotransformer to supply a load at 550 V from a
300 MVA, 230:34.5 kV. For the following con- 440-V supply. Draw a schematic diagram of the
figurations, determine the voltage, current, and connections and determine: (a) The maximum
kVA ratings of each single-phase transformer: (a) kVA rating as an autotransformer. (b) The maxi-
?–?, (b) Y–?, (c) Y–Y, (d) ?–Y. mum apparent power transferred by conduction.
11.6.1 A single-phase, 10-kVA, 2300:230-V, 60-Hz, (c) The maximum apparent power transferred by
two-winding distribution transformer is con- electromagnetic induction.
nected as an autotransformer to step up the volt- *11.6.5 A 15-kVA, 2200:220-V, two-winding, single-
age from 2300 V to 2530 V. phase transformer is connected as an autotrans-
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former to step up voltage from 220 V to 2420 is to be connected as an autotransformer to step

V. Without exceeding the rated current of any down a 600-V source to 480 V.
winding, determine the kVA rating of the auto- (a) Draw a schematic connection diagram as an
transformer, the kVA transformed by transformer autotransformer.
action, and the kVA conducted.
(b) Find the maximum kVA rating as an auto-
transformer.
11.6.6 A 5-kVA, 480:120-V, two-winding, 60-Hz,
single-phase transformer has an efficiency of (c) Compute the efficiency as an autotrans-
95% while delivering rated load at rated voltage former delivering its rated kVA at 480 V and
and 0.8 power factor lagging. This transformer 0.8 power factor lagging.
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12 Electromechanics
12.1 Basic Principles of Electromechanical Energy Conversion
12.2 emf Produced by Windings
12.3 Rotating Magnetic Fields
12.4 Forces and Torques in Magnetic-Field Systems
12.5 Basic Aspects of Electromechanical Energy Converters
12.7 Practical Application: A Case Study—Sensors or Transducers
Problems
12.1 BASIC PRINCIPLES OF ELECTROMECHANICAL ENERGY CONVERSION

Energy available in many forms is often converted to and from electrical form because electric
energy can be transmitted and controlled simply, reliably, and efficiently. Among the energy-
conversion devices, electromechanical energy converters are the most important. Electromechan-
ical energy conversion involves the interchange of energy between an electric system and a
mechanical system, while using magnetic field as a means of conversion.
Devices that convert control signals from one form to another are known as transducers, most
of which have an output signal in the form of electric energy. For example, a potentiometer is used
to convert a mechanical position to an electric voltage, a tachometer generator converts a velocity
into a voltage (dc or ac), and a pressure transducer indicates a pressure drop (or rise) in terms
of a corresponding drop (or rise) in electric potential. Thus, a transducer translates the command
signal appropriately into an electrical form usable by the system, and forms an important part
of control systems. Electromechanical transducers form a link between electric and mechanical
systems.
When the energy is converted from electrical to mechanical form, the device is displaying
motor action. A generator action involves converting mechanical energy into electric energy. The
electromechanical energy-conversion process can be expressed as
505
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506 ELECTROMECHANICS
Motor
→
Electric energy Mechanical energy
←
Generator
Electromechanical energy converters, simply known as electric machines, embody three essential
features: (1) an electric system, (2) a mechanical system, and (3) a coupling field. Figure 12.1.1
is a schematic representation of an ideal electric machine (or a lossless electromechanical device)
for which the following relations hold:
Electric input (or output) energy vi?t = mechanical output (or input) energy T ωm ?t
or
Electric input (or output) power vi = mechanical output (or input) power T ωm (12.1.1)
where v and i are the voltage and the current associated with the electrical port, and T and ωm are
the torque and the angular rotational velocity associated with the mechanical port.
The principle of conservation of energy may be stated as follows: Energy can be neither
created nor destroyed, even though, within an isolated system, energy may be converted from one
form to another form, and transferred from an energy source to an energy sink. The total energy
in the system is constant.
A practical electromechanical system with losses can be represented by adding on the lossy
portion of the electric system and the lossy portion of the mechanical system modeled externally.
Excluding all types of dissipation and losses makes the energy-conversion part to be lossless or
conservative with a coupling field.
Both electric and magnetic fields store energy, from which useful mechanical forces and
torques can be derived. With a normal working electric field intensity of about 3 × 106 V/m, the
stored electric-energy density is on the order of
1 1 10−9
ε0 E 2 = (3 × 106 )2 ∼
= 40 J/m3
2 2 36π
where ε0 is the permittivity of free space, given by 10−6 /36π or 8.854 × 10−12 F/m, and E is
the electric field intensity. This corresponds to a force density of 40 N/m2. The stored magnetic
energy density in air, on the other hand, with a normal working magnetic flux density of about
1.6 T, comes to
1 B2 1 1.62 ∼
= = 1 × 106 J/m3
2 µ0 2 4π × 10−7
where µ0 is the permeability of free space, and B is the magnetic flux density. As this is nearly
25,000 times as much as for the electric field, almost all industrial electric machines are magnetic
Figure 12.1.1 Schematic repre-

i Lossless sentation of a lossless electrome-
electromechanical chanical device.
Electrical v Mechanical
device
port port
with coupling
field
ωm, T
Motor
v, i Generator T, ωm
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12.1 BASIC PRINCIPLES OF ELECTROMECHANICAL ENERGY CONVERSION 507
in principle and are magnetic-field devices.

Three basic principles associated with all electromagnetic devices are (1) induction, (2)
interaction, and (3) alignment.
Induction
The essentials for producing an emf by magnetic means are electric and magnetic circuits, mutually
interlinked. Figure 12.1.2(a) shows a load (or sink or motor) convention with the induced emf
(or back emf) e directed in opposition to the positive current, in which case Faraday’s law of
induction,
dλ dφ
e=+ = +N (12.1.2a)
dt dt
applies, where λ is the flux linkages, N is the number of turns, and φ is the flux. On the other
hand, the induced emf e (or generated emf) acting in the direction of positive current, as shown
in Figure 12.1.2(b) with a source (or generator) convention, satisfies Faraday’s law of induction,
dλ dφ
e=− = −N (12.1.2b)
dt dt
The change in flux linkage in a coil may occur in one of the following three ways:
1. The coil remaining stationary with respect to the flux, the flux varies in magnitude with
time. Since no motion is involved, no energy conversion takes place. Equation (12.1.2a)
gives the transformer emf (or the pulsational emf ) as in the case of a transformer (see
Chapter 11), in which a time-varying flux linking a stationary coil yields a time-varying
voltage.
2. The flux remaining constant, the coil moves through it. A conductor or a coil moving
through a magnetic field will have an induced voltage, known as the motional emf (or
speed emf ), given by
i R R i Figure 12.1.2 Circuit conven-

+ + + tions. (a) Load (or sink or motor)
+ convention. Note that the power
v e e v absorbed by the circuit is posi-
−
tive when v and i are positive, and
when current flows in the direc-
− − − tion of voltage drop. (b) Source
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(or generator) convention. Note
v = Ri + e = Ri + dλ = Ri + N dφ
dt dt that the power delivered by this
(a) circuit to the external circuit is
positive when v and i are posi-
i R R i tive, and when current flows out
+ + + of the positive terminal.
+
v e e v
−
− − −
v = e − iR = − dλ − iR = −N dφ − iR
dt dt
(b)
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Motional emf e = BlU (12.1.3)
which is often called the cutting-of-flux equation, where B is the flux density of a non-
time-varying, uniform magnetic field, l is the length of the conductor, U is the velocity
¯ and Ū are mutually perpendicular in their directions. If the
of the conductor, and B̄, l,
motion is rotary in nature, it is also known as rotational voltage. The direction for the
motional emf can be worked out from the right-hand rule: if the thumb, first, and second
fingers of the right hand are extended so that they are mutually perpendicular to each
other, and if the thumb represents the direction of Ū and the first finger the direction of
¯ This is depicted
B̄, the second finger will then represent the direction of the emf along l.
in Figure 12.1.3(a).
The generation of motional emf is further illustrated by a simple example, as shown
in Figure 12.1.3(b), where a single-turn coil formed by the moving (or sliding) conductor
(moving with velocity U), the two conducting rails, and the voltmeter are situated in a
magnetic field of flux density B. The conductor moving with a velocity U, in a direction at
right angles to both B and l, sweeps the area lU in 1 second. The flux per unit time in this
area is BlU, which is also the flux linkage per unit time with the single-turn coil. Thus,
the induced emf e is simply given by BlU. The motional emf (or speed emf) is always
associated with the conversion of energy between the mechanical and electrical forms.
3. The coil may move through a time-varying flux; that is to say, both changes (1) and (2)
may occur together. Usually one of the two phenomena is so predominant in a given device
that the other may be neglected for the purposes of analysis.
Because magnetic poles occur in pairs (north and south) and the movement of a conductor
through a natural north–south sequence induces an emf that changes direction in accordance with
the magnetic polarity (i.e., an alternating emf), the devices are inherently ac machines.
Figure 12.1.3 Generation of motional emf. (a) Right-hand rule. (b) Simple example.
--`,,,``,,`,```,``,`````,```,``
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Interaction
Current-carrying conductors, when placed in magnetic fields, experience mechanical force.
Considering only the effect of the magnetic field, the Lorentz force equation gives the force
F as
F = BlI (12.1.4)
when a current-carrying conductor of length l is located in a uniform magnetic field of flux
density B, and the direction of the current in the conductor is perpendicular to the direction of the
magnetic field. The direction of the force is orthogonal (perpendicular) to the directions of both
the current-carrying conductor and the magnetic field. Equation (12.1.4) is often used in electric
machine analysis.
The principle of interaction is illustrated in Figure 12.1.4, in which B̄ is the flux density, I¯
the current, and F̄ the force. Shown in Figure 12.1.4(a) is the flux density B̄ of an undisturbed
uniform field, on which an additional field is imposed due to the introduction of a current-carrying
conductor. For the case in which the current is directed into and perpendicular to the plane of
the paper, the resultant flux distribution is depicted in Figure 12.1.4(b). It can be seen that in the
neighborhood of the conductor the resultant flux density is greater than B on one side and less
than B on the other side. The direction of the mechanical force developed is such that it tends to
restore the field to its original undisturbed and uniform configuration. Figure 12.1.4(c) shows the
conditions corresponding to the current being in the opposite direction to that of Figure 12.1.4(b).
The force is always in such a direction that the energy stored in the magnetic field is minimized.
Figure 12.1.5 shows a one-turn coil in a magnetic field and illustrates how torque is produced by
forces caused by the interaction between current-carrying conductors and magnetic fields.
Alignment
Pieces of highly permeable material, such as iron, situated in ambient medium of low permeability,
such as air, in which a magnetic field is established, experience mechanical forces that tend to
align them with the field direction in such a way that the reluctance of the system is minimized (or
the inductance of the system is maximized). Figure 12.1.6 illustrates this principle of alignment
B Figure 12.1.4 Principle of interaction.
I
F F
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(a) (b) (c)
Figure 12.1.5 Torque produced by forces caused by interaction of

current-carrying conductors and magnetic fields.
F
I
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Ferromagnetic pieces Figure 12.1.6 Principle of alignment.
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F
Magentic flux lines
and shows the direction of forces. The force is always in a direction that reduces the net magnetic
reluctance and shortens the magnetic flux path.
A mechanical force is exerted on ferromagnetic material, tending to align it with or bring it
into the position of the densest part of the magnetic field. This force is the familiar attraction of a
magnet for pieces of iron in its field. In magnetic circuits, for example, definite forces are exerted
on the iron at the air–iron boundary. Energy changes associated with a differential displacement of
the iron cause the mechanical force. This force is the essential operating mechanism of many elec-
tromagnetic devices, such as lifting magnets, magnetic clutches, chucks, brakes, switches (known
as contactors), and relays. Solenoid-operated (solenoid being another name for the operating coil)
valves are common elements in piping systems. Actuators used in control systems operate due to
the mechanical force or torque converted from the electric, pneumatic, or hydraulic inputs.
In motor and generator action, the magnetic fields tend to line up, pole to pole. When their
complete alignment is prevented by the need to furnish torque to a mechanical shaft load, motor
action results when electric to mechanical energy conversion takes place. On the other hand, when
the alignment is prevented by the application of a mechanical torque to the rotor from a source of
mechanical energy, generator action results when mechanical to electric energy conversion takes
place.
EXAMPLE 12.1.1
A magnetic crane used for lifting weights can be modeled and analyzed as a simple magnetic
circuit, as shown in Figure E12.1.1. Its configuration consists of two distinct pieces of the same
magnetic material with two air gaps. Obtain an expression for the total pulling force on the bar
in terms of the flux density B in the air-gap region and the cross-sectional area A perpendicular
to the plane of paper, while making reasonable approximations.
Solution
Reasonable approximations include infinite permeability of the magnetic material, as well as

neglecting leakage and fringing. The magnetic energy stored in an incremental volume of the
air-gap region is given by

1 B
dWm = B dv
2 µ0
where B and H (= B/µ0 ) are in the same direction. Working with one pole of the magnetic circuit,
in view of the symmetry, the incremental change in volume is dv = A dg. Hence,
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1 B2
dWm = A dg
2 µ0
The definition of work gives us
dW = F dg
where F is the pulling force per pole on the bar. While a magnetic pull is exerted upon the bar,
an energy dW equal to the magnetic energy dWm stored in the magnetic field is expended. Thus,
dWm = dW
or

1 B2
A dg = F dg
2 µ0
which yields the pulling force per pole on the bar as

1 B2
F = A
2 µ0
The total pulling on the bar is then given by

B2
Ftotal = 2F = A
µ0
Figure E12.1.1 Simple magnetic circuit for weight

I lifting.
Core or yoke of uniform
cross-sectional area A
N turns
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g g
Bar
EXAMPLE 12.1.2
Consider the arrangement shown in Figure E12.1.2. A conductor bar of length l is free to move
along a pair of conducting rails. The bar is driven by an external force at a constant velocity of
U m/s. A constant uniform magnetic field B̄ is present, pointing into the paper of the book page.
Neglect the resistance of the bar and rails, as well as the friction between the bar and the rails.
(a) Determine the expression for the motional voltage across terminals 1 and 2. Is terminal
1 positive with respect to terminal 2?
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(b) If an electric load resistance R is connected across the terminals, what are the current and
power dissipated in the load resistance? Show the direction of current on the figure.
(c) Find the magnetic-field force exerted on the moving bar, and the mechanical power
required to move the bar. How is the principle of energy conservation satisfied?
(d) Since the moving bar is not accelerating, the net force on the bar must be equal to zero.
How can you justify this?
Conducting Figure E12.1.2

rail
1
dl
R l B U
Conducting bar
2
Conducting
(a) rail
1 I
dl
l B U
I
2 I
(b)
Solution
(a) U, B, and l being perpendicular to each other, as per the right-hand rule, the motional
voltage is e = BlU . 1 is positive with respect to 2, since the resulting current (when the
switch is closed) produces a flux opposing the original B, thereby satisfying Lenz’s law.
(b) I = BlU/R; P = I 2 R = (BlU )2 /R.
(c) The magnitude of the induced magnetic-field force exerted on the moving bar is BlI, and
it opposes the direction of motion. The mechanical force is equal and opposite to the
induced field force. Hence the mechanical power required to move the bar is
BlU (BlU )2
(BlI )U = Bl U=
R R
which is the same as the electric power dissipated in the resistor. Energy (from the
mechanical source) that is put in to move the conductor bar is expended (or trans-
ferred) as heat in the resistor, thereby satisfying the principle of energy conserva-
tion.
(d) In order to move the conductor bar at a constant velocity, it is necessary to impress a
mechanical force equal and opposite to the induced field force. Hence the net force on
the bar is equal to zero.
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EXAMPLE 12.1.3
A loudspeaker is a common electrochemical transducer in which vibration is caused by changes in
the input current to a coil which, in turn, is coupled to a magnetic structure that can produce time-
varying forces on the loudspeaker diaphragm. Figure E12.1.3(a) shows the schematic diagram of
a loudspeaker, Figure E12.1.3(b) is a simplified model, Figure E12.1.3(c) is a free-body diagram
of the forces acting on the loudspeaker diaphragm, and Figure E12.1.3(d) is the electrical model.
The force exerted on the coil is also exerted on the mass of the loudspeaker diaphragm.
Electric Sound
input output k
+
v m du
− f=m
dt
(a) d
dx
x u=
dt
N
Spring
N turns Mass of dx
loudspeaker u=
Permanent dt
magnet S diaphragm fk
m fe = Bli
fd
Moving
N x
coil
(b) (c)
+ L R +
v e = Blu
− −
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(d)
Figure E12.1.3 Loudspeaker.
Develop the equation of motion for the electrical and mechanical sides of the device and
determine the frequency response U (j ω)/V (j ω) of the loudspeaker using phase analysis, and
neglecting the coil inductance.
Solution
The electrical side is described by

di di
v=L
+ Ri + e = L + Ri + Blu
dt dt
where B is the flux density and l is the length of the coil given by 2π N r, in which N is the number
of coil turns and r the coil radius. Note that e is the emf generated by the motion of the coil in the
magnetic field.
The mechanical side is described by
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du
= fe − fd − fk = fe − du − kx = Bli − du − kx
f =m
dt
where d represents the damping coefficient, k represents the spring constant, and fe is the magnetic
force due to current flow in the coil. Using phasor techniques, we have
V (j ω) = j ωLI (j ω) + RI (j ω) + BlU (j ω)
and
k
(j ωm + d)U (j ω) + U (j ω) = BlI (j ω)
jω
Neglecting the coil inductance L, we get
V (j ω) − BlU (j ω)
I (j ω) =
R
The frequency response of the loudspeaker is then given by
U (j ω Bl jω
=
V (j ω) Rm (j ω) + j ω(d/m + B 2 l 2 /Rm) + k/m
2
12.2 emf PRODUCED BY WINDINGS

The time variation of emf for a single conductor corresponds to the spatial variation of air-gap flux
density. By suitable winding design, the harmonics can be reduced appreciably, and the waveform
of the generated emf can be made to approach a pure sine shape.
Figure 12.2.1 shows an elementary single-phase, two-pole synchronous machine. In al-
most all cases, the armature winding of a synchronous machine is on the stator and the field
winding is on the rotor, because it is constructionally advantageous to have the low-power
field winding on the rotating member. The field winding is excited by direct current, which
is supplied by a dc source connected to carbon brushes bearing on slip rings (or collector
rings). The armature windings, though distributed in the slots around the inner periphery of
the stator in an actual machine, are shown in Figure 12.2.1(a) for simplicity as consisting
of a single coil of N turns, indicated in cross section by the two sides a and −a placed in
diametrically opposite narrow slots. The conductors forming these coil sides are placed in
slots parallel to the machine shaft and connected in series by means of the end connections.
The coil in Figure 12.2.1(a) spans 180° (or a complete pole pitch, which is the peripheral
distance from the centerline of a north pole to the centerline of an adjacent south pole) and
is hence known as a full-pitch coil. For simplicity and convenience, Figure 12.2.1(a) shows
only a two-pole synchronous machine with salient-pole construction; the flux paths are shown
by dashed lines. Figure 12.2.1(b) illustrates a nonsalient-pole or cylindrical-rotor construc-
tion. The stator winding details are not shown and the flux paths are indicated by dashed
lines.
The space distribution of the radial air-gap flux density around the air-gap periphery can be
made to approximate a sinusoidal distribution by properly shaping the rotor pole faces facing the
air gap,
B = Bm cos β (12.2.1)
where Bm is the peak value at the rotor pole center and β is measured in electrical radians from
the rotor pole axis (or the magnetic axis of the rotor), as shown in Figure 12.2.1. The air-gap flux
per pole is the integral of the flux density over the pole area. For a two-pole machine,
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12.2 emf PRODUCED BY WINDINGS 515
β Figure 12.2.1 Elementary single-

N-turn coil on stator Magnetic axis of rotor phase two-pole synchronous ma-
chine. (a) Salient-pole machine.
Field winding
(b) Nonsalient-pole or cylindrical-
+ rotor machine.
a
θ = ωt; θ = ω
N
e Magnetic axis
+
of stator coil
S +
−a
− +
Magnetic flux path
(a)
Stator winding located

Air gap
in armature slots
(not shown here)
+
N +
Mean magnetic
+
flux path
+
+
S + Teeth of laminated
+
armature core
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Cylindrical rotor field winding
(b)
+π/2
φ= Bm cos β lr dβ = 2Bm lr (12.2.2)
−π/2
and for a P-pole machine,

2
2Bm lr φ= (12.2.3)
P
where l is the axial length of the stator and r is the average radius at the air gap. For a P-pole
machine, the pole area is 2/P times that of a two-pole machine of the same length and diameter.
The flux linkage with the stator coil is Nφ when the rotor poles are in line with the magnetic
axis of the stator coil. If the rotor is turned at a constant speed ω by a source of mechanical power
connected to its shaft, the flux linkage with the stator coil varies as the cosine of the angle between
the magnetic axes of the stator coil and the rotor,
λ = N φ cos ωt (12.2.4)
where time t is arbitrarily taken as zero when the peak of the flux-density wave coincides with
the magnetic axis of the stator coil. By Faraday’s law, the voltage induced in the stator coil is
given by
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dλ dφ
e=− = ωN φ sin ωt − N cos ωt (12.2.5)
dt dt
The minus sign associated with Faraday’s law in Equation (12.2.5) implies generator reference
directions, as explained earlier. Considering the right-hand side of Equation (12.2.5), the first term
is a speed voltage caused by the relative motion of the field and the stator coil. The second term
is a transformer voltage, which is negligible in most rotating machines under normal steady-state
operation because the amplitude of the air-gap flux wave is fairly constant. The induced voltage
is then given by the speed voltage itself,
e = ωN φ sin ωt (12.2.6)
Equation (12.2.6) may alternatively be obtained by the application of the cutting-of-flux concept
given by Equation (12.1.3), from which the motional emf is given by the product of Bcoil times
the total active length of the conductors leff in the two coil sides times the linear velocity of the
conductor relative to the field, provided that these three are mutually perpendicular. For the case
under consideration, then,
e = Bcoil leff v = (Bm sin ωt)(2lN )(rωm )
or

r2ω 2
e = (Bm sin ωt)(2lN ) = ωN 2Bm lr sin ωt (12.2.7)
P P
which is the same as Equation (12.2.6) when the expression for φ, given by Equation (12.2.3), is
substituted.
The resulting coil voltage is thus a time function having the same sinusoidal waveform as
the spatial distribution B. The coil voltage passes through a complete cycle for each revolution
of the two-pole machine of Figure 12.2.1. So its frequency in hertz is the same as the speed of
the rotor in revolutions per second (r/s); that is, the electrical frequency is synchronized with the
mechanical speed of rotation. Thus, a two-pole synchronous machine, under normal steady-state
conditions of operation, revolves at 60 r/s, or 3600 r/min, in order to produce 60-Hz voltage. For
a P-pole machine in general, however, the coil voltage passes through a complete cycle every
time a pair of poles sweeps, i.e., P/2 times in each revolution. The frequency of the voltage wave
is then given by
P n
f = · Hz (12.2.8)
2 60
where n is the mechanical speed of rotation in r/min. The synchronous speed in terms of the
frequency and the number of poles is given by
120f
n= r/min (12.2.9)
P
The radian frequency ω of the voltage wave in terms of ωm , the mechanical speed in radians per
second (rad/s), is given by
P
ω= ωm (12.2.10)
2
Figure 12.2.2 shows an elementary single-phase synchronous machine with four salient poles;
the flux paths are shown by dashed lines. Two complete wavelengths (or cycles) exist in the
flux distribution around the periphery, since the field coils are connected so as to form poles of
alternate north and south polarities. The armature winding now consists of two coils (a1 , −a1 )
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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and (a2 , −a2 ), connected in series by their end connections. The span of each coil is one-half
wavelength of flux, or 180 electrical degrees for the full-pitch coil. Since the generated voltage
now goes through two complete cycles per revolution of the rotor, the frequency is then twice the
speed in revolutions per second, consistent with Equation (12.2.8).
The field winding may be concentrated around the salient poles, as shown in Figures 12.2.1(a)
and 12.2.2, or distributed in slots around the cylindrical rotor, as in Figure 12.2.1(b). By properly
shaping the pole faces in the former case, and by appropriately distributing the field winding in
the latter, an approximately sinusoidal field is produced in the air gap.
A salient-pole rotor construction is best suited mechanically for hydroelectric generators
because hydroelectric turbines operate at relatively low speeds, and a relatively large number
of poles is required in order to produce the desired frequency (60 Hz in the United States),
in accordance with Equation (12.2.9). Salient-pole construction is also employed for most
synchronous motors.
The nonsalient-pole (smooth or cylindrical) rotor construction is preferred for high-speed
turbine-driven alternators (known also as turbo alternators or turbine generators), which are
usually of two or four poles driven by steam turbines or gas turbines. The rotors for such machines
may be made either from a single steel forging or from several forgings shrunk together on the
shaft.
Going back to Equation (12.2.6), the maximum value of the induced voltage is
Emax = ωN φ = 2πf N φ (12.2.11)
and the rms value is
2π
Erms = √ f N φ = 4.44 f N φ (12.2.12)
2
which are identical in form to the corresponding emf equations for a transformer. The effect of
a time-varying flux in association with stationary transformer windings is the same as that of the
relative motion of a coil and a constant-amplitude spatial flux-density wave in a rotating machine.
The space distribution of flux density is transformed into a time variation of voltage because of the
time element introduced by mechanical rotation. The induced voltage is a single-phase voltage
for single-phase synchronous machines of the nature discussed so far. As pointed out earlier, to
avoid the pulsating torque, the designer could employ polyphase windings and polyphase sources
to develop constant power under balanced conditions of operation.
−a1 Figure 12.2.2 Elementary single-

Magnetic flux path phase, four-pole synchronous machine.
+
+
a1 N N a2
+
+
−a2
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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In fact, with very few exceptions, three-phase synchronous machines are most commonly
used for power generation. In general, three-phase ac power systems, including power generation,
transmission, and usage, have grown most popular because of their economic advantages. An
elementary three-phase, two-pole synchronous machine with one coil per phase (chosen for
simplicity) is shown in Figure 12.2.3(a). The coils are displaced by 120 electrical degrees from
each other in space so that the three-phase voltages of positive phase sequence a–b–c, displaced
by 120 electrical degrees from each other in time, could be produced. Figure 12.2.3(b) shows
an elementary three-phase, four-pole synchronous machine with one slot per pole per phase. It
has 12 coil sides or six coils in all. Two coils belong to each phase, which may be connected in
series in either wye or delta, as shown in Figures 12.2.3(c) and (d). Equation (12.2.12) can be
applied to give the rms voltage per phase when N is treated as the total series turns per phase.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
The coils may also be connected in parallel to increase the current rating of the machine. In
actual ac machine windings, instead of concentrated full-pitch windings, distributed fractional-
pitch armature windings are commonly used to make better use of iron and copper and to make
waveforms of the generated voltage (in time) and the armature mmf (in space) as nearly sinusoidal
as possible. That is to say, the armature coils of each phase are distributed in a number of slots, and
the coil span may be shorter than a full pitch. In such cases, Equation (12.2.12) is modified to be
Erms = 4.44kW f Nph φ V/phase (12.2.13)
where kW is a winding factor (less than unity, usually about 0.85 to 0.95), and N ph is the number
of series turns per phase.
Special mechanical arrangements must be provided when making electrical connections to
the rotating member. Such connections are usually made through carbon brushes bearing on either
a slip ring or a commutator, mounted on—but insulated from—the rotor shaft and rotating with
the rotor. A slip ring is a continuous ring, usually made of brass, to which only one electrical
connection is made. For example, two slip rings are used to supply direct current to the field
winding on the rotor of a synchronous machine. A commutator, on the other hand, is a mechanical
switch consisting of a cylinder formed of hard-drawn copper segments separated and insulated
from each other by mica.
In the conventional dc machine (with a closed continuous commutator winding on its
armature), for example, full-wave rectification of the alternating voltage induced in individual
armature coils is achieved by means of a commutator, which makes a unidirectional voltage
available to the external circuit through the stationary carbon brushes held against the commutator
surface. The armature windings of dc machines are located on the rotor because of this necessity for
commutation and are of the closed continuous type, known as lap and wave windings. The simplex
lap winding has as many parallel paths as there are poles, whereas the simplex wave winding
always has two parallel paths. The winding connected to the commutator, called the commutator
winding, can be viewed as a pseudostationary winding because it produces a stationary flux when
carrying a direct current, as a stationary winding would. The direction of the flux axis is determined
by the position of the brushes. In a conventional dc machine, in fact, the flux axis corresponds
to the brush axis (the line joining the two brushes). The brushes are located so that commutation
(i.e., reversal of current in the commutated coil) occurs when the coil sides are in the neutral
zone, midway between the field poles. The axis of the armature mmf is then in the quadrature
axis, whereas the stator mmf acts in the field (or direct) axis. Figure 12.2.4 shows schematic
representations of a dc machine. The commutator is thus a device for changing the connections
between a rotating closed winding and an external circuit at the instants when the individual
coil-generated voltages reverse. In a dc machine, then, this arrangement enables a constant and
unidirectional output voltage. The armature mmf axis is fixed in space because of the switching
Copyright OUP
b1
−c1 −a1
−c
a1 c1
a N + b N + + S
−b2 −b1
+
−b −a
S S + + N
c2 a2
c
−a2 −c2
b2
(a) (b)
a1
−a1
a2 a1 −c2
−a2 −a1 c2
−c2 −b2
c2 b2 a2 −c1
−c1 −b1
c1 b1 −a2 c1
b1 −b1 b2 −b2
(c) (d)
Figure 12.2.3 Elementary three-phase synchronous machines. (a) Salient two-pole machine. (b) Salient
four-pole machine. (c) Phase windings connected in wye. (d) Phase windings connected in delta.
action of the commutator (even though the closed armature winding on the rotor is rotating), so
the commutator winding becomes pseudostationary.
The action of slip rings and that of a commutator differ in only one way. The conducting coil
connected to the slip ring is always connected to the brush, regardless of the mechanical speed ωm
of the rotor and the rotor position, but with the commutator, the conducting coil conducts current
only when it is physically under the commutator brush, i.e., when it is stationary with respect to
the commutator brush. This difference is illustrated in Figure 12.2.5.
A dc machine then operates with direct current applied to its field winding (generally located
on the salient-pole stator of the machine) and to a commutator (via the brushes) connected to the
armature winding situated inside slots on the cylindrical rotor, as shown schematically in Figure
12.2.4. In a dc machine the stator mmf axis is fixed in space, and the rotor mmf axis is also fixed in
space, even when the rotor winding is physically rotating, because of the commutator action, which
was briefly discussed earlier. Thus, the dc machine will operate under steady-state conditions,
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Field
structure
Quadrature axis,
rotor mmf axis
Direct axis,
+
stator mmf
+
or field axis
+
+
+ + +
Field Field
Armature
coil Armature
Brushes on commutator
(not shown)
(a) (b)
Figure 12.2.4 Schematic representations of a dc machine. (a) Schematic arrangement. (b) Circuit represen-
tation.
whatever the rotor speed ωm . The armature current in the armature winding is alternating. The
action of the commutator is to change the armature current from a frequency governed by the
mechanical speed of rotation to zero frequency at the commutator brushes connected to the
external circuit.
For the case of a dc machine with a flux per pole of φ, the total flux cut by one conductor in
one revolution is given by φP , where P is the number of poles of the machine. If the speed of
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
rotation is n r/min, the emf generated in a single conductor is given by

φP n
e= (12.2.14)
60
For an armature with Z conductors and α parallel paths, the total generated armature emf Ea is
given by
P φnZ
Ea = (12.2.15)
60α
Since the angular velocity ωm is given by 2π n/60, Equation (12.2.15) becomes
PZ
Ea = φωm = Ka φωm (12.2.16)
2π α
where Ka is the design constant given by P Z/2π α. The value obtained is the speed voltage
appearing across the brush terminals in the quadrature axis (see Figure 12.2.4) due to the field
excitation producing φ in the direct axis. For this reason, in the schematic circuit representation of
a dc machine, the field axis and the brush axis are shown in quadrature, i.e., perpendicular to each
other. The generated voltage, as observed from the brushes, is the sum of the rectified voltages of
all the coils in series between brushes. If the number of coils is sufficiently large, the ripple in the
waveform of the armature voltage (as a function of time) becomes very small, thereby making
the voltage direct or constant in magnitude.
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ωm ωm
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Instant 1 Instant 1
ωm ωm
Instant 2 Instant 2
(a) (b)
Figure 12.2.5 (a) Slip-ring action. (b) Commutator action connections.
The instantaneous electric power associated with the speed voltage should be equal to the
instantaneous mechanical power associated with the electromagnetic torque Te, the direction of
power flow being determined by whether the machine is operating as a motor or a generator,
Te ωm = Ea Ia (12.2.17)
where Ia is the armature current (dc). With the aid of Equation (12.2.15), it follows that
Te = Ka φIa (12.2.18)
which is created by the interaction of the magnetic fields of stator and rotor. If the machine is acting
as a generator, this torque opposes rotation; if the machine is acting as a motor, the electromagnetic
torque acts in the direction of the rotation.
In a conventional dc machine, the brush axis is fixed relative to the stator. If, however, there
is continuous relative motion between poles and brushes, the voltage at the brushes will in fact
be alternating. This principle is made use of in ac commutator machines.
EXAMPLE 12.2.1
A two-pole, three-phase, 60-Hz, wye-connected, round-rotor synchronous generator has Na = 12
turns per phase in each armature phase winding and flux per pole of 0.8 Wb. Find the rms induced
voltage in each phase and the terminal line-to-line rms voltage.
Solution
Emax = 2πf Na φ = 2π × 60 × 12 × 0.8 = 3619 V
√
Erms = 3619/ 2 = 2559.5 V
√
VT = 2559.5 3 = 4433 V line-to-line rms
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EXAMPLE 12.2.2
The armature of a four-pole dc machine has a simplex lap wound commutator winding (which has
the number of parallel paths equal to the number of poles) with 120 two-turn coils. If the flux per
pole is 0.02 Wb, calculate the dc voltage appearing across the brushes located on the quadrature
axis when the machine is running at 1800 r/min.
Solution
This example can be solved by the direct application of Equation (12.2.15),

P φnZ
Ea =
α × 60
For our example, P = 4, φ = 0.02, n = 1800, the number of conductors Z = 120 × 2 × 2 = 480
and the number of parallel paths α = 4 for the simplex lap winding (the same as the number of
poles). Therefore,
4 × 0.02 × 1800 × 480
Ea = = 288 V dc
4 × 60
12.3 ROTATING MAGNETIC FIELDS

When a machine has more than two poles, only a single pair of poles needs to be considered
because the electric, magnetic, and mechanical conditions associated with every other pole pair
are repetitions of those for the pole pair under consideration. The angle subtended by one pair
of poles in a P-pole machine (or one cycle of flux distribution) is defined to be 360 electrical
degrees, or 2π electrical radians. So the relationship between the mechanical angle Qm and the
angle Q in electrical units is given by
P
θ= θm (12.3.1)
2
because one complete revolution has P/2 complete wavelengths (or cycles). In view of this
relationship, for a two-pole machine, electrical degrees (or radians) will be the same as mechanical
degrees (or radians).
In this section we set out to show that a rotating field of constant amplitude and sinusoidal
space distribution of mmf around a periphery of the stator is produced by a three-phase winding
located on the stator and excited by balanced three-phase currents when the respective phase
windings are wound 2π/3 electrical radians (or 120 electrical degrees) apart in space. Let us
consider the two-pole, three-phase winding arrangement on the stator shown in Figure 12.3.1.
The windings of the individual phases are displaced by 120 electrical degrees from each other in
space around the air-gap periphery. The reference directions are given for positive phase currents.
The concentrated full-pitch coils, shown here for simplicity and convenience, do in fact represent
the actual distributed windings producing sinusoidal mmf waves centered on the magnetic axes
of the respective phases. Thus, these three sinusoidal mmf waves are displaced by 120 electrical
degrees from each other in space. Let a balanced three-phase excitation be applied with phase
sequence a–b–c,
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
ia = I cos ωs t; ib = I cos(ωs t − 120°); ic = I cos(ωs t − 240°) (12.3.2)

where I is the maximum value of the current, and the time t = 0 is chosen arbitrarily when the
a-phase current is a positive maximum. Each phase current is an ac wave varying in magnitude
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12.3 ROTATING MAGNETIC FIELDS 523
sinusoidally with time. Hence, the corresponding component mmf waves vary sinusoidally with
time. The sum of these components yields the resultant mmf.
Analytically, the resultant mmf at any point at an angle θ from the axis of phase a is given by
F (θ) = Fa cos θ + Fb cos(θ − 120°) + Fc cos(θ − 240°) (12.3.3)
But the mmf amplitudes vary with time according to the current variations,
Fa = Fm cos ωs t; Fb = Fm cos(ωs t − 120°); Fc = Fm cos(ωs t − 240°) (12.3.4)
Then, on substitution, it follows that
F (θ, t) = Fm cos θ cos ωs t + Fm cos(θ − 120°) cos(ωs t − 120°)
+ Fm cos(θ − 240°) cos(ωs t − 240°) (12.3.5)
By the use of the trigonometric identity
1 1
cos α cos β = cos(α − β) + cos(α + β)
2 2
and noting that the sum of three equal sinusoids displaced in phase by 120° is equal to zero,
Equation (12.3.5) can be simplified as
3
F (θ, t) = Fm cos(θ − ωs t) (12.3.6)
2
which is the expression for the resultant mmf wave. It has a constant amplitude 3/2 Fm, is a
sinusoidal function of the angle θ, and rotates in synchronism with the supply frequency; hence it
is called a rotating field. The constant amplitude is 3/2 times the maximum contribution Fm of any
one phase. The angular velocity of the wave is ωs = 2πfs electrical radians per second, where
fs is the frequency of the electric supply in hertz. For a P-pole machine, the rotational speed is
given by
2 120fs
ωm = ωs rad/s or n= r/min (12.3.7)
P P
which is the synchronous speed.
The same result may be obtained graphically, as shown in Figure 12.3.2, which shows
the spatial distribution of the mmf of each phase and that of the resultant mmf (given by the
algebraic sum of the three components at any given instant of time). Figure 12.3.2(a) applies
Axis of phase b Figure 12.3.1 Simple two-pole, three-phase wind-

ing arrangement on a stator.
θ
a
−c −b
+ +
Axis of phase a
c
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
b
+
−a
Axis of phase c
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for that instant when the a-phase current is a positive maximum; Figure 12.3.2(b) refers to that
instant when the b-phase current is a positive maximum; the intervening time corresponds to
120 electrical degrees. It can be seen from Figure 12.3.2 that during this time interval, the
resultant sinusoidal mmf waveform has traveled (or rotated through) 120 electrical degrees
of the periphery of the stator structure carrying the three-phase winding. That is to say, the
resultant mmf is rotating in synchronism with time variations in current, with its peak amplitude
remaining constant at 3/2 times that of the maximum phase value. Note that the peak value of
the resultant stator mmf wave coincides with the axis of a particular phase winding when that
phase winding carries its peak current. The graphical process can be continued for different
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
instants of time to show that the resultant mmf is in fact rotating in synchronism with the supply
frequency.
Although the analysis here is carried out only for a three-phase case, it holds good for any q-
phase (q > 1; i.e., polyphase) winding excited by balanced q-phase currents when the respective
phases are wound 2π/q electrical radians apart in space. However, in a balanced two-phase case,
note that the two phase windings are displaced 90 electrical degrees in space, and the phase
currents in the two windings are phase-displaced by 90 electrical degrees in time. The constant
amplitude of the resultant rotating mmf can be shown to be q/2 times the maximum contribution
of any one phase. Neglecting the reluctance of the magnetic circuit, the corresponding flux density
in the air gap of the machine is then given by
µ0 F
Bg = (12.3.8)
g
where g is the length of the air gap.
Production of Rotating Fields from Single-Phase Windings

In this subsection we show that a single-phase winding carrying alternating current produces a
stationary pulsating flux that can be represented by two counterrotating fluxes of constant and
equal magnitude.
Let us consider a single-phase winding, as shown in Figure 12.3.3(a), carrying alternating
current i = I cos ωt. This winding will produce a flux-density distribution whose axis is fixed
along the axis of the winding and that pulsates sinusoidally in magnitude. The flux density along
the coil axis is proportional to the current and is given by Bm cos ωt, where Bm is the peak flux
density along the coil axis.
Let the winding be on the stator of a rotating machine with uniform air gap, and let the flux
density be distributed sinusoidally around the air gap. Then the instantaneous flux density at any
position θ from the coil axis can be expressed as
B(θ ) = (Bm cos ωt) cos θ (12.3.9)
which may be rewritten by the use of the trigonometric identity following Equation (12.3.5) as
Bm Bm
B(θ ) = cos(θ − ωt) + cos(θ + ωt) (12.3.10)
2 2
The sinusoidal flux-density distribution given by Equation (12.3.9) can be represented by a
vector Bm cos ωt of pulsating magnitude on the axis of the coil, as shown in Figure 12.3.3(a).
Alternatively, as suggested by Equation (12.3.10), this stationary pulsating flux-density vector can
be represented by two counterrotating vectors of constant magnitude Bm /2, as shown in Figure
12.3.3(b). While Equation (12.3.9) represents a standing space wave varying sinusoidally with
time, Equation (12.3.10) represents the two rotating components of constant and equal magnitude,
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12.3 ROTATING MAGNETIC FIELDS 525
F
Total
ia
Phase a
ic ib
Phase b Phase c Instant in time
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
θ
−90° −30° 0° 30° 90° 150° 210° 270°
(a)
120°
ib
Total
ia ic
Phase b
Instant in time
Phase c
−90° −30°
θ
0° 30° 90° 150° 210° 270°
(b)
Phase a
Figure 12.3.2 Generation of a rotating mmf. (a) Spatial mmf distribution at the instant in time when the
a-phase current is a maximum. (b) Spatial mmf distribution at the instant in time when the b-phase current
is a maximum.
rotating in opposite directions at the same angular velocity given by dθ/dt = ω. The vertical
components of the two rotating vectors in Figure 12.3.3(b) always cancel, and the horizontal
components always yield a sum equal to Bm cos ωt, the instantaneous value of the pulsating
vector.
This principle is often used in the analysis of single-phase machines. The two rotating fluxes
are considered separately, as if each represented the rotating flux of a polyphase machine, and
the effects are then superimposed. If the system is linear, the principle of superposition holds
and yields correct results. In a nonlinear system with saturation, however, one must be careful in
reaching conclusions since the results are not as obvious as in a linear system.
Copyright OUP
Bm /2
ω
ωt
B = Bm cos ωt Bm cos ωt
i = I cos ωt ωt
ω Bm /2
(a) (b)
Figure 12.3.3 Single-phase winding carrying alternating current, producing a stationary pulsating flux or
equivalent rotating flux components.
12.4 FORCES AND TORQUES IN MAGNETIC-FIELD SYSTEMS

We mentioned earlier that the greater ease of storing energy in magnetic fields largely accounts
for the common use of electromagnetic devices for electromechanical energy conversion. In a
magnetic circuit containing an air-gap region, the energy stored in the air-gap space is several
times greater than that stored in the iron portion, even though the volume of the air gap is only a
small fraction of that of the iron.
The energy-conversion process involves an interchange between electric and mechanical
energy via the stored energy in the magnetic field. This stored energy, which can be determined
for any configuration of the system, is a state function defined solely by functional relationships
between variables and the final values of these variables. Thus, the energy method is a powerful
tool for determining the coupling forces of electromechanics.
In a singly excited system, a change in flux density from a value of zero initial flux density to
B requires an energy input to the field occupying a given volume,
B1
Wm = vol H dB (12.4.1)
0
which can also be expressed by
λ1 φ1
Wm = i(λ) dλ = F(φ) dφ (12.4.2)
0 0
Note that the current i is a function of the flux linkages λ and that the mmf F is a function of the
flux φ; their relations depend on the geometry of the coil, the magnetic circuit, and the magnetic
l Figure 12.4.1 Graphical interpretation of energy

and coenergy in a singly excited nonlinear system.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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12.4 FORCES AND TORQUES IN MAGNETIC-FIELD SYSTEMS 527
properties of the core material. Equations (12.4.1) and (12.4.2) may be interpreted graphically as
the area labeled energy in Figure 12.4.1. The other area, labeled coenergy in the figure, can be
expressed as
H1 i1 F1

Wm = vol B dH = λ(i) di = φ(F) dF (12.4.3)
0 0 0
For a linear system in which B and H, λ and i, or φ and F are proportional, it is easy to see that
the energy and the coenergy are numerically equal. For a nonlinear system, on the other hand,
the energy and the coenergy differ, as shown in Figure 12.4.1, but the sum of the energy and the
coenergy for a singly excited system is given by
Wm + Wm = vol · B1 H1 = λ1 i1 = φ1 F1 (12.4.4)
The energy stored in a singly excited system can be expressed in terms of self-inductance,
and that stored in a doubly excited system in terms of self and mutual inductances, for the circuit-
analysis approach, as we pointed out earlier.
Let us now consider a model of an ideal (lossless) electromechanical energy converter that
is doubly excited, as shown in Figure 12.4.2, with two sets of electrical terminal pairs and one
mechanical terminal, schematically representing a motor. Note that all types of losses have been
excluded to form a conservative energy-conversion device that can be described by state functions
to yield the electromechanical coupling terms in electromechanics. A property of a conservative
system is that its energy is a function of its state only, and is described by the same independent
variables that describe the state. State functions at a given instant of time depend solely on the
state of the system at that instant and not on past history; they are independent of how the system
is brought to that particular state.
We shall now obtain an expression for the electromagnetic torque Te from the principle of
conservation of energy, which, for the case of a sink of electric energy (such as an electric motor),
may be expressed as
We = W + Wm
or in differential form as
dWe = dW + dWm (12.4.5)
where We stands for electric energy input from electrical sources, Wm represents the energy stored
in the magnetic field of the two coils associated with the two electrical inputs, and W denotes the
mechanical energy output. We and W may further be written in their differential forms,
dWe = v1 i1 dt + v2 i2 dt (12.4.6)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
i1 Doubly excited
+
v1 lossless electromechanical
energy-conversion device
− with conservative coupling fields
i2 Te, θm = ωmt + θm(0)
v2
+ −
Figure 12.4.2 Model of an ideal, doubly excited electromechanical energy converter.
Copyright OUP
dW = Te dθm (12.4.7)
where θm is expressed in electrical radians. Neglecting the winding resistances, the terminal
voltages are equal to the induced voltages given by
dλ1
v1 = e1 = (12.4.8)
dt
dλ2
v2 = e2 = (12.4.9)
dt
These are the volt-ampere equations, or the equations of motion, for the electrical side. Two
volt-ampere equations result because of the two sets of electrical terminals. Substituting these
into Equation (12.4.6), one gets
dWe = i1 dλ1 + i2 dλ2 (12.4.10)
Substituting Equations (12.4.7) and (12.4.10) into the differential form of Equation (12.4.5), we
have
dWm = dWe − dW = i1 dλ1 + i2 dλ2 − Te dθm (12.4.11)
By specifying one independent variable for each of the terminal pairs, i.e., two electrical variables
(flux linkages or currents) and one mechanical variable θm for rotary motion, we shall attempt to
express Te in terms of the energy or the coenergy of the system.
Based on Equation (12.4.4) and the concepts of energy and coenergy, one has
Wm + Wm = λ1 i1 + λ 2 i2 (12.4.12)
Expressing Equation (12.4.12) in differential form, the expression for the differential coenergy
function dWm is obtained as
dWm = d(λ1 i1 ) + d(λ2 i2 ) − dWm

= λ1 di1 + i1 dλ1 + λ2 di2 + i2 dλ2 − dWm (12.4.13)
Substituting Equation (12.4.11) into Equation (12.4.13) and simplifying, one gets
dWm = λ1 di1 + λ2 di2 + Te dθm (12.4.14)

Expressing the coenergy as a function of the independent variables i1, i2, and θm ,
Wm = Wm (i1 , i2 , θm ) (12.4.15)

the total differential of the coenergy function can be written as
∂Wm ∂Wm ∂Wm
dWm = di1 + di2 + dθm (12.4.16)
∂i1 ∂i2 ∂θm
On comparing Equations (12.4.14) and (12.4.16) term by term, the expression for the electromag-
netic torque Te is obtained as
∂Wm (i1 , i2 , θm )
Te = (12.4.17)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
∂θm
On the other hand, choosing the independent variables λ1 , λ2 , and θm , it can be shown that
∂Wm (λ1 , λ2 , θm )
Te = − (12.4.18)
∂θm
Copyright OUP
Depending on the convenience in a given situation, either Equation (12.4.17) or (12.4.18) can be
used. For the case of a translational electromechanical system consisting of only one-dimensional
motion, say, in the direction of the coordinate x, the torque Te and the angular displacement dθm
are to be replaced by the force Fe and the linear displacement dx, respectively. Thus,
∂Wm (i1 , i2 , x)
Fe = (12.4.19)
∂x
and
∂Wm (λ1 , λ2 , x)
Fe = − (12.4.20)
∂x
For a linear magnetic system, however, the magnetic energy and the coenergy are always
equal in magnitude. Thus,
1 1
Wm = Wm = λ1 i1 + λ2 i2 (12.4.21)
2 2
In linear electromagnetic systems, the relationships between flux linkage and currents (in a doubly
excited system) are given by
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
λ1 = L11 i1 + L12 i2 (12.4.22)

λ2 = L21 i1 + L22 i2 (12.4.23)
where L11 is the self-inductance of winding 1, L22 is the self-inductance of winding 2, and
L12 = L21 = M is the mutual inductance between windings 1 and 2. All of these in-
ductances are generally functions of the angle θm (mechanical or spatial variable) between
the magnetic axes of windings 1 and 2. Neglecting the iron-circuit reluctances, the electro-
magnetic torque can be found from either the energy or the coenergy stored in the mag-
netic field of the air-gap region by applying either Equation (12.4.17) or (12.4.18). For a
linear system, the energy or the coenergy stored in a pair of mutually coupled inductors is
given by
1 1
Wm (i1 , i2 , θm ) = L11 i12 + L12 i1 i2 + L22 i22 (12.4.24)
2 2
The instantaneous electromagnetic torque is then given by
i12 dL11 dL12 i 2 dL22
Te = + i 1 i2 + 2 (12.4.25)
2 dθm dθm 2 dθm
The first and third terms on the right-hand side of Equation (12.4.25), involving the angular
rate of change of self-inductance, are the reluctance-torque terms; the middle term, involving the
angular rate of change of mutual inductance, is the excitation torque caused by the interaction of
fields produced by the stator and rotor currents in an electric machine. It is this mutual inductance
torque (or excitation torque) that is most commonly exploited in practical rotating machines.
Multiply excited systems with more than two sets of electrical terminals can be handled in
a manner similar to that for two pairs by assigning additional independent variables to the
terminals.
If none of the inductances is a function of the mechanical variable θm , no electromagnetic
torque is developed. If, on the other hand, the self-inductances L11 and L22 are independent of
the angle θm , the reluctance torque is zero and the torque is produced only by the mutual term
L12 (θm ), as seen from Equation (12.4.25). Let us consider such a case in the following example
on the basis of the coupled-circuit viewpoint (or coupled-coils approach).
Copyright OUP
EXAMPLE 12.4.1
Consider an elementary two-pole rotating machine with a uniform (or smooth) air gap, as shown
in Figure E12.4.1, in which the cylindrical rotor is mounted within the stator consisting of a hollow
cylinder coaxial with the rotor. The stator and rotor windings are distributed over a number of slots
so that their mmf can be approximated by space sinusoids. As a consequence of a construction of
this type, we can fairly assume that the self-inductances Lss and Lrr are constant, but the mutual
inductance Lsr is given by
Lsr = L cos θ
where θ is the angle between the magnetic axes of the stator and rotor windings. Let the currents
in the two windings be given by
is = Is cos ωs t and ir = Ir cos(ωr t + α)
and let the rotor rotate at an angular velocity
ωm = θ̇ rad/s
such that the position of the rotor at any instant is given by
θ = ωm t + θ0
Assume that the reluctances of the stator and rotor-iron circuits are negligible, and that the stator
and rotor are concentric cylinders neglecting the effect of slot openings.
(a) Derive an expression for the instantaneous electromagnetic torque developed by the
machine.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(b) Find the condition necessary for the development of an average torque in the machine.
(c) Obtain the expression for the average torque corresponding to the following cases, where
ωs and ωr are different angular frequencies:
(1) ωs = ωr = ωm = 0; α = 0
(2) ωs = ωr ; ωm = 0
(3) ωr = 0; ωs = ωm ; α = 0
(4) ωm = ωs − ωr
Solution
(a) Equations (12.4.22) through (12.4.25) apply. With constant Lss and Lrr, and the variation
of Lsr as a function of θ substituted, Equation (12.4.25) simplifies to
dLsr
Te = is ir = −is ir L sin θ
dθ
Note: For a P-pole machine this expression would be modified as −(P /2)is ir L sin
[(P /2)θm ].
For the given current variations, the instantaneous electromagnetic torque developed
by the machine is given by
Te = −LIs Ir cos ωs t cos(ωr t + α) sin(ωm t + θ0 )
Copyright OUP
Stator winding
Rotor coil
Stator coil
Rotor Magnetic axis +
+ winding of stator + −
θ −
+
+
+ +
θ
+ +
+ + + + +
Magnetic axis of rotor
(a) (b)
Fs sin δ = F sin δr
Fs
δs
F r sin δ = F sin δs δr δ
F
Fr
(c)
Figure E12.4.1 Elementary two-pole rotating machine with uniform air gap. (a) Winding distribution.
(b) Schematic representation. (c) Vector diagram of mmf waves.
Using trigonometric identities, the product of the three trigonometric terms in this
equation may be expressed to yield
−LIs Ir
Te = [sin {[ωm + (ωs + ωr )] t + α + θ0 }
4
+ sin {[ωm − (ωs + ωr )] t − α + θ0 }
+ sin {[ωm + (ωs − ωr )] t − α + θ0 }
+ sin {[ωm − (ωs − ωr )] t + α + θ0 }]
(b) The average value of each of the sinusoidal terms in the previous equation is zero, unless
the coefficient of t is zero in that term. That is, the average torque (Te)av developed by
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
the machine is zero unless

ωm = ±(ωs ± ωr )
which may also be expressed as

|ωm | = |ωs ± ωr |
Copyright OUP
(c) (1) The excitations are direct currents Is and Ir. For the given conditions of ωs = ωr =
ωm = 0 and α = 0,
Te = −LIs Ir sin θ0
which is a constant. Hence,

(Te )av = −LIs Ir sin θ0
The machine operates as a dc rotary actuator, developing a constant torque against

any displacement θ0 produced by an external torque applied to the rotor shaft.
(2) With ωs = ωr , both excitations are alternating currents of the same frequency. For
the conditions ωs = ωr and ωm = 0,
LIs Ir
Te = − [sin(2ωs t + α + θ0 ) + sin(−2ωs t − α + θ0 ) + sin(−α + θ0 )
4
+ sin(α + θ0 )]
The machine operates as an ac rotary actuator, and the developed torque is fluctu-
ating. The average value of the torque is
LIs Ir
(Te )av = − sin θ0 cos α
2
Note that α becomes zero if the two windings are connected in series, in which case
cos α becomes unity.
(3) With ωr = 0, the rotor excitation is a direct current Ir. For the conditions ωr =
0, ωs = ωm , and α = 0,
LIs Ir
Te = − [sin(2ωs t + θ0 ) + sin θ0 + sin(2ωs t + θ0 ) + sin θ0 ]
4
or
LIs Ir
Te = − [sin(2ωs t + θ0 ) + sin θ0 )]
2
The device operates as an idealized single-phase synchronous machine, and the
instantaneous torque is pulsating. The average value of the torque is
LIs Ir
(Te )av = − sin θ0
2
since the average value of the double-frequency sine term is zero. If the machine
is brought up to synchronous speed (ωm = ωs ), an average unidirectional torque is
established. Continuous energy conversion takes place at synchronous speed. Note
that the machine is not self-starting, since an average unidirectional torque is not
developed at ωm = 0 with the specified electrical excitations.
(4) With ωm = ωs − ωr , the instantaneous torque is given by
LIs Ir
Te = − [sin(2ωs t + α + θ0 ) + sin(−2ωr t − α + θ0 )
4
+ sin(2ωs t − 2ωr t − α + θ0 ) + sin(α + θ0 )]
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
The machine operates as a single-phase induction machine, and the instantaneous

torque is pulsating. The average value of the torque is
LIs Ir
(Te )av = − sin(α + θ0 )
4
If the machine is brought up to a speed of ωm = ωs − ωr , an average unidirec-
tional torque is established, and continuous energy conversion takes place at the
asynchronous speed of ωm . Again, note that the machine is not self-starting, since
an average unidirectional torque is not developed at ωm = 0 with the specified
electrical excitations.
The pulsating torque, which may be acceptable in small machines, is, in general,
an undesirable feature in a rotating machine working as either a generator or a
motor, since it may result in speed fluctuation, vibration, noise, and a waste of
energy. In magnetic-field systems excited by single-phase alternating sources, the
torque pulsates while the speed is relatively constant. Consequently, pulsating power
becomes a feature. This calls for improvement; in fact, by employing polyphase
windings and polyphase sources, constant power is developed in a balanced system.
EXAMPLE 12.4.2
Consider an electromagnet, as shown in Figure E12.4.2, which is used to support a solid piece of
steel and is excited by a coil of N = 1000 turns carrying a current i = 1.5 A. The cross-sectional
area of the fixed magnetic core is A = 0.01 m2. Assume magnetic linearity, infinite permeability
of the magnetic structure, and negligible fringing in the air gap.
(a) Develop a general expression for the force f acting to pull the bar toward the fixed
magnetic core, in terms of the stored energy, from the basic principle of conservation of
energy.
(b) Determine the force that is required to support the weight from falling for x = 1.5 mm.
+ − Figure E12.4.2 Electromagnet.

i v
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Fixed core
N turns
fe
x
Movable steel
Copyright OUP
Solution
(a) A change in the energy stored in the electromagnetic field dWm is equal to the sum of
the incremental work done by the electric circuit and the incremental work done by the
mechanical system. Thus,
dλ
dWm = ei dt − fe dx = i dt − fe dx = i dλ − fe dx
dt
or
fe dx = i dλ − dWm
where e is the electromotive force across the coil and the negative sign is due to the
sign convention shown in Figure E.12.4.2. Noting that the flux in the magnetic structure
depends on two independent variables, namely, the current i through the coil and the
displacement x of the bar, one can rewrite the equation,

∂λ ∂λ ∂Wm ∂Wm
fe dx = i di + dx − di + dx
∂i ∂x ∂i ∂x
where Wm is a function of i and x. Since i and x are independent variables, one gets
∂λ ∂Wm ∂λ ∂Wm
fe = i − and 0=i −
∂x ∂x ∂i ∂i
We can then see that
∂ ∂
fe = (iλ − Wm ) = W
∂x ∂x m
where Wm is the coenergy, which is equal to the energy Wm in structures that are
magnetically linear.
The force f acting to pull the bar toward the fixed magnet core is given by
∂Wm
f = −fe = −
∂x
The stored energy in a linear magnetic structure is given by
φF φ 2 R (x)
Wm = =
2 2
where φ is the flux, F is the mmf, and R (x) is the reluctance, which is a function of
displacement. Finally, we get
∂Wm φ 2 d R (x)
f =− =−
∂x 2 dx
(b) The reluctance of the air gaps in the magnetic structure is given by
2x 2x x
R (x) = = −7
=
µ0 A 4π × 10 × 0.01 0.6285 × 10−8
The magnitude of the force in the air gap is then given by
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
2
φ 2 d R (x) 1 Ni dR
|f | = =
2 dx 2 R dx
i2 N 2 dR 1.52 0.6285 × 10−8
= 2
= 10002
2 R dx 2 x2
For x = 1.5 mm = 1.5 × 10−3 m,
1.52 0.6285 × 10−8
|f | = 10002 = 3142.5 N
2 (1.5 × 10−3 )2
The student should recognize the practical importance of force-generating capabilities

of electromechanical transducers.
EXAMPLE 12.4.3
Solenoids find application in a variety of electrically controlled valves. The magnetic structure
shown in Figure E12.4.3 is a simplified representation of a solenoid in which the flux in the air
gap activates the motion of the iron plunger.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(a) Develop a general expression for the force exerted on the iron plunger and comment on
its dependence on position x.
(b) Determine the current through the coil of N = 100 turns to pull the plunger to x = a,
given that a = 1 cm, lg = 1 mm, and the spring constant is k = 1 N/m. Assume the
permeability of the magnetic structure to be infinite and neglect fringing.
Fixed magnetic Figure E12.4.3 Simplified representation of a

core structure solenoid.
(µ ∞)
i
N turns a
lg 2a
a
x x=0
a a
Nonmagnetic
bushing material
Movable iron Spring (µr 1)
plunger
Copyright OUP
Solution
(a) The force in the air gap can be expressed by

1 dR
f = − φ2
2 dx
(See Example 12.4.2.) The gap reluctance, which in this case is due to the nonmagnetic
bushing, is given by
2lg
R = 2 Rg =
µ0 ax
where the area ax is variable, depending on the position of the plunger, and lg is the
thickness of the bushing on either side of the plunger. The air-gap magnetic flux is given
by
F Ni µ0 N iax
φ= = =
R R 2lg
Now,

--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
dR d 2lg −2lg
= =
dx dx µ0 ax µ0 ax 2
The force is then given by

2
1 dR 1 µ0 N iax −2lg
f = − φ2 =−
2 dx 2 2lg µ0 ax 2
or
1 µ0 a
f = (N i)2
4 lg
which is independent of the position x, and is a constant for a given exciting mmf and
geometry.
(b) For x = a = 1 cm = 0.01 m,
1 4π × 10−7 × 0.01
f = kx = 1 × 0.01 = (100 i)2
4 0.001
or
4 × 0.001 × 0.01 1
i2 = = 0.3182
4π × 10−7 × 0.01 (100)2
or
i = 0.564 A
The student should recognize the practical importance of determining the approximate
mmf or current requirements for electromechanical transducers.
Copyright OUP
EXAMPLE 12.4.4
A relay is essentially an electromechanical switch that opens and closes electrical contacts. A
simplified relay is represented in Figure E12.4.4. It is required to keep the fenomagnetic plate at a
distance of 0.25 cm from the electromagnet excited by a coil of N = 5000 turns, when the torque
is 10 N · m at a radius r = 10 cm. Estimate the current required, assuming infinitely permeable
magnetic material and negligible fringing as well as leakage.
(a) Express the stored magnetic energy Wm as a function of the flux linkage λ and the position
x.
(b) Express the coenergy Wm as a function of the current i and the position x.
x = lg Figure E12.4.4 Simplified representation of a relay.

Electromagnet
Cross–sectional area
i Ag = 1 cm2
N turns
Radius r
Ferromagnetic plate
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Solution
For the stated torque at a radius of 10 cm, the force on the plate is
10
f = = 100 N
0.1
The magnitude of the force developed by the electromagnet must balance this force. The reluctance
due to the two air gaps is given by
2x 2x x
Q= = −7 −4
=
µ0 A g 4π × 10 × 1 × 10 2π × 10−11
The inductance is then given by

N2 50002 × 2π × 10−11 5π × 10−4 1.57 × 10−3
L= = = =
R x x x
In a magnetically linear circuit, the stored magnetic energy Wm is equal to the coenergy Wm ,
1 2 1 λ2
Wm = Wm = Li =
2 2L
1 2 x λ2 x
(a) Wm (λ, x) = λ =
2 5π × 10−4 π × 10−3
Since f = −∂Wm (λ, x)/∂x, the magnitude of the developed force is given by
λ2 (Li)2 (5π × 10−4 )2 i 2 i2
|f | = −3
= −3
= −3
= 2.5 π × 10−4 2
π × 10 π × 10 π × 10 × x 2 x
Copyright OUP
For x = 0.25 cm and |f | = 100 N,

100(0.25 × 10− 2)2 2.5
i2 = −4
= = 0.795
2.5π × 10 π
or
i = 0.89 A
1 2 1 5π × 10−4 2
(b) Wm (i, x) =Li = i
2 2 x
Since f = ∂Wm (i, x)/∂x, the magnitude of the developed force is given by
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
1 5π × 10−4 2
|f | = i
2 x2
For x = 0.25 cm and |f | = 100 N,
100 × 2 × (0.25 × 10−2 )2 2.5
i2 = −4
= = 0.795
5π × 10 π
or
i = 0.89 A
Such relays find common application in industrial practice to remotely switch large
industrial loads. The student should recognize that a relatively low-level current can be
used to operate the relay, which in turn controls the opening and closing of a circuit that
carries large currents.
Starting with the flux linkages given by Equations (12.4.22) and (12.4.23), one can develop
the volt–ampere equations for the stator and rotor circuits. While the voltage and torque equations
for the idealized elementary machine of Example 12.4.1 with a uniform air gap are now obtained
from the coupled-circuit viewpoint, these can also be formulated from the magnetic-field viewpoint
based on the interaction of the magnetic fields of the stator and rotor windings in the air gap.
Since the mmf waves of the stator and rotor are considered spatial sine waves, they can be
represented by the space vectors F̄s and F̄r , drawn along the magnetic axes of the stator and
rotor mmf waves, as in Figure E12.4.1, with the phase angle δ (in electrical units) between their
magnetic axes. The resultant mmf F̄ acting across the air gap is also a sine wave, given by the
vector sum of F̄s and F̄r , so that
F 2 = Fs2 + Fr2 + 2Fs Fr cos δ (12.4.26)
where F’s are the peak values of the mmf waves. Assuming the air-gap field to be entirely radial,
the resultant H̄ -field is a sinusoidal space wave whose peak is given by
F
Hpeak = (12.4.27)
g
where g is the radial length of the air gap. Because of linearity, the coenergy is equal to the energy.
The average coenergy density obtained by averaging over the volume of the air-gap region is
2
µ0 µ0 Hpeak µ0 F 2
(w )av = (average value of H 2 ) = = (12.4.28)
2 2 2 4 g2
Copyright OUP
12.5 BASIC ASPECTS OF ELECTROMECHANICAL ENERGY CONVERTERS 539
since the average value of the square of a sine wave is one-half of the square of its peak value.
The total coenergy for the air-gap region is then given by
µ0 F 2
W = (w )av (volume of air-gap region) = π Dlg (12.4.29)
4 g2
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
where D is the average diameter at the air gap and l is the axial length of the machine. Equation
(12.4.29) may be rewritten as follows by using Equation (12.4.26):
π Dlµ0 2
W = (Fs + Fr2 + 2Fs Fr cos δ) (12.4.30)
4g
The torque in terms of the interacting magnetic fields is obtained by taking the partial derivative
of the field coenergy with respect to the angle δ. For a two-pole machine, such a torque is given by
∂W π Dlµ0
Te = =− Fs Fr sin δ = −KFs Fr sin δ (12.4.31)
∂δ 2g
in which K is a constant determined by the dimensions of the machine. The torque for a P-pole
cylindrical machine with a uniform air gap is then
P
Te = − KFs Fr sin δ (12.4.32)
2
Equations (12.4.31) and (12.4.32) have shown that the torque is proportional to the peak values
of the interacting stator and rotor mmfs and also to the sine of the space-phase angle δ between
them (expressed in electrical units). The interpretation of the negative sign is the same as before, in
that the fields tend to align themselves by decreasing the displacement angle δ between the fields.
Equation (12.4.32) shows that it is possible to obtain a constant torque, varying neither with
time nor with rotor position, provided that the two mmf waves are of constant amplitude and
have constant angular displacement from each other. While it is easy to conceive of the two mmf
waves having constant amplitudes, the question would then be how to maintain a constant angle
between the stator and rotor mmf axes if one winding is stationary and the other is rotating. Three
possible answers arise:
1. If the stator mmf axis is fixed in space, the rotor mmf must also be fixed in space, even
when the rotor winding is physically rotating, as is the case with a dc machine.
2. If the rotor mmf axis is fixed relative to the rotor, the stator mmf axis must rotate at
the rotor speed relative to the stationary stator windings, as is the case with a polyphase
synchronous machine.
3. The two mmf axes must rotate at such speeds relative to their windings that they remain
stationary with respect to each other, as is the case with a polyphase induction machine
(which we will explain later).
12.5 BASIC ASPECTS OF ELECTROMECHANICAL ENERGY CONVERTERS

Whereas detailed differences and particularly challenging problems emerge among various ma-
chine types, this section briefly touches on the interrelated problems that are common to all
machine types, such as losses and efficiency, ventilation and cooling, machine ratings, magnetic
saturation, leakage and harmonic fluxes, and machine applications. Various standards, developed
by IEEE (Institute of Electrical and Electronics Engineers), NEMA (National Electrical Man-
ufacturers Association), ANSI (American National Standards Institute), and IEC (International
Electrotechnical Commission), deal with machine ratings, insulation and allowable temperature
rise, testing methods, losses, and efficiency determination.
Copyright OUP
Besides the stator and rotor iron-core losses, friction and windage losses (which are generally
functions of machine speed, and are usually assumed to be practically constant for small speed
variations) are included in no-load rotational losses, which are effectively constant. Besides
copper losses (stator and rotor winding I 2R losses), stray-load losses (which arise from various
causes that are not usually accounted for, and are usually taken to be about 0.5 to 5% of the
machine output) are included for the determination of efficiency (= output/input).
Much of the considerable progress made over the years in electric machinery is due to the
improvements in the quality and characteristics of steel and insulating materials, as well as to
innovative cooling methods. Modern large turbo alternators have direct water cooling (cooling
water circulated through hollow passages in their conductors, being in direct contact with the
copper conductors) in the stator (and the rotor in a few cases) and hydrogen cooling (with
hydrogen under 1 to 5 atmospheres of pressure) in the rotor. With hydrogen under pressure,
sealing the bearings appropriately needs particular attention for turbogenerators. For hydroelectric
generators, on the other hand, designing the thrust bearings for vertical mounting becomes a
prominent issue.
In general, every machine has a nameplate attached to the frame inscribed with relevant
information regarding voltage, current, power, power factor, speed, frequency, phases, and
allowable temperature rise. The nameplate rating is the continuous rating, unless otherwise
specified, such as short-time rating. Motors are rated in hp (horsepower); dc generators in kW;
and alternators and transformers in terms of kVA rather than kW (because their losses and heating
are approximately determined by the voltage and current, regardless of the power factor). The
physical size and cost of ac power-system apparatus are roughly proportional to the kVA rating.
In order to fully utilize the magnetic properties of the iron and optimize the machine design,
the machine iron is worked at fairly saturated levels of flux density, such that the normal operating
point on the open circuit is near the knee of the open-circuit characteristic (or the no-load
saturation curve, which is similar to the magnetization B–H characteristic). Magnetic saturation
does influence the machine performance to a considerable degree. Leakage and harmonic fluxes,
which exist in addition to the mutual flux (generally assumed to be sinusoidally distributed) and
which may develop parasitic torques causing vibration and noise, also have to be considered.
Accounting for, and including, these effects becomes too involved to be discussed here.
For motors the major consideration is the torque–speed characteristics. The requirements
of motor loads generally vary from one application to another. Some may need constant speed
or horsepower, while some others may require adjustable varying speeds with different torque
capabilities. For any motor application, the starting torque, maximum torque, and running
characteristics (along with current requirements) should be looked into.
For generators it is the volt–ampere, or voltage–load, characteristics. For machines in general,
it is also vital to know the limits between which characteristics can be varied and how to obtain
such variations. Relevant economic features, such as efficiency, power factor, relative costs, and
the effect of losses on heating and machine rating, need to be investigated.
Finally, since a generator or a motor may only be one component of a complicated modern
power system, system-related dynamic applications and behavior (both steady-state and transient-
state) and proper models to study such behavior become very important when designing electric
machines.

--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
• Basic principles of electromechanical energy conversion, including induction, interaction,

alignment, and torque production.
• Simplified analysis of electromechanical transducers, such as electromagnets, position and
velocity sensors, relays, solenoids, and loudspeakers, which convert electric signals to
mechanical forces, or mechanical motion to electric signals.
• Calculating the emf produced in ac and dc machines.
• Generation of rotating magnetic fields.
• Evaluating forces and torques in magnetic-field systems, from the coupled-circuit viewpoint
and the magnetic-field viewpoint.
• Basic aspects of motors and generators.
Sensors or Transducers
In almost all engineering applications there arises a need to measure some physical quantities, such
as positions, displacements, speeds, forces, torques, temperatures, pressures, or flows. Devices
known as sensors or transducers convert a physical quantity to a more readily manipulated
electrical quantity (such as voltage or current), such that changes in physical quantity usually
produce proportional changes in electrical quantity. The direct output of the sensor may often
need additional manipulation, known as signal conditioning, for the output to be in a useful
form free from noise and intereference. The conditioned sensor signal may then be sampled and
converted to digital form and stored in a computer for additional manipulation or display. A
typical computer-based measurement system using a sensor is represented in block diagram form
in Figure 12.7.1. Table 12.7.1 lists various sensors and their uses.
TABLE 12.7.1 Sensors classified according to variable sensed
Variable Sensed Sensor or Transducer
Variations in dimensions due to motion Strain gauge

Resistive potentiometer
Variable reluctance sensor
Moving-coil transducer
Seismic sensor
Temperature Thermocouple
Resistance temperature detector
Radiation detector
Force, torque, and pressure Capacitive sensor
Piezoelectric transducer
Flow Magnetic flow meter
Turbine flow meter
Hot-wire anemometer
Ultrasonic sensor
Light intensity Photoelectric sensor
Humidity Semiconductor transducer
Chemical composition Solid-state gas sensor
Liquid level Differential-pressure transducer
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Copyright OUP
Data gathering with various sensors and data reduction have become much easier, automatic,
and quite sophisticated due to the advent of the computer, since the computer can monitor many
inputs, process and record data, furnish displays, and produce control outputs.
Physical Analog-to- Digital

Sensor or Signal Output
phenomenon Sampling digital computer
transducer conditioning display
or stimulus conversion with interface
Figure 12.7.1 Block diagram of measurement system using a sensor.
PROBLEMS
12.1.1 (a) Show by applying Ampere’s circuital law an expression for the total flux linking the loop,
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
that the magnetic field associated with a long assuming a medium of permeability µ.
straight, current-carrying wire is given by 12.1.3 Consider a conducting loop of length l and width
Bφ = µ0 I /(2πr), where the subscript φ de- w, as shown in Figure P12.1.3, rotated about its
notes the φ-component in the circular cylin- axis (shown by the broken line) at a speed of ωm
drical coordinate system, µ0 is the free-space rad/s under the influence of a magnetic field B.
permeability, I is the current carried by the
(a) Obtain an expression for the induced emf,
wire, and r is the radius from the current-
assuming the angle θm is zero at t = 0 and
carrying wire. What is the net force on the
θm = ωm t.
wire due to the interaction of the B-field
(produced by the current I) and the current I? (b) If a resistor R is connected across terminals
a–a , explain what happens and how the prin-
(b) A magnetic force exists between two adja- ciple of energy conservation is satisfied.
cent, parallel, current-carrying wires. Let I 1 12.1.4 A coil is formed by connecting 15 conducting
and I 2 be the currents carried by the wires loops, or turns, in series. Each loop has length
and r the separation between them. Use the l = 2.5 m and width w = 10 cm. The 15-turn
result of part (a) to find the force between the coil is rotated at a constant speed of 30 r/s (or
wires. Discuss the nature of the force when 1800 r/min) in a magnetic field of density B = 2
the wires carry currents in the same direction, T. The configuration of Figure P12.1.3 applies.
and in opposite directions.
(a) Find the induced emf across the coil.
*12.1.2 A rectangular loop is placed in the field of an in- (b) Determine the average power delivered to
finitely long straight conductor carrying a current the resistor R = 500 -, which is connected
of I amperes, as shown in Figure P12.1.2. Find between the terminals of the coil.
Figure P12.1.2
I dr
r1 × × ×
× × ×
r2 × × × B
× × × l
r × × ×
× × ×
× × ×
Copyright OUP
PROBLEMS 543
ωm l
B ωm
y a B y
θm a
w
a'
a' Axis of
rotation
x z
Figure P12.1.3 Rotating conducting loop.
(c) Calculate the average mechanical torque turns and carries a direct current of 3 A. Compute
needed to turn the coil and generate power the pull on the plunger for g = 1.25 cm.
for the resistor. Identify the action of the 12.1.9 Figure E12.1.1 can also be considered as a simple
device as that of a motor or a generator. model of a magnetically operated relay that is
12.1.5 The machine of Problem 12.1.4 can be used as a commonly used for the automatic control and
motor. Let the terminals of the coil be connected protection of electric equipment. Consider the
to a voltage source of 1 kV rms. If the motor runs core and armature (shown as “Bar” in Figure
at 1800 r/min and draws a current of 2 A, find the E12.1.1) of the relay to be constructed out of
torque supplied to the mechanical load. infinitely permeable magnetic material. The core
has a circular cross section and is 1.25 cm in
12.1.6 The 50-turn coil in the configuration of Figure diameter, while the armature has a rectangular
P12.1.3 is rotated at a constant speed of 300 cross section. The armature is so supported that
r/min. The axis of rotation is perpendicular to the two air gaps are always equal and of uniform
a uniform magnetic flux density of 0.1 T. The length over their areas. A spring (not shown in
loop has width w = 10 cm and length l = 1 m. the figure), whose force opposes the magnetic
Compute: pull, restrains the motion of the armature. If the
(a) The maximum flux passing through the coil. operating coil has 1800 turns carrying a current
of 1 A, and the gaps are set at 0.125 cm each, find
(b) The flux linkage as a function of time. the pull that must be exerted by the spring. You
(c) The maximum instantaneous voltage in- may neglect leakage and fringing.
duced in the coil. 12.1.10 The coil is placed so that its axis of revolution
(d) The time-average value of the induced volt- is perpendicular to a uniform field, as shown in
age. Figure P12.1.10. If the flux per pole is 0.02 Wb,
and the coil, consisting of 2 turns, is revolving at
(e) The induced voltage when the plane of the 1800 r/min, compute the maximum value of the
coil is 30° from the vertical. voltage induced in the coil.
*12.1.7 A 100-turn coil in the configuration of Figure 12.2.1 An elementary two-pole, single-phase, synchro-
P12.1.3 is rotated at a constant speed of 1200 nous machine, as illustrated in Figure P12.2.1,
r/min in a magnetic field. The rms induced volt- has a field winding on its rotor and an armature
age across the coil is 1 kV, and each turn has a winding on its stator, with Nf = 400 turns and
length l = 112.5 cm and a width w = 10 cm. Na = 50 turns, respectively. The uniform air gap
Determine the required value of the flux density. is of length 1 mm, while the armature diameter is
0.5 m, and the axial length of the machine is 1.5
12.1.8 A sectional view of a cylindrical iron-clad
m. The field winding carries a current of 1 A (dc)
plunger magnet is shown in Figure P12.1.8. The
and the rotor is driven at 3600 r/min. Determine:
small air gap between the sides of the plunger
and the iron shell is uniform and 0.25 mm long. (a) The frequency of the stator-induced voltage.
Neglect leakage and fringing, and consider the (b) The rms-induced voltage in the stator wind-
iron to be infinitely permeable. The coil has 1000 ing.
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Copyright OUP
12.5 cm Figure P12.1.8 Plunger magnet.

10 cm
1.25 cm
1000-turn
coil
Cylindrical 10 cm
g
cast-steel
shell
5 cm
1.25 cm
Cylindrical
plunger
Uniform vertical field Figure P12.1.10
12.2.2 The flux-density distribution produced in a two- coil has three turns, and all the turns in any one
pole synchronous generator by an ac-excited field phase are connected in series. The flux per pole,
winding is distributed sinusoidally in space, is 0.1 Wb. The
rotor is driven at 1800 r/min.
B(θ, t) = Bm sin ω1 t cos θ
(a) Calculate the rms voltage generated in each
Find the nature of the armature voltage induced
phase.
in an N-turn coil if the rotor (or field) rotates
at ω2 rad/s. Comment on the special case when (b) If a voltmeter were connected across the two
ω1 = ω2 = ω. line terminals, what would it read?
12.2.3 The flux-density distribution in the air gap of a (c) For the a–b–c phase sequence, take t = 0 at
60-Hz, two-pole, salient-pole machine is sinu- the instant when the flux linkages with the
soidal, having an amplitude of 0.6 T. Calculate a-phase are maximum.
the instantaneous and rms values of the voltage (i) Express the three phase voltages as
induced in a 150-turn coil on the armature, if the functions of time.
axial length of the armature and its inner diameter
(ii) Draw a corresponding phasor diagram
are both 100 mm.
of these voltages with the a-phase volt-
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*12.2.4 Consider an elementary three-phase, four-pole age as reference.

alternator with a wye-connected armature wind- (iii) Represent the line-to-line voltages on
ing, consisting of full-pitch concentrated coils, as the phasor diagram in part (ii).
shown in Figures 12.2.3(b) and (c). Each phase
Copyright OUP
PROBLEMS 545
Stator Figure P12.2.1 Rotating machine with uniform air

magnetic axis gap.
θm Rotor
magnetic axis
ωm
(iv) Obtain the time functions of the line-to- 12.2.9 A 10-turn square coil of side 200 mm is mounted
line voltages. on a cylinder 200 mm in diameter. If the cylinder
12.2.5 A wye-connected, three-phase, 50-Hz, six-pole rotates at 1800 r/min in a uniform 1.2-T field,
synchronous alternator develops a voltage of determine the maximum value of the voltage
1000 V rms between the lines when the rotor dc induced in the coil.
field current is 3 A. If this alternator is to generate 12.3.10 A four-pole dc machine with 728 active conduc-
60-Hz voltages, find the new synchronous speed, tors and 30 mWb flux per pole runs at 1800 r/min.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
and calculate the new terminal voltage for the
(a) If the armature winding is lap wound, find
same field current.
the voltage induced in the armature, given
12.2.6 Determine the synchronous speed in revolutions that the number of parallel paths is equal to
per minute and the useful torque in newton- the number of poles for lap windings.
meters of a 200-hp, 60-Hz, six-pole synchronous
motor operating at its rated full load (1 hp ∼
= 746
(b) If the armature is wave wound, calculate the
W). voltage induced in the armature, given that
the number of parallel paths is equal to 2 for
12.2.7 From a three-phase, 60-Hz system, through a wave windings.
motor–generator set consisting of two directly
coupled synchronous machines, electric power (c) If the lap-wound armature is designed to
is supplied to a three-phase, 50-Hz system. carry a maximum line current of 100 A, com-
pute the maximum electromagnetic power
(a) Determine the minimum number of poles for and torque developed by the machine.
the motor.
(d) If the armature were to be reconnected as
(b) Determine the minimum number of poles for wave wound, while limiting per-path current
the generator. to the same maximum as in part (c), will
(c) With the number of poles decided, find the either the maximum developed power or the
speed in r/min at which the motor–generator torque be changed from that obtained in part
set will operate. (c)?
*12.2.8 Two coupled synchronous machines are used as 12.2.11 A four-pole, lap-wound armature has 144 slots
a motor–generator set to link a 25-Hz system to with two coil sides per slot, each coil having
a 60-Hz system. Find the three highest speeds at two turns. If the flux per pole is 20 mWb and
which this linkage would be possible. the armature rotates at 720 r/min, calculate the
Copyright OUP
induced voltage, given that the number of parallel (a) If the three-phase windings are connected in
paths is equal to the number of poles for lap series and supplied by a single-phase voltage
windings. source, find the resultant mmf due to all the
12.2.12 A four-pole dc generator is lap wound with 326
three windings as a function of θm .
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
armature conductors. It runs at 650 r/min on full (b) If the three-phase windings are connected to
load, with an induced voltage of 252 V. If the a balanced three-phase voltage supply of f
bore of the machine is 42 cm in diameter, its axial Hz (with positive sequence), determine the
length is 28 cm, and each pole subtends an angle resultant mmf.
of 60°, determine the air-gap flux density. (Note (c) Letting θm = ωm t + α, obtain the relation-
that the number of parallel paths is equal to the ship between ωm and ω(= 2πf ) that results
number of poles for lap windings.) in maximum mmf.
12.2.13 A six-pole, double-layer dc armature winding in 12.3.3 A two-pole, three-phase synchronous generator
28 slots has five turns per coil. If the field flux has a balanced three-phase winding with 15 turns
is 0.025 Wb per pole and the speed of the rotor per phase. If the three-phase currents are given by
is 1200 r/min, find the value of the induced emf ia = 100 cos 377t, ib = 100 cos(377t − 120°),
when the winding is (a) lap connected, and (b) and ic = 100 cos(377t − 240°), determine:
wave-connected. (Note: The number of parallel (a) The peak fundamental component of the
paths is equal to the number of poles for lap wind- mmf of each winding.
ings, while it is equal to 2 for wave windings.)
(b) The resultant mmf.
*12.2.14 A four-pole, dc series motor has a lap-connected,
12.3.4 Consider the balanced three-phase alternating
two-layer armature winding with a total of 400
currents, shown in Figure P12.3.4(a), to be flow-
conductors. Calculate the gross torque developed
ing in phases a, b, and c, respectively, of the two-
for a flux per pole of 0.02 Wb and an armature
pole stator structure shown in Figure P12.3.4(b)
current of 50 A. (Note: The number of parallel
with balanced three-phase windings. For instants
paths is equal to the number of poles for lap
t = t 1, t 3, and t 5 of Figure P12.3.4(a), sketch
windings.)
the individual phase flux contributions and their
*12.3.1 For a balanced two-phase stator supplied by bal- resultants in vectorial form.
anced two-phase currents, carry out the steps 12.4.1 Consider the electromagnetic plunger shown in
leading up to an equation such as Equation Figure P12.4.1. The λ–i relationship for the nor-
(12.3.6) for the rotating mmf wave. mal working range is experimentally found to be
12.3.2 The N-coil windings of a three-phase, two-pole λ = Ki 2/3 /(x + t), where K is a constant. Deter-
machine are supplied with currents ia, ib, and ic, mine the electromagnetic force on the plunger
which produce mmfs given by Fa = N ia cos θm ; by the application of Equations (12.4.19) and
Fb = Nib cos(θm − 120°); and Fc = N ic (12.4.20). Interpret the significance of the sign
cos(θm − 240°), respectively. that you obtain in the force expression.
ia ib ic
c' b
t a a'
c
b'
t1 t2 t3 t4 t5
(a) (b)
Figure P12.3.4
Copyright OUP
PROBLEMS 547
Nonmagnetic
cylindrical sleeve
i
N turns t
Spring
x
Cylindrical plunger
t
x0
x 0: position of plunger when spring is relaxed
Figure P12.4.1
12.4.2 In Problem 12.4.1 neglect the saturation of the and l = 40 mm, find the magnitude of the
core, leakage, and fringing. Neglect also the re- force. Assume infinite permeability of the
luctance of the ferromagnetic circuit. Assuming core and neglect leakage.
that the cross-sectional area of the center leg 12.4.5 Let the solenoid of Problem 12.4.4 carry an al-
is twice the area of the outer legs, obtain ex- ternating current of 10 A (rms) at 60 Hz instead
pressions for the inductance of the coil and the of the direct current.
electromagnetic force on the plunger. (a) Find an expression for the instantaneous
*12.4.3 For the electromagnet shown in Figure P12.4.3, force.
the λ–i relationship for the normal working range (b) For the numerical values of N, g, a, b, and
is given by i = aλ2 + bλ(x − d)2 ,where a and b l given in Problem 12.4.4(b) compute the
are constants. Determine the force applied to the average force. Compare it to that of Problem
plunger by the electric system. 12.4.4(b).
12.4.4 A solenoid of cylindrical geometry is shown in 12.4.6 Consider the solenoid with a core of square cross
Figure P12.4.4. section shown in Figure P12.4.6.
(a) If the exciting coil carries a steady direct (a) For a coil current I (dc), derive an expression
current I, derive an expression for the force for the force on the plunger.
on the plunger. (b) Given I = 10 A, N = 500 turns, g = 5 mm,
(b) For the numerical values I = 10 A, N = 500 a = 20 mm, and b = 2 mm, calculate the
turns, g = 5 mm, a = 20 mm, b = 2 mm, magnitude of the force.
Cylindrical magnetic shell Figure P12.4.3
+ +
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+ +
Coil Coil
+ +
Plunger
d
x
Copyright OUP
N-turn coil Figure P12.4.4
µ=∞
Cylindrical core
Air gap g
b
c
l
µ=∞
a
Nonmagnetic sleeve
Plunger Mean radius of sleeve
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Figure P12.4.6
µ=• Core
Core thickness (into paper) a
I
N
Air gap g
µ=•
Plunger a
b Nonmagnetic sleeve
2a
12.4.7 Let the coil of the solenoid of Problem 12.4.6 a speed, which can be controlled, of ωm rad/s. See
have a resistance R and be excited by a voltage Figure P12.4.8 for the machine configuration.
v = Vm sin ωt. Consider a plunger displacement (a) Find the values of ωm at which the machine
of g = g0 . can develop average torque.
(a) Obtain the expression for the steady-state (b) At each of the speeds obtained in part (a),
coil current. determine the maximum value of the average
(b) Obtain the expression for the steady-state torque and the maximum mechanical power
electric force. output.
*12.4.8 A two-pole rotating machine with a singly ex- Note: Te = ∂Wm (i, θ)/∂θ = 1/2 i 2
cited magnetic field system as its stator and a ∂L(θ)/∂θ. Let θ = ωm t − δ.
rotor (that carries no coil) has a stator-coil in-
12.4.9 Consider Example 12.4.1. With the assumed
ductance that can be approximated by L(θ) =
(0.02 − 0.04 cos 2θ − 0.03 cos 4θ) H, where current-source excitations of part (c), determine
θ is the angle between the stator-pole axis and the voltages induced in the stator and rotor wind-
the rotor axis. A current of 5 A (rms) at 60 Hz is ings at the corresponding angular velocity ωm at
passed through the coil, and the rotor is driven at which an average torque results.
Copyright OUP
PROBLEMS 549
− +
vs
is
Stator
Ns turns
θ = ωmt − δ
Rotor
θ Stator pole axis

(d-axis or
direct axis)
ωm
Rotor axis
Interpole axis
(q-axis or
quadrature axis)
Figure P12.4.8
12.4.10 A two-winding system has its inductances given given by Laa = Lbb. The mutual inductance be-
by tween the stator windings is zero since they are in
k1 k2 space quadrature; the mutual inductance between
L11 = = L22 ; L12 = L21 = a stator winding and the rotor winding depends
x x
where k 1 and k 2 are constants. Neglecting the on the angular position of the rotor,
winding resistances, derive an expression for the Laf = L cos θ; Lbf = L sin θ
electric force when both windings are connected
where L is the maximum value of the mutual in-
to the same voltage source v = Vm sin ωt.
ductance, and θ is the angle between the magnetic
Comment on its dependence on x.
axes of the stator a-phase winding and the rotor
12.4.11 Two mutually coupled coils are shown in Figure
field winding.
P12.4.11. The inductances of the coils are L11 =
A, L22 = B, and L12 = L21 = C cos θ. Find the (a) Let the instantaneous currents be ia, ib, and if
electric torque for: in the respective windings. Obtain a general
expression for the electromagnetic torque Te
(a) i1 = I 0, i2 = 0. in terms of these currents, angle θ , and L.
(b) i1 = i2 = I 0.
(b) Let the stator windings carry balanced two-
(c) i1 = Im sin ωt, i2 = I 0. phase currents given by ia = Ia cos ωt, and
(d) i1 = i2 = Im sin ωt. ib = Ia sin ωt, and let the rotor winding be
(e) Coil 1 short-circuited and i2 = I 0. excited by a constant direct current If. Let the
rotor revolve at synchronous speed so that its
*12.4.12 Consider an elementary cylindrical-rotor two-
instantaneous angular position θ is given by
phase synchronous machine with uniform air
θ = ωt +δ. Derive the torque expression un-
gap, as illustrated in the schematic diagram in
der these conditions and describe its nature.
Figure P12.4.12. It is similar to that of Figure
E12.4.1, except that Figure P12.4.12 has two (c) For conditions of part (b), neglect the re-
identical stator windings in quadrature instead sistance of the stator windings. Obtain the
of one. The self-inductance of the rotor or field volt–ampere equations at the terminals of
winding is a constant given by Lff H; the self- stator phases a and b, and identify the speed–
inductance of each stator winding is a constant voltage terms.
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Copyright OUP
i1 Figure P12.4.11
L11 Fixed coil
i2
Movable coil
L22
Stator a-phase axis Figure P12.4.12
θ
Rotor field winding
magnetic axis
−
+
ia
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Stator b-phase axis
ib
if + −
12.4.13 Consider the machine configuration of Problem

Laa = L0 + L2 cos 2θ; Laf = L cos θ
12.4.12. Let the rotor be stationary and constant
direct currents Ia, Ib, and If be supplied to the Lbb = L0 − L2 cos 2θ; Lbf = L sin θ ;
windings. Further, let Ia and Ib be equal. If the Lab = L2 sin 2θ
rotor is now allowed to move, will it rotate con-
tinuously or will it tend to come to rest? If the Lff is a constant, independent of θ; L0, L2, and L
latter, find the value of θ for stable equilibrium. are positive constants; and θ is the angle between
the magnetic axes of the stator a-phase winding
12.4.14 Let us consider an elementary salient-pole, two-
and the rotor field winding.
phase, synchronous machine with nonuniform air
gap. The schematic representation is the same (a) Let the stator windings carry balanced two-
as for Problem 12.4.12. Structurally the stator phase currents given by ia = Ia cos ωt and
is similar to that of Figure E12.4.1 except that ib = Ia sin ωt, and let the rotor winding be
this machine has two identical stator windings excited by a constant direct current If. Let the
in quadrature instead of one. The salient-pole rotor revolve at synchronous speed so that its
rotor with two poles carries the field winding con- instantaneous angular position θ is given by
nected to slip rings. The inductances are given as θ = ωt + δ. Derive an expression for the
Copyright OUP
PROBLEMS 551
torque under these conditions and describe (e) Cylindrical stator carrying a coil, and a cylin-
its nature. drical rotor.
(b) Compare the torque with that of Problem (f) Cylindrical rotor carrying a coil, and a cylin-
12.4.12(b). drical stator.
(c) Can the machine be operated as a motor? As (g) Cylindrical stator carrying a coil, and a
a generator? Explain. salient-pole rotor.
(d) Suppose that the field current If is brought to (h) Cylindrical rotor carrying a coil, and a
zero. Will the machine continue to run? salient-pole stator.
12.4.15 Consider the analysis leading up to Equation *12.4.19 An elementary two-pole rotating machine with
(12.4.32) for the torque of an elementary cylin- uniform air gap, as shown in Figure E12.4.1, has
drical machine with uniform air gap. a stator-winding self-inductance Lss of 50 mH, a
(a) Express the torque in terms of F, Fs, and δ s, rotor-winding self-inductance Lrr of 50 mH, and
where δ s is the angle between F̄ and F̄s . a maximum mutual inductance L of 45 mH. If the
(b) Express the torque in terms of F, Fr, and δ r, stator were excited from a 60-Hz source, and the
where δ r is the angle between F̄ and F̄r . rotor were excited from a 25-Hz source, at what
speed or speeds would the machine be capable of
(c) Neglecting magnetic saturation, obtain the converting energy?
torque in terms of B, Fr, and δ r, where B is
12.4.20 A rotating electric machine with uniform air gap
the peak value of the resultant flux-density
has a cylindrical rotor winding with inductance
wave.
L2 = 1 H and a stator winding with inductance L1
(d) Let φ be the resultant flux per pole given by = 3 H. The mutual inductance varies sinusoidally
the product of the average value of the flux with the angle θ between the winding axes, with a
density over a pole and the pole area. Express maximum of 2 H. Resistances of the windings are
the torque in terms of φ, Fr, and δ r, where φ is negligible. Compute the mean torque if the stator
the resultant flux produced by the combined current is 10 A (rms), the rotor is short-circuited,
effect of the stator and rotor mmfs. and the angle between the winding axes is 45°.
12.4.16 An electromagnetic structure is characterized by 12.4.21 The self and mutual inductances of a machine
the inductances L11 = L22 = 4 + 2 cos 2θ with two windings are given by L11 = (1 +
and L12 = L21 = 2 + cos θ. Neglecting the sin θ), L22 = 2(1 + sin θ), and L12 = L21 =
resistances of the windings, find the torque as a M = (1 − sin θ). Assuming θ = 45°, and letting
function of θ when both windings are connected coils 1 and 2 be supplied by constant currents I 1
to the same ac voltage source such that = 15 A and I2 = −4 A, respectively, find the
√
v1 = v2 = 220 2 sin 314t following:
12.4.17 By using the concept of interaction between mag- (a) Magnitude and direction of the developed
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
netic fields, show that the electromagnetic torque torque.
cannot be obtained by using a four-pole rotor in (b) Amount of energy supplied by each source.
a two-pole stator.
(c) Rms value of the current in coil 2, if the
12.4.18 For each of the following devices, is a reluctance current of coil 1 is changed to a sinusoidal
torque produced when their coils carry direct current of 10 A (rms) at 60 Hz and coil 2 is
current? short-circuited.
(a) Salient-pole stator carrying a coil, and a (d) Instantaneous torque produced in part (c).
salient-pole rotor.
(e) Average torque in part (c).
(b) Salient-pole rotor carrying a coil, and a
salient-pole stator. 12.4.22 Consider the elementary two-pole rotating ma-
chine with uniform air gap shown in Figure
(c) Salient-pole stator carrying a coil, and a E12.4.1. Let Ns be the number of turns on the
cylindrical rotor. stator, Nr the number of turns on the rotor, l the
(d) Salient-pole rotor carrying a coil, and a cylin- axial length of the machine, r the radius of the
drical stator. rotor, and g the length of the air gap.
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(a) Obtain expressions for self and mutual in- (a) Calculate the full-load efficiency.
ductances, assuming infinite permeability (b) Compute the efficiency at one-half load, as-
for the magnetic cores. suming that the stray-loss and rotational
(b) Find the expression for the electromagnetic losses do not change with load.
torque in terms of currents is and ir and angle 12.5.2 A synchronous motor operates continuously on
θ. the following duty cycle: 50 hp for 8 min, 100
(c) Show that the expression of part (b) is equiv- hp for 8 min, 150 hp for 10 min, 120 hp for 20
alent to min, and no load for 14 min. Specify the required
πµ0 rl continuous-rated hp of the motor. (Note: A motor
Te = − Fs Fr sin δ rating is normally chosen on the basis of the rms
g
value given by
3 ,
12.5.1 A certain 10-hp, 230-V motor has a rotational (hp)2 (time)
loss of 600 W, a stator copper loss of 350 W, a rms hp =
running time + standstill time/k
rotor copper loss of 350 W, and a stray load loss
of 50 W. It is not known whether the motor is an where k is a constant accounting for reduced
induction, synchronous, or dc machine. ventilation at standstill.)
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13 Rotating Machines
13.1 Elementary Concepts of Rotating Machines
13.2 Induction Machines
13.3 Synchronous Machines
13.4 Direct-Current Machines
13.6 Practical Application: A Case Study—Wind-Energy-Conversion Systems
Problems
The most widely used electromechanical device is a rotating machine, which utilizes the magnetic
field to store energy. The main purpose of most rotating machines is to convert electromechanical
energy, i.e., to convert energy between electrical and mechanical systems, either for electric power
generation (as in generators or sources) or for the production of mechanical power to perform
useful tasks (as in motors or sinks). Rotating machines range in size and capacity from small motors
that consume only a fraction of a watt to large generators that produce several hundred megawatts.
In spite of the wide variety of types, sizes, and methods of construction, all such machines operate
on the same principle, namely, the tendency of two magnets to align themselves.
Most space is devoted to induction, synchronous, and direct-current machines. In spite of the
distinguishing features peculiar to each class of machines, there are several striking similarities
among the main kinds of machines.
13.1 ELEMENTARY CONCEPTS OF ROTATING MACHINES

Some of the basic features of conventional ac (particularly synchronous) and dc machines have
been introduced in Chapter 12. More will be presented in this section. Three modes of operation of
a rotating electric machine—motoring, generating, and braking—are illustrated in Figure 13.1.1.
1. The motoring mode has electric power input and mechanical power output. The electro-
magnetic torque Te drives the machine against the load torque T. The input voltage v drives the
current into the winding against the generated emf e.
553
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554 ROTATING MACHINES
T Figure 13.1.1 Three modes of operation of

a rotating electric machine. (a) Motoring
i mode. (b) Generating mode. (c) Braking
+
Te, ωm mode.
Field
v e
Armature
(a)
Te
i
+
T, ωm
Field
v e
Armature
(b)
T, ωm
i
+
Te
Field
v e
Armature
(c)
2. The generating mode has mechanical power input and electric power output. The torque
T applied externally to the shaft drives the machine against the electrically developed torque Te.
The generated emf e drives current out of the winding against the terminal voltage v.
3. The braking mode has both mechanical and electric energy input. The total input is dissi-
pated as heat. The machine is driven by the externally applied torque T, while the electromagnetic
torque Te is opposing T, thereby braking the machine. The electric braking of motor drives
is achieved by causing the motor to act as a generator, receiving mechanical energy from the
moving parts and converting it to electric energy, which is dissipated in a resistor or pumped
back into the power line. Note that the applied voltage v and the generated emf e do not oppose
each other.
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As mentioned in Section 12.3, polyphase windings can be arranged to yield sinusoidally

distributed current sheets and rotating mmfs. A number of possible doubly excited combinations,
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13.1 ELEMENTARY CONCEPTS OF ROTATING MACHINES 555
satisfying ωs = ωm ± ωr , which relates electrical and mechanical angular speeds, exist, giving
rise to the names by which the machines are generally known, synchronous, induction, or dc
machines.
Elementary Synchronous Machines

The polyphase synchronous machine operates with direct current supplied to the field winding
(assumed to be on the rotor, which is usually the case) through two slip rings and with polyphase
alternating current supplied to the armature (assumed to be on the stator). The rotor mmf, which is
obtained from a dc source, is stationary with respect to the rotor structure. When carrying balanced
polyphase currents, as shown in Section 12.3, the armature winding produces a magnetic field in
the air gap rotating at synchronous speed [Equation (12.2.9) or (12.2.10)], as determined by the
system frequency and the number of poles in the machine. But the field produced by the dc rotor
winding revolves with the rotor. To produce a steady unidirectional torque, the rotating fields of
stator and rotor must be traveling at the same speed. Therefore, the rotor must turn precisely at
the synchronous speed. Such conditions satisfy the second possibility for the development of a
constant torque suggested in the discussion following Equation (12.4.32). The resulting physical
system is shown in Figure 13.1.2.
The polyphase synchronous machine is one in which the rotor rotates in synchronism with
and in the same direction as the rotating mmf wave produced by the stator. Thus for synchronous
machines with polyphase stator winding, the following equation relating mechanical and electrical
angular speeds is satisfied:
2πf
ωm = ωs = (13.1.1)
P /2
or alternatively, the steady-state speed at which the machine operates is known as the synchronous
speed, given by
Axis of stator field Figure 13.1.2 Simplified two-pole

F
Fs synchronous machine with non-
Axis of resultant field salient poles.
ωs
ωs
S
ωs
Fr
δr Axis of rotor field
N
δ
Air gap
ωm = ωs
Rotor
S
Stator
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120f
Synchronous speed = r/min (13.1.2)
P
where f is the frequency of the system of which the machine is a part and P is the number of poles
of the machine.
The electromagnetic torque, produced by the nonsalient-pole (or cylindrical-rotor) machine,
can be expressed in terms of the resultant flux φ per pole produced by the combined effect of the
stator and rotor mmfs (see Problem 12.4.15),
Te = Kφ Fr sin δr (13.1.3)
where K is a constant, Fr is the rotor mmf, and δr is the angle between the rotor mmf and the
resultant flux or mmf axis. When the armature terminals are connected to a balanced polyphase
infinite bus (which is a high-capacity, constant-voltage, constant-frequency system), the resultant
air-gap flux φ is approximately constant, independent of the shaft load. Under normal operating
conditions the resultant air-gap flux φ, which is given by Equation (12.2.13) as
terminal phase voltage
φ= (13.1.4)
4.44 kW f Nph
is essentially constant. The rotor mmf Fr determined by the direct field current is also a constant
under normal operating conditions. So, as seen from Equation (13.1.3), any variation in the torque
requirements of the load has to be accounted for entirely by variation of the angle δr , which is
why δr is known as the torque angle (or load angle) of a synchronous machine. The effect of
salient poles on the torque-angle characteristic is discussed in Section 13.3.
The torque-angle characteristic curve of a cylindrical-rotor synchronous machine is shown
in Figure 13.1.3 as a function of the angle δr . For δr < 0, Te > 0, the developed torque is positive
and acts in the direction of the rotation; the machine operates as a motor. If, on the other hand,
the machine is driven by a prime mover so that δr becomes positive, the torque is then negative,
and the machine operates as a generator. Note that at standstill, i.e., when ωm = 0, no average
unidirectional torque is developed by the synchronous machine. Such a synchronous motor is not
capable of self-starting because it has no starting torque. The designer must provide a method for
bringing the machine up to synchronous speed.
Te (or power) Figure 13.1.3 Torque-angle char-

acteristic curve of a cylindrical-
rotor synchronous machine (for a
given field current and a fixed ter-
Pull-out torque as a motor minal voltage, i.e., for a constant
resultant air-gap flux).
π Torque
angle, δr
−π −π/2 π/2
Pull-out torque as a generator
Motor operation Generator operation

Te > 0 Te < 0
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Figure 13.1.4 Sketch of damper bars located on salient-

pole shoes of a synchronous machine.
Because a synchronous machine operates only at synchronous speed under steady-state

conditions, the machine cannot operate at synchronous speed during the load transition when the
load on the synchronous machine is to be changed; the readjustment process is in fact dynamic.
In the case of a generator connected to an infinite bus, an increase in the electric output power of
the generator is brought about by increasing the mechanical input power supplied by the prime
mover. The speed of the rotor increases momentarily during the process, and the axis of the rotor-
field mmf advances relative to the axes of both the armature mmf and the resultant air-gap mmf.
The increase in torque angle results in an increase in electric power output. The machine then
locks itself into synchronism and continues to rotate at synchronous speed until the load changes
further. The same general argument can be made for the operation of a synchronous motor, except
that an increase in mechanical load decreases the speed of the rotor during the transition period,
so that the axis of the rotor-field mmf falls behind that of the stator mmf or the resultant air-gap
mmf by the required value of the load angle.
When the load on a synchronous machine changes, the load angle changes from one steady
value to another. During this transition, oscillations in the load angle and consequent associated
mechanical oscillations (known as hunting) occur. To damp out these oscillations, it is common
practice to provide an additional short-circuited winding on the field structure, made out of copper
or brass bars located in pole-face slots on the pole shoes of a salient-pole machine and connected
together at the ends of the machine. This additional winding (known as damper or amortisseur
winding) is shown in Figure 13.1.4. The winding is also useful in getting a synchronous motor
started, as explained in the subsection on elementary induction machines. When the machine
is operating under steady-state conditions at synchronous speed, however, this winding has no
effect. Because there is no rate of change of flux linkage, no voltage is induced in it.
As seen in Figure 13.1.3, when δr is ±π/2 or 90°, the maximum torque or power (called pull-
out torque or pull-out power) is reached for a fixed terminal voltage and a given field current. If the
load requirements exceed this value, the motor slows down because of the excess shaft torque.
Synchronous-motor action is lost because the rotor and stator fields are no longer stationary
with respect to each other. Any load requiring a torque greater than the maximum torque results
in unstable operation of the machine; the machine pulls out of synchronism, known as pulling
out of step or losing synchronism. The motor is usually disconnected from the electric supply by
automatic circuit breakers, and the machine comes to a standstill. Note that the pull-out torque can
be increased by increasing either the field current or the terminal voltage. In the case of a generator
connected to an infinite bus, synchronism will be lost if the torque applied by the prime mover
exceeds the maximum generator pull-out torque. The speed will then increase rapidly unless the
quick-response governor action comes into play on the prime mover to control the speed.
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Elementary Induction Machines

In the discussion that followed Equation (12.4.32), the third possible method of producing constant
torque was to cause the mmf axes of stator and rotor to rotate at such speeds relative to their
windings that they remain stationary with respect to each other. If the stator and rotor windings
are polyphase and carry polyphase alternating current, then both the stator mmf and the rotor
mmf axes may be caused to rotate relative to their windings. Such a machine will have polyphase
stator ac excitation at ωs , polyphase rotor ac excitation at ωr , and the rotor speed ωm satisfying
ωm = ωs − ωr (13.1.5)
Let us consider the rotor speed given by Equation (13.1.5) and the same phase sequence of
sources. A rotating magnetic field of constant amplitude, rotating at ωs rad/s relative to the
stator, is produced because of polyphase stator excitation. A rotating magnetic field of constant
amplitude, rotating at ωs rad/s relative to the rotor, is also produced because of polyphase rotor
excitation. The speed of rotation of the rotor magnetic field relative to the stator is ωm + ωr , or
ωs , if the rotor is rotating with a positive speed of rotation ωm in the direction of the rotating
fields. If so, the condition for energy conversion at constant torque is satisfied. Such a situation
is illustrated diagrammatically in Figure 13.1.5. Under these conditions the machine is operating
as a double-fed polyphase machine. Normally, in an induction machine with polyphase stator
and rotor windings, only a source to excite the stator is employed, and the rotor excitation at
the appropriate frequency is induced from the stator winding. The device is thus known as an
induction machine.
In an induction machine, the stator winding is essentially the same as in a synchronous
machine. Equation (12.2.13) and the considerations leading to it hold here as in the case of a
synchronous machine. When excited from a balanced polyphase source, the polyphase windings
produce a magnetic field in the air gap rotating at a synchronous speed determined by the number
of poles and the applied stator frequency given by Equation (12.2.9). On the rotor, the winding is
electrically closed on itself (i.e., short-circuited) and often has no external terminals.
The induction machine rotor may be one of two types: the wound rotor or the squirrel-cage
rotor. The wound rotor has a polyphase winding similar to and wound for the same number of
poles as the stator winding. The terminals of the rotor winding (wye- or delta-connected, in the
case of three-phase machines) are brought to insulated slip rings mounted on the shaft. Carbon
brushes bearing on these slip rings make the rotor terminals available to the circuitry external to
Fs Fr Figure 13.1.5 Mmf axes of an induction machine.

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ωm + ωr = ωs
ωs Stator
S
δ
N
S
ωm
Rotor
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the motor. The rotor winding is usually short-circuited through external resistances that can be
varied. A squirrel-cage rotor has a winding consisting of conducting bars of copper or aluminum
embedded in slots cut in the rotor iron and short-circuited at each end by conducting end rings.
The squirrel-cage induction machine is the electromagnetic machine most widely used as a motor
because of its extreme simplicity and ruggedness. Although the induction machine in the motor
mode is the most common of all motors, the induction machine has very rarely been used as
a generator because its performance characteristics as a generator are not satisfactory for most
applications; however, it has recently been used as a wind-power generator. The induction machine
with a wound rotor is also used as a frequency changer.
The polyphase induction motor operates with polyphase alternating current applied to the
primary winding, usually located on the stator of the polyphase machines. Three-phase motors are
most used commercially in practice, whereas two-phase motors are used in control systems. The
induction machine has emf (and consequently current) induced in the short-circuited secondary
(or rotor) winding by virtue of the primary rotating mmf. Such a machine is then singly excited.
The induction machine may be regarded as a generalized transformer in which energy conversion
takes place, and electric power is transformed between the stator and the rotor along with a change
of frequency and a flow of mechanical power.
Let us assume that the rotor is turning at a steady speed of n r/min in the same direction as
the rotating stator field. Let the synchronous speed of the stator field be n1 r/min, as given by
Equation (12.2.9), corresponding to the applied stator frequency fs Hz, or ωs rad/s. It is convenient
to introduce the concept of per-unit slip S given by
synchronous speed − actual rotor speed n1 − n ωs − ω m
S= = = (13.1.6)
synchronous speed n1 ωs
The rotor is then traveling at a speed of n1 − n or n1 S r/min in the backward direction with
respect to the stator field. The relative motion of the flux and rotor conductors induces voltages
of frequency Sfs, known as the slip frequency, in the rotor winding. Thus, the induction machine
is similar to a transformer in its electrical behavior but with an additional feature of frequency
change. The frequency fr Hz of the secondary (or rotor) currents is then given by
ωr
fr = = Sfs (13.1.7)
2π
At standstill, ωm = 0, so that the slip S = 1 and fr = fs ; that is, the machine then acts as a simple
transformer with an air gap and a short-circuited secondary winding. A steady starting torque is
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produced because the condition for energy conversion at constant torque is satisfied; hence the
polyphase induction motor is self-starting. At synchronous speed, however, ωm = ωs , so that the
slip S = 0 and fr = 0; no induction takes place because there is no relative motion between flux
and rotor conductors. Thus, at synchronous speed, the value of the secondary mmf is zero, and
no torque is produced; that is, the induction motor cannot run at synchronous speed. The no-load
speed of the induction motor is usually on the order of 99.5% of synchronous speed so that the
no-load per-unit slip is about 0.005, and the full-load per-unit slip is on the order of 0.05. Thus,
the polyphase induction motor is effectively a constant-speed machine.
An induction machine, connected to a polyphase exciting source on its stator side, can be
made to generate (i.e., with the power flow reversed compared to that of a motor) if its rotor is
driven mechanically by an external means at above synchronous speed, so that ωm > ωs and
the slip becomes negative. If the machine is driven mechanically in the direction opposite to
its primary rotating mmf, then the slip is greater than unity and the machine acts as a brake. For
example, let the machine be operating normally as a loaded motor; if two of the three phase supply
lines to the stator are reversed, the direction of the stator rotating mmf will reverse. The rotor will
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then be rotating in the direction opposite that of the rotating mmf, so the machine will act as a
brake and the speed will rapidly come to zero, at which time the electric supply can be removed
from the machine. Such a reversal of two supply lines of the three-phase system, a useful method
of stopping the motor rapidly, is generally referred to as plugging or plug-braking. If the electric
supply is not removed at zero speed, however, the machine will reverse its direction of rotation
because of the change of phase sequence of the supply resulting from the interchange of the two
stator leads. The general form of the torque–speed curve (or torque–slip characteristic) for the
polyphase induction machine between rotor speed limits of −ωs ≤ ωm ≤ 2ωs , corresponding to
a range of slips −1 ≤ S ≤ 2, is shown in Figure 13.1.6.
The torque that exists at any mechanical speed other than synchronous speed is known as an
asynchronous torque. The induction machine is also known as an asynchronous machine, since no
torque is produced at synchronous speed and the machine runs at a speed other than synchronous
speed. In fact, as a motor, the machine runs only at a speed that is less than synchronous speed
with positive slip. The factors influencing the general shape of the torque-speed characteristic
(shown in Figure 13.1.6) can be appreciated in terms of the torque equation, Equation (13.1.3).
Noting that the resultant air-gap flux φ is nearly constant when the stator-applied voltage and
frequency are constant, as seen by Equation (13.1.4), and that the rotor mmf Fr is proportional to
the rotor current ir, the torque may be expressed as
Te = K1 ir sin δr (13.1.8)
where K 1 is a constant and δr is the angle between the rotor mmf axis and the resultant flux or mmf
axis. The rotor current ir is determined by the rotor-induced voltage (proportional to slip) and the
rotor impedance. Since the slip is small under normal running conditions, as already mentioned,
the rotor frequency fr = Sfs is very low (on the order of 3 Hz in 60-Hz motors with a per-unit slip
of 0.05). Hence, in this range the rotor impedance is largely resistive, and the rotor current is very
nearly proportional to and in phase with the rotor voltage; that is, the rotor current is very nearly
proportional to slip. An approximately linear torque–speed relationship can be observed in the
range of low values of slip in Figure 13.1.6. Further, with the rotor-leakage reactance being very
small compared with the rotor resistance, the rotor mmf wave lags approximately 90 electrical
degrees behind the resultant flux wave, and therefore sin δr is approximately equal to unity.
As slip increases, the rotor impedance increases because of the increasing effect of rotor-
leakage inductance; the rotor current is then somewhat less than proportional to slip. The rotor
current lags further behind the induced voltage, and the rotor mmf wave lags further behind the
resultant flux wave, so that sin δr decreases. The torque increases with increasing values of slip
up to a point and then decreases, as shown in Figure 13.1.6 for the motor region. The maximum
torque that the machine can produce is sometimes referred to as the breakdown torque, because it
limits the short-time overload capability of the motor. Higher starting torque can be obtained by
inserting external resistances in the rotor circuit, as is usually done in the case of the wound-rotor
induction motor. These resistances can be cut out for the normal running conditions in order to
operate the machine with a higher efficiency. Recall that a synchronous motor has no starting
torque. It is usually provided with a damper or amortisseur winding located in the rotor pole
faces. Such a winding acts like a squirrel-cage winding to make the synchronous motor start as an
induction motor and come up almost to synchronous speed, with the dc field winding unexcited. If
the load and inertia are not too large, the motor will pull into synchronism and act as a synchronous
motor when the field winding is energized from a dc source.
So far the discussion of induction machines applies only to machines operating from a
polyphase supply. Of particular interest is the single-phase induction machine, which is widely
used as a fractional-horsepower ac motor supplying the motive power for all kinds of equipment
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Torque Figure 13.1.6 General form of

torque–speed curve (or torque–
slip characteristic) for a poly-
phase induction machine.
Q
S
−ωs R 0 P ωs Speed 2ωs
2 1 0 Slip −1
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Braking Motor Generator

region region region
in the home, office, and factory. For the sake of simplicity, let us consider a single-phase induction
motor with a squirrel-cage rotor and a stator carrying a single-phase winding, connected to a single-
phase ac supply. The primary mmf cannot be rotating, but, in fact, it is pulsating in phase with
the variations in the single-phase primary current. It can be shown, however, that any pulsating
mmf can be resolved in terms of two rotating mmfs of equal magnitude, rotating in synchronism
with the supply frequency but in opposite directions (see Section 12.3). The wave rotating in the
same direction as the rotor is known as the forward-rotating wave, whereas the one rotating in
the opposite direction is the backward-rotating wave. Then the slip S of the machine with respect
to the forward-rotating wave is given by
ωs − ωm
Sf = (13.1.9)
ωs
which is the same as Equation (13.1.6). The slip Sb of the machine with respect to the backward-
rotating wave, however, is given by
−ωs − ωm
Sb = = 2 − Sf (13.1.10)
ωs
Sf and Sb are known as forward (or positive-sequence) slip and backward (or negative-sequence)
slip, respectively. Assuming that the two component mmfs exist separately, the frequency and
magnitude of the component emfs induced in the rotor by their presence will, in general, be
different because Sf is not equal to Sb. Then the machine can be thought of as producing a steady
total torque as the algebraic sum of the component torques. The equivalent circuit based on
the revolving-field theory is pursued in Section 13.2. At standstill, however, ωm = 0 and the
component torques are equal and opposite; no starting torque is produced. Thus, it is clear that
a single-phase induction motor is not capable of self-starting, but it will continue to rotate once
started in any direction. In practice, additional means are provided to get the machine started
(usually as an asymmetrical two-phase motor) from a single-phase source, and the machine is
then run as a single-phase motor. An approximate shape of the torque–speed curve for the single-
phase motor can readily be obtained from that of the three-phase machine shown in Figure 13.1.6.
Corresponding to a positive slip of Sf = OP in Figure 13.1.6, the positive-sequence torque is PQ.
Then, corresponding to Sb = 2 − Sf = OR, the negative-sequence torque is RS. The resultant
torque is given by P Q − RS. This procedure can be repeated for a range of slips 1 ≤ S ≤ 0
to give the general form of the torque–speed characteristic of a single-phase induction motor, as
Copyright OUP
Torque Figure 13.1.7 Approximate shape of

torque–speed curve for a single-phase
induction motor.
ωs
Speed
0
Elementary Direct-Current Machines

A preliminary discussion of dc machines, including Equations (12.2.14) through (12.2.18), was
presented in Section 12.2. The location of the brushes on the commutator arrangement connected
to the armature winding ensures that the rotor and stator mmf axes are at all times at right angles
to one another, as shown in Figure 12.2.4. The expression for torque given by Equation (12.4.32)
is applicable to the dc machine, provided the constant K is adjusted for the nonsinusoidal mmf
distributions and sin δ is made equal to unity. Not only are the conditions for constant torque
fulfilled, but also the condition for maximum torque and hence for maximum energy conversion
is satisfied, since δ = ±π/2, depending upon whether generator or motor action occurs for a
given direction of rotation.
Since both armature and field circuits carry direct current in the case of a dc machine, they can
be connected either in series or in parallel. When the armature and field circuits are connected in
parallel, the machine is known as a shunt machine. In the shunt machine, the field coils are wound
with a large number of turns carrying a relatively small current. When the circuits are connected
in series, the machine is known as a series machine. The field winding in the series machine
carries the full armature current and is wound with a smaller number of turns. A dc machine
provided with both a series-field and a shunt-field winding is known as a compound machine. In
the compound machine, the series field may be connected either cumulatively, so that its mmf adds
to that of the shunt field, or differentially, so that the mmf opposes. The differential connection is
used very rarely. The voltage of both shunt and compound generators (or the speed, for motors) is
controlled over reasonable limits by means of a field rheostat in the shunt field. The machines are
said to be self-excited when the machine supplies its own excitation of the field windings, as in
the cases just defined. The field windings may be excited separately from an external dc source,
however. A small amount of power in the field circuit can control a large amount of power in
the armature circuit. The dc generator may then be viewed as a power amplifier. Some possible
field-circuit connections of dc machines are shown in Figure 13.1.8.
For self-excited generators, residual magnetism must be present in the ferromagnetic circuit
of the machine in order to start the self-excitation process. For a dc generator, the relationship
between steady-state generated emf Ea and the terminal voltage Vt is given by
Vt = Ea − Ia Ra (13.1.11)
where Ia is the armature current output, and Ra is the armature circuit resistance. For a dc motor,
the relationship is given by
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13.2 INDUCTION MACHINES 563
Field
Field rheostat
Armature Armature
Field Shunt field

rheostat
Dc source
(a) (b)
Field rheostat
Armature Series field
Armature Series field
Shunt field
(c) (d)
Figure 13.1.8 Field-circuit connections of dc machines. (a) Separately excited machine. (b) Shunt machine.
(c) Series machine. (d) Compound machine.
Vt = Ea + Ia Ra (13.1.12)
where Ia is now the armature current input. Under steady-state conditions, volt–ampere charac-
teristic curves are of interest for dc generators, and speed–torque characteristics are of interest
for dc motors. Depending on the method of excitation of the field windings, a wide variety of
operating characteristics can be obtained. These possibilities make the dc machine both versatile
and adaptable for control. More about dc machines is presented in Section 13.4.
13.2 INDUCTION MACHINES

We shall first consider polyphase induction motors and then single-phase induction motors. The
polyphase induction motors used in industrial applications are almost without exception three-
phase. The stator winding is connected to the ac source, and the rotor winding is either short-
circuited, as in squirrel-cage machines, or closed through external resistances, as in wound-rotor
machines. The cage machines are also known as brushless machines; the wound-rotor machines
are also called slip-ring machines.
A review of the subsection on elementary induction machines in Section 13.1 can be helpful
at this stage to recall the operating principle of polyphase induction machines.
Equivalent Circuit of a Polyphase Induction Machine

The induction machine may be regarded as a generalized transformer in which energy is converted
and electric power is transferred between stator and rotor, along with a change of frequency and a
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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flow of mechanical power. At standstill, however, the machine acts as a simple transformer with
an air gap and a short-circuited secondary winding. The frequency of the rotor-induced emf is
the same as the stator frequency at standstill. At any value of the slip under balanced steady-state
operation, the rotor current reacts on the stator winding at the stator frequency because the rotating
magnetic fields caused by the stator and rotor are stationary with respect to each other.
The induction machine may thus be viewed as a transformer with an air gap and variable
resistance in the secondary; the stator of the induction machine corresponds to the transformer
primary, and the rotor corresponds to the secondary. For analysis of the balanced steady state, it
is sufficient to proceed on a per-phase basis with some phasor concepts; so we will now develop
an equivalent circuit on a per-phase basis. Only machines with symmetrical polyphase windings
excited by balanced polyphase voltages are considered. As in other discussions of polyphase
devices, let us think of three-phase machines as wye-connected, so that currents are always line
values and voltages are always line-to-neutral values (on a per-phase basis).
The resultant air-gap flux is produced by the combined mmfs of the stator and rotor currents.
For the sake of conceptual and analytical convenience, the total flux is divided into a mutual flux
(linking both the stator and the rotor) and leakage fluxes, represented by appropriate reactances.
Considering the conditions in the stator, the synchronously rotating air-gap wave generates
balanced polyphase counter emfs in the phases of the stator. The volt–ampere equation for the
phase under consideration in phasor notation is given by
V̄1 = Ē1 + I¯1 (R1 + j Xl 1 ) (13.2.1)
where V̄1 is the stator terminal voltage, Ē1 is the counter emf generated by the resultant air-gap
flux, I¯1 is the stator current, R1 is the stator effective resistance, and X l1 is the stator-leakage
reactance.
As in a transformer, the stator (primary) current can be resolved into two components:
a load component I¯2 (which produces an mmf that exactly counteracts the mmf of the rotor
current) and an excitation component I¯0 (required to create the resultant air-gap flux). This
excitation component itself can be resolved into a core-loss component I¯c in phase with Ē1
I1 R1 jXl1 I'2 Figure 13.2.1 Equivalent circuit for the stator

phase of a polyphase induction motor.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
+ +
I0
Ic Im
V1 gc −jbm E1
− −
jSXl2 Figure 13.2.2 Slip-frequency equivalent circuit for the rotor

I2 phase of a polyphase induction motor.
+
SE2 R2
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and a magnetizing component I¯m lagging Ē1 by 90°. A shunt branch formed by the core-loss
conductance gc and magnetizing susceptance bm in parallel, connected across Ē1 , will account for
the exciting current in the equivalent circuit, as shown in Figure 13.2.1, along with the positive
directions in a motor.
Thus far the equivalent circuit representing the stator phenomenon is exactly like that of the
transformer primary. Because of the air gap, however, the value of the magnetizing reactance
tends to be relatively low compared to that of a transformer, and the leakage reactance is larger
in proportion to the magnetizing reactance than it is in transformers. To complete the equivalent
circuit, the effects of the rotor must be incorporated, which we do by referring the rotor quantities
to the stator.
Because the frequency of the rotor voltages and currents is the slip frequency, the magnitude
of the voltage induced in the rotor circuit is proportional to the slip. Also, in terms of the standstill
per-phase rotor-leakage reactance X l2, the leakage reactance at a slip S is given by SX l2. With R2
as the per-phase resistance of the rotor, the slip-frequency equivalent circuit for a rotor phase is
shown in Figure 13.2.2, in which E2 is the per-phase voltage induced in the rotor at standstill. The
rotor current I 2 is given by
SE2
I2 = (13.2.2)
R22 + (SXl2 )2
E2
I2 = (13.2.3)
(R2 /S)2 + Xl2
2
resulting in the alternate form of the per-phase rotor equivalent circuit shown in Figure 13.2.3.
All rotor electrical phenomena, when viewed from the stator, become stator-frequency
phenomena because the stator winding sees the mmf and flux waves traveling at synchronous
jXl2 Figure 13.2.3 Alternate form of a per-phase rotor equivalent

I2 circuit.
+
R2
E2 S
jXl1 jXl2
R1
I1 I'2 I2
+
I0 + +
Ic Im R2
V1 E1 E2 S
gc −jbm
− −
Figure 13.2.4 Per-phase equivalent coupled circuit of a polyphase induction motor.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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speed. Returning to the analogy of a transformer, and considering that the rotor is coupled to the
stator in the same way the secondary of a transformer is coupled to its primary, we may draw the
equivalent circuit as shown in Figure 13.2.4.
Referring the rotor quantities to the stator, we can now draw the per-phase equivalent circuit
of the polyphase induction motor, as shown in Figure 13.2.5(a). The combined effect of the shaft
load and the rotor resistance appears as a reflected resistance R2 /S, which is a function of slip and
therefore of the mechanical load. The quantity R2 /S may conveniently be split into two parts:
R2 R (1 − S)
= R2 + 2 (13.2.4)
S S
jXl1 jX 'l2
R1
I1 I'2
+ +
I0
Ic Im R'2
V1 E 1 = E'2 S
gc −jbm
−
−
(a)
jXl1 jX 'l2
R1 R'2
I1 I'2
+ +
I0
Ic Im R'2 (1 − S)
V1 E 1 = E '2 S
gc −jbm
−
−
(b)
jXl1 jX 'l2
R1 R'2
I1 I'2
+
I0
R'2 (1 − S)
V1 −jbm S
−
(c)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Figure 13.2.5 Per-phase equivalent circuits of a polyphase induction motor, referred to the stator.
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and the equivalent circuit may be redrawn as in Figure 13.2.5(b). R2 is the per-phase standstill
rotor resistance referred to the stator, and R2 [(1 − S)/S] is a dynamic resistance that depends on
the rotor speed and corresponds to the load on the motor. [See the discussion following Equation
(13.2.6).]
When power aspects need to be emphasized, the equivalent circuit is frequently redrawn as
in Figure 13.2.5(c), in which the shunt conductance gc is omitted. The core losses can be included
in efficiency calculations along with the friction, windage, and stray-load losses.
Recall that, in static transformer theory, analysis of the equivalent circuit is often simplified
either by neglecting the exciting shunt branch entirely, or by adopting the approximation of moving
it out directly to the terminals. For the induction machine, however, such approximations might
not be permissible under normal running conditions because the air gap leads to a much higher
exciting current (30 to 50% of full-load current) and relatively higher leakage reactances.
The parameters of the equivalent circuit of an induction machine can be obtained from the
no-load (in which the motor is allowed to run on no load) and blocked-rotor (in which the rotor
of the induction motor is blocked so that the slip is equal to unity) tests. These tests correspond
to the no-load and short-circuit tests on the transformer, and are very similar in detail.
Polyphase Induction Machine Performance

Some of the important steady-state performance characteristics of a polyphase induction motor
include the variation of current, speed, and losses as the load–torque requirements change, and the
starting and maximum torque. Performance calculations can be made from the equivalent circuit.
All calculations can be made on a per-phase basis, assuming balanced operation of the machine.
Total quantities can be obtained by using an appropriate multiplying factor.
The equivalent circuit of Figure 13.2.5(c), redrawn for convenience in Figure 13.2.6, is
usually employed for the analysis. The core losses, most of which occur in the stator, as well as
friction, windage, and stray-load losses, are included in the efficiency calculations. The power-
flow diagram for an induction motor is given in Figure 13.2.7, in which m1 is the number of stator
phases, φ 1 is the power factor angle between V̄1 and I¯1 , φ 2 is the power factor angle between Ē1
and I¯2 , T is the internal electromagnetic torque developed, ωs is the synchronous angular velocity
in mechanical radians per second, and ωm is the actual mechanical rotor speed given by ωs (1 − S).
The total power Pg transferred across the air gap from the stator is the difference between the
electric power input Pi and the stator copper loss. Pg is thus the total rotor input power, which is
dissipated in the resistance R2 /S of each phase so that
R
Pg = m1 (I2 )2 2 = T ωs (13.2.5)
S
Subtracting the total rotor copper loss, which is m1 (I2 )2 R2 or SPg, from Equation (13.2.5) for
Pg, we get the internal mechanical power developed,
jXl1 jX 'l2 Figure 13.2.6 Per-phase equivalent

R1 R'2
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
I1 I'2 circuit of a polyphase induction

+ motor used for performance
I0 calculations.
R'2 (1 − S)
V1 jXm E1 S
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R2 (1 − S)
Pm = Pg (1 − S) = T ωm = m1 (I2 )2 (13.2.6)
S
This much power is absorbed by a resistance of R2 (1 − S)/S, which corresponds to the load.
For this reason, the resistance term R2 /S has been split into two terms, as in Equation (13.2.4)
and shown in the equivalent circuit of Figure 13.2.6. From Equation (13.2.6) we can see that of
the total power delivered to the rotor, the fraction 1 − S is converted to mechanical power and
the fraction S is dissipated as rotor copper loss. We can then conclude that an induction motor
operating at high slip values will be inefficient.
The total rotational losses, including the core losses, can be subtracted from Pm to obtain the
mechanical power output Po that is available in mechanical form at the shaft for useful work,
Po = Pm − Prot = To ωm (13.2.7)
The per-unit efficiency of the induction motor is then given by
η = Po /Pi (13.2.8)
Let us now illustrate this procedure and the analysis of the equivalent circuit in the following
example.
Power transferred Mechanical power

across air gap Pg developed Pm
Electric = rotor input power = Pg(1 − S) Mechanical power
power input Pi = m1(I'2)2R'2/S = Tωm output Po
= m1V1I1 cos φ1 = m1E1I'2 cos φ2 1−S
= m1(I'2)2R'2 = Pm − Prot = Toωm
= Tωs S
Stator copper loss Rotor copper loss Rotational losses

= m1I 21R1 = m1(I'2)2R'2 (core losses will be
= SPg included here) Prot
Figure 13.2.7 Power flow in an induction motor.
EXAMPLE 13.2.1
The parameters of the equivalent circuit shown in Figure 13.2.6 for a three-phase, wye-connected,
220-V, 10-hp, 60-Hz, six-pole induction motor are given in ohms per phase referred to the stator:
R1 = 0.3, R2 = 0.15, Xl1 = 0.5, X12
= 0.2, and Xm = 15. The total friction, windage, and core
losses can be assumed to be constant at 400 W, independent of load. For a per-unit slip of 0.02,
when the motor is operated at rated voltage and frequency, calculate the stator input current, the
power factor at the stator terminals, the rotor speed, output power, output torque, and efficiency.
Solution
From the equivalent circuit of Figure 13.2.6, the total impedance per phase, as viewed from the
stator input terminals, is given by
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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R2
j Xm + j Xl2
S j 15(7.5 + j 0.2)
Zt = R1 + j Xl1 + = 0.3 + j 0.5 +
R2 7.5 + j (15 + 0.2)
+ j (XM + Xl2 )
S
= (0.3 + j 0.5) + (5.87 + j 3.10) = 6.17 + j 3.60
= 7.14 30.26° -
√
Phase voltage = 220/ 3 = 127 V
Stator input current = 127/7.14 = 17.79 A
Power factor = cos 30.26° = 0.864
Synchronous speed = 120 × 60/6 = 1200 r/min
Rotor speed = (1 − 0.02)1200
√ = 1176 r/min
Total input power = 3 × 220 × 17.79 × 0.864 = 5856.8 W
Stator copper loss = 3 × 17.792 × 0.3 = 284.8 W
Power transferred across air gap Pg = 5856.8 − 284.8 = 5572 W
Pg can also be obtained as follows:
Pg = m1 (I2 )2 R2 /S = m1 I12 Rf
where Rf is the real part of the parallel combination of jXm and R2 /S + j Xl2

. Thus,
Pg = 3 × 17.792 × 5.87 = 5573 W
Internal mechanical power developed = Pg (1 − S) = 0.98 × 5572 = 5460 W
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Total mechanical power output = 5460 − 400 = 5060 W, or 5060/745.7 = 6.8 hp
output power output power
Total output torque = ωm
= (1−S)ωs
Since,
4πf 4π × 60
ωs = = = 40π = 125.7 mechanical rad/s
poles 6
it follows that
5060
Total output torque = = 41.08 N · m
0.98 × 125.7
5060
Efficiency = = 0.864, or 86.4%
5856.8
The efficiency may alternatively be calculated from the losses:
Total stator copper loss = 284.8 W
Rotor copper loss = m1 (I2 )2 R2 = SPg = 0.02 × 5572 = 111.4 W
Friction, windage, and core losses = 400 W
Total losses = 284.8 + 111.4 + 400 = 796.2 W
Output = 5060 W
Input = 5060 + 796.2 = 5856.2 W
losses 796.2
Efficiency = 1 − =1− = 1 − 0.136 = 0.864, or 86.4%
input 5856.2
Torque-Speed Characteristics of 3-Phase Induction Motors

Because the torque–slip characteristic is one of the most important aspects of the induction motor,
we will now develop an expression for torque as a function of slip and other equivalent circuit
parameters. Recalling Equation (13.2.8) and the equivalent circuit of Figure 13.2.6, we will obtain
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an expression for I2 . To that end, let us redraw the equivalent circuit in Figure 13.2.8. By applying
Thévenin’s theorem, we have the following from Figures 13.2.6 and 13.2.8:
j Xm
V̄1a = V̄1 − I¯0 (R1 − j Xl1 ) = V̄1 (13.2.9)
R1 + j (Xl1 + Xm )
(R1 + j Xl1 )j Xm
R1 + j X1 = (13.2.10)
R1 + j (Xl1 + Xm )
V1a
I2 = (13.2.11)
[R1 + (R2 /S)]2 + (X1 + Xl2 2
)
1 2
m1 V1a (R2 /S)
T = (13.2.12)
ωs [R1 + (R2 /S)]2 + (X1 + Xl2
2
)
Neglecting the stator resistance in Equation (13.2.9) results in negligible error for most induction
motors. If Xm of the equivalent circuit shown in Figure 13.2.6 is sufficiently large that the shunt
branch need not be considered, calculations become much simpler; R1 and X1 are then equal to
R1 and X l1, respectively; also, V 1a is then equal to V 1.
The general shape of the torque–speed or torque–slip characteristic is shown in Figure 13.1.6,
in which the motor region (0 < S ≤ 1), the generator region (S < 0), and the breaking region (S
> 1) are included for completeness. The performance of an induction motor can be characterized
by such factors as efficiency, power factor, starting torque, starting current, pull-out (maximum)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
torque, and maximum internal power developed. Starting conditions are those corresponding to
S = 1.
The maximum internal (or breakdown) torque T max occurs when the power delivered to R2 /S
in Figure 13.2.8 is a maximum. Applying the familiar impedance-matching principle of circuit
theory, this power will be a maximum when the impedance R2 /S equals the magnitude of the
impedance between that and the constant voltage V 1a. That is to say, the maximum occurs at a
value of slip Smax T for which the following condition is satisfied:
R2
= (R1 )2 + (X1 + Xl2 2
) (13.2.13)
Smax T
The same result can also be obtained by differentiating Equation (13.2.12) with respect to S, or,
more conveniently, with respect to R2 /S, and setting the result equal to zero. This calculation has
been left to the enterprising student. The slip corresponding to maximum torque Smax T is thus
given by
R2
Smax T = (13.2.14)
(R1 )2 + (X1 + Xl2
2
)
and the corresponding maximum torque from Equation (13.2.12) results in
jX''1 jX 'l2 Figure 13.2.8 Another form of per-

I'2 R''1 R'2 I'2
phase equivalent circuit for the
+ polyphase induction motor of Fig-
ure 13.2.6.
R'2 (1 − S)
V1a S
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2
1 0.5m1 V1a
Tmax = (13.2.15)
2
ωs R1 + (R1 )2 + (X1 + Xl2 )
which can be verified by the reader. Equation (13.2.15) shows that the maximum torque is
independent of the rotor resistance. The slip corresponding to the maximum torque is directly
proportional to the rotor resistance R2 , however, as seen from Equation (13.2.14). Thus, when
the rotor resistance is increased by inserting external resistance in the rotor of a wound-rotor
induction motor, the maximum internal torque is unaffected, but the speed or slip at which
it occurs is increased, as shown in Figure 13.2.9. Also note that maximum torque and max-
imum power do not occur at the same speed. The student is encouraged to work out the
reason.
A conventional induction motor with a squirrel-cage rotor has about 5% drop in speed from
no load to full load, and is thus essentially a constant-speed motor. Employing a wound-rotor
motor and inserting external resistance in the rotor circuit achieves speed variation but results
in poor efficiency. Variations in the starting torque (at S = 1) with rotor-circuit resistance can
also be seen from Figure 13.2.9. As stated in Section 13.1, we can obtain a higher starting torque
by inserting external resistances in the rotor circuit and then cutting them out eventually for
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
the normal running conditions in order to operate the machine at a higher efficiency. Creating
a sufficiently large rotor-circuit resistance might make it possible to achieve an almost linear
torque–slip relationship for the slip range of 0 to 1. For instance, two-phase servo motors
(used as output actuators in feedback control systems) are usually designed with very high rotor
resistance to ensure a negative slope for the torque–speed characteristic over the entire operating
range.
Since the stator resistance is quite low and has only a negligible influence, let us set
R1 = R1 = 0, in which case, from Equations (13.2.12) and (13.2.15), we can show that
T 2
= (13.2.16)
Tmax (S/Smax T ) + (Smax T /S)
where S and Smax T are the slips corresponding to T and T max, respectively.
T/Tfull load Stable operating Figure 13.2.9 Effect of changing

region for motor rotor-circuit resistance on the torque–
with resistance (R'2)A slip characteristic of a polyphase in-
3.0 duction motor.
Tmax
2.5
(R'2)C (R'2)A
2.0 (R'2)B
(R'2)D
1.5 Load
NB
NC NA
1.0
(R'2)D > (R'2)C > (R'2)B > (R'2)A
0.5 ND
0
1.0 0.8 0.6 0.4 0.2 0 Slip
0 0.2 0.4 0.6 0.8 1.0 Speed

Synchronous speed
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EXAMPLE 13.2.2
For the motor specified in Example 13.2.1, compute the following:
(a) The load component I2 of the stator current, the internal torque T, and the internal power
Pm for a slip of 0.02.
(b) The maximum internal torque, and the corresponding slip and speed.
(c) The internal starting torque and the corresponding stator load current I2 .
Solution
Let us first reduce the equivalent circuit of Figure 13.2.6 to its Thévenin-equivalent form shown
in Figure 13.2.8. With the aid of Equations (13.2.9) and (13.2.10), we obtain
j Xm ∼ Xm 220 15
V̄1a = V̄1 = V̄1 = √ 0° = 122.9 0° V
R1 + j (Xl1 + Xm ) Xl1 + Xm 3 0.5 + 15
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(0.3 + j 0.5)j 15
R1 + j X1 = = 0.281 + j 0.489
0.3 + j (0.5 + 15)
(a) Corresponding to a slip of 0.02, R2 /S = 0.15/0.02 = 7.5. From Equation (13.2.11), we
get
122.9 122.9
I2 = √ = = 15.7 A
7.8 + 0.689
2 2 7.83
The internal torque T can be calculated from either Equation (13.2.5) or (13.2.12),
1 5546
T = 3 × 15.72 × 7.5 = = 44.12 N · m
125.7 125.7
From Equation (13.2.6), the internal mechanical power is calculated as
Pm = 3 × 15.72 × 7.5 × 0.98 = 5435 W
which is also the same as T ωm = T ωs (1−S) = 44.12×125.7×0.98. In Example 13.2.1,

this value is calculated as 5460 W; the small discrepancy is due to the approximations.
(b) From Equation (13.2.14) it follows that
0.15 0.15
Smax T =√ = = 0.202
0.2812 + 0.6892 0.744
or the corresponding speed at T max is (1 − 0.202)1200 = 958 r/min. From Equation

(13.2.15), the maximum torque can be calculated as
1 0.5 × 3 × 122.92 1 0.5 × 3 × 122.92
Tmax = √ = = 175.8 N · m
125.7 0.281 + 0.2812 + 0.6892 125.7 0.281 + 0.744
(c) Assuming the rotor-circuit resistance to be constant, with S = 1 at starting, from Equations
(13.2.11) and (13.2.12) we get
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122.9 122.9
I2 start = = = 151.2 A
(0.281 + 0.15)2 + (0.489 + 0.2)2 0.813
1
Tstart = 3 × 151.22 × 0.15 = 81.8 N · m
125.7
For such applications as fans and blowers, a motor needs to develop only a moderate starting
torque. Some loads, like conveyors, however, require a high starting torque to overcome high
static torque and load inertia. The motor designer sometimes makes the starting torque equal to
the maximum torque by choosing the rotor-circuit resistance at startup to be

R2 start = (R1 )2 + (X1 + Xl2
2
) (13.2.17)
which can easily be obtained from Equation (13.2.13) with Smax T = 1.
Speed and Torque Control of Polyphase Induction Motors

The induction motor is valuable in so many applications because it combines simplicity and
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
ruggedness. Although a good number of industrial drives run at substantially constant speed,
quite a few applications need variable speed. Speed-control capability is essential in such
applications as conveyors, hoists, and elevators. Because the induction motor is essentially a
constant-speed machine, designers have sought creative ways to easily and efficiently vary its
speed continuously over a wide range of operating conditions. We only indicate the methods of
speed control here.
The appropriate equation to be examined, based on Equation (13.1.8), is
n = (1 − S)n1 = (1 − S)120fs /P (13.2.18)
where n is the actual speed of the machine in revolutions per minute, S is the per-unit slip, fs
is the supply frequency in hertz, P is the number of poles, and n1 is the synchronous speed in
revolutions per minute. Equation (13.2.18) suggests that the speed of the induction motor can
be varied by varying either the slip or the synchronous speed, which in turn can be varied by
changing either the number of poles or the supply frequency. Any method of speed control that
depends on the variation of slip is inherently inefficient because the efficiency of the induction
motor is approximately equal to 1 − S. On the other hand, if the supply frequency is constant,
varying the number of poles results only in discrete and stepped variation in motor speed.
Indeed, all methods of speed control require some degree of sacrifice in performance, cost,
and simplicity. These disadvantages must be weighed carefully against the advantages of speed
variability.
The following are methods available for speed and torque control of induction motors.
• Pole-changing method
• Variable-frequency method
• Variable-line-voltage method
• Variable-rotor-resistance method
• Rotor-slip frequency control
• Rotor-slip energy recovery method
• Control by auxiliary devices (Kramer control, Scherbius control, Schrage motor)
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• Solid-state control (variable-terminal-voltage control, variable-frequency control, rotor-
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
resistance control for wound-rotor motors, injecting voltage into rotor circuit of wound-rotor
motors) usually discussed under power-semiconductor controlled drives (see Section 16.1).
Figure 13.2.10 lists various ac motors as well as techniques for their speed and torque control.
Starting Methods for Polyphase Induction Motors

When high starting torques are required, a wound-rotor induction motor, with external resistances
inserted in its rotor circuits, can be used. The starting current can be reduced and high values of
starting torque per ampere of starting current can be obtained with rotor-resistance starting. The
external resistances are generally cut out in steps as the machine runs up to speed.
Induction Synchronous
motors motors
Wound Squirrel Salient

Hysteresis Reluctance
rotor cage pole
In-line Multispeed
control winding
(stator) control
Adjustable Adjustable
voltage frequency
Voltage Synchronous
regulator generator
Induction
Impedance
generator
Electronic Electronic
magnetic SCR-commutator
SCR motor
Figure 13.2.10 Ac motors and techniques for their speed and torque control.
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For squirrel-cage-rotor machines, the problem is to keep down the starting current while
maintaining adequate starting torque. The input current, for example, can be no more than 6 times
the full-load current, while the starting torque may be about 1.5 times the full-load torque. Depend-
ing on the capacity of the available supply system, direct-on-line starting may be suitable only
for relatively small machines, up to 10-hp rating. Other starting methods include reduced-voltage
starting by means of wye–delta starting, autotransformer starting, or stator-impedance starting.
For employing the wye–delta starting method, a machine designed for delta operation is
connected in wye during the starting period. Because the impedance between line terminals for
wye connection is three times that for delta connection for the same line voltage, the line current
at standstill for wye connection is reduced√ to one-third of the value for delta connection. Since the
phase voltage is reduced by a factor of 3 during starting, it follows that the starting torque will
be one-third of normal. For autotransformer starting, the setting of the autotransformer can be
predetermined to limit the starting current to any desired value. An autotransformer, which reduces
the voltage applied to the motor to x times the normal voltage, will reduce the starting current in
the supply system as well as the starting torque of the motor to x 2 times the normal values.
Stator-impedance starting may be employed if the starting-torque requirement is not severe.
Series resistances (or impedances) are inserted in the lines to limit the starting current. These
resistances are short-circuited out when the motor gains speed. This method has the obvious
disadvantage of inefficiency caused by the extra losses in the external resistances.
EXAMPLE 13.2.3
An induction motor has a starting current that is 6 times the full-load current and a per-unit full-
load slip of 0.04. The machine is to be provided with an autotransformer starter. If the minimum
starting torque must be 0.3 times the full-load torque, determine the required tapping on the
transformer and the per-unit supply-source line current at starting.
Solution
From Equation (13.2.5), with slip at starting equal to 1, we have

2
Ts Is
= Sf l
Tf l If l
where subscripts s and fl correspond to starting and full-load conditions.
Substituting values, 0.3 = (Is /If l )2 × 0.04, from which

Is /If l = 0.03/0.04 = 2.74
or Is = 2.74 per unit, with Ifl taken as 1 per unit.
The applied voltage to the motor must reduce the current from 6 per unit to 2.74 per unit,
i.e., the tapping must be sufficient to reduce the voltage to 2.74/6 = 0.456 of the full value.
The supply-source line current will then be 2.74 × 0.456 = 1.25 per unit, where 0.456 is the
secondary-to-primary turns ratio.
Single-Phase Induction Motors

For reasons of simplicity and cost, a single-phase power supply is universally preferred for
fractional-horsepower motors. It is also used widely for motors up to about 5 hp. Single-phase
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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induction motors are usually two-pole or four-pole, rated at 2 hp or less, while slower and larger
motors can be manufactured for special purposes. Single-phase induction motors are widely used
in domestic appliances and for a very large number of low-power drives in industry. The single-
phase induction machine resembles a small, three-phase, squirrel-cage motor, except that at full
speed only a single winding on the stator is usually excited.
The single-phase stator winding is distributed in slots so as to produce an approximately
sinusoidal space distribution of mmf. As discussed in Section 13.1, such a motor inherently has
no starting torque, and as we saw in Section 12.3, it must be started by an auxiliary winding, by
being displaced in phase position from the main winding, or by some similar device. Once started
by auxiliary means, the motor will continue to run. Thus, nearly all single-phase induction motors
are actually two-phase motors, with the main winding in the direct axis adapted to carry most or
all of the current in operation, and an auxiliary winding in the quadrature axis with a different
number of turns adapted to provide the necessary starting torque.
Since the power input in a single-phase circuit pulsates at twice the line frequency, all single-
phase motors have a double-frequency torque component, which causes slight oscillations in rotor
speed and imparts vibration to the motor supports. The design must provide a means to prevent
this vibration from causing objectionable noise.
The viewpoint adopted in explaining the operation of the single-phase motor, based on
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
the conditions already established for polyphase motors, is known as the revolving-field theory.
(The other viewpoint, cross-field theory, is not presented here.) For computational purposes, the
revolving-field point of view, already introduced in Section 13.1, is followed hereafter to parallel
the analysis we applied to the polyphase induction motor. As stated in Section 13.1 and shown
in Section 12.3, a stationary pulsating field can be represented by two counterrotating fields of
constant magnitude. The equivalent circuit of a single-phase induction motor, then, consists of
the series connection of a forward rotating field equivalent circuit and a backward rotating one.
Each circuit is similar to that of a three-phase machine, but in the backward rotating field circuit,
the parameter S is replaced by 2 − S, as shown in Figure 13.2.11(a). The forward and backward
torques are calculated from the two parts of the equivalent circuit, and the total torque is given by
the albegraic sum of the two. As shown in Figure 13.2.11(b), the torque–speed characteristic of
a single-phase induction motor is thus obtained as the sum of the two curves, one corresponding
to the forward rotating field and the other to the backward rotating field.
The slip Sf of the rotor with respect to the forward rotating field is given by
ns − n n
Sf = S = =1− (13.2.19)
ns ns
where ns is the synchronous speed and n is the actual rotor speed. The slip Sb of the rotor with
respect to the backward rotating field is given by
ns − (−n) n
Sb = =1+ =2−S (13.2.20)
ns ns
Since the amplitude of the rotating fields is one-half of the alternating flux, as seen from Equation
(12.3.10), the total magnetizing and leakage reactances of the motor can be divided equally so
as to correspond to the forward and backward rotating fields. In the equivalent circuit shown in
Figure 13.2.11(a), then, R1 and X l1 are, respectively, the resistance and the leakage reactance of
the main winding, Xm is the magnetizing reactance, and R2 and Xl2
are the standstill values of
the rotor resistance and the leakage reactance referred to the main stator winding by the use
of the appropriate turns ratio. The core loss, which is omitted here, can be accounted for later
as if it were a rotational loss. The resultant torque of a single-phase induction motor can thus be
expressed as
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If2 (1 − S)
Ib2 (1 − S)
Te = R2 −
R (13.2.21)
ωm S ωm (2 − S) 2
The following example illustrates the usefulness of the equivalent circuit in evaluating the
motor performance.
I1 R1 jXl1 Figure 13.2.11 Single-phase in-

+ duction motor based on the
If revolving-field theory. (a) Equiva-
lent circuit. (b) Torque–speed char-
0.5R'2 acteristics.
S
Zf j0.5Xm
j0.5X'l2
V Ib
0.5R'2
2−S
Zb j0.5Xm
j0.5X'l2
−
(a)
Torque Torque due to

forward rotating field
Resultant torque
Speed
Torque due to backward rotating field
(b)
EXAMPLE 13.2.4
A 1/4-hp, 230-V, 60-Hz, four-pole, single-phase induction motor has the following parameters and

losses: R1 = 10 -, Xl1 = Xl2 = 12.5 -, R2 = 11.5 -, and Xm = 250 -. The core loss at 230 V
is 35 W and the friction and windage loss is 10 W. For a slip of 0.05, determine the stator current,
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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power factor, developed power, shaft output power, speed, torque, and efficiency when the motor
is running as a single-phase motor at rated voltage and frequency with its starting winding open.
Solution
From the given data applied to the equivalent circuit of Figure 13.2.11, we see that
0.5R2 11.5
= = 115 -
S 2 × 0.05
0.5R2 11.5
= = 2.95 -
2−S 2(2 − 0.05)
j 0.5Xm = j 125 -

j 0.5Xl2 = j 6.25 -
For the forward-field circuit, the impedance is
(115 + j 6.25)j 125
Zf = = 59 + j 57.65 = Rf + j Xf
115 + j 131.25
and for the backward-field circuit, the impedance is
(2.95 + j 6.25)j 125
Zb = = 2.67 + j 6.01 = Rb + j Xb
2.95 + j 131.25
The total series impedance Ze is then given by
Ze = Z1 + Zf + Zb = (10 + j 12.5) + (59 + j 57.65) + (2.67 + j 6.01)
= 71.67 + j 76.16 = 104.6 − 46.74°
The input stator current is
230
I¯1 = = 2.2 − 46.74° A
104.6 46.74°
also,
Power factor = cos 46.74° = 0.685 lagging,
Developed power Pd = I12 Rf (1 − S) + I12 Rb [1 − (2 − S)] = I12 (Rf − Rb )(1 − S) =
2.22 (59 − 2.67)(1 − 0.05) = 259 W
Shaft-output power Po = Pd − Prot − Pcore = 259 − 10 − 35 = 214 W, or 0.287 hp
Speed = (1 − S) synchronous speed = 0.95 × 120 × 60/4 = 1710 r/min, or 179 rad/s
Torque = 214/179 = 1.2 N · m
output 214 214
Efficiency = = = = 0.6174, or 61.74%
input 230 × 2.2 × 0.685 346.6
Starting Methods for Single-Phase Induction Motors

The various forms of a single-phase induction motor are grouped into three principal types,
depending on how they are started.
1. Split-phase or resistance-split-phase motors: Split-phase motors have two stator windings
(a main winding and an auxiliary winding) with their axes displaced 90 electrical degrees in space.
As represented schematically in Figure 13.2.12(a), the auxiliary winding in this type of motor
has a higher resistance-to-reactance ratio than the main winding. The two currents are thus out
of phase, as indicated in the phasor diagram of Figure 13.2.12(b). The motor is equivalent to
an unbalanced two-phase motor. The rotating stator field produced by the unbalanced two-phase
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winding currents causes the motor to start. The auxiliary winding is disconnected by a centrifugal
switch or relay when the motor comes up to about 75% of the synchronous speed. The torque–speed
characteristic of the split-phase motor is of the form shown in Figure 13.2.12(c). A split-phase
motor can develop a higher starting torque if a series resistance is inserted in the starting auxiliary
winding. A similar effect can be obtained by inserting a series inductive reactance in the main
winding; this additional reactance is short-circuited when the motor builds up speed.
2. Capacitor motors: Capacitor motors have a capacitor in series with the auxiliary winding
and come in three varieties: capacitor start, two-value capacitor, and permanent-split capacitor.
As their names imply, the first two use a centrifugal switch or relay to open the circuit or reduce
the size of the starting capacitor when the motor comes up to speed. A two-value-capacitor motor,
with one value for starting and one for running, can be designed for optimum starting and running
performance; the starting capacitor is disconnected after the motor starts. The relevant schematic
diagrams and torque–speed characteristics are shown in Figures 13.2.13, 13.2.14, and 13.2.15.
Motors in which the auxiliary winding and the capacitor are not cut out during the normal running
conditions operate, in effect, as unbalanced two-phase induction motors.
3. Shaded-pole motors: The least expensive of the fractional-horsepower motors, generally
rated up to 1/20 hp, they have salient stator poles, with one-coil-per-pole main windings. The
auxiliary winding consists of one (or rarely two) short-circuited copper straps wound on a portion
of the pole and displaced from the center of each pole, as shown in Figure 13.2.16(a). The shaded-
I Cage rotor
+
Centrifugal switch
Main V
V winding Im Ia
−
Ia
Im
Auxiliary winding I
(a) (b)
Torque, per unit
Torque during starting due to main

4 and auxiliary windings
2
Switching
speed
Speed or slip
S=1 S=0
(zero speed) (synchronous speed)
Torque due to main winding only

(c)
Figure 13.2.12 Split-phase motor. (a) Schematic diagram. (b) Phasor diagram at starting. (c) Typical torque–
speed (or slip) characteristic.
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I
Ia
+
Centrifugal switch
Main V
V winding Im
C
− I
Ia
Auxiliary winding Im
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(a) (b)
Torque, per unit

Torque during starting due to
main and auxiliary windings
4
2
Switching
speed
Speed or slip
S=1 S=0
Torque due to main winding only

(c)
Figure 13.2.13 Capacitor-start motor. (a) Schematic diagram. (b) Phasor diagram at starting. (c) Typical
torque–speed characteristic.
pole motor got its name from these shading bands. Induced currents in the shading coil cause the
flux in the shaded portion of the pole to lag the flux in the other portion in time. The result is
then like a rotating field moving in the direction from the unshaded to the shaded portion of the
pole. A low starting torque is produced. A typical torque-speed characteristic is shown in Figure
13.2.16(b). Shaded-pole motors have a rather low efficiency.
Applications for Induction Motors

Before specifying a particular motor for a given application, the designer must know the load
characteristics, such as horsepower requirement, starting torque, acceleration capability, speed
variation, duty cycle, and the environment in which the motor is to operate. Typical speed–torque
curves for squirrel-cage induction motors with NEMA design classification A, B, C, and D are
shown in Figure 13.2.17. Having selected the appropriate motor for a given application, the next
step is to specify a controller for the motor to furnish proper starting, stopping, and reversing
without damaging the motor, other connected loads, or the power system. The ranges of standard
power ratings given by NEMA for single-phase motors are listed in Table 13.2.1. Two-phase
induction motors with high rotor resistance are employed as servomotors for control-system
applications that usually require positive damping over the full speed range.
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Torque, per unit
+ 2
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Main
winding 1
− Speed
S=1 S=0 or slip
Auxiliary winding (zero speed) (synchronous speed)
(a) (b)
Figure 13.2.14 Permanent-split-capacitor motor. (a) Schematic diagram. (b) Typical torque–speed
characteristic.
Torque, per unit

Starting capacitor
+ Centrifugal
switch 2
Switching
Main
speed
winding 1
− Running capacitor Speed
or slip
Auxiliary winding S=1 S=0
(a) (b)
Figure 13.2.15 Two-value-capacitor motor. (a) Schematic diagram. (b) Typical torque–speed characteristic.
Torque, per unit
Cage rotor 2
Shading band 1
or coil Speed
S=1 S=0 or slip
(a) (b)
Figure 13.2.16 Shaded-pole motor. (a) Schematic diagram. (b) Typical torque–speed characteristic.
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TABLE 13.2.1 Ranges of Standard Power Ratings for Single-Phase Induction Motors
Motor Power Range
Capacitor start 1 mhp to 10 hp

Resistance start 1 mhp to 10 hp
Two-value capacitor 1 mhp to 10 hp
Permanent-split capacitor 1 mhp to 1.5 hp
Shaded pole 1 mhp to 1.5 hp
Source: NEMA Standards Publication MG 1, Motors and Generators, New York, 1987.
Figure 13.2.17 Typical speed–torque curves for

squirrel-cage induction motors with NEMA design
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
300 classifications A, B, C, and D. (Adapted from NEMA

Standards Publication MG 10, Energy Management
Guide for Selection and Use of Polyphase Motors,
D New York, 1988.)
Torque, % full-load torque
200
A or B
100
0 20 40 60 80 100
Speed, % synchronous speed
13.3 SYNCHRONOUS MACHINES

Large ac power networks operating at a constant frequency of 60 Hz in the United States (50 Hz
in Europe) rely almost exclusively on synchronous generators to generate electric energy. They
can also have synchronous compensators or condensers at key points for reactive power control.
Generators are the largest single-unit electric machines in production, having power ratings in
the range of 1500 MVA, and we can expect machines of several thousand MVA to come into
use in future decades. Private, standby, and peak-load plants with diesel or gas-turbine prime
movers also have alternators. Non-land-based synchronous plants can be found on oil rigs, on
large aircraft with hydraulically driven alternators operating at 400 Hz, and on ships for variable
frequency supply to synchronous propeller motors. Synchronous motors provide constant speed
industrial drives with the possibility of power factor correction, although they are not often built
in small ratings, for which the induction motor is cheaper.
This section develops analytical methods of examining the steady-state performance of
synchronous machines. We first consider cylindrical-rotor machines and discuss the effects of
salient poles subsequently.
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13.3 SYNCHRONOUS MACHINES 583
Equivalent Circuit of a Synchronous Machine

A review of the material about elementary synchronous machines presented in Section 13.1 is
very helpful at this stage to recall the principles of operation for synchronous machines.
To investigate the equivalent circuit of a synchronous machine, for the sake of simplicity, let
us begin by considering an unsaturated cylindrical-rotor synchronous machine. Effects of saliency
and magnetic saturation can be considered later. Since for the present we are only concerned with
the steady-state behavior of the machine, circuit parameters of the field and damper windings need
not be considered. The effect of the field winding, however, is taken care of by the flux produced
by the dc field excitation and the ac voltage generated by the field flux in the armature circuit.
Thus, let Ēf be the ac voltage, known as excitation voltage, generated by the field flux. As for
the armature winding, under balanced conditions of operation we will analyze it on a per-phase
basis. The armature winding obviously has a resistance Ra and a leakage reactance Xl of the
armature per phase.
The armature current I¯a produces the armature reaction flux, the effect of which can be
represented by an inductive reactance Xφ , known as magnetizing reactance or armature reaction
reactance. Thus Figure 13.3.1 shows the equivalent circuits in phasor notation, with all per-phase
quantities, for a cylindrical-rotor synchronous machine working as either a generator or a motor.
The sum of the armature leakage reactance and the armature reaction reactance is known as the
synchronous reactance,
Xs = Xφ + Xl (13.3.1)
and Ra + j Xs is called the synchronous impedance Zs. Thus, the equivalent circuit for an
unsaturated cylindrical-rotor synchronous machine under balanced polyphase conditions reduces
to that shown in Figure 13.3.1(b), in which the machine is represented on a per-phase basis by
its excitation voltage Ēf in series with the synchronous impedance. Note that V̄t is the terminal
per-phase rms voltage, usually taken as reference.
In all but small machines, the armature resistance is usually neglected except for its effect on
losses (and hence the efficiency) and heating. With this simplification, Figure 13.3.2 shows the
four possible cases of operation of a round-rotor synchronous machine, in which the following
relation holds:
V̄t + j I¯a Xs = Ēf (13.3.2)
Observe that the motor armature current is taken in the direction opposite to that of the generator.
The machine is said to be overexcited when the magnitude of the excitation voltage exceeds
that of the terminal voltage; otherwise it is said to be underexcited. The angle δ between the
excitation voltage Ēf and the terminal voltage V̄t is known as the torque angle or power angle of
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Ia Motor Ia Motor
jXφ jXl Ra jXs = j(Xφ + XI) Ra
+ +
+
+ + Ia
Ef −Er Ia Vt Ef Generator Vt
Generator
− −
−
− −
(a) (b)
Figure 13.3.1 Per-phase equivalent circuits of a cylindrical-rotor synchronous machine.
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Ef
jIa Xs Ia
δ
jIa Xs
Vt Ef
φ
φ δ
Ia Vt
(a) (b)
Ia
−Ia
Vt
φ
Vt φ δ
δ Ef jIa Xs
jIa Xs
Ia Ef −Ia
(c) (d )
Figure 13.3.2 Four possible cases of operation of a round-rotor synchronous machine with negligible armature
resistance. (a) Overexcited generator (power factor lagging), P > 0, Q > 0, δ > 0. (b) Underexcited
generator (power factor leading), P > 0, Q < 0, δ > 0. (c) Overexcited motor (power factor leading),
P < 0, Q > 0, δ < 0. (d) Underexcited motor (power factor lagging), P < 0, Q < 0, δ < 0.
the synchronous machine. The power-angle performance characteristics are discussed later in this
section. The dc excitation can be provided by a self-excited dc generator, known as the exciter,
mounted on the same shaft as the rotor of the synchronous machine.
The voltage regulation of a synchronous generator at a given load, power factor, and rated
speed is defined as
Ef − Vt
% voltage regulation = × 100 (13.3.3)
Vt
where Vt is the terminal voltage on the load, and Ef is the no-load terminal voltage at rated speed
when the load is removed without changing the field current.
EXAMPLE 13.3.1
The per-phase synchronous reactance of a three-phase, wye-connected, 2.5-MVA, 6.6-kV, 60-Hz
turboalternator is 10 -. Neglect the armature resistance and saturation. Calculate the voltage
regulation when the generator is operating at full load with (a) 0.8 power factor lagging, and (b)
0.8 power factor leading.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Solution
6.6 × 1000
Per-phase terminal voltage Vt = √ = 3811 V
3
2.5 × 106
Full-load per-phase armature current Ia = √ = 218.7 A
3 × 6.6 × 1000
(a) Referring to Figure 13.3.2(a) for an overexcited generator operating at 0.8 power factor
lagging, and applying Equation (13.3.2), we have
Ēf = 3811 + j 218.7(0.8 − j 0.6)(10) = 5414 tan−1 0.3415

5414 − 3811
% voltage regulation = × 100 = 0.042 × 100 = 4.2%
3811
(b) Referring to Figure 13.3.2(b) for an underexcited generator operating at 0.8 power factor
leading, and applying Equation (13.3.2), we have
Ēf = 3811 + j 218.7(0.8 + j 0.6)(10) = 3050 tan−1 0.7

3050 − 3811
% voltage regulation = × 100 = −0.2 × 100 = −20%
3811
As we have just seen, the voltage regulation for a synchronous generator can become
negative.
Power Angle and Other Performance Characteristics

The real and reactive power delivered by a synchronous generator, or received by a synchronous
motor, can be expressed in terms of the terminal voltage Vt, the generated voltage Ef, the
synchronous impedance Zs, and the power angle or torque angle δ. Referring to Figure 13.3.2,
it is convenient to adopt a convention that makes positive the real power P and the reactive
power Q delivered by an overexcited generator. Accordingly, the generator action corresponds
to positive values of δ, whereas the motor action corresponds to negative values of δ. With
the adopted notation it follows that P > 0 for generator operation, whereas P < 0 for motor
operation. Further, positive Q means delivering inductive VARs for a generator action, or receiving
inductive VARs for a motor action; negative Q means delivering capacitive VARs for a generator
action, or receiving capacitive VARs for a motor action. It can be observed from Figure 13.3.2
that the power factor is lagging when P and Q have the same sign, and leading when P and Q
have opposite signs.
The complex power output of the generator in volt-amperes per phase is given by
S̄ = P + j Q = V̄t I¯a∗ (13.3.4)
¯ *
where V̄t is the terminal voltage per phase, Ia is the armature current per phase, and indicates a
complex conjugate. Referring to Figure 13.3.2(a), in which the effect of armature resistance has
been neglected, and taking the terminal voltage as reference, we have the terminal voltage,
V̄t = Vt + j 0 (13.3.5)
the excitation voltage or generated voltage,
Ēf = Ef (cos δ + j sin δ) (13.3.6)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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and the armature current,

Ēf − V̄t Ef cos δ − Vt + j Ef sin δ
I¯a = = (13.3.7)
j Xs j Xs
where Xs is the synchronous reactance per phase. Since
Ef cos δ − Vt − j Ef sin δ Ef sin δ Ef cos δ − Vt
I¯a∗ = = +j (13.3.8)
−j Xs Xs Xs
therefore,
Vt Ef sin δ
P = (13.3.9)
Xs
and
Vt Ef cos δ − Vt2
Q= (13.3.10)
Xs
Equations (13.3.9) and (13.3.10) hold for a cylindrical-rotor synchronous generator with negligible
armature resistance. To obtain the total power for a three-phase generator, Equations (13.3.9) and
(13.3.10) should be multiplied by 3 when the voltages are line to neutral. If the line-to-line
magnitudes are used for the voltages, however, these equations give the total three-phase power.
The power-angle or torque-angle characteristic of a cylindrical-rotor synchronous machine
is shown in Figure 13.3.3, neglecting the effect of armature resistance. The maximum real power
output per phase of the generator for a given terminal voltage and a given excitation voltage is
Vt Ef
Pmax = (13.3.11)
Xs
Any further increase in the prime-mover input to the generator causes the real power output to
decrease. The excess power goes into accelerating the generator, thereby increasing its speed
and causing it to pull out of synchronism. Hence, the steady-state stability limit is reached when
δ = π/2. For normal steady operating conditions, the power angle or torque angle is well below
90°. The maximum torque or pull-out torque per phase that a round-rotor synchronous motor can
develop for a gradually applied load is
Real power or torque Figure 13.3.3 Steady-state power-angle

or torque-angle characteristic of a cylin-
drical-rotor synchronous machine (with
Pull-out torque
as a generator negligible armature resistance).
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Generator
−π
−δ −π/2 0 π/2 π δ
Motor
Pull-out torque
as a motor
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Pmax Pmax
Tmax = = (13.3.12)
ωm 2π ns /60
where ns is the synchronous speed in r/min.
In the steady-state theory of the synchronous machine, with known terminal bus voltage Vt
and a given synchronous reactance Xs, the six operating variables are P, Q, δ, φ, Ia, and Ef. The
synchronous machine is said to have two degrees of freedom, because the selection of any two,
such as φ and Ia, P and Q, or δ and Ef, determines the operating point and establishes the other
four quantities.
The principal steady-state operating characteristics are the interrelations among terminal
voltage, field current, armature current, real power, reactive power, torque angle, power factor,
and efficiency. These characteristics can be computed for application studies by means of phasor
diagrams, such as those shown in Figure 13.3.2, corresponding to various conditions of operation.
The efficiency of a synchronous generator at a specified power output and power factor is
determined by the ratio of the output to the input; the input power is given by adding the machine
losses to the power output. The efficiency is conventionally computed in accordance with a set
of rules agreed upon by ANSI. Six losses are included in the computation:
• Armature winding copper loss for all phases, calculated after correcting the dc resistance
of each phase for an appropriate allowable temperature rise, depending on the class of
insulation used.
• Field copper loss, based on the field current and measured field-winding dc resistance,
corrected for temperature in the same way armature resistance is corrected. Note that the
losses in the field rheostats that are used to adjust the generated voltage are not charged to
the synchronous machine.
• Core loss, which is read from the open-circuit core-loss curve at a voltage equal to the
internal voltage behind the resistance of the machine.
• Friction and windage loss.
• Stray-load losses, which account for the fact that the effective ac resistance of the armature
is greater than the dc resistance because of the skin effect, and for the losses caused by the
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
armature leakage flux.

• Exciter loss, but only if the exciter is an integral component of the alternator, i.e., shares a
common shaft or is permanently coupled. Losses from a nonintegral exciter are not charged
to the alternator.
EXAMPLE 13.3.2
A 1000-hp, 2300-V, wye-connected, three-phase, 60-Hz, 20-pole synchronous motor, for which
cylindrical-rotor theory can be used and all losses can be neglected, has a synchronous reactance
of 5.00 -/phase.
(a) The motor is operated from an infinite bus supplying rated voltage and rated frequency,
and its field excitation is adjusted so that the power factor is unity when the shaft load
is such as to require an input of 750 kW. Compute the maximum torque that the motor
can deliver, given that the shaft load is increased slowly with the field excitation held
constant.
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(b) Instead of an infinite bus as in part (a), let the power to the motor be supplied by a
1000-kVA, 2300-V, wye-connected, three-phase, 60-Hz synchronous generator whose
synchronous reactance is also 5.00 -/phase. The generator is driven at rated speed, and the
field excitations of the generator and motor are adjusted so that the motor absorbs 750 kW
at unity power factor and rated terminal voltage. If the field excitations of both machines
are then held constant, and the mechanical load on the synchronous motor is gradually
increased, compute the maximum motor torque under the conditions. Also determine the
armature current, terminal voltage, and power factor at the terminals corresponding to
this maximum load.
(c) Calculate the maximum motor torque if, instead of remaining constant as in part (b), the
field currents of the generator and motor are gradually increased so as to always maintain
rated terminal voltage and unity power factor while the shaft load is increased.
Solution
The solution neglects reluctance torque because cylindrical-rotor theory is applied.

(a) The equivalent circuit and the corresponding phasor diagram for the given conditions are
shown in Figure E13.3.2 (a), with the subscript m attached to the motor quantities,
2300
Rated voltage per phase Vt = √ = 1328 V line-to-neutral
3
750 × 103
Current per phase Iam = √ = 188.3 A
3 × 2300 × 1.0
Iam Xsm = 188.3 × 5 = 941.5 V
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
jXsm
Iam
+ Iam −Iam Vt
+
Vt Efm
jIam Xsm
−
− Efm
(a)
Efg
jXsg jXsm
Iag Iam
jIag Xsg
+
+ +
Iam Iag = −Iam
Efg Vt Efm
− − Vt
−
jIam Xsm
Efm
(b)
Figure E13.3.2
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Ef m = 13282 + 941.52 = 1628 V
Ef m Vt 1628 × 1328
Pmax = =
Xsm 5
= 432.4 kW per phase, or 1297.2 kW for three phases
120 × 60
Synchronous speed = = 360 r/min, or 6 r/s
20
ωs = 2π × 6 = 37.7 rad/s
1297.2 × 103
Tmax = = 34,408 N · m
37.7
(b) With the synchronous generator as the power source, the equivalent circuit and the
corresponding phasor diagram for the given conditions are shown in Figure E13.3.2(b),
with subscript g attached to the generator quantities,
Ef g = Ef m = 1628 V
Ef g Ef m 1628 × 1628
Pmax = =
Xsg + Xsm 10
= 265 kW per phase, or 795 kW for three phases
795 × 103
Tmax = = 21,088 N · m
37.7
If a load torque greater than this amount were applied to the motor shaft, synchronism
would be lost; the motor would stall, the generator would tend to overspeed, and the
circuit would be opened by circuit-breaker action.
Corresponding to the maximum load, the angle between Ēf g and Ēf m is 90°. From
the phasor diagram it follows that
Ef g 1628
Vt = √ = √ = 1151.3 V line-to-neutral, or 1994 V line-to-line
2 2
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
1151.3
Iag Xsg = 1151.3 or Iag = = 230 A
5
The power factor is unity at the terminals.
(c) Vt = 1328 V, and the angle between Ēf g and Ēf m is 90°. Hence it follows that
√
Efg = Ef m = 1328 2 = 1878 V
Efg Ef m 1878 × 1878
Pmax = = = 352.7 kW per phase, or 1058 kW for three phases
Xsg + Xsm 10
1058 × 103
Tmax = = 28,064 N · m
37.7
Effects of Saliency and Saturation

Because of saliency, the reactance measured at the terminals of a salient-pole synchronous machine
as opposed to a cylindrical-rotor machine (with uniform air gap) varies as a function of the rotor
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position. The effects of saliency are taken into account by the two-reactance theory, in which
the armature current I¯a is resolved into two components: Id in the direct or field axis, and Iq in
the quadrature or interpolar axis. Iq will be in the time phase with the excitation speed voltage
Ēf , whereas Id will be in time quadrature with Ēf . Direct- and quadrature-axis reactances (Xd
and Xq) are then introduced to model the machine in two axes. While this involved method of
analysis is not pursued here any further, the steady-state power-angle characteristic of a salient-
pole synchronous machine (with negligible armature resistance) is shown in Figure 13.3.4. The
resulting power has two terms: one due to field excitation and the other due to saliency. The
maximum torque that can be developed is somewhat greater because of the contribution due to
saliency.
Saturation factors and saturated reactances can be developed to account approximately for
saturation, or more involved field-plotting methods may be used if necessary. Such matters are
obviously outside the scope of this text.
Parallel Operation of Interconnected Synchronous Generators

In order to assure continuity of the power supply within prescribed limits of frequency and voltage
at all the load points scattered over the service area, it becomes necessary in any modern power
system to operate several alternators in parallel, interconnected by various transmission lines, in
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
a well-coordinated and optimized manner for the most economical operation. A generator can be
paralleled with an infinite bus (or with another generator running at rated voltage and frequency
supplying the load) by driving it at synchronous speed corresponding to the system frequency and
adjusting its field excitation so that its terminal voltage equals that of the bus. If the frequency of
the incoming machine is not exactly equal to that of the system, the phase relation between its
voltage and the bus voltage will vary at a frequency equal to the difference between the frequencies
of the machine and the bus voltages. In normal practice, this difference can usually be made quite
small, to a fraction of a hertz; in polyphase systems, it is essential that the same phase sequence be
P
Resultant power P
Power due to field excitation
Motor Vt Ef
sin δ
Xd
−δ +δ
−π −π/2 0 π/2 π
Power due to saliency

Vt 2 1
2 Xq Xd(−
1
sin 2δ)
Generator
−P
Figure 13.3.4 Steady-state power-angle characteristic of a salient-pole synchronous machine (with negli-
gible armature resistance).
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maintained on either side of the synchronizing switch. Thus, synchronizing requires the following
conditions of the incoming machine:
• Correct phase sequence
• Phase voltages in phase with those of the system
• Frequency almost exactly equal to that of the system
• Machine terminal voltage approximately equal to the system voltage
A synchroscope is used for indicating the appropriate moment for synchronization. After the
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
machine has been synchronized and is part of the system, it can be made to take its share of the
active and reactive power by appropriate adjustments of its prime-mover throttle and field rheostat.
The system frequency and the division of active power among the generators are controlled
by means of prime-mover throttles regulated by governors and automatic frequency regulators,
whereas the terminal voltage and the reactive volt-ampere division among the generators are
controlled by voltage regulators acting on the generator-field circuits and by transformers with
automatic tap-changing devices.
EXAMPLE 13.3.3
Two three-phase, 6.6-kV, wye-connected synchronous generators, operating in parallel, supply a
load of 3000 kW at 0.8 power factor lagging. The synchronous impedance per phase of machine A
is 0.5 + j 10 -, and of machine B it is 0.4 + j 12-. The excitation of machine A is adjusted so that
it delivers 150 A at a lagging power factor, and the governors are set such that the load is shared
equally between the two machines. Determine the armature current, power factor, excitation
voltage, and power angle of each machine.
Solution
One phase of each generator and one phase of the equivalent wye of the load are shown in Figure
E13.3.3(a). The load current I¯L is calculated as
3, 000
I¯L = √ − cos−1 0.8 = 328(0.8 − j 0.6) = 262.4 − j 196.8 A
3 × 6.6 × 0.8
For machine A,
1500
cos φA = √ = 0.875 lagging; φA = 29°; sin φA = 0.485
3 × 6.6 × 150
I¯A = 150(0.874 − j 0.485) = 131.1 − j 72.75 A
For machine B,
131.3
I¯B = I¯L − I¯A = 131.3 − j 124 = 180.6 − cos
180.6
131.3
cos φB = = 0.726 lagging
180.6
With the terminal voltage V̄r as reference, we have
√
Ēf A = V̄t + I¯A Z̄A = (6.6/ 3) + (131.1 − j 72.75)(0.5 + j 10) × 10−3
= 4.6 + j 1.27 kV per phase
Power angle δA = tan−1 (1.27/4.6) = 15.4°
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√ √
The line-to-line excitation voltage for machine A is 3 4.62 + 1272 = 8.26 kV.
√
Ēf B = V̄t + I¯B Z̄B = (6.6/ 3) + (131.1 − j 124)(0.4 + j 12) × 10−3
= 5.35 + j 1.52 kV per phase
Power angle δB = tan−1 (1.52/5.35) = 15.9°
√ √
The line-to-line excitation voltage for machine B is 3 5.352 + 1.522 = 9.6 kV.
The corresponding phasor diagram is sketched in Figure E13.3.3(b).
IL
IA IB +
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
ZA ZB Vt Load
+ +
EfA EfB
− −
−
(a)
EfB Figure E13.3.3
EfA IBZB
IAZA
δB
δA
φA Vt
φB
IA
IB
(b)
Steady-State Stability
The property of a power system that ensures that it will remain in equilibrium under both normal
and abnormal conditions is known as power-system stability. Steady-state stability is concerned
with slow and gradual changes, whereas transient stability is concerned with severe disturbances,
such as sudden changes in load or fault conditions. The largest possible flow of power through
a particular point, without loss of stability, is known as the steady-state stability limit when
the power is increased gradually, and as the transient-stability limit when a sudden disturbance
occurs.
For a generator connected to a system that is very large compared to its own size, the system
in Figure 13.3.5 can be used. The power-angle equation (neglecting resistances) for the system
under consideration becomes
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Bus Figure 13.3.5 Generator connected to an infinite bus.
Infinite bus
Generator Es ∠ δs
jXe
Eg ∠ δg
Eg Es
P =
sin δgs (13.3.13)
X
where δgs is the angular difference between δg and δs , and X = Xd + Xe , with Xd being the
direct-axis reactance of the synchronous generator. The power angle characteristic given by
Equation (13.3.13) is plotted in Figure 13.3.6. The peak of the power-angle curve, given by
Pmax, is known as the steady-state power limit (shown by point b in Figure 13.3.6), representing
the maximum power that can theoretically be transmitted in a stable manner. A machine is
usually operated at less than the power limit (such as at point a in Figure 13.3.6), thereby
leaving a steady-state margin, as otherwise even a slight increase in the angle δgs (such as at
point c in Figure 13.3.6) would lead to instability. Installing parallel transmission lines [which
effectively reduces X in Equation (13.3.13)] or adding series capacitors in lines raises the stability
limit.
Applications for Synchronous Motors

With constant-speed operation, power factor control, and high operating efficiency, three-phase
synchronous motors are employed in a wide range of applications. An overexcited synchronous
motor, known as a synchronous condenser, is used to improve the system power factor. Syn-
chronous motors are used as prime movers of dc generators and variable-frequency ac generators.
Typical applications include pumps, compressors, mills, mixers, and crushers.
Single-phase reluctance motors find application in such devices as clocks, electric shavers,
electric clippers, vibrators, sandpapering machines, and engraving tools. A hysteresis motor is
employed for driving high-quality record players and tape recorders, electric clocks, and other
timing devices. The horsepower range is up to 1 hp for hysteresis motors, and up to 100 hp for
reluctance motors.
P Figure 13.3.6 Power-angle curve of

Equation (13.3.13).
b
Pmax
a c
Generator
δgs
90°
Motor
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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13.4 DIRECT-CURRENT MACHINES

Generally speaking, conventional dc generators are becoming obsolete and increasingly often are
being replaced by solid-state rectifiers in most applications for which an ac supply is available.
The same is not true for dc motors. The torque–speed characteristics of dc motors are what makes
them extremely valuable in many industrial applications. The significant features of the dc drives
include adjustable motor speed over wide ranges, constant mechanical power output or torque,
rapid acceleration or deceleration, and responsiveness to feedback signals.
The dc commutator machines are built in a wide range of sizes, from small control devices
with a 1-W power rating up to the enormous motors of 10,000 hp or more used in rolling-mill
applications. The dc machines today are principally applied as industrial drive motors, particularly
when high degrees of flexibility in controlling speed and torque are required. Such motors are
used in steel and aluminum rolling mills, traction motors, overhead cranes, forklift trucks, electric
trains, and golf carts. Commutator machines are also used in portable tools supplied from batteries,
in automobiles as starter motors, in blower motors, and in control applications as actuators and
speed-sensing or position-sensing devices.
In this section, we examine the steady-state performance characteristics of dc machines to
help us understand their applications and limitations, illustrating the versatility of the dc machine.
Constructional Features of DC Machines

A dc generator or motor may have as many as four field windings, depending on the type and size of
the machine and the kind of service intended. These field windings consist of two normal exciting
fields, the shunt and series windings, and two fields that act in a corrective capacity to combat
the detrimental effects of armature reaction, called the commutating (compole or interpole) and
compensating windings, which are connected in series with the armature. The type of machine,
whether shunt, series, or compound, is determined solely by the normal exciting-field circuit
connections, as shown in Figure 13.1.8. Figure 13.4.1 illustrates how various field windings
are arranged with respect to one another in part of a cross section of a dc machine, whereas
Figure 13.4.2 shows the schematic connection diagram of a dc machine. The commutating and
compensating windings, their purpose, as well as the circuit connections are presented later in
this section.
Equivalent Circuit of a DC Machine

A review of the material presented with regard to elementary direct-current machines in Section
13.1 can be helpful at this stage to recall the principles of operation for dc machines.
The circuit representations of a dc generator and a dc motor are shown in Figure 13.4.3.
Under steady-state conditions the interrelationships between voltage and current are given by
Vf = If Rf (13.4.1)
and
Vt = Ea ± Ia Ra (13.4.2)
where the plus sign signifies a motor and the minus sign a generator. Vf is the voltage applied
to the field circuit, If is the field current, and Rf is the field-winding resistance. Vt is the terminal
voltage, Ea is the generated emf, Ia is the armature current, and Ra is the armature resistance. The
generated emf Ea is given by Equation (12.2.16) as
--`,,,``,,`,```,``,`````,`
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13.4 DIRECT-CURRENT MACHINES 595
Commutating pole (interpole)
Commutating (interpole)
field winding
Main Main
pole pole
+
+
+
+ + +
+
+
+ Armature with
+ armature winding
Shunt field Compensating field winding

winding located in main-pole shoes
Series field
winding
Figure 13.4.1 Section of a dc machine illustrating the arrangement of various field windings.
Commutating Figure 13.4.2 Schematic con-

(compole or interpole) nection diagram of a dc machine.
winding
Shunt field
Armature
Series field
Field rheostat
Compensating winding
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Ea = Ka φωm (13.4.3)
which is the speed (motional) voltage induced in the armature circuit due to the flux of the
stator-field current. The electromagnetic torque Te is given by Equation (12.2.18) as
Te = Ka φIa (13.4.4)
where Ka is the design constant. The product EaIa, known as the electromagnetic power being
converted, is related to the electromagnetic torque by the relation
Pem = Ea Ia = Te ωm (13.4.5)
For a motor, the terminal voltage is always greater than the generated emf, and the electromagnetic
torque produces rotation against a load. For a generator, the terminal voltage is less than the
generated emf, and the electromagnetic torque opposes that applied to the shaft by the prime
mover. If the magnetic circuit of the machine is not saturated, note that the flux φ in Equations
(13.4.3) and (13.4.4) is proportional to the field current If producing the flux.
Commutator Action
As a consequence of the arrangement of the commutator and brushes, the currents in all conductors
under the north pole are in one direction and the currents in all conductors under the south pole
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Ia Ia
+ +
Rf Ra Rf Ra
Vt Vt
If + If +
Ea Ea
− −
+ Vf − + Vf −
− −
(a) (b)
Figure 13.4.3 (a) Circuit representation of a dc generator under steady-state conditions, Vf = Rf If and
Vt = Ea − I aRa . (b) Circuit representation of a dc motor under steady-state conditions, Vf = Rf If and
Vt = Ea + Ia Ra .
are in the opposite direction. Thus, the magnetic field of the armature currents is stationary in
space in spite of the rotation of the armature.
The process of reversal of currents in the coil is known as commutation. The current changes
from +I to −I in time ?t. Ideally, the current in the coils being commutated should reverse
linearly with time, as shown in Figure 13.4.4. Serious departure from linear commutation results
in sparking at the brushes. Means for achieving sparkless commutation are touched upon later.
As shown in Figure 13.4.4, with linear commutation, the waveform of the current in any coil as
a function of time is trapezoidal.
Interpoles and Compensating Windings

The most generally used method for aiding commutation is by providing the machine with inter-
poles, also known as commutating poles, or simply as compoles. These are small, narrow auxiliary
poles located between the main poles and centered on the interpolar gap. The commutating
(interpole) winding is connected in series with the armature.
The demagnetizing effect of the armature mmf under pole faces can be compensated for, or
neutralized, by providing a compensating (pole-face) winding, arranged in slots in the pole face
in series with the armature, having a polarity opposite to that of the adjoining armature winding
and having the same axis as that of the armature. Because they are costly, pole-face windings
Commutation
+I
Coil current t
−I
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
∆t ∆t
Figure 13.4.4 Waveform of current in an armature coil undergoing linear commutation.
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are usually employed only in machines designed for heavy overload or rapidly changing loads,
such as steel-mill motors subjected to reverse duty cycles or in motors intended to operate over
wide speed ranges by shunt-field control. The schematic diagram of Figure 13.4.2 shows the
relative positions of various windings, indicating that the commutating and compensating fields
act along the armature axis (i.e., the quadrature axis), and the shunt as well as series fields act
along the axis of the main poles (i.e., the direct axis). It is thus possible to achieve rather complete
control of the air-gap flux around the entire armature periphery, along with smooth sparkless
commutation.
DC Generator Characteristics
Figure 13.1.8 shows schematic diagrams of field-circuit connections for dc machines with-
out including commutating pole or compensating windings. Shunt generators can be either
separately excited or self-excited, as shown in Figures 13.1.8 (a) and (b), respectively. Com-
pound machines can be connected either long shunt, as in Figure 13.1.8(d), or short shunt, in
which the shunt-field circuit is connected directly across the armature, without including the
series field.
In general, three characteristics specify the steady-state performance of a dc generator:
1. The open-circuit characteristic (abbreviated as OCC, and also known as no-load magne-
tization curve), which gives the relationship between generated emf and field current at
constant speed.
2. The external characteristic, which gives the relationship between terminal voltage and
load current at constant speed.
3. The load characteristic, which gives the relationship between terminal voltage and field
current, with constant armature current and speed.
All other characteristics depend on the form of the open-circuit characteristic, the load, and the
method of field connection. Under steady-state conditions, the currents being constant or, at most,
varying slowly, voltage drops due to inductive effects are negligible.
As stated earlier and shown in Figure 13.4.3, the terminal voltage Vt of a dc generator is
related to the armature current Ia and the generated emf Ea by
Vt = Ea − Ia Ra (13.4.6)
where Ra is the total internal armature resistance, including the resistance of interpole and
compensating windings as well as that of the brushes. The value of the generated emf Ea, by
Equation (13.4.3), is governed by the direct-axis field flux (which is a function of the field current
and armature reaction) and the angular velocity ωm of the rotor.
The open-circuit and load characteristics of a separately excited dc generator, along with
its schematic diagram of connections, are shown in Figures 13.4.5(a) and (b). It can be seen
from the form of the external volt–ampere characteristic, shown in Figure 13.4.5(c), that the
terminal voltage falls slightly as the load current increases. Voltage regulation is defined as the
percentage change in terminal voltage when full load is removed, so that, from Figure 13.4.5(c)
it follows that
Ea − Vt
Voltage regulation = × 100% (13.4.7)
Vt
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Ia = IL Figure 13.4.5 Open-circuit and

+ load characteristics of a separately
excited dc generator. (a) Schematic
Ra
diagram of connections. (b) Termi-
nal voltage versus field current rela-
tionships. (c) External volt-ampere
characteristic.
+ Vt
Ea
If −
+ Vf −
−
(a)
Drop due to Open circuit

armature reaction
Load
Terminal voltage Vt
Ia Ra
Field current If
(b)
Ea
Drop due to armature reaction
Terminal voltage Vt
Ia Ra
External characteristic
Vt at rated full load
Rated load
Load current IL
(c)
Because the separately excited generator requires a separate dc field supply, its use is limited to
applications in which a wide range of controlled voltage is essential.
A shunt generator maintains approximately constant voltage on load. It finds wide application
as an exciter for the field circuit of large ac generators. The shunt generator is also sometimes
used as a tachogenerator when a signal proportional to the motor speed is required for control or
display purposes.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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IL = Ia
+
Diverter Ea
Ra Ia(Ra + Rs)
Vt
Voltage
+ Vt
Ea
− Series field Rs
Residual
−
voltage
Vt = Ea − Ia(Ra + Rs) A C
(b) Load current
(a)
Figure 13.4.6 Dc series generator. (a) Schematic diagram of connections. (b) Volt–ampere characteristic at
constant speed.
The schematic diagram and the volt–ampere characteristic of a dc series generator at constant
speed are shown in Figure 13.4.6. The resistance of the series-field winding must be low for
efficiency as well as for low voltage drop. The series generator was used in early constant-current
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
systems by operating in the range B–C, where the terminal voltage fell off very rapidly with
increasing current.
The volt–ampere characteristics of dc compound generators at constant speeds are shown in
Figure 13.4.7. Cumulatively compound generators, in which the series- and shunt-field winding
mmfs are aiding, may be overcompounded, flat-compounded, or undercompounded, depending
on the strength of the series field. Overcompounding can be used to counteract the effect of a
decrease in the prime-mover speed with increasing load, or to compensate for the line drop when
the load is at a considerable distance from the generator. Differentially compounded generators, in
which the series-winding mmf opposes that of the shunt-field winding, are used in applications in
which wide variations in load voltage can be tolerated, and when the generator might be exposed
to load conditions approaching short circuit.
Overcompounded
(rated value) Flat compounded

1.0
Undercompounded
Per-unit
terminal voltage
Differentially
compounded
1.0 (rated value)

Per-unit armature current
Figure 13.4.7 Volt–ampere characteristics of dc compound generators

at constant speed.
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EXAMPLE 13.4.1
A 250-V, 50-kW short-shunt compound dc generator, whose schematic diagram is shown in Figure
E13.4.1(a), has the following data: armature resistance 0.05 -, series-field resistance 0.05 -, and
shunt-field resistance 130 -. Determine the induced armature emf at rated load and terminal
voltage, while taking 2 V as the total brush-contact drop.
Figure E13.4.1 Short-shunt com-

pound generator. (a) Schematic dia-
gram. (b) Equivalent circuit.
A1
F1 F2 S1 S2
A2
(a)
It
+
RSe = 0.05 Ω
Ia
If + +
Vt = 250 V
E
Rf = 130 Ω Vf −
Ra = 0.05 Ω
−
−
(b)
Solution
The equivalent circuit is shown in Figure E13.4.1(b).

50 × 103
It = = 200 A
250
It RSe = 200 × 0.05 = 10 V
Vf = 250 + 10 = 260 V
260
If = = 2.0 A
130
Ia = 200 + 2 = 202 A
Ia Ra = 202 × 0.05 = 10.1 V
E = 250 + 10.1 + 10 + 2 = 272.1 V
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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DC Motor Characteristics
We gain an understanding of the speed–torque characteristics of a dc motor from Equations
(13.4.2) through (13.4.4). In shunt motors, the field current can be simply controlled by the
use of a variable resistance in series with the field winding; the load current influences the
flux only through armature reaction, and its effect is therefore relatively small. In series mo-
tors, the flux is largely determined by the armature current, which is also the field current;
it is somewhat difficult to control the armature and field currents independently. In the com-
pound motor, the effect of the armature current on the flux depends on the degree of com-
pounding. Most motors are designed to develop a given horsepower at a specified speed,
and it follows from Equations (13.4.2) and (13.4.3) that the angular velocity ωm can be ex-
pressed as
Vt − Ia Ra
ωm = (13.4.8)
Ka φ
Thus, the speed of a dc motor depends on the values of the applied voltage Vt, the armature current
Ia, the resistance Ra, and the field flux per pole φ.
If IL = Ia + If
+
Ia Ia = IL
+
Ra
Ra
Field rheostat Vt
Diverter resistance
+ + Vt
Shunt field Ea Ea
− − Series field
− −
(a) (b)
If IL = Ia + If
+
Ia
Ra
Vt
+
Shunt field Ea
Series field
−
−
(c)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Figure 13.4.8 Schematic diagrams of dc motors. (a) Shunt motor. (b) Series motor. (c) Cumulatively
compounded motor.
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The schematic arrangement of a shunt motor is shown in Figure 13.4.8(a). For a given applied
voltage and field current, Equations (13.4.4) and (13.4.3) can be rewritten as
Te = Ka φIa = Km Ia (13.4.9)
Ea = Ka φωm = Km ωm (13.4.10)
Because Vt = Ea + Ia Ra , or Ia = (Vt − Ea )/Ra , it follows that
Km V t K 2 ωm
Te = − m (13.4.11)
Ra Ra
Vt Km ωm K 2 ω2
Pem = Ea Ia = Te ωm = − m m (13.4.12)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Ra Ra
The forms of the torque–armature current, speed–torque, and speed–power characteristics for a
shunt-connected dc motor are illustrated in Figure 13.4.9.
The shunt motor is essentially a constant-speed machine with a low speed regulation. As
seen from Equation (13.4.8), the speed is inversely proportional to the field flux, and thus it can
be varied by controlling the field flux. When the motor operates at very low values of field flux,
however, the speed will be high, and if the field becomes open-circuited, the speed will rise rapidly
beyond the permissible limit governed by the mechanical structure. In order to limit the speed to
a safe value, when a shunt motor is to be designed to operate with a low value of shunt-field flux,
it is usually fitted with a small cumulative series winding, known as a stabilizing winding.
The schematic diagram of a series motor is shown in Figure 13.4.8(b). The field flux is directly
determined by the armature current so that
Te = Ka φ Ia = KIa2 (13.4.13)
and with negligible armature resistance,
Vt = Ea = Ka φωm = KIa ωm (13.4.14)
Vt2
Te = 2
(13.4.15)
Kωm
Vt2
Pem = ωm Te = (13.4.16)
Kωm
and the speed–power curve is a rectangular hyperbola. The forms of the torque–armature current,
speed–torque, and speed–power characteristics for a series-connected dc motor are also illustrated
Shunt Shunt
Compound
Series
Torque
Speed
Speed
Shunt
Series
Series
Armature current Torque Power
Figure 13.4.9 Characteristic curves for dc motors.
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in Figure 13.4.9. Note that the no-load speed is very high; care must be taken to ensure that the
machine always operates on load. In practice, however, the series machine normally has a small
shunt-field winding to limit the no-load speed. The assumption that the flux is proportional to
the armature current is valid only on light load in the linear region of magnetization. In general,
performance characteristics of the series motor must be obtained by using the magnetization
curve. The series motor is ideally suited to traction, when large torques are required at low speeds
and relatively low torques are needed at high speeds.
A schematic diagram for a cumulatively compounded dc motor is shown in Figure 13.4.8(c).
The operating characteristics of such a machine lie between those of the shunt and series motors,
as shown in Figure 13.4.9. (The differentially compounded motor has little application, since
it is inherently unstable, particularly at high loads.) Figure 13.4.10 compares the speed–torque
characteristics of various types of electric motors; 1.0 per unit represents rated values.
Compound motor Figure 13.4.10 Typical speed–torque

Series dc motor characteristics of various electric motors.
Shunt motor
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(rated value)
1.0
Induction motor
Synchronous motor
Per-unit
speed
Per-unit torque 1.0 (rated value)
EXAMPLE 13.4.2
A 200-V dc shunt motor has a field resistance of 200 - and an armature resistance of 0.5 -.
On no load, the machine operates with full field flux at a speed of 1000 r/min with an armature
current of 4 A. Neglect magnetic saturation and armature reaction.
(a) If the motor drives a load requiring a torque of 100 N · m, find the armature current and
speed of the motor.
(b) If the motor is required to develop 10 hp at 1200 r/min, compute the required value of
external series resistance in the field circuit.
Solution
(a) Full field current If = 200/200 = 1 A. On no load, Ea = Vt −Ia Ra = 200−(4×0.5) =

198 V. Since Ea = k1 If ωm , where k 1 is a constant,
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198
k1 = = 1.89
1[(2π/60) × 1000]
On load, Te = k1 If Ia , or 100 = 1.89 × 1.0 × Ia . Therefore, the armature current
Ia = 100/1.89 = 52.9 A. Now, Vt = Ea + Ia Ra , or Ea = 200 − (52.9 × 0.5) = 173.55
V. Since Ea = k1 If ωm , it follows that
173.55
ωm = = 91.8 rad/s
1.89 × 1.0
That is, the load speed is 91.8 × 60/2π = 876 r/min.
(b) For 10 hp at 1200 r/min,
10
Te = = 59.34 N · m
(2π/60) × 1200
Then, 59.34 = 1.89If Ia, or If Ia = 31.4. Since Vt = Ea + IaRa, it follows that

2π
200 = 1.89 × 1200 If + 0.5Ia
60
0.5 × 31.4
= 237.6If + 0.5Ia = 237.6If +
If
Hence, If = 0.754 A or 0.088 A; and Ia = 31.4/If = 41.6 A or 356.8 A. Since the value of
If = 0.088 A will produce very high armature currents, it will not be considered. Thus,
with If = 0.754 A,
Rf = 200/0.754 = 265.25 -
The external resistance required is 265.25 − 200 = 65.25 -.
Speed Control of DC Motors

Equation (13.4.8) showed that the speed of a dc motor can be varied by control of the field
flux, the armature resistance, and the armature applied voltage. The three most common speed-
control methods are shunt-field rheostat control, armature circuit-resistance control, and armature
terminal-voltage control. The base speed of the machine is defined as the speed with rated armature
voltage and normal armature resistance and field flux. Speed control above the base value can
be obtained by varying the field flux. By inserting a series resistance in the shunt-field circuit
of a dc shunt motor (or a compound motor), we can achieve speed control over a wide range
above the base speed. It is important to note, however, that a reduction in the field flux causes a
corresponding increase in speed, so that the generated emf does not change appreciably while the
speed is increased, but the machine torque is reduced as the field flux is reduced. The dc motor
with shunt-field rheostat speed control is accordingly referred to as a constant-horsepower drive.
This method of speed control is suited to applications in which the load torque falls as the speed
increases. For a machine with a series field, speed control above the base value can be achieved
by placing a diverter resistance in parallel with the series winding, so that the field current is less
than the armature current.
When speed control below the base speed is required, the effective armature resistance can be
increased by inserting external resistance in series with the armature. This method can be applied
to shunt, series, or compound motors. It has the disadvantage, however, that the series resistance,
carrying full armature current, will cause significant power loss with an associated reduction in
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overall efficiency. The speed of the machine is governed by the value of the voltage drop in the
series resistor and is therefore a function of the load on the machine. The application of this method
of control is thus limited. Because of its low initial cost, however, the series-resistance method,
or a variation of it, is often attractive economically for short-time or intermittent slowdowns.
Unlike shunt-field control, armature-resistance control offers a constant-torque drive because
both flux and, to a first approximation, allowable armature current remain constant as speed varies.
The shunted-armature method is a variation of this control scheme. This is illustrated in Figure
13.4.11(a) as applied to a series motor, and in Figure 13.4.11(b) as applied to a shunt motor.
Resistors R1 and R2 act as voltage dividers applying a reduced voltage to the armature. They offer
greater flexibility in their adjustments to provide the desired performance.
The overall output limitations are as shown in Figure 13.4.12. With base speed defined as the
full-field speed of the motor at the normal armature voltage, speeds above base speed are obtained
by motor-field control at approximately constant horsepower, and speeds below base speed are
obtained by armature-voltage control at approximately constant torque. The development of solid-
state controlled rectifiers capable of handling many kilowatts has opened up a whole new field of
solid-state dc motor drives with precise control of motor speed. The control resistors (in which
energy is wasted) are eliminated through the development of power semiconductor devices and
+ +
R1 R1
Vt Vt
R2 Armature R2 Armature
Series field Shunt field
− −
(a) (b)
Figure 13.4.11 Shunted-armature method of speed control. (a) As applied to a series motor. (b) As applied
to a shunt motor.
Approximate Approximate
allowable allowable
torque horsepower
Constant torque Constant horsepower

Constant horsepower Constant
torque
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Armature voltage Motor field Armature voltage Motor field

control control control control
Base Maximum Base Maximum

speed speed speed speed
Figure 13.4.12 Output limitations combining the armature voltage and field rheostat methods of speed control.
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the evolution of flexible and efficient converters (see Section 16.1). Thus, the inherently good
controllability of a dc machine has been increased significantly.
EXAMPLE 13.4.3
Figure E13.4.3 shows a simplified Ward–Leonard system for controlling the speed of a dc motor.
Discuss the effects of varying Rfg and Rfm on the motor speed. Subscripts g and m correspond to
generator and motor, respectively.
Rag + Ram = R Figure E13.4.3 Simplified
I
Ward–Leonard system.
ωm
+ +
Ifg Ifm
G Eg M
− −
Rfg Rfm
+ − + −
Solution
Increasing Rfg decreases Ifg and hence Eg. Thus, the motor speed will decrease. The opposite will
be true if Rfg is decreased.
Increasing Rfm will increase the speed of the motor. Decreasing Rfm will result in a decrease
of the speed.
DC Motor Starting
When voltage is applied to the armature of a dc motor with the rotor stationary, no emf is generated
and the armature current is limited only by the internal armature resistance of the machine. So, to
limit the starting current to the value that the motor can commutate successfully, all except very
small dc motors are started with variable external resistance in series with their armatures. This
starting resistance is cut out manually or automatically as the motor comes up to speed.
EXAMPLE 13.4.4
A 10-hp, 230-V, 500-r/min shunt motor, having a full-load armature current of 37 A, is started
with a four-point starter. The resistance of the armature circuit, including the interpole winding,
is 0.39 -, and the resistances of the steps in the starting resistor are 1.56, 0.78, and 0.39 -, in
the order in which they are successively cut out. When the armature current has dropped to its
rated value, the starting box is switched to the next point, thus eliminating a step at a time in the
starting resistance. Neglecting field-current changes, armature reaction, and armature inductance,
find the initial and final values of the armature current and speed corresponding to each step.
Solution
Step 1: At this point, the entire resistance of the starting resistor is in series with the armature
circuit. Thus,
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RT 1 = 1.56 + 0.78 + 0.39 + 0.39 = 3.12 -

At starting, the counter emf is zero; the armature starting current is then
Vt 230
Ist = = = 73.7 A
RT 1 3.12
By the time the armature current drops to its rated value of 37 A, the counter emf is
E = 230 − 3 × 12 × 37 = 230 − 115.44 = 215.57 V
The counter emf, when the motor is delivering rated load at a rated speed of 500 r/min with the
series starting resistor completely cut out, is
230 − 0.39 × 37 = 230 − 14.43 = 215.57 V
The speed corresponding to the counter emf of 114.56 V is then given by
114.56
N= × 500 = 265.7 r/min
215.57
Step 2: The 1.56-- step is cut out, leaving a total resistance of 3.12 − 1.56 = 1.56 - in the
armature circuit. The initial motor speed at this step is 265.7 r/min, which means that the counter
emf is still 114.56 V, if the effect of armature reaction is neglected. Accordingly, the resistance
drop in the armature circuit is still 115.44 V, so that
115.44
Ia RT 2 = 115.44 or Ia = = 74A
1.56
That is, if the inductance of the armature is neglected, the initial current is 74 A. With the final
current at 37 A, the counter emf is
E = 230 − 37 × 1.56 = 230 − 57.72 = 172.28 V
corresponding to which the speed is
172.28
N= × 500 = 399.6 rpm
215.57
Step 3: The total resistance included in the armature circuit is 0.78 - at the beginning of this
step. The initial motor speed is 399.6 r/min, and the counter emf is 172.28 V. The initial armature
current is then (230 − 172.28)/0.78 = 57.72/0.78 = 74 A. With the final current at 37 A, the
counter emf is
E = 230 − 37 × 0.78 = 230 − 28.86 = 201.14 V
corresponding to which the speed is
201.14
N= × 500 = 466.5 r/min
215.57
Thus, we have the results shown in Table E13.4.4.
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TABLE E13.4.4
Current (A) Speed (r/min)

Step
Number Initial Final Initial Final
1 74 37 0 266
2 74 37 266 400
3 74 37 400 467
4 74 37 467 500
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Efficiency
As is true for any other machine, the efficiency of a dc machine can be expressed as
output input − losses losses
Efficiency = = =1− (13.4.17)
input input input
The losses are made up of rotational losses (3 to 15%), armature-circuit copper losses (3 to 6%),
and shunt-field copper losses (1 to 5%). Figure 13.4.13 shows the schematic diagram of a dc
machine, along with the power division in a generator and a motor. The resistance voltage drop,
also known as arc drop, between brushes and commutator is generally assumed constant at 2
V, and the brush-contact loss is therefore calculated as 2Ia. In such a case, the resistance of the
armature circuit should not include the resistance between brushes and commutator.
EXAMPLE 13.4.5
The following data apply to a 100-kW, 250-V, six-pole, 1000-r/min long-shunt compound
generator: no-load rotational losses 4000 W, armature resistance at 75°C = 0.015 -, series-
field resistance at 75°C = 0.005 -, interpole field resistance at 75°C = 0.005 -, and shunt-field
current 2.5 A. Assuming a stray-load loss of 1% of the output and a brush-contact resistance drop
of 2 V, compute the rated-load efficiency.
Solution
The total armature-circuit resistance (not including that of brushes) is

Ra = 0.015 + 0.005 + 0.005 = 0.025 -
100, 000
Ia = IL + If = + 2.5 = 402.5 A
250
The losses are then computed as follows:
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
No-load rotational loss 4000 W

Armature-circuit copper loss = 402.52 × 0.025 4050 W
Brush-contact loss = 2Ia = 2 × 402.5 805 W
Shunt-field circuit copper loss = 250 × 2.5 625 W
Stray-load loss = 0.01 × 100,000 1000 W
Total losses 10,480 W
The efficiency at rated load is then given by

10,480
η =1− = 1 − 0.095 = 0.905, or 90.5%
100,000 + 10,480
It is usual to determine the efficiency by some method based on the measurement of losses,
according to test codes and standards.
Applications for DC Machines

Dc motors find wide applications in which control of speed, voltage, or current is essential.
Shunt motors with constant speed are used for centrifugal pumps, fans, blowers, and conveyors,
whereas shunt motors with adjustable speed are employed in rolling mills and paper mills.
Compound motors find their use for plunger pumps, crushers, punch presses, and hoists. Series
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Ia (motor) IL (motor)
Ia (generator) IL (generator)
+
Is
If
+
Shunt field
Vta Vt
Armature Field rheostat
Series field
−
−
(a)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Input from Electromagnetic power Armature terminal power Output power

prime mover = Ea Ia = Vta Ia = Vt IL
No-load rotational loss Armature copper loss Series-field loss I 2s Rs

(friction, windage, and core) I 2a Ra + shunt-field loss I 2f Rf
+ stray-load loss + brush-contact loss
(b)
Input power
from mains Armature terminal power Electromagnetic power Output available
= Vt IL = Vta Ia = Ea Ia at shaft
Shunt-field loss I 2f Rf Brush-contact loss No-load rotational loss

+ series-field loss I 2s Rs + armature loss I 2a Ra + stray-load loss
(c)
Figure 13.4.13 (a) Schematic diagram of a dc machine. (b) Power division in a dc generator. (c) Power
division in a dc motor.
motors (known as traction motors) are utilized for electric locomotives, cranes, and car dumpers.
Universal motors, operating with either dc or ac excitation, are employed in vacuum cleaners,
food processors, hand tools, and several other household applications. They are available in sizes
of fractional horsepower up to, and well beyond, 1 hp, in speeds ranging between 2000 and 12,000
r/min.
The dc shunt generators are often used as exciters to provide dc supply. The series generator
is employed as a voltage booster and also as a constant-current source in welding machines. In
applications for which a constant dc voltage is essential, the cumulative-compound generator
finds its use. The differential-compound generator is used in applications such as arc welding,
where a large voltage drop is desirable when the current increases.
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• Principles of operation of elementary synchronous, induction, and dc machines.
• Modeling a polyphase induction machine and evaluating its steady-state performance.
• Torque–speed characteristics of three-phase induction motors.
• Basic notions of speed and torque control of polyphase induction motors.
• Starting methods for polyphase induction motors.
• Analysis of single-phase induction motors by revolving-field theory.
• Starting methods for single-phase induction motors.
• Basic ideas about applications for induction motors.
• Modeling a polyphase synchronous machine and evaluating its steady-state performance.
• Parallel operation of interconnected synchronous generators.
• Basic notions about applications for synchronous motors.
• Modeling a dc machine and evaluating its steady-state performance as a motor and generator.
• Basic ideas about speed control of dc motors, dc motor starting, and applications for dc
machines.

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Wind-Energy-Conversion Systems
It has been well recognized that renewable energy sources would have to play a key role in
solving the world energy problem. Wind energy with an estimated potential of 130 million MW
far exceeds the world’s hydraulic supply of about 3 million MW. Consequently, researchers have
been looking into the economic utilization of wind energy on a large scale by developing cost-
competitive and reliable wind-energy-conversion systems (WECSs) for various applications such
as electricity generation, agriculture, heating, and cooling.
The power coefficient Cp of wind turbines varies with the tip-speed ratio λ, as shown in
Figure 13.6.1. Maximum power transfer is achieved by ensuing operation of λopt, where the
turbine is most efficient. The mechanical power Pm available at the shaft of the wind turbine may
be expressed as a function of the wind speed v and the shaft speed w,
Pm (v, w) = C1 vw 2 + C2 v 2 w + C3 v 3 (13.6.1)
where C1 , C2 , and C3 are constants to be determined by curve-fitting techniques. Figure 13.6.2
depicts typical wind-turbine characteristics of mechanical power versus wind speed for different
values of shaft speed. The two nonzero roots of the curves represent a lower limit for the cut-in
wind speed vci and an upper limit for the cut-out wind speed vco . If the variable-speed operation is
opted and the resulting system is able to follow the wind-speed variations, the operation at optimum
tip-speed ratio can be ensured. In such a case, the power versus wind-speed characteristic will be
as shown by the dashed line in Figure 13.6.2.
WECSs developed for the generation of electricity are generally classified as:
Copyright OUP
Cp Optimum Figure 13.6.1 Typical power coefficient versus tip-speed

operating ratio characteristic.
point
Cp max
λ
λopt
Maximum Figure 13.6.2 Typical mechan-

shaft ical power versus wind speed
power characteristics of a wind turbine
1.0 for various values of shaft speed.
shaft power
P/Pmax
0.5
0 v, m/s
10 20 30
14 18 22 26
− 0.2
w = 10 rod/s
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• Constant-speed, constant-frequency (CSCF) systems
• Variable-speed, constant-frequency (VSCF) systems
• Variable-speed, variable-frequency (VSVF) systems
The generating units in these WECSs are commonly the induction and synchronous generators.
Constant shaft-speed operation requires more complex and expensive mechanical and/or
hydraulic control systems for accurate control of the shaft speed. This is usually accomplished by
controlling the turbine blades. Since the turbine operates with a low efficiency for wind speeds
other than the rated speed, only a small portion of the available wind energy is extracted. Hence
variable-shaft-speed systems have been developed.
In variable-shaft-speed operation, the turbine is allowed to rotate at different speeds with
the varying wind speed. Optimum power transfer is possible, while the actual speed of rotation
is determined by the torque–speed characteristics of both the turbine and the generator. In such
an operating mode, major control means are inevitably placed on the electrical side, since the
control of electric systems is easy to implement, more reliable, and less costly than the control of
mechanical systems.
Figure 13.6.3 illustrates a typical double-output induction generator (DOIG) scheme, in which
the DOIG is equipped with two controlled converters to allow power flow in both directions. Power
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3 phase, 50-Hz supply Figure 13.6.3 Double-output induc-

tion-generator scheme.
fs
DC link
Induction
generator
sfs
Converter 1 Converter 2
(both fully controlled)
generation over a wide range of shaft speeds, in the slip range of −1 to +1, is possible. The net
output power is maximized by varying the firing angles of both converters.
Induction generates are also employed nowadays for power generation in conjunction with
helical water turbines developed for operating in water streams.
PROBLEMS
13.1.1 A three-phase, 50-Hz induction motor has a full- (c) The speed of the rotor rotating magnetic field
load speed of 700 r/min and a no-load speed of with respect to the stator frame in r/min.
740 r/min.
(d) The speed of the rotor rotating magnetic field
(a) How many poles does the machine have? with respect to the stator rotating magnetic
(b) Find the slip and the rotor frequency at full field in r/min.
load. 13.1.4 Consider a three-phase induction motor with a
normal torque–speed characteristic. Neglecting
(c) What is the speed of the rotor field at full
the effects of stator resistance and leakage react-
load (i) with respect to the rotor? and (ii)
ance, discuss the approximate effect on the char-
with respect to the stator?
acteristic, if:
13.1.2 A three-phase, 60-Hz induction motor runs at
almost 1800 r/min at no load, and at 1710 r/min (a) The applied voltage and frequency are
at full load. halved.
(a) How many poles does the motor have? (b) Only the applied voltage is halved, but the
frequency is at its normal value.
(b) What is the per-unit slip at full load?
13.1.5 Induction motors are often braked rapidly by
(c) What is the frequency of rotor voltages at full a technique known as plugging, which is the
load? reversal of the phase sequence of the voltage
(d) At full load, find the speed of (i) the rotor supplying the motor. Assume that a motor with
field with respect to the rotor, (ii) the rotor four poles is operating at 1750 r/min from an
field with respect to the stator, and (iii) the infinite bus (a load-independent voltage supply)
rotor field with respect to the stator field. at 60 Hz. Two of the stator supply leads are
suddenly interchanged.
*13.1.3 A four-pole, three-phase induction motor is ener-
gized from a 60-Hz supply. It is running at a load (a) Find the new slip.
condition for which the slip is 0.03. Determine:
(b) Calculate the new rotor current frequency.
(a) The rotor speed in r/min.
13.1.6 A four-pole, three-phase, wound-rotor induction
(b) The rotor current frequency in Hz. machine is to be used as a variable-frequency
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PROBLEMS 613
supply. The frequency of the supply connected speed of the motor when the total line current is
to the stator is 60 Hz. 80 A in both cases.
(a) Let the rotor be driven at 3600 r/min in either 13.1.12 A 100-kW, dc shunt generator, connected to a
direction by an auxiliary synchronous motor. 220-V main, is belt-driven at 300 r/min, when
If the slip-ring voltage is 20 V, what frequen- the belt suddenly breaks and the machine con-
cies and voltages can be available at the slip tinues to run as a motor, taking 10 kW from the
rings when the rotor is at standstill? mains. The armature winding resistance is 0.025
-, and the shunt field winding resistance is 60 -.
(b) If the slip-ring voltage is 400 V, when the Determine the speed at which the machine runs
rotor frequency is 120 Hz, at what speed must as a motor.
the rotor be driven in order to give 150 Hz
at the slip-ring terminals? What will the slip- *13.1.13 A dc shunt motor runs off a constant 200-V
ring voltage be in this case? supply. The armature winding resistance is 0.4 -,
and the field winding resistance is 100 -. When
*13.1.7 A three-phase, wound-rotor induction machine, the motor develops rated torque, it draws a total
with its shaft rigidly coupled to the shaft of a line current of 17.0 A.
three-phase synchronous motor, is used to change
(a) Determine the electromagnetic power devel-
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
balanced 60-Hz voltages to other frequencies at

oped by the armature under these conditions,
the wound-rotor terminals brought out through
in watts and in horsepower.
slip rings. Both machines are electrically con-
nected to the same balanced three-phase, 60-Hz (b) Find the total line current drawn by the motor
source. Let the synchronous motor, which has when the developed torque is one-half the
four poles, drive the interconnecting shaft in the rated value.
clockwise direction, and let the eight-pole bal- 13.1.14 A dc machine, operating as a generator, develops
anced three-phase stator winding of the induc- 400 V at its armature terminals, corresponding to
tion machine produce a counterclockwise rotat- a field current of 4 A, when the rotor is driven at
ing field, i.e., opposite that of the synchronous 1200 r/min and the armature current is zero.
motor. Determine the frequency of the rotor volt- (a) If the machine produces 20 kW of electro-
ages of the induction machine. magnetic power, find the corresponding ar-
13.1.8 A synchronous generator has a rotor with six mature current and the electromagnetic
poles and operates at 60 Hz. torque produced.
(a) Determine the speed of prime mover of the (b) If the same machine is operated as a motor
generator. supplied from a 400-V dc supply, and if the
motor is delivering 30 hp to the mechanical
(b) Repeat part (a) if the generator has 12 poles.
load, determine: (i) the current taken from
(c) Repeat part (a) if the generator has 2 poles. the supply, (ii) the speed of the motor, and
13.1.9 Repeat Problem 13.1.8 if the generator operates (iii) the electromagnetic torque, if the field
at 50 Hz. current is maintained at 4 A. Assume that
13.1.10 A three-phase ac motor, used to drive a draft fan,
the armature circuit resistance and the me-
is connected to a 60-Hz voltage supply. At no- chanical losses are negligible.
load, the speed is 1188 r/min; at full load, the (c) If this machine is operated from a 440-V dc
speed drops to 1128 r/min. supply, determine the speed at which this
motor will run and the current taken from
(a) Determine the number of poles of this ac
the supply, assuming no mechanical load, no
motor.
friction and windage losses, and that the field
(b) Comment on whether this motor is an induc- current is maintained at 4 A.
tion motor or a synchronous motor. 13.1.15 Consider the operation of a dc shunt motor that is
13.1.11 A dc shunt machine has an armature winding affected by the following changes in its operating
resistance of 0.12 - and a shunt-field winding conditions. Explain the corresponding approxi-
resistance of 50 -. The machine may be run on mate changes in the armature current and speed
250-V mains as either a generator or a motor. of the machine for each change in operating con-
Find the ratio of the speed of the generator to the ditions.
Copyright OUP
(a) The field current is doubled, with the ar- Rotational and stray-load losses at full load are
mature terminal voltage and the load torque 5% of the output power. Calculate the power
remaining the same. transferred across the air gap, the rotor copper
(b) The armature terminal voltage is halved, loss at full load, and the electromagnetic torque
with the field current and load torque remain- at full load in newton-meters.
ing the same. 13.2.4 The power transferred across the air gap of a two-
pole induction motor is 24 kW. If the electromag-
(c) The field current and the armature terminal
netic power developed is 22 kW, find the slip.
voltage are halved, with the horsepower out-
Calculate the output torque if the rotational loss
put remaining the same.
at this slip is 400 W.
(d) The armature terminal voltage is halved,
13.2.5 The stator and rotor of a three-phase, 440-V,
with the field current and horsepower output
15-hp, 60-Hz, eight-pole, wound-rotor induction
remaining the same.
motor are both connected in wye and have the
(e) The armature terminal voltage is halved and following parameters per phase: R1 = 0.5 -,
the load torque varies as the square of the R2 = 0.1 -, Xl1 = 1.25 -, and Xl2 = 0.2 -.
speed, with the field current remaining the The magnetizing impedance is 40 - and the core-
same. loss impedance is 360 -, both referred to the sta-
13.2.1 A balanced three-phase, 60-Hz voltage is applied tor. The ratio of effective stator turns to effective
to a three-phase, two-pole induction motor. Cor- rotor turns is 2.5. The friction and windage losses
responding to a per-unit slip of 0.05, determine total 200 W, and the stray-load loss is estimated
the following: as 100 W. Using the equivalent circuit of Figure
13.2.5(a), calculate the following values for a
(a) The speed of the rotating-stator magnetic
slip of 0.05 when the motor is operated at rated
field relative to the stator winding.
voltage and frequency applied to the stator, with
(b) The speed of the rotor field relative to the the rotor slip rings short-circuited: stator input
rotor winding. current, power factor at the stator terminals, cur-
(c) The speed of the rotor field relative to the rent in the rotor winding, output power, output
stator winding. torque, and efficiency.
(d) The speed of the rotor field relative to the 13.2.6 Considering only the rotor equivalent circuit
stator field. shown in Figure 13.2.2 or 13.2.3, find:
(e) The frequency of the rotor currents. (a) The R2 for which the developed torque would
be a maximum.
(f) Neglecting stator resistance, leakage reac-
tance, and all losses, if the stator-to-rotor (b) The slip corresponding to the maximum
turns ratio is 2:1 and the applied voltage is torque.
100 V, find the rotor-induced emf at standstill (c) The maximum torque.
and at 0.05 slip.
(d) R2 for the maximum starting torque.
13.2.2 No-load and blocked-rotor tests are conducted
on a three-phase, wye-connected induction motor *13.2.7 A three-phase induction motor, operating at its
with the following results. The line-to-line volt- rated voltage and frequency, develops a starting
age, line current, and total input power for the torque of 1.6 times the full-load torque and a
no-load test are 220 V, 20 A, and 1000 W; and maximum torque of 2 times the full-load torque.
for the blocked-rotor test they are 30 V, 50 A, and Neglecting stator resistance and rotational losses,
1500 W. The stator resistance, as measured on a and assuming constant rotor resistance, deter-
dc test, is 0.1 - per phase. mine the slip at maximum torque and the slip
at full load.
(a) Determine the parameters of the equivalent
circuit shown in Figure 13.2.5(c). 13.2.8 A three-phase, wye-connected, 400-V, four-pole,
60-Hz induction motor has primary leakage
(b) Compute the no-load rotational losses. impedance of 1 + j 2 - and secondary leakage
*13.2.3 A three-phase, 5-hp, 220-V, six-pole, 60-Hz in- impedance referred to the primary at standstill of
duction motor runs at a slip of 0.025 at full load. 1 + j 2 -. The magnetizing impedance is j40 -
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
PROBLEMS 615
and the core-loss impedance is 400 -. Using the 13.2.10 The per-phase equivalent circuit shown in Fig-
T-equivalent circuit of Figure 13.2.5(a): ure 13.2.6 of a three-phase, 600-V, 60-Hz, four-
(a) Calculate the input current and power (i) on pole, wye-connected, wound-rotor induction mo-
the no-load test (S ∼ tor has the following parameters: R1 = 0.75 -,
= 0) at rated voltage, and
(ii) on a blocked-rotor test (S = 1) at rated R2 = 0.80 -, Xl1 = Xl2
= 2.0 -, and Xm =
voltage. 50 -. Neglect the core losses.
(b) Corresponding to a slip of 0.05, compute (a) Find the slip at which the maximum devel-
the input current, torque, output power, and oped torque occurs.
efficiency. (b) Calculate the value of the maximum torque
(c) Determine the starting torque and current; developed.
the maximum torque and the corresponding (c) What is the range of speed for stable opera-
slip; and the maximum output power and the tion of the motor?
corresponding slip.
(d) Determine the starting torque.
For the following parts, use the approximate
equivalent circuit obtained by transferring the (e) Compute the per-phase referred value of the
shunt core loss/magnetizing branch to the input additional resistance that must be inserted
terminals. in the rotor circuit in order to obtain the
maximum torque at starting.
(d) Find the same values requested in part (b).
13.2.11 A three-phase, wye-connected, 220-V, 10-hp, 60-
(e) When the machine is driven as an induction Hz, six-pole induction motor (using Figure 13.2.6
generator with a slip of −0.05, calculate the for notation) has the following parameters in
primary current, torque, mechanical power ohms per phase referred to the stator: R1 =
input, and electric power output. 0.294, R2 = 0.144, Xl1 = 0.503, X12
= 0.209,
(f) Compute the primary current and the braking and Xm = 13.25. The total friction, windage,
torque at the instant of plugging (i.e., reversal and core losses can be assumed to be constant at
of the phase sequence) if the slip immedi- 403 W, independent of load. For a slip of 2.00%,
ately before plugging is 0.05. compute the speed, output torque and power, sta-
13.2.9 A 500-hp, wye-connected, wound-rotor inductor current, power factor, and efficiency when the
tion motor, when operated at rated voltage and motor is operated at rated voltage and frequency.
frequency, develops its rated full-load output at Neglect the impedance of the source.
a slip of 0.02; maximum torque of 2 times the *13.2.12 A squirrel-cage induction motor operates at a slip
full-load torque at a slip of 0.06, with a referred of 0.05 at full load. The rotor current at starting is
rotor current of 3 times that at full load; and 1.2 five times the rotor current at full load. Neglecting
times the full-load torque at a slip of 0.2, with a stator resistance and rotational and stray-load
referred rotor current of 4 times that at full load. losses, and assuming constant rotor resistance,
Neglect rotational and stray-load losses. If the calculate the starting torque and the maximum
rotor-circuit resistance in all phases is increased torque in per-unit of full-load torque, as well as
to 5 times the original resistance, determine the the slip at which the maximum torque occurs.
following: 13.2.13 Using the approximate equivalent circuit in
(a) The slip at which the motor will develop the which the shunt branch is moved to the stator in-
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
same full-load torque. put terminals, show that the rotor current, torque,
and electromagnetic power of a polyphase induc-
(b) The total rotor-circuit copper loss at full-load
tion motor vary almost directly as the slip, for
torque.
small values of slip.
(c) The horsepower output at full-load torque.
13.2.14 A three-phase, 50-hp, 440-V, 60-Hz, four-pole,
(d) The slip at maximum torque. wound-rotor induction motor operates at a slip of
(e) The rotor current at maximum torque. 0.03 at full load, with its slip rings short-circuited.
The motor is capable of developing a maximum
(f) The starting torque. torque of two times the full-load torque at rated
(g) The rotor current at starting. voltage and frequency. The rotor resistance per
Copyright OUP
phase referred to the stator is 0.1 -. Neglect • No-load test: line-to-line voltage 400 V, input
the stator resistance and rotational and stray-load power 1770 W, input current 18.5 A, and fric-
losses. Find the rotor copper loss at full load and tion and windage loss 600 W
the speed at maximum torque. Compute the value • Blocked-rotor test: line-to-line voltage 45 V,
of the per-phase rotor resistance (referred to the input power 2700 W, and input current 63 A
stator) that must be added in series to produce a
Determine the parameters of the equivalent cir-
starting torque equal to the maximum torque.
cuit of Figure 13.2.5(a), assuming R1 = R2 and
13.2.15 A three-phase, 220-V, 60-Hz, four-pole, wye- Xl1 = Xl2
.
connected induction motor has a per-phase stator
resistance of 0.5 -. The following no-load and *13.2.18 A three-phase induction motor has the per-phase
blocked rotor test data on the motor are given: circuit parameters shown in Figure P13.2.18. At
what slip is the maximum power developed?
• No-load test: line-to-line voltage 220 V, total
input power 600 W, of which 200 W is the 13.2.19 A large induction motor is usually started by
friction and windage loss, and line current 3 A applying a reduced voltage across the motor; such
a voltage may be obtained from an autotrans-
• Blocked-rotor test: line-to-line voltage 35 V,
former. A motor is to be started on 50% of full-
total input power 720 W, and line current 15 A
load torque, and the full-voltage starting current
(a) Calculate the parameters of the equivalent is 5 times the full-load current. The full-load slip
circuit shown in Figure 13.2.5(c). is 4%. Determine the percentage reduction in the
(b) Compute the output power, output torque, applied voltage (i.e., the percentage tap on the
and efficiency if the machine runs as a motor autotransformer).
with a slip of 0.05. 13.2.20 A three-phase, 400-V, wye-connected induction
(c) Determine the slip at which maximum torque motor takes the full-load current at 45 V with the
is developed, and obtain the value of the rotor blocked. The full-load slip is 4%. Calculate
maximum torque. the tappings k on a three-phase autotransformer
Note: It may help the student to solve Problems to limit the starting current to 4 times the full-
13.2.15 through 13.2.17 if the background given load current. For such a limitation, determine the
in the solutions manual as part of the solution to ratio of starting torque to full-load torque.
Problem 13.2.15 is provided.
13.2.21 A three-phase, 2200-V, 60-Hz, delta-connected,
13.2.16 The synchronous speed of a wound-rotor induc- squirrel-cage induction motor, when started at
tion motor is 900 r/min. Under a blocked-rotor full rated voltage, takes a starting current of 693
condition, the input power to the motor is 45 kW A from the line and develops a starting torque of
at 193.6 A. The stator resistance per phase is 0.2 6250 N · m.
-, and the ratio of effective stator turns to effec-
tive rotor turns is 2. The stator and rotor are both (a) Neglect the impedance and the exciting cur-
rent of the compensator. Calculate the ra-
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
wye-connected. Neglect the effect of the core-

loss and magnetizing impedances. Calculate: tio of a starting compensator (i.e., an auto-
transformer starter) such that the current sup-
(a) The value in ohms of the rotor resistance per plied by the 2200-V line is 300 A. Compute
phase. the starting torque with the starting compen-
(b) The motor starting torque. sator.
13.2.17 The no-load and blocked-rotor tests on a three-
phase, wye-connected induction motor yield the
following results:
I '2 Figure P13.2.18

+
R1 = 0.05 Ω Xl1 + X 'l2 = 0.3 Ω
R'2
V1 Xm = 20 Ω = 0.05 Ω
S S
Copyright OUP
PROBLEMS 617
(b) If a wye–delta starting method is employed, stator winding of the induction machine is ex-
find the starting current and the starting cited from a 60-Hz supply, while the variable-
torque. frequency three-phase power is taken out of the
*13.2.22 A three-phase, four-pole, 220-V, 60-Hz induction slip rings. The output frequency range is to be
machine with a per-phase resistance of 0.5 - is 120 to 420 Hz; the maximum speed is not to
operating at rated voltage as a generator at a slip exceed 3000 r/min; and the maximum power
of −0.04, delivering 12 A of line current and a output at 420 Hz is to be 70 kW at 0.8 power
total output of 4000 W. The constant losses from factor. Assuming that the maximum-speed condi-
a no-load run as a motor are given to be 220 W, tion determines the machine size, and neglecting
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
of which 70 W represents friction and windage exciting current, losses, and voltage drops in the
losses. Calculate the efficiency of the induction induction machine, calculate:
generator. (a) The minimum number of poles for the induc-
13.2.23 A 2200-V, 1000-hp, three-phase, 60-Hz, 16-pole,
tion machine.
wye-connected, wound-rotor induction motor is (b) The corresponding minimum and maximum
connected to a 2200-V, three-phase, 60-Hz bus speeds.
that is supplied by synchronous generators. The (c) The kVA rating of the induction-machine
per-phase equivalent circuit of Figure 13.2.6 has stator winding.
the following parameters: R1 = 0.1 - = R2 ,
(d) The horsepower rating of the dc machine.
Xl1 = 0.625 - = Xl2 , and Xm = 20 -. If the
machine is driven at a speed of 459 r/min to act as 13.2.27 A 1/4-hp, 110-V, 60-Hz, four-pole, capacitor-
a generator of real power, find the rotor current start, single-phase induction motor has the fol-
referred to the stator and the real and reactive lowing parameters and losses: R1 = 2 -, Xl1 =

power outputs of the induction machine. 2.8 -, Xl2 = 2 -, R2 = 4 -, Xm = 70 -.
13.2.24 A three-phase, 440-V, 60-Hz, four-pole induction The core loss at 110 V is 25 W, and friction and
motor operates at a slip of 0.025 at full load, with windage is 12 W. For a slip of 0.05, compute
its rotor circuit short-circuited. This motor is to the output current, power factor, power output,
be operated on a 50-Hz supply so that the air-gap speed, torque, and efficiency when the motor is
flux wave has the same amplitude at the same running at rated voltage and rated frequency with
torque as on a 60-Hz supply. Determine the 50- its starting winding open.
Hz applied voltage and the slip at which the motor 13.2.28 The no-load and blocked-rotor tests conducted
will develop a torque equal to its 60-Hz full-load on a 110-V, single-phase induction motor yield
value. the following data:
13.2.25 The rotor of a wound-rotor induction motor is • No-load test: input voltage 110 V, input current 3.7
rewound with twice the number of its original A, and input power 50 W
turns, with a cross-sectional area of the conductor
• Blocked-rotor test: input voltage 50 V and input
in each turn of one-half the original value. De-
current 5.6 A
termine the ratio of the following in the rewound
motor to the corresponding original quantities: Taking the stator resistance to be 2.0 -, friction
(a) Full-load current. and windage loss to be 7 W, and assuming Xl1 =

Xl2 , determine the parameters of the double-
(b) Actual rotor resistance. revolving-field equivalent circuit.
(c) Rotor resistance referred to the stator. *13.2.29 The impedance of the main and auxiliary wind-
Repeat the problem, given that the original rotor ings of a 1/3-hp, 120-V, 60-Hz, capacitor-start
is rewound with the same number of turns as motor are given as Z̄m = 4.6 + j 3.8 - and
originally, but with one-half the original cross- Z̄a = 9.6 + j 3.6 -. Determine the value of the
section of the conductor. Neglect the changes in starting capacitance that will cause the main and
the leakage flux. auxiliary winding currents to be in quadrature at
13.2.26 A wound-rotor induction machine, driven by a starting.
dc motor whose speed can be controlled, is op- *13.3.1 A three-phase, wye-connected, cylindrical-rotor
erated as a frequency changer. The three-phase synchronous generator rated at 10 kVA and 230
Copyright OUP
V has a synchronous reactance of 1.5 - per phase (a) The exciter setting Vex for operation at rated
and an armature resistance of 0.5 - per phase. conditions and a power factor of (i) 0.866
(a) Determine the voltage regulation at full load lagging, and (ii) 0.866 leading.
with: (i) 0.8 lagging power factor, and (ii) 0.8 (b) Vex in part (a) for unity power factor and the
leading power factor. same real power input as in part (a).
(b) Calculate the power factor for which the volt- (c) The complex power absorbed by the ma-
age regulation becomes zero on full load. chine in parts (a) and (b).
13.3.2 A three-phase, wye-connected, 2300-V, four- 13.3.6 For a 45-kVA, three-phase, wye-connected, 220-
pole, 1000-kVA, 60-Hz synchronous machine V synchronous machine at rated armature cur-
has a synchronous reactance Xs = 5 -, a field re- rent, the short-circuit load loss (total for three
sistance Rf = 10 -, and an approximately linear phases) is 1.80 kW at a temperature of 25°C. The
magnetization characteristic (Ef versus If ) with dc resistance of the armature at this temperature
a slope Kag = 200 -. The machine is connected is 0.0335 - per phase. Compute the effective
to a balanced three-phase ac system and is used armature ac resistance in per unit and in ohms
as a generator. Determine the following: per phase at 25°C.
(a) The rated stator current. *13.3.7 A 4000-V, 5000-hp, 60-Hz, 12-pole synchronous
(b) The exciter setting Vex = If Rf for operating motor, with a synchronous reactance of 4 - per
the machine at rated conditions, at a power phase (based on cylindrical-rotor theory), is ex-
factor of (i) 0.866 lagging and (ii) 0.866 cited to produce unity power factor at rated load.
leading. Neglect all losses.
(c) Vex in part (b) for unity power factor and the (a) Find the rated and maximum torques.
same real power output as in part (b). (b) What is the armature current corresponding
(d) The complex power delivered by the gener- to the maximum torque?
ator to the system for parts (b) and (c). 13.3.8 A three-phase, wye-connected, four-pole, 400-
13.3.3 The loss data for the synchronous generator of V, 60-Hz, 15-hp synchronous motor has a syn-
Problem 13.3.2 are: chronous reactance of 3 - per phase and negligi-
ble armature resistance. The data for its no-load
Open-circuit core magnetization curve follow:
loss at 13.8 kV 70 kW
Short-circuit load Field current, A:
loss at 418 A, 75°C 50 kW 2 3.5 4.4 6 8 10 12
Friction and windage Line-to-neutral voltage, V:
100 175 200 232 260 280 295
loss 80 kw
Field-winding resis-
tance at 75°C 0.3 - (a) When the motor operates at full load at 0.8
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Stray-load loss at leading power factor, determine the power

full load 20 kW angle and the field current. Neglect all losses.
(b) Compute the minimum line current for the
Determine the efficiency of the generator at rated
motor operating at full load and the corre-
load, rated voltage, and 0.8 power factor lagging.
sponding field current.
13.3.4 A three-phase, six-pole, wye-connected syn-
chronous generator is rated at 550 V and has (c) When the motor runs with an excitation of 10
a synchronous reactance Xs = 2 -. When the A while taking an armature current of 25 A,
generator supplies 50 kVA at rated voltage and calculate the power developed and the power
a power factor of 0.95 lagging, find the arma- factor.
ture current Ia and the excitation voltage Ef . (d) If the excitation is adjusted such that the
Sketch the phasor diagram of V̄t , I¯a , and Ēf . magnitudes of the excitation voltage and the
Also, determine the regulation corresponding to terminal voltage are equal, and if the motor
the operating conditions. is taking 20 A, find the torque developed.
13.3.5 The synchronous machine of Problem 13.3.2 is 13.3.9 A three-phase, wye-connected, 2300-V, 60-Hz,
to be used as a motor. Determine the following: round-rotor synchronous motor has a syn-
Copyright OUP
PROBLEMS 619
chronous reactance of 2 - per phase and neg- (b) The reactive power of the motor.
ligible armature resistance. 13.3.14 Two identical three-phase, 33-kV, wye-
(a) If the motor takes a line current of 350 A op- connected, synchronous generators operating in
erating at 0.8 power factor leading, calculate parallel share equally a total load of 12 MW
the excitation voltage and the power angle. at 0.8 lagging power factor. The synchronous
reactance of each machine is 8 - per phase, and
(b) If the motor is operating on load with a power
the armature resistance is negligible.
angle of −20°, and the excitation is adjusted
so that the excitation voltage is equal in mag- (a) If one of the machines has its field excita-
nitude to the terminal voltage, determine the tion adjusted such that it delivers 125 A lag-
armature current and the power factor of the ging current, determine the armature current,
motor. power factor, excitation voltage, and power
13.3.10 A 2300-V, three-phase, wye-connected, round- angle of each machine.
rotor synchronous motor has a synchronous reac- (b) If the power factor of one of the machines is
tance of 3 - per phase and an armature resistance 0.9 lagging, find the power factor and current
of 0.25 - per phase. The motor operates on load of the other machine.
with a power angle of −15°, and the excitation is 13.3.15 A three-phase, wye-connected, round-rotor, 220-
adjusted so that the internally induced voltage V, 60-Hz, synchronous motor, having a syn-
is equal in magnitude to the terminal voltage. chronous reactance of 1.27 - per phase and
Determine: negligible armature resistance, is connected in
(a) The armature current. parallel with a three-phase, wye-connected load
(b) The power factor of the motor. that takes a current of 50 A at 0.707 lagging
Neglect the effect of armature resistance. power factor and 220 V line-to-line. At a power
angle of 30°, the power developed by the motor is
13.3.11 An induction motor takes 350 kW at 0.8 power
33 kW. Determine the reactive kVA of the motor,
factor lagging while driving a load. When an and the overall power factor of the motor and the
overexcited synchronous motor taking 150 kW load.
is connected in parallel with the induction mo-
tor, the overall power factor is improved to 0.95 13.3.16 A three-phase, wye-connected, 2500-kVA, 6600-
lagging. Determine the kVA rating of the syn- V, 60-Hz turboalternator has a per-phase syn-
chronous motor. chronous reactance and an armature resistance
of 10.4 and 0.071 -, respectively. Compute the
*13.3.12 An industrial plant consumes 500 kW at a lagging
power factor for zero voltage regulation on full
power factor of 0.6.
load.
(a) Find the required kVA rating of a syn- 13.4.1 A 100-kW, 250-V shunt generator has an
chronous capacitor to improve the power armature-circuit resistance of 0.05 - and a field-
factor to 0.9. circuit resistance of 60 -. With the generator
(b) If a 500-hp, 90% efficient synchronous mo- operating at rated voltage, determine the induced
tor, operating at full load and 0.8 leading voltage at (a) full load, and (b) one-half full load.
power factor, is added instead of the capaci- Neglect brush-contact drop.
tor in part (a), calculate the resulting power 13.4.2 A 100-kW, 230-V shunt generator has Ra =
factor. 0.05 - and Rf = 57.5 -. If the generator oper-
13.3.13 A three-phase, wye-connected, cylindrical-rotor, ates at rated voltage, calculate the induced volt-
synchronous motor, with negligible armature re- age at (a) full load, and (b) one-half full load.
sistance and a synchronous reactance of 1.27 - Neglect brush-contact drop.
per phase, is connected in parallel with a three- *13.4.3 A 10-hp, 250-V shunt motor has an armature-
phase, wye-connected load taking 50 A at 0.707 circuit resistance of 0.5 - and a field resistance
lagging power factor from a three-phase, 220-V, of 200 -. At no load, rated voltage, and 1200
60-Hz source. If the power developed by the mo- r/min, the armature current is 3 A. At full load
tor is 33 kW at a power angle of 30°, determine: and rated voltage, the line current is 40 A, and the
(a) The overall power factor of the motor and flux is 5% less than its no-load value because of
the load. armature reaction. Compute the full-load speed.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
13.4.4 When delivering rated load a 10-kW, 230-V self- The armature-circuit resistance is 0.25 - and the
excited shunt generator has an armature-circuit series-field resistance is 0.25 -. Calculate the
voltage drop that is 6% of the terminal voltage speed of the motor (a) when the armature current
and a shunt-field current equal to 4% of the rated is 25 A, and (b) when the electromagnetic torque
load current. Calculate the resistance of the ar- is 36 N · m. Neglect the armature reaction.
mature circuit and the field circuit.
*13.4.12 A dc series motor operates at 750 r/min with
13.4.5 A 20-hp, 250-V shunt motor has a total armature- a line current of 100 A from the 250-V mains.
circuit resistance of 0.25 - and a field-circuit Its armature-circuit resistance is 0.15 - and its
resistance of 200 -. At no load and rated voltage, series-field resistance is 0.1 -. Assuming that
the speed is 1200 r/min, and the line current is the flux corresponding to a current of 25 A is
4.5 A. At full load and rated voltage, the line 40% of that corresponding to a current of 100 A,
current is 65 A. Assume the field flux to be determine the motor speed at a line current of 25
reduced by 6% from its value at no load, due A at 250 V.
to the demagnetizing effect of armature reaction.
Compute the full-load speed. 13.4.13 A 7.5-hp, 250-V, 1800-r/min shunt motor, having
a full-load line current of 26 A, is started with a
13.4.6 A dc series motor is connected to a load. The
four-point starter. The resistance of the armature
torque varies as the square of the speed. With the
circuit, including the interpole winding, is 0.48
diverter-circuit open, the motor takes 20 A and
-; and the resistance of the shunt-field circuit,
runs at 500 r/min. Determine the motor current
including the field rheostat, is 350 -. The resis-
and speed when the diverter-circuit resistance is
tances of the steps in the starting resistor are 2.24,
made equal to the series-field resistance. Neglect
1.47, 0.95, 0.62, 0.40, and 0.26 -, in the order
saturation and the voltage drops across the series-
in which they are successively cut out. When the
field resistance as well as the armature resistance.
armature current is dropped to its rated value,
13.4.7 A 50-kW, 230-V compound generator has the fol- the starting box is switched to the next point,
lowing data: armature-circuit resistance 0.05 -, thus eliminating a step in the starting resistance.
series-field circuit resistance 0.05 -, and shunt- Neglecting field-current changes, armature reac-
field circuit resistance 125 -. Assuming the total tion, and armature inductance, find the initial and
brush-contact drop to be 2 V, find the induced final values of the armature current and speed
armature voltage at rated load and rated terminal corresponding to each step.
voltage for: (a) short-shunt, and (b) long-shunt
13.4.14 Two shunt generators operate in parallel to supply
compound connection.
a total load current of 3000 A. Each machine has
*13.4.8 A 50-kW, 250-V, short-shunt compound genera- an armature resistance of 0.05 - and a field resis-
tor has the following data: Ra = 0.06 -, RS = tance of 100 -. If the generated emfs are 200 and
0.04 -, and Rf = 125 -. Calculate the induced 210 V, respectively, determine the load voltage
armature voltage at rated load and terminal volt- and the armature current of each machine.
age. Take 2 V as the total brush-contact drop.
13.4.15 Three dc generators are operating in parallel with
13.4.9 Repeat the calculations of Problem 13.4.8 for a
machine that is a long-shunt compound genera- excitations such that their external characteristics
tor. are almost straight lines over the working range
with the following pairs of data points:
13.4.10 A 10-kW, 230-V shunt generator, with an
armature-circuit resistance of 0.1 - and a field-
circuit resistance of 230 -, delivers full load at Terminal Voltage (V)
rated voltage and 1000 r/min. If the machine is Load Current (A) Generator I Generator II Generator III
run as a motor while absorbing 10 kW from 230-
V mains, find the speed of the motor. Neglect the 0 492.5 510 525
2000 482.5 470 475
brush-contact drop.
13.4.11 The magnetization curve taken at 1000 r/min on
a 200-V dc series motor has the following data: Compute the terminal voltage and current of each
generator.
Field current, A: 5 10 15 20 25 30
Voltage, A: 80 160 202 222 236 244 (a) When the total load current is 4350 A.
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PROBLEMS 621
(b) When the load is completely removed with- 13.4.19 A dc series motor, with a design constant Ka =
out change of excitation currents. 40 and flux per pole of 46.15 mWb, operates at
13.4.16 The external-characteristics data of two shunt
200 V while taking a current of 325 A. The total
generators in parallel are given as follows: series-field and armature-circuit resistances are
25 and 50 m-, respectively. The core loss is 220
W; friction and windage loss is 40 W. Determine:
Load Current, A: 0 5 10 15 20 25 30
(a) The electromagnetic torque developed.
Terminal voltage I, V: 270 263 254 240 222 200 175 (b) The motor speed.
Terminal voltage II, V: 280 277 270 263 253 243 228
(c) The mechanical power output.
(d) The motor efficiency.
Calculate the load current and terminal voltage 13.4.20 A 230-V dc shunt motor delivers 30 hp at the shaft
of each machine. at 1120 r/min. If the motor has an efficiency of
87% at this load, find:
(a) When the generators supply a load resistance
of 6 -. (a) The total input power.
(b) The line current.
(b) When the generators supply a battery of emf
(c) If the torque lost due to friction and windage
300 V and resistance of 1.5 -.
is 7% of the shaft torque, calculate the de-
*13.4.17 A separately excited dc generator with an veloped torque.
armature-circuit resistance Ra is operating at a 13.4.21 A 10-kW, 250-V dc shunt generator, having an
terminal voltage Vt, while delivering an armature armature resistance of 0.1 - and a field resistance
current Ia, and has a constant loss Pc. Find the of 250 -, delivers full load at rated voltage and
value of Ia for which the generator efficiency is 800 r/min. The machine is now run as a motor
a maximum. while taking 10 kW at 250 V. Neglect the brush-
13.4.18 A 100-kW, 230-V, dc shunt generator, with Ra = contact drop. Determine the speed of the motor.
0.05 -, and Rf = 57.5 - has no-load rotational 13.4.22 A 10-hp, 230-V dc shunt motor takes a full-
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loss (friction, windage, and core loss) of 1.8 kW. load line current of 40 A. The armature and field
Compute: resistances are 0.25 and 230 -, respectively. The
total brush-contact drop is 2 V, and the core and
(a) The generator efficiency at full load.
rotational losses are 380 W. Assume that stray-
(b) The horsepower output from the prime load loss is 1% of output. Compute the efficiency
mover to drive the generator at this load. of the motor.
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PART
INFORMATION SYSTEMS
FOUR
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14 Signal Processing
14.1 Signals and Spectral Analysis
14.2 Modulation, Sampling, and Multiplexing
14.3 Interference and Noise
14.5 Practical Application: A Case Study—Antinoise Systems—Noise Cancellation
Problems
The essential feature of communication, control, computation, and instrumentation systems is

the processing of information. Because of the relative ease and flexibility of processing and
transmitting electrical quantities, usually the information obtained from a nonelectrical source is
converted into electrical form. An electric signal is a voltage or current waveform whose time or
frequency variations correspond to the desired information. The information-bearing signals are
processed either for purposes of measurement in an instrumentation system, or for transmitting
over long distance in a communication system. All such systems, regardless of their particular
details, share certain basic concepts and common problems.
Continuous signals (shown in Figure 6.0.1) are described by time functions which are defined
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for all values of t (a continuous variable). Commercial broadcast systems, analog computers,
and various control and instrumentation systems process continuous signals. The information
processed in analog systems is contained in the time function which defines the signal. Analog
systems are often thought of as performing signal processing in the frequency domain.
Discrete signals (shown in Figure 6.0.2), on the other hand, exist only at specific instances
of time, and as such, their functional description is valid only for discrete-time intervals. Dis-
crete signals are invariably a sequence of pulses in which the information is contained in the
pulse characteristics and the relation amidst the pulses in the sequence during a specified time
interval. Digital computers, pulsed-communication systems (modern telephone and radar), and
microprocessor-based control systems utilize discrete signals. Digital systems process digits, i.e.,
pulse trains, in which the information is carried in the pulse sequence rather than the amplitude–
time characterization of the pulses. Digital systems are often thought of as performing signal
processing in the time domain. Because of the advantages of economy in time, low power
625
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626 SIGNAL PROCESSING
consumption, accuracy, and reliability, digital communication systems are increasingly used for
transmitting information.
Foremost among signal concepts is spectral analysis (representation of signals in terms of
their frequency components), a concept that serves as a unifying thread in signal processing and
communication systems. Signals and spectral analysis are considered first in Section 14.1. Then
in Section 14.2, processing techniques such as equalization, filtering, sampling, modulation, and
multiplexing are presented, while topics on interference and noise are exposed in Section 14.3. The
circuit functions required for time-domain processing parallel those needed for frequency-domain
processing.
14.1 SIGNALS AND SPECTRAL ANALYSIS

Figure 14.1.1 shows the functional block diagram of a signal-processing system. The information
source may be a speech (voice), an image (picture), or plain text in some language. The output
of a source that generates information may be described in probabilistic terms by a random
variable, when the random or stochastic signal is defined by a probability density function. The
output of a source may not be deterministic, given by a real or complex number at any instant of
time. However, in view of the scope of this text, random signals and random processes are not
discussed here.
A transducer is usually required to convert the output of a source into an electrical signal
that is suitable for transmission. Typical examples include a microphone converting an acoustic
speech or a video camera converting an image into electric signals. A similar transducer is needed
at the destination to convert the received electric signals into a form (such as voice, image, etc.)
that is suitable for the user.
The heart of any communication system consists of three basic elements: transmitter, trans-
mission medium or channel, and receiver. The transmitter (input processor) converts the electric
signal into a form that is suitable for transmission through the physical channel or transmis-
sion medium. For example, in radio and TV broadcasts, since the FCC (Federal Communi-
cations Commission) specifies the frequency range for each transmitting station, the trans-
mitter must translate the information signal to be transmitted into the appropriate frequency
range that matches the frequency allocation assigned to the transmitter. This process is called
modulation, which usually involves the use of the information signal to vary systematically
the amplitude, frequency, or phase of a sinusoidal carrier. Thus, in general, carrier modula-
tion such as amplitude modulation (AM), frequency modulation (FM), or phase modulation
Information Input Input processor

source transducer (transmitter)
Transmission medium
Attenuation, distortion, interference, noise
(channel)
Output signal Output Output processor

at destination transducer (receiver)
Figure 14.1.1 Functional block diagram of a signal-processing system.

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14.1 SIGNALS AND SPECTRAL ANALYSIS 627
(PM) is performed primarily at the transmitter. For example, for a radio station found at a
setting of AM820, the carrier wave transmitted by the radio station is at the frequency of
820 kHz.
The function of the receiver is to recover the message signal contained in the received
signal. If the message signal is transmitted by carrier modulation, the receiver performs carrier
demodulation to extract the message from the sinusoidal carrier.
The communication channel (transmission medium) is the physical medium that is utilized to
send the signal from the transmitter to the receiver. In wireless transmission, such as microwave
radio, the transmission medium is usually the atmosphere or free space. Telephone channels, on
the other hand, employ a variety of physical media such as wire lines and optical fiber cables.
Irrespective of the type of physical medium for signal transmission, the essential feature is that
the transmitted signal is corrupted in a random manner by a variety of possible mechanisms. For
simplicity, the effects of these phenomena (attenuation, distortion, interference, noise, etc.) are
shown at the center of Figure 14.1.1, since the transmission medium is often the most vulnerable
part of a communication system, particularly over long distances.
Attenuation, caused by losses within the system, reduces the size or strength of the signal,
whereas distortion is any alteration of the waveshape itself due to energy storage and/or non-
linearities. Contamination by extraneous signals causes interference, whereas noise emanates
from sources both internal and external to the system. To eliminate any one of these may pose a
challenge to the design engineer.
Successful information recovery, while handling the aforementioned problems, invariably
calls for signal processing at the input and output. Common signal-processing operations include
the following:
• Amplification to compensate for attenuation
• Filtering to reduce interference and noise, and/or to obtain selected facets of information
• Equalization to correct some types of distortion
• Frequency translation or sampling to get a signal that better suits the system characteristics
• Multiplexing to permit one transmission system to handle two or more information-bearing
signals simultaneously
In addition, to enhance the quality of information recovery, several specialized techniques,
such as linearizing, averaging, compressing, peak detecting, thresholding, counting, and timing,
are used.
Analog signals in an analog communication system can be transmitted directly via carrier
modulation over the communication channel and demodulated accordingly at the receiver. Alter-
natively, an analog source output may be converted into a digital form and the message can be
transmitted via digital modulation and demodulated as a digital signal at the receiver. Potential
advantages in transmitting an analog signal by means of digital modulation are the following:
• Signal fidelity is better controlled through digital transmission than through analog trans-
mission; effects of noise can be reduced significantly.
• Since the analog message signal may be highly redundant, with digital processing, redun-
dancy may be removed prior to modulation.
• Digital communication systems are often more economical to implement.
Figure 14.1.2 illustrates the basic elements of a digital communication system. For each
function in the transmitting station, there is an inverse operation in the receiver. The analog input
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Digital message
source
Analog message Analog-to-digital Source Channel Digital

source converter encoder encoder modulator
(transmitter side)
Noise, interference Channel
(receiver side)
Analog message Digital-to-analog Source Channel Digital

output signal converter decoder decoder demodulator
Digital message
output signal
Figure 14.1.2 Basic elements of a digital communication system.
signal (such as an audio or video signal) must first be converted to a digital signal by an analog-
to-digital (A/D) converter. If no analog message is involved, a digital signal (such as the output
of a teletype machine, which is discrete in time and has a finite number of output characters) can
be directly input.
Encoding is a critical function in all digital systems. The messages produced by the source
are usually converted into a sequence of binary digits. The process of efficiently converting the
output of either an analog or a digital source into a sequence of binary digits is called source
encoding or data compression.
The sequence of binary digits from the source encoder, known as the information sequence,
is passed on to the channel encoder. The purpose of the channel encoder is to introduce some
redundancy in a controlled manner in the binary information sequence, so that the redundancy
can be used at the receiver to overcome the effects of noise and interference encountered in the
transmission of the signal through the channel. Thus, redundancy in the information sequence
helps the receiver in decoding the desired information sequence, thereby increasing the reliability
of the received data and improving the fidelity of the received signal.
The binary sequence at the output of the channel encoder is passed on to the digital modulator,
which functions as the interface to the communication channel. The primary purpose of the digital
modulator is to map the binary information sequence into signal waveforms, since nearly all the
communication channels used in practice are capable of transmitting electric signals (waveforms).
Because the message has only two amplitudes in a binary system, the modulation process is known
as keying. In amplitude-shift keying (ASK), a carrier’s amplitude is shifted or keyed between two
levels. Phase-shift keying (PSK) involves keying between two phase angles of the carrier, whereas
frequency-shift keying (FSK) consists of shifting a carrier’s frequency between two values. Many
other forms of modulation are also possible.
The functions of the receiver in Figure 14.1.2 are the inverse of those in the transmitter.
At the receiving end of a digital communication system, the digital demodulator processes the
channel-corrupted transmitted waveform and reduces each waveform to a single number, which
represents an estimate of the transmitted data symbol. For example, when binary modulation is
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used, the demodulator may process the received waveform and decide on whether the transmitted
bit is a 0 or 1. The source decoder accepts the output sequence from the channel decoder, and
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from the knowledge of the source encoding method used, attempts to reconstruct the original
signal from the source. Errors due to noise, interference, and practical system imperfections
do occur. The digital-to-analog (D/A) converter reconstructs an analog message that is a close
approximation to the original message. The difference, or some function of the difference, between
the original signal and the reconstructed signal is a measure of the distortion introduced by the
digital communication system.
The remainder of this chapter deals with basic methods for analyzing and processing analog
signals. A large number of building blocks in a communication system can be modeled by linear
time-invariant (LTI) systems. LTI systems provide good and accurate models for a large class of
communication channels. Some basic components of transmitters and receivers (such as filters,
amplifiers, and equalizers) are LTI systems.
Periodic Signals and Fourier Series

In the study of analog systems, predicting the response of circuits to a general time-varying voltage
or current waveform x(t) is a difficult task. However, if x(t) can be expressed as a sum of sinusoids,
then the principle of superposition can be invoked on linear systems and the frequency response
of the circuit can be utilized to expedite calculations. Expressing a signal in terms of sinusoidal
components is known as spectral analysis. Let us begin here by considering the Fourier-series
expansion of periodic signals, which has been introduced in Section 3.1.
A periodic signal has the property that it repeats itself in time, and hence, it is sufficient to
specify the signal in the basic time interval called the period. A periodic signal x(t) satisfies the
property
x(t + kT ) = x(t) (14.1.1)
for all t, all integers k, and some positive real number T, called the period of the signal. For
discrete-time periodic signals, it follows that
x(n + kN ) = x(n) (14.1.2)
for all integers n, all integers k, and a positive integer N, called the period. A signal that does not
satisfy the condition of periodicity is known as nonperiodic.
EXAMPLE 14.1.1
Consider the following signals, sketch each one of them and comment on the periodic nature:
(a) x(t) = A cos(2πf0 t + θ), where A, f 0, and θ are the amplitude, frequency, and phase of
the signal.
(b) x(t) = ej (2πf0 t+θ ) , A > 0.
(
1, t >0
(c) Unit step signal u−1 (t) defined by u−1 (t) = 1/ , t = 0 .
2
0, t <0
(d) Discrete-time signal x[n] = A cos(2πf0 n + θ), where n is an integer.
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Solution
(a) This is a continuous-time signal (called a sinusoidal signal) that is real and periodic with
period T = 1/f0 , as sketched in Figure E14.1.1(a).
(b) This is a complex periodic exponential signal. Its real part is
xr (t) = A cos(2πf0 t + θ)
and its imaginary part is
xi (t) = A sin(2πf0 t + θ)
This signal could also be described in terms of its modulus and phase. The absolute value
of x(t) is

|x(t)| = xr2 (t) + xi2 (t) = A
and its phase is

x(t) = 2πf0 t + θ
Sketches of these functions are shown in Figure E14.1.1(b). In addition, the following
relations apply:
xr (t) = |x(t)| cos[ x(t)]

xi (t) = |x(t)| sin[ x(t)]
xi (t)
x(t) = arctan
xr (t)
(c) The unit step signal is a nonperiodic signal, sketched in Figure E14.1.1(c).
(d) A sketch of this discrete-time signal is shown in Figure E14.1.1(d).
This is not periodic for all values of f 0. The condition for it to be periodic is
2πf0 (n + kN ) + θ = 2πf0 n + θ + 2mπ

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x(t) Figure E14.1.1 (a) Sinusoidal signal. (b) Real–imaginary and

magnitude–phase graphs of the complex exponential signal. (c)
Unit step signal. (d) Discrete sinusoidal signal.
3
2
1
0 t
−1
−2
−3
(a)
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xr(t) xi(t)
t t
|x(t)| ∠x(t)
1
t
t
−4 −2 0 2 4
(b)
u−1(t)
1
2
t
(c)
x[n]
2.5
2
1.5
1
0.5
0 n
−0.5
−1
−1.5
−2
−2.5
(d)
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for all integers n and k, some positive integer N, and some integer m. From this it follows
that
2πf0 kN = 2mπ or f0 = m/(kN )
that is, the discrete sinusoidal signal is periodic only for rational values of f 0.
Evenness and oddness are expressions of various types of symmetry present in signals. A
signal x(t) is even if it has a mirror symmetry with respect to the vertical axis. A signal is odd
if it is symmetric with respect to the origin. The signal x(t) is even if and only if, for all t, it
satisfies
x(−t) = x(t) (14.1.3)
and is odd if and only if, for all t,
x(−t) = −x(t) (14.1.4)
Any signal x(t), in general, can be expressed as the sum of its even and odd parts,
x(t) = xe (t) + x0 (t) (14.1.5)
x(t) + x(−t)
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xe (t) = (14.1.6)
2
x(t) − x(−t)
xo (t) = (14.1.7)
2
The half-wave symmetry is expressed by

T
x t± = −x(t) (14.1.8)
2
EXAMPLE 14.1.2
Discuss the nature of evenness and oddness of:
(a) The sinusoidal signal x(t) = A cos(2πf0 t + θ).
(b) The complex exponential signal x(t) = ej 2πf0 t .
Solution
(a) The signal is, in general, neither even nor odd. However, for the special case of θ = 0,
it is even; for the special case of θ = ±π/2, it is odd. In general,
x(t) = A cos θ cos 2πf0 t − A sin θ sin 2πf0 t
Since cos 2πf0 t is even and sin 2πf0 t is odd, it follows that
xe (t) = A cos θ cos 2πf0 t
and
xo (t) = −A sin θ sin 2πf0 t
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(b) From the sketches of Figure E14.1.1(b), for θ = 0, x(t) = Aej 2πf0 t , the real part and
the magnitude are even; the imaginary part and the phase are odd. Noting that a complex
signal x(t) is called hermitian if its real part is even and its imaginary part is odd, the
signal and symmetry are then said to be hermitian.
A signal x(t) is said to be causal if, for all t < 0, x(t) = 0; otherwise, the signal is noncausal.
An anticausal signal is identically equal to zero for t > 0. A discrete-time signal is a causal signal
if it is identically equal to zero for n < 0. Note that the unit step multiplied by any signal produces
a causal version of the signal.
Signals can also be classified as energy-type and power-type signals based on the finiteness
of their energy content and power content, respectively. A signal x(t) is an energy-type signal if
and only if the energy Ex of the signal,
∞ T /2
Ex = |x(t)| dt = lim
2
|x(t)|2 dt (14.1.9)
−∞ T →∞ −T /2
is well defined and finite. A signal is a power-type signal if and only if the power Px of the signal,
T /2
1
Px = lim |x(t)|2 dt (14.1.10)
T →∞ T −T /2
is well defined and 0 ≤ Px < ∞. For real signals, note that |x(t)|2 can be replaced by x 2 (t).
EXAMPLE 14.1.3
(a) Evaluate whether the sinusoidal signal x(t) = A cos (2πf0 t + θ) is an energy-type or a
power-type signal.
(b) Show that any periodic signal is not typically energy type, and the power content of any
periodic signal is equal to the average power in one period.
Solution
T /2
(a) Ex = lim A2 cos2 (2πf0 t + θ) dt = ∞
T →∞ −T /2
Therefore, the sinusoidal signal is not an energy-type signal. However, the power of this
signal is
T /2 --`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
1
Px = lim A2 cos2 (2πf0 t + θ) dt
T →∞ T −T /2
T /2 2
1 A
= lim [1 + cos(4πf0 t + 2θ)] dt
T →∞ T −T /2 2
( +T /2 1
A2 T A2
= lim + sin(4πf0 t + 2θ)
T →∞ 2T 8πf0 T −T /2
A2
= <∞
2
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Hence, the given x(t) is a power-type signal with its power given by A2 /2.
(b) For any periodic signal with period T 0, the energy is given by
+T /2 +nT0 /2
Ex = lim |x(t)| dt = lim
2
|x(t)|2 dt
T →∞ −T /2 n→∞ −nT0 /2
+T0 /2
= lim n |x(t)|2 dt = ∞
n→∞ −T0 /2
Therefore, periodic signals are not typically energy type. The power content of any
periodic signal is
T /2 nT0 /2
1 1
Px = lim |x(t)| dt = lim |x(t)|2 dt
2
T →∞ T −T /2 n→∞ nT0 −nT0 /2
T0 /2 T0 /2
n 1
= lim |x(t)|2 dt = |x(t)|2 dt
n→∞ nT0 −T0 /2 T0 −T0 /2
which shows that the power content of a periodic signal is equal to the average power in
one period.
The Fourier-series representation states that almost any periodic signal can be decomposed
into an infinite series of the form
∞

x(t) = a0 + (an cos nωt + bn sin nωt) (14.1.11)
n=1
where a0, a1, b1, . . . are the Fourier coefficients, and ω is the fundamental angular frequency
related to the period T by ω = 2π/T = 2πf . The integer multiples of ω are known as harmonics:
2ω being the second harmonic that is even, 3ω being the third harmonic that is odd, and so forth.
The dc component is given by
T
1
a0 = x(t)dt (14.1.12)
T 0
which is seen to be the average value of x(t). The remaining coefficients can be computed from
the following integrals:
T
2
an = x(t) cos nωt dt, for n = 1, 2, . . . (14.1.13)
T 0
T
2
bn = x(t) sin nωt dt, for n = 1, 2, . . . (14.1.14)
T 0
It can be seen that bn = 0 for n = 1, 2, 3, . . . for even symmetry. Similarly, for odd symmetry,
an = 0 for n = 0, 1, 2, 3, . . . . For half-wave symmetry, an = bn = 0 for n = 2, 4, 6, . . . so that
the series contains only the odd-harmonic components. For relatively smooth signals, the higher
harmonic components tend to be smaller than the lower ones. Discontinuous signals have more
significant high-frequency content than continuous signals.
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EXAMPLE 14.1.4
Consider the following periodic waveforms shown in Figure E14.1.4:
t
−T −D/2 0 D/2 T
(a)
−T/2 T/2
t
−T 0 T
−A
(b)
−T/2
t
−T 0 T
T/2
−A
(c)
t
−T −T/2 0 T/2 T
−A
(d)
t
−T −T/2 0 T/2 T
(e)
Figure E14.1.4 Periodic waveforms.
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(a) Rectangular pulse train

(b) Triangular wave
(c) Sawtooth wave
(d) Square wave
(e) Half-rectified sine wave
Identify the waveform symmetry and find expressions for the Fourier coefficients.
Solution
Waveform Symmetry a0 an or bn
DA 2A π Dn
(a) Rectangular pulse train Even an = sin n = 1, 2, 3, . . .
T πn T
8A
(b) Triangular wave Even and half-wave 0 an = 2 2 n = 1, 3, 5, . . .
π n
2A
(c) Sawtooth wave Odd 0 bn = n = 1, 2, 3, . . .
πn
4A
(d) Square wave Odd and half-wave 0 bn = n = 1, 3, 5, . . .
πn
A A
(e) Half-rectified sine wave None b1 =
π 2
2A
an = − n = 2, 4, 6, . . .
π(n2 − 1)
Spectral Analysis and Signal Bandwidth

Spectral analysis is based on the fact that a sinusoidal waveform is completely characterized by
three quantities: amplitude, phase, and frequency. By plotting amplitude and phase as a function
of frequency f (= ω/2π = 1/T ), the frequency-domain picture conveys all the information,
including the signal’s bandwidth and other significant properties about the signal that consists
entirely of sinusoids. The two plots together (amplitude versus frequency and phase versus
frequency) constitute the line spectrum of the signal x(t).
If x(t) happens to be a periodic signal whose Fourier coefficients are known, Equation
(14.1.11) can be rewritten as
∞
x(t) = a0 + An cos(nωt + φn ) (14.1.15)
n=1
where

bn
An = an2 + bn2 and φn = −arctan
an
The phase angles are referenced to the cosine function, in agreement with our phasor notation.
The corresponding phasor diagram of Fourier coefficients is shown in Figure 14.1.3.
Equation (14.1.15) reveals that the spectrum of a periodic signal contains lines at frequencies
of 0, f, 2f, and all higher harmonics of f, although some harmonics may be missing in particular
cases. The zero-frequency or dc component represents the average value a0, the components
corresponding to the first few harmonics represent relatively slow time variations, and the higher
harmonics represent more rapid time variations.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Figure 14.1.3 Phasor diagram of Fourier coefficients.
an
φn
bn
An
EXAMPLE 14.1.5
The rectangular pulse train of Figure E14.1.4(a) consists of pulses of height A and duration D.
Such pulse trains are employed for timing purposes and to represent digital information. For a
particular pulse train, A = 3 and the duty cycle D/T = 1/3.
(a) Find the Fourier-series expansion of the pulse train.
(b) Sketch the line spectrum of the rectangular pulse train when T = 1 ms.
Solution
(a) Using the solution of Example 14.1.4, we have for the particular pulse train:
DA 2A 2Dn 6 πn
a0 = = 1; an = sin = sin ; bn = 0
T πn T πn 3
Thus, the Fourier-series expansion results,
x(t) = 1 + 1.65 cos ωt + 0.83 cos 2ωt − 0.41 cos 4 ωt − 0.33 cos 5 ωt + . . .
Note that the terms corresponding to 3ω, 6ω, . . . are missing because an = 0 for n = 3,
6, . . . .
(b) T = 1 ms = 10−3 s and f = 103 Hz = 1 kHz. The line spectrum of the particular
rectangular pulse train is shown in Figure E14.1.5. As seen from the spectrum, most of
the time variation comes from the large-amplitude components below 6 kHz. The higher
frequency components have much smaller amplitudes, which account for the stepwise
jumps in the pulse train.
Amplitude Figure E14.1.5
f, kHz
0 1 2 3 4 5 6 7 8 9
Phase
0
−180°
--`,,,``,,`,```,``,`````,```,```-`-`
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Amplitude
AD
t f
−D/2 D/2 0 1/D 2/D 3/D
(a) (b)
Figure 14.1.4 Nonperiodic signal and its spectrum. (a) Single rectangular pulse. (b) Continuous amplitude
spectrum.
By letting T → ∞ for the rectangular pulse train of Figure E14.1.4(a), so that all pulses
vanish except the one centered at t = 0, we would obtain a single rectangular pulse, as shown in
Figure 14.1.4(a). Because f = 1/T → 0 when T → ∞, intuitively, the amplitude lines will
merge to form a continuous plot, as shown in Figure 14.1.4(b). Spectral analysis of nonperiodic
signals involves Fourier transform theory, which goes beyond the scope of this text. Smooth
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
curves, such as one in Figure 14.1.4(b), suggest that the signal energy is spread over a continuous
frequency range, rather than being concentrated in discrete sinusoidal components. Note that the
amplitude at f = 0 is equal to the net area DA of the nonperiodic signal.
When spectral peaks occur at or near f = 0, and their amplitude spectra become progressively
smaller as frequency increases, such waveforms are known as low-pass signals, for which there
exists a signal bandwidth W such that all significant frequency content falls within the range of
0 ≤ f ≤ W . The concept of signal bandwidth plays a significant role in signal-processing and
communication systems. Table 14.1.1 lists the nominal bandwidths of a few selected signals.
The approximate reciprocal relationship W ∼ = 1/D conveys the salient point that long pulses
have small bandwidths while short pulses have large bandwidths. This agrees qualitatively with
the rectangular pulse spectrum of Figure 14.1.4(b), although it ignores the components above
f = 1/D. In order to preserve the square corners of the rectangular pulse shape, we would have
to take W >> 1/D.
Filtering, Distortion, and Equalization

Frequency response and filters were discussed in Section 3.4. Any undesired waveform alteration
produced by a frequency-selective network is known as linear distortion. It is so designated to
distinguish it from the distortion caused by nonlinear elements. Let us now investigate filtering
and linear distortion from the point of view of spectral analysis.
TABLE 14.1.1 Lowpass Signal Bandwidths of Selected Signals
Signal Type Bandwidth
Telephone-quality voice 3 kHz

Moderate-quality audio 5 kHz
High-fidelity audio 20 kHz
Television video 4 MHz
Copyright OUP
Figure 14.1.5 shows a block diagram in which an arbitrary linear network characterized by its
ac transfer function H(jω) has an input signal x(t) yielding an output signal y(t). Note that H(jω)
is represented here in terms of the amplitude ratio and phase shift as a function of frequency f
given by |H (f )| = |H (j ω)| and θ(f ) = H (j ω), respectively, where ω is related to f through
the relation ω = 2πf .
If x(t) contains a sinusoidal component of magnitude A1 and phase φ 1 at frequency f 1, the
corresponding output component of the linear network will have amplitude |H (f1 )| A1 and phase
φ1 + θ (f1 ). If, on the other hand, the input should consist of several sinusoids given by

x(t) = An cos(2πfn t + θn ) (14.1.16)
n
By superposition, the steady-state response at the output will be

y(t) = |H (fn )| An cos [2πfn t + φn + θ(fn )] (14.1.17)
n
By letting fn = nf 1 with n = 0, 1, 2, . . . , periodic steady-state response due to a periodic signal

can be obtained.
Whether periodic or nonperiodic, the output waveform signal is said to be undistorted if the
output is of the form
y(t) = Kx(t − td ) (14.1.18)
That is to say, the output has the same shape as the input scaled by a factor K and delayed in time
by td. For distortionless transmission through a network it follows then that
|H (f )| = K and θ(f ) = −360°(td f ) (14.1.19)
which must hold for all frequencies in the input signal x(t). Thus, a distortionless network will
have a constant amplitude ratio and a negative linear phase shift over the frequency range in
question.
When a low-pass signal having a bandwidth W is applied to a low-pass filter (see Section
3.4) with bandwidth B, essentially distortionless output is obtained when B ≥ W . Figure 14.1.6
illustrates the frequency-domain interpretation of distortionless transmission.
The preceding observation is of practical interest because many information-bearing wave-
forms are low-pass signals, and transmission cables often behave like low-pass filters. Also notice
that unwanted components at f > W contained in a low-pass signal can be eliminated by low-pass
filtering without distorting the filtered output waveform.
If |H (f )| = K, one of the conditions given by Equation (14.1.19) for distortionless
transmission is not satisfied. Then the output suffers from amplitude or frequency distortion,
i.e., the amplitudes of different frequency components are selectively increased or decreased.
If θ (f ) does not satisfy the condition given in Equation (14.1.19), then the output suffers from
phase or delay distortion, i.e., different frequency components are delayed by different amounts
of time. Both types of linear distortion usually occur together.
The linear distortion occurring in signal transmission can often be corrected or reduced by
using an equalizer network. The concept is illustrated in Figure 14.1.7, in which an equalizer is
connected at the output of the transmission medium, such that
* *
|H (f )| *Heq (f )* = K and θ(f ) + θeq (f ) = −360°(td f ) (14.1.20)
x(t) y(t)
Figure 14.1.5 Linear network with input and output signals.
Linear network
|H( f )| ∠θ( f )
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Figure 14.1.6 Frequency-domain

interpretation of distortionless
Amplitude transmission when B ≥ W .
spectrum
f
0 W
H( f )
f
0 B
0 f
θ( f )
−360°td
x(t) y(t) z(t)

Figure 14.1.7 Transmission sys-
|H( f )| ∠θ( f ) |Heq( f )| ∠θeq( f ) tem with equalizer.
Transmission medium Equalizer
so that the equalized output signal is then z(t) = Kx(t − td ), i.e., undistorted, regardless of the
distortion in y(t). For example, for correcting electrical and acoustical frequency distortion, audio
equalizers in high-fidelity systems are used to adjust the amplitude ratio over several frequency
bands. Sometimes, as in audio systems, phase equalization is not that critical since the human
ear is not that sensitive to delay distortion. However, human vision is quite sensitive to delay
distortion. Equalizers are also applied whenever energy storage in a transducer, or some other
part of a signal-processing system, causes linear distortion.
14.2 MODULATION, SAMPLING, AND MULTIPLEXING

Modulation is the process whereby the amplitude (or another characteristic) of a wave is varied
as a function of the instantaneous value of another wave. The first wave, which is usually a
single-frequency wave, is called the carrier wave; the second is called the modulating wave.
Demodulation or detection is the process whereby a wave resulting from modulation is so operated
upon that a wave is obtained having substantially the characteristics of the original modulating
wave. Modulation and demodulation are then reverse processes.
The information from a signal x(t) is impressed on a carrier waveform whose characteristics
suit a particular application. If the carrier is a sinusoid, we will see that a phenomenon known
as frequency translation occurs. If, on the other hand, the carrier is a pulse train, the modulating
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14.2 MODULATION, SAMPLING, AND MULTIPLEXING 641
signal needs to be sampled as part of the modulation process. Frequency translation and sampling
have extensive use in communication systems. Both of these lend to multiplexing, which permits
a transmission system to handle two or more information-bearing signals simultaneously.
Frequency Translation and Product Modulation

The basic operation needed to build modulators is the multiplication of two signals. Whenever
sinusoids are multiplied, frequency translation takes place. Figure 14.2.1(a) shows a product
modulator, which multiplies the signal x(t) and a sinusoidal carrier wave at frequency fc to yield
xc (t) = x(t) cos 2πfc t (14.2.1)
Choosing x(t) to be a low-pass signal with bandwidth W << fc , Figure 14.2.1(b) depicts the
relationship between xc(t) and x(t). The modulated wave xc(t) can now be seen to have a bandpass
spectrum resulting from frequency translation, which will be explained later.
If x(t) contains a sinusoidal component Am cos 2π fmt, multiplication by a sinusoidal carrier
wave cos 2πfct with fc >> fm yields
Am Am
(Am cos 2πfm t) × (cos 2πfc t) = cos 2π(fc − fm )t + cos 2π(fc + fm )t (14.2.2)
2 2
Waveforms of the signal, the carrier wave, and the product, as well as their respective line
spectra, are shown in Figure 14.2.2. Notice that the low frequency fm has been translated to the
higher frequencies fc ± fm .
Next, let us consider an arbitrary low-pass signal x(t) with the typical amplitude spectrum
of Figure 14.2.3(a). The amplitude spectrum of the modulated wave xc(t) will now have two
sidebands (lower and upper sidebands), each of width W on either side of fc, as illustrated in
Figure 14.2.3(b). Thus, we have a signal that can be transmitted over a bandpass system with a
minimum bandwidth of
B = 2W (14.2.3)
which is twice the bandwidth of the modulating signal. This process is then known as double-
sideband modulation (DSB). Either the lower or the upper sideband may be removed by filtering so
as to obtain single-sideband modulation (SSB) with B = W, if the bandwidth needs to be conserved.
By choosing the carrier frequency fc at a value where the system has favorable characteristics,
the frequency translation by product modulation helps in minimizing the distortion and other
problems in system design.
xc(t)
x(t)
Ideal
multiplier
x(t) xc(t) 0 t
Information-bearing Modulated
input signal wave
cos 2πfct
Sinusoidal
carrier
wave 1/fc
(a) (b)
Figure 14.2.1 (a) Product modulator. (b) Waveforms.
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Am
Am cos 2πfm t
Signal
t
f
0 fm
cos 2πfc t 1
Carrier wave
t
f
0 fm fc
Am cos 2πfm t × cos 2πfc t
Am Am
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Product
2 2
f
0 fm fc − fm fc fc + fm
Figure 14.2.2 Frequency translation waveforms and line spectra.
Amplitude Amplitude
Lower Upper
sideband 2W sideband
f f
0 W 0 fc − W fc fc + W
(a) (b)
Figure 14.2.3 Amplitude spectra in double-sideband modulation (DSB). (a) Amplitude spectrum of low-
pass modulation signal. (b) Amplitude spectrum of bandpass modulated signal.
Now, in order to recover x(t) from xc(t), the product demodulator shown in Figure 14.2.4(a),
which has a local oscillator synchronized in frequency and phase with the carrier wave, can be
used. The input y(t) to the low-pass filter is given by
x(t) cos 2πfc t = x(t) cos2 2πfc t
1 1
= x(t) + x(t) cos 2π(2fc )t (14.2.4)
2 2
indicating that the multiplication has produced both upward and downward frequency translation.
In Equation (14.2.4), the first term is proportional to x(t), while the second looks like DSB at
carrier frequency 2fc. Then, if the low-pass filter in Figure 14.2.4(a) rejects the high-frequency
components and passes f ≤ W , the filtered output z(t) will have the desired form z(t) = Kx(t).
Copyright OUP
xc(t) y(t) Low-pass

Figure 14.2.4 (a) Product demodula-
filter
z(t) tor. (b) Spectrum prior to low-pass fil-
tering.
Synch
cos 2πfc t
Oscillator
(a)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
f
0 W 2fc
(b)
Sampling and Pulse Modulation

In most analog circuits, signals are processed in their entirety. However, in many modern electric
systems, especially those that convert waveforms for processing by digital circuits, such as digital
computers, only sample values of signals are utilized for processing. Sampling makes it possible
to convert an analog signal to discrete form, thereby permitting the use of discrete processing
methods. Also, it is possible to sample an electric signal, transmit only the sample values, and use
them to interpolate or reconstruct the entire waveform at the destination. Sampling of signals and
signal reconstruction from samples have widespread applications in communications and signal
processing.
One of the most important results in the analysis of signals is the sampling theorem, which
is formally presented later. Many modern signal-processing techniques and the whole family
of digital communication methods are based on the validity of this theorem and the insight it
provides. The idea leading to the sampling theorem is rather simple and quite intuitive. Let us
consider a relatively smooth signal x 1(t), which varies slowly and has its main frequency content
at low frequencies, as well as a rapidly changing signal x 2(t) due to the presence of high-frequency
components. Suppose we are to approximate these signals with samples taken at regular intervals,
so that linear interpolation of the sampled values can be used to obtain an approximation of the
original signals. It is obvious that the sampling interval for the signal x 1(t) can be much larger
than the sampling interval necessary to reconstruct signal x 2(t) with comparable distortion. This
is simply a direct consequence of the smoothness of the signal x 1(t) compared to x 2(t). Therefore,
the sampling interval for the signals of smaller bandwidths can be made larger, or the sampling
frequency can be made smaller. The sampling theorem is, in fact, a statement of this intuitive
reasoning.
Let us now look from another point of view by considering a simple switching sampler
and waveforms shown in Figure 14.2.5(a). Let the switch alternate between the two con-
tacts at the sampling frequency fs = 1/Ts . The lower contact of the switch is grounded.
Copyright OUP
fs
x(t)
x(t) D
xs(t) 2Ts 3Ts
t
−Ts 0 Ts
xs(t)
(a)
s(t)
1
x(t) xs(t) D
t
−Ts 0 Ts 2Ts 3Ts
s(t)
(b)
Figure 14.2.5 (a) Switching sampler. (b) Model using switching function s(t).
While the switch is in touch with the upper contact for a short interval of time D << Ts ,
and obtains a sample piece of the input signal x(t) every Ts seconds, the output sampled
waveform xs(t) will look like a train of pulses with their tops carrying the sample values of
x(t), as shown in the waveform in Figure 14.2.5(a). This process can be modeled by using
a switching function s(t), shown in the waveform of Figure 14.2.5(b), and a multiplier in
the form
xs (t) = x(t)s(t) (14.2.5)
shown in Figure 14.2.5(b). The periodic switching function s(t) is simply a rectangular pulse train
of unit height, whose Fourier expansion is given by
s(t) = a0 + a1 cos 2πfs t + a2 cos 2π(2fs ) t + . . . (14.2.6)
with a0 = D/Ts and an = (2/π n) sin (π Dn/Ts ) for n = 1, 2, . . . [see Figure 14.1.4(a)]. Using
Equation (14.2.6) in Equation (14.2.5), we get
xs (t) = a0 x(t) + a1 x(t) cos 2πfs t + a2 x(t) cos 2π(2fs ) t + . . . (14.2.7)
By employing the frequency-domain methods, one can gain insight for signal analysis and easily
interpret the results. Supposing that x(t) has a low-pass amplitude spectrum, as shown in Figure
14.2.6(a), the corresponding spectrum of the sampled signal xs(t) is depicted in Figure 14.2.6(b).
Taking Equation (14.2.7) term by term the first term will have the same spectrum as x(t) scaled by
the factor a0; the second term corresponds to product modulation with a scale factor a1 and carrier
frequency fs, so that it will have a DSB spectrum over the range fs − W ≤ f ≤ fs + W ; the
third and all other terms will have the same DSB interpretation with progressively higher carrier
frequencies 2fs, 3fs, . . . .
Note that provided the sampling frequency satisfies the condition
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Amplitude
Am
f
0 W
(a)
Amplitude
a0 Am a1Am /2 a2Am /2
f
0 W fs − W fs fs + W 2fs
(b)
Figure 14.2.6 (a) Spectrum of low-pass signal. (b) Spectrum of sampled signal.
fs ≥ 2W (14.2.8)
none of the translated components falls into the signal range of 0 ≤ f ≤ W , as seen from Figure
14.2.6(b). Therefore, if the sampled signal xs(t) is passed through a low-pass filter, all components
at f ≥ fs − W will be removed so that the resulting output signal is of the same shape as a0x(t),
where a0 is given by D/Ts . These observations are summarized in the following uniform sampling
theorem:
A signal that has no frequency components at f ≥ W is completely described by uni-
formly spaced sample values taken at the rate fs ≥ 2W . The entire signal waveform
can be reconstructed from the sampled signal put through a low-pass filter that rejects
f ≥ fs − W .
The importance of the sampling theorem lies in the fact that it provides a method of recon-
struction of the original signal from the sampled values and also gives a precise upper bound
on the sampling interval (or equivalently, a lower bound on the sampling frequency) needed
for distortionless reconstruction. The minimum sampling frequency fs = 2W is known as
Nyquist rate.
When Equation (14.2.8) is not satisfied, spectral overlap occurs, thereby causing unwanted
spurious components in the filtered output. In particular,* if any* component of x(t) originally at
f > fs /2 appears in the output at the lower frequency *fs − f * < W , it is known as aliasing. In
order to prevent aliasing, one can process the signal x(t) through a low-pass filter with bandwidth
Bp ≤ fs /2 prior to sampling.
The elements of a typical pulse modulation system are shown in Figure 14.2.7(a). The
pulse generator produces a pulse train with the sampled values carried by the pulse ampli-
tude, duration, or relative position, as illustrated in Figure 14.2.7(b). These are then known
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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x(t) Low-pass Pulse Transmission Pulse Low-pass

filter generator medium converter filter
(a)
x(t)
t
0 Ts 2Ts 3Ts 4Ts 5Ts
PAM
t
0
PDM
t
0
PPM
t
0 Ts 2Ts 3Ts 4Ts 5Ts
(b)
Figure 14.2.7 (a) Typical pulse modulation system. (b) Waveforms.
as pulse amplitude modulation (PAM), pulse duration modulation or pulse width modula-
tion (PDM or PWM), and pulse position modulation (PPM), respectively. At the output end,
the modulated pulses are converted back to sample values for reconstruction by low-pass
filtering.
EXAMPLE 14.2.1
In order to demonstrate aliasing, make a plot of the signal
x(t) = 3 cos 2π10t − cos 2π 30t

which approximates a square wave with W = 30 Hz. If the sample points are taken at
1 2 6
t = 0, , , ...,
60 60 60
corresponding to Ts = 1/(2W ), you can see that x(t) could be recovered from those samples.
However, if the sample points are taken at
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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1 2
t = 0, , , ...
40 40
corresponding to Ts = 1/(2W ) and fs < 2W , a smooth curve drawn through these points will
show the effect of aliasing.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Solution
The waveforms are sketched in Figure E14.2.1.
Figure E14.2.1
x(t) Aliased waveform
2
2 4
60 60
t
0 1 1 3 = 2 3 5 6 = 4
60 40 60 40 40 60 60 40
−2
Multiplexing Systems
A multiplexing system is one in which two or more signals are transmitted jointly over the
same transmission channel. There are two commonly used methods for signal multiplexing.
In frequency-division multiplexing (FDM), various signals are translated to nonoverlapping
frequency bands. The signals are demultiplexed for individual recovery by bandpass filtering
at the destination. FDM may be used with either analog or discrete signal transmission. Time-
division multiplexing (TDM), on the other hand, makes use of the fact that a sampled signal is
off most of the time and the intervals between samples are available for the insertion of samples
from other signals. TDM is usually employed in the transmission of discrete information. Let us
now describe basic FDM and TDM systems.
Figure 14.2.8(a) shows a simple FDM system which is used in telephone communication
systems. Each input is passed through a low-pass filter (LPF) so that all frequency components
above 3 kHz are eliminated. It is then modulated onto individual subcarriers with 4-kHz spacing.
While all subcarriers are synthesized from a master oscillator, the modulation is achieved with
single sideband (SSB). The multiplexed signal, with a typical spectrum as shown in Figure
14.2.8(b), is formed by summing the SSB signals and a 60-kHz pilot carrier. The bandpass filters
(BPFs) at the destination separate each SSB signal for product demodulation. Synchronization is
achieved by obtaining the local oscillator waveforms from the pilot carrier. Telephone signals are
often multiplexed in this fashion.
A basic TDM system is illustrated in Figure 14.2.9(a). Let us assume for simplicity that all
three input signals have equal bandwidths W. A commutator or an electronic switch subsequently
obtains a sample from each input every T s seconds, thereby producing a multiplexed waveform
with interleaved samples, as shown in Figure 14.2.9(b). Another synchronized commutator at the
destination isolates and distributes the samples to a bank of low-pass filters (LPFs) for individual
signal reconstruction. More sophisticated TDM systems are available in which the sampled values
are converted to pulse modulation prior to multiplexing and carrier modulation is included after
Copyright OUP
Master
oscillator
Frequency
synthesizer 60-kHz pilot
Frequency
BPF synthesizer
x1(t) SSB
LPF 60-kHz pilot
mod
x1(t)
64 kHz BPF Demod
x2(t) SSB Transmission 60–64 kHz 64 kHz

LPF Σ medium
mod
x2(t)
68 kHz BPF Demod
x3(t) SSB 64–68 kHz 68 kHz

LPF
mod
x3(t)
Input BPF Demod
signals 72 kHz
Output
68–72 kHz 72 kHz signals
(a)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Pilot
f , kHz
0 60 64 68 72
(b)
Figure 14.2.8 (a) Simple FDM system. (b) Typical spectrum of multiplexed signal with pilot.
multiplexing. Integrated switching circuits have made the TDM implementation much simpler
than FDM.
EXAMPLE 14.2.2
Find the transmission bandwidth required of a data telemetry system that is to handle three different
signals with bandwidths W 1 = 1 kHz, W 2 = 2 kHz, and W 3 = 3 kHz, by employing:
(a) FDM with DSB subcarrier modulation.
(b) TDM with pulse duration D = Ts /6.
Solution
(a) B ≥ 2W1 + 2W2 + 2W3 = 12kH z.

(b) fs ≥ 2W3 = 6 kHz, so B ≥ 1/D = 6fs ≥ 36 kHz.
Copyright OUP
14.3 INTERFERENCE AND NOISE 649
x1 x1s
LPF LPF x1
x2 Transmission x2s
LPF LPF x2
fs medium fs
x3 x3s
LPF LPF x3
Input Commutator Commutator Output
signals signals
(a)
x1(t)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
t
(b)
Figure 14.2.9 (a) Basic TDM system. (b) Multiplexed waveform.
14.3 INTERFERENCE AND NOISE

An information-bearing signal often becomes contaminated by externally generated interference
and noise and/or by internally generated noise. The demodulated message signal is generally
degraded to some extent by the presence of these distortions (attenuation, interference, and
noise) in the received signal. The fidelity of the received message signal is then a function
of the type of modulation, the strength of the additive noise, the type and strength of any
other additive interference, and the type of any nonadditive interference or noise. This section
only introduces some of the major causes of interference and noise, and touches upon some
methods of dealing with their effects in order to minimize the interference and suppress the
noise.
Interference may take several forms: ac hum, higher frequency pulses and “whistles,” or
erratic waveforms commonly known as static. Interfering signals can be seen to enter the system
primarily through the following mechanisms:
• Capacitive coupling, because of the stray capacitance between the system and an external
voltage
• Magnetic coupling, because of the mutual inductance between the system and an external
current
• Radiative coupling, because of electromagnetic radiation impinging on the system, partic-
ularly in the channel
• Ground-loop coupling, because of the currents flowing between different ground points
To minimize coupling from the inevitable sources, all exposed elements are usually enclosed
within conducting shields, which offer low-resistance paths to ground. When held at a common
potential, these shields are quite effective in reducing most types of interference. However, low-
frequency magnetic coupling can induce unwanted current flow through the shields themselves.
Then the shield connection has to be interrupted to avoid a closed-loop current path. An additional
Copyright OUP
layer of special magnetic shielding material may become necessary sometimes in extreme cases
of magnetic-coupling interference. The grounding terminals, the equipment cases, and the shields
are generally tied together at a single system ground point so as to prevent ground-loop current-
coupling interference.
The transducer in some cases may have a local ground that cannot be disconnected. In such
a case, a separate ground strap (braided-wire straps used because of their low inductance) is used
to connect the local ground and the system ground point. The shield is also disconnected from
the amplifier so as to prevent ground-loop current through the shield. Because the ground strap
has nonzero resistance, any stray current through the strap will cause an interference voltage vcm
known as common-mode voltage since it appears at both the transducer and the shield terminals.
vcm is generally quite small; however, when the information-bearing signal voltage itself is rather
small, the common-mode voltage may pose a problem, which can be eliminated by using the
differential amplifier, as shown in Figure 14.3.1. The analysis with the virtual-short model of the
op-amp reveals that
vout = K(v2 − v1 ) (14.3.1)
amplifying the difference voltage v2 − v1 . With reasonable assumptions that Rs << R1 and Rt <<
R2, we have v1 ∼
= vcm and v2 ∼ = x + vcm , so that
vout = K [(x + vcm ) − vcm ] = Kx (14.3.2)
in which vcm has been eliminated as desired. Such an op-amp circuit is also known as an
instrumentation or transducer amplifier.
Any interference at frequencies outside the signal band can be eliminated by appropriate
filtering. However, in order to combat interference within the signal band (after proper shielding
and grounding), a notch filter is sometimes used to avoid the bothersome interference at a single
frequency f 0. Figure 14.3.2 illustrates the point: Part (a) shows the composite amplitude spectrum
including the single-frequency interference; part (b) depicts the amplitude ratio of the notch filter.
The notch-filtering technique does, of course, introduce some inevitable signal distortion, and
such filtering should precede amplification to prevent possible saturation of the amplifier due to
the interference.
RF = KR1
Shield
Rs v1 R1
−
vout
+ +
v2
x(t) Rt R2
Transducer
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
R3 = KR2
vcm +
Differential
amplifier
Model of a transducer
with common-mode voltage
Figure 14.3.1 Differential amplifier to eliminate the common-mode voltage.
Copyright OUP
Figure 14.3.2 (a) Composite am-

Amplitude Interference plitude spectrum including single-
spectrum frequency interference. (b) Amplitude
ratio of notch filter.
Signal
f
0 f0
(a)
|H( f )|
f
0 f0
(a)
Noise
In any communication system there are usually two dominant factors that limit the performance
of the system:
1. Additive noise, generated by electronic devices that are used to filter and amplify the
communication signal.
2. Signal attenuation, as the signal travels through a lossy channel.
A simple mathematical model of a channel with attenuation and additive noise is shown in
Figure 14.3.3. If the transmitted signal is s(t), the received signal is given by
r(t) = αs(t) + n(t) (14.3.3)
where α < 1, and n(t) represents an additive random noise process corrupting the transmitted
signal. Physically, the additive noise may arise from electronic components and amplifiers at the
Channel
Transmitted Received signal

signal s(t) r(t) : α s(t) + n(t)
Attenuation α Noise n(t)
Figure 14.3.3 Mathematical model of channel with attenuation and additive noise.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
receiver of the communication system, or from interference encountered in transmission as in

the case of radio-signal transmission. The effect of signal attenuation is to reduce the amplitude
of the desired signal s(t) and, thus, to render the information-bearing signal more vulnerable to
additive noise.
Signal attenuation in many channels can be offset by using amplifiers to boost the signal
level during transmission. However, the amplifier also introduces additive noise in the process
of amplification, thereby corrupting the signal. The additional noise must also be taken into
consideration in the design of the communication system.
Any conductive two-terminal device is characterized generally as lossy, with some resistance
R. A resistor, which is at a temperature τ above absolute zero, contains free electrons that exhibit
random motion and, thus, result in a noise voltage across the terminals of the resistor. Such a noise
voltage is known as thermal noise. If the noise is introduced primarily by electronic components
and amplifiers at the receiver, it may be characterized as thermal noise.
In general, any physical resistor or lossy device can be modeled by a noise source in series
with a noiseless resistor, as shown in Figure 14.3.4. The noise source is usually characterized as a
sample function of a random process. Since random processes involving probability and random
variables are outside the scope of this text, we will resort to simpler explanations. Figure 14.3.5
Figure 14.3.4 Physical resistor or lossy device. (a) Noiseless resistor. (b) Noise-
less resistor in series with a noise source.
R R
n(t)
(a) (b)
n(t)
nrms
0 t
(a)
Noise power spectrum
f
0 1012 Hz
(b)
Figure 14.3.5 Thermal or white noise. (a) Typical waveform. (b) Typical power spectrum.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
(a) illustrates a typical thermal noise waveform n(t). In view of the unpredictable behavior, since
the average value of n(t) may be equal to zero, a more useful quantity is the rms value nrms so that
the average noise power is given by
N = n2rms /R, if nrms is noise voltage (14.3.4)
or
N = n2rms R, if nrms is noise current (14.3.5)
The spectrum of thermal noise power is uniformly spread over frequency up to the infrared region
around 1012 Hz, as shown in Figure 14.3.5(b). Such a distribution indicates that n(t) contains all
electrical frequencies in equal proportion, and an equal number of electrons is vibrating at every
frequency. By analogy to white light, which contains all visible frequencies in equal proportion,
thermal noise is also referred to as white noise.
The constant η in Figure 14.3.5(b) stands for the noise power spectral density, expressed in
terms of power per unit frequency (W/Hz). Statistical theory shows that
η = kT (14.3.6)
−23
where k is the Boltzmann constant given by 1.381 × 10 J/K and T is the source temperature
in kelvins. Equation (14.3.6) suggests that a hot resistance is noisier than a cool one, which is
compatible with our notion of thermally agitated electrons. At room temperature T0 ∼ = 290 K
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(17° C), η0 works out as 4 × 10−21 W/Hz.

When we employ amplifiers in communication systems to boost the level of a signal, we are
also amplifying the noise corrupting the signal. Because any amplifier has some finite passband,
we may model an amplifier as a filter with frequency response characteristic H(f ). Let us evaluate
the effect of the amplifier on an input thermal noise source.
Thermal
Amplifier
noise Load
H( f )
source
Matched Matched
(a)
Power
Noiseless spectrum
N amplifier Nout
η
G, B
N = ηB
n(t) nout(t)
R RL
0
B
Bandwidth
fl fu
Lower Upper
cutoff cutoff
(b) (c)
Figure 14.3.6 Thermal noise converted to amplifier and load. (a) Matched block diagram. (b) Circuit
representing thermal noise at amplifier input. (c) Power spectrum.
Copyright OUP
Figure 14.3.6(a), in block diagram form, illustrates a thermal noise source connected to
a matched two-port network having frequency response H (f ) and the output of the network
connected to a matched load. Figure 14.3.6(b) shows a thermal noise source represented by a
resistance R connected to an amplifier with a matched input resistance. Presuming the amplifier
to be noiseless, with power gain G and bandwidth B, the output noise power is
Nout = GN = GηB (14.3.7)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
where N = ηB represents the source noise power [the area under the power-spectrum curve
falling within the passband, as shown in Figure 14.3.6(c)] accepted by the amplifier as input. The
rms noise voltage for a thermal source connected to a matched resistance is then given by
√
ηrms = RkT B (14.3.8)
The open-circuit voltage would be twice this value.
Amplifier noise arises from both thermal sources (resistances) and nonthermal sources
(semiconductor devices). Although nonthermal noise is not related to physical temperature and
does not necessarily have a uniform spectrum like that of thermal noise, one still refers to an
amplifier’s noise temperature Ta, for convenience, as a measure of noisiness referred to the input.
The model of a noisy amplifier is shown in Figure 14.3.7(a) with input noise N = ηB = kT B
from a source at temperature T, and the output power given by
Nout = GN + Na = GN + GkTa B = Gk(T + Ta )B (14.3.9)
where Na = GkTa B is the output noise power caused only by the amplifier, G is the power gain
of the amplifier, and B is the bandwidth of the amplifier. Note that the amplifier noise Na is added
to the amplified source noise to yield the output power in Equation (14.3.9). If T = T0 (i.e., room
temperature), then Nout ∼ = Na , and the amplifier noise dominates the source noise, which is a
common occurrence. When Ta >> T 0, the amplifier is very noisy, although not physically hot.
Figure 14.3.7(b) depicts the variation of noise temperature with frequency for a nonthermal
source. Several phenomena lumped together under the term one-over-f (1/f ) noise lead to the
pronounced low-frequency rise in Figure 14.3.7(b). Such 1/f noise is produced by transistors
and certain transducers, such as photodiodes and optical sensors.
Signals in Noise
Let us now consider a weak information signal that is to be amplified by a noisy amplifier.
The signal-to-noise ratio (SNR), usually expressed in decibels, becomes an important system
performance measure. It is given by
Power
spectrum
1 noise
f
Nout = GN + Na
N = kTB = Gk(T + Ta)B
G, B, Ta f
(b)
(a)
Figure 14.3.7 (a) Model of a noisy amplifier. (b) Power spectrum of nonthermal noise.
Copyright OUP
Pout GPin Pin

SNR = = = (14.3.10)
Nout Gk(T + Ta )B k(T + Ta )B
where the amplified signal power is Pout = GPin in the numerator, which includes source and
amplifier noise given by Equation (14.3.9); Pin is the average power of the input signal; and the
denominator N out is the total output noise power given by Equation (14.3.9). Notice that the am-
plifier’s power gain G does not appear in the final result of the SNR. A large SNR indicates that the
signal is strong enough to mask the noise and possibly make the noise inconsequential. For exam-
ple, with SNR ≥ 20 dB, intelligible voice communication results; otherwise, “static” in the voice
signal; with SNR ≥ 50 dB, noisefree television image results; otherwise, “snowy” TV picture.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
For a good system performance, Equation (14.3.10) suggests a large value of Pin and/or small
values for T + Ta and B. However, one should be reminded here that the amplifier’s bandwidth
B should not be less than the signal bandwidth W. That simply means that with large-bandwidth
signals, one would expect noise to be more troublesome.
Frequency translation can be used effectively to reduce the effect of 1/f noise by putting the
signal in a less noisy frequency band. Figure 14.3.8(a) shows the schematic implementation with
product modulation and demodulation, whereas Figure 14.3.8(b) illustrates the noise reduction in
terms of the areas under the noise power curve. The two multipliers in Figure 14.3.8(a) are normally
implemented by using a pair of synchronized switches. It turns out that the product modulation
requires bandwidth B = 2W , and the synchronized product demodulation doubles the final SNR.
Another way of improving the SNR is by preemphasis and deemphasis filtering. Generally,
for low-frequency components of the message signal FM (frequency modulation) performs better,
and for high-frequency components PM (phase modulation) is a better choice. Hence, if one can
design a system that performs FM for low-frequency components of the message signal, and
Amplifier with 1/f noise

Kx(t) Low-pass
filter
Synchronized
fc switches
(a)
Power
spectrum
f
0 W fc − W fc fc + W
(b)
Figure 14.3.8 (a) Schematic arrangement with frequency translation to reduce
the effect of 1/f noise. (b) Noise power spectrum.
Copyright OUP
works as a phase modulator for high-frequency components, a better overall system performance
results compared to each system (FM or PM) alone. This is the idea behind preemphasis and
deemphasis filtering techniques.
Figure 14.3.9(a) shows a typical noise power spectrum at the output of the demodulator in the
frequency interval |f | < W for PM, whereas Figure 14.3.9(b) shows that for FM. The preemphasis
and deemphasis filter characteristics (i.e., frequency responses) are shown in Figure 14.3.10.
Due to the high level of noise at high-frequency components of the message in FM, it is
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
desirable to attenuate the high-frequency components of the demodulated signal. This results in
a reduction in the noise level, but causes the higher frequency components of the message signal
to be attenuated also. In order to compensate for the attenuation of the higher components of the
message signal, one can amplify these components at the transmitter before modulation. Thus, at
the transmitter we need a high-pass filter, and at the receiver we must use a low-pass filter. The
net effect of these filters is to have a flat frequency response. The receiver filter should therefore
be the inverse of the transmitter filter. The modulator filter, which emphasizes high frequencies,
is called the preemphasis filter, and the demodulator filter, which is the inverse of the modulator
filter, is called the deemphasis filter.
If the signal in question is a constant whose value we seek, as is the case sometimes in simple
measurement systems, the measurement accuracy will be enhanced by a low-pass filter with the
smallest bandwidth B. Low-pass filtering, in a sense, carries out the operation of averaging, since
a constant corresponds to the average value (or dc component) and since noise usually has zero
average value. However, some noise will get through the filter and cause the processed signal
z(t) to fluctuate about the true value x, as shown in Figure 14.3.11. Allowing any sample to fall
somewhere between x − ε and x + ε, the rms error G is defined by
Noise-power Figure 14.3.9 Noise power spectrum at de-

spectrum modulator output. (a) In PM. (b) In FM.
N0
Ac2
f
−W W
(a)
Noise-power
spectrum
f
−W W
(b)
Copyright OUP
f2 Figure 14.3.10 (a) Preemphasis

|Hp( f )| = 1+ filter characteristic. (b) Deempha-
f02
sis filter characteristic.
f
−5f0 − 4f0 −3f0 −2f0 −f0 0 f0 2f0 3f0 4 f0 5f0
(a)
1
|Hd ( f )| =
f2
1+
f02
1
f
−5f0 − 4f0 −3f0 −2f0 −f0 0 f0 2f0 3f0 4 f0 5f0
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(b)
z(t) Figure 14.3.11 Constant signal x

with noise fluctuations.
x+ε
z(t2) z(t3)
x
x−ε
z(t1)
t
t1 t2 t3
x
G= √ (14.3.11)
Pout /Nout
By taking M different samples of z(t), the arithmetic average can be seen to be
1
zav = (z1 + z2 + . . . + zM ) (14.3.12)
M
If the samples are spaced in time by at least 1/B seconds, then the noise-induced errors tend to
cancel out and the rms error of zav becomes
√
εM = ε/ M (14.3.13)
This averaging method amounts to reducing the bandwidth to B/M.
When the signal in question is a sinusoid whose amplitude is to be measured, averaging
techniques can also be used by utilizing a narrow bandpass filter, or a special processor known
Copyright OUP
as a lock-in amplifier. For extracting information from signals deeply buried in noise, more
sophisticated methods based on digital processing are available.
EXAMPLE 14.3.1
A low-noise transducer is connected to an instrumentation system by a cable that generates thermal
noise at room temperature. The information-bearing signal has a bandwidth of 6 kHz. The signal
power delivered is Pin = 120 pW. Evaluate the condition on the amplifier noise temperature Ta
such that the signal-to-noise ratio (SNR) is greater than or equal to 50 dB.
Solution
Applying Equation (14.3.10) with T = T 0,

Pout Pin Pin 120 × 10−12
SNR = = = = ≥ 105
Nout k(T + Ta )B kT0 1 + Ta
B 4 × 10 −21 1 + T0 6 × 10
Ta 3
T0
Hence,
Ta ≤ 49T0
This condition can easily be satisfied in the case of a well-designed amplifier.

• Basic ideas of analog and digital communication systems.
• Constructing the line spectrum of a periodic signal from its Fourier-series expansion.
• Conditions for distortionless transmission.
• Sketching spectra at various points in a system using product modulation and filtering.
• Conditions under which a signal can be sampled and then reconstructed from a pulse-
modulated waveform.
• Basic notions of multiplexing systems.
• Causes of interference and noise, and techniques for minimizing their effects.
Antinoise Systems—Noise Cancellation

Traditionally sound-absorbing materials have been used quite effectively to reduce noise levels in
aircraft, amphitheaters, and other locations. An alternate way is to develop an electronic system
that cancels the noise. Ear doctors and engineers have successfully developed ear devices that
will nearly eliminate the bothersome and irritating noise (so-called tinnitus) experienced by
patients suffering from Ménière’s disease. For passengers in airplanes, helicopters, and other
flying equipment, a proper headgear is being developed in order to eliminate the annoying noise.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
PROBLEMS 659
Applications could conceivably extend to people residing near airports and bothered by airplane
takeoffs and landings. For industrial workers who are likely to develop long-term ill effects due
to various noises they may be subjected to in their workplace, and even for persons who are
irritated by the pedestrian noise levels in certain locations, antinoise systems that nearly eliminate
or nullify noise become very desirable.
Figure 14.5.1 illustrates in block-diagram form the principle of noise cancellation as applied
to an aircraft carrying passengers. The electric signal resulting after sampling the noise at the
noise sources is passed through a filter whose transfer function is continuously adjusted by a
special-purpose computer to match the transfer function of the sound path. An inverted version
of the signal is finally applied to loudspeakers, which project the sound waves out of phase with
those from the noise sources, nearly canceling the noise. Microphones on the headrests monitor
the sound experienced by the airline passengers so that the computer can determine the proper
filter adjustments.
Signal processing, which is concerned with manipulating signals to extract information and
to use that information to generate other useful electric signals, is indeed an important and far-
reaching subject.
Inverted signal version Sound waves

of the transfer function nearly cancel those
of the sound path from noise sources
applied to loudspeakers
Noise Adaptable
source filter
Microphone near
sources of noise Loudspeakers
such as located in
engines and propellers passenger
(noise sampled before Computer cabin area
entering passenger area)
Microphones
(located on passenger headrests)
monitor sound level
Figure 14.5.1 Block diagram of antinoise system to suppress the noise in an aircraft.
PROBLEMS
14.1.1 (a) A rectangular pulse is denoted by R(t) and (b) The sinc signal is given by
' sinπt
defined as t = 0
 sinc(t) = πt ,
 1 1 1, t =0
 1, − <t <
R(t) = 2 2
 1
 2, t = ± 21
Sketch the waveform and comment on its
0, otherwise
salient features.
Sketch the signal. Also express it in terms of
unit-step signals. (c) The sign or signum signal is represented by
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP

 1, t >0 1 α+T0
−j 2π Tn t an bn
sgn(t) = −1 xn = x(t)e 0 dt = −j
t <0 T0 2 2
 α
0, t =0 α+T0
2 n
an = x(t) cos 2π t dt
which can be expressed as the limit of the T0 α T0
signal xn(t) defined by
 −1/n 2 α+T0
n
e , t >0 bn = x(t) sin 2π t dt
T0 α T0
xn (t) = −e1/n , t <0
 1
0, t =0 |xn | = a 2 + bn2
2 n
as n → ∞. Sketch the waveform as the limit
bn
xn = −arctan
of xn(t).
an
*14.1.2 A large number of building blocks in a commu- in which the parameter α in the limits of the
nication system can be modeled by LTI (linear integral is arbitrarily chosen as α = 0 or α =
time-invariant) systems, for which the impulse −T0 /2, for convenience.
response completely characterizes the system.
(a) Show that the Fourier-series representation
Consider the system described by
t of an impulse train is given by
+∞
+∞

y(t) = x(τ ) dτ 1 j 2π Tn t
−∞ x(t) = δ(t − nT0 ) = e
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
n=−∞
T0 n=−∞
which is called an integrator. Investigate whether
the system is LTI by finding its response to x(t − Also sketch the impulse train.
t 0). (b) Obtain the Fourier-series expansion for the
14.1.3 For a real periodic signal x(t) with period T 0, signal x(t) sketched in Figure P14.1.3 with
three alternative ways to represent the Fourier T0 = 2, by choosing α = − 1/2.
series expansion are: 14.1.4 (a) Show that the sum of two discrete periodic
+∞
j 2π n
t signals is periodic.
x(t) = xn e T0
−∞ (b) Show that the sum of two continuous peri-

∞
odic signals is not necessarily periodic; find
a0 n the condition under which the sum of two
= + an cos 2π t
2 T0 continuous periodic signals is periodic.
n=1
14.1.5 Classify the following signals into even and odd
n
+ bn sin 2π t signals:
T0  −t
∞
(a) e , t >0
n
= x0 + 2 |xn | cos 2π t + xn
x1 (t) = −e−t , t <0
T0 
n=1 0, t =0
where the corresponding coefficients are
(b) x2 (t) = e−|t|
obtained from
Figure P14.1.3
1
1 3 5
−2 −1 2 2 2
t
−5 −3 −1 1 2
2 2 2
−1
Copyright OUP
PROBLEMS 661
(c) 14.1.12 For real, even, and periodic functions with period
' t
t = 0 T 0, the Fourier-series expansion can be expressed
x3 (t) = |t| ,
0, t =0 as
∞
a0 n
x(t) = + an cos 2π t
*14.1.6 For the following neither even nor odd signals, 2
n=1
T0
find the even and odd parts of the signals.
where
(a) α+T0
' an =
2 n
x(t) cos 2π t
t, t ≥0 dt
x4 (t) = T0 α T0
0, t <0
Determine an for the following signals:
(b) x 5(t) = sin t + cos t (a) x(t) = |cos 2πf0 t|, full wave rectifier out-
put.
14.1.7 Classify the following signals into energy-type
or power-type signals, and determine the energy (b) x(t) = cos 2πf0 t + |cos 2πf0 t|, half-wave
or power content of the signal. rectifier output.
*14.1.13 For real x(t) given by Equation (14.1.11), identify
(a) x1 (t) = e−t cos t u−1 (t)
the even and odd parts of x(t).
(b) x2 (t) = e−t cos t 14.1.14 Three alternative ways of representing a real peri-
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(c) odic signal x(t) in terms of Fourier-series expan-
 sion are given in Problem 14.1.3. Determine the
 1, t >0
expansion coefficients xn of each of the periodic
x3 (t) = sgn(t) = −1, t <0
 signals shown in Figure P14.1.14, and for each
0, t =0 signal also determine the trigonometric Fourier-

Note: eax cos2 x dx = 1
4+a 2
[(a cos2 x+ series coefficients an and bn.
sin 2x) + a2 ]eax . 14.1.15 Certain waveforms can be viewed as a combi-
nation of some other waveforms for which the
14.1.8 (a) Based on Example 14.1.3, comment on Fourier coefficients are already known. Exam-
whether x(t) = A cos 2πf 1t + B 2πf 2t is ple 14.1.4 shows some periodic waveforms for
an energy- or a power-type signal. which the coefficients a0, an, and bn are given by
Equations (14.1.12) through (14.1.14), respec-
(b) Find its energy or power content for f 1 = f 2
tively. Use those to find the nonzero Fourier-
and f 1 = f 2.
series coefficients for the waveforms given in
14.1.9 For the power-type signals given, find the power Figure P14.1.15.
content in each case. 14.1.16 Determine the bandwidth W from two criteria, (i)
An < (An )max /10, for nf1 > W , and (ii) An <
(a) x(t) = Aej (2πf0 t+θ ) .
(An )max /20, for nf1 > W , for the following
(b) x(t) = u−1 (t), the unit-step signal. cases. (Note that A stands for amplitude.)
(a) Waveform of Figure E14.1.4(a), with A =
14.1.10 Show that the product of two even or two odd
π, D = 0.25 µs, and T = 0.5 µs.
signals is even, whereas the product of an even
and an odd signal is odd. (b) Waveform of Figure E14.1.4(b), with A =
π 2 and T = 2.5 µs.
14.1.11 The triangular signal is given by
 (c) Waveform of Figure E14.1.4(d), with A = π
 t + 1, −1 ≤ t ≤ 0 and T = 10 ms.
S(t) = −t + 1, 0≤t ≤1
 (d) Waveform of Figure E14.1.4(e), with A = π
0, otherwise
and T = 800 µs.
(a) Sketch the triangular pulse. 14.1.17 Consider the rectangular pulse train x(t) of Figure
, E14.1.4(a), with A = 2 and D = T/2. Let v(t) =
(b) Sketch x(t) = +∞ n=−∞ S(t − 2n). x(t) − 1.
,+∞
(c) Sketch x(t) = n=−∞ (−1)n S(t − n). (a) Sketch x(t) and v(t).
Copyright OUP
x(t)
x(t)
1
e−t
1
t t
−T T 2T −T T
−1
(a) (b)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
x(t) x(t)
1
1
t t
T T T T T 2T T
− −
(c) 2 4 4 2 (d) 3 3
x(t) x(t)
1 2
t 1
−T −
T T T
2 4 4 2
−1 t
−T −
2T −T T 2T T
3 3 3 3
(e) (f)
Figure P14.1.14
(b) Using the result of Figure E14.1.4(a), find + cos(2π3t + 180°), |H (f )| = 1, and constant
the Fourier coefficients of v(t). phase shift θ(f ) = −90°. Sketch x(t) and y(t).
*14.1.18 The waveforms of Figure E14.1.4(b) and (c) are
14.1.20 The frequency response of a transmission system
given to have A = π and T = 0.2 ms.
is given by
(a) For 0 ≤ f ≤ 30 kHz, sketch and label the 1
amplitude spectra. |H (f )| = ;
1 + (f/fco )2
(b) For An < A1 /5 for all nf1 < W (where A f
stands for amplitude), determine the value of θ(f ) = −tan−1
fco
W in each case.
where fco = ωco /2π = 5 kHz. In order to satisfy
14.1.19 Consider Figure 14.1.5, with x(t) = 3 cos 2πt Equation (14.1.20), over the range of 0 ≤ f ≤
Copyright OUP
PROBLEMS 663
Figure P14.1.15
3
2
t
0 T/2 T
−2
−3
(a)
4
−T/4
t
−T/2 0 T/4 T/2
−4
(b)
t
0 T/2 T
−6
(c)
10 kHz, with K = 1, find and sketch the required 14.2.1 is given by x(t) = 8 cos 2π 3000t + 4
equalizer characteristics. cos 2π7000t. The frequency of the carrier wave
14.1.21 The frequency response of a high-pass transmis- is 6 kHz. Sketch the amplitude line spectrum of
sion system is given by the modulated wave xc(t).
f/fco *14.2.3 Consider the following system with x(t) = 12 cos
|H (f )| = ;
1 + (f/fco )2 2π100t + 4 cos 2π300t and two ideal filters as
shown in Figure P14.2.3. Find xa(t) and xb(t).
θ (f ) = 90° − tan−1 (f/fco )
14.2.4 Consider the product modulator of Figure
with fco = ωco /2π = 100 Hz. If x(t) is a 14.2.4(a), where the oscillator generates
triangular wave of Figure E14.1.4(b), with A = cos[2π(fc +?f )t +?φ] in which ?f and ?φ are
π 2 /8 and T = 25 ms, obtain an approximate synchronization errors. Find z(t) produced by the
expression for the periodic steady-state response following inputs, when fm = 1 kHz, ?f = 200
y(t). See Figure 14.1.5. Hz, and ?φ = 0:
14.2.1 (a) Let x(t) = 12 cos 2π100t + 8 cos 2π150t,
and xc(t) = x(t) cos 2πfct, where fc = 600 (a) DSB input xc (t) = 4 cos 2πfm t cos 2πfc t.
Hz. Sketch the amplitude spectrum. (b) Upper-sideband SSB input xc (t) = 2 cos
(b) List all the frequencies in the product xc(t) 2π(fc + fm )t.
cos 2π500t, where x c(t) is given in part (a). (c) Lower-sideband SSB input xc (t) = 2 cos
14.2.2 The input to the product modulator of Figure 2π(fc − fm )t.
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14.2.5 Repeat Problem 14.2.4 when fm = 1 kHz, ?f = (a) Find the maximum number of voice signals
0, and ?φ = 90°. with W = 4 kHz that can be multiplexed.
14.2.6 (a) Consider Figure 14.2.5, in which the signal (b) Repeat part (a) with the additional constraint
to be sampled is x(t) = 18 cos 2π20t + 12 that the TDM waveform be off for at least
cos 2π60t. With fs = 100 and D = Ts/2, for 50% of the time.
0 ≤ f ≤ 2fs , sketch the amplitude line 14.3.1 An amplifier has a gain of 50 dB, a bandwidth
spectrum of xs(t). of 9 MHz, and a noise temperature Ta = 25T 0,
(b) Then find the signal y(t) that would be re- where T 0 is the room temperature, 290 K. Find
constructed by an ideal low-pass filter that the output noise power and rms voltage across a
rejects all f > fs /2. 100-- load resistor when the source temperature
14.2.7 (a) The continuous amplitude spectrum of the T = T 0.
input to a switching sampler (Figure 14.2.5) *14.3.2 If the signal in Example 14.3.1 has a bandwidth of
is shown in Figure P14.2.7. For 0 ≤ f ≤ 600 kHz, determine Pout/N out assuming a noise-
100, with fs = 70 and D = Ts/4, sketch the less amplifier. Then check to see whether it is
resulting spectrum of xs(t). possible to obtain Pout/N out ≥ 105.
(b) Suggest how x(t) can be reconstructed from 14.3.3 A simple RC filter yields |H (ω)|2 = 1/[1 +
xs(t). (ω/ωco )2 ], whereas a more sophisticated and rel-
14.2.8 PDM and PPM (see Figure 14.2.7) have the ad- atively more expensive Butterworth filter gives
vantage of being immune to nonlinear distortion, |H (ω)|2 = 1/[1 + (ω/ωco )4 ]. Either of these
because the pulse is either on or off. However, in can be used to reduce the hum amplitude. Let
exchange, the transmission bandwidth must be an information signal with significant frequency
B ≥ 1/D >> W , which is needed to accommo- content for f ≤ 30 Hz be contaminated by ac
date pulses with duration D << Ts ≤ 1/(2W ). hum at 120 Hz. The contaminated signal is then
Let D be the pulse duration of the PPM waveform applied to a low-pass filter to reduce the hum
in Figure 14.2.7. Let the maximum position shift amplitude by a factor of α. For (i) α = 0.25,
be ±?. For ? = 2D and fs = 20 kHz, find the and (ii) α = 0.1, determine the required cutoff
maximum allowed value of D and the minimum frequency f co for (a) the RC filter, and (b) the
required transmission bandwidth. Butterworth filter, and suggest the filter to be used
in each case.
*14.2.9 The TDM system of Figure 14.2.9 has a trans-
mission bandwidth B = 250 kHz.
x(t) Ideal filter A Ideal filter B x b(t)

which rejects all which rejects all
f < 800 f > 1200
cos 2πfa t = cos 2π800t cos 2πfb t = cos 2π1200t
Figure P14.2.3
Amplitude Figure P14.2.7
20
f
0 40 60
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PROBLEMS 665
14.3.4 (a) The transfer function of a notch filter is given 14.3.8 A signal (with P = 1 µW and B = 250 kHz)
by H (j ω) = (100 + j ω − ω2 )/(10 + j ω)2 . contaminated by white noise at noise temperature
Sketch H dB versus ω. T = 2T 0 is applied to an amplifier. Obtain the
(b) A notch filter centered at f0 = ω0 /2π can be condition on Ta such that Pout/N out ≥ 80.8 dB.
formed by using a resonant circuit arranged 14.3.9 The noise figure of an amplifier is given by F =
such that 1 + Ta /T0 . Express the output signal-to-noise
j Q(ω/ω0 − ω0 /ω) ratio in terms of F, input noise power N, and
H (j ω) = input noise temperature T. See how the result is
1 + j Q(ω/ω0 − ω0 /ω)
simplified when T = T0 .
Investigate |H (f )| at f = 0 and f = ∞;
14.3.10 A system for measuring the constant signal value
also at fl = f0 (1 − 1/(2Q), and fu = f 0(1 +
x has Pout/N out = 40 dB and B = 8 Hz. In order
1/(2Q), for Q >> 1.
√ √ to obtain an accuracy of ±0.2%, how long must
(c) With ω0 = 1/ LC and Q = (1/R) L/C, the output be observed?
show that a series RLC circuit can perform 14.3.11 An amplifier has a noise equivalent bandwidth B
as a notch filter when the output voltage is = 25 kHz and a maximum available power gain
taken across L and C. of G = 30 dB. If its output noise power is 108kT 0,
(d) For the purpose of rejecting 1-kHz interfer- determine the effective noise temperature and the
ence, in order to get fl = 980 Hz and fu = noise figure (given by F = 1 + Ta /T0 ). Assume
1020 Hz, find the values of L and C of the the input noise source temperature to be T 0.
series RLC circuit with R = 50 -. *14.3.12 The overall noise figure of a cascade of K am-
(e) Now consider a tuned circuit in which R is plifiers with gains Gk and corresponding noise
connected in series with a parallel combi- figures Fk, 1 ≤ k ≤ K, is
nation of L and C, and the output √ voltage
is taken across R. With = 1/ LC and F2 − 1 F3 − 1
√ ω0 F = F1 + + + ...
Q = R C/L, show that the circuit can G1 G1 G2
perform as a notch filter. FK − 1
+
(f) For the purpose of rejecting 60-Hz interfer- G1 G2 . . . GK−1
ence, in order to get fl = 58 Hz and fu = 62
Hz, find the values of L and C of the circuit If an amplifier is designed having three identical
in part (e) with R = 1 k-. states, each of which has a gain of Gi = 5 and a
14.3.5 A noisy amplifier has N out = 600 µW when T = noise figure of Fi = 6, i = 1, 2, 3, determine
T 0; but N out drops to 480 µW when the source is the overall noise figure of the cascade of the
immersed in liquid nitrogen at T = 80 K. Find three stages. Looking at the result, justify the
the amplifier’s noise temperature Ta. statement that the front end of a receiver should
have a low noise figure and a high gain. (Note
14.3.6 Two noisy amplifiers (with noise temperatures
that the noise figure of an amplifier is F =
T a1 and T a2) having the same bandwidth are con-
1 + Ta /T0 .)
nected in cascade so that the overall gain is G
= G1G2. If the input noise to the first amplifier 14.3.13 A radio antenna with a noise temperature of 60
is N = kTB, determine the total output noise K is pointed in the direction of the sky. The
power and the effective noise temperature Ta of antenna feeds the received signal to the preampli-
the cascade, so that N out = Gk(T + Ta)B. fier, which has a gain of 30 dB over a bandwidth
of 10 MHz and a noise figure (F = 1 + Ta /T0 )
*14.3.7 In order to measure the amplifier noise tempera-
of 2 dB.
ture Ta, a thermal source at temperature T 0 is con-
nected and the corresponding N out is observed; (a) Determine the effective noise temperature at
then the source temperature is increased to TR the input to the preamplifier.
when the corresponding N out is doubled. Find Ta (b) Determine the noise power at the output of
in terms of TR and T 0. the preamplifier.
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15 Communication Systems
15.1 Waves, Transmission Lines, Waveguides, and Antenna Fundamentals
15.2 Analog Communication Systems
15.3 Digital Communication Systems
15.5 Practical Application: A Case Study—Global Positioning Systems
Problems
Even though most modern communication systems have only been invented and developed during
the eighteenth and nineteenth centuries, it is difficult to imagine a world without telephones, radio,
and television. After the invention of the electric battery by Alessandro Volta in 1799, Samuel
Morse developed the electric telegraph and demonstrated it in 1837. Morse devised the variable-
length binary code, in which letters of the English alphabet are represented by a sequence of
dots and dashes (code words). In this code, more frequently occurring letters are represented by
short code words, whereas letters occurring less frequently are represented by larger code words.
Morse code (variable-length binary code), developed in 1837, became the precursor to variable-
length source coding methods. Telegraphy, the earliest form of electrical communication, was a
binary digital communication system in which the letters of the English alphabet were efficiently
encoded into corresponding variable-length code words having binary elements. In the baudout
code, developed in 1875, the binary code elements were of equal length, and each letter was
encoded into fixed-length binary code words of length 5.
With the invention of the telephone, telephony came into being and the Bell Telephone
Company was established in 1877. Transcontinental telephone transmission became operational
in 1915. Automatic switching was another important advance, and a digital switch was placed in
service in 1960. Numerous significant advances have taken place in telephone communications
over the past four decades. For example, fiber-optic cables have replaced copper wire, and
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electronic switches have come into use in place of electromechanical devices.

Marconi is credited with the development of wireless telegraphy in the late 1890s, after
Maxwell’s theory of electromagnetic radiation was verified experimentally by Hertz in 1887. The
666
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Communication Systems 667
invention of the vacuum tube was particularly instrumental in the development of radio commu-
nication systems. Amplitude modulation (AM) broadcast was initiated in 1920, while frequency
modulation (FM) broadcast was developed commercially by the end of World War II. Commercial
television broadcasting began in 1936 by the BBC (British Broadcasting Corporation), and the
FCC (Federal Communications Commission) authorized television broadcasting five years later
in the United States.
The growth in communications over the past 60 years has been phenomenal. The invention of
the transistor in 1947 and the integrated circuit and laser in 1958 have paved the way to satellite
communication systems. Most of the wire-line communication systems are being replaced by
fiber-optic cables (providing extremely high bandwidth), which makes the transmission of a wide
variety of information sources (voice, data, and video) possible. High-speed communication
networks linking computers and the greater need for personal communication services are just
the beginning of the modern telecommunications era.
Today digital communication systems are in common use, carrying the bulk of our daily
information transmission through a variety of communication media, such as wire-line telephone
channels, microwave radio, fiber-optic channels, and satellite channels. Even the current analog
AM and FM radio and television broadcasts will be replaced in the near future by digital transmis-
sion systems. High-speed integrated circuits (ICs), programmable digital signal processing chips,
microelectronic IC fabrication, and sophisticated digital modulation techniques have certainly
helped digital communications as a means of transmitting information.
In spite of the general trend toward digital transmission of analog signals, a significant amount
of analog signal transmission still takes place, especially in audio and video broadcasting. His-
torically, analog communication systems were placed first, and then came digital communication
systems.
In any communication system, the communication channel provides the connection between
the transmitter and the receiver. The physical channel (medium) may be any of the following:
• A pair of wires, which carry the electric signal

• Optical fiber, which carries the information on a modulated light beam
• An underwater ocean channel, in which the information is transmitted acoustically
• Free space, over which the information-bearing signal is radiated by using an antenna
• Data storage media, such as magnetic tape, magnetic disks, and optical disks.
The available channel bandwidth, as well as the noise and interference, limit the amount of
data that can be transmitted reliably over any communication channel.
Figure 15.0.1 illustrates the various frequency bands of the electromagnetic spectrum (radio --`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
and optical portions) along with types of transmission media and typical applications.
Wire-line channels are used extensively by the telephone network for voice, data, and video
transmission. Twisted-pair wire lines (with a bandwidth of several hundred kHz) and coaxial
cable (with a usable bandwidth of several MHz) are basically guided electromagnetic channels.
Fiber-optic channels offer a channel bandwidth that is several orders of magnitude larger than
coaxial cable channels. The transmitter or modulator in a fiber-optic communication system is a
light source, such as a light-emitting diode (LED) or a laser, whose intensity is varied (modulated)
with the message signal. The light propagates through the fiber as a light wave and is amplified
periodically along the transmission path to compensate for signal attenuation. At the receiver
end, the light intensity is detected by a photodiode, whose output is an electric signal that varies
Copyright OUP
668 COMMUNICATION SYSTEMS
Designation Transmission media Applications
Ultraviolet
Experimental 1015 Hz
Visible light Optical Laser digital
10−6 m fibers beams telecommunication
Infrared
1015 Hz
Millimeter Experimental
100 GHz
waves Navigation
1 cm
Superhigh Waveguide Satellite to satellite
frequency Microwave 10 GHz
(SHF) radio Microwave relay
10 cm Earth to satellite
Ultrahigh
frequency Radar 1 GHz
(UHF)
1m UHF TV
Wavelength
Frequency
Very high Mobile, Aeronautical
frequency Short-wave VHF TV and FM 100 MHz
(VHF) radio
10 m Mobile radio
Coaxial
High cable Business
frequency 10 MHz
Amateur radio
(HF) International
100 m Citizens band
Medium
frequency AM broadcasting 1 MHz
(MF)
1 km Aeronautics
Low Long-wave
frequency radio Submarine cable
100 kHz
(LF) Navigation
10 km
Very low Transoceanic radio
Wire pairs
frequency 10 kHz
(VLF)
Telephone
100 km
Audio Telegraph
band
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1 kHz
Figure 15.0.1 Frequency bands of the electromagnetic spectrum. (Source: A. Carlson,

Communication Systems, 3rd ed., McGraw-Hill, New York, 1986.)
in direct proportion to the power of light striking on the photodiode. Optical fiber channels are
replacing nearly all wire-line channels in the telephone network.
Wireless electromagnetic channels are used in wireless communication systems, in which
the electromagnetic energy is coupled to the propagation medium through an antenna that serves
as a radiator. The physical size and configuration of the antenna depend mainly on the frequency
of operation. For example, a radio station transmitting AM frequency band of 1 MHz (with
a corresponding wavelength of λ = c/fc = 300 m) requires an antenna of at least 30 m
(approximately one-tenth of the wavelength).
The mode of propagation of electromagnetic waves in free space and atmosphere may be
subdivided into three categories:
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Communication Systems 669
• Ground-wave propagation
• Sky-wave propagation
• Line-of-sight (LOS) propagation.
In the frequency bands that are primarily used to provide navigational aids from shore to
ships around the world (VLF to LF to MF), the available channel bandwidths are relatively small,
and hence the information that is transmitted through these channels is relatively slow speed and
generally confined to digital transmission. Noise at these frequencies is caused by thunderstorm
activity around the globe, whereas interference is caused by the many users.
For frequencies of 0.3 to 3 MHz, in the MF band, ground-wave (or surface-wave) propagation,
illustrated in Figure 15.0.2, is the dominant mode used for AM broadcasting and maritime radio
broadcasting. Dominant disturbances include atmospheric noise, human-made noise, and thermal
noise from electronic components. The range is limited to about 100 miles for even the more
powerful radio stations.
In the ionosphere, the rarefied air becomes ionized, mainly due to ultraviolet sunlight. The
D-region, usually falling between 50 and 90 km in altitude, will reflect waves below 300 kHz or
so, and attenuate higher frequency waves (300 kHz < f < 30 MHz), especially in the daytime.
The D-region mostly disappears at night. The E-region (about 110 km in altitude) reflects high
frequencies (3 MHz < f < 30 MHz) during the daytime, and medium frequencies (300 kHz < f
< 3 MHz) at night. The F1-region (about 175 to 250 km in altitude) is distinct from the F2-region
(250 to 400 km in altitude) only during the day; at night they merge. Waves that penetrate the
E-region usually go through the F1-region as well, with some attenuation being the primary effect.
The F2-region provides the main means of long-distance, high-frequency (3 MHz < f < 30 MHz)
communication by wave reflection. Sky-wave propagation is illustrated in Figure 15.0.3.
Signal multipath occurs with electromagnetic wave propagation via sky wave in the HF
range. When the transmitted signal reaches the receiver through multiple propagation paths with
different delays, signal fading may result. Both atmospheric noise and thermal noise become the
additive noise at high frequencies. It is possible to have ionospheric scatter propagation in the
frequency range of 30 to 60 MHz, and tropospheric scattering in the range of 40 to 300 MHz; but
relatively large antennas are needed with a large amount of transmitted power, because of large
signal propagation losses.
Frequencies above 30 MHz, propagating through the ionosphere with relatively little loss,
make satellite and extraterrestrial communications possible. In the VHF band and higher, the
dominant mode is line-of-sight (LOS) propagation, in which the transmitter and receiver antennas
must be in direct LOS with relatively little or no obstruction. That is why television stations
Ground or surface Figure 15.0.2 Illustration of ground-wave propagation in MF

Troposphere wave band.
(20 km above
earth surface) Earth
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Ionosphere (with D, E, F regions) Figure 15.0.3 Illustration of sky-wave propaga-

tion.
(50 to 600 km
Sky waves
above earth
surface)
Earth
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transmitting in the VHF and UHF bands have their antennas mounted on high towers to achieve a
broad coverage area. A television
√ antenna mounted on a tower of 1200 feet in height (= h) provides
a coverage of about d = 2h ∼ = 50 miles. Microwave radio relay systems (for telephone and
video transmission at about 1 GHz) also have antennas mounted on tall towers.
In the VHF and UHF bands, thermal noise and cosmic noise, picked up by the antenna, become
predominant. Above 10 GHz in the SHF band, atmospheric conditions (such as precipitation and
heavy rains) play a major role in signal propagation. In the infrared and visible light regions of
the electromagnetic spectrum, LOS optical communication in free space is being experimented
with for satellite-to-satellite links.
A good understanding of a communication system can be achieved by studying electro-
magnetic wave propagation (via transmission lines and antennas), and modulation as well as
demodulation involved in analog and digital communication systems. Toward that end, this chapter
is divided into three sections. Since the wave concepts that apply to transmission lines are easily
understood, the first section deals with waves, transmission lines, and antenna fundamentals.
Then we go on to discuss analog and digital communication systems in Sections 15.2 and 15.3,
respectively.
15.1 WAVES, TRANSMISSION LINES, WAVEGUIDES, AND ANTENNA

FUNDAMENTALS
In basic circuit theory we neglect the effects of the finite time of transit of changes in current and
voltage and the finite distances over which these changes occur. We assume that changes occur
simultaneously at all points in the circuits. But there are situations in which we must consider the
finite time it takes for an electrical or magnetic wave to travel and the distance it will travel. It is
in these situations that one must employ traveling-wave theory. Traveling-wave concepts must
be used whenever the distance is so great or the frequency so high that it takes an appreciable
portion of a cycle for the wave to travel the distance.
For sinusoidal signals, a wavelength λ is defined as the distance that a wave travels in one
cycle or period. Since electric waves in free space travel at the velocity of light c(∼
= 3 × 108 m/s),
the free-space wavelength is given by c/f. Table 15.1.1 shows some free-space wavelengths at
selected frequencies. If the traveling-wave technique is to be employed for distances greater than
1/10 wavelength, a distance of 3 mm at 10 GHz would require the use of this technique, whereas
the same distance at 100 MHz would not. On the other hand, a distance of 1 km is insignificant
at power-line frequencies, but not in the broadcast band.
The connection of the high-power output of a transmitter located on a building to the
transmitting antenna on a tower is often made by special conductors called transmission lines,
which guide the waves and usually consist of two or more parallel conductors, which are separated
by insulating (dielectric) materials. While transmission lines are available in many forms, Figure
15.1.1 illustrates cross sections of some common types. The two-wire line of Figure 15.1.1(a) is
TABLE 15.1.1 Free-Space Wavelengths at Selected Frequencies
Application Frequency Wavelength
Power transmission 60 Hz 5000 km

Voice 1 kHz 300 km
Broadcast band 1 MHz 300 m
FM, television 100 MHz 3m
X-band radar 10 GHz 3 cm
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15.1 WAVES, TRANSMISSION LINES, WAVEGUIDES, AND ANTENNA FUNDAMENTALS 671
used to connect some television antennas. The coaxial cable of Figure 15.1.1(b) is the most widely
used of the many possible cable-type transmission lines. For printed-circuit and integrated-circuit
applications, transmission lines sketched in Figures 15.1.1(c) through (f) are commonly employed.
At higher frequencies, when power levels are large and attenuation in transmission lines is
significant, connections between system components are often made through waveguides, which
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
are usually hollow, closed, rigid conductor configurations (much like water pipes) through which
waves propagate. The most common waveguides are either rectangular or circular in cross
section, as depicted in Figure 15.1.2, but other shapes and flexible varieties are also possible.
Coaxial transmission lines commonly operate in what is called the transverse electric
magnetic (TEM) mode, in which both the electric and the magnetic fields are perpendicular
Conductors
Conductor
W
d d
Dielectric
Dielectric εr εr D
(a) (b)
Conducting strip Conducting strip

W
Free space ε 0
Dielectric εr h Dielectric εr h
W
(c) (d)
S W S
Hot lead h
2h
Ground Hot lead Ground h
Dielectric εr W Dielectric εr
(e) (f)
Figure 15.1.1 Transmission lines (cross sections of some common types). (a) Two-wire line. (b) Coaxial
line (cable). (c) Parallel strip line. (d) Microstrip line. (e) Strip line. (f) Coplanar waveguide.
a a
(a) (b)
Figure 15.1.2 Waveguides. (a) Rectangular. (b) Circular.
Copyright OUP
(transverse) to the direction of propagation, which is along the axial line. That is to say, no
electromagnetic field component exists in the axial direction. In the case of single-conductor
hollow (pipelike) waveguides, either the TE (transverse electric) or the TM (transverse magnetic)
mode can be energized. In the TE configuration, the electric field is transverse to the direction of
propagation (which is along the axial line of the waveguide); that is to say, no electric field exists
in the direction of propagation, while an axial component of the magnetic field is present. On the
other hand, in the TM configuration, the magnetic field is transverse to the direction of propagation:
i.e., no magnetic field exists in the axial direction, whereas an axial component of the electric
field is present. Within either grouping, a number of configurations or modes can exist, either
separately or simultaneously. However, we are generally concerned with the so-called dominant
mode, which is defined as the lowest frequency mode that can exist in the waveguide. When
operating at a frequency above fc, known as the cutoff frequency, a wave propagates down the
waveguide and the mode is called propagation mode. When operating below the cutoff frequency,
the field decays exponentially and there is no wave propagation.
Figure 15.1.3 represents a transmission line of length l connecting a signal source to a distant
load. The line may be a two-wire line, a coaxial cable, or a hollow waveguide. The voltage v1(t)
between the source-side (input) terminals of the transmission line gives rise to an electric field,
while the current i1(t) produces a magnetic field. The characteristic impedance Z̄0 of the line is
given by
V̄1
Z̄0 = (15.1.1)
I¯1
which relates the voltage and current of the wave traveling along the line. Although Z̄0 in general
could be complex, for distortionless transmission, Z̄0 (= R0) must be constant and resistive over
the frequency range of the signal. The signal-source voltage vS(t) is related to v1(t) by
vS (t) = v1 (t) + i1 (t)RS (15.1.2)
where RS is the signal-source internal resistance. From Equations (15.1.1) and (15.1.2), we get
R0
v1 (t) = vS (t) (15.1.3)
RS + R 0
1
i1 (t) = vS (t) (15.1.4)
RS + R 0
As the electromagnetic fields associated with v1(t) and i1(t) propagate down the line, they carry
along the associated voltages and currents that are no different from v1(t) and i1(t) except for a
delay in time, because the charges (and therefore current) move down the line at finite velocity
vg. Thus, at output terminals c and d in Figure 15.1.3, which are a distance l apart, the voltage
RS = Z0 Figure 15.1.3 Transmission line (with

matched impedances).
i1(t) a c i2(t)
Transmission
vS (t) line RL = Z0
x (t) = v1(t) b d y (t) = v2(t)

Pin Pout
Signal Z0 Load
source
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and current are given by

v2 (t) = v1 (t − tl ) (15.1.5)
i2 (t) = i1 (t − tl ) (15.1.6)
where the delay time tl is
tl = l/vg (15.1.7)
On substituting Equations (15.1.3) and (15.1.4), we obtain

R0 l
v2 (t) = vS t − (15.1.8)
RS + R 0 vg

1 l
i2 (t) = vS t − (15.1.9)
RS + R 0 vg
Because of the line’s behavior, the impedance at terminals c and d, which is V̄2 /I¯2 , is still Z̄0 (= R0 ).
As a consequence, the line can be terminated by an impedance Z̄0 (= R0 ) at the output terminals
with no effect on voltages and currents anywhere else on the line. This result is very significant,
because if a wave is launched on a real, finite-length transmission line, the wave will dissipate
itself in the terminating load impedance if that impedance is equal to the line’s characteristic
impedance. The load is then said to be matched to the line. In Figure 15.1.3, the source and
load resistances are shown matched so that RS = R0 = RL . Otherwise, a mismatch at the load
(RL = R0 ) reflects some of the signal energy back toward the source where any mismatch (RS =
R0) further reflects energy in the forward direction. Impedance matching on both ends eliminates
these undesired multiple reflections. Note that the value of R0 will be different for different types
of transmission lines.
EXAMPLE 15.1.1
An RG-213/U (radio guide 213/universal coaxial cable) is a small-sized, flexible, double-braided
cable with silvered-copper conductors, and a characteristic impedance of 50 -. The characteristic
impedance Z̄0 (= R0 ) is related to the cable’s geometrical parameters by
60 b
Z̄0 = R0 = √ ln
εr a
where εr is the relative permittivity (dielectric constant) of the dielectric, and b and a are the radii
of the outer and inner conductors, respectively. The velocity of wave propagation in a coaxial line
√
is vg = c/ εr , where c = 3 × 108 m/s is the velocity of light. The cutoff frequency, given by
c
fc = √ Hz
π εr (a + b)
puts an upper bound for wave propagation. The attenuation due to conductor losses is approxi-
mately given by √
* (1.373 × 10−3 ) ρf 1 1
*
Attenuation c = + dB/m
Z0 a b
where ρ is the resistivity of the conductors. Attenuation due to dielectric losses is given by
* √
Attenuation*d = (9.096 × 10−8 ) εr f tan δ dB/m
where tan δ is known as the loss tangent of the dielectric.
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With a = 0.445 mm, b = 1.473 mm, εr = 2.26 for polyethylene dielectric, tan δ = 2 × 10−4 ,
and ρ = 1.63 × 10−8 - · m, calculate the total line attenuation at 100 MHz, and check the value of
Z̄0 (= R0 ) in the specification. If the cable connects an antenna to a receiver 30 m away, determine
the time delay of the cable, the velocity of wave propagation, and the cutoff frequency.
Solution
√
* (1.373 × 10−3 ) 1.63 × 10−8 × 108 1 1
*
Attenuation c = +
50 0.445 × 10−3 1.473 × 10−3
∼
= 0.103 dB/m
* √
*
Attenuation d = (9.096 × 10−8 ) 2.26 × 108 × 2 × 10−4
∼
= 0.00273 dB/m
Losses due to conductors obviously dominate.
Total attenuation = 0.103 + 0.00273 ∼= 0.106 dB/m
60 1.473 ∼
Z̄0 = R0 = √ ln = 50 -
2.26 0.445
√
l 30 2.26 ∼
Time delay = τ = = = 0.15 µs
vg 3 × 108
√ √
The velocity of wave propagation vg = c/ εr = c/ 2.26 = 0.665 times the speed of light, or
vg ∼
= 2 × 108 m/s
3 × 108
Cutoff frequency fc = √
π 2.26(0.445 + 1.473)10−3
3 × 1011 ∼
= √ = 33 GHz
π 2.26 × 1.918
In practice, f < 0.95fc is usually maintained.
EXAMPLE 15.1.2
Unlike transmission lines, which operate at any frequency up to a cutoff value, waveguides
have both upper and lower cutoff frequencies. For rectangular air-filled waveguides [see Figure
15.1.2(a)], the lower cutoff frequency (for propagation by the dominant mode) is given by
fc = c/2a, where c is the speed of light. Since the upper limit cannot be larger than 2fc, practical
waveguides are designed with b ∼ = a/2 with a suggested frequency of 1.25fc ≤ f ≤ 1.9fc . For a
circular air-filled waveguide [see Figure 15.1.2(b)] with inside radius a, the lower cutoff frequency
(for propagation by the dominant mode) is fc = 0.293c/a. The operating band is usually fc < f
< 1.307fc. The characteristic impedance Z̄0 (= R0 ) in waveguides is not constant with frequency,
as it is in transmission lines. For rectangular or circular air-filled waveguides, the expression for
Z̄0 (= R0 ) is given by
377
Z̄0 = R0 =
1 − (fc /f )2
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(a) For a rectangular air-filled waveguide with a = 4.8 cm and b = 2.4 cm, compute the
cutoff frequency. If the operating frequency is 4 GHz, find the waveguide’s characteristic
impedance.
(b) Calculate the diameter of an air-filled circular waveguide that will have a lower cutoff
frequency of 10 GHz.
Solution
c 3 × 108
(a) fc = = = 3.125 GHz
2a 2 × 4.8 × 10−2
377 377 377
Z̄0 = R0 = =√ = = 1106.5 -
1− (3.125/4)2 1 − 0.8839 0.3407
0.293c 0.293 × 3 × 108

(b) a = = = 0.88 cm
fc 10 × 109
Diameter = 2a = 1.76 cm
Now referring to Figure 15.1.3, assuming matched and distortionless conditions, with signal
voltage x(t) across the line input, the resulting output voltage y(t) is given by
y(t) = Kx(t − td ) (15.1.10)
where K is the attenuation factor (less than unity) due to ohmic heating in the line dissipating part
of the input signal energy and td is the delay time. Working with the average signal powers Pin
and Pout, the transmission loss L is defined as the power ratio
L = Pin /Pout (15.1.11)
where L = 1/K 2 > 1 and Pout < Pin. Regardless of the type of transmission line, the transmission
loss increases exponentially with distance l such that
L = 10αl/10) (15.1.12)
where α is the attenuation coefficient of the line in decibels per unit length. Expressing L in dB,
similar to power gain, we obtain
Pin
LdB = 10 log = αl (15.1.13)
Pout
Typical values of α range from 0.05 to 100 dB/km, depending on the type of transmission line
and the frequency. Rewriting Equation (15.1.13) as
Pout
= 10−LdB /10 = 10−αl/10 (15.1.14)
Pin
Equation (15.1.14) reveals that Pout will be one-tenth of Pin when l = 10/α, showing thereby
how rapidly the output power falls off as the distance increases.
The transmission loss can be overcome with the aid of one or more amplifiers connected
in cascade with the transmission line. Figure 15.1.4 shows such a system with a preamplifier
(transmitting amplifier) at the source, a receiving amplifier at the destination, and a repeater
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Preamplifier Repeater Receiving

amplifier
Pin L1 L2 Pout
G1 G2 G3
α1 α2
1 2
Figure 15.1.4 Transmission system with preamplifier, repeater, and receiving amplifier.
(an additional amplifier) at some intermediate point in the line. All amplifiers will of course be
impedance-matched for maximum power transfer. The final output power Pout in Figure 15.1.4 is
then given by
Pout G1 G2 G3
= (15.1.15)
Pin L1 L 2
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where the Gs are the power gains of the amplifiers, and the Ls are the transmission losses of the
two parts of the line. Equation (15.1.15) reveals that we can compensate for the line loss and get
Pout ≥ Pin if G1G2G3 ≥ L1L2. Noise considerations often call for a preamplifier to boost the signal
level before the noise becomes significant. As in the case of transcontinental telephone links,
several repeaters are generally required for long-distance transmission.
EXAMPLE 15.1.3
From a source with Pin = 2.4 mW, we want to get Pout = 60 mW at a distance l = 20 km from
the source. α for the transmission line is given to be 2.3 dB/km. The available amplifiers have
adjustable power gain, but are subject to two limitations: (i) the input signal power must be at
least 1 µW to overcome internal noise, and (ii) the output signal power must not be greater than
1 W to avoid nonlinear distortion. Design an appropriate system.
Solution
αl = 2.3 × 20 = 46 dB
LdB = 46 or L = 1046/10 ∼
= 40,000
Hence, we need a total gain of
Gtotal = L(Pout /Pin ) = 40,000 × (60/2.4) = 106 , or 60 dB
We cannot put all the amplification at the destination, because the signal power at the output
of the line would be Pin /L = 2.4 × 10−3 /(40 × 103 ) = 0.06 µ W, which falls below the amplifier
noise level. Nor can we put all amplification at the source, because the amplified source power
GPin = 106 × 2.4 × 10−3 = 2.4 kW would exceed the amplifier power rating. But we could
try a preamplifier with G1 = 400, so as to get G1Pin = 400 × 2.4 × 10−3 = 0.96 W at the
input of the line, and G1 Pin /L = 24 µ W at the output. The output amplifier should then have
G2 = Pout /(24 µW) = 60 × 10−3 /(24 × 10−6 ) = 2500, and a repeater is not needed.
Antenna Fundamentals
We shall discuss here only the fundamental concepts needed to understand the role of an antenna as
a power-coupling element of a system. Figure 15.1.5 illustrates the elements of a communication
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system that involves antennas (with no conductors in the propagation medium) and the following
nomenclature:
Pt Power generated by the transmitter
Lt, Lr Transmitting-path loss (representing the power reduction caused by the transmission line
or waveguide that connects to the transmitting antenna) and receiving-path loss
Lta, Lra Transmitting antenna loss and receiving antenna loss
R Distance of separation between the antennas
S Signal power available at the lossless antenna output
Sr Signal power available at the receiver input
Radio transmission consists of antennas at the source and at the destination. It requires the
signal to be modulated on a high-frequency carrier, which usually is a sinusoid. Driven by an
appropriate carrier, the transmitting antenna launches an electromagnetic wave that propagates
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through space without the help of a transmission line. A portion of the radiated power is collected
at the receiving antenna.
The wavelength λ of the radio wave in air is related to the carrier frequency fc by
fc λ = c = 3 × 108 m/s (15.1.16)
The radio-transmission loss differs from that of a transmission line in two ways: (i) it increases as
the square of the separating distance instead of exponentially, and (ii) it can be partly compensated
by the antenna gains.
Antenna gain depends on both shape and size. Dipole antennas, commonly used at lower
radio frequencies, are made up of a rod or wire of length λ/10 to λ/2, and have an antenna-gain
range of 1.5 to 1.64 (1.8 to 2.1 dB). Horn antennas and parabolic dishes (so named after their
shapes) have much more gain at higher frequencies. A useful, although approximate, expression
for gain is given by
Transmitting Transmitting
path losses antenna loss
Information-bearing
signal Transmitter Lt Lta
Pt
Lossless
Medium R
antenna
Information-bearing
signal Receiver Lr Lra
Sr S
Receiving Receiving
path losses antenna loss
Figure 15.1.5 Communication system elements involving antennas.
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4π Ae
G= (15.1.17)
λ2
where λ is the wavelength being transmitted (or received), and Ae is the effective aperture or
effective area of the antenna. Power amplifiers are needed to overcome the radio-transmission
loss just as in a transmission-line system. Similar considerations hold for optical radiation, in
which the electromagnetic wave takes the form of a coherent light beam.
Radio transmission is inherently a bandpass process with a limited bandwidth B nominally
centered at the carrier frequency fc. The fractional bandwidth B/fc is a key design factor with
a general range of 1/100 ≤ B/fc ≤ 1/10. It is obvious then that large signal bandwidths
require high carrier frequencies to satisfy fc ≥ 10B. You can reason why television signals
are transmitted at fc of 100 MHz, whereas AM radio signals are transmitted at fc of 1 MHz.
Since optical communication systems offer tremendous bandwidth potential on the order of 1012
Hz, and a corresponding high information rate, they have become topics of current research
interest.
Antennas do not radiate power equally in all directions in space. The radiation intensity
pattern describes the power intensity (which is power per unit solid angle, expressed in units of
watts per steradian) in any spatial direction. Conceptually it is convenient to define an isotropic
antenna as a lossless antenna that radiates its power uniformly in all directions. Although an
isotropic antenna cannot be realized in practice, it serves as a reference for comparison with real
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antennas. The radiation intensity for such an antenna, with input power P, is a constant in any
direction, given by P /4π . The power gain G of a realistic antenna is a measure of the maximum
radiation intensity of the antenna as compared with the intensity that would result from an isotropic
antenna, with the same power input. G is then expressed as
maximum radiation intensity
G=
radiation intensity of isotropic source (with the same power input)
4π (maximum radiation intensity)
= (15.1.18)
P
Referring to Figure 15.1.5, when a power Pt /Lt is applied to the transmitting antenna, let us find
the signal power Sr available to the receiver from the receiving antenna. An isotropic transmitting
antenna would cause a radiation power density (power per unit area of a sphere) of
Pt
Power density = (15.1.19)
4π R 2 Lt
For a practical antenna that has power gain Gt and loss Lta relative to an isotropic antenna, Equation
(15.1.19) would be modified as
Pt Gt
Power density = (15.1.20)
4π R 2 Lt Lta
We shall assume that the transmitting and receiving antennas (reciprocal elements) point directly
toward each other, so that their gains are maximum. Letting Lch denote any losses incurred by the
wave in the channel (medium), and Are be the effective area of the receiving antenna, the power
that the receiving antenna is able to produce is given by
Pt Gt Are
S= (15.1.21)
4π R 2 Lt Lta Lch
Accounting for the receiving antenna loss and receiving-path losses, a total system loss L can be
defined as
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L = Lt Lta Lch Lra Lr (15.1.22)

Sr would then be given by
Pt Gt Are
Sr = (15.1.23)
4π R 2 L
Using Equation (15.1.17) with Gr representing the receiving antenna gain, Equation (15.1.23)
becomes
Pt Gt Gr λ2
Sr = (15.1.24)
(4π )2 R 2 L
Quite often, for simplicity, in the case of LOS radio transmission illustrated in Figure 15.1.6,
the transmission loss for a path of length R is given by

Pin 1 4π R 2
LTR = = (15.1.25)
Pout Gt Gr λ
which justifies the statements following Equation (15.1.16).
EXAMPLE 15.1.4
Let a LOS radio system and a transmission-line system both have L = 60 dB when the distance
R between transmitter and receiver is 15 km. Compute the loss of each when the distance is
increased to 30 km.
Solution
R is doubled. LdB for the transmission line is proportional to the distance, as per Equation
(15.1.13). Hence, LdB for the new transmission line = 2 × 60 = 120 dB.
LTR for the LOS radio system is proportional to R2, as per Equation (15.1.25). Noting that
LdB = 10 log L and L = KR2, where K is a constant, it follows that
LdB = 20 log KR
When R is doubled,
LdB new = 20 log (K2R) = 20(log KR + log 2)
= 20 log KR + 20 log 2 = LdB old + 6
Hence, LdB for the new LOS radio system = 60 + 6 = 66 dB.
Power gain Power gain Figure 15.1.6 Illustration of LOS radio trans-
Gt Gr mission.
Pin Pout
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EXAMPLE 15.1.5
(a) Some antennas have a physical aperture area A that can be identified and is related to
the effective area Ae by Ae = ρa A, where ρa is known as the aperture efficiency. For a
circular-aperture antenna with a diameter of 2 m and an aperture efficiency of 0.5 at 4
GHz, calculate the power gain.
(b) Referring to Figure 15.1.5, let two such antennas be used for transmitting and receiving,
while the two stations are separated by 50 km. Let the total loss over the link be 9 dB,
while the transmitter generates 0.5 W. Find the available received power.
Solution
c 3 × 108
(a) λ = = = 0.075 m. From Equation (15.1.17),
f 4 × 109
4π Ae 4πρa A 4π × 0.5 × π
G= = = = 3509
λ2 λ2 0.0752
(b) G = Gt = Gr = 3509; LdB = 10 log L, or L = 7.94. From Equation (15.1.24),
0.5 × 35092 × 0.0752 ∼
= 1.1 × 10−8 W
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Sr =
(4π )2 × 502 × 106 × 7.94
The variety and number of antennas are almost endless. However, for our introductory
purposes, they may be divided into the following types:
• Wire antennas, such as half-wavelength dipole, folded half-wave dipole, and helical antenna
• Array antennas, such as YAGI-UDA array
• Aperture antennas, such as pyramidal horn, conical horn, paraboloidal antenna, and Casse-
grain antenna
• Lens-type antennas in radar and other applications.
Some of their geometries are illustrated in Figure 15.1.7.
The radiation-intensity pattern describing the power intensity in any spatial direction is
an important antenna characteristic, since the antenna does not radiate power equally in all
directions in space. Such patterns are three-dimensional in nature. One normally chooses spherical
coordinates centered on the antenna at A, and represents the power-intensity function P(θ, φ) at
any distant point R as a magnitude P from A, which appears as a surface with a large main lobe
and several side lobes (minor lobes), as shown in Figure 15.1.8.
Generally speaking, in most of the communication systems the transmitting and receiving
antennas (reciprocal elements) face each other directly such that their large main lobes point
toward each other, and the received-power output will be maximum. When scaled such that
the maximum intensity is unity, the radiation-intensity pattern is commonly called the radiation
pattern. In many problems in practice, the radiation pattern occurs with one dominant main
lobe, and as such, instead of considering the full three-dimensional picture, the behavior may
adequately and conveniently be described in two orthogonal planes containing the maximum of
the main lobe. These are known as principal-plane patterns in terms of angles θ and φ. Figure
15.1.9 illustrates one such pattern in polar and linear angle plots as a function of θ . The angular
separation between points on the radiation pattern that are 3 dB down from the maximum is called
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z s
L =λ
2 4
y
θ d L
a d
a λ
Transmission b 2
line b z
d φ Transmission P
line
−L = − λ x Transmission
N turns
2 4 line S
(a) (b) (c)
Transmission line
Directors
L
a
z b
Throat B y x
Active element z
(regular or folded dipole) A
Horn
Reflector Aperture throat z
(d) (e) (f)
y Focus f
z
f' Hyperbola
(subreflector)
z Feeding
D
f line
Focus
Parabola
(g) (h)
Figure 15.1.7 (a) Half-wave dipole. (b) Folded half-wave dipole. (c) Helical-beam antenna. (d) YAGI-UDA
array antenna. (e) Pyramidal horn. (f) Conical horn. (g) Paraboloidal antenna. (h) Cassegrain antenna (section).
the beamwidth, which is designated as θB or φB in the principal-plane patterns. Another useful,

although approximate, expression for gain in terms of the beamwidths θB and φB of the pattern’s
main lobe is given by
4π
G= (15.1.26)
θ B φB
when beamwidths are expressed in radians, or
41.3 × 103
G= (15.1.27)
θ B φB
when beamwidths are expressed in degrees.
The antenna impedance, looking into the feed-point terminals of an antenna, will in general
have both resistive and reactive components. The antenna resistance is the combination of the
radiation resistance (accounting for the power radiated by the antenna) and the loss resistance
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um
z xim
z Main f ma R
o To
on
lobe
re cti
Di
θ Side
R lobes
A
φ A
x y
x y
(a) (b)
Figure 15.1.8 (a) Spherical coordinates centered on the antenna at A. (b) Typical radiation-intensity pattern
with main and side lobes (with all possible values of θ and φ considered).
(accounting for the power dissipated in the antenna itself as losses). Ideally, the antenna resistance
should be equal (matched) to the characteristic impedance of the feeding line or guide to prevent
reflected power, and the antenna reactance should be zero.
Most antennas transmit only one polarization of electromagnetic wave. That is to say, the
electric field of the propagating wave is oriented with respect to the antenna in only one direction.
The main lobe in most antennas is directed normal to the plane of the aperture. For phased-array
antennas, however, the main lobe is electronically steered to other angles away from the so-called
broadside. Figure 15.1.10 illustrates vertical, horizontal, and arbitrarily linear polarizations of
the electric field. In Figure 15.1.10(a), with the electric field lying in the vertical plane, the
radiation is said to be vertically polarized. With the electric field being in the horizontal plane,
as in Figure 15.1.10(b), the radiation is said to be horizontally polarized. Since both vertical and
horizontal polarizations are simply special cases of linear polarization, the electric field, having
both horizontal and vertical components (that are in time phase), can still be in a plane, as shown
in Figure 15.1.10(c).
Some systems transmit simultaneously two linear orthogonal polarizations that are not in
time phase. Elliptical polarization results when the two linear components have arbitrary relative
amplitudes and arbitrary time phase. Circular polarization (probably the most useful type) is a
special case in which the horizontal and vertical electric fields are 90° out of time phase and have
equal magnitude. Left-hand circular polarization results when the horizontal radiation component
lags the vertical one by 90° and the resultant field appears to rotate counterclockwise in the xy-
plane with time, as one located at the antenna views the wave leaving the antenna. If the horizontal
component leads the vertical one by 90°, right-hand circular polarization is said to take place.
Referring to Figure 15.1.7, the half-wave dipole is a relatively narrow-band antenna with
its radiated wave linearly polarized. The dipole can be driven by a transmission line of 75--
characteristic impedance. The folded half-wave dipole (a variation of the half-wave dipole) is
used in television, broadcast FM, and other applications. This antenna is well suited for use with
300-- television cable. The helical antenna of Figure 15.1.7(c) yields a pencil-beam pattern in
the axis of the helix with circular wave polarization.
The YAGI-UDA array of Figure 15.1.7(d) is commonly used for television reception. It is
usually seen with 3 to 12 elements, although even 40 elements are sometimes employed. Design
frequencies from 100 to 1000 MHz are typical. A half-wave or folded half-wave dipole is the
active element. The array consists of parallel dipoles, all lying in the same plane. The reflector,
which reflects waves back toward the active element, enhances radiation in the axis of the array
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z Figure 15.1.9 Typical radiation pattern

in one principal plane as a function of
θ. (a) Polar-coordinate plot. (b) Linear-
ity
Main Relative radiation
ens
1.0 coordinate plot.
ion ve
lobe intensity (dB)
iat elati
int
θ 0
θ
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
θB θB
−0.5
rad
Side Main
Side lobe lobes lobe
x
(a) (b)
(+z-direction). The radiation pattern, with linear polarization, exhibits a principal lobe in the
+z-direction. The other elements, called directors, are designed to enhance radiation in the +z
direction. Gain increases with the number of elements and is often in the range of 10 to 20 dB.
The bandwidth is usually small.
Both conical-horn and pyramidal-horn (aperture-type) antennas are mainly used as illumi-
nators for large-aperture paraboloidal antennas, which are capable of generating very narrow
beamwidth patterns (with even less than 1° in angle-tracking radars). When a parabola is rotated
about the z-axis [see Figure 15.1.17(g)], a surface of revolution known as a paraboloid results.
With the source at the focus called the feed, the radiation pattern is mainly a dominant lobe in
the z-direction with smaller side lobes. Paraboloidal antennas have found wide use as antennas
for radar and communications. The Cassegrain antenna [shown in section in Figure 15.1.17(h)]
is a variation of the paraboloid that gives improved system performance. The feed in this case
is moved to the rear of the antenna, and it illuminates a conducting surface (subreflector in the
shape of a hyperboloid) placed near the focus.
Noise in receiving systems exists in two broad categories: (i) that originated external to the
system (i.e., the one generated by the antenna in response to random waves from cosmic sources
and atmospheric effects), and (ii) internally generated noise (i.e., the one generated within all
circuits making up the receiver, including transmission lines and amplifiers). It is common to
model internal noise as having been generated by an external source.
Figure 15.1.11(a) shows a typical receiving system with noise. The antenna is a source of noise
with effective noise temperature Ta, known as the antenna temperature. Whatever receiving path
components (such as transmission lines, waveguides, and filters) are present prior to the receiver’s
amplifier, their noise effect is represented by a noisy loss Lr (≥ 1) between points A and B, while
the loss is assumed to have a physical temperature TL. The noisy receiver is supposed to operate at
a nominal center frequency f 0, and have available power gain Ga(f ) as a function of the frequency,
with Ga(f 0) as center-frequency power gain. N ao represents the total available output noise power
in Figure 15.1.11(a).
Figure 15.1.11(b) shows the noise-free model in a small frequency band df. Here k is the
Boltzmann constant (see Section 14.3), and TR(f ) is the effective input noise temperature (to the
noise-free receiver).
Figure 15.1.11(c) gives the noise-free model with noise bandwidth BN (a rectangular passband
of width BN in hertz centered on f 0). The actual receiver is replaced by an idealized one with the
same nominal power gain Ga(f 0) and a constant (average) effective input noise temperature T̄R ,
which is related to the average standard noise figure F0;
T̄R = 290(F0 − 1) (15.1.28)
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y y y
x x x
−
E
− −
E E
z z z
(a) (b) (c)
Figure 15.1.10 Polarizations of the electric field. (a) Vertical polarization.
(b) Horizontal polarization. (c) General linear polarization.
Antenna with antenna temperature Ta Figure 15.1.11 (a) Receiving

system with noise. (b) Noise-
A B
free model in a small frequency
Noisy band df. (c) Noise-free model
Noisy loss Lr Nao
receiver
with noise bandwidth BN.
Physical temperature TL Available power gain Ga( f )
Center-frequency power gain Ga( f 0 )
(a)
A Noise-free B Noise-free
dNao
loss Lr receiver
TL Ga( f )
kTL( Lr − 1) df kTR df
(b)
Available noise power kTsysBN

--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Ga( f 0)
Nao = kTsysBN
Lr
Noise-free
A loss and receiver
Available power gain Ga( f 0)/Lr

Noise bandwidth BN
(c)
Note that both F0 and T̄R are measures of the noisiness of an amplifier. The noise figure F0 is
usually available, whereas the temperature T̄R may not be given. In an ideal noise-free unit, F0 = 1
and T̄R = 0.
The system noise temperature T sys, which is the equivalent noise temperature of the antenna,
can now be introduced such that
Tsys = Ta + TL (Lr − 1) + T̄R Lr (15.1.29)
and all available output noise power is emanating from the antenna, as illustrated in Figure
15.1.11(c). Now the available system noise power becomes kT sysBN at point A; the noise-free
receiver has available power gain Ga (f0 )/Lr with noise bandwidth BN; and the output noise
power is given by
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15.2 ANALOG COMMUNICATION SYSTEMS 685
kTsys BN Ga (f0 )
Nao = (15.1.30)
Lr
The signal-to-noise power ratio at the system output is an excellent measure of performance
for many communication systems. The available signal power at point A in Figure 15.1.11(a) is
given by
P t G t G r λ2
SA = (15.1.31)
(4π )2 R 2 Lt Lta Lch Lra
based on Equation (15.1.24). The available noise power at point A is given by
NaA = kTsys BN (15.1.32)
Thus, the system performance with noise is measured by the signal-to-noise power ratio,

S Pt G t G r λ 2
= (15.1.33)
N A (4π )2 R 2 Lt Lta Lch Lra kTsys BN
15.2 ANALOG COMMUNICATION SYSTEMS

An analog message is a continuum of possible amplitudes at any given time, and analog signals
are continuous in time and in amplitude, such as audio and video signals. When the message to
be sent over a communication system is analog, we refer to the system as analog. The transmitted
waveform must be some function of the message so that the receiver could decipher the message.
Usually the transmitted waveform is the result of varying either the amplitude, phase, or frequency
of a basic signal called a carrier. Combinations of amplitude, phase, and frequency variations are
also possible.
The carrier usually is sinusoidal of the form Ac cos (ωc t +φc ), where Ac , φc , and fc = ωc /2π
are the carrier’s amplitude, phase, and frequency, respectively. When A is varied as a linear function
of the message, amplitude modulation (AM) occurs. In phase modulation (PM) a phase term that
is a linear function of the message is added to the carrier. When the added phase is a linear function
of the integral of the message, the result is known as frequency modulation (FM). Note that the
carrier’s frequency in FM is a linear function of the message, because instantaneous angular
frequency is the time derivative of instantaneous phase. Thus, FM and PM are closely related.
Every communication system has a modulator at the transmitting station to structure the
transmitted waveform, and a demodulator (detector) at the receiving end to recover the message
from the received signal. Radio (AM and FM) and television broadcasting are the most familiar
forms of communication through analog signal transmission. The FCC in the United States
regulates the carrier-frequency assignments in order to minimize the interference between nearby
stations. Commercial AM radio broadcasting utilizes the frequency band of 535 to 1605 kHz for
the transmission of voice and music. The carrier-frequency allocations range from 540 kHz to
1600 kHz, with 10-kHz spacing. Each station can occupy a channel bandwidth of only 10 kHz
centered on its carrier. Even though the baseband message signal is limited to a bandwidth of about
5 kHz, the AM broadcasting system adequately meets the need for low-cost mass communication
and general audio entertainment, in spite of lacking high-fidelity behavior.
Commercial FM radio broadcasting utilizes the frequency band of 88 to 108 MHz for the
transmission of music and voice signals. The carrier frequencies are separated by 200 kHz, and the
peak frequency deviation is fixed at 75 kHz. Each station (out of the possible 100) broadcasts in
a channel bandwidth of 200 kHz centered on the carrier. The FM system is capable of presenting
higher quality audio to the user than AM because of the larger audio band allowed from 50 Hz to
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15 kHz. Distortion at most stations is below 1%. Besides broadcast applications, FM is also used
in satellite links, aircraft altimetry, radars, amateur radio, and various two-way radio applications.
Because of the larger bandwidth (up to 20 times more than in AM), an FM system has more
freedom from interference and better performance in noise than any AM station.
Commercial television broadcasting is allocated frequencies that fall in the VHF and UHF
bands. Table 15.2.1 lists the television channel allocations in the United States, with the channel
bandwidth of 6 MHz. In contrast to radio broadcasting, television signal-transmission standards
vary from country to country. The U.S. standard is set by the National Television Systems Com-
mittee (NTSC). Commercial television broadcasting began as black-and-white (monochrome)
picture transmission in London in 1936 by the British Broadcasting Corporation (BBC). Although
color television was demonstrated a few years later, due to the high cost of color television
receivers, color television signal transmission was slow in its development. With the advent of
the transistor and microelectronic components, the cost of color television receivers decreased
significantly, and by the middle 1960s, color television broadcasting was widely used by the
industry. The NTSC color system is compatible with monochrome receivers, so that the older
monochrome receivers still function receiving black-and-white images out of the transmitted
color signal.
Amplitude Modulation (AM)

In AM the message signal is impressed on the amplitude of the carrier signal. There are several
different ways of amplitude modulating the carrier signal by the message signal, each of which
results in different spectral characteristics for the transmitted signal. Four methods are:
• Conventional (standard) double-sideband AM
• Double-sideband suppressed-carrier AM
• Single-sideband AM
• Vestigial-sideband AM.
AM, as its name implies, carries the modulating signal x(t) in a time-varying amplitude of
the form
a(t) = Ac [1 + mA x(t)] (15.2.1)
where the constant Ac stands for the unmodulated carrier amplitude, and mA is the modulation
index. The resulting modulated wave is
xc (t) = a(t) cos(2πfc t + φc )
= Ac cos(2πfc t + φc ) + Ac mA x(t) cos(2πfc t + φc ) (15.2.2)
TABLE 15.2.1 VHF and UHF Allocations for

Commercial TV in the United States
Frequency Band
Channel (6-MHz bandwidth/station)
VHF 2–4 54–72 MHz

VHF 5–6 76–88 MHz
VHF 7–13 174–216 MHz
UHF 14–69 470–896 MHz
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whereas the sinusoidal carrier waveform is given by

c(t) = Ac cos(ωc t + φc ) = Ac cos(2πfc t + φc )
Sometimes the standard AM signal is expressed in the form of
xc (t) = sAM (t) = [Ac + f (t)] cos(ωc t + φc ) (15.2.3)
in which the total amplitude of the carrier [Ac + f (t)] is a linear function of the message. Figure
15.2.1 illustrates the AM waveforms.
If the maximum amplitude of f (t) in Equation (15.2.3) exceeds Ac, overmodulation is said
to occur. In order to prevent excessive distortion in the receiver, overmodulation is avoided in
standard AM by requiring
|f (t)|max ≤ Ac (15.2.4)
such that the envelope of sAM(t) or xc(t) will never go negative and may at most become zero.
The spectral behavior is depicted in Figure 15.2.2, assuming φ0 = 0 for simplicity. The spectral
impulses are due to the carrier and will always be present, even if the message were to disappear.
The effect of AM is to shift half-amplitude replicas of the signal spectrum out to angular
frequencies ωc and −ωc . The band of frequencies above ωc or below −ωc is called the upper
sideband (USB). The one on the opposing side is known as the lower sideband (LSB). Since AM
transmits both USB and LSB, it is known as double-sideband modulation. If the maximum circular
(radian) frequency extent of f (t) is Wf rad/s, the frequency extent of the standard AM waveform
is 2Wf. Thus, the low-pass signal is translated in frequency to the passband of the channel so that
the spectrum of the transmitted bandpass signal will match the passband characteristics of the
channel.
There are several different methods for generating amplitude-modulated signals. Since the
process of modulation involves the generation of new frequency components, modulators are
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generally characterized as nonlinear and/or time-variant systems, because a linear or a time-
invariant system cannot create new frequencies other than those contained in its input signal.
Figure 15.2.3 shows a block diagram of power-law modulation that is nonlinear. Let the voltage
input to such a device be the sum of the message signal and the carrier, as illustrated in
Figure 15.2.3. The nonlinear device (that has an input–output characteristic of the form of
a square law) will generate a product of the message x(t) with the carrier, plus additional
terms. The desired modulated signal can be filtered out by passing the output of the nonlinear
device through a bandpass filter. The signal generated by this method is a conventional DSB
AM signal.
x (t) Figure 15.2.1 AM waveforms. (a) Information (message or

modulating) signal. (b) Modulated wave (corresponding stan-
t dard AM signal).
(a)
xc (t) Envelope |A(t)|

Ac
t
−Ac
(b)
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Amplitude spectrum Figure 15.2.2 Spectral behavior. (a) Informa-

1 tion-signal spectrum. (b) Corresponding AM
Lower sideband (LSB) Upper sideband (USB) signal spectrum.
0 ω
(a)
Amplitude spectrum
Spectral impulse Spectral impulse
due to carrier due to carrier
1
2
USB LSB LSB USB
−ωc 0 ωc ω
(b)
Nonlinear
Message signal Bandpass Conventional
device
x (t) + filter tuned
such as a DSB AM signal
P–N diode to fc
Ac cos 2π fc t
Figure 15.2.3 Block diagram of power-law modulation.
Let sAM(t) of Equation (15.2.3) be a voltage representing the wave that excites the transmitting
station’s antenna, which is assumed to represent a resistive impedance R0 to the transmitter that
feeds it. The power in sAM(t) is found by
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2
sAM (t) 1 2
PAM = = Pc + Pf = Ac + f 2 (t) (15.2.5)
R0 2R0
in which the overbar represents the time average, and f (t) is assumed to have no dc component,
as is the usual case. Pc = A2c /2R0 is the power in the carrier, and Pf = f 2 (t)/2R0 is the added
power caused by modulation. Pf is called the useful power, since only this power caused by the
message contributes toward message quality. Pc, the carrier power, is not useful power in the
sense that it carries no information. However, it is important to the receiver’s ability to recover
the message with low-cost circuitry. Modulation efficiency ηAM of the transmitted signal is defined
as the ratio of the useful power to the total power,
Pf f 2 (t)
ηAM = = (15.2.6)
Pc + Pf A2c + f 2 (t)
When f (t) is a square wave of peak amplitude Ac, the largest possible value of ηAM equal to 0.5,
or 50%, occurs. When f (t) is a sinusoid, ηAM ≤ 1/3, as shown in Example 15.2.1. For practical
audio (voice and music) messages, efficiency could be less than 1/3.
Copyright OUP
EXAMPLE 15.2.1
Let f (t) be a sinusoid given by f (t) = Am cos ωm t with period Tm = 2π/ωm . Apply Equation
(15.2.6) and obtain the value of ηAM .
Solution
Tm /2
1
f 2 (t) = A2m cos2 (ωm t) dt
Tm −Tm /2
2π
A2m A2m
= (1 + cos x) dx =
8π −2π 2
A2m (Am /Ac )2
ηAM = =
2A2c + A2m 2 + (Am /Ac )2
For no overmodulation, Am ≤ Ac , so that ηAM ≤ 1/3.
Suppressed-carrier AM, also known as double-sideband suppressed-carrier (DSB SC AM),

results when the carrier term Ac in Equation (15.2.3) is eliminated. The DSB waveform is then
given by
sDSB (t) = f (t) cos(ωc t + φc ) (15.2.7)
Figure 15.2.4(a) depicts the waveforms of the message signal and its amplitude spectrum; Figure
15.2.4(b) shows the DSB waveform sDSB(t), and Figure 15.2.4(c) displays the amplitude spectrum
of sDSB(t). From Equation (15.2.6) with Ac = 0, the efficiency of DSB SC AM comes out as 1.0,
or 100%. While the power efficiency is increased, there will be added complexity, especially in
the demodulator.
Amplitude spectrum Figure 15.2.4 (a) Message signal and its

amplitude spectrum. (b) DSB SC sig-
f (t) LSB USB nal sDSB(t) corresponding to the message.
(c) Corresponding SC AM signal spectrum.
t ω
0 0
Message signal
(a)
sDSB(t) Phase reversal when f (t) changes sign
(b)
Amplitude spectrum of sDSB(t)

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USB LSB LSB USB

ω
−ωc 0 ωc
(c)
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A relatively simple method to generate a DSB SC AM signal is by employing two (identical)

conventional AM modulators, such as two square-law AM modulators, arranged in the config-
uration of Figure 15.2.5, which is known as a balanced modulator. φc = 0 is assumed here for
simplicity.
Single-sideband (SSB) AM is obtained by filtering one sideband of the DSB signal. As pointed
out earlier, a DSB SC AM signal required a channel bandwidth of 2W for transmission, where
W is the bandwidth of the baseband signal. However, the two sidebands are redundant. The
transmission of either sideband is sufficient to reconstruct the message signal at the receiver.
Thus, the bandwidth of the transmitted signal is reduced to that of the baseband signal. Figure
15.2.6 illustrates the generation of an SSB AM signal by filtering one of the sidebands (either
USB or LSB) of a DSB SC AM signal. SSB is popular with amateur radio operators because of
its high efficiency (ηSSB = 1) and bandwidth savings.
Vestigial-sideband (VSB) AM is a variation of SSB where a small portion (or vestige) of
the filtered sideband is allowed to remain. The stringent frequency-response requirements on the
sideband filter in an SSB AM system can be relaxed by allowing a part, known as a vestige, of
the unwanted sideband to appear at the output of the modulator. Thus, the design of the sideband
filter is simplified at the cost of a modest increase in the channel bandwidth required to transmit
the signal. Figure 15.2.7 illustrates the generation of a VSB AM signal. VSB is mainly used in the
x (t) AM Ac [1 + x (t)] cos 2π fc t Figure 15.2.5 Block diagram of

modulator a balanced modulator.
Message signal
+ 2Ac x(t) cos 2π fc t
−
Ac cos 2π fc t
−x (t) AM
modulator Ac [1 − x (t)] cos 2π fc t
cos (ωc t + φc)
Gain = 2
f (t) Balanced sDSB(t) High-pass sSSB(t)
Message modulator filter H(ω)
signal
SDSB(ω) H(ω) SSSB(ω)
ω ω ω
−ωc 0 ωc −ωc 0 ωc −ωc 0 ωc
Figure 15.2.6 Generation of a SSB AM signal by filtering one of the sidebands of a

DSB SC AM signal.
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television broadcast system. The generation of VSB is similar to the generation of SSB, except
that the sideband-removal filter has a slightly different transfer function.
Message Demodulation
The major advantage of the conventional (standard) DSB AM signal transmission is the ease with
which the signal can be demodulated. The message signal is received by passing the rectified signal
through a low-pass filter whose bandwidth matches that of the message signal. The combination of
the rectifier and the low-pass filter is known as an envelope detector, which is almost universally
used. A standard AM envelope detector consisting of a diode and an RC circuit (which is basically
a simple low-pass filter) and its response are shown in Figure 15.2.8.
During the positive half-cycle of the input signal, the diode is conducting and the capacitor
charges up to the peak value of the input signal. When the input falls below the voltage on the
capacitor, the diode becomes reverse-biased and the input becomes disconnected from the output.
During this period, the capacitor discharges slowly through the load resistor R. On the next cycle
of the carrier, the diode conducts again when the input signal exceeds the voltage across the
capacitor. The capacitor charges up again to the peak value of the input signal, and the process is
continued. The time constant RC must be selected to follow the variations in the envelope of the
carrier-modulated signal. Generally, it is so chosen that
Balanced Figure 15.2.7 Generation of a VSB AM

modulator signal.
x(t) Sideband
× filter VSB AM signal
Message H(ω)
signal
Ac cos 2π fc t
Voltage proportional to sAM(t)
R C sd (t)
(a)
sd (t) Proportional to
Ac + f (t) Envelope
Carrier
Ac
t
(b)
Figure 15.2.8 Envelope detection of conventional (standard) AM signal.
(a) Standard AM envelope detector. (b) Its response.
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1 1
<< RC << (15.2.8)
fc W
The simplicity of the demodulator has made conventional DSB AM a practical choice for AM
radio broadcasting. A relatively inexpensive demodulator is very important in view of the several
billions of radio receivers. With only a few broadcast transmitters and numerous receivers, the
power inefficiency of conventional AM is justified. Thus, it is cost-effective to construct powerful
transmitters and sacrifice power efficiency in order to have simpler signal demodulation at the
receivers.
Demodulation of DSB SC AM signals requires a synchronous demodulator, which is also
known as coherent or synchronous detector. That is, the demodulator must use a coherent phase
reference. This is usually generated by means of a phase-locked loop (PLL), which forces the
phase of the voltage-controlled oscillator to follow the phase of the reference signal, to demodulate
the received signal. The need for such a device is a chief disadvantage of the DSB SC scheme.
Figure 15.2.9 shows the general configuration. A PLL is utilized to generate a phase-coherent
carrier signal that is mixed with the received signal in a balanced modulator. The output of the
balanced modulator is fed into a low-pass filter of bandwidth W, which passes the desired signal
and rejects all signal (and noise) components above W Hz.
Demodulation of SSB signals also requires the use of a phase-coherent reference. Figure
15.2.10 shows the general configuration to demodulate the SSB signal. A small carrier component,
which is transmitted along with the message, is inserted. A balanced modulator is used for
frequency conversion of the bandpass signal to low pass or baseband.
Demodulation of VSB signals generally uses a synchronous detector in the configuration of
Figure 15.2.10. In VSB, a carrier component is generally transmitted along with the message
sidebands. The existence of the carrier component makes it possible to extract a phase-coherent
reference for demodulation in a balanced modulator. In some applications, such as television
broadcasting, however, a large carrier component is transmitted along with the message in the
VSB signal, and in such a case it is possible to recover the message by passing the received signal
through an envelope detector.
Message Figure 15.2.9 Demodulator for

sDSB(t) Balanced Low-pass signal the DSB SC AM signal.
Received modulator filter x(t)
signal
Phase-locked
loop
Message Figure 15.2.10 Demodulation of

sSSB(t) Balanced Low-pass signal SSB AM signal with a carrier
Received modulator filter component.
x(t)
signal
Estimate
carrier
component
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From the noise performance point of view, all the AM systems yield the same performance
for the same messages and transmitted powers. Note, however, that the bandwidth of the DSB
system is twice that of the SSB or VSB systems, so its input noise power is twice as large.
Frequency Modulation
So far we have considered AM of the carrier as a means for transmitting the message signal.
AM methods are also known as linear modulation methods, although conventional AM is not
linear in the strict sense. Other classes of modulation methods are frequency modulation (FM)
and phase modulation (PM). In FM systems the frequency of the carrier fc is changed by the
message signal, and in PM systems the phase of the carrier is changed according to the variations
of the message signal. FM and PM, which are quite nonlinear, are referred to as angle-modulation
methods. Angle modulation is more complex to implement and much more difficult to analyze
because of its inherent nonlinearity. FM and PM systems generally expand the bandwidth such
that the effective bandwidth of the modulated signal is usually many times the bandwidth of the
message signal. The major benefit of these systems is their high degree of noise immunity. Trading
off bandwidth for high-noise immunity, the FM systems are widely used in high-fidelity music
broadcasting and point-to-point communication systems where the transmitter power is rather
limited.
A sinusoid is said to be frequency-modulated if its instantaneous angular frequency ωF M (t)
is a linear function of the message,
ωFM (t) = ωc + kFM f (t) (15.2.9)
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where k FM is a constant with units of radians per second per volt when f (t) is a message-signal
voltage, and ωc is the carrier’s nominal angular frequency. Instantaneous phase being the integral
of instantaneous angular frequency, the FM signal can be expressed as

SFM (t) = Ac cos ωc t + φc + kFM f (t) dt (15.2.10)
where Ac is a constant amplitude and φc is an arbitrary constant phase angle. The maximum
amount of deviation that ωFM (t) of Equation (15.2.9) can have from its nominal value is known
as peak frequency deviation, given by
?ω = kFM |f (t)|max (15.2.11)
Because FM involves more than just direct frequency translation, spectral analysis and bandwidth
calculations are difficult in general, except for a few message forms. However, practical experience
indicates that the following relations hold for the FM transmission bandwidth:
WFM ∼
= 2(?ω + Wf ) (15.2.12)
known as Carson’s rule for narrow-band FM with ?ω < Wf or
WFM ∼
= 2(?ω + 2Wf ) (15.2.13)
for wide-band FM with ?ω >> Wf , where Wf is the spectral extent of f (t); i.e., the message
signal has a low-pass bandwidth Wf. For example, commercial FM broadcasting utilizes Wf =
2π(15 × 103 ) rad/s (corresponding to 15 kHz) and ?ω = 5Wf such that ωFM = 14Wf . Because
the performance of narrow-band FM with noise is roughly equivalent to that of AM systems, only
wide-band FM that exhibits a marked improvement will be considered here.
Figure 15.2.11 illustrates the close relationship between FM and PM. Phase modulating
the integral of a message is equivalent to the frequency modulation of the original message,
Copyright OUP
f (t) FM f (t) PM
≡ Integrator
Message modulator modulator
signal
f (t) PM f (t) FM
modulator ≡ Differentiator modulator
Figure 15.2.11 Close relationship between FM and PM.
and frequency modulating the derivative of a message is equivalent to phase modulation of the
message itself.
Generation of wide-band FM can be done by various means. However, only the most common
and conceptually the simplest one, known as the direct method, is considered here. It employs
a voltage-controlled oscillator (VCO) as a modulator. A VCO is an oscillator whose oscillation
frequency is equal to the resonant frequency of a tuned circuit, as shown in Figure 15.2.12. The
frequency can be varied if either the inductance or the capacitance is made voltage-sensitive to
the message signal f (t).
One approach to obtaining a voltage-variable reactance is through a varactor diode, whose
capacitance changes with the applied voltage, such as the junction capacitance of a reverse-
biased diode, which depends on the amount of bias. Figure 15.2.13 illustrates the varactor-diode
implementation of an angle modulator. The frequency of the tuned circuit and the oscillator will
change in accordance with the message signal f (t). Varactor-controlled VCOs can have a nearly
linear frequency–voltage characteristic, but often yield only small frequency deviations, i.e., small
?ω. Since any VCO is inherently unstable as its frequency is varied to produce FM, it becomes
necessary in many applications to stabilize the carrier’s frequency.
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Demodulators for FM
Figure 15.2.14 shows a block diagram of a general FM demodulator, which is implemented by
generating an AM signal whose amplitude is proportional to the instantaneous frequency of the
FM signal, and then using an AM demodulator to recover the message signal. Transforming
Figure 15.2.12 Oscillator for use

in a VCO.
Active Output proportional to cos ωt

L C oscillator
circuit where ω = 1
√LC
Resonant
circuit
. . . Figure 15.2.13 Varactor-diode implementation of an angle

Cv modulator.
To
+ C0 L oscillator
f (t ) circuit
−
. . .
Copyright OUP
the FM signal into an AM signal can be achieved by passing the FM signal through an LTI
system whose frequency response is nearly a straight line in the frequency band of the FM
signal.
FM demodulators mainly fall into two categories: frequency discriminators and locked-loop
demodulators. While both give the same performance for relatively high signal levels, locked-
loop demodulators provide better performance than the discriminator when signal levels are
low and noise is a problem. The discriminator produces an output voltage proportional to the
frequency variations that occur in the FM signal at its input. Locked-loop demodulators are more
cost-efficient when implemented in IC form.
A balanced discriminator with the corresponding frequency characteristics is depicted in
Figure 15.2.15. The rising half of the frequency characteristic of a tuned circuit, shown in Figure
15.2.15(b), may not have a wide enough linear region. In order to obtain a linear characteristic
over a wider range of frequencies [see Figure 15.2.15(d)], usually two circuits tuned at two
frequencies f 1 and f 2 [with the frequency response shown in Figure 15.2.15(c)] are used in a
balanced discriminator [Figure 15.2.15(a)].
Figure 15.2.16 shows a block diagram of an FM demodulator with feedback (FMFB), in
which the FM discrimination is placed in a feedback system that uses a VCO path for feedback.
The bandwidth of the discriminator and the subsequent low-pass filter is matched with that of the
message signal, which is the output of the low-pass filter.
An alternative to the FMFB demodulator is the use of a PLL, as shown in Figure 15.2.17,
in which the phase of the VCO’s output signal is forced to follow (or lock to) the phase of
the input FM waveform with small error. Since the VCO acts as an integrator, and phase
is the integral of frequency, the amplified error voltage appearing at the VCO input will be
proportional to the message signal f (t). The filter is selected with a closed-loop bandwidth that
is wide enough to yield demodulation with minor distortion of f (t), and narrow enough to reject
noise.
The signal and noise components, particularly at low SNRs, are so intermingled that one
may not be able to distinguish the signal from the noise. In such a case, a mutilation or threshold
effect is said to be present. There exists a specific SNR at the input of the demodulator known as
the threshold SNR, beyond which signal mutilation occurs. The threshold effect then places an
upper limit on the tradeoff between bandwidth and power in an FM system. Since the thresholds
for locked loops are lower than for the discriminator, loop-type receivers, operating at smaller
signal-power levels, find wide application in space communications where transmitter power is
at a premium.
At the output of the discriminator in an FM receiver, higher frequency components of output
noise power are accentuated. A low-pass filter, known as a deemphasis filter, is added so that
the large-amplitude noise can be greatly reduced and the output SNR increased. Since the filter
also acts on the message, causing distortion, the message at the transmitter is passed through
a compensating filter, called a preemphasis filter, before modulation occurs. It accentuates the
higher frequencies in the message so as to exactly compensate for the effect of the deemphasis
filter, so that there is no overall effect on the message (see also Section 14.3). The scheme is
illustrated in Figure 15.2.18.
FM signal Figure 15.2.14 Block diagram of a general FM

FM to AM AM signal AM Output
convertor demodulator signal demodulator.
input
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Bandpass filters Envelope detectors

R D
L1 C1 Re Ce
sFM(t) Message
FM signal f (t)
signal
L2 C2 Re Ce
R D
(a)
Amplitude response
|H1( f )|
f
f1
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Linear region
(b)
Amplitude response
|H2( f )| |H1( f )|
f
f2 f1
(c)
|H( f )| = |H1( f )| − |H2( f )| |H1( f )|

Amplitude response
−|H2( f )|
Linear region
(d)
Figure 15.2.15 Balanced discriminator with the corresponding frequency response.
Copyright OUP
Bandpass Low-pass
× filter
Discriminator
filter
Received Ouput
FM signal signal
VCO
Figure 15.2.16 Block diagram of an FMFB demodulator.
Phase Amplifier and Output ∝ f (t)

Input SFM(t) Error voltage
detector low-pass filter
with input (comparator) ∝ phase shift (loop filter)
phase φ(t)
VCO
Output phase φ(t)
Figure 15.2.17 Block diagram of a PLL FM demodulator.

--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Preemphasis Amplifier Deemphasis

f (t) FM Channel FM f (t)
filter of voltage
modulator
.... demodulator
filter
Hp(ω) gain K Hd (ω)
Figure 15.2.18 Schematic block diagram of an FM system with emphasis filters.
EXAMPLE 15.2.2
A common deemphasis filter used in FM broadcast has a transfer function
1
Hd (ω) =
1 + j (ω/W1 )
where W1 /2π = 2.12 kHz. For perfect message recovery, the preemphasis filter must have a
transfer function

1 ω
Hp (ω) = =1+j
Hd (ω) W1
over all important frequencies (out to about 15–20 kHz). The system performance improvement
with these filters for voice-type messages is given by
SNR with emphasis (Wf /W1 )3
RF M = =
SNR with no emphasis 3 (Wf /W1 ) − tan−1 (Wf /W1 )

where Wf is the spectral extent of f (t). However, for broader band messages, such as music audio,
since the channel bandwidth in FM broadcast is limited to 200 kHz, a reduction in the improvement
factor occurs, when it can be shown that
RFM with bandwidth limitation 1
=
RFM with no bandwidth limitation 1 + (Wrms /Wf )2 (Wf /W1 )2
Copyright OUP
where W rms is the rms bandwidth of f (t). Given W1 /2π = 2.12 kHz, Wf /2π = 15 kHz, and
Wrms /2π = 4.25 kHz, determine RFM with and without bandwidth constraints.
Solution
(15/2.12)3
RFM =
∼
= 20.92, or 13.2 dB
(with no bandwidth constraint) 3 (15/2.12) − tan−1 (15/2.12)
20.92 ∼
RFM = = 4.17, or 6.2 dB
(with bandwidth limitation) 1 + (4.25/15)2 (15/2.12)2
Thus, the bandwidth constraint has resulted in a loss in emphasis improvement of 13.2 − 6.2 =
7 dB.
FM Stereo
Figure 15.2.19 shows the block diagram of an FM stereo transmitter and an FM stereo receiver.
The following notation is used:
• fL(t), fR(t): Left and right messages that undergo preemphasis and are then added to yield
f 1(t) and differenced to give fd(t).
• f 2(t): Given by signal fd(t) when it DSB-modulates (with carrier suppressed) a 38-kHz
subcarrier.
• f 3(t): A low-level pilot carrier at 19 kHz that is included to aid in the receiver’s demodulation
process.
• fs(t): Final composite message when f 1(t), f 2(t), f 3(t), and SCA (subsidiary communications
authorization) are all added up.
• SCA: A narrow-band FM waveform on a 67-kHz subcarrier with a total bandwidth of
16 kHz. It is a special signal available to fee-paying customers who may desire to have
background music free of commercials or nonaudio purposes such as paging.
• NBPF: Narrow-band band-pass filter.
• LPF, BPF, and NBPF: Appropriate filters that select the spectrum portions corresponding
to f 1(t), f 2(t), and f 3(t), respectively.
The output signal-to-noise power ratio is smaller in FM stereo than in a monaural system
with the same transmitted power, messages, and other parameters. With a loss as high as 22 dB,
many FM stations can tolerate the loss because of the high power being transmitted.
Comparison of Analog-Modulation Systems

The comparison of analog modulation systems (conventional AM, DSB SC, SSB SC, VSB, FM,
and PM) can be based on three practical criteria:
1. Bandwidth efficiency of the system.

2. Power efficiency of the system, as reflected in its performance in the presence of noise.
The output SNR at a given received signal power is used as a criterion for comparing the
power efficiencies of various systems.
3. Ease of implementation of the system (transmitter and receiver).
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Preemphasis +
fL(t) Σ
KHp(ω)
+ f1(t)
SCA
+
+ fd (t) f2(t) +
Preemphasis DSB FM
fR(t) Σ Σ
KHp(ω) − modulator + modulator
+
f3(t) f4(t)
2
19-kHz pilot sFM(t)
38-kHz
oscillator
(a)
0–15 kHz
f1(t) 2fL(t)
LPF Σ Deemphasis Hd (ω)
+
Synchronous detector +
fs (t) 23–53 kHz 0–15 kHz
f2(t) + 2fR (t)
sFM(t) FM demodulator BPF Product LPF Σ Deemphasis Hd (ω)
−
f3(t) fd (t)
19 kHz
NBPF × 2 multiplier 38-kHz subcarrier

A B
Local-carrier recovery
or
Replaced by phase-locked loop
Phase detector LPF 38-kHz VCO

A B
÷2
(b)
Figure 15.2.19 (a) FM stereo transmitter. (b) FM stereo receiver.
The most bandwidth-efficient analog communication system is the SSB SC system with a
transmission bandwidth equal to the signal bandwidth. In bandwidth-critical applications, such
as voice transmission over microwave and satellite links and some point-to-point communication
systems in congested areas, this system is used widely. When transmission signals have a
significant dc component, such as image signals, SSB SC cannot be used because it cannot
effectively transmit direct current. A good compromise is the VSB system (with its bandwidth
slightly larger than SSB and a capability for transmitting dc values), which is widely used in
television broadcasting and some data-communication systems. When bandwidth is the major
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concern, PM and particularly FM systems are least favorable. Only in terms of their high level of
noise immunity, their usage may sometimes be justified.
FM, with its high level of noise immunity, and hence power efficiency, is widely used
on high-fidelity radio broadcasting and power-critical communication links such as point-to-
point communication systems. It is also employed for satellite links and voice transmission on
microwave LOS systems. When the transmitted power is a major concern, conventional AM
and VSB (being the least power-efficient systems) are not used, unless their development can be
justified by the simplicity of the receiver structure.
From the viewpoint of ease of implementation, the simplest receiver structure is that of
conventional AM. Standard AM, VSB, and FM are widely used for AM, television, and high-
fidelity FM broadcasting. The relative power inefficiency of the AM transmitter is compensated
for by the extremely simple structure of several billions of receivers. The receiver structure
is much more complicated for DSB SC and SSB SC systems, since they require synchronous
demodulation. These systems, therefore, are never used for broadcasting purposes. Note that
DSB SC also suffers from its relative bandwidth inefficiency.
Radio and Television Broadcasting

Radio (AM and FM) and television broadcasting are the most familiar forms of communication
via analog transmission systems. The receiver most commonly used in AM radio broadcasting is
the superheterodyne receiver, shown in Figure 15.2.20, which consists of a radio-frequency (RF)
tuned amplifier, mixer, local oscillator, intermediate frequency (IF) amplifier, envelope detector,
audio-frequency amplifier, and a loudspeaker. Tuning at the desired radio frequency fc is achieved
by a variable capacitor, which simultaneously tunes the RF amplifier and the frequency f LO of the
local oscillator. Every AM radio signal, in a superheterodyne receiver, is converted to a common IF
frequency of fIF = |fc − fLO | = 455 kHz, which allows the use of a single tuned IF amplifier for
signals from any radio station in the frequency band. Matching the bandwidth of the transmitted
signal, the IF amplifier is set to have a bandwidth of 10 kHz.
The frequency conversion to IF is done by the combination of the RF amplifier and the mixer.
The tuning range of the local oscillator is 955–2,055 kHz. f LO could be either higher or lower than
fc. If f LO is higher than fc, then fLO = fc + fIF . By tuning the RF amplifier to the frequency fc and
mixing its output with the local oscillator frequency f LO, we obtain two signal components: one
centered at the difference frequency f IF; and the other centered at the sum frequency 2fc + fIF ,
known as the image frequency. Only the first component is passed on by the IF amplifier. The
Audio
RF IF
Mixer Detector frequency
amplifier amplifier
amplifier
Loud speaker
Automatic
volume control
Local
oscillator
Common tuning
Figure 15.2.20 Superheterodyne receiver.
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image response is suppressed by using the antenna and other RF-tuned circuits as a filter. By
limiting the bandwidth of the RF amplifier to the range Bc < BRF < 2fIF , where Bc is the
bandwidth of the AM radio signal (10 kHz), the radio signal transmitted at the image frequency
(fc = fLO + fIF ) is rejected. A similar behavior occurs when f LO is lower than fc. Figure 15.2.21
illustrates the AM station and image frequencies for a high-side and a low-side local oscillator,
whereas Figure 15.2.22 depicts the frequency response characteristics of IF and RF amplifiers for
the case fLO > fc .
Amplifiers in the IF circuits provide most of the gain needed to raise the small antenna
signal to a level sufficient to drive the envelope detector. The output of the detector contains a
dc component proportional to Ac and a component proportional to the audio message f (t), the
amplified signal of which is used to drive the loudspeaker. The dc component is utilized in an
automatic volume control (AVC), otherwise known as automatic gain control (AGC), loop to
control the gain of RF and IF amplifiers by controlling their operating bias points. The loop action
is to maintain nearly a constant IF level at the detector’s input, even for large variations in antenna
voltage.
The IF amplifier, with its narrow bandwidth, provides signal rejection from adjacent channels,
and the RF amplifier provides signal rejection from image channels.
An FM radio superheterodyne receiver is shown in block diagram form in Figure 15.2.23.
The part consisting of the antenna, RF amplifier, mixer, and local oscillator functions in a manner
similar to that of an AM receiver, except that the frequencies involved are different. fIF = 10.7
MHz in FM, so that the image is 21.4 MHz from the carrier frequency fc. The RF amplifier must
eliminate the image-frequency band 2f IF away from the station to which the receiver is tuned.
The IF amplifier is generally divided into two parts. The higher level stage is set to limit at
a proper level to drive the demodulator. More expensive FM receivers may have AGC added to
RF-tuned circuit response Figure 15.2.21 AM radio station

and image frequencies. (a) High-
side local oscillator, fLO > fc .
fc fLO = fc + fIF (b) Low-side local oscillator,
fimage = fc + 2fIF fLO < fc .
f, kHz
0 500 1000 1500 2000
AM station frequencies
540 1600
(a)
fimage = fc − 2fIF fLO = fc − fIF fc
f, kHz
0 500 1000 1500 2000
AM station frequencies
540 1600
(b)
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Figure 15.2.22 Frequency response

characteristics of IF and RF ampli-
Bc fiers. (a) IF amplifier. (b) RF am-
plifier. (c) Desired signal and image
signal to be rejected.
f
0 fIF
(a)
BRF
BRF < 2fIF
f
0 fc = fLO − fIF
(b)
Bc
f
0 fc fLO f 'c = fLO + fIF
2fIF
(c)
reduce the gains of the RF and IF amplifier stages. A heavily filtered output from the demodulator
is often used to provide an automatic frequency control (AFC) loop through the local oscillator
that can be implemented to have electronic tuning by using a varactor. After manual tuning, the
AFC loop locks the receiver to the selected station. Finally, the response of the demodulator is
fed into the stereo demodulator, which is implemented as shown in Figure 15.2.19(b).
Television signals in television signal transmission are the electric signals generated by
converting visual images through raster (TV image area) scanning. The two-dimensional image
or picture is converted into a one-dimensional electric signal by sequentially scanning the image
and producing an electrical signal that is proportional to the brightness level of the image. A
television camera, which optically focuses the image on a photo cathode tube that consists of
a photosensitive surface, is used for scanning. An electron beam produces an output current or
voltage that is proportional to the brightness of the image, known as a video signal. The scanning
of the electron beam is controlled by two voltages, as shown in Figure 15.2.24, applied across
the horizontal and vertical deflection plates. In the raster scanning in an NTSC TV system, the
image is divided into 525 lines which define a frame, as illustrated in Figure 15.2.25. The resulting
signal is transmitted in 1/30 second. The number of lines determines the picture resolution and,
along with the rate of transmission, sets the channel bandwidth needed for image transmission.
However, the time interval of 1/30 second to transmit a complete image is not generally fast
enough to avoid flickering, which is annoying to the average viewer. Therefore, to overcome the
flickering, the scanning of the image is performed in an interlaced pattern, as shown in Figure
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Left loud
fIF = 10.7 MHz speaker
Antenna
Bandwidth 210 kHz
IF
RF IF FM Stereo
Mixer amplifier
amplifier amplifier demodulator demodulator
limiter
AGC Right loud

detector speaker
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Local
oscillator AFC
Frequency tuning
Figure 15.2.23 Block diagram of a superheterodyne FM radio receiver.
15.2.26, consisting of two fields, each of 262.5 lines. Each field is transmitted in 1/60 second. The
first field begins at point a and terminates at point b, whereas the second field begins at point c
and terminates at point d.
The image is scanned left to right and top to bottom in a system of closely spaced parallel
lines. When 242.5 lines are completed at the rate of 15,734.264 lines per second (63.556 µs per
line), the raster’s visual area is scanned once; this scan is called a field. While the next 20 lines
are not used for visual information, during that time of 1.27 ms special signals (testing, closed
captions, etc.) are inserted and the beam is retraced vertically to begin a new field (shown as the
second field in Figure 15.2.26). The raster (TV image area) has a standardized aspect ratio of
four units of width for each three units of height. Good performance is achieved when the raster
is scanned with 525 lines at a rate of 29.97 frames per second.
The television waveform representing one scan is illustrated in Figure 15.2.27. A blanking
pulse with a duration of 0.18 of the horizontal-sweep period Th is added to the visual voltage
generated by the camera. While the blanking pulse turns off the electron beam in the receiver’s
picture tube during the horizontal retrace time, an added sync (synchronization) pulse helps the
receiver to synchronize its horizontal scanning rate with that of the transmitter. Also, a burst of
at least 8 cycles of 3.579545 MHz, called the color burst, is added to the “back porch” of the
blanking pulse for synchronizing the receiver’s color circuits. The visual information fluctuates
according to the image between the “black level” and the “white level” set at 70.3% and 12.5%,
respectively, of the peak amplitude. An array of various sync pulses are added on top for both
horizontal and vertical synchronization purposes.
If a filter is added to the television camera optics, so that only the red color passes through, the
camera’s voltage becomes proportional to the intensity of the amount of red in the image. Three
such cameras, all synchronized and viewing the same image, are employed in color television
to decompose the image into its primary color components of red R, green G, and blue B. The
color receiver utilizes a picture tube with three electron beams and a phosphor having R, G,
and B components. While each beam excites one color of phosphor, at any spot in the image
the three colors separately glow with proper intensities in response to the three transmitted color
signals. The viewer’s eye effectively adds the three colors together to reproduce the original scene
in color.
Copyright OUP
t
10 µs
53.5 µs
(a)
t
15.4 ms
1.27 ms
(b)
Figure 15.2.24 Voltage waveforms. (a) Applied to horizontal deflection plate.
(b) Applied to vertical deflection plate.
Figure 15.2.25 Raster scanning in

an NTSC television system.
First field of frame 242.5 lines
Vertical retrace time

--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
(1.27 ms) 20 lines

525 Lines
per frame
Second field of frame 242.5 lines
Vertical retrace time

20 lines
(1.27 ms)
Now that the fundamentals needed in color television have been explained, it remains to be
seen how the signals are processed by the transmitter and the receiver.
A color television transmitter in a transmitting station is shown in Figure 15.2.28 in a block
diagram indicating the most important functions. A mixture of three primary-color signals (having
the visual signal bandwidth of about 4.2 MHz) are transmitted in the standard color television
system in terms of the following three linearly independent combinations generated by the matrix
circuit:
mY (t) = 0.30mR (t) + 0.59mG (t) + 0.11mB (t) (15.2.14)
mI (t) = 0.60mR (t) − 0.28mG (t) − 0.32mB (t) (15.2.15)
mQ (t) = 0.21mR (t) − 0.52mG (t) + 0.31mB (t) (15.2.16)
The following notation is being used:
• mY(t): Luminance signal, to which monochrome receivers respond, and which defines the
brightness (white or gray level) of the image.
• mI(t), mQ(t): Chrominance signals, which relate only to the color content of the image and
have bandwidths of about 1.6 and 0.6 MHz, respectively.
Copyright OUP
Beginning of Beginning of Figure 15.2.26 Interlaced scanning

first field second field pattern to avoid flickering.
a c
Retrace
Retrace
485 lines
in picture
b d
End of End of
first field second field
Color burst of 8 cycles Figure 15.2.27 TV waveform

minimum of 3.579545 MHz representing one horizontal line
of a raster scan.
Peak carrier level (100%)
Sync pulse
Blanking level (75%)
Reference black level (70.3%)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Visual signal
Reference white level (12.5%)

t
Visual signal
0.18 Th
Th = 63.556 µs
(one line)
• [m2I (t) + m2Q (t)]1/2 : Saturation or color intensity. A very deep red is saturated while red
diluted with white to give a light pink is nearly unsaturated.
• tan−1 [mQ (t)/mI (t)]: Hue or tint.
• SI(t), SQ(t): Filtered chrominance signals of mI(t), mQ(t) by low-pass filters. SI(t) modulates
a color subcarrier at a frequency of 3.579545 MHz ± 10 Hz via DSB.
Copyright OUP
Frequency Aural carrier

Color camera Audio
modulator
R mR(t) mY (t) fY (t)
R LPF Composite Standard
baseband fc (t) AM signal
0–4.2 MHz
VSB + +
G mG(t) mI (t) sI (t) DSB signal fI (t) + Visual LSB +
G Matrix LPF BPF Σ modulator filter Σ
+
0–1.6 MHz 2.0–4.2 MHz + VSB
B DSB fQ (t) Transmitted
mB(t) mQ (t) sQ (t)
B LPF BPF signal sTV(t)
DSB
0–0.6 MHz 3.0–4.2 MHz
Color-carrier −π Visual-carrier
Cameras for R, G, B oscillator 2 oscillator
Color filters for (R, G, B) 3.579545 MHz
Sync
÷ 455
2 generator
Horizontal sweep rate
÷ 525
2 Vertical (field) sweep rate
Figure 15.2.28 Color TV transmitter in a TV-transmitting station.
• fI(t): Nearly a VSB signal, when the DSB signal is filtered by the BPF of passband 2–4.2
MHz to remove part of the USB in the DSB.
• fQ(t): DSB signal that is produced when the other chrominance signal modulates a quad-
rature-phase version of the color subcarrier. This DSB signal passes directly through the
BPF with passband 3–4.2 MHz without any change.
• fY(t): Filtered luminance signal of mY(t) by an LPF.
• fc(t): Composite baseband waveform by adding fY(t), fI(t), fQ(t), and sync pulses. This has
a bandwidth of about 4.2 MHz and modulates a visual carrier by standard AM.
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The standard AM signal is then filtered to remove part of the lower sideband. The resulting
VSB signal and the audio-modulated aural carrier are added to form the final transmitted signal
STV(t). Figure 15.2.29 illustrates the spectrum of a color television signal.
A color television receiver is shown in Figure 15.2.30 in block diagram form, indicating only
the basic functions. The early part forms a straightforward superheterodyne receiver, except for
the following changes:
• The frequency-tuning local oscillator is typically a push-button-controlled frequency syn-
thesizer.
• IF circuitry in television is tuned to give a filter characteristic required in VSB modulation.
The filter shapes the IF signal spectrum so that envelope detection is possible. The output
of the envelope detector contains the composite visual signal fc(t) and the frequency-modulated
aural carrier at 4.5 MHz. The latter is processing in a frequency demodulator to recover the
audio information for the loudspeaker. The former is sent through appropriate filters to separate
Copyright OUP
6 MHz
assigned channel band
Video (visual)
carrier
Luminance 4.2 MHz
signal
Chrominance Audio
signal (FM)
Chrominance carrier
3.579545 MHz
1.25 MHz Audio carrier Color subcarrier
4.5 MHz
Figure 15.2.29 Spectrum of a color television signal.
out signals fY(t) and [fI(t) + fQ(t)], which is further processed by two synchronous detectors in
quadrature to recover SI(t) and SQ(t). An appropriate matrix combines fY(t), SI(t), and SQ(t) to yield
close approximations of the originally transmitted mR(t), mG(t), and mB(t). These three signals
control the three electron beams in the picture tube.
The output of the envelope detector is also applied to circuits that separate the sync signals
needed to lock in the horizontal and vertical sweep circuits of the receiver. The bursts of color
carriers are isolated such that a PLL can lock to the phase of the color carrier, and thereby provide
the reference signals for the chrominance synchronous detectors.
Mobil Radio Systems (Cellular Telephone Systems)

Today radio-based systems make it possible for mobile people to communicate via cellular
telephone systems while traveling on airplanes and motor vehicles. For radio telephone service,
the FCC in the United States has assigned parts of the UHF band in the range of 806–890 MHz.
For efficient use of the available frequency spectrum, especially in highly populated metropolitan
areas with the greatest demand for mobile telephone services, the cellular radio concept has been
adopted, in which a geographic area is subdivided into cells, each of which contains a base station,
as shown in Figure 15.2.31. Each base station is connected by telephone lines to a mobile telephone
switching office (MTSO), which in turn is connected through telephone lines to a telephone central
office of the terrestrial telephone network.
When a mobile user (identified by the telephone number and telephone serial number assigned
by the manufacturer) communicates via radio with the base station within the cell, the base station
routes the call through the MTSO to another base station if the called party is located in another
cell, or to the central office if the called party is not mobile. Once the desired telephone number is
keyed and the “send” button is pressed, the MTSO checks the authentication of the mobile user and
assigns (via a supervisory control channel) an available frequency channel for radio transmission
of the voice signal from the mobile telephone to the base station. A second frequency is assigned
for radio transmission from the base station to the mobile user. Simultaneous transmission between
two parties is known as full-duplex operation. In order to complete the connection to the called
party, the MTSO interfaces with the central office of the telephone network by means of wide-
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Copyright OUP
708
No reproduction or networking permitted without license from IHS

Copyright by Oxford University Press, Inc. and the materials contained herein
4.5 MHz
Aural IF FM demodulator
Audio loud speaker
4.2 MHz 3.6 MHz
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
LPF Trap fY (t)
IF passband sI (t)
Antenna
41–47 MHz
COMMUNICATION SYSTEMS
2.0–4.2 MHz 0–1.6 MHz

R
RF IF Envelop Picture
amplifier Mixer amplifier detector BPF LPF Matrix G tube
B
0–0.6 MHz
Gain adjust
Local (color) LPF sQ(t)
oscillator
Sync Color-burst
separator gate −π
2
Not for Resale, 08/23/2019 14:15:14 MDT

Frequency
tuning Vertical Horizontal Phase-shift
Hue (tint) control
oscillator oscillator adjust
Sweep to Sweep to
vertical yoke horizontal yoke
Color-burst PLL
LPF VCO
Licensee=Tipiel Colombia - Bogota /5931917151, User=Quinones-External, Sergio

Figure 15.2.30 Block diagram of a color television receiver.
Telephone Cell
central office with base station MTSO
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Figure 15.2.31 Cellular telephone concept in mobile radio system.
band trunk lines, which carry speech signals from many users. When the two parties hang up
upon completion of the telephone call, the radio channel then becomes available for another user.
During the telephone conversation, if the signal strength drops below a preset threshold, the
MTSO monitors and finds a neighboring cell that receives a stronger signal and automatically
switches (in a fraction of a second) the mobile user to the base station of the adjacent cell. If a
mobile user is outside of the assigned service area, the mobile telephone may be placed in a roam
mode, which allows the user to initiate and receive calls.
In analog transmission between the base station and the mobile user, the 3-kHz wide audio
signal is transmitted via FM using a channel bandwidth of 30 kHz. Such a large bandwidth
expansion (by a factor of 10) is needed to obtain a sufficiently large SNR at the output of
the FM demodulator. Since the use of FM is indeed wasteful of the radio frequency spectrum,
cellular telephone systems based on digital transmission of digitized compressed speech are later
developed. With the same available channel bandwidth, the system then accommodates a four-
to tenfold increase in the number of simultaneous users.
Cellular systems employed cells with a radius in the range of 5–18 km. The base station
usually transmitted at a power level of 35 W or less, and the mobile users transmitted at a power
level of about 3 W, so that signals did not propagate beyond immediately adjacent cells. By
making the cells smaller and reducing the radiated power, frequency reuse, bandwidth efficiency,
and the number of mobile users have been increased. With the advent of small and powerful
integrated circuits (which consume very little power and are relatively inexpensive), the cellular
radio concept has been extended to various types of personal communication services using
low-power hand-held sets (radio transmitter and receivers).
With analog cellular, or AMPS (Advanced Mobile Phone System), calls are transmitted in
sound waves at 800 MHz to 900 MHz. This was the first mobile phone technology available in
early 1980s. Digital cellular, or D-AMPS (Digital AMPS), transmits calls in bits at the same
frequency as analog cellular, with improved sound quality and security. To send numerous calls
at once, D-AMPS phones use either CDMA (Code Division Multiple Access) or TDMA (Time
Division Multiple Access) technology; but CDMA phones won’t work in TDMA areas, and vice
versa. A dual-mode unit can switch to analog transmission outside of the more limited digital
network.
PCS (Personal Communications Service) phones transmit at 1800 MHz to 1900 MHz and
are smaller and more energy efficient. To get around the limited coverage, a dual-band digital
phone (which switches to the lower digital frequency) and a trimode phone (which works in
Copyright OUP
AMPS, D-AMPS, or PCS areas) has been developed. The GSM (Global System for Messaging
communications) is the most widely accepted transmission method for PCS phones.
The latest wireless communications technology is the personal satellite phone. The coverage
is planetary and one can reach anywhere on earth. Examples include the Iridium satellite handset
developed by Motorola and others from the Teledesic constellation. Special requirements, such as
sending and receiving data or faxes, can be handled by the new handheld computer-and-mobile-
phone hybrids such as Nokia’s 9000i and the Ericsson DI27. Mobile phones with a Web browser
capability are also available. We have yet to see the more exciting new developments in the
telecommunications industry with computers, networking, and wireless technology.
15.3 DIGITAL COMMUNICATION SYSTEMS

A digital signal can be defined as having any one of a finite number of discrete amplitudes at any
given time. The signal could be a voltage or current, or just a number such as 0 or 1. A signal for
which only two amplitudes are possible is known as a binary digital signal, the type of which is
commonly used in computers and most digital communication systems. A communication system
that is designed to process only digital signals (or messages) to convey information is said to be
digital. The recent trend is to make as much of the system digital as possible, because:
• Discrete data are efficiently processed.
• Analog messages can also be converted to digital form.
• Digital systems interface well with computers.
• Digital systems offer great reliability and yield high performance at low cost.
• Being flexible, digital systems can accommodate a variety of messages with ease.
• Security techniques are available to offer message privacy to users.
• Advanced signal-processing techniques can be added on.
However, the most serious disadvantages are the increased complexity needed for system
synchronization and the need for larger bandwidths than in an equivalent analog system. A
digital system can directly interface with a source having only discrete messages, because of
the inherent characteristic of the digital system. With suitable conversion methods, however,
systems currently exist that can simultaneously transmit audio, television, and digital data over
the same channel. Figure 14.1.2 illustrates the basic elements of a digital communication system,
which was introduced in Section 14.1.
Before we begin discussing digital systems, it is helpful to talk about the methods by which
analog messages are converted into digital form. Sampling, quantization, and coding are the three
operations needed for the transmission of an analog signal over a digital system.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Sampling
This method was introduced in Section 14.2. Sampling of an analog signal makes it discrete in
time. A bandlimited signal can be recovered exactly from its samples, taken periodically in time
at a rate at least equal to twice the signal’s bandwidth. If a message f (t) has a spectral extent of
Wf rad/s, the sampling rate fs (samples per second) must satisfy
Wf
fs ≥ (15.3.1)
π
from the sampling theorem. The minimum rate Wf /π (samples per second) is known as the
Nyquist rate. If the exact message samples could be transmitted through the digital system, the
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15.3 DIGITAL COMMUNICATION SYSTEMS 711
original f (t) could be exactly reconstructed at all times, with no error by the receiver. However,
since the exact samples cannot be conveyed, they must be converted to discrete samples in a
process known as quantization.
Quantization
Let Figure 15.3.1(a) illustrate a message f (t) with values between 0 and 7 V. A sequence of
exact samples taken at uniform intervals of time is shown: 1.60, 3.70, 4.75, 3.90, 3.45, and
5.85 V. Quantization consists of rounding exact sample values to the nearest of a set of discrete
amplitudes called quantum levels. Assuming the quantizer to have eight quantum levels (0, 1,
2, . . . , 7 V), a sequence of quantized samples (2, 4, 5, 4, 3, and 6 V) is shown in Figure 15.3.1(a).
Obviously, the scheme is not limited to messages with only nonnegative voltages. The quantizer
is said to be uniform when the step size between any two adjacent quantum levels is a constant,
denoted by δv volts. Quantizers with nonuniform step size are also designed for improved system
performance. An L-level quantizer can have even or odd L. A quantizer is said to be saturated or
overloaded when

L−2 L
|f (t)| > δv + δv = δv (15.3.2)
2 2
Figure 15.3.2 shows the output quantum levels versus input voltage characteristic (stairstep in
shape) of an L-level quantizer, when the message signal has both positive and negative amplitudes
of the same maximum magnitude. Case (a) corresponds to L being an even integer, when the
midriser can be observed; and case (b) corresponds to L being an odd integer, when the midtread
can be seen.
V Figure 15.3.1 (a) Analog message f (t) with

exact and quantized samples. (b) Coding and
7 waveform formatting of quantized samples.
f (t)
6 5.85
4.75
5
4 3.90
3.70
3 3.45
2
1.60
1
0 t
Ts 2Ts 3Ts 4Ts 5Ts 6Ts
2 4 5 4 3 6
Quantized samples
(a)
0 1 0 1 0 0 1 0 1 1 0 0 0 1 1 1 1 0
Binary code words (Nb = 3)
−A
Polar format
(b)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Output Figure 15.3.2 Uniform quantizer

( L 2− 1 ) δ v characteristics. (a) Midriser with
even L. (b) Midtread with odd L.
≈
5 δv L even
2
− ( L 2− 2 ) δ
v
3 δv
2
f (t)
≈
−
3 δv
2
( L 2− 2 ) δ v
Midriser
5 δv
−
≈ 2
− ( L 2− 1 ) δ v
(a)
Output
( L 2− 1 ) δ v
≈ L odd
2 δv
− ( L 2− 2 ) δ v δv
f (t)
≈
−δv ( L 2− 2 ) δ v
−2 δv Midtread
− ( L 2− 1 ) δ v
(b)
EXAMPLE 15.3.1
A uniform quantizer is said to have 16 levels, and hence is called a midriser. The saturation levels
are to correspond to extreme values of the message of 1 V ≤ f (t) ≤ 17 V. Find the quantum
levels.
Solution
The tread width is δv = (17 − 1)/16 = 1 V. The first quantum level is then given by
1 + (δv/2) = 1.5 V. Other quantum levels, denoted by li, are given by
li = 1.5 + (i − 1)δv = 1.5 + (i − 1)1, i = 1, 2, . . . , 16
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Quantization Error
Sampling followed by quantization is equivalent to quantization followed by sampling. Figure
15.3.3 illustrates a message signal f (t) and its quantized version denoted by fq(t). The difference
between fq(t) and f (t) is known as the quantization error ε q(t),
εq (t) = fq (t) − f (t) (15.3.3)
Theoretically, fq(t) can be recovered in the receiver without error. The recovery of fq(t) can
be viewed as the recovery of f (t) with an error (or noise) εq(t) present. For a small δv with a large
number of levels, it can be shown that the mean-squared value of ε q(t) is given by
(δv)2
εq2 (t) = (15.3.4)
12
When a digital communication system transmits an analog signal processed by a uniform
quantizer, the best SNR that can be attained is given by

So f 2 (t) 12f 2 (t)
= = (15.3.5)
Nq εq2 (t) (δv)2
where S0 and Nq represent the average powers in f (t) and ε q(t), respectively. When f (t) fluctu-
ates symmetrically between equal-magnitude extremes, i.e., − |f (t)|max ≤ f (t) ≤ |f (t)|max ,
choosing a sufficiently large number of levels L, the step size δv comes out as
2 |f (t)|max
δv = (15.3.6)
L
and the SNR works out as

S0 3L2 f 2 (t)
= (15.3.7)
Nq |f (t)|2max
By defining the message crest factor K CR as the ratio of peak amplitude to rms value,
|f (t)|2max
2
=
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
KCR (15.3.8)
f 2 (t)
Equation (15.3.7) can be rewritten as
Figure 15.3.3 Message signal f (t), its quantized

Message f (t) version fq(t), and quantization error εq(t).
Quantized
message fq(t)
δv
δv
Quantization
error εq(t)
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So 3L2
= 2
(15.3.9)
Nq KCR
It can be seen that messages with large crest factors will lead to poor performance.
Companding
In order to lower the crest factor of a waveform, so as to produce better performance, a process
known as companding is used. It works like a compressor which progressively compresses the
larger amplitudes of a message when it is passed through a nonlinear network. The inverse
operation in the receiver is known as an expandor, when it restores the original message. Figure
15.3.4 illustrates a typical set of input–output characteristics for a form of compandor. One can see
that the action of the compressor is to increase the rms–signal value for a given peak magnitude.
Source Encoding
After the quantization of message samples, the digital system will then code each quantized
sample into a sequence of binary digits (bits) 0 and 1. Using the natural binary code is a simple
approach. For a code with Nb bits, integers N (from 0 to 2Nb − 1) are represented by a sequence
of digits, bNb , bNb −1 , . . . , b2 , b1 , such that
N = bNb (2Nb −1 ) + . . . + b2 (21 ) + b1 (20 ) (15.3.10)
Note that b1 is known as the least significant bit (LSB), and bNb as the most significant bit (MSB).
Since a natural binary code of Nb bits can encode Lb = 2Nb levels, it follows that
Output Figure 15.3.4 Compandor input–output character-

|f (t)|max istics. (a) Compressor. (b) Expandor.
With compression
No compression
Input
|f (t)|max
(a)
Output
|f (t)|max
No expansion
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
With expansion
Input
|f (t)|max
(b)
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L ≤ Lb = 2Nb (15.3.11)
if L levels span the message variations. For example, in Figure 15.3.1(b), Nb = 3 and L = 8;
the binary code word 010 represents 0(23−1 ) + 1(21 ) + 0(20 ) = 2 V, and 110 represents
1(23−1 ) + 1(21 ) + 0(20 ) = 6 V. Thus, binary code words with Nb = 3 are shown in Figure
15.3.1(b).
EXAMPLE 15.3.2
A symmetrical fluctuating message, with |f (t)|max = 6.3 V and KCR = 3, is to be encoded by
using an encoder that employs an 8-bit natural binary code to encode 256 voltage levels from
−7.65 V to +7.65 V in steps of δv = 0.06 V. Find L, f 2 (t), and S0 /Nq .
Solution

2 |f (t)|max 2 × 6.3
L= = = 210
δv 0.06
|f (t)|2max 6.32
f 2 (t) = 2
= = 4.41 V2
KCR 9

S0 3L2 3 × 2102
= 2 = = 14,700 or 41.67 dB
Nq KCR 9
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Digital Signal Formatting
After quantization and coding the samples of the message, a suitable waveform has to be chosen
to represent the bits. This waveform can then be transmitted directly over the channel (if no carrier
modulation is involved), or used for carrier modulation. The waveform selection process is known
as formatting the digital sequence. Three kinds of waveforms are available:
1. Unipolar waveform, which assigns a pulse to code 1 and no pulse to code 0. The duration
of a pulse is usually chosen to be equal to Tb, if binary digits occur each Tb seconds (the
bit interval’s duration).
2. Polar waveform, which consists of a pulse of duration Tb for a binary 1 and a negative
pulse of the same magnitude and duration for a 0. This yields better system performance
in noise than the unipolar format, because of the wider distinction between the two values.
3. Manchester waveform, which transmits a pulse of duration Tb /2 followed by an equal
magnitude, but negative pulse of duration Tb /2 for each binary 1, and the negative of this
two-pulse sequence for a binary 0. Even when a long string of 0s or 1s may occur in the
digital sequence, the advantage of this format is that it never contains a dc component.
Figure 15.3.5 illustrates these formats for a sequence of binary digits. Figure 15.3.1 (b) shows
the polar format corresponding to the coding in that case. Since it is important that a digital system
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not lose track of polarity while processing polar or Manchester waveforms, a technique called
differential encoding (see Problem 15.3.9) is employed so as to remove the need to maintain
polarity.
Because the digits in a typical digital sequence fluctuate randomly between 0s and 1s with
time, the formatted waveform is then a randomly fluctuating set of pulses corresponding to the
selected format. With such random waveforms, one uses the power spectral density (with units of
V2/Hz) to define the spectral content. On comparing the three waveform formats, the unipolar and
polar formats both have the same bandwidth and relative side-lobe level, whereas the Manchester
waveform has no spectral component at direct current, but requires twice the bandwidth of the
other two signals.
Pulse-Code Modulation (PCM)

PCM is the simplest and oldest waveform coding scheme for processing an analog signal by
sampling, quantizing, and binary encoding. Figure 15.3.6 shows a functional block diagram of
a PCM system transmitter. In order to guarantee that the message is band-limited to the spectral
extent for which the system is designed, a low-pass filter is introduced. The compressor is rather
optional for better performance. Let us assume that the PCM signal is transmitted directly over
the baseband channel. Corrupted by the noise generated within the receiver, the PCM signal is
shown as the input to the PCM reconstruction function in Figure 15.3.7, which depicts a block
diagram of functions (including an optional expandor) needed to receive PCM. The operations of
the receiver are basically the inverse of those in the transmitter. The first and most critical receiver
operation is to reconstruct the originally transmitted PCM signal as nearly as possible from the
noise-contaminated received waveform. The effect of noise is to be minimized through a careful
selection of circuit implementation.
The only knowledge required of the receiver to reconstruct the original PCM signal is whether
the various transmitted bits are 0s and 1s, depending on the voltage levels transmitted, assuming
that the receiver is synchronized with the transmitter. The two levels associated with unipolar
0 1 1 1 0 1 0 0 1 0 1 1 0 0 Figure 15.3.5 Waveform formats for a binary

digital sequence. (a) Binary digital sequence {bk }.
(a)
(b) Its unipolar format. (c) Its polar format. (d) Its
Manchester format.
Tb
A
t
(b)
t
−A
(c)
−A
(d)
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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Band-limited message
Presampling
Analog Compressor Uniform
lowpass Sampler
message f (t) A (optional) quantizer
filter
Quantized
Timing samples
control Binary
encoder
Waveform
formatter
Binary PCM
to channel
Figure 15.3.6 Block diagram of a PCM system transmitter.

--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Original PCM plus errors Quantized samples plus noise
PCM plus
broad-band PCM Binary Expandor
channel noise reconstruction decoder (optional)
Message
reconstruction
(low pass filter)
Timing
f (t) plus noise
Figure 15.3.7 Block diagram of a PCM system receiver.
pulses of amplitude A are 0 and A, whereas those associated with polar pulses (of amplitudes ±A)
are A and −A. It is, of course, better for the receiver if the ratio of the pulse-caused voltage to the
noise rms voltage is the largest possible at the time of measurement. Figure 15.3.8 shows PCM
reconstruction circuits for unipolar, polar, and Manchester waveforms. The following notation is
used:
• VT: Preset threshold, which is zero for polar and Manchester PCM. In the unipolar system,
it is equal to half the signal component of the integrator’s output level (A2 Tb /2) at the
sampling time when the input has a binary 1. (After the sample is taken, the integrator is
discharged to 0 V in preparation for integration over the next bit interval.)
• D: The difference between the integrator’s output and VT at the end of each bit interval of
duration Tb. If D ≥ 0, binary 1 is declared; if D < 0, a 0 is declared.
• Square-wave clock: Generates a voltage A for 0 < t < Tb /2 and −A for Tb /2 < t < Tb ,
with its fundamental frequency 1/Tb Hz. The product of the clock and the incoming
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Sampler
Tb + ≥0 choose 1
PCM + noise A∫ ( . ) dt Σ D
0
− <0 choose 0
A2Tb Timing
VT =
2
(a)
Sampler
Tb ≥0 choose 1
PCM + noise 2A∫ ( . ) dt D
0 <0 choose 0
Timing
(b)
Square-
wave clock
Sampler
+ Tb ≥0 choose 1
PCM + noise Σ ∫0 ( . ) dt D
<0
Inverter − choose 0
Timing
(c)
Figure 15.3.8 PCM reconstruction circuits. (a) For unipolar waveform. (b) For polar waveform. (c) For
Manchester waveform.
Manchester PCM waveform becomes a polar PCM signal; the product with the clock
inverted is the negative of a polar signal.
In Figure 15.3.8(c), after differencing in the summing junction, the response is then a double-
amplitude polar PCM signal. The rest of the circuit is similar to that of a polar PCM, as in Figure
15.3.8(b).
The very presence of noise suggests that the PCM reconstruction circuits may occasion-
ally make a mistake in deciding what input pulse was received in a given bit interval. How
often an error is made is determined by the bit-error probability. Bit errors in a unipolar
system occur much more frequently than in a polar system having the same signal-to-noise
ratio.
With negligible receiver noise, only quantization error is present when Equation (15.3.3)
applies. With not so negligible receiver noise, the recovered signal fqR (t) can be expressed as
fqR (t) = fq (t) + εn (t) = f (t) + εq (t) + εn (t) (15.3.12)
in which an error εn (t) due to noise is introduced in the reconstructed message fqR (t). The ratio
of desired output signal power to total output noise power is given by

S0 S0 /Nq
= (15.3.13)
N0 PCM 1 + εn2 (t)/εq2 (t)
--`,,,``,,`,```,``,```
Copyright OUP
where the numerator S0 /Nq is given by Equation (15.3.5), or by Equation (15.3.9) when Equation
(15.3.6) applies. If εn2 (t) << εq2 (t), noise has no effect on performance; otherwise it has a
significant effect. Thus, εn (t) gives rise to a threshold effect in PCM.
Signal Multiplexing
Frequency-division multiplexing (FDM) and time-division multiplexing (TDM) systems were
introduced in Section 14.2. When data from many sources in time are interlaced, the interlacing
of data is called time multiplexing, in which case a single link can handle all sources. Figure
15.3.9(a) illustrates time multiplexing soon after sampling for N similar messages. With proper
interleaving of sampling pulses [see Figures 15.3.9(b) and (c) for individual message signal
waveforms], the train of samples can be added for the signal at point A in Figure 15.3.9(a), as
shown in Figure 15.3.9(d). If we consider N similar messages of spectral extent Wf rad/s, the
sampling interval Ts must satisfy
π
Ts ≤ (15.3.14)
Wf
based on the sampling theorem (see Section 14.2). A time slot is the time per sampling interval
that is allowed per message. It is equal to the sum of the sampling-pulse duration τ and separation
τg , called the guard time. Thus, we have
Ts π
τ + τg = ≤ (15.3.15)
N N Wf
The time that is required to gather at least one sample of each message is known as a frame,
which is Ts, as shown in Figure 15.3.9(d). Now, with a single composite source of the waveform
shown in Figure 15.3.9(d) at point A of Figure 15.3.9(a), the time multiplexer of Figure 15.3.9(a)
operates beyond A. For Nb-bit encoding, each time slot in the output PCM signal will have Nb bits
of duration,
Ts
Tb = (15.3.16)
N Nb
It is assumed that all sample trains are derived from the same timing source, called a clock, and
hence have the same frequency. Instead of using up all frame time for messages, some time is
usually allocated for synchronization so that the receiver will know the start times of frames. The
American Telephone and Telegraph Company (AT & T) employs a device known as a D3 channel
bank, which is a synchronous multiplexer, whose characteristics are as follows:
• It multiplexes 24 telephone messages, each having an 8-kHz sampling rate so that Ts =

1/(8 × 103 ) = 125 µs. The digital structure of each input message is determined by a single
master clock.
• Each sample uses 8-bit encoding, so that there are 8 × 24 = 192 message bits; one extra
bit, known as a framing bit, of less than one time slot is allowed for frame synchronization.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Thus, a total of 193 bits per frame, with a total bit rate of 193 × 8000 = 1.544 megabits
per second (Mbit/s), is available.
• The frame structure is illustrated in Figure 15.3.10.
• Bit robbing or bit stealing, which is the occasional borrowing of a message bit for purposes
other than message information, is done for signaling, which refers to conveying information
concerning telephone number dialed, dial tone, busy signal, ringing, and so on.
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f1(t) LPF Sampler
Timing 1
+
A Uniform Binary
f2(t) LPF Sampler Σ Compressor
+ quantizer encoder
...
+
..
Timing 2
. Waveform
formatter
fN (t) LPF Sampler

Binary PCM
Timing N
(a)
f1(t)
2Ts
t
Ts 3Ts
(b)
f2(t)
2Ts
t
Ts 3Ts
(c)
τ
1 Guard time τg
3 1
2 2 1
... ... N ... ... ...
t
2 2
1
Time slot Ts
2Ts 3Ts
Frame
(d)
Figure 15.3.9 (a) Time multiplexing for N similar analog signals. (b) Waveform at point A for message
signal 1. (c) Waveform at point A for message signal 2. (d) Full waveform at point A.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
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One frame, 193 bits, 125 µs
. 1 2 3 4 5 ... Message time slots ... 22 23 24
Time
One framing bit

8 bits per message word
1 2 3 4 5 6 7 8
MSB LSB
Figure 15.3.10 Frame structure for a D3 channel bank.
64 kbit/s DS-1 lines DS-2 lines DS-3 lines DS-4 lines

each 1.544 Mbit/s 6.312 Mbit/s 44.736 Mbit/s 274.176 Mbit/s
each each each each
1 1 1 1 1
Digital
2 First 2 Second 2 Third 2 Fourth Fifth
subscriber DS-5 line
signals
.. level
3
level .. level .. level level
560.16 Mbit/s
. multiplexer multiplexer . multiplexer . multiplexer multiplexer
output
24 DS-1 4 DS-2 7 DS-3 6 DS-4 2 DS-5
D3 channel
bank Signals from Signals from Signals from Signals from
other DS-1 other DS-2 other DS-3 other DS-4units
units units units
Figure 15.3.11 Digital TDM hierarchy for North American telephone communication system.
In digital speech transmission over telephone lines via PCM, a standard TDM hierarchy has been
established for accommodating multiple subscribers. Figure 15.3.11 illustrates the TDM hierarchy
for the North American telephone system. The output from the channel bank is a digital signal
(DS) on a line said to carry level 1 multiplexing. In the first level of the TDM hierarchy, 24
digital subscriber signals are time-division multiplexed into a single high-speed data stream of
1.544 Mbit/s (nominal bit rate). The resulting combined signal is usually called a DS-1 channel.
In the second level of TDM, four DS-1 channels are multiplexed into a DS-2 channel, having the
nominal bit rate of 6.312 Mbit/s. In a third level of hierarchy, seven DS-2 channels are combined
via TDM to produce a DS-3 channel, which has a nominal bit rate of 44.736 Mbit/s. Beyond
DS-3, there are two more levels, as shown in Figure 15.3.11. All multiplexers except the channel
bank are asynchronous.
In a mobile cellular radio system (see Section 15.2) for the transmission of speech signals,
since the available channel bandwidth per user is small and cannot support the high bit rates
needed by waveform encoding methods such as PCM, the analysis–synthesis method based on
linear predictive coding (LPC) is used to estimate the set of model parameters from short segments
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
of the speech signal. The speech-model parameters are then transmitted over the channel. With
LPC, a bit rate of 4800–9600 bit/s is achieved.
In mobile cellular communication systems, LPC speech compression is only needed for
the radio transmission between the mobile transcriber and the base station in any cell. At the
base station interface, the LPC-encoded speech is converted to analog form and resampled and
digitized (by using PCM) for transmission over the terrestrial telephone system. Thus, a speech
Copyright OUP
signal transmitted from a mobile subscriber to a fixed subscriber will undergo two different types
of analog-to-digital (A/D) encoding, whereas speech-signal communication between two mobiles
serviced by different base stations will undergo four translations between the analog and digital
domains.
In the conversion of analog audio signals to digital form, with the development of the compact
disc (CD) player and the digital audio tape recorder, the most dramatic changes and benefits
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
have been experienced by the entertainment industry. The CD system, from a systems point
of view, embodies most of the elements of a modern digital communication system: A/D and
D/A conversion, modulation/demodulation, and channel coding/decoding. Figure 15.3.12 shows
a general block diagram of the elements of a CD digital audio system. The sampling rate in a
CD system is chosen to be 44.1 kHz, which is compatible with the video recording equipment
commonly used for digital recording of audio signals on magnetic tape. The samples of both the L
and R signals are quantized using PCM with 16 bits per sample. While the D/A conversion of the
two 16-bit signals at the 44.1-kHz sampling rate is relatively simple, the practical implementation
of a 16-bit D/A converter is very expensive. Because inexpensive D/A converters with 12-bit (or
less) precision are readily available, a method is to be devised for D/A conversion that employs
a low precision (and hence a low-cost D/A converter), while maintaining the 16-bit precision
of the digital audio signal. Without going into details, the practical solution to this problem is
to expand the bandwidth of the digital audio signal by oversampling through interpolation and
digital filtering prior to analog conversion.
Time-division multiple access (TDMA) is an important means by which each station on earth
timeshares the communication satellite in the sky, and broadcasts to all other stations during its
assigned time. Figure 15.3.13 shows the communication links of several (N) earth stations that
communicate with each other through satellite. All stations use the same up-link frequency, and
all receive a single down-link frequency from the satellite.
Carrier Modulation by Digital Signals

Digitally modulated signals with low-pass spectral characteristics can be transmitted directly
through baseband channels (having low-pass frequency-response characteristics) without the
need for frequency translation of the signal. However, there are many communication bandpass
channels (telephone, radio, and satellite channels) that pass signals within a band of frequencies
(that is far removed from dc). Digital information may be transmitted through such channels by
using a sinusoidal carrier that is modulated by the information sequence in either amplitude, phase,
or frequency, or some other combination of amplitude and phase. The effect of impressing the in-
formation signal on one or more of the sinusoidal parameters is to shift the frequency content of the
transmitted signal to the appropriate frequency band that is passed by the channel. Thus, the signal
is transmitted by carrier modulation. There are several carrier-modulation methods. However, we
shall limit our discussion to the following, assuming only binary modulation in all cases:
• Amplitude-shift keying (ASK)
• Phase-shift keying (PSK)
• Differential phase-shift keying (DPSK)
• Frequency-shift keying (FSK).
AMPLITUDE-SHIFT KEYING (ASK)

A carrier’s amplitude is keyed between two levels (binary 1 and 0) in binary ASK. Figure 15.3.14
shows the functions of a coherent ASK communication system. Let us consider a bit interval from
Copyright OUP
Channel Figure 15.3.12 General block diagram of

a CD digital audio system.
Master disc Compact disc
Replication 1.25 m/s
Laser
recording
Modulator Digital Demodulator

control
and display
information
Channel Channel
encoder decoder
Up-sampling
Digital and
recorder interpolation
A/D D/A
converter converter
L R L R
Studio
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Communication Figure 15.3.13 Communication links of several earth stations

satellite communicating through a satellite.
...
Reference
Station 2 station
Station N
Station 1 Earth
t = 0 to t = Tb, since the operation of any other interval will be similar. The desired ASK signal
is given by
'
Ac cos(ωc t + φc ), 0 < t < Tb , for 1
sASK (t) = (15.3.17)
0, 0 < t < Tb , for 0
Copyright OUP
where Ac, ωc, and φ c are the peak amplitude, angular frequency, and phase angle of the mod-
ulated carrier, respectively. Equation (15.3.17) can be viewed as a carrier Ac cos(ωc t + φc )
modulated by a digital signal d(t) that is 0 or 1 in a given bit interval. The digital signal and
product device shown in Figure 15.3.14 are then equivalent to the waveform formatter and
modulator. Assuming that the received signal sR(t) differs only in amplitude from sASK(t), one
can write
'
sR (t) = (15.3.18)
0, 0 < t < Tb , for 0
The product device in the receiver’s demodulator acts like a synchronous detector that
removes the input carrier. The major disadvantage of the coherent ASK is that the required local
carrier must be phase-connected with the input signal. The input to the integrator is a unipolar
PCM signal, and the remainder of Figure 15.3.14 is a PCM receiver [see Figure 15.3.8(a)].
The noncoherent ASK system eliminates the need for a coherent local oscillator. Figure
15.3.15 shows the demodulator and code generator for a noncoherent ASK system. A matched
filter (that has its impulse response matched to have the same form as the carrier pulse at its input)
and envelope detector take the place of the synchronous detector and integrator of Figure 15.3.14.
While ASK systems are not as widely used as other systems for various reasons, the ASK
concept remains significant, particularly as applied to modern optical communication systems
which use intensity modulation of a light source.
Broad-band system noise
+ Sampler
Digital R Tb + ≥0 choose 1
signal d(t) sASK(t) +
Σ
sR(t) ∫ 0 ( . ) dt Σ D
<0 choose 0
−
Ac cos (ωc t + φc ) A cos (ωc t + φc ) A2Tb

(local carrier) VT =
4
Sample at time Tb for bit interval 0 < t ≤ Tb
Waveform formatter Channel Demodulator and code generator of receiver

and modulator
Figure 15.3.14 Functions of a coherent ASK communication system.
sR(t) plus noise + ≥0 choose 1

Matched Envelope
R Σ D
filter detector <0 choose 0
−
A2Tb
VT
4
Sample at time Tb for

bit interval 0 < t ≤ Tb
Figure 15.3.15 Demodulator and code generator for a noncoherent ASK system.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
PHASE-SHIFT KEYING (PSK)

In PSK, the phase angle of a carrier is keyed between two values. When the values are separated
by π radians, it is known as phase-reversal keying (PRK). The PSK waveform in the bit interval
is given by
'
sPSK (t) = (15.3.19)
−Ac cos(ωc t + φc ), 0 < t < Tb , for 0
Equation (15.3.18) can be viewed as a carrier Ac cos(ωc t + φc ) modulated in amplitude by
a digital signal d(t) with amplitudes of 1 when the binary digit in the bit interval is 1 and 0,
respectively. Figure 15.3.16 illustrates the functions of a coherent PSK communication system,
which is similar to the ASK system of Figure 15.3.14 with the following differences:
• The received signal is now given by
'
sR (t) = (15.3.20)
−Ac cos(ωc t + φc ), 0 < t < Tb , for 0
• A gain of 2 is assigned to the integrator.
• A threshold is absent when binary digits 0 and 1 occur with equal probability.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
No truly noncoherent PSK version is possible because the PSK signal carries its information
in the carrier’s phase, whereas a noncoherent system purposely disregards phase and operates
only on signal amplitude.
DIFFERENTIAL PHASE-SHIFT KEYING (DPSK)

In order to eliminate the need of a local carrier, DPSK has been developed in which the receiver
uses the received signal to act as its own carrier. Figure 15.3.17 shows the functions of a DPSK
system in which the leftmost product operation along with 1-bit delay is the differential encoder.
The digital signal d(t) is a polar waveform of levels ±1, corresponding to binary digits 1 and
0, respectively. The output signal a(t) from the differential encoder PSK-modulates a carrier to
produce the DPSK signal sDPSK(t). The product device followed by the wide-band low-pass filter
acts as the coherent detector. The two inputs to the product device are obtained from the output
of a filter matched to the input pulse in a single bit interval. Note that the 1-bit delayed input to
the product device serves the purpose of the local oscillator for the coherent detector; that is to
+ Sampler
R Tb ≥0 choose 1
Digital
signal d(t) Σ 2 ( . ) dt D
sPSK(t) + sR(t) 0 <0 choose 0
Ac cos (ωc t + φc ) A cos (ωc t + φc )

(local oscillator)

and modulator
Figure 15.3.16 Functions of a coherent PSK communication system.
Copyright OUP
Coherent detector
Differential encoder Wide-band
+ si (t) + noise low-pass filter
Digital a(t) R
signal d(t)
... Σ Matched WBLPF
sDPSK(t) + sR(t) filter
sd (t) + noise
Delay Tb
a(t − Tb) Delay Tb Sampler
Ac cos (ωc t + φc )
Sample at time Tb for bit interval 0 < t ≤ Tb D
If D ≥ 0 choose 1
If D < 0 choose 0

and modulator
Figure 15.3.17 Functions of a DPSK system.
say, the DPSK waveform in a given bit interval serves as its own local-oscillator signal in the
following bit interval.
In Figure 15.3.17, si(t) is the signal component of the matched filter output, and sd(t) is the
signal component of the detector output. If the phases of both si(t) and si(t − Tb ) are the same,
sd(t) is then a positive voltage; if their phases differ by π radians, sd(t) will then be a negative
voltage. These voltages will have maximum amplitudes at the sample time at the end of the bit
interval. Because the sign of the voltage at the sampler depends upon the phase relationship
between si(t) and its delayed replica, and the sign of sd(t) is of the same form as d(t), the
original digital bit sequence can be determined by sampling to decide the sign of the detector
output.
Figure 15.3.18 illustrates an example sequence of message binary digits, modulator wave-
forms in DPSK, and phase and polarity relationships as applied to DPSK message recovery.
FREQUENCY-SHIFT KEYING (FSK)

Digital transmission by FSK is a nonlinear modulation method that is appropriate for channels
that lack the phase stability needed to perform carrier-phase estimation. Figure 15.3.19 shows
the functions of a coherent FSK system in which the transmitted signal sFSK(t) is generated by
frequency modulation of a voltage-controlled oscillator (VCO). The digital signal d(t) has a polar
format with amplitudes ±1, corresponding to binary digits 1 and 0, respectively. Modulation keys
the VCO’s angular frequency between two values, such that
ω2 = ωc + ?ω when d(t) = 1 (15.3.21)

ω1 = ωc − ?ω when d(t) = −1 (15.3.22)
where ?ω is the frequency deviation from a nominal or carrier angular frequency ωc . In order
to conserve the bandwidth in the signal sFSK(t), ?ω is usually selected not much larger than the
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
minimum allowable value given by

π ωb
?ω = = (15.3.23)
Tb 2
Copyright OUP
Example digital bit sequence Figure 15.3.18 (a) Example sequence

0 1 1 1 0 1 0 0 1 0 1 1 0 0 of message binary digits and modulator
waveforms in DPSK. (b) Phase and polar-
Digital signal d(t) ity relationships as applied to DPSK mes-
1
sage recovery.
t
−1
a(t)
1
Initial level
t
−1
a(t − Tb)
1
t
−1
(a)
Phase of si (t)
0
π t
Phase of si (t − Tb)
0
t
π
Sign of sd (t)
+
t
−
(b)
Tb
∫ 0 ( . ) dt
Sampler
+ + ≥0 choose 1
Digital R A cos (ω2t + φ2)
VCO Σ Σ D
signal d(t) sFSK(t) + − <0 choose 0
sR(t)
Tb
∫ 0 ( . ) dt
A cos (ω1t + φ1)
Modulator Channel Demodulator and code generator of receiver
Figure 15.3.19 Functions of a coherent FSK system.
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
When Equation (15.3.23) is satisfied, the bandwidth of the channel needed to support sFSK(t) is
about 2ωb rad/s. The transmitted signal in Figure 15.3.19 can be seen to be two unipolar ASK
signals in parallel, one at carrier frequency ω2 and the other at ω1. The receiver then becomes two
coherent ASK receivers in parallel (see Figure 15.3.14).
The noncoherent FSK version results when each product device and the following inte-
grator in the receiver are replaced by a corresponding matched filter followed by an envelope
detector.
Comparison of Digital Communication Systems

The noise performances of different digital communication systems are usually compared on the
basis of their bit-error probabilities Pe. Keeping the ratio Eb /N0 as an independent parameter,
where Eb represents the average signal energy per bit and N0 stands for the noise level, the
following expressions are given here with no derivation:

−Eb

2
1
1 + 1
exp noncoherent ASK


2π(Eb /N0 )

2N0



 1
exp −E
 noncoherent FSK
b

 2 2N0

 1

 coherent ASK
 1 erfc Eb
coherent FSK
Pe = 2 2No (15.3.24)

 unipolar PCM



 1
exp −E b
DPSK

 2 No

 1

 PSK


 1
 2 erfc
Eb
No
polar PCM
Manchester PCM
where
x
2
e−ξ dξ
2
erfc(x) = 1 − √ (15.3.25)
π 0
is known as the complementary error function, which is equal to 1 at x = 0 and decreases to 0 as

x → ∞; its behavior may be approximated by
e−x
2
erfc(x) ∼
= √ when x > 2 (15.3.26)
x π
and
erfc(−x) = 2 − erfc(x) (15.3.27)
Figure 15.3.20 gives the plots of Equation (15.3.24). Of the PCM (noncarrier) systems, the
polar and Manchester-formatted systems are superior to the unipolar system, since no energy is
transmitted during half the bits (on average) in the unipolar system. Of the carrier-modulated
systems, coherent systems perform slightly better (by about 1 dB) than their corresponding
noncoherent versions. However, in practice, to avoid having to generate a local carrier in the
receiver, it may be worth the expense of 1 dB more in transmitted power. The PSK system can
be seen to be superior by about 3 dB for a given Pe to both FSK and ASK (which exhibit nearly
the same performance).
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Copyright OUP
10 0 Figure 15.3.20 Plots of Pe versus [Eb /N0 ]dB for various

ASK (noncoherent) digital communication systems.
FSK (noncoherent)
10 −1
PCM (unipolar)
ASK (coherent)
10 −2 FSK (coherent)
10 −3
DPSK
Pe
10 −4
PCM (polar)
PCM (Manchester)
10 −5 PSK
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
10 −6
10 −7
0 4 8 12 16
Eb
10 log (dB)
N0
EXAMPLE 15.3.3
Let both coherent ASK and coherent PSK systems transmit the same average energy per bit interval
and operate on the same channel such that Eb /N0 = 18. Determine the bit-error probability Pe
for the two systems.
Solution
From Equation (15.3.24) it follows for coherent ASK,

3
1 Eb
Pe = erfc
2 2N0
&
1 18 1
= erfc = erfc(3)
2 2 2
∼ 1 e−9
= √ [from Equation (15.3.26)]
2 3 π
∼
= 1.16 × 10−5
and for coherent PSK,
3
1 Eb
Pe = erfc
2 No
1 √ 1
= erfc 18 = erfc(4.243)
2 2
Copyright OUP
∼ 1 e−18
= √
2 4.243 π
∼
= 1.01 × 10−9
The PSK system is clearly superior to the ASK system, based on equal values of Eb /N0 .
--`,,,``,,`,```,``,`````,```,```-`-`,,`,,`,`,,`---
Digital Transmission on Fading Multipath Channels
We have discussed thus far digital modulation and demodulation methods for the transmission
of information over two types of channels, namely, an additive noise channel and a linear filter
channel. While these channel models are appropriate for a large variety of physical channels, they
become inadequate in characterizing signal transmission over radio channels whose transmission
characteristics vary with time. Time-varying behavior of the channel is exhibited by the following:
• Signal transmission via ionospheric propagation in the HF band (see Figure 15.0.3), in
which signal fading is a result of multipath signal propagation that makes the signal arrive
at the receiver via different propagation paths with different delays.
• Mobile cellular transmission, between a base station and a telephone-equipped automobile,
in which the signal transmitted by the base station to the automobile is reflected from
surrounding buildings, hills, and other obstructions.
• Line-of-sight microwave radio transmission, in which signals may be reflected from the
ground to the receiving antenna due to tall obstructions or hilly terrain in the path of
propagation.
• Airplane-to-airplane radio communications, in which secondary signal components may
be received from ground reflections.
Such channels may be treated as linear systems with time-varying impulse response by
adopting a statistical characterization. Models for time-variant multipath channels will not be
considered here.


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INTRODUCTION TO

New York Oxford

Oxford New York

and associated companies in

Copyright © 2001 by Oxford University Press, Inc.

Published by Oxford University Press, Inc.,

Oxford is a registered trademark of Oxford University Press

All rights reserved. No part of this publication may be reproduced,

Library of Congress Cataloging-in-Publication Data

Printing (last digit): 10 9 8 7 6 5 4 3 2 1

Printed in the United States of America

List of Case Studies and Computer-Aided Analysis xiii

PART 1 ELECTRIC CIRCUITS

2 Circuit Analysis Techniques 66

3 Time-Dependent Circuit Analysis 102

3.5 Computer-Aided Circuit Simulation for Transient Analysis, AC Analysis, and

4 Three-Phase Circuits and Residential Wiring 198

PART 2 ELECTRONIC ANALOG AND DIGITAL SYSTEMS

5 Analog Building Blocks and Operational Ampliﬁers 223

6 Digital Building Blocks and Computer Systems 268

7 Semiconductor Devices 339

7.4 Field-Effect Transistors 367

8 Transistor Ampliﬁers 393

8.2 Biasing the FET 395

9 Digital Circuits 422

PART 3 ENERGY SYSTEMS

10 AC Power Systems 451

11 Magnetic Circuits and Transformers 471

11.7 Learning Objectives 494

13 Rotating Machines 553

PART 4 INFORMATION SYSTEMS

14 Signal Processing 625

15 Communication Systems 666

PART 5 CONTROL SYSTEMS

16 Basic Control Systems 747

Appendix A: References 831

13.6 Practical Application: A Case Study—Wind-Energy-Conversion Systems 610

III. PREREQUISITES AND BACKGROUND

IV. ORGANIZATION AND FLEXIBILITY

MicroSoft PowerPoint Overheads to Accompany Introduction to Electrical Engineering

What is electrical engineering? What is the scope of electrical engineering?

TABLE I IEEE Publications

IEEE Society/Council Periodicals

Consumer Electronics, Transactions on 1021

Power Electronics, Transactions on 4501

Broad Scope Publications

A historical perspective of electrical engineering, in chronological order, is furnished in Table

TABLE II Chronological Historical Perspective of Electrical Engineering

1750–1850 Coulomb’s law (1785)

1900–1920 Marconi’s wireless telegraph system: transatlantic communication (1901)

1.1 Electrical Quantities

1.2 Lumped-Circuit Elements

1.3 Kirchhoff’s Laws

1.4 Meters and Measurements

1.5 Analogy between Electrical and Other Nonelectric Physical Systems

1.6 Learning Objectives

1.7 Practical Application: A Case Study—Resistance Strain Gauge

1.1 ELECTRICAL QUANTITIES

Charge and Electric Force