SST26VF064B

SST26VF064B / SST26VF064BA
3.0V Serial Quad I/O (SQI) Flash Memory

Features • Temperature Range
- Industrial: -40°C to +85°C
• Single Voltage Read and Write Operations
• Packages Available
- 2.7-3.6V
- 8-contact WSON (6mm x 5mm)
• Serial Interface Architecture
- 8-lead SOIC (200 mil)
- Nibble-wide multiplexed I/O’s with SPI-like serial - 16-lead SOIC (300 mil)
command structure
- 24-ball TBGA (6mm x 8mm)
- Mode 0 and Mode 3
• All devices are RoHS compliant
- x1/x2/x4 Serial Peripheral Interface (SPI) Proto-
col
Product Description
• High Speed Clock Frequency
- 104 MHz max The Serial Quad I/O™ (SQI™) family of flash-memory
devices features a six-wire, 4-bit I/O interface that
• Burst Modes
allows for low-power, high-performance operation in a
- Continuous linear burst low pin-count package. SST26VF064B/064BA also
- 8/16/32/64 Byte linear burst with wrap-around support full command-set compatibility to traditional
• Superior Reliability Serial Peripheral Interface (SPI) protocol. System
- Endurance: 100,000 Cycles (min) designs using SQI flash devices occupy less board
- Greater than 100 years Data Retention space and ultimately lower system costs.
• Low Power Consumption: All members of the 26 Series, SQI family are manufac-
- Active Read current: 15 mA (typical @ 104 MHz) tured with proprietary, high-performance CMOS Super-
- Standby Current: 15 µA (typical) Flash® technology. The split-gate cell design and thick-
• Page-Program oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches.
- 256 Bytes per page in x1 or x4 mode
• End-of-Write Detection The SST26VF064B/064BA significantly improve per-
formance and reliability, while lowering power con-
- Software polling the BUSY bit in status register
sumption. These devices write (Program or Erase) with
• Flexible Erase Capability a single power supply of 2.7-3.6V. The total energy
- Uniform 4 KByte sectors consumed is a function of the applied voltage, current,
- Four 8 KByte top and bottom parameter overlay and time of application. Since for any given voltage
blocks range, the SuperFlash technology uses less current to
- One 32 KByte top and bottom overlay block program and has a shorter erase time, the total energy
- Uniform 64 KByte overlay blocks consumed during any Erase or Program operation is
• Write-Suspend less than alternative flash memory technologies.
- Suspend Program or Erase operation to access SST26VF064B/064BA are offered in 8-contact WSON
another block/sector (6 mm x 5 mm), 8-lead SOIC (200 mil), 16-lead SOIC
• Software Reset (RST) mode (300 mil), and 24-ball TBGA. See Figure 2-2 for pin
assignments.
• Software Write Protection
- Individual Block-Locking Two configurations are available upon order:
SST26VF064B default at power-up has the WP# and
- 64 KByte blocks, two 32 KByte blocks, and
Hold# pins enabled and SST26VF064BA default at
eight 8 KByte parameter blocks
power-up has the WP# and Hold# pins disabled.
• Security ID
- One-Time Programmable (OTP) 2 KByte,
Secure ID
- 64 bit unique, factory pre-programmed
identifier
- User-programmable area
 2013 Microchip Technology Inc. Advance Information DS25119C-page 1

1.0 BLOCK DIAGRAM
OTP
SuperFlash
X - Decoder Memory
Address
Buffers
and
Latches
Y - Decoder
Page Buffer,
Control Logic I/O Buffers
and
Data Latches
Serial Interface
WP# HOLD# SCK CE# SIO [3:0]

25119 B1.0
FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM
DS25119C-page 2 Advance Information  2013 Microchip Technology Inc.

2.0 PIN DESCRIPTION
CE# 1 8 VDD
SO/SIO1 2 7 HOLD/SIO3
Top View
WP#/SIO2 3 6 SCK
VSS 4 5 SI/SIO0
25119 08-soic S2A P1.0
FIGURE 2-1: PIN DESCRIPTION FOR 8-LEAD SOIC
CE# 1 8 VDD
SO/SIO1 2 7 HOLD/SIO3
Top View
WP#/SIO2 3 6 SCK
VSS 4 5 SI/SIO0
25119 08-wson QA P1.0
FIGURE 2-2: PIN DESCRIPTION FOR 8-CONTACT WSON
HOLD#/SIO3 SCK
VDD SI/SIO0
NC Top View NC
NC NC
NC NC
NC NC
CE# VSS
SO/SIO1 WP#/SIO2
16-SOIC P1.0
FIGURE 2-3: PIN DESCRIPTION FOR 16-LEAD SOIC

Top View
4
NC VDD WP#/ HOLD#/ NC NC
SIO2 SIO3
3
NC VSS NC SI/ NC NC
SIO0
2
NC SCK CE# S0/ NC NC
SIO1
1
NC NC NC NC NC NC
A B C D E F T4D-P1.0
FIGURE 2-4: PIN DESCRIPTION FOR 24-BALL TBGA
TABLE 2-1: PIN DESCRIPTION

Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SIO[3:0] Serial Data To transfer commands, addresses, or data serially into the device or data out of
Input/Output the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)
command instruction configures these pins for Quad I/O mode.
SI Serial Data Input To transfer commands, addresses or data serially into the device. Inputs are
for SPI mode latched on the rising edge of the serial clock. SI is the default state after a power
on reset.
SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge
for SPI mode of the serial clock. SO is the default state after a power on reset.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence; or in the case of Write operations,
for the command/data input sequence.
WP# Write Protect The WP# is used in conjunction with the WPEN and IOC bits in the Configura-
tion register to prohibit write operations to the Block-Protection register. This pin
only works in SPI, single-bit and dual-bit Read mode.
HOLD# Hold Temporarily stops serial communication with the SPI Flash memory while the
device is selected. This pin only works in SPI, single-bit and dual-bit Read mode
and must be tied high when not in use.
VDD Power Supply To provide power supply voltage.
VSS Ground

3.0 MEMORY ORGANIZATION

The SST26VF064B/064BA SQI memory array is orga-
nized in uniform, 4 KByte erasable sectors with the fol-
lowing erasable blocks: eight 8 KByte parameter, two
32 KByte overlay, and 126 64 KByte overlay blocks.
See Figure 3-1.
Top of Memory Block
8 KByte
8 KByte
8 KByte
8 KByte
32 KByte
64 KByte
2 Sectors for 8 KByte blocks

...

4 KByte
4 KByte
64 KByte
...
4 KByte
4 KByte
64 KByte
32 KByte
8 KByte
8 KByte
8 KByte
8 KByte
Bottom of Memory Block

25119 F41.0
FIGURE 3-1: MEMORY MAP

4.0 DEVICE OPERATION

SST26VF064B/064BA support both Serial Peripheral bus master is in stand-by mode and no data is being
Interface (SPI) bus protocol and a 4-bit multiplexed SQI transferred. The SCK signal is low for Mode 0 and SCK
bus protocol. To provide backward compatibility to tra- signal is high for Mode 3. For both modes, the Serial
ditional SPI Serial Flash devices, the device’s initial Data I/O (SIO[3:0]) is sampled at the rising edge of the
state after a power-on reset is SPI mode which sup- SCK clock signal for input, and driven after the falling
ports multi-I/O (x1/x2/x4) Read/Write commands. A edge of the SCK clock signal for output. The traditional
command instruction configures the device to SQI SPI protocol uses separate input (SI) and output (SO)
mode. The dataflow in the SQI mode is similar to the data signals as shown in Figure 4-1. The SQI protocol
SPI mode, except it uses four multiplexed I/O signals uses four multiplexed signals, SIO[3:0], for both data in
for command, address, and data sequence. and data out, as shown in Figure 4-2. This means the
SQI Flash Memory supports both Mode 0 (0,0) and SQI protocol quadruples the traditional bus transfer
Mode 3 (1,1) bus operations. The difference between speed at the same clock frequency, without the need
the two modes is the state of the SCK signal when the for more pins on the package.
CE#
MODE 3 MODE 3
SCK MODE 0 MODE 0
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DON'T CARE
MSB
HIGH IMPEDANCE
SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB 25119 F03.0
FIGURE 4-1: SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)
CE#
MODE 3 MODE 3
CLK
MODE 0 MODE 0
SIO(3:0) C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 H3 L3
MSB
25119 F04.0
FIGURE 4-2: SQI SERIAL QUAD I/O PROTOCOL
4.1 Device Protection 4.1.1 INDIVIDUAL BLOCK PROTECTION

SST26VF064B/064BA offer a flexible memory protec- SST26VF064B/064BA have a Block-Protection regis-
tion scheme that allows the protection state of each ter which provides a software mechanism to write-lock
individual block to be controlled separately. In addition, the individual memory blocks and write-lock, and/or
the Write-Protection Lock-Down register prevents any read-lock, the individual parameter blocks. The Block-
change of the lock status during device operation. To Protection register is 144 bits wide: two bits each for the
avoid inadvertent writes during power-up, the device is eight 8 KByte parameter blocks (write-lock and read-
write-protected by default after a power-on reset cycle. lock), and one bit each for the remaining 32 KByte and
A Global Block-Protection Unlock command offers a 64 KByte overlay blocks (write-lock). See Table 5-6 for
single command cycle that unlocks the entire memory address range protected per register bit.
array for faster manufacturing throughput. Each bit in the Block-Protection register (BPR) can be
For extra protection, there is an additional non-volatile written to a ‘1’ (protected) or ‘0’ (unprotected). For the
register that can permanently write-protect the Block- parameter blocks, the most significant bit is for read-
Protection register bits for each individual block. Each lock, and the least significant bit is for write-lock. Read-
of the corresponding lock-down bits are one time pro- locking the parameter blocks provides additional secu-
grammable (OTP)—once written, they cannot be rity for sensitive data after retrieval (e.g., after initial
erased. Data that had been previously programmed boot). If a block is read-locked all reads to the block
into these blocks cannot be altered by programming or return data 00H.
erase and is not reversible

The Write Block-Protection Register command is a Writing a ‘0’ in any location in the nVWLDR has no
two-cycle command which requires that Write-Enable effect on either the nVWLDR or the corresponding
(WREN) is executed prior to the Write Block-Protection Write-Lock bit in the BPR.
Register command. The Global Block-Protection Note that if the Block-Protection register had been pre-
Unlock command clears all write protection bits in the viously locked down, see “Write-Protection Lock-Down
Block-Protection register. (Volatile)”, the device must be power cycled before
using the nVWLDR. If the Block-Protection register is
4.1.2 WRITE-PROTECTION LOCK-DOWN
locked down and the Write nVWLDR command is
(VOLATILE) accessed, the command will be ignored.
To prevent changes to the Block-Protection register,
use the Lock-Down Block-Protection Register (LBPR) 4.2 Hardware Write Protection
command to enable Write-Protection Lock-Down.
Once Write-Protection Lock-Down is enabled, the The hardware Write Protection pin (WP#) is used in
Block-Protection register can not be changed. To avoid conjunction with the WPEN and IOC bits in the config-
inadvertent lock down, the WREN command must be uration register to prohibit write operations to the Block-
executed prior to the LBPR command. Protection and Configuration registers. The WP# pin
function only works in SPI single-bit and dual-bit read
To reset Write-Protection Lock-Down, performing a power
mode when the IOC bit in the configuration register is
cycle on the device is required. The Write-Protection
set to ‘0’.
Lock-Down status may be read from the Status register.
The WP# pin function is disabled when the WPEN bit
4.1.3 WRITE-LOCK LOCK-DOWN (NON- in the configuration register is ‘0’. This allows installa-
VOLATILE) tion of the SST26VF064B/064BA in a system with a
grounded WP# pin while still enabling Write to the
The non-Volatile Write-Lock Lock-Down register is an
Block-Protection register. The Lock-Down function of
alternate register that permanently prevents changes
the Block-Protection Register supersedes the WP# pin,
to the block-protect bits. The non-Volatile Write-Lock
see Table 4-1 for Write Protection Lock-Down states.
Lock-Down register (nVWLDR) is 136 bits wide per
device: one bit each for the eight 8-KByte parameter The factory default setting at power-up of the WPEN bit
blocks, and one bit each for the remaining 32 KByte is ‘0’, disabling the Write Protect function of the WP#
and 64 KByte overlay blocks. See Table 5-6 for address after power-up. WPEN is a non-volatile bit; once the bit
range protected per register bit. is set to ‘1’, the Write Protect function of the WP# pin
continues to be enabled after power-up. The WP# pin
Writing ‘1’ to any or all of the nVWLDR bits disables the
only protects the Block-Protection Register and Config-
change mechanism for the corresponding Write-Lock
uration Register from changes. Therefore, if the WP#
bit in the BPR, and permanently sets this bit to a ‘1’
pin is set to low before or after a Program or Erase
(protected) state. After this change, both bits will be set
command, or while an internal Write is in progress, it
to ‘1’, regardless of the data entered in subsequent
will have no effect on the Write command.
writes to either the nVWLDR or the BPR. Subsequent
writes to the nVWLDR can only alter available locations The IOC bit takes priority over the WPEN bit in the con-
that have not been previously written to a ‘1’. This figuration register. When the IOC bit is ‘1’, the function
method provides write-protection for the corresponding of the WP# pin is disabled and the WPEN bit serves no
memory-array block by protecting it from future pro- function. When the IOC bit is ‘0’ and WPEN is ‘1’, set-
gram or erase operations. ting the WP# pin active low prohibits Write operations
to the Block Protection Register.

TABLE 4-1: WRITE PROTECTION LOCK-DOWN STATES

WP# IOC WPEN WPLD Execute WBPR Instruction Configuration Register
L 0 1 1 Not Allowed Protected
L 0 0 1 Not Allowed Writable
L 0 1 0 Not Allowed Protected
L 01 02 0 Allowed Writable
H 0 X 1 Not Allowed Writable
H 0 X 0 Allowed Writable
X 1 X 1 Not Allowed Writable
X 13 0 2
0 Allowed Writable
1. Default at power-up Register settings for SST26VF064B

2. Factory default setting is ‘0’. This is a non-volatile bit; default at power-up is the value set prior to power-down.
3. Default at power-up Register settings for SST26VF064BA
4.3 Security ID bit set to ‘0’ and the HOLD# pin function enabled;
SST26VF064BA ships with the IOC bit set to ‘1’ and the
SST26VF064B/064BA offer a 2 KByte Security ID (Sec HOLD# pin function disabled. The HOLD# pin is always
ID) feature. The Security ID space is divided into two disabled in SQI mode and only works in SPI single-bit
parts – one factory-programmed, 64-bit segment and and dual-bit read mode.
one user-programmable segment. The factory-pro-
grammed segment is programmed during manufactur- To activate the Hold mode, CE# must be in active low
ing with a unique number and cannot be changed. The state. The Hold mode begins when the SCK active low
user-programmable segment is left unprogrammed for state coincides with the falling edge of the HOLD# sig-
the customer to program as desired. nal. The Hold mode ends when the HOLD# signal’s ris-
ing edge coincides with the SCK active low state.
Use the Program Security ID (PSID) command to pro-
gram the Security ID using the address shown in Table If the falling edge of the HOLD# signal does not coin-
5-5. The Security ID can be locked using the Lockout cide with the SCK active low state, then the device
Security ID (LSID) command. This prevents any future enters Hold mode when the SCK next reaches the
write operations to the Security ID. active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active
The factory-programmed portion of the Security ID low state, then the device exits Hold mode when the
can’t be programmed by the user; neither the factory- SCK next reaches the active low state. See Figure 4-3.
programmed nor user-programmable areas can be
erased. Once the device enters Hold mode, SO will be in high
impedance state while SI and SCK can be VIL or VIH.
4.4 Hold Operation If CE# is driven active high during a Hold condition, it
resets the internal logic of the device. As long as
The HOLD# pin pauses active serial sequences with- HOLD# signal is low, the memory remains in the Hold
out resetting the clocking sequence. This pin is active condition. To resume communication with the device,
after every power up and only operates during SPI HOLD# must be driven active high, and CE# must be
single-bit and dual-bit modes. Two factory configura- driven active low.
tions are available: SST26VF064B ships with the IOC
SCK
HOLD#
Active Hold Active Hold Active
25119 F46.0
FIGURE 4-3: HOLD CONDITION WAVEFORM.

4.5 Status Register

The Status register is a read-only register that provides Protection register and/or Security ID are locked down.
the following status information: whether the flash During an internal Erase or Program operation, the Sta-
memory array is available for any Read or Write oper- tus register may be read to determine the completion of
ation, if the device is write-enabled, whether an erase an operation in progress. Table 4-2 describes the func-
or program operation is suspended, and if the Block- tion of each bit in the Status register.
TABLE 4-2: STATUS REGISTER

Default at Read/Write (R/
Bit Name Function Power-up W)
0 BUSY Write operation status 0 R
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 WEL Write-Enable Latch status 0 R
1 = Device is write-enabled
0 = Device is not write-enabled
2 WSE Write Suspend-Erase status 0 R
1 = Erase suspended
0 = Erase is not suspended
3 WSP Write Suspend-Program status 0 R
1 = Program suspended
0 = Program is not suspended
4 WPLD Write Protection Lock-Down status 0 R
1 = Write Protection Lock-Down enabled
0 = Write Protection Lock-Down disabled
5 SEC1 Security ID status 01 R
1 = Security ID space locked
0 = Security ID space not locked
6 RES Reserved for future use 0 R
7 BUSY Write operation status 0 R
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1. The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout Security ID instruction, oth-
erwise default at power-up is ‘0’.

4.5.1 WRITE-ENABLE LATCH (WEL) 4.5.3 WRITE SUSPEND PROGRAM

The Write-Enable Latch (WEL) bit indicates the status STATUS (WSP)
of the internal memory’s Write-Enable Latch. If the The Write Suspend-Program status (WSP) bit indicates
WEL bit is set to ‘1’, the device is write enabled. If the when a Program operation has been suspended. The
bit is set to ‘0’ (reset), the device is not write enabled WSP is ‘1’ after the host issues a suspend command
and does not accept any memory Program or Erase, during the Program operation. Once the suspended
Protection Register Write, or Lock-Down commands. Program resumes, the WSP bit is reset to ‘0’.
The Write-Enable Latch bit is automatically reset under
the following conditions: 4.5.4 WRITE PROTECTION LOCK-DOWN
• Power-up STATUS (WPLD)
• Reset The Write Protection Lock-Down status (WPLD) bit
• Write-Disable (WRDI) instruction completion indicates when the Block-Protection register is locked-
down to prevent changes to the protection settings.
• Page-Program instruction completion
The WPLD is ‘1’ after the host issues a Lock-Down
• Sector-Erase instruction completion Block-Protection command. After a power cycle, the
• Block-Erase instruction completion WPLD bit is reset to ‘0’.
• Chip-Erase instruction completion
• Write-Block-Protection register instruction 4.5.5 SECURITY ID STATUS (SEC)
• Lock-Down Block-Protection register instruction The Security ID Status (SEC) bit indicates when the
• Program Security ID instruction completion Security ID space is locked to prevent a Write com-
mand. The SEC is ‘1’ after the host issues a Lockout
• Lockout Security ID instruction completion
SID command. Once the host issues a Lockout SID
• Write-Suspend instruction command, the SEC bit can never be reset to ‘0.’
• SPI Quad Page program instruction completion
• Write Status Register 4.5.6 BUSY
The Busy bit determines whether there is an internal
4.5.2 WRITE SUSPEND ERASE STATUS Erase or Program operation in progress. If the BUSY
(WSE) bit is ‘1’, the device is busy with an internal Erase or
The Write Suspend-Erase status (WSE) indicates Program operation. If the bit is ‘0’, no Erase or Program
when an Erase operation has been suspended. The operation is in progress.
WSE bit is ‘1’ after the host issues a suspend command
during an Erase operation. Once the suspended Erase 4.5.7 CONFIGURATION REGISTER
resumes, the WSE bit is reset to ‘0’. The Configuration register is a Read/Write register that
stores a variety of configuration information. See Table
4-3 for the function of each bit in the register.
TABLE 4-3: CONFIGURATION REGISTER

Bit Name Function Default at Power-up Read/Write (R/W)
0 RES Reserved 0 R
IOC I/O Configuration for SPI Mode 01 R/W
1 1 = WP# and HOLD# pins disabled
0 = WP# and HOLD# pins enabled
2 RES Reserved 0 R
BPNV Block-Protection Volatility State 1 R
3 1 = No memory block has been permanently locked
0 = Any block has been permanently locked
4 RES Reserved 0 R
5 RES Reserved 0 R
6 RES Reserved 0 R
WPEN Write-Protection Pin (WP#) Enable 02 R/W
7 1 = WP# enabled
0 = WP# disabled
1. SST26VF064B default at Power-up is ‘0’

SST26VF064BA default at Power-up is ‘1’
2. Factory default setting. This is a non-volatile bit; default at power-up will be the setting prior to power-down.

4.5.8 I/O CONFIGURATION (IOC)

The I/O Configuration (IOC) bit re-configures the I/O
pins. The IOC bit is set by writing a ‘1’ to Bit 1 of the
Configuration register. When IOC bit is ‘0’ the WP# pin
and HOLD# pin are enabled (SPI or Dual Configuration
setup). When IOC bit is set to ‘1’ the SIO2 pin and SIO3
pin are enabled (SPI Quad I/O Configuration setup).
The IOC bit must be set to ‘1’ before issuing the follow-
ing SPI commands: SQOR (6BH), SQIOR (EBH),
RBSPI (ECH), and SPI Quad page program (32H).
Without setting the IOC bit to ‘1’, those SPI commands
are not valid. The I/O configuration bit does not apply
when in SQI mode. The default at power-up for
SST26VF064B is ‘0’ and for SST26VF064BA is ‘1’.
4.5.9 BLOCK-PROTECTION VOLATILITY

STATE (BPNV)
The Block-Protection Volatility State bit indicates
whether any block has been permanently locked with
the nVWLDR. When no bits in the nVWLDR have been
set, the BPNV is ‘1’; this is the default state from the
factory. When one or more bits in the nVWLDR are set
to ‘1’, the BPNV bit will also be ‘0’ from that point for-
ward, even after power-up.
4.5.10 WRITE-PROTECT ENABLE (WPEN)

The Write-Protect Enable (WPEN) bit is a non-volatile
bit that enables the WP# pin.
The Write-Protect (WP#) pin and the Write-Protect
Enable (WPEN) bit control the programmable hard-
ware write-protect feature. Setting the WP# pin to low,
and the WPEN bit to ‘1’, enables Hardware write-pro-
tection. To disable Hardware write protection, set either
the WP# pin to high or the WPEN bit to ‘0’. There is
latency associated with writing to the WPEN bit. Poll
the BUSY bit in the Status register, or wait TWPEN, for
the completion of the internal, self-timed Write opera-
tion. When the chip is hardware write protected, only
Write operations to Block-Protection and Configuration
registers are disabled. See “Hardware Write Protec-
tion” on page 7 and Table 4-1 on page 8 for more infor-
mation about the functionality of the WPEN bit.

5.0 INSTRUCTIONS
Instructions are used to read, write (erase and pro-
gram), and configure the SST26VF064B/064BA. The
complete list of the instructions is provided in Table 5-1.
TABLE 5-1: DEVICE OPERATION INSTRUCTIONS FOR SST26VF064B/064BA

Command Mode Address Dummy Data Max
Instruction Description Cycle1 SPI SQI Cycle(s)2, 3 Cycle(s)3 Cycle(s)3 Freq
Configuration
NOP No Operation 00H X X 0 0 0 104
RSTEN Reset Enable 66H X X 0 0 0 MHz
RST4 Reset Memory 99H X X 0 0 0
EQIO Enable Quad I/O 38H X 0 0 0
RSTQIO5 Reset Quad I/O FFH X X 0 0 0
RDSR Read Status Register 05H X 0 0 1 to ∞
X 0 1 1 to ∞
WRSR Write Status Register 01H X X 0 0 2
RDCR Read Configuration 35H X 0 0 1 to ∞
Register X 0 1 1 to ∞
Read
Read Read Memory 03H X 3 0 1 to ∞ 40
MHz
High-Speed Read Memory at Higher 0BH X 3 3 1 to ∞ 104
Read Speed X 3 1 1 to ∞ MHz
SQOR6 SPI Quad Output Read 6BH X 3 1 1 to ∞
SQIOR7 SPI Quad I/O Read EBH X 3 3 1 to ∞
SDOR8 SPI Dual Output Read 3BH X 3 1 1 to ∞
SDIOR9 SPI Dual I/O Read BBH X 3 1 1 to ∞ 80 MHz
SB Set Burst Length C0H X X 0 0 1 104
RBSQI SQI Read Burst with Wrap 0CH X 3 3 n to ∞ MHz
RBSPI7 SPI Read Burst with Wrap ECH X 3 3 n to ∞
Identification
JEDEC-ID JEDEC-ID Read 9FH X 0 0 3 to ∞ 104
Quad J-ID Quad I/O J-ID Read AFH X 0 1 3 to ∞ MHz
SFDP Serial Flash Discoverable 5AH X 3 1 1 to ∞
Parameters
Write
WREN Write Enable 06H X X 0 0 0 104
WRDI Write Disable 04H X X 0 0 0 MHz
SE10 Erase 4 KBytes of Memory 20H X X 3 0 0
Array
BE11 Erase 64, 32 or 8 KBytes of D8H X X 3 0 0
Memory Array
CE Erase Full Array C7H X X 0 0 0
PP Page Program 02H X X 3 0 1 to 256
SPI Quad SQI Quad Page 32H X 3 0 1 to 256
PP6 Program

TABLE 5-1: DEVICE OPERATION INSTRUCTIONS FOR SST26VF064B/064BA

Command Mode Address Dummy Data Max
Instruction Description Cycle1 SPI SQI Cycle(s)2, 3 Cycle(s)3 Cycle(s)3 Freq
WRSU Suspends Program/Erase B0H X X 0 0 0 104
WRRE Resumes Program/Erase 30H X X 0 0 0 MHz
Protection
RBPR Read Block-Protection 72H X 0 0 1 to 18 104
Register X 0 1 1 to 18 MHz
WBPR Write Block-Protection 42H X X 0 0 1 to 18
Register
LBPR Lock Down 8DH X X 0 0 0
Block-Protection
Register
nVWLDR non-Volatile Write Lock- E8H X X 0 0 1 to 18
Down Register
ULBPR Global Block Protection 98H X X 0 0 0
Unlock
RSID Read Security ID 88H X 2 1 1 to 2048
X 2 3 1 to 2048
PSID Program User A5H X X 2 0 1 to 256
Security ID area
LSID Lockout Security ID Pro- 85H X X 0 0 0
gramming
1. Command cycle is two clock periods in SQI mode and eight clock periods in SPI mode.
2. Address bits above the most significant bit of each density can be VIL or VIH.
3. Address, Dummy/Mode bits, and Data cycles are two clock periods in SQI and eight clock periods in SPI mode.
4. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
5. Device accepts eight-clock command in SPI mode, or two-clock command in SQI mode.
6. Data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command.
7. Address, Dummy/Mode bits, and data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command.
8. Data cycles are four clock periods.
9. Address, Dummy/Mode bits, and Data cycles are four clock periods.
10. Sector Addresses: Use AMS - A12, remaining address are don’t care, but must be set to VIL or VIH.
11. Blocks are 64 KByte, 32 KByte, or 8KByte, depending on location. Block Erase Address: AMS - A16 for 64 KByte; AMS - A15
for 32 KByte; AMS - A13 for 8 KByte. Remaining addresses are don’t care, but must be set to VIL or VIH.

5.1 No Operation (NOP) The Reset operation requires the Reset-Enable com-
mand followed by the Reset command. Any command
The No Operation command only cancels a Reset other than the Reset command after the Reset-Enable
Enable command. NOP has no impact on any other command will disable the Reset-Enable.
command.
Once the Reset-Enable and Reset commands are suc-
cessfully executed, the device returns to normal opera-
5.2 Reset-Enable (RSTEN) and Reset tion Read mode and then does the following: resets the
(RST) protocol to SPI mode, resets the burst length to 8
The Reset operation is used as a system (software) Bytes, clears all the bits, except for bit 4 (WPLD) and
reset that puts the device in normal operating Ready bit 5 (SEC), in the Status register to their default states,
mode. This operation consists of two commands: and clears bit 1 (IOC) in the configuration register to its
Reset-Enable (RSTEN) followed by Reset (RST). default state. A device reset during an active Program
or Erase operation aborts the operation, which can
To reset the SST26VF064B/064BA, the host drives cause the data of the targeted address range to be cor-
CE# low, sends the Reset-Enable command (66H), rupted or lost. Depending on the prior operation, the
and drives CE# high. Next, the host drives CE# low reset timing may vary. Recovery from a Write operation
again, sends the Reset command (99H), and drives requires more latency time than recovery from other
CE# high, see Figure 5-1. operations. See Table 8-2 on page 48 for Rest timing
parameters.
TCPH
CE#
MODE 3 MODE 3 MODE 3
CLK
SIO(3:0) C1 C0 C3 C2
25119 F05.0
Note: C[1:0] = 66H; C[3:2] = 99H
FIGURE 5-1: RESET SEQUENCE
5.3 Read (40 MHz) will automatically increment until the highest memory
address is reached. Once the highest memory address
The Read instruction, 03H, is supported in SPI bus pro- is reached, the address pointer will automatically return
tocol only with clock frequencies up to 40 MHz. This to the beginning (wrap-around) of the address space.
command is not supported in SQI bus protocol. The
device outputs the data starting from the specified Initiate the Read instruction by executing an 8-bit com-
address location, then continuously streams the data mand, 03H, followed by address bits A[23:0]. CE# must
output through all addresses until terminated by a low- remain active low for the duration of the Read cycle.
to-high transition on CE#. The internal address pointer See Figure 5-2 for Read Sequence.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70
SCK MODE 0
SI 03 ADD. ADD. ADD.

MSB MSB
N N+1 N+2 N+3 N+4
HIGH IMPEDANCE DOUT DOUT DOUT DOUT DOUT
SO
MSB 25119 F29.0
FIGURE 5-2: READ SEQUENCE (SPI)

5.4 Enable Quad I/O (EQIO)

The Enable Quad I/O (EQIO) instruction, 38H, enables expected to be 4-bit multiplexed input/output (SQI
the flash device for SQI bus operation. Upon comple- mode) until a power cycle or a “Reset Quad I/O instruc-
tion of the instruction, all instructions thereafter are tion” is executed. See Figure 5-3.
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SIO0 38
SIO[3:1]
25119 F43.0
Note: SIO[3:1] must be driven VIH
FIGURE 5-3: ENABLE QUAD I/O SEQUENCE
5.5 Reset Quad I/O (RSTQIO) where it can accept new command instruction. An addi-
tional RSTQIO is required to reset the device to SPI
The Reset Quad I/O instruction, FFH, resets the device mode.
to 1-bit SPI protocol operation or exits the Set Mode
configuration during a read sequence. This command To execute a Reset Quad I/O operation, the host drives
allows the flash device to return to the default I/O state CE# low, sends the Reset Quad I/O command cycle
(SPI) without a power cycle, and executes in either 1- (FFH) then, drives CE# high. Execute the instruction in
bit or 4-bit mode. If the device is in the Set Mode con- either SPI (8 clocks) or SQI (2 clocks) command
figuration, while in SQI High-Speed Read mode, the cycles. For SPI, SIO[3:1] are don’t care for this com-
RSTQIO command will only return the device to a state mand, but should be driven to VIH or VIL. See Figures
5-4 and 5-5.
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SIO0 FF
SIO[3:1]
25119 F73.0
Note: SIO[3:1] must be driven VIH
FIGURE 5-4: RESET QUAD I/O SEQUENCE (SPI)
CE#
MODE 3 0 1
SCK MODE 0
SIO(3:0) F F
25119 F74.0
FIGURE 5-5: RESET QUAD I/O SEQUENCE (SQI)

5.6 High-Speed Read (104 MHz) Initiate High-Speed Read by executing an 8-bit com-
mand, 0BH, followed by address bits A[23-0] and a
The High-Speed Read instruction, 0BH, is supported in dummy byte. CE# must remain active low for the dura-
both SPI bus protocol and SQI protocol. On power-up, tion of the High-Speed Read cycle. See Figure 5-6 for
the device is set to use SPI. the High-Speed Read sequence for SPI bus protocol.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80
SCK MODE 0
SI/SIO0 0B ADD. ADD. ADD. X
N N+1 N+2 N+3 N+4

HIGH IMPEDANCE
SO/SIO1 DOUT DOUT DOUT DOUT DOUT
MSB
25119 F31.0
FIGURE 5-6: HIGH-SPEED READ SEQUENCE (SPI) (C[1:0] = 0BH)

In SQI protocol, the host drives CE# low then send the mand, 0BH, and does not require the op-code to be
Read command cycle command, 0BH, followed by entered again. The host may initiate the next Read
three address cycles, a Set Mode Configuration cycle, cycle by driving CE# low, then sending the four-bits
and two dummy cycles. Each cycle is two nibbles input for address A[23:0], followed by the Set Mode
(clocks) long, most significant nibble first. configuration bits M[7:0], and two dummy cycles. After
After the dummy cycles, the device outputs data on the the two dummy cycles, the device outputs the data
falling edge of the SCK signal starting from the speci- starting from the specified address location. There are
fied address location. The device continually streams no restrictions on address location access.
data output through all addresses until terminated by a When M[7:0] is any value other than AXH, the device
low-to-high transition on CE#. The internal address expects the next instruction initiated to be a command
pointer automatically increments until the highest mem- instruction. To reset/exit the Set Mode configuration,
ory address is reached, at which point the address execute the Reset Quad I/O command, FFH. While in
pointer returns to address location 000000H. During the Set Mode configuration, the RSTQIO command will
this operation, blocks that are Read-locked will output only return the device to a state where it can accept
data 00H. new command instruction. An additional RSTQIO is
The Set Mode Configuration bit M[7:0] indicates if the required to reset the device to SPI mode. See Figure 5-
next instruction cycle is another SQI High-Speed Read 10 for the SPI Quad I/O Mode Read sequence when
command. When M[7:0] = AXH, the device expects the M[7:0] = AXH.
next continuous instruction to be another Read com-
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 20 21
SCK
MODE 0 MSN LSN
SIO(3:0) C0 C1 A5 A4 A3 A2 A1 A0 M1 M0 X X X X H0 L0 H8 L8
Command Address Mode Dummy Data Byte 0 Data Byte 7
25119 F47.0
Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble
Hx = High Data Nibble, Lx = Low Data Nibble C[1:0]=0BH
FIGURE 5-7: HIGH-SPEED READ SEQUENCE (SQI)

5.7 SPI Quad-Output Read

The SPI Quad-Output Read instruction supports up to Following the dummy byte, the device outputs data
104 MHz frequency. SST26VF064B requires the IOC from SIO[3:0] starting from the specified address loca-
bit in the configuration register to be set to ‘1’ prior to tion. The device continually streams data output
executing the command. Initiate SPI Quad-Output through all addresses until terminated by a low-to-high
Read by executing an 8-bit command, 6BH, followed transition on CE#. The internal address pointer auto-
by address bits A[23-0] and a dummy byte. CE# must matically increments until the highest memory address
remain active low for the duration of the SPI Quad is reached, at which point the address pointer returns
Mode Read. See Figure 5-8 for the SPI Quad Output to the beginning of the address space.
Read sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 41
SCK MODE 0
SIO0 6BH A[23:16] A[15:8] A[7:0] X b4 b0 b4 b0

Data Data
OP Code Address Dummy Byte 0 Byte N
SIO1 b5 b1 b5 b1
SIO2 b6 b2 b6 b2
SIO3 b7 b3 b7 b3
25119 F48.3
FIGURE 5-8: SPI QUAD OUTPUT READ

5.8 SPI Quad I/O Read

The SPI Quad I/O Read (SQIOR) instruction supports The Set Mode Configuration bit M[7:0] indicates if the
up to 104 MHz frequency. SST26VF064B requires the next instruction cycle is another SPI Quad I/O Read
IOC bit in the configuration register to be set to ‘1’ prior command. When M[7:0] = AXH, the device expects the
to executing the command. Initiate SQIOR by execut- next continuous instruction to be another Read com-
ing an 8-bit command, EBH. The device then switches mand, EBH, and does not require the op-code to be
to 4-bit I/O mode for address bits A[23-0], followed by entered again. The host may set the next SQIOR cycle
the Set Mode configuration bits M[7:0], and two dummy by driving CE# low, then sending the four-bit wide input
bytes.CE# must remain active low for the duration of for address A[23:0], followed by the Set Mode configu-
the SPI Quad I/O Read. See Figure 5-9 for the SPI ration bits M[7:0], and two dummy cycles. After the two
Quad I/O Read sequence. dummy cycles, the device outputs the data starting
Following the dummy bytes, the device outputs data from the specified address location. There are no
from the specified address location. The device contin- restrictions on address location access.
ually streams data output through all addresses until When M[7:0] is any value other than AXH, the device
terminated by a low-to-high transition on CE#. The expects the next instruction initiated to be a command
internal address pointer automatically increments until instruction. To reset/exit the Set Mode configuration,
the highest memory address is reached, at which point execute the Reset Quad I/O command, FFH. See Fig-
the address pointer returns to the beginning of the ure 5-10 for the SPI Quad I/O Mode Read sequence
address space. when M[7:0] = AXH.
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK MODE 0
SIO0 EBH A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0 b4 b0
SIO1 A21 A17 A13 A9 A5 A1 M5 M1 X X X X b5 b1 b5 b1

MSN LSN

Set Data Data
Address Mode Dummy Byte 0 Byte 1
25119 F49.2
FIGURE 5-9: SPI QUAD I/O READ SEQUENCE

CE#
0 1 2 3 4 5 6 7 8 9 10 11 12 13
SCK
SIO0 b4 b0 b4 b0 A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0

MSN LSN
Data Data Set Data
Byte Byte Address Mode Dummy Byte 0
N N+1
25119 F50.2
FIGURE 5-10: BACK-TO-BACK SPI QUAD I/O READ SEQUENCES WHEN M[7:0] = AXH
5.9 Set Burst sends the Set Burst command cycle (C0H) and one
data cycle, then drives CE# high. After power-up or
The Set Burst command specifies the number of bytes reset, the burst length is set to eight Bytes (00H). See
to be output during a Read Burst command before the Table 5-2 for burst length data and Figures 5-11 and 5-
device wraps around. It supports both SPI and SQI pro- 12 for the sequences.
tocols. To set the burst length the host drives CE# low,
TABLE 5-2: BURST LENGTH DATA
Burst Length High Nibble (H0) Low Nibble (L0)
8 Bytes 0h 0h
16 Bytes 0h 1h
32 Bytes 0h 2h
64 Bytes 0h 3h
CE#
MODE 3 0 1 2 3
SCK MODE 0
SIO(3:0) C1 C0 H0 L0
MSN LSN
25119 F32.0
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0]=C0H
FIGURE 5-11: SET BURST LENGTH SEQUENCE (SQI)

CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK MODE 0
SIO0 C0 DIN
SIO[3:1]
25119 F51.0
Note: SIO[3:1] must be driven VIH.
FIGURE 5-12: SET BURST LENGTH SEQUENCE (SPI)
5.10 SQI Read Burst with Wrap (RBSQI) 5.11 SPI Read Burst with Wrap (RBSPI)
SQI Read Burst with wrap is similar to High Speed SPI Read Burst with Wrap (RBSPI) is similar to SPI
Read in SQI mode, except data will output continuously Quad I/O Read except the data will output continuously
within the burst length until a low-to-high transition on within the burst length until a low-to-high transition on
CE#. To execute a SQI Read Burst operation, drive CE#. To execute a SPI Read Burst with Wrap opera-
CE# low then send the Read Burst command cycle tion, drive CE# low, then send the Read Burst com-
(0CH), followed by three address cycles, and then mand cycle (ECH), followed by three address cycles,
three dummy cycles. Each cycle is two nibbles (clocks) and then three dummy cycles.
long, most significant nibble first. After the dummy cycle, the device outputs data on the
After the dummy cycles, the device outputs data on the falling edge of the SCK signal starting from the speci-
falling edge of the SCK signal starting from the specified address location. The data output stream is contin-
fied address location. The data output stream is continuous through all addresses until terminated by a low-to-
uous through all addresses until terminated by a low-to- high transition on CE#.
high transition on CE#. During RBSPI, the internal address pointer automati-
During RBSQI, the internal address pointer automatically increments until the last byte of the burst is
cally increments until the last byte of the burst is reached, then it wraps around to the first byte of the
reached, then it wraps around to the first byte of the burst. All bursts are aligned to addresses within the
burst. All bursts are aligned to addresses within the burst length, see Table 5-3. For example, if the burst
burst length, see Table 5-3. For example, if the burst length is eight Bytes, and the start address is 06h, the
length is eight Bytes, and the start address is 06h, the burst sequence would be: 06h, 07h, 00h, 01h, 02h,
burst sequence would be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05h, 06h, etc. The pattern repeats until the
03h, 04h, 05h, 06h, etc. The pattern repeats until the command is terminated by a low-to-high transition on
command is terminated by a low-to-high transition on CE#.
CE#. During this operation, blocks that are Read-locked will
During this operation, blocks that are Read-locked will output data 00H.
output data 00H.
TABLE 5-3: BURST ADDRESS RANGES
Burst Length Burst Address Ranges
8 Bytes 00-07H, 08-0FH, 10-17H, 18-1FH...
16 Bytes 00-0FH, 10-1FH, 20-2FH, 30-3FH...
32 Bytes 00-1FH, 20-3FH, 40-5FH, 60-7FH...
64 Bytes 00-3FH, 40-7FH, 80-BFH, C0-FFH
0

5.12 SPI Dual-Output Read Following the dummy byte, the SST26VF064B/064BA
outputs data from SIO[1:0] starting from the specified
The SPI Dual-Output Read instruction supports up to address location. The device continually streams data
104 MHz frequency. Initiate SPI Dual-Output Read by output through all addresses until terminated by a low-
executing an 8-bit command, 3BH, followed by address to-high transition on CE#. The internal address pointer
bits A[23-0] and a dummy byte. CE# must remain automatically increments until the highest memory
active low for the duration of the SPI Dual-Output Read address is reached, at which point the address pointer
operation. See Figure 5-13 for the SPI Quad Output returns to the beginning of the address space.
Read sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 41
SCK MODE 0
SIO0 3BH A[23:16] A[15:8] A[7:0] X b6 b5 b3 b1 b6 b5 b3 b1

MSB
SIO1 b7 b4 b2 b0 b7 b4 b2 b0
Data Data
OP Code Address Dummy Byte 0 Byte N
Note: MSB = Most Significant Bit. 25119 F52.3
FIGURE 5-13: FAST READ, DUAL-OUTPUT SEQUENCE
5.13 SPI Dual I/O Read When M[7:0] is any value other than AXH, the device
expects the next instruction initiated to be a command
The SPI Dual I/O Read (SDIOR) instruction supports instruction. To reset/exit the Set Mode configuration,
up to 80 MHz frequency. Initiate SDIOR by executing execute the Reset Quad I/O command, FFH. See Fig-
an 8-bit command, BBH. The device then switches to ure 5-15 for the SPI Dual I/O Read sequence when
2-bit I/O mode for address bits A[23-0], followed by the M[7:0] = AXH.
Set Mode configuration bits M[7:0], and two dummy
bytes.CE# must remain active low for the duration of
the SPI Dual I/O Read. See Figure 5-14 for the SPI
Dual I/O Read sequence.
Following the dummy bytes, the SST26VF064B/064BA
outputs data from the specified address location. The
device continually streams data output through all
addresses until terminated by a low-to-high transition
on CE#. The internal address pointer automatically
increments until the highest memory address is
reached, at which point the address pointer returns to
the beginning of the address space.
The Set Mode Configuration bit M[7:0] indicates if the
next instruction cycle is another SPI Dual I/O Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another SDIOR com-
mand, BBH, and does not require the op-code to be
entered again. The host may set the next SDIOR cycle
by driving CE# low, then sending the two-bit wide input
for address A[23:0], followed by the Set Mode configu-
ration bits M[7:0], and two dummy cycles. After the two
dummy cycles, the device outputs the data starting
from the specified address location. There are no
restrictions on address location access.

CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK MODE 0
SIO0 BBH 6 4 2 0 6 4 2 0 6 4 2 0 6 4
SIO1 7 5 3 1 7 5 3 1 7 5 3 1 7 5
A[23:16] A[15:8] A[7:0] M[7:0]
CE#(cont’)
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK(cont’)
I/O Switches from Input to Output
SIO0(cont’) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
MSB MSB MSB MSB
SIO1(cont’) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte 0 Byte 1 Byte 2 Byte 3
25119 F53.1
Note: MSB= Most Significant Bit, LSB = Least Significant Bit
FIGURE 5-14: SPI DUAL I/O READ SEQUENCE
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK MODE 0
I/O Switch
SIO0 6 4 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4
MSB MSB
SIO1 7 5 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5
A[23:16] A[15:8] A[7:0] M[7:0]
CE#(cont’)
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK(cont’)
I/O Switches from Input to Output
SIO0(cont’) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
MSB MSB MSB MSB
SIO1(cont’) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte 0 Byte 1 Byte 2 Byte 3
25119 F54.1
Note: MSB= Most Significant Bit, LSB = Least Significant Bit
FIGURE 5-15: BACK-TO-BACK SPI DUAL I/O READ SEQUENCES WHEN M[7:0] = AXH

5.14 JEDEC-ID Read (SPI Protocol) Immediately following the command cycle,
SST26VF064B/064BA output data on the falling edge
Using traditional SPI protocol, the JEDEC-ID Read of the SCK signal. The data output stream is continu-
instruction identifies the device as SST26VF064B/ ous until terminated by a low-to-high transition on CE#.
064BA and the manufacturer as Microchip®. To exe- The device outputs three bytes of data: manufacturer,
cute a JECEC-ID operation the host drives CE# low device type, and device ID, see Table 5-4. See Figure
then sends the JEDEC-ID command cycle (9FH). 5-16 for instruction sequence.
TABLE 5-4: DEVICE ID DATA OUTPUT

Device ID
Product Manufacturer ID (Byte 1) Device Type (Byte 2) Device ID (Byte 3)
SST26VF064B/064BA BFH 26H 43H
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCK MODE 0
SI 9F
HIGH IMPEDANCE
SO BF 26 Device ID
MSB MSB
25119 F38.0
FIGURE 5-16: JEDEC-ID SEQUENCE (SPI)
5.15 Read Quad J-ID Read (SQI Immediately following the command cycle and one
Protocol) dummy cycle, SST26VF064B/064BA output data on
the falling edge of the SCK signal. The data output
The Read Quad J-ID Read instruction identifies the stream is continuous until terminated by a low-to-high
device as SST26VF064B/064BA and manufacturer as transition of CE#. The device outputs three bytes of
Microchip. To execute a Quad J-ID operation the host data: manufacturer, device type, and device ID, see
drives CE# low and then sends the Quad J-ID com- Table 5-4. See Figure 5-17 for instruction sequence.
mand cycle (AFH). Each cycle is two nibbles (clocks)
long, most significant nibble first.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 N
SCK
MODE 0 MSN LSN
SIO(3:0) C0 C1 X X H0 L0 H1 L1 H2 L2 H0 L0 H1 L1 HN LN
Dummy BFH 26H Device ID BFH 26H N
25119 F55.0
Note: MSN = Most significant Nibble; LSN= Least Significant Nibble. C{1:0]=AFH
FIGURE 5-17: QUAD J-ID READ SEQUENCE

5.16 Serial Flash Discoverable ware support for all future Serial Flash device families.
Parameters (SFDP) See Table 11-1 on page 59 for address and data val-
ues.
The Serial Flash Discoverable Parameters (SFDP)
Initiate SFDP by executing an 8-bit command, 5AH, fol-
contain information describing the characteristics of the
lowed by address bits A[23-0] and a dummy byte. CE#
device. This allows device-independent, JEDEC ID-
must remain active low for the duration of the SFDP
independent, and forward/backward compatible soft-
cycle. For the SFDP sequence, see Figure 5-18.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80
SCK MODE 0
SI 5A ADD. ADD. ADD. X
N N+1 N+2 N+3 N+4

HIGH IMPEDANCE
SO DOUT DOUT DOUT DOUT DOUT
MSB
25119 F56.0
FIGURE 5-18: SERIAL FLASH DISCOVERABLE PARAMETERS SEQUENCE
5.17 Sector-Erase To execute a Sector-Erase operation, the host drives

CE# low, then sends the Sector Erase command cycle
The Sector-Erase instruction clears all bits in the (20H) and three address cycles, and then drives CE#
selected 4 KByte sector to ‘1,’ but it does not change a high. Address bits [AMS:A12] (AMS = Most Significant
protected memory area. Prior to any write operation, Address) determine the sector address (SAX); the
the Write-Enable (WREN) instruction must be exe- remaining address bits can be VIL or VIH. To identify the
cuted. completion of the internal, self-timed, Write operation,
poll the BUSY bit in the Status register, or wait TSE. See
Figures 5-19 and 5-20 for the Sector-Erase sequence.
CE#
MODE 3 0 1 2 4 6
SCK MODE 0
SIO(3:0) C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
25119 F07.0
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 20H
FIGURE 5-19: 4 KBYTE SECTOR-ERASE SEQUENCE– SQI MODE
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0
SI 20 ADD. ADD. ADD.

MSB MSB
SO HIGH IMPEDANCE
25119 F57.0
FIGURE 5-20: 4 KBYTE SECTOR-ERASE SEQUENCE (SPI)

5.18 Block-Erase To execute a Block-Erase operation, the host drives

CE# low then sends the Block-Erase command cycle
The Block-Erase instruction clears all bits in the (D8H), three address cycles, then drives CE# high.
selected block to ‘1’. Block sizes can be 8 KByte, 32 Address bits AMS-A13 determine the block address
KByte or 64 KByte depending on address, see Figure (BAX); the remaining address bits can be VIL or VIH. For
3-1, Memory Map, for details. A Block-Erase instruction 32 KByte blocks, A14:A13 can be VIL or VIH; for 64
applied to a protected memory area will be ignored. KByte blocks, A15:A13 can be VIL or VIH. Poll the BUSY
Prior to any write operation, execute the WREN instruc- bit in the Status register, or wait TBE, for the completion
tion. Keep CE# active low for the duration of any com- of the internal, self-timed, Block-Erase operation. See
mand sequence. Figures 5-21 and 5-22 for the Block-Erase sequence.
CE#
MODE 3 0 1 2 4 6
SCK MODE 0
SIO(3:0) C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
25119 F08.0
Note: MSN = Most Significant Nibble,

LSN = Least Significant Nibble
C[1:0] = D8H
FIGURE 5-21: BLOCK-ERASE SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31
SCK MODE 0
SI D8 ADDR ADDR ADDR

MSB MSB
SO HIGH IMPEDANCE
25119 F58.0
FIGURE 5-22: BLOCK-ERASE SEQUENCE (SPI)

5.19 Chip-Erase To execute a Chip-Erase operation, the host drives

CE# low, sends the Chip-Erase command cycle (C7H),
The Chip-Erase instruction clears all bits in the device then drives CE# high. Poll the BUSY bit in the Status
to ‘1.’ The Chip-Erase instruction is ignored if any of the register, or wait TSCE, for the completion of the internal,
memory area is protected. Prior to any write operation, self-timed, Write operation. See Figures 5-23 and 5-24
execute the WREN instruction. for the Chip Erase sequence.
CE#
MODE 3 0 1
SCK MODE 0
SIO(3:0) C1 C0
25119 F09.1
Note: C[1:0] = C7H
FIGURE 5-23: CHIP-ERASE SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI C7
MSB
SO HIGH IMPEDANCE
25119 F59.0
FIGURE 5-24: CHIP-ERASE SEQUENCE (SPI)

5.20 Page-Program partial Byte to be ignored. Poll the BUSY bit in the Sta-
tus register, or wait TPP, for the completion of the inter-
The Page-Program instruction programs up to 256 nal, self-timed, Write operation. See Figures 5-25 and
Bytes of data in the memory, and supports both SPI 5-26 for the Page-Program sequence.
and SQI protocols. The data for the selected page
address must be in the erased state (FFH) before initi- When executing Page-Program, the memory range for
ating the Page-Program operation. A Page-Program the SST26VF064B/064BA is divided into 256 Byte
applied to a protected memory area will be ignored. page boundaries. The device handles shifting of more
Prior to the program operation, execute the WREN than 256 Bytes of data by maintaining the last 256
instruction. Bytes of data as the correct data to be programmed. If
the target address for the Page-Program instruction is
To execute a Page-Program operation, the host drives not the beginning of the page boundary (A[7:0] are not
CE# low then sends the Page Program command cycle all zero), and the number of bytes of data input exceeds
(02H), three address cycles followed by the data to be or overlaps the end of the address of the page bound-
programmed, then drives CE# high. The programmed ary, the excess data inputs wrap around and will be pro-
data must be between 1 to 256 Bytes and in whole Byte grammed at the start of that target page.
increments; sending less than a full Byte will cause the
CE#
MODE 3 0 2 4 6 8 10 12
SCK MODE 0
SIO(3:0) C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 HN LN
MSN LSN
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 255
25119 F10.1
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble
C[1:0] = 02H
FIGURE 5-25: PAGE-PROGRAM SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39
SCK MODE 0
SI 02 ADD. ADD. ADD. Data Byte 0

MSB LSB MSB LSB MSB LSB
SO
HIGH IMPEDANCE
CE#(cont’)
2072
2073
2074
2075
2076
2077
2078
2079
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK(cont’)
SI(cont’) Data Byte 1 Data Byte 2 Data Byte 255

MSB LSB MSB LSB MSB LSB
SO(cont’)
HIGH IMPEDANCE
25119 F60.1
FIGURE 5-26: PAGE-PROGRAM SEQUENCE (SPI)

5.21 SPI Quad Page-Program mand cycle is eight clocks long, the address and data
cycles are each two clocks long, most significant bit
The SPI Quad Page-Program instruction programs up first. Poll the BUSY bit in the Status register, or wait TPP,
to 256 Bytes of data in the memory. The data for the for the completion of the internal, self-timed, Write
selected page address must be in the erased state operation.See Figure 5-27.
(FFH) before initiating the SPI Quad Page-Program
operation. A SPI Quad Page-Program applied to a pro- When executing SPI Quad Page-Program, the memory
tected memory area will be ignored. SST26VF064B range for the SST26VF064B/064BA is divided into 256
requires the ICO bit in the configuration register to be Byte page boundaries. The device handles shifting of
set to ‘1’ prior to executing the command. Prior to the more than 256 Bytes of data by maintaining the last 256
program operation, execute the WREN instruction. Bytes of data as the correct data to be programmed. If
the target address for the SPI Quad Page-Program
To execute a SPI Quad Page-Program operation, the instruction is not the beginning of the page boundary
host drives CE# low then sends the SPI Quad Page- (A[7:0] are not all zero), and the of bytes of data input
Program command cycle (32H), three address cycles exceeds or overlaps the end of the address of the page
followed by the data to be programmed, then drives boundary, the excess data inputs wrap around and will
CE# high. The programmed data must be between 1 to be programmed at the start of that target page.
256 Bytes and in whole Byte increments. The com-
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SCK MODE 0
SIO0 32H A20A16A12 A8 A4 A0 b4 b0 b4 b0 b4 b0
SIO1 A21 A17A13 A9 A5 A1 b5 b1 b5 b1 b5 b1
SIO2 A22 A18A14A10 A6 A2 b6 b2 b6 b2 b6 b2

MSN LSN
SIO3 A23 A19 A15 A11 A7 A3 b7 b3 b7 b3 b7 b3

Data Data Data
Address Byte 0 Byte 1 Byte
255
25119 F61.0
FIGURE 5-27: SPI QUAD PAGE-PROGRAM SEQUENCE
5.22 Write-Suspend and Write-Resume 5.23 Write-Suspend During Sector-

Write-Suspend allows the interruption of Sector-Erase,
Erase or Block-Erase
Block-Erase, SPI Quad Page-Program, or Page-Pro- Issuing a Write-Suspend instruction during Sector-
gram operations in order to erase, program, or read Erase or Block-Erase allows the host to program or
data in another portion of memory. The original opera- read any sector that was not being erased. The device
tion can be continued with the Write-Resume com- will ignore any programming commands pointing to the
mand. This operation is supported in both SQI and SPI suspended sector(s). Any attempt to read from the sus-
protocols. pended sector(s) will output unknown data because the
Only one write operation can be suspended at a time; Sector- or Block-Erase will be incomplete.
if an operation is already suspended, the device will To execute a Write-Suspend operation, the host drives
ignore the Write-Suspend command. Write-Suspend CE# low, sends the Write Suspend command cycle
during Chip-Erase is ignored; Chip-Erase is not a valid (B0H), then drives CE# high. The Status register indi-
command while a write is suspended. The Write- cates that the erase has been suspended by changing
Resume command is ignored until any write operation the WSE bit from ‘0’ to ‘1,’ but the device will not accept
(Program or Erase) initiated during the Write-Suspend another command until it is ready. To determine when
is complete. The device requires a minimum of 500 µs the device will accept a new command, poll the BUSY
between each Write-Suspend command. bit in the Status register or wait TWS.

5.24 Write Suspend During Page a Read Security ID operation in SQI mode, the host
Programming or SPI Quad Page drives CE# low and then sends the Read Security ID
command, two address cycles, and three dummy
Programming
cycles.
Issuing a Write-Suspend instruction during Page Pro- After the dummy cycles, the device outputs data on the
gramming allows the host to erase or read any sector falling edge of the SCK signal, starting from the speci-
that is not being programmed. Erase commands point- fied address location. The data output stream is contin-
ing to the suspended sector(s) will be ignored. Any uous through all SID addresses until terminated by a
attempt to read from the suspended page will output low-to-high transition on CE#. See Table 5-5 for the
unknown data because the program will be incomplete. Security ID address range.
To execute a Write Suspend operation, the host drives
CE# low, sends the Write Suspend command cycle 5.27 Program Security ID
(B0H), then drives CE# high. The Status register indi-
cates that the programming has been suspended by The Program Security ID instruction programs one to
changing the WSP bit from ‘0’ to ‘1,’ but the device will 2040 Bytes of data in the user-programmable, Security
not accept another command until it is ready. To deter- ID space. This Security ID space is one-time program-
mine when the device will accept a new command, poll mable (OTP). The device ignores a Program Security
the BUSY bit in the Status register or wait TWS. ID instruction pointing to an invalid or protected
address, see Table 5-5. Prior to the program operation,
execute WREN.
5.25 Write-Resume
To execute a Program SID operation, the host drives
Write-Resume restarts a Write command that was sus- CE# low, sends the Program Security ID command
pended, and changes the suspend status bit in the Sta- cycle (A5H), two address cycles, the data to be pro-
tus register (WSE or WSP) back to ‘0’. grammed, then drives CE# high. The programmed data
To execute a Write-Resume operation, the host drives must be between 1 to 256 Bytes and in whole Byte
CE# low, sends the Write Resume command cycle increments.
(30H), then drives CE# high. To determine if the inter- The device handles shifting of more than 256 Bytes of
nal, self-timed Write operation completed, poll the data by maintaining the last 256 Bytes of data as the
BUSY bit in the Status register, or wait the specified correct data to be programmed. If the target address for
time TSE, TBE or TPP for Sector-Erase, Block-Erase, or the Program Security ID instruction is not the beginning
Page-Programming, respectively. The total write time of the page boundary, and the number of data input
before suspend and after resume will not exceed the exceeds or overlaps the end of the address of the page
uninterrupted write times TSE, TBE or TPP. boundary, the excess data inputs wrap around and will
be programmed at the start of that target page.
5.26 Read Security ID The Program Security ID operation is supported in both
The Read Security ID operation is supported in both SPI and SQI mode. To determine the completion of the
SPI and SQI modes. To execute a Read Security ID internal, self-timed Program SID operation, poll the
(SID) operation in SPI mode, the host drives CE# low, BUSY bit in the software status register, or wait TPSID
sends the Read Security ID command cycle (88H), two for the completion of the internal self-timed Program
address cycles, and then one dummy cycle. To execute Security ID operation.
TABLE 5-5: PROGRAM SECURITY ID

Program Security ID Address Range
Unique ID Pre-Programmed at factory 0000 – 0007H
User Programmable 0008H – 07FFH

5.28 Lockout Security ID mands function in both SPI and SQI modes. The Status
register may be read at any time, even during a Write
The Lockout Security ID instruction prevents any future operation. When a Write is in progress, poll the BUSY
changes to the Security ID, and is supported in both bit before sending any new commands to assure that
SPI and SQI modes. Prior to the operation, execute the new commands are properly received by the
WREN. device.
To execute a Lockout SID, the host drives CE# low, To Read the Status or Configuration registers, the host
sends the Lockout Security ID command cycle (85H), drives CE# low, then sends the Read-Status-Register
then drives CE# high. Poll the BUSY bit in the software command cycle (05H) or the Read Configuration Reg-
status register, or wait TPSID, for the completion of the ister command (35H). A dummy cycle is required in
Lockout Security ID operation. SQI mode. Immediately after the command cycle, the
device outputs data on the falling edge of the SCK sig-
5.29 Read-Status Register (RDSR) and nal. The data output stream continues until terminated
Read-Configuration Register by a low-to-high transition on CE#. See Figures 5-28
(RDCR) and 5-29 for the instruction sequence.
The Read-Status Register (RDSR) and Read-Configu-

ration Register (RDCR) commands output the contents
of the Status and Configuration registers. These com-
CE#
MODE 3 0 2 4 6 8
SCK MODE 0
MSN LSN
SIO(3:0) C1 C0 X X H0 L0 H0 L0 H0 L0
Dummy Data Byte Data Byte Data Byte
25119 F11.1
Note: MSN = Most Significant Nibble; LSN = Least Significant Nibble, C[1:0]=05H or 35H
FIGURE 5-28: READ-STATUS-REGISTER AND READ-CONFIGURATION REGISTER

SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK MODE 0
SI 05 or 35
MSB
HIGH IMPEDANCE
SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB Status
Data Out
25119 F62.0
FIGURE 5-29: READ-STATUS-REGISTER AND READ-CONFIGURATION REGISTER

SEQUENCE (SPI)

5.30 Write-Status Register (WRSR) low, then sends the Write-Status Register command
cycle (01H), two cycles of data, and then drives CE#
The Write-Status Register (WRSR) command writes high. Values in the second data cycle will be accepted
new values to the Configuration register. To execute a by the device. See Figures 5-30 and 5-31.
Write-Status Register operation, the host drives CE#
CE#
MODE 3 0 1 2 3 4 5
SCK MODE 0
MSN LSN
SIO[3:0] C1 C0 XX XX H0 L0
Command Status Config-
Byte uration
Byte 25119 F63.1
Note: MSN = Most Significant Nibble; LSN = Least Significant Nibble, XX = Don’t Care, C[1:0]=01H
FIGURE 5-30: WRITE-STATUS-REGISTER SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK MODE 0
STATUS CONFIGURATION
BYTE BYTE
SI 01 XX XX XX XX XX XX XX XX 7 6 5 4 3 2 1 0
MSB MSB MSB
SO HIGH IMPEDANCE
25119 F64.1
Note: XX = Don’t Care
FIGURE 5-31: WRITE-STATUS-REGISTER SEQUENCE (SPI)

5.31 Write-Enable (WREN) Protection Register, Lock-Down Block-Protection Reg-

ister, Non-Volatile Write-Lock Lock-Down Register, SPI
The Write Enable (WREN) instruction sets the Write- Quad Page program, and Write-Status Register. To
Enable-Latch bit in the Status register to ‘1,’ allowing execute a Write Enable the host drives CE# low then
Write operations to occur. The WREN instruction must sends the Write Enable command cycle (06H) then
be executed prior to any of the following operations: drives CE# high. See Figures 5-32 and 5-33 for the
Sector Erase, Block Erase, Chip Erase, Page Program, WREN instruction sequence.
Program Security ID, Lockout Security ID, Write Block-
CE#
MODE 3 0 1
SCK MODE 0
SIO[3:0] 0 6
25119 F12.1
FIGURE 5-32: WRITE-ENABLE SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI 06
MSB
SO HIGH IMPEDANCE
25119 F18.0
FIGURE 5-33: WRITE-ENABLE SEQUENCE (SPI)

5.32 Write-Disable (WRDI) ing any internal write operations. Any Write operation
started before executing WRDI will complete. Drive
The Write-Disable (WRDI) instruction sets the Write- CE# high before executing WRDI.
Enable-Latch bit in the Status register to ‘0,’ preventing
Write operations. The WRDI instruction is ignored dur- To execute a Write-Disable, the host drives CE# low,
sends the Write Disable command cycle (04H), then
drives CE# high. See Figures 5-34 and 5-35.
CE#
MODE 3 0 1
SCK MODE 0
SIO(3:0) 0 4
25119 F33.1
FIGURE 5-34: WRITE-DISABLE (WRDI) SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SI 04
MSB
SO HIGH IMPEDANCE
25119 F19.0
FIGURE 5-35: WRITE-DISABLE (WRDI) SEQUENCE (SPI)

5.33 Read Block-Protection Register After the command cycle, the device outputs data on
(RBPR) the falling edge of the SCK signal starting with the most
significant bit(s), see Table 5-6 for definitions of each bit
The Read Block-Protection Register instruction outputs in the Block-Protection register. The RBPR command
the Block-Protection register data which determines does not wrap around. After all data has been output,
the protection status. To execute a Read Block-Protec- the device will output 0H until terminated by a low-to-
tion Register operation, the host drives CE# low, and high transition on CE#. Figures 5-36 and 5-37.
then sends the Read Block-Protection Register com-
mand cycle (72H). A dummy cycle is required in SQI
mode.
CE#
MODE 3 0 2 4 6 8 10 12
SCK
SIO[3:0] C1 C0 X X H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 HN LN
MSN LSN
BPR [m:m-7] BPR [7:0] 25119 F34.2

Block-Protection Register (BPR), m = 143 for SST26VF064B/064BA, C[1:0]=72H
FIGURE 5-36: READ BLOCK-PROTECTION REGISTER SEQUENCE (SQI)
CE#
MODE 3
0 1 2 3 4 5 6 7 8 15 16 23 24 32 33
SCK MODE 0
SIO0 72H
OP Code
SIO Data Byte 0 Data Byte 1 Data Byte 2 Data Byte N
25119 F48.0
FIGURE 5-37: READ BLOCK-PROTECTION REGISTER SEQUENCE (SPI)

5.34 Write Block-Protection Register To execute a Write Block-Protection Register operation

(WBPR) the host drives CE# low, sends the Write Block-Protec-
tion Register command cycle (42H), sends 18 cycles of
The Write Block-Protection Register (WBPR) com- data, and finally drives CE# high. Data input must be
mand changes the Block-Protection register data to most significant bit(s) first. See Table 5-6 for definitions
indicate the protection status. Execute WREN before of each bit in the Block-Protection register. See Figures
executing WBPR. 5-38 and 5-39.
CE#
MODE 3 0 2 4 6 8 10 12
SCK MODE 0
SIO(3:0) C1 C0 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 HN LN
MSN LSN
BPR [143:136] BPR [7:0]
25119 F35.1

Block-Protection Register (BPR) C[1:0]=42H
FIGURE 5-38: WRITE BLOCK-PROTECTION REGISTER SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32
SCK MODE 0
OP Code
SI 42H Data Byte0 Data Byte1 Data Byte2 Data ByteN
SO
25119 F66.1
Note: C[1:0]=42H
FIGURE 5-39: WRITE BLOCK-PROTECTION REGISTER SEQUENCE (SPI).

5.35 Lock-Down Block-Protection cycling; this allows the Block-Protection register to be

Register (LBPR) changed. Execute WREN before initiating the Lock-
Down Block-Protection Register instruction.
The Lock-Down Block-Protection Register instruction
To execute a Lock-Down Block-Protection Register, the
prevents changes to the Block-Protection register dur-
host drives CE# low, then sends the Lock-Down Block-
ing device operation. Lock-Down resets after power
Protection Register command cycle (8DH), then drives
CE# high.
CE#
MODE 3 0 1
SCK MODE 0
SIO(3:0) C1 C0
25119 F30.1
Note: C[1:0]=8DH
FIGURE 5-40: LOCK-DOWN BLOCK-PROTECTION REGISTER (SQI)
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SIO0 8D
SIO[3:1]
25119 F67.0
FIGURE 5-41: LOCK-DOWN BLOCK-PROTECTION REGISTER (SPI)

5.36 Non-Volatile Write-Lock Lock- After CE# goes high, the non-volatile bits are pro-
Down Register (nVWLDR) grammed and the programming time-out must com-
plete before any additional commands, other than
The Non-Volatile Write-Lock Lock-Down Register Read Status Register, can be entered. Poll the BUSY
(nVWLDR) instruction controls the ability to change the bit in the Status register, or wait TPP, for the completion
Write-Lock bits in the Block-Protection register. Exe- of the internal, self-timed, Write operation. Data inputs
cute WREN before initiating the nVWLDR instruction. must be most significant bit(s) first.
To execute nVWLDR, the host drives CE# low, then
sends the nVWLDR command cycle (E8H), followed by
18 cycles of data, and then drives CE# high.
CE#
MODE 3 0 2 4 6 8 10 12
SCK MODE 0
SIO(3:0) E 8 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 HN LN
MSN LSN
BPR [m:m-7] BPR [7:0]
25119 F36.0
Note: MSN= Most Significant Nibble; LSN = Least Significant Nibble
Write-Lock Lock-Down Register (nVWLDR) m = 143
FIGURE 5-42: WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SQI)
CE#
MODE 3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32
SCK MODE 0
OP Code
SI E8H Data Byte0 Data Byte1 Data Byte2 Data ByteN
SO
25119 F69.1
FIGURE 5-43: WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SPI)

5.37 Global Block-Protection Unlock To execute a ULBPR instruction, the host drives CE#
(ULBPR) low, then sends the ULBPR command cycle (98H), and
then drives CE# high.
The Global Block-Protection Unlock (ULBPR) instruc-
tion clears all write-protection bits in the Block-Protec-
tion register, except for those bits that have been
locked down with the nVWLDR command. Execute
WREN before initiating the ULBPR instruction.
CE#
MODE 3 0 1
SCK MODE 0
SIO(3:0) C1 C0
25119 F20.1
Note: C[1:0]=98H
FIGURE 5-44: GLOBAL BLOCK-PROTECTION UNLOCK (SQI)
CE#
MODE 3 0 1 2 3 4 5 6 7
SCK MODE 0
SIO0 98
SIO[3:1]
25119 F68.0
FIGURE 5-45: GLOBAL BLOCK-PROTECTION UNLOCK (SPI)

TABLE 5-6: BLOCK-PROTECTION REGISTER FOR SST26VF064B/064BA (1 OF 4)1

BPR Bits
Write Lock/ Protected Block
Read Lock nVWLDR2 Address Range Size
143 142 7FE000H - 7FFFFFH 8 KByte
141 140 7FC000H - 7FDFFFH 8 KByte
139 138 7FA000H - 7FBFFFH 8 KByte
137 136 7F8000H - 7F9FFFH 8 KByte
135 134 006000H - 007FFFH 8 KByte
133 132 004000H - 005FFFH 8 KByte
131 130 002000H - 003FFFH 8 KByte
129 128 000000H - 001FFFH 8 KByte
127 7F0000H - 7F7FFFH 32 KByte
126 008000H - 00FFFFH 32 KByte
125 7E0000H - 7EFFFFH 64 KByte
124 7D0000H - 7DFFFFH 64 KByte
123 7C0000H - 7CFFFFH 64 KByte
122 7B0000H - 7BFFFFH 64 KByte
121 7A0000H - 7AFFFFH 64 KByte
120 790000H - 79FFFFH 64 KByte
119 780000H - 78FFFFH 64 KByte
118 770000H - 77FFFFH 64 KByte
117 760000H - 76FFFFH 64 KByte
116 750000H - 75FFFFH 64 KByte
115 740000H - 74FFFFH 64 KByte
114 730000H - 73FFFFH 64 KByte
113 720000H - 72FFFFH 64 KByte
112 710000H - 71FFFFH 64 KByte
111 700000H - 70FFFFH 64 KByte
110 6F0000H - 6FFFFFH 64 KByte
104 690000H - 69FFFFH 64 KByte
103 680000H - 68FFFFH 64 KByte
102 670000H - 67FFFFH 64 KByte
101 660000H - 66FFFFH 64 KByte
100 650000H - 65FFFFH 64 KByte
99 640000H - 64FFFFH 64 KByte
98 630000H - 63FFFFH 64 KByte
97 620000H - 62FFFFH 64 KByte
96 610000H - 61FFFFH 64 KByte
95 600000H - 60FFFFH 64 KByte

TABLE 5-6: BLOCK-PROTECTION REGISTER FOR SST26VF064B/064BA (CONTINUED) (2 OF

BPR Bits
88 590000H - 59FFFFH 64 KByte
87 580000H - 58FFFFH 64 KByte
86 570000H - 57FFFFH 64 KByte
85 560000H - 56FFFFH 64 KByte
84 550000H - 55FFFFH 64 KByte
83 540000H - 54FFFFH 64 KByte
82 530000H - 53FFFFH 64 KByte
81 520000H - 52FFFFH 64 KByte
80 510000H - 51FFFFH 64 KByte
79 500000H - 50FFFFH 64 KByte
72 490000H - 49FFFFH 64 KByte
71 480000H - 48FFFFH 64 KByte
70 470000H - 47FFFFH 64 KByte
69 460000H - 46FFFFH 64 KByte
68 450000H - 45FFFFH 64 KByte
67 440000H - 44FFFFH 64 KByte
66 430000H - 43FFFFH 64 KByte
65 420000H - 42FFFFH 64 KByte
64 410000H - 41FFFFH 64 KByte
63 400000H - 40FFFFH 64 KByte
56 390000H - 39FFFFH 64 KByte
55 380000H - 38FFFFH 64 KByte
54 370000H - 37FFFFH 64 KByte
53 360000H - 36FFFFH 64 KByte
52 350000H - 35FFFFH 64 KByte
51 340000H - 34FFFFH 64 KByte
50 330000H - 33FFFFH 64 KByte


BPR Bits
49 320000H - 32FFFFH 64 KByte
48 310000H - 31FFFFH 64 KByte
47 300000H - 30FFFFH 64 KByte
40 290000H - 29FFFFH 64 KByte
39 280000H - 28FFFFH 64 KByte
38 270000H - 27FFFFH 64 KByte
37 260000H - 26FFFFH 64 KByte
36 250000H - 25FFFFH 64 KByte
35 240000H - 24FFFFH 64 KByte
34 230000H - 23FFFFH 64 KByte
33 220000H - 22FFFFH 64 KByte
32 210000H - 21FFFFH 64 KByte
31 200000H - 20FFFFH 64 KByte
24 190000H - 19FFFFH 64 KByte
23 180000H - 18FFFFH 64 KByte
22 170000H - 17FFFFH 64 KByte
21 160000H - 16FFFFH 64 KByte
20 150000H - 15FFFFH 64 KByte
19 140000H - 14FFFFH 64 KByte
18 130000H - 13FFFFH 64 KByte
17 120000H - 12FFFFH 64 KByte
16 110000H - 11FFFFH 64 KByte
15 100000H - 10FFFFH 64 KByte
8 090000H - 09FFFFH 64 KByte
7 080000H - 08FFFFH 64 KByte


BPR Bits
6 070000H - 07FFFFH 64 KByte
5 060000H - 06FFFFH 64 KByte
4 050000H - 05FFFFH 64 KByte
3 040000H - 04FFFFH 64 KByte
2 030000H - 03FFFFH 64 KByte
1 020000H - 02FFFFH 64 KByte
0 010000H - 01FFFFH 64 KByte
1. The default state after a power-on reset is write-protected BPR[143:0] = 5555 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF
2. nVWLDR bits are one-time-programmable. Once a nVWLDR bit is set, the protection state of that particular block is perma-
nently write-locked.

6.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maxi-
mum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these conditions or conditions greater than those defined in the operational
sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may
affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
TABLE 6-1: OPERATING RANGE TABLE 6-2: AC CONDITIONS OF TEST1

Range Ambient Temp VDD Input Rise/Fall Time Output Load
Industrial -40°C to +85°C 2.7-3.6V 3ns CL = 30 pF
1. See Figure 8-5

6.1 Power-Up Specifications When VDD drops from the operating voltage to below
the minimum VDD threshold at power-down, all opera-
All functionalities and DC specifications are specified tions are disabled and the device does not respond to
for a VDD ramp rate of greater than 1V per 100 ms (0V commands. Data corruption may result if a power-down
to 3.0V in less than 300 ms). See Table 6-3 and Figure occurs while a Write-Registers, program, or erase
6-1 for more information. operation is in progress. See Figure 6-2.
TABLE 6-3: RECOMMENDED SYSTEM POWER-UP/DOWN TIMINGS

Symbol Parameter Minimum Max Units Condition
TPU-READ1 VDD Min to Read Operation 100 µs
TPU-WRITE1 VDD Min to Write Operation 100 µs
TPD 1 Power-down Duration 100 ms
VOFF VDD off time 0.3 V 0V recommended
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
VDD
VDD Max
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
VDD Min
TPU-READ
TPU-WRITE Device fully accessible
Time
25119 F27.0
FIGURE 6-1: POWER-UP TIMING DIAGRAM

VDD
VDD Max
No Device Access Allowed
VDD Min
TPU Device
Access
Allowed
VOFF
TPD
Time
25119 F72.0
FIGURE 6-2: POWER-DOWN AND VOLTAGE DROP DIAGRAM

7.0 DC CHARACTERISTICS
TABLE 7-1: DC OPERATING CHARACTERISTICS (VDD = 2.7 - 3.6V)

Limits
Symbol Parameter Min Typ Max Units Test Conditions
IDDR1 Read Current 8 15 mA VDD=VDD Max,
CE#=0.1 VDD/0.9 VDD@40 MHz,
SO=open
IDDR2 Read Current 20 mA VDD = VDD Max,
CE#=0.1 VDD/0.9 VDD@104 MHz,
SO=open
IDDW Program and Erase Cur- 25 mA VDD Max
rent
ISB Standby Current 15 45 µA CE#=VDD, VIN=VDD or VSS
ILI Input Leakage Current 2 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 2 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VIH Input High Voltage 0.7 VDD V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
TABLE 7-2: CAPACITANCE (TA = 25°C, F=1 MHZ, OTHER PINS OPEN)
Parameter Description Test Condition Maximum
COUT1 Output Pin Capacitance VOUT = 0V 8 pF
CIN1 Input Capacitance VIN = 0V 6 pF
TABLE 7-3: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method
NEND1 Endurance 100,000 Cycles JEDEC Standard A117
TDR1 Data Retention 100 Years JEDEC Standard A103
ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78
TABLE 7-4: WRITE TIMING PARAMETERS (VDD = 2.7 - 3.6V)

Symbol Parameter Minimum Maximum Units
TSE Sector-Erase 25 ms
TBE Block-Erase 25 ms
TSCE Chip-Erase 50 ms
TPP Page-Program 1.5 ms
TPSID Program Security-ID 1.5 ms
TWS Write-Suspend Latency 25 µs
TWpen Write-Protection Enable Bit Latency 25 ms

8.0 AC CHARACTERISTICS
TABLE 8-1: AC OPERATING CHARACTERISTICS (VDD = 2.7 - 3.6V)

Limits - 40 MHz Limits - 80 MHz Limits - 104 MHz
Symbol Parameter Min Max Min Max Min Max Units
FCLK Serial Clock Frequency 40 80 104 MHz
TCLK Serial Clock Period 25 12.5 9.6 ns
TSCKH Serial Clock High Time 11 5.5 4.5 ns
TSCKL Serial Clock Low Time 11 5.5 4.5 ns
TSCKR1 Serial Clock Rise Time (slew rate) 0.1 0.1 0.1 V/ns
TSCKF1 Serial Clock Fall Time (slew rate) 0.1 0.1 0.1 V/ns
TCES2 CE# Active Setup Time 8 5 5 ns
TCEH2 CE# Active Hold Time 8 5 5 ns
TCHS2 CE# Not Active Setup Time 8 5 5 ns
TCHH2 CE# Not Active Hold Time 8 5 5 ns
TCPH CE# High Time 25 12.5 12 ns
TCHZ CE# High to High-Z Output 19 12.5 12 ns
TCLZ SCK Low to Low-Z Output 0 0 0 ns
THLS HOLD# Low Setup Time 8 5 5 ns
THHS HOLD# High Setup Time 8 5 5 ns
THLH HOLD# Low Hold Time 8 5 5 ns
THHH HOLD# High Hold Time 8 5 5 ns
THZ HOLD# Low-to-High-Z Output 8 8 8 ns
TLZ HOLD# High-to-Low-Z Output 8 8 8 ns
TDS Data In Setup Time 3 3 3 ns
TDH Data In Hold Time 4 4 4 ns
TOH Output Hold from SCK Change 0 0 0 ns
TV Output Valid from SCK 8/5 3 8/5 3 8/5 3 ns
1. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements
2. Relative to SCK.
3. 30 pF/10 pF
CE#
THHH THLS THHS
SCK
THLH
THZ TLZ
SO
SI
HOLD#
25119 F43.1
FIGURE 8-1: HOLD TIMING DIAGRAM

TCPH
CE#
TCHH TCES TCEH TCHS

TSCKF
SCK
TDS TDH
TSCKR
SIO[3:0] MSB LSB
25119 F70.1
FIGURE 8-2: SERIAL INPUT TIMING DIAGRAM
CE#
TSCKH TSCKL
SCK
TOH
TCLZ TCHZ
SIO[3:0] MSB LSB

TV
25119 F25.1
FIGURE 8-3: SERIAL OUTPUT TIMING DIAGRAM
TABLE 8-2: RESET TIMING PARAMETERS

TR(i) Parameter Minimum Maximum Units
TR(o) Reset to Read (non-data operation) 20 ns
TR(p) Reset Recovery from Program or Suspend 100 µs
TR(e) Reset Recovery from Erase 1 ms
TCPH
CE#
CLK
SIO(3:0) C1 C0 C3 C2
25119 F14.0
Note: C[1:0] = 66H; C[3:2] = 99H
FIGURE 8-4: RESET TIMING DIAGRAM

VIHT
VHT VHT
INPUT REFERENCE POINTS OUTPUT
VLT VLT
VILT
25119 F28.0
AC test inputs are driven at VIHT (0.9VDD) for a logic ‘1’ and VILT (0.1VDD) for a logic ‘0’. Measure-
ment reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and
fall times (10% ↔ 90%) are <3 ns.
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 8-5: AC INPUT/OUTPUT REFERENCE WAVEFORMS

9.0 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X XXX XX XX Valid Combinations:
Tape/Reel Operating Endurance/ SST26VF064B-104-5I-MF

Device Package
Indicator Frequency Temperature SST26VF064BT-104-5I-MF
SST26VF064BA-104-5I-MF
SST26VF064BAT-104-5I-MF
SST26VF064B-104-5I-SM
Device: SST26VF064B = 64 Mbit, 2.7-3.6V, SQI Flash Memory
SST26VF064BT-104-5I-SM
WP#/Hold# pin Enable at power-up
SST26VF064BA-104-5I-SM
SST26VF064BA = 64 Mbit, 2.7-3.6V, SQI Flash Memory
SST26VF064BAT-104-5I-SM
WP#/Hold# pin Disable at power-up
SST26VF064B-104-5I-SO
SST26VF064BT-104-5I-SO
Tape and T = Tape and Reel SST26VF064BA-104-5I-SO
Reel Flag: SST26VF064BAT-104-5I-SO
SST26VF064B-104-5I-TD
SST26VF064BT-104-5I-TD
Operating 104 = 104 MHz SST26VF064BA-104-5I-TD
Frequency: SST26VF064BAT-104-5I-TD
Endurance: 5 = 100,000 cycles
Temperature: I = -40°C to +85°C
Package: MF = WSON (6mm x 5mm Body), 8-lead

SM = SOIC (200 mil Body), 8-lead
SO = SOIC (300 mil Body), 16-lead
TD = TBGA(>1mm pitch, <1.2mmheight),
24-lead
TABLE 9-1: PART MARKING

Ordering Number Marking On Part
SST26VF064B-104-5I-MF 26VF064B-I/MF
SST26VF064BA-104-5I-MF 26VF064B-I/MF
SST26VF064B-104-5I-SM 26VF064B-I/SM
SST26VF064BA-104-5I-SM 26VF064B-I/SM
SST26VF064B-104-5I-SO 26VF064B-I/SO
SST26VF064BA-104-5I-SO 26VF064B-I/SO
SST26VF064B-104-5I-TD 26VF064B-I/TD
SST26VF064BA-104-5I-TD 26VF064B-I/TD

10.0 PACKAGING DIAGRAMS


Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging






11.0 APPENDIX
TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (1 OF 11)

Address Bit Address Data Comments
SFDP Header
SFDP Header: 1st DWORD
00H A7:A0 53H SFDP Signature
01H A15:A8 46H SFDP Signature=50444653H
02H A23:A16 44H
03H A31:A24 50H
SFDP Header: 2nd DWORD
04H A7:A0 00H SFDP Minor Revision Number
05H A15:A8 01H SFDP Major Revision Number
06H A23:A16 02H Number of Parameter Headers (NPH)
07H A31:A24 FFH Unused. Contains FF and can not be changed.
Parameter Headers
JEDEC Flash Parameter Header: 1st DWORD
ID Number.
When this field is set to 00H, it indicates a JEDEC-specified header. For
08H A7:A0 00H
vendor-specified headers, this field must be set to the vendor’s manufac-
turer ID.
Parameter Table Minor Revision Number
Minor revisions are either clarifications or changes that add parameters
09H A15:A8 00H
in existing Reserved locations. Minor revisions do NOT change overall
structure of SFDP. Minor Revision starts at 00H.
Parameter Table Major Revision Number
Major revisions are changes that reorganize or add parameters to loca-
0AH A23:A16 01H tions that are NOT currently Reserved. Major revisions would require
code (BIOS/firmware) or hardware change to get previously defined dis-
coverable parameters. Major Revision starts at 01H
Parameter Table Length
0BH A31:A24 09H
Number of DWORDs that are in the Parameter table
JEDEC Flash Parameter Header: 2nd DWORD
0CH A7:A0 30H Parameter Table Pointer (PTP)
A 24-bit address that specifies the start of this header’s Parameter table
0DH A15:A8 00H
in the SFDP structure. The address must be DWORD-aligned.
0EH A23:A16 00H
0FH A31:A24 FFH Unused. Contains FF and can not be changed.
JEDEC Flash Parameter Header: 3rd DWORD
ID Number.
When this field is set to 00H, it indicates a JEDEC-specified header. For
10H A7:A0 00H
vendor-specified headers, this field must be set to the vendor’s manufac-
turer ID.
Parameter Table Minor Revision Number
Minor revisions are either clarifications or changes that add parameters
11H A15:A8 FFH
in existing Reserved locations. Minor revisions do NOT change overall
structure of SFDP. Minor Revision starts at 00H.

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (2 OF 11)

Parameter Table Major Revision Number
Major revisions are changes that reorganize or add parameters to loca-
12H A23:A16 FFH tions that are NOT currently Reserved. Major revisions would require
code (BIOS/firmware) or hardware change to get previously defined dis-
coverable parameters. Major Revision starts at 01H
Parameter Table Length
13H A31:A24 00H
Number of DWORDs that are in the Parameter table
JEDEC Flash Parameter Header: 4th DWORD
14H A7:A0 FFH Parameter Table Pointer (PTP)
This 24-bit address specifies the start of this header’s Parameter Table in
15H A15:A8 FFH
the SFDP structure. The address must be DWORD-aligned.
16H A23:A16 FFH
17H A31:A24 FFH Unused. Contains FF can not be changed.
Microchip (Vendor) Parameter Header: 5th DWORD
ID Number
18H A7:A0 BFH
Manufacture ID (vendor specified header)
19H A15:A8 00H Parameter Table Minor Revision Number
1AH A23:A16 01H Parameter Table major Revision Number, Revision 1.0
1BH A31:A24 18H Parameter Table Length, 24 Double Words
Microchip (Vendor) Parameter Header: 6th DWORD
1CH A7:A0 00H Parameter Table Pointer (PTP)
1DH A15:A8 02H This 24-bit address specifies the start of this header’s Parameter Table in
the SFDP structure. The address must be DWORD-aligned.
1EH A23:A16 00H
1FH A31:A24 FFH Unused. Contains FF can not be changed.
JEDEC Flash Parameter Table
JEDEC Flash Parameter Table: 1st DWORD
Block/Sector Erase Sizes
00: Reserved
A1:A0 01: 4 KByte Erase
10: Reserved
11: Use this setting only if the 4 Kilobyte erase is unavailable.
Write Granularity
0: Single-byte programmable devices or buffer programmable devices
A2 with buffer is less than 64 bytes (32 Words).
1: For buffer programmable devices when the buffer size is 64
bytes (32 Words) or larger.
30H FDH
Write Enable Instruction Required for Writing to Volatile Status Reg-
ister
0: Target flash has nonvolatile status bit. Write/Erase commands do
A3
not require status register to be written on every power on.
1: Target flash requires 0x00 to be written to the status register in
order to allow write and Erase
Write Enable Opcode Select for Writing to Volatile Status Register
A4 0: 0x50. Enables a status register write when bit 3 is set to 1.
1: 0x06 Enables a status register write when bit 3 is set to 1.
A7:A5 Unused. Contains 111b and can not be changed


31H A15:A8 20H 4 KByte Erase Opcode
Supports (1-1-2) Fast Read
A16 0: (1-1-2) Fast Read NOT supported
1: (1-1-2) Fast Read supported
Address Bytes
Number of bytes used in addressing flash array read, write and erase
00: 3-Byte only addressing
A18:A17 01: 3- or 4-Byte addressing (e.g. defaults to 3-Byte mode; enters 4-Byte
mode on command)
10: 4-Byte only addressing
11: Reserved
Supports Double Transfer Rate (DTR) Clocking
Indicates the device supports some type of double transfer rate clocking.
A19
0: DTR NOT supported
1: DTR Clocking supported
32H F1H Supports (1-2-2) Fast Read

Device supports single input opcode, dual input address, and dual output
A20 data Fast Read.
0: (1-2-2) Fast Read NOT supported.
1: (1-2-2) Fast Read supported.
Device supports single input opcode, quad input address, and quad out-
A21 put data Fast Read
Device supports single input opcode & address and quad output data
A22 Fast Read.
A23 Unused. Contains ‘1’ can not be changed.
33H A31:A24 FFH Unused. Contains FF can not be changed
JEDEC Flash Parameter Table: 2nd DWORD
34H A7:A0 FFH Flash Memory Density
35H A15:A8 FFH SST26VF064B/064BA = 03FFFFFFH
36H A23:A16 FFH
37H A31:A24 03H
JEDEC Flash Parameter Table: 3rd DWORD
(1-4-4) Fast Read Number of Wait states (dummy clocks) needed
before valid output
A4:A0
00100b: 4 dummy clocks (16 dummy bits) are needed with a quad input
address phase instruction
38H 44H
Quad Input Address Quad Output (1-4-4) Fast Read Number of Mode
Bits
A7:A5
010b: 2 dummy clocks (8 mode bits) are needed with a single input
opcode, quad input address and quad output data Fast Read Instruction.
(1-4-4) Fast Read Opcode
39H A15:A8 EBH Opcode for single input opcode, quad input address, and quad output
data Fast Read.


before valid output
A20:A16
01000b: 8 dummy bits are needed with a single input opcode & address
3AH 08H and quad output data Fast Read Instruction
(1-1-4) Fast Read Number of Mode Bits
A23:A21 000b: No mode bits are needed with a single input opcode & address and
quad output data Fast Read Instruction
3BH A31:A24 6BH Opcode for single input opcode & address and quad output data Fast
Read.
JEDEC Flash Parameter Table: 4th DWORD
before valid output
A4:A0
01000b: 8 dummy clocks are needed with a single input opcode, address
3CH 08H and dual output data fast read instruction.
A7:A5 000b: No mode bits are needed with a single input opcode & address and
quad output data Fast Read Instruction
3DH A15:A8 3BH
Opcode for single input opcode& address and dual output data Fast Read.
A20:A16 before valid output
3EH 42H 00010b: 2 clocks of dummy cycle.
(1-2-2) Fast Read Number of Mode Bits (in clocks)
A23:A21
010b: 2 clocks of mode bits are needed
3FH A31:A24 BBH Opcode for single input opcode, dual input address, and dual output data
Fast Read.
Device supports dual input opcode& address and dual output data Fast
A0 Read.
A3:A1 Reserved. Bits default to all 1’s.
40H FEH
Device supports Quad input opcode & address and quad output data
A4 Fast Read.
41H A15:A8 FFH Reserved. Bits default to all 1’s.


th
JEDEC Flash Parameter Table: 6 DWORD
46H 00H 00000b: No dummy bit is needed
A23:A21
000b: No mode bits are needed
47H A31:A24 FFH Opcode for dual input opcode& address and dual output data Fast Read.
(not supported)
before valid output
A20:A16
00100b: 4 clocks dummy are needed with a quad input opcode &
4AH 44H address and quad output data Fast Read Instruction
A23:A21 010b: 2 clocks mode bits are needed with a quad input opcode & address
and quad output data Fast Read Instruction
4BH A31:A24 0BH
Opcode for quad input opcode/address, quad output data Fast Read
Sector Type 1 Size
4CH A7:A0 0DH
8 KByte, Sector/block size = 2N bytes
Sector Type 1 Opcode
4DH A15:A8 D8H Opcode used to erase the number of bytes specified by Sector Type 1
Size (bits 7-0).
Sector Type 2 Size
4EH A23:A16 0FH
4FH A31:A24 D8H Opcode used to erase the number of bytes specified by Sector Type 2
Size (bits23-16).
Sector Type 3 Size
50H A7:A0 10H
51H A15:A8 D8H Opcode used to erase the number of bytes specified by Sector Type 3
Size (bits7-0).
Sector Type 4 Size
52H A23:A16 00H
0x00: this sector type does not exist
Opcode used to erase the number of bytes specified by Sector Type 4
53H A31:A24 00H
Size (bits23-16)
0x00: this sector type does not exist


SST26VF064B/064BA (Vendor) Parameter Table
SST26VF064B/064BA Identification
200H A7:A0 BFH Manufacturer ID
201H A15:A8 26H Memory Type
202H A23:A16 43H Device ID
SST26VF064B/064BA=43H
SST26VF064B/064BA Interface
Interfaces Supported
000: SPI only
001: Power up default is SPI; Quad can be enabled/disabled
A2:A0
010: Reserved
: :
111: Reserved
Supports Enable Quad
A3 0: not supported
204H B9H 1: supported
Supports Hold#/Reset# Function
000: Hold#
A6:A4 001: Reset#
010: HOLD/Reset#
011: Hold# & I/O when in SQI(4-4-4), 1-4-4 or 1-1-4 Read
Supports Software Reset
A7 0: not supported
1: supported
Supports Quad Reset
A8 0: not supported
1: supported
A10:A9 Reserved. Bits default to all 1’s
Byte-Program or Page-Program (256 Bytes)
A13:A11 011: Byte Program/Page Program in SPI and Quad Page Program once
205H 5FH Quad is enabled
Program-Erase Suspend Supported
A14 0: Not Supported
1: Program/Erase Suspend Supported
Deep Power-Down Mode Supported
A15 0: Not Supported
1: Deep Power-Down Mode Supported


OTP Capable (Security ID) Supported
A16 0: not supported
1: supported
Supports Block Group Protect
1: supported
Supports Independent Block Protect
206H FDH
1: supported
Supports Independent non Volatile Lock (Block or Sector becomes
OTP)
A19
0: not supported
1: supported
208H A7:A0 70H VDD Minimum Supply Voltage
209H A15:A8 F2H 2.7V (F270H)
20AH A23:A16 60H VDD Maximum Supply Voltage
20BH A31:A24 F3H 3.6V (F360H)
Typical time out for Byte-Program: 50 µs
20CH A7:A0 32H Typical time out for Byte Program is in µs. Represented by conversion of
the actual time from the decimal to hexadecimal number.
20DH A15:A8 FFH Reserved. Bits default to all 1’s.
20EH A23:A16 0AH Typ time out for page program: 1.0ms (xxH*(0.1ms)
Typical time out for Sector-Erase/Block-Erase: 18 ms
20FH A31:A24 12H Typical time out for Sector/Block-Erase is in ms. Represented by conversion
of the actual time from the decimal to hexadecimal number.
Typical time out for Chip-Erase: 35 ms
210H A7:A0 23H Typical time out for Chip-Erase is in ms. Represented by conversion of
Max. time out for Byte-Program: 70 µs
211H A15:A8 46H Typical time out for Byte Program is in µs. Represented by conversion of
Max time out for Page-Program: 1.5ms.
213H A31:A24 0FH
Typical time out for Page Program in xxH * (0.1ms) ms
Max. time out for Sector Erase/Block Erase: 25ms.
214H A7:A0 19H
Max time out for Sector/Block Erase in ms
Max. time out for Chip Erase: 50ms.
215H A15:A8 32H
Max time out for Chip Erase in ms.
Max. time out for Program Security ID: 1.5 ms
216H A23:A16 0FH
Max time out for Program Security ID in xxH*(0.1ms) ms
Max. time out for Write-Protection Enable Latency: 25 ms
217H A31:A24 19H Max time out for Write-Protection Enable Latency is in ms. Represented by con-
version of the actual time from the decimal to hexadecimal number.
Max. time Write-Suspend Latency: 25 µs
218H A23:A16 19H Max time out for Write-Suspend Latency is in µs. Represented by conversion of
Max. time to Deep Power-Down
219H A31:A24 FFH
0FFH = Reserved


Max. time out from Deep Power-Down mode to Standby mode
21AH A23:A16 FFH
0FFH = Reserved
21BH A31:A24 FFH Reserved. Bits default to all 1’s.
21CH A23:A16 FFH Reserved. Bits default to all 1’s.
21DH A31:A24 FFH Reserved. Bits default to all 1’s.
21EH A23:A16 FFH Reserved. Bits default to all 1’s.
21FH A31:A24 FFH Reserved. Bits default to all 1’s.
Supported Instructions
220H A7:A0 00H No Operation
221H A15:A8 66H Reset Enable
222H A23:A16 99H Reset Memory
223H A31:A24 38H Enable Quad I/O
224H A7:A0 FFH Reset Quad I/O
225H A15:A8 05H Read Status Register
226H A23:A16 01H Write Status Register
227H A31:A24 35H Read Configuration Register
228H A7:A0 06H Write Enable
229H A15:A8 04H Write Disable
22AH A23:A16 02H Byte Program or Page Program
22BH A31:A24 32H SPI Quad Page Program
22CH A7:A0 B0H Suspends Program/Erase
22DH A15:A8 30H Resumes Program/Erase
22EH A23:A16 72H Read Block-Protection register
22FH A31:A24 42H Write Block Protection Register
230H A7:A0 8DH Lock Down Block Protection Register
231H A15:A8 E8H non-Volatile Write-Lock Down Register
232H A23:A16 98H Global Block Protection Unlock
233H A31:A24 88H Read Security ID
234H A7:A0 A5H Program User Security ID Area
235H A15:A8 85H Lockout Security ID Programming
236H A23:A16 C0H Set Burst Length
237H A31:A24 9FH JEDEC-ID
238H A7:A0 AFH Quad J-ID
239H A15:A8 5AH SFDP
Deep Power-Down Mode
23AH A23:A16 FFH
FFH = Reserved
Release Deep Power-Down Mode
23BH A31:A24 FFH
FFH = Reserved
(1-4-4) SPI nB Burst with Wrap Number of Wait states (dummy
A4:A0 clocks) needed before valid output
23CH 06H 00110b: 6 clocks of dummy cycle
(1-4-4) SPI nB Burst with Wrap Number of Mode Bits
A7:A5
000b: Set Mode bits are not supported
23DH A15:A8 ECH (1-4-4) SPI nB Burst with Wrap Opcode


(4-4-4) SQI nB Burst with Wrap Number of Wait states (dummy
A20:A16 clocks) needed before valid output
23EH 06H 00110b: 6 clocks of dummy cycle
(4-4-4) SQI nB Burst with Wrap Number of Mode Bits
A23:A21
000b: Set Mode bits are not supported
23FH A31:A24 0CH (4-4-4) SQI nB Burst with Wrap Opcode
(1-1-1) Read Memory Number of Wait states (dummy clocks) needed
240H 00H 00000b: Wait states/dummy clocks are not supported.
(1-1-1) Read Memory Number of Mode Bits
A7:A5
000b: Mode bits are not supported,
241H A15:A8 03H (1-1-1) Read Memory Opcode
(1-1-1) Read Memory at Higher Speed Number of Wait states
A20:A16 (dummy clocks) needed before valid output
242H 08H 01000: 8 clocks (8 bits) of dummy cycle
(1-1-1) Read Memory at Higher Speed Number of Mode Bits
A23:A21
000b: Mode bits are not supported,
243H A31:A24 0BH (1-1-1) Read Memory at Higher Speed Opcode
Security ID
248H A7:A0 FFH Security ID size in bytes
Example: If the size is 2 KBytes, this field would be 07FFH
Security ID Range
249H A15:A8 07H Unique ID
0000H - 0007H
(Pre-programmed at factory)
User Programmable 0008H - 07FFH
24AH A23:A16 FFH Reserved. Bits default to all 1’s.

24BH A31:A24 FFH Reserved. Bits default to all 1’s.
Memory Organization/Block Protection Bit Mapping 1
Section 1: Sector Type Number:
24CH A7:A0 01H
Sector type in JEDEC Parameter Table (bottom, 8 KByte)
Section 1 Number of Sectors
24DH A15:A8 02H
Four of 8KB block (2n)
Section 1 Block Protection Bit Start
((2m) +1)+ c, c=FFH or -1, m= 7 for 64 Mb
Address bits are Read Lock bit locations and Even Address bits are Write
24EH A23:A16 FFH Lock bit locations. The most significant (left-most) bit indicates the sign of
the integer; it is sometimes called the sign bit. If the sign bit is zero, then
the number is greater than or equal to zero, or positive. If the sign bit is
one then the number is less than zero or negative.

Section 1 (bottom) Block Protection Bit End
((2m) +1)+ c, c=06H or 6, m= 7 for 64 Mb
24FH A31:A24 06H Lock bit locations. The most significant (left-most) bit indicates the sign of
Section 2: Sector Type Number
250H A7:A0 02H
Sector type in JEDEC Parameter Table (32KB Block)
251H A15:A8 00H
One of 32KB Block (2^n, n=0)
((2m) +1)+ c, c=FDH or -3, m= 7 for 64 Mb
The most significant (left-most) bit indicates the sign of the integer; it is
252H A23:A16 FDH
sometimes called the sign bit. If the sign bit is zero, then the number is
greater than or equal to zero, or positive. If the sign bit is one then the
number is less than zero or negative.
Section 2 Block Protection Bit End
((2m) +1)+ c, c=FDH or -3, m= 7 for 64 Mb
253H A31:A24 FDH
254H A7:A0 03H
255H A15:A8 07H
126 of 64KB Block (2m-2, m= 7 for 64 Mb)
256H A23:A16 00H
Section 3 Block Protection Bit starts at 00H
257H A31:A24 FCH
((2m) +1)+ c, c=FCH or -4, m= 7 for 64 Mb
258H A7:A0 02H
259H A15:A8 00H
One of 32KB Block (2^n, n=0)
((2m) +1)+ c, c=FEH or -2, m= 7 for 64 Mb
25AH A23:A16 FEH
((2m) +1)+ c, c=FEH or -2, m= 7 for 64 Mb
25BH A31:A24 FEH
Section 5 Sector Type Number:
25CH A7:A0 01H
Sector type in JEDEC Parameter Table (top, 8 KByte)
25DH A15:A8 02H
Four of 8KB block (2^n)

((2m) +1)+ c, c=07H or 7, m= 7 for 64 Mb
25EH A23:A16 07H Lock bit locations. The most significant (left-most) bit indicates the sign of
Section 5 (bottom) Block Protection Bit End
(((2m) +1)+ c, c=0EH or 14, m= 7 for 64 Mb,
25FH A31:A24 0EH Lock bit locations. The most significant (left-most) bit indicates the sign of
1. See “Mapping Guidance Details” for more detailed mapping information

11.1 Mapping Guidance Details number of these uniform and different sectors/blocks
from address 000000H to the full range of Memory and
The SFDP Memory Organization/Block Protection Bit the associated Block Locking Register bits of each sec-
Mapping defines the memory organization including tor/block.
uniform sector/block sizes and different contiguous
sectors/blocks sizes. In addition, this bit defines the Each major Section is defined as follows:
TABLE 11-2: SECTION DEFINITION

Major Section X Section X: Sector Type Number
Section X: Number of Sectors
Section X: Block-Protection Register Bit Start Location
Section X: Block-Protection Register Bit End Location
A Major Section consists of Sector Type Number, Num- 11.1.3 BLOCK-PROTECTION REGISTER
ber of Sector of this type, and the Block-Protection Bit BIT START LOCATION (BPSL)
Start/End locations. This is tied directly to JEDEC Flash
Block-Protection Register Bit Start Location (BPSL)
Parameter Table Sector Size Type (in 7th DWORD and
designates the start bit location in the Block-Protection
8th DWORD section). Note that the contiguous 4KByte
Register where the first sector/block of this Major Sec-
Sectors across the full memory range are not included
tion begins. If the value of BPSL is 00H, this location is
on this section because they are not defined in the
the 0 bit location. If the value is other than 0, then this
JEDEC Flash Parameter Table Sector Size Type sec-
value is a constant value adder (c) for a given formula,
tion. Only the sectors/blocks that are dependently tied
(2m + 1) + (c). See “Memory Configuration”.
with the Block-Protection Register bits are defined. A
major section is a partition of contiguous same-size From the initial location, there will be a bit location for
sectors/blocks. There will be several Major Sections as every increment by 1 until it reaches the Block Protec-
you dissect across memory from 000000h to the full tion Register Bit End Location (BPEL). This number
range. Similar sector/block size that re-appear may be range from BPSL to BPEL will correspond to, and be
defined as a different Major Section. equal to, the number of sectors/blocks on this Major
Section.
11.1.1 SECTOR TYPE NUMBER
11.1.4 BLOCK PROTECTION REGISTER
Sector Type Number is the sector/block size typed
defined in JEDEC Flash Parameter Table: SFDP BIT END LOCATION (BPEL)
address locations 4CH, 4EH, and 50H. For SFDP Block Protection Register Bit End Location designates
address location 4CH, which is Sector Type 1, the size the end bit location in the Block Protection Register bit
is represented by 01H; SFDP address location 4EH, where the last sector/block of this Major Section ends.
Sector Type 2, size is represented by 02H; SFDP The value in this field is a constant value adder (c) for
address location 50H, Sector Type 3, size is repre- a given formula or equation, (2m + 1) + (c). See “Mem-
sented by 03H; and SFDP address location 52H, Sec- ory Configuration”
tor Type 4, size is represented by 04H. Contiguous
Same Sector Type # Size can re-emerge across the 11.1.5 MEMORY CONFIGURATION
memory range and this Sector Type # will indicate that For the SST26VF064B/064BA family, the memory con-
it is a separate/independent Major Section from the figuration is setup with different contiguous block sizes
previous contiguous sectors/blocks. from bottom to the top of the memory. For example,
starting from bottom of memory it has four 8KByte
11.1.2 NUMBER OF SECTORS blocks, one 32KByte block, x number of 64KByte
Number of Sectors represents the number of contigu- blocks depending on memory size, then one 32KByte
ous sectors/blocks with similar size. A formula calcu- block, and four 8KByte block on the top of memory. See
lates the contiguous sectors/blocks with similar size. Table 11-3.
Given the sector/block size, type, and the number of
sectors, the address range of these sectors/blocks can
be determined along with specific Block Locking Reg-
ister bits that control the read/write protection of each
sectors/blocks.

TABLE 11-3: MEMORY BLOCK DIAGRAM REPRESENTATION

8 KByte Bottom Block Section 1: Sector Type 1
(from 000000H) Section 1: Number of Sectors
Section 1: Block-Protection Register Bit Start Location
Section 1: Block-Protection Register Bit End Location
32 KByte Section 2: Sector Type Number
Section 2: Number of Sectors
8 KByte (Top Block) Section 5: Sector Type Number
Classifying these sector/block sizes via the Sector • 64Mbit = 7

Type derived from JEDEC Flash Parameter Table: • 128Mbit = 8
SFDP address locations 4CH, 4EH, and 50H is as fol-
Block Protect Register Start/End Bits are mapped in the
lows:
SFDP by using the formula (2m + 1) + (c). “m” is a con-
• 8KByte Blocks are classified as Sector Type 1 stant value that represents the different densities from
(@4CH of SFDP) 8Mbit to 128Mbit (used also in the formula calculating
• 32KByte Blocks are classified as Sector Type 2 number of 64Kbyte Blocks above). The values that are
(@4EH of SFDP) going to be placed in the Block Protection Bit Start/End
• 64KByte Blocks are classified as Sector Type 3 field table are the constant value adder (c) in the for-
(@50H of SFDP) mula and are represented in two’s compliment except
when the value is 00H. If the value is 00H, this location
For the Number of Sectors associated with the contig-
is the 0 bit location. If the value is other than 0, then this
uous sectors/blocks, a formula is used to determine the
is a constant value adder (c) that will be used in the for-
number of sectors/blocks of these Sector Types:
mula. The most significant (left most) bit indicates the
• 8KByte Block (Type 1) is calculated by 2n. n is a sign of the integer; it is sometimes called the sign bit.
byte. If the sign bit is zero, then the number is greater than or
• 32KByte Block (Type 2) is calculated by 2n. n is a equal to zero, or positive. If the sign bit is one, then the
byte. number is less than zero, or negative.
• 64KByte Block (Type 3) is calculated by (2m - 2). See Table 11-4 for an example of this formula.
m can either be a 4, 5, 6, 7 or 8 depending on the
memory size. This m field is going to be used for
the 64KByte Block Section and will also be used
for the Block Protection Register Bit Location for-
mula.
m will have a constant value for specific densities and
is defined as:
• 8Mbit = 4
• 16Mbit = 5
• 32Mbit = 6

TABLE 11-4: BPSL/BPEL EQUATION WITH ACTUAL CONSTANT ADDER DERIVED FROM THE
FORMULA (2M + 1) + (C)
Block Size 8 Mbit to 128 Mbit Comments
8 KByte (Type 1) Bottom BPSL = (2m + 1) + 0FFH 0FFH = -1; 06H = 6
BPEL = (2m + 1) + 04H Odd address bits are Read-Lock bit
locations and even address bits are
Write-Lock bit locations.
32 KByte (Type 2) BPSL = BPEL= (2m + 1) + 0FDH 0FDH= -3
64 KByte (Type 3) BPSL = 00H 00H is Block-Protection Register bit 0
BPEL = (2m + 1) + 0FCH location; 0FCH = -4
32 KByte (Type 2) BPSL = BPEL= (2m + 1) + 0FEH 0FEH=-2
8 KByte (Type 1) Top BPSL = (2m + 1) + 07H 07H = 7; 0EH = 14
BPEL = (2m + 1) + 0EH Odd address bits are Read-Lock bit
locations and even address bits are
Write-Lock bit locations.

TABLE 11-5: REVISION HISTORY

Revision Description Date
A • Initial release of data sheet Mar 2012
B • Revised figures 5-8-5-10on pages 17-19, figures 5-13-5-15 on pages Jun 2012
21-22, figures 5-25- 5-28 on pages 27- 30, figures 5-36-5-39 on pages
35-35, and figures 5-42-5-43 on pages 37-37
• Updated the SFDP Table: Table 11-1 on page 59
C • Updated document to new format Apr 2013
• Revised CPNs to reflect the new package codes
• Updated package drawings to the new format
• Revised “Hardware Write Protection” on page 7, “Write-Suspend and
Write-Resume” on page 28, and “Lock-Down Block-Protection Regis-
ter (LBPR)” on page 36
• Updated “Power-Up Specifications” on page 44

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Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
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Microchip’s customer notification service helps keep
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specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
MICROCHIP MAKES NO REPRESENTATIONS OR
and UNI/O are registered trademarks of Microchip Technology
WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of
devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries.
the buyer’s risk, and the buyer agrees to defend, indemnify and
Analog-for-the-Digital Age, Application Maestro, BodyCom,
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
conveyed, implicitly or otherwise, under any Microchip
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
intellectual property rights.
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
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Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-134-1
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headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
== ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

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SST26VF064B / SST26VF064BA

3.0V Serial Quad I/O (SQI) Flash Memory

 2013 Microchip Technology Inc. Advance Information DS25119C-page 1

1.0 BLOCK DIAGRAM

WP# HOLD# SCK CE# SIO [3:0]

FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM

DS25119C-page 2 Advance Information  2013 Microchip Technology Inc.

2.0 PIN DESCRIPTION

25119 08-soic S2A P1.0

FIGURE 2-1: PIN DESCRIPTION FOR 8-LEAD SOIC

25119 08-wson QA P1.0

FIGURE 2-2: PIN DESCRIPTION FOR 8-CONTACT WSON

FIGURE 2-3: PIN DESCRIPTION FOR 16-LEAD SOIC

 2013 Microchip Technology Inc. Advance Information DS25119C-page 3

FIGURE 2-4: PIN DESCRIPTION FOR 24-BALL TBGA

TABLE 2-1: PIN DESCRIPTION

DS25119C-page 4 Advance Information  2013 Microchip Technology Inc.

3.0 MEMORY ORGANIZATION

Top of Memory Block

2 Sectors for 8 KByte blocks

8 Sectors for 32 KByte blocks

Bottom of Memory Block

FIGURE 3-1: MEMORY MAP

 2013 Microchip Technology Inc. Advance Information DS25119C-page 5

4.0 DEVICE OPERATION

FIGURE 4-1: SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)

FIGURE 4-2: SQI SERIAL QUAD I/O PROTOCOL

4.1 Device Protection 4.1.1 INDIVIDUAL BLOCK PROTECTION

DS25119C-page 6 Advance Information  2013 Microchip Technology Inc.

 2013 Microchip Technology Inc. Advance Information DS25119C-page 7

TABLE 4-1: WRITE PROTECTION LOCK-DOWN STATES

1. Default at power-up Register settings for SST26VF064B

Active Hold Active Hold Active

FIGURE 4-3: HOLD CONDITION WAVEFORM.

DS25119C-page 8 Advance Information  2013 Microchip Technology Inc.

4.5 Status Register

TABLE 4-2: STATUS REGISTER

 2013 Microchip Technology Inc. Advance Information DS25119C-page 9

4.5.1 WRITE-ENABLE LATCH (WEL) 4.5.3 WRITE SUSPEND PROGRAM

TABLE 4-3: CONFIGURATION REGISTER

1. SST26VF064B default at Power-up is ‘0’

DS25119C-page 10 Advance Information  2013 Microchip Technology Inc.

4.5.8 I/O CONFIGURATION (IOC)

4.5.9 BLOCK-PROTECTION VOLATILITY

4.5.10 WRITE-PROTECT ENABLE (WPEN)

 2013 Microchip Technology Inc. Advance Information DS25119C-page 11

TABLE 5-1: DEVICE OPERATION INSTRUCTIONS FOR SST26VF064B/064BA

DS25119C-page 12 Advance Information  2013 Microchip Technology Inc.

TABLE 5-1: DEVICE OPERATION INSTRUCTIONS FOR SST26VF064B/064BA

 2013 Microchip Technology Inc. Advance Information DS25119C-page 13

Note: C[1:0] = 66H; C[3:2] = 99H

FIGURE 5-1: RESET SEQUENCE

SI 03 ADD. ADD. ADD.

FIGURE 5-2: READ SEQUENCE (SPI)

DS25119C-page 14 Advance Information  2013 Microchip Technology Inc.

5.4 Enable Quad I/O (EQIO)

Note: SIO[3:1] must be driven VIH

FIGURE 5-3: ENABLE QUAD I/O SEQUENCE

FIGURE 5-4: RESET QUAD I/O SEQUENCE (SPI)

FIGURE 5-5: RESET QUAD I/O SEQUENCE (SQI)