From Design To Tape-Out in SCL 180nm CMOS Integrated Circuit Fabrication Technology
From Design To Tape-Out in SCL 180nm CMOS Integrated Circuit Fabrication Technology
From Design To Tape-Out in SCL 180nm CMOS Integrated Circuit Fabrication Technology
Joydeep Basu is with the Department of Electronics & Electrical Communication Engineering (E&ECE) and Advanced VLSI Design Laboratory (AVDL),
Indian Institute of Technology (IIT) Kharagpur, Kharagpur 721302, India.
ABSTRACT
Although India has achieved considerable capability in electronic chip design, but developing the infrastructure for capital-
intensive semiconductor fabrication remains a challenge. The rising domestic and global demand for electronics products, the
need of enhancing the country’s high-technology talent pool, employment generation, and national security concerns dictates the
Indian Government’s heightened efforts in promoting electronics hardware manufacturing in the country. A recent milestone in
this regard is the setting up of 180nm CMOS fabrication facility at SCL, Chandigarh. The Multi Project Wafer runs of this
indigenous foundry promises to be a relatively cost-effective option for Indian academic and R&D institutions in realizing their
designed VLSI circuits. Written from the perspective of an Analog VLSI designer, this tutorial paper strives to provide all the
requisite information and guidance that might be required in order to prepare chip designs for submission to SCL for fabrication.
Keywords:
Cadence Virtuoso, Calibre, CMOS, electronics, foundry, integrated circuit, layout, post-layout, SCL, semiconductor, simulation, Spectre, VLSI
common in academia (and more convenient too from within ring in the layout, select the area to be enclosed, and then click
ADE GUI) than HSPICE, this paper documents the usage of Create MPP Guard Ring. In the resulting dialog, select the
Spectre for all simulations. preferred option in Guard Ring Template field, e.g., choosing
After the schematic is completed, click Launch ADE-L. “PWELL Tap” or “PWELL RING” will enclose the selected
Here, ensure that Simulator option is set to “spectre” (by using area with a P-well guard ring. Then click Apply and Hide.
Setup Simulator). Next, click on Setup Model Libraries. Remember to place matching labels (using suitable layer
Enter the path of the model file (an example being shown with purpose “lbl”) for each corresponding pin as used in the
below), and choose appropriate Section from the drop-down schematic. Note: use layer WN (of purpose “vss”) if you have
list. E.g., select “tt_18” for typical 1.8V MOSFETs. multiple Grounds (e.g., Digital Ground and Analog Ground) in
~/scl_pdk/design_kit/models/hspice/ts18sl_scl. the layout to avoid LVS error (as electrically, both of these
lib Grounds are connected to the same bulk).
Separate model file sections are required to be used if other 3.2 Design Rule Check
device types, like resistors (e.g., res2t_typ), capacitors (e.g., To run a Design Rule Check (DRC) on the designed layout,
mimcap_typ), etc. are present in the schematic. use Calibre menu in Virtuoso layout editor window (for this,
In SCL PDK, dimensions of the devices are assumed to be the Calibre-Virtuoso interface should be present installed).
in micrometer scale. Thus, in ADE, ensure that the parameter Click Calibre Run DRC from the layout window. Go to
Scale is set to 1e-6 (using Simulation Options Analog FileLoad Runset and browse to the drc.rsf file. Then, click
Component). With these settings, you are ready to perform on Run DRC. Rectify layout errors (if any) as pointed by DRC.
simulations in ADE.
3.3 Antenna Rule Check
To check for antenna errors, invoke Calibre Run DRC from
3. PHYSICAL DESIGN
the layout editor. Go to FileLoad Runset and browse to the
After schematic freeze, layout design is to be done followed by antenna.rsf file. Click on Run DRC, and rectify errors if any.
related DRC, LVS, etc. checking steps, as delineated below.
SCL recommended die sizes are 2mm×2mm and 5mm×5mm. 3.4 Layout Versus Schematic
In order to check the electrical propriety of the prepared layout
3.1 Design of Layout
with respect to its schematic, run Layout Versus Schematic
From the schematic editor window, launch Layout-XL in order (LVS) using the following steps.
to create the corresponding layout. The Layout Grid of layout (i) Create CDL netlist of the schematic using CIWFile
editor must be set to an integer multiple of 0.005µm. Thus, ExportCDL. In the window that appears, click on the button
using Options Display in Layout-XL window, set X Snap Library Browser and browse to the desired schematic. In the
Spacing and Y Snap Spacing to 0.005 (i.e., 5nm). Output section of the window, specify the Run Directory as the
Now, prepare the layout design as desired. Some common cdl_netlist directory in the <WORKING_DIR>. Also, specify
layers that may be needed for drawing are WN, GC, ACTIVE, the Output CDL Netlist File as the name of the cell. An
XP, XN, M1, M2, M3, TOP_M, CS, V2, V3, TOP_V (all with example screenshot is shown in Fig. 2 for convenience.
purpose “drw”). Corresponding description and DRC rules are (ii) Launch Calibre Run LVS from the layout editor.
available in [6]. To instantiate vias, click Create Via, and in (iii) Go to FileLoad Runset and browse to the lvs.rsf file.
the Via Definition field, select as required. For using guard (iv) In the Inputs section of the LVS window, select the Netlist
Figure 2. Screenshots showing setup as required for creating the CDL netlist (left) and for running LVS using Calibre (right).
4
tab. In the Files field, browse to your cdl_netlist directory and 4.2.1 CDF Edit
select the CDL file as generated before, and also the scale.cdl Go to Cadence CIW window, and click ToolsCDFEdit.
file, and add these in the list of files (as shown in Fig. 2). Select Base in “CDF layer”. Then, choose the appropriate
(v) You can now click on Run LVS, and clean errors if any. library name and cell name. Click on “Component Parameter”
section in the CDF form, and write “model” in both the Name
4. POST-LAYOUT SIMULATION and Prompt columns. And select “string” in Type section.
Steps for performing post-layout simulation on the extracted Also, set “yes” in Parse as CEL field. Keep the other fields at
circuit netlist as obtained from the layout are discussed here. default values and click on Apply. An illustrative screenshot is
given in Fig. 3.
4.1 Parasitics Extraction Next, go to Simulation Information section and select “By
Generate the parasitics extracted netlist using following steps. Simulator” option. In the drop-down menu, select “spectre”
(i) Launch CalibreRun PEX from the layout editor window. and write “model” in otherParameters box. In “termOrder”
(ii) Go to FileLoad Runset and browse to the pex.rsf file. field, write down the pin names in the proper order as in the
(iii) In the Inputs section of the PEX window, select the Netlist corresponding PEX netlist file. Click on the button OK. These
tab. In the Files field, browse to your cdl_netlist directory and settings are depicted in Fig. 3. Note: The pin names entered
select the CDL file (as generated before for the particular cell) here should match with that in the corresponding symbol (in
and the scale.cdl file, and add these in the list of files. case those names differ with the netlist). Also, the order of
(iv) Go to the Outputs section of the PEX window and choose pins in the generated PEX netlist might change if the layout is
Format as either HSPICE (if you wish to use HSPICE for re-extracted. Then, the order should be changed accordingly in
post-layout simulation) or SPECTRE (if you want Spectre); CDF as well.
and change the File name to <cell_name.sp> (for HSPICE) or
4.2.2 Spectre View Generation of Cell
to <cell_name.pex.netlist > (for Spectre).
(v) Go to PEX Options section and select the LVS Options tab. From Virtuoso Library Manager, select the symbol view of the
Here, enter VDD in the field Power nets and GND in the field cell (corresponding to the layout for which we need to do post-
Ground nets. layout simulation), right click on it, and select copy option. In
(vi) Following this, click on Run PEX. This will generate a the “To” section of the ensuing Copy View window, change
parasitics extracted file named <cell_name.pex.netlist>. the view field from “symbol” to “spectre”, and click OK. So, a
spectre view is created that appears exactly like the symbol.
4.2 Lone Simulation of a PEX Netlist
4.2.3 Instantiate PEX Netlist into Schematic
Post-layout simulation can be done with HSPICE in command-
mode. For this, the user should write an appropriate SPICE Create a testbench schematic by instantiating the symbol (or
testbench netlist. This should include reference to the PEX alternatively, the spectre view) of the cell (whose layout PEX
generated netlist. For reasons mentioned before, post-layout netlist is to be simulated). Now select the symbol and press
simulation with Spectre has been detailed here instead of “Q”. Go to CDF parameter section in “Edit Object Properties”
HSPICE. Its various consecutive steps are mentioned below. window and write the name of the corresponding cell in the
The netlist created by PEX is a file like <cell.pex.netlist>. Is “model” field.
it possible to associate this netlist to the corresponding sub- Then, invoke ADE where the Simulator should be set to
circuit symbol used in a bigger circuit in Virtuoso schematic Spectre. In SetupModel libraries form, provide the path to
editor. For this, you need to create a cell with a CDF parameter the SCL model files (as before) along with the path to the PEX
“model” which will point to the netlist that you want to use. netlist file. Go to SimulationOptionAnalogComponent,
and set the “scale” field to 1 (as all the dimensions in the
extracted PEX netlist are actual values and not scaled ones).
With these settings, you are ready to run simulations. Mind
that this method holds for multiple instantiations (sub-circuits)
of PEX netlists in the testbench, but, would not work if some
schematic level symbol is included in the testbench (due to
mismatch in requirement of the “scale” field setting).
Note: If you want to switch between the schematic and the
“spectre” (i.e., netlist) views, use the Switch view list in Setup
Environment in ADE and put “schematic” ahead of
“spectre”. You also need to remove the previously included
sub-circuit netlist in Model Libraries; and change the “scale”
value to the one as discussed above.
4.3 Co-Simulation of PEX Netlists with Schematics
Here, besides different constituent sub-circuits, the testbench
schematic also includes a sub-circuit defined by a PEX netlist
(associated using “spectre” view as discussed). Now, the issue
is that the schematic sub-circuits require scale=1e-6; but, the
sub-circuit defined in the netlist doesn't require this scale.
In this scenario, the simulation can be performed using the
MTS (Multi Technology Simulation) mechanism in ADE-XL.
The following steps are required to be followed for this. Let
the netlist defined sub-circuit be named “Comparator_ver2a”.
(i) At first, create a wrapper i.e., a schematic (say, named
“Comparator_ver2a_wrapper”) which instantiates symbol of
“Comparator_ver2a”, and also has the same symbol view as
“Comparator_ver2a” - simply wire through all the connections:
(also, do enter the corresponding cell name in the field
“model” as shown below; the field “model” actually appears
due to the prior CDF editing step).
(ii) Use the “Comparator_ver2a_wrapper” symbol (in place of
“Comparator_ver2a symbol”) in the main testbench schematic.
Then, use the Hierarchy Editor to create a config view for your
design. As depicted in Fig. 4, select the view to use as spectre
for the “Comparator_ver2a” block in the Hierarchy Editor.
(iii) Launch ADE-XL from this config schematic window. Figure 4. Example screenshots showing creation and instantiation of
Define a test by clicking on “Click to add test” - select View wrapper cell view, setting up of Hierarchy Editor for config, ADE-XL
window, MTS Options form, and Model Library Setup form settings.
Name as config in Choosing Design dialog, which opens the
ADE-XL Test Editor window. You may need to set Setup
simulatorspectre. Then, define the simulations and outputs for “Comparator_ver2a_wrapper” (so the netlist would not be
required. After this, you can close the ADE-XL Test Editor. used), and set its scale to 1e-6. Then you can run. Unchecking
(iv) Right Mouse click over the test name in ADE-XL to pick MTS_BLOCK for “Comparator_ver2a”, or disabling MTS
Simulator, and turn on the MTS checkbox there. Then, do fully will also work.
Right Mouse click over the test nameMTS Options. In the
MTS setup, enable “Comparator_ver2a_wrapper” as the MTS 5. MONTE-CARLO SIMULATION
block, and add the model file (the netlist path) for Launch ADE-XL from the schematic window for which Monte
“Comparator_ver2a” and scale=1.0 to it. Carlo simulation is to be run. As prompted, create a new adexl
(v) Set the default scale in SimulationOptionsAnalog to view after which the ADE-XL GUI opens [14]. In the Tests
1e-6 as usual. section, click to create a new test due to which an ADE child
Then you can run the simulation from ADE-XL. Note: To window opens. Here, ensure that the Simulator option is set to
change back to the schematic view (instead of the netlist) for Spectre, and set the model file to ts18sl_scl_mat.lib (instead
“Comparator_ver2a”: In the Hierarchy Editor, change view to of the usual ts18sl_scl.lib). Then, set the simulations and
use to schematic for the “Comparator_ver2a” block, and click outputs to be saved/plotted.
on Recompute the hierarchy button. Also, in the MTS Options Now return back to the ADE-XL window. Select Monte
window, uncheck the model file (i.e., the path of the netlist) Carlo Sampling in the drop-down list. Click on Settings and
6
6. I/O LIBRARY
CIO150 is the 1.8V I/O pad library (CIO250 being the 3.3V
one) of SCL, that will be used here for demonstrating I/O ring.
6.1 Different I/O pads
Different types of I/O pads are available in the CIO150 library
which is present within the home directory. From this, the pads
required commonly are listed below (and shown in Fig. 5):
pc3d00 (used for analog I/O connection)
pv0a (used for ground connection)
pv0i (used for ground connection)
pv0c (used for ground connection)
pvda (used for power connection) Figure 5. Depiction of general constituent cells of I/O ring with usage.
pvdi (used for power connection)
pvdc (used for power connection) FileNewCell View from Library Manager. Like this, make
Apart from these, there are layouts of many other types of symbols for all your pads (as depicted in example in Fig. 6).
pads available in the I/O library [15]. Together with I/O pads, In this regard, it should be mentioned that symbols are not
we will need four corner cells and suitable filler cells to make required to be made for the corner and filler cells.
the layout of the ring. The layout of fillers (e.g., pfeed00010,..) 6.2.2 Making the Ring
of various widths are present in CIO150, while the corner cells Using the symbols created earlier, compose the schematic of
(comprised of pfrelf and dummy_corner cells) should be the ring. Ensure all the individual VDD, VDDO, VSS, VSSO
obtained from SCL (e.g., from their io_template library). are connected by means of proper labeling (as seen in Fig. 7).
Fig. 5 depicts the use of various pads and cells to compose Note: Put pins for at least a pair of Vdd & ground (say, VDD
the I/O ring. The ring has four supply lines (i.e., VDD, VDDO, & VSS) in the schematic (as this is needed by LVS).
VSS and VSSO required for the circuits within the I/O pads). Further, create the corresponding layout (i.e., the I/O ring)
Further, as evident from the figure, the supplies from the pvdi for this schematic by instantiation of layouts of the required
and pv0i pads (i.e., VDD and VSS) may be used for the core cells (including the fillers and corner cells). Consequently, the
circuits as well. completed layout will be something like that shown in Fig. 7.
6.2 Composing the I/O Ring Note: Make sure that the individual cells are perfectly abutted,
For the sake of demonstration, let’s make a new library named i.e., neither overlapped nor separated. It should give no DRC
“Inverter_with_IO” to create a sample I/O ring. Copy all cells error and warning (apart from “projection parallel” warning)!
that you will need (e.g., pvdi, pv0i, etc.) from CIO150 and Put labels for the Vdd & ground (here, VDD & VSS) as used
io_template to your “Inverter_with_IO” library. in the schematic on the corresponding pads.
6.2.1 Making Symbols of the Pads 6.3 LVS of the I/O Ring
After copying the layouts of the individual cells, we have to After DRC cleaning the layout, go for its LVS. To check LVS,
make corresponding symbols for each. The information about we need to generate CDL netlist of the schematic of the ring
port names of individual pads are in the file tsl18cio150.cdl (using same procedure as described before). Let the file name
provided by SCL (shown in Fig. 6). To make the schematic be “ring.cdl” for example.
and symbol views for individual pads, click on the respective Modify the generated CDL file in the following manner:
cell (e.g., “pvdi” from the library “Inverter with IO”), then do (i) Comment all the sub circuit definitions of the cells used e.g.
Figure 6. Example screenshots showing ts018150.cdl file, schematic prepared for pvdi, and an instantiated symbol of pvdi cell.
7
pvda, pvdi, etc. using ‘*’ symbol (except the main SUBCKT to the corresponding labels on the pads.
which defines the whole ring). E.g., for pvda: (iii) Using labeling layer for TOP_M, put labels on all the pads
*.SUBCKT pvda VDD VDDO VSS VSSO of your I/O ring as necessary.
*.PININFO VDD:B VDDO:B VSS:B VSSO:B Next, perform DRC and LVS of this whole layout following
*.ENDS the same steps as mentioned in previous section. Note: if you
are using CMOS input pad pc3d01 or the output pad pc3o01,
(ii) Arrange/edit all the port names associated with the
Calibre LVS will throw the following type of error:
individual pad cell instances, defined inside the main
SUBCKT named “ring” in the order as defined in the property w not found on I9/RM30 (R) (here I9 is
tsl18cio150.cdl. E.g., in the generated CDL, it may be like: an instance of pc3o01)
XI0 VDD VDDO VSS VSSO / pvda To clear this LVS error, comment the following lines within
But, in tsl18cio150.cdl, for pvda cell: your LVS header file, as shown below:
// Select w/l property check for res/cap devices
.SUBCKT pvda VDDO VDD VSS VSSO
//#define ANALOG
So, appropriately edit the order/name of the ports like below:
6.5 PEX and Simulation of Core Together with I/O Ring
XI0 VDDO VDD VSS VSSO / pvda
Perform the PEX of the whole layout, for which the Inputs
(iii) After editing CDL file, launch Calibre LVS and include Netlists are to be loaded in the same way as done for LVS.
the files tsl18cio150.cdl (first) and ring.cdl (second). The Then, you can run post-layout simulation of this extracted
order is important (as all the devices/pads used in ring.cdl are netlist. Here, you will need to include the following extra
defined in tsl18cio150.cdl file). sections from the model file ts18sl_scl.lib (required for the
(iv) Now run LVS. If every step mentioned are followed devices present within the pads, like NHV MOS, DPH diode,
correctly, the ring should be LVS clean. NWCAPH2T): “tt_hv”, “diodes”, “acc_typ”.
6.4 LVS of Core Together with I/O Ring 6.6 Schematic Simulation of Core Together with I/O Ring
For this, make a schematic instantiating (and interconnecting) Circuit schematics of the I/O pads are not available and only
your core and I/O ring blocks. Correspondingly, create the netlist definition of these have been provided by the foundry in
layout, containing the core and ring layouts, and route to the the file tsl18cio150.cdl. Thus, to simulate the total schematic
pads as required. Also, note the following: of core jointly with its I/O ring, the method involving config
(i) For analog I/O pad pc3d00, connect from core to the metal view and MTS (as also discussed previously) is required. This
layer labeled as “PADR”. is done using the steps as described below.
(ii) For the pv0i, pvdc, etc. power pads, connect using Metal-2 (i) Create a symbol view for the schematic that comprises of
the I/O ring and core. Instantiate this symbol in a testbench
schematic, and invoke ADE-XL. Set Spectre as the simulator,
and enable the MTS option (steps for this has been discussed
before). Note: You need to edit CDF and create spectre views
for each of the I/O pads used in your circuit (using procedure
as delineated in earlier section). For editing the CDF, the
termOrder is required to be filled as defined for that particular
pad in tsl18cio150.cdl.
(ii) Create and define a corresponding config view as needed:
we need to use netlist definition for I/O pads (hence, spectre
view to be used), and schematic definition of core circuits.
(iii) In MTS Options form, click to check and hence, enable
MTS for the constituent core blocks. Set scale to 1e-6 for
these blocks. However, keep the scale at 1 in ADE Simulator
Options form.
(iv) As the provided tsl18cio150.cdl netlist is for LVS etc.
purposes, so the devices are defined using their LVS names
(refer to SCL Design Rules manual [16] for details). Hence,
manually replace those names in this file with corresponding
SPICE names (for all of the I/O pads used). E.g., the LVS
name of 1.8V PMOS is “P” while its SPICE name is “P18”.
(v) In the Model Library Setup form of ADE, include the path
to the edited tsl18cio150.cdl file.
Figure 7. Example showing creation of I/O ring schematic and layout. With these settings, you are ready to simulate in ADE-XL.
8
APPENDIX
Information on environment/version of EDA tools as utilized:
Cadence: Virtuoso version IC6.1.5.500.17
Mentor Graphics: Calibre v2013.2_18.13
Synopsys: HSPICE version J-2014.09-2
The author wishes to state that the best effort has been put to
avoid cases of error or missing information in this tutorial.
However, any such instance if found is completely inadvertent.
The tool usage methods discussed here are not necessarily best
case ones, and there may be more efficient ways for the same.
ACKNOWLEDGMENT
The author would like to sincerely thank Mr. H. S. Jattana, Mr.
Figure 9. Example showing how to edit the DUMMY.header file. Uday P. Khambete, and Mr. Ashutosh Yadav of SCL,
Chandigarh for information and support received during the
from the user. Download the “mosiscrc.c” file from [17] and course of interactions. The author would like to express deep
copy it to a new folder together with your GDSII file. Open a gratitude to Prof. Pradip Mandal of E&ECE, IIT Kharagpur
terminal there and enter following command: for all the helpful advice and guidance. Appreciations are also
gcc mosiscrc.c -o mosiscrc due to Dr. Samiran Dam and Mr. Koustav Roy (formerly with
./mosiscrc -b <your_GDSII_file_name.gds> AVDL, IIT Kharagpur) for their documentation efforts related
to the usage of SCL process; and to Prof. T. K. Bhattacharyya
This will display the checksum for the concerned GDSII file. (of E&ECE and Professor-in-charge, AVDL), Prof. Mrigank
7.7 Sending Files to SCL Sharad (of E&ECE), Dr. Nijwm Wary (formerly with AVDL),
Fill up SCL tapeout submission form doc file with required and Mr. Indranil Som and Mr. Hrishikesh Sarkar (of AVDL)
details pertaining to the layout, e.g., customer information, for their various helpful efforts and kind support.
design environment/version used, GDSII file name/size, die
size/coordinates, types of core device and I/O library used, REFERENCES
checksum value, etc. This is to be submitted together with the 1. Report on “Human Resource and Skill Requirements
GDSII file, reports/logs of DRC, Antenna, Stream out; and in the Electronics and IT Hardware Sector (2013-17,
lists of device types and layers used in the design. The list of 2017-22),” National Skill Development Corporation
devices is a text file containing names of devices used in both (NSDC), India. Available at:
the core and I/O ring of the design, like pmos_18, nmos_18, http://meity.gov.in/esdm/hrd
cmim_sq, pdio_sal, etc. 2. R. Rastogi, “Indian Electronics and IT Industry - An
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