DIGITAL ELECTRONICS (ECE 211) LAB MANUAL

3rd Semester (2019-20)

Department of Electronics and Communication Engineering

School of Engineering and Applied Sciences
SRM University-AP, Amaravati
List of Experiments
0. Realization of Basic Logic Gates

1. Design of Code Converters (Binary to Gray) & (Gray to Binary)

2. Design of

a) Half-Adder/Subtractor

b) Full-Adder/Subtractor

c) Multiplexers/De Multiplexers

d) ALU Design
3. Design of Decoder and Encoder/ BCD 7SSD

4. Design of Magnitude Comparator (2-bit)

5. Design and Verification of Flip-Flops using IC

6. Design of Asynchronous Counter (Any Mod, Up and Down, Johnson and Ring)

7. Design of Synchronous Counter (Any Mod, Decade counter 74ls90)

8. Design of Universal Shift Register (Serial to Parallel, Parallel to Serial, Serial to Serial and
Parallel to Parallel Converters)

9. Design & Verification of Memory (SRAM)

10. FSM Based Design Project.
IC PIN DIAGRAMS:

AND GATE (7408) OR GATE (7432)

NOT GATE (7404) Ex-OR GATE (7486)

NAND GATE (7400) NOR GATE (7402)

EX NOR GATE (74266) 3 INPUT AND GATE (7411)

3 INPUT NAND GATE (7410) D FLIPFLOP (7474)

JK FLIP FLOP (7476)

 Experiment 0
REALIZATION OF BASIC LOGIC GATES
AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - As per
Required

THEORY:

Circuit that takes the logical decision and the process are called logic gates.
Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal gates.
Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs
is low.
OR GATE:

The OR gate performs a logical addition commonly known as OR function. The output
is high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT GATE:

The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.
NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are
low and any one of the input is low .The output is low level when both inputs are high.
NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low.
The output is low when one or both inputs are high.
X- OR GATE:

The output is high when any one of the inputs is high. The output is low when both the
inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
OR GATE:

NOT GATE:
X-OR GATE :
SYMBOL : PIN DIAGRAM :
3- INPUT NAND GATE :

Conclusion:
 Experiment 1
DESIGN OF CODE CONVERTORS (BINARY TO GRAY AND GRAY TO
BINARYCONVERSION)

Aim: To design code converters and verify their truth tables

Apparatus:

1. IC - 7486
2.Electronic circuit designer

3.Connecting patch chords

Circuit diagram:
BINARY TO GRAY:
GRAY TO BINARY:

THEORY:
WHAT IS BINARY CODE: -
BINARY code is a way of representing the text or the data generated by the computers and other
devices. In binary coding the text or the data is represented in a stream of bits of 1's and 0's. that is
weighted as ......8,4,2,1. so for forming 7, you just need 111.similar computation for other decimal
numbers.
WHAT ARE GRAY CODES: -
GRAY CODES are non-weighted codes, that is they can’t be provided a weight to calculate their
equivalent in decimal. Gray codes are often called reflected binary code; the reason is clear if you
compare the column of gray code with the binary code. gray Code is a symbolic representation of
discrete information. Codes are of different types. Gray Code is one of the most important codes. It
is a non-weighted code which belongs to a class of codes called minimum change codes. In this
codes while traversing from one step to another step only one bit in the code group changes. In case
of Gray Code two adjacent code numbers differs from each other by only one bit. The idea of it can
be cleared from the table given below.

Procedure: -
1. The circuit connections are made as shown in fig.
2. Pin (14) is connected to +Vcc and Pin (7) to ground.
3. In the case of binary to gray conversion, the inputs B0, B1, B2 and B3 are given atrespective
pins and outputs G0, G1, G2, G3 are taken for all the 16 combinations of the input.

4. In the case of gray to binary conversion, the inputs G0, G1, G2 and G3 are given at respective
Pins and outputs B0, B1, B2, and B3 are taken for all the 16 combinations of inputs.

5. The values of the outputs are tabulated.

Conclusion:
 Experiment 2
DESIGN OF COMBINATIONAL LOGIC CIRCUITS

Aim: - To design and construct a) Half-adder, Half- subtractor,

b) Full-adder, Full- subtractor.

Apparatus: -
1.IC’s - 7486, 7432, 7408, 7400

2. Electronic Circuit Designer

3. Connecting patch chords.

THEORY:

HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘ S’
and other from the carry ‘ c’ into the higher adder position. Above circuit is called as a carry signal
from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND gate.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three
inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so.
In full adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate.
HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input
and two outputs. The outputs are difference and borrow. The difference can be applied using X-OR
Gate, borrow output can be implemented using an AND Gate and an inverter.
FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the
logic circuit should have three inputs and two outputs. The two half subtractor put together gives a full
subtractor. The first half subtractor will be C and A B.
The output will be difference output of full subtractor. The expression AB assembles the borrow output
of the half subtractor and the second term is the inverted difference output of first X-OR.

Half adder:

Half Subtractor:
 Full Adder:

FULL SUBTRACTOR:

Procedure: -
1. Verify the gates.

2. Make the connections as per the circuit diagram.

3. Switch on VCC and apply various combinations of input according to truth table.

4. Note down the output readings for half/full adder and half/full subtractor, Sum/difference and the
carry/borrow bit for different combinations of inputs verify their truth tables.
Conclusion:
 C)DESIGN OF MULTIPLEXER & DEMULTIPLEXER
Aim: To design Multiplexer and Demultiplexer and verify their truth tables
Apparatus: 1. IC 74153, IC 74139 etc
2. Electronic circuit designer kit

3.Connecting patch chords

Theory:
Multiplexer means many to one. A multiplexer is a circuit with many inputs but only one output.
By using control signals (select lines) we can select any input to the output. Multiplexer is also called as
data selector because the output bit depends on the input data bit that is selected. The general idea about
the multiplexing the circuit has N input signals, M control signals and 1 output signal.8 X 1 Multiplexer
has 8 input signals and one output signal, three data control or select lines. These data control lines are
nothing but 3-bit binary code on the data control signal inputs which will allow the data on the
corresponding data input to pass through to the data output.
Procedure: - (IC 74153)
1. The Pin [16] is connected to + Vcc.

2. Pin [8] is connected to ground.

3. The inputs are applied either to ‘A’ input or ‘B’ input.

4. If MUX ‘A’ has to be initialized, Ea is made low and if MUX ‘B’ has to be initialized, Eb is
made low.

5. Based on the selection lines one of the inputs will be selected at the output and thus verify the
truth table

Procedure: - (IC 74139)

1. The inputs are applied to either ‘a’ input or ‘b’ input

2. The demux is activated by making Ea low and Eb low.

3. Verify the truth table .

Conclusion:
PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs.

CONCLUSION:
 D)ARITHMETIC LOGIC UNIT
Aim: - To verify the Function table of 4 bit ALU(IC 74181).
Apparatus Required: -
IC 74181, etc.
Procedure:
1. Connections are made as shown in the Circuit diagram.

2. Change the values of the inputs and verify at least 5 functions given in the function table.

Pin detail & Function table:-

IC 74181:
Functionality:
When the model control input(M) is high, all internal carries are disabled and device performs logical
operation on individual bits as listed. When Mode control input is low the carries are enabled and the device
performs arithmetic operation on two four bit words. The Device includes full internal look ahead and
provides for either ripple carry between devices using C n+4 output, for carry loclahead between packages
using signals P (Carry Propagate) and C (Carry Generate).P and G are not affected by carry in.When speed
requirement are not so much required, it can be used in a simple ripple carry mode by connecting the carry
output signal (Cn+4 )signal to the carry input Cn of the next unit. For high speed operation the device is used
in the conjunction with the 182 carry look ahead circuit. One carry look ahead package is required for each
group of four 181' devices. Carry look ahead can be provided in various angle and provide at various levels
and can offer high speed capability over long words length. The A=B output from the device goes High, when
all four output from the device is high and can be used to indicate logical equivalence over 4bit when the unit
is in subtract mode. The A=B output is open collector and can be wired AND with other A=B outputs to give
a comparison for more than 4bits.The A=B signal can be used with Cn+4 signal to indicate A< B and A >B

The function table list the arithmetic operation that are performed without a carry in.An incoming carry adds
a one to each operation. Thus the select code LHHS generates A minus B minus 1 (2s compliment notation)
without a carry in and and generates A minus B when a carry is applied. Because subtraction is actually
performed by complimentary addition (1s compliment),a carry out means borrow; thus a carry is generated
when there is no under flow and no carry is generated when there is underflow. As indicated this device can
be used with either active low inputs producing active low outputs or with active high inputs producing active
active high outputs. For either cause the table lists the operations that are performed to operands labelled
inside the logic symbol.
ALU CIRCUIT DIAGRAM:
Conclusion: -
 Experiment 3
DESIGN OF DECODER AND ENCODER
Aim:
To verify the operation of 8 to 3 line Encoder and 3 to 8 Decoder using IC 74138 and 74148.
Apparatus:

Equipment : Digital IC Trainer Kit

Discrete Components : IC 74148,IC 74138,RESISTOR 100Ω,LEDS.

ENCODER:
A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs,
where the input and output codes are different. Binary Decoder has n inputs and 2n outputs also called as
n-to-2n decoder.

DECODER:
Decoder is the combinational circuit which contains ‘n’ input lines to 2n output lines. The decoder is used
for converting the binary code into the octal code. The IC74138 is the 3 x 8 decoder which contains three
inputs and 8 outputs and also three enables out of them two are active low and one is active high.
Decoders are used in the circuit where required to get more outputs than that of the inputs.

Circuit Diagram:
PROCEDURE:
1. Connect as per the diagram given.
2. Apply Vcc to pin 16 and Gnd to pin 8 of the 74138.
3. Connect the inputs to pins 1,2,3.
4. Connect pin 4,5 to gnd and 6 to Vcc.
5. Similarly when E2 is HIGH all the outputs are high irrespective of the inputs.
6. When E3 is low all the inputs are high irrespective of E1 and E2 = high.
7. If E1 and E2 are low and E3 is high the inputs are low, the outputs 0o will be low with all
the other outputs are low.
9. Change the inputs we get 1 and outputs as low and all the other outputs as high.
10. Note BCD output from the IC 74148 as the input to 74138.
11. Compare the truth table.
12. Note outputs of decoder truth table.

CONCLUSION:
 Experiment 4
DESIGN OF MAGNITUDE COMPARATOR

Aim: - To verify the truth table of one bit and four bit comparators using logic
Gates and IC 7485

Apparatus: -
IC’s -7486, 7404, 7408 and 7485

Theory: -
Magnitude Comparator is a logical circuit, which compares two signals A and B and
generates three logical outputs, whether A > B, A = B, or A < B. IC 7485 is a high speed 4-
bit Magnitude comparator, which compares two 4-bit words. The A = B Input must be held
high for proper compare operation.

Circuit diagrams:

2Bit Comparator:
Truth table:
Procedure: -

1. Connect the circuit as shown in fig. Feed the 4-bit binary words A0, A1, A2, A3 and
B0, B1, B2, B3 from the logic input switches.

2. Pin 3 of IC 7485 should be at logic 1 to enable compare operation.

3. Observe the output A>B, A=B, and A<B on logic indicators. The outputs must
be 1 or 0 respectively.

4. Repeat the steps 1 ,2 and 3 for various inputs A0, A1, A2, A3 and B0, B1, B2, B3 and
observe the outputs at A>B , A=B and A<B .

Conclusion:
 Experiment 5
VERIFICATION OF TRUTH TABLES OF FLIPFLOPS USING IC

Aim: ‐To design and construct basic flip-flops R-S, J-K,D,T flip-flops using IC and
verify their truth tables

Apparatus:‐
1. IC’s - 7404, 7402, 7400,7474,7476.
2. Electronic circuit designer

3. Connecting patch chords

THEORY:
•RS FLIP-FLOP:
There are two inputs to the flip-flop defined as R and S. When I/Ps R=0 and S=0 then O/P
remains unchanged. When I/Ps R=0andS=1 the flip-flop is switches to the stable state where
O/P is 1i.e. SET. The I/P condition is R=1 and S=0 the flip-flop is switched to the stable state
where O/P is 0i.e. RESET. The I/P condition is R=1 and S=1 the flip-flop is switched to the
stable state where O/P is forbidden.

•JK FLIP-FLOP:
For purpose of counting, the JK flip-flop is the ideal element to use. The variable J and K are
called control I/Ps because they determine what the flip-flop does when a positive edge arrives.
When J and K are both0s, both AND gates are disabled and Q retain sits last value.

•D FLIP–FLOP:
This kind of flip-flop prevents the value of D from reaching the Q output until clock pulses
occur. When the clock is low, both AND gates are disabled D can change value without affecting
the value of Q. On the other hand, when the clock is high, both AND gates are enabled. In this
case, Q is forced to equal the value of D. When the clock a gain goes low, Q retains or stores the
last value of D.A D flip-flop is a bistable circuit whose D input is transferred to the output after
a clock pulse is received.

•T FLIP-FLOP:
TheTor"toggle"flipflop changes its output on each clock edge, giving an output which is half
the frequency of the signal to the T input. It is useful for constructing binary counters, frequency
dividers, and general binary addition devices. It can be made from a J-K flip-flop by tying both
of its inputs high.
JK FLIP FLOP USING IC:

Truth table:
D FLIP FLOP USING IC: TRUTH TABLE:

PIN DIAGRAM:

T FLIP FLOP USING IC:

Procedure:
1. Connect the Flip-flop circuits as shown above.
2. Apply different combinations of inputs and observe the outputs

Conclusion:
 Experiment 6
DESIGN OF ASYNCHRONOUS COUNTER
Aim:-To design and construct of 3-bit Asynchronous up and down counters.

Apparatus:
1. IC’s - 7408,7476,7400,7432
2. Electronic circuit designer
3. Connecting patch chords

THEORY:
A counter in which each flip-flop is triggered by the output goes to previous flip-flop. As all the
flip-flops do not change state simultaneously spike occur at the output. To avoid this, strobe pulse
is required. Because of the propagation delay the operating speed of asynchronous counter is low.
Asynchronous counter are easy and simple to construct.

Circuit Diagram:
MOD-8 UP COUNTER
MOD-8 DOWN COUNTER:

PROCEDURE:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Rig up the circuit as shown in the logic circuit diagram.
4. Apply various input data to the logic circuit via the input logic switches.
5. Note down the corresponding output and verify the truth table.

Conclusion:
 Experiment 6.B
DESIGN OF RING AND JOHNSON COUNTERS USING FLIP-FLOPS

Aim: To design Ring counter and Johnson counter and verify their truth tables

Apparatus:

1. IC’s - 7404, 7402, 7400

2. Electronic circuit designer
3. Connecting patch chords

THEORY:
A ring counter is a circular shift register which is initiated such that only one of its flip-flops is
the state one while others are in their zero states.
A ring counter is a shift register (a cascade connection of flip-flops) with the output of the last
one connected to the input of the first, that is, in a ring. Typically, a pattern consisting of a single
bit is circulated so the state repeats every n clock cycles if n flip-flops are used.
A Johnson counter (or switch-tail ring counter, twisted ring counter, walking ring counter,
or Mobius counter) is a modified ring counter, where the output from the last stage is inverted
and fed back as input to the first stage. The register cycles through a sequence of bit-patterns,
whose length is equal to twice the length of the shift register, continuing indefinitely. These
counters find specialist applications, including those similar to the decade counter, digital-to-
analog conversion, etc. They can be implemented easily using D- or JK-type flip-flops.
Circuit Diagram:
RING COUNTER:

Truth Table:
CLK Q2 Q1 Q0
0 1 0 0
1 0 1 0
2 0 0 1
JOHNSON COUNTER:

Truth Table:

CLK Q2 Q1 Q0
0 0 0 0
1 1 0 0
2 1 1 0
3 1 1 1
4 0 1 1
5 0 0 1

Procedure:
1. Connections are made as per the circuit diagram

2. Switch on the power supply.

3. Apply clock pulses and note the outputs after each clock pulse

Conclusion:
 Experiment 7
Design Synchronous Counter, Mod Counter, Up Counter, Down Counter

Aim:-To design and construct of 3-bit Synchronous up and down counters.

Apparatus:

1. IC’s - 7408,7476,7400,7432
2. Electronic circuit designer
3. Connecting patch chords
THEORY:

A counter in which each flip-flop is triggered by the output goes to previous flipflop. As all the
flip-flops do not change states simultaneously in asynchronous counter, spike occur at the output.
To avoid this, strobe pulse is required. Because of the propagation delay the operating speed of
asynchronous counter is low. This problem can be solved by triggering all the flip-flops in
synchronous with the clock signal and such counters are called synchronous counters.

Circuit Diagram:
 TRUTH TABLE:

Procedure:

1. Connections are made as per the circuit diagram

2. Switch on the power supply.

3. Apply clock pulses and note the outputs after each clock pulse and note done the out puts.

Conclusion:
 7.B DECADE COUNTER 74LS90

Aim: To construct and verify the working of a single digit decade counter using IC 7490.

Apparatus: 1) IC7490 Decade counter kit

2 ) Connecting patch cards.

THEORY:
A decade counter is one that counts in decimal digits, rather than binary. A decade counter may
have each (that is, it may count in binary-coded decimal, as the 7490 integrated circuit did) or
other binary encodings. "A decade counter is a binary counter that is designed to count to 1010
(decimal 10). An ordinary four-stage counter can be easily modified to a decade counter by adding
a NAND gate as in the schematic to the right. Notice that FF2 and FF4 provide the inputs to the
NAND gate. The NAND gate outputs are connected to the CLR input of each of the FFs." A
decade counter is one that counts in decimal digits, rather than binary. It counts from 0 to 9 and
then resets to zero. The counter output can be set to zero by pulsing the reset line low. The count
then increments on each clock pulse until it reaches 1001 (decimal 9). When it increments to 1010
(decimal 10) both inputs of the NAND gate go high. The result is that the NAND output goes low,
and resets the counter to zero. D going low can be a CARRY OUT signal, indicating that there has
been a count of ten.

Circuit Diagram:-
 MOD 6 COUNTERS:

Truth Table:-
Procedure:
1. Wire the circuit diagram shown in figure 1.
2. Connect the 1Hz clock to pin CPO.(14)
3. Connect the reset terminals (MR1 & MR2) to high and set terminals (MS1 & MS2) to
zero and observe the output.
4. Now connect set and reset inputs to zero and observe the outputs.
5. Record the counter states for each clock pulse.
6. Design mod 6 counter using IC 7490 as shown in fig 2.
7. Record the counter states for each clock pulse.
8. Now Construct decade counter using J – K F/F’s and record the counter states.

CONCLUSION:
 Experiment 8
DESIGN OF SHIFT REGISTER

Aim:- To study shift register using IC 7495 in all its modes i.e. SIPO/SISO,
PISO/PIPO.

Apparatus: - IC 7495, etc.

THEORY:
In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output
of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting in a circuit
that shifts by one position the "bit array" stored in it, "shifting in" the data present at its input and
'shifting out' the last bit in the array, at each transition of the clock input.
More generally, a shift register may be multidimensional, such that its "data in" and stage outputs are
themselves bit arrays; this is implemented simply by running several shift registers of the same bit-
length in parallel.
Shift registers can have both parallel and serial inputs and outputs. These are often configured as
"serial-in, parallel-out" (SIPO) or as "parallel-in, serial-out" (PISO). There are also types that have
both serial and parallel input and types with serial and parallel output. There are also "bidirectional"
shift registers which allow shifting in both directions: L→R or R→L. The serial input and last output
of a shift register can also be connected to create a "circular shift register". One register is PIPO
(parallel in parallel out), which is very fast, within single clock pulse, it is giving output

Circuit diagram: ‐
PISO:-
Procedure:
Serial In Parallel Out(SIPO):

1. Connections are made as per circuit diagram.

2. Apply the data at serial i/p

3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.

4. Apply the next data at serial i/p.

5. Apply one clock pulse at clock 2, observe that the data on QA will shift to QB and the new data
applied will appear at QA.

6. Repeat steps 2 and 3 till all the 4 bits data are entered one
by one into the shift register.
Serial In Serial Out (SISO):

1. Connections are made as per circuit diagram.

2. Load the shift register with 4 bits of data one by one serially.

3. At the end of 4th clock pulse the first data ‘d0’ appears at QD.

4. Apply another clock pulse; the second data ‘d1’ appears at QD.

5. Apply another clock pulse; the third data appears at QD.

6. Application of next clock pulse will enable the 4th data ‘d3’ to appear at QD. Thus the data
applied serially at the input comes out serially at QD

Parallel In Serial Out (PISO):

1. Connections are made as per circuit diagram.

2. Apply the desired 4 bit data at A, B, C and D.

3. Keeping the mode control M=1 apply one clock pulse. The data applied at A, B,
C and D will appear at QA, QB, QC and QD respectively.

4. Now mode control M=0. Apply clock pulses one by one and observe the Data coming
out serially at QD.

Parallel In Parallel Out (PIPO):

1. Connections are made as per circuit diagram.

2. Apply the 4 bit data at A, B, C and D.

3. Apply one clock pulse at Clock 2 (Note: Mode control M=1).

4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively.

CONCLUSION:
 EXPERIMENT 9

Design & Verification of Memory (SRAM) (16×4) - IC 7489

Aim: -
To study the operation of the RAM Ic7489.

Apparatus:

1. RAM IC 7489 Trainer

kits.
2. Connecting wires.

Pin Diagram: -

Operation: -
• RAM IC 7489 is 16 words x 4-bit Read/Write Memory.
• The Truth Table for the RAM IC 7489 is given below.
• The memory Enable pin is used to select 1- of-n ICs i.e. like a Chip Select signal. For
simply city, the memory enable pin is permanently held low.
• The address lines are given through an up /down counter with preset capability.
• The set address switch is held high to allow the user choose any location in the RAM, using
the address bits.
• The address and data bits are used to set an address and enter the data.
• The ‘Read/Write ‘switch is used to write data on to the RAM.
Procedure:
This experiment has 3 stages – Clearing the memory, data entry (Write operation)
and data verification (Read operation).
Clearing the Memory: -The RAM IC 7489 is a volatile memory. This means that it will lose
the
data stored in it, on loss of power. However, this dose not means that the content of the
memory
becomes 0h, but not always. The RAM IC 7489 does not come with a ‘ Clear Memory ‘
signal.
The memory has to be cleared manually.
1. Position the ‘Stack/Queue’ switch in the ‘Queue’ position.
2. Position the ‘Set Address’ switch in the ‘1’ position.
3. Set the address bits to 0h (first byte in the memory)
4. Position the ‘Set Address’ switch in the ‘0’ position to disable random access and enable
the counter.
5. Position the’ Read/Write ‘switch in the’ Write’ position to write data on to the memory.
6. Set the data bits to 0h (clearing the content)
7. Observe that the LEDs (D3 to D0) glow. This is to indicate that the content is 0h. Refer
the truth table above and observe that the data outputs of the RAM will be compliments of
the data inputs.
8. Position the ‘Increment/Decrement ‘switch in the ‘Increment’ position.
9. Press the ‘Clock’ to increment the counter to the next address. As the ‘Read /Write ‘
switch is already in the ‘Write’ position, and the data bits are set to the 0h, the content in the
new location is also replaced with 0h.
Write Operation: -
1. Assume that the following data has to be written on to the RAM. The address and data
are given in the hexadecimal format.
2. Position the ‘Stack/Queue’ switch in the ‘ Queue ‘position.
3. Position the’ Read/Write ‘switch in the’ Write’ position to enable the entry of data in to the
RAM.
4. Position the ‘Set Address’ switch in the ‘1’ position to allow random access of memory.
5. Set the desired address (any address at random) using the address bit switches.
6. Set the desired data (refer table for the data to be entered in each location) using the data
bit switches.
7. Observe that the data is indicated by the LEDs (D3 toD0). This is because the data is
written on to the RAM.
8. Also observe that the data is indicated by the data outputs is the compliment of the data
input (refer truth table condition ME =L and WE=L).
9. After each data entry, make a note of the location where data is entered. This is to make
sure that we are not re –entering data in the same location.
10. Repeat steps 4 and 5 until data has been entered in all the addresses listed in the above
table
11. Position the’ Read/Write ‘switch in the’ Read’ position, to disable data entry.
12. This completes data entry.

Read Operation: -
1. Position the ‘Stack/Queue’ switch in the ‘Queue’ position.
2. Position the ‘Set Address’ switch in the ‘0’ position to allow random access of memory.
3. Position Read/Write ‘switches in the’ Read’ position, to disable unauthorized entry of data.
4. Set the desired address (any address at random).
5. Observe that the data entered in the location is indicated by the LEDs (D3 toD0).
This is because the data was written during the data entry procedure.
6. Also observe that the data indicated by the data out puts is the compliment of the data
input (refer truth table condition ME=L and WE=H).

CONCLUSION:
 EXPERIMENT 10

FSM Based Design Project

The finite state machines (FSMs) are significant for understanding the decision making logic
as well as control the digital systems. In the FSM, the outputs, as well as the next state, are a
present state and the input function. This means that the selection of the next state mainly
depends on the input value and strength lead to more compound system performance. As in
sequential logic, we require the past inputs history for deciding the output. Therefore FSM
proves very cooperative in understanding sequential logic roles. Basically, there are two
methods for arranging a sequential logic design namely mealy machine as well as more
machine. This article discusses the theory and implementation of a finite state machine or FSM,
types, finite state machine examples, advantages, and disadvantages.

What is an FSM (Finite State Machine)?

The definition of a finite state machine is, the term finite state machine (FSM) is also known
as finite state automation. FSM is a calculation model that can be executed with the help of
hardware otherwise software. This is used for creating sequential logic as well as a few
computer programs. FSMs are used to solve the problems in fields like mathematics, games,
linguistics, and artificial intelligence. In a system where specific inputs can cause specific
changes in state that can be signified with the help of FSMs.

This finite state machine diagram explains the various conditions of a turnstile. Whenever
placing a coin into a turnstile will unbolt it, and after the turnstile has been pressed, it bolts
gain. Placing a coin into an unbolted turnstile, otherwise pressing against a bolted turnstile
will not alter its state.
Types of Finite State Machine

The finite state machines are classified into two types such as Mealy state machine and Moore
state machine.

Mealy State Machine

When the outputs depend on the current inputs as well as states, then the FSM can be named
to be a mealy state machine. The following diagram is the mealy state machine block diagram.
The mealy state machine block diagram consists of two parts namely combinational logic as
well as memory. The memory in the machine can be used to provide some of the previous
outputs as combinational logic inputs.

Based on the current inputs as well as states, this machine can produce outputs. Thus, the
outputs can be suitable only at positive otherwise negative of the CLK signal. The mealy state
machine’s state diagram is shown below.
The state diagram of mealy state machine mainly includes three states namely A, B, and C.
These three states are tagged within the circles as well as every circle communicates with one
state. Conversions among these three states are signified by directed lines. In the above
diagram, the inputs and outputs are denoted with 0/0, 1/0, and 1/1. Based on the input value,
there are two conversions from every state.

Generally, the amount of required states in the mealy machine is below or equivalent to the
number of required states in Moore state machine. There is an equal Moore state machine for
every Mealy state machine. As a result, based on the necessity we can employ one of them.

Moore State Machine:

When the outputs depend on current states then the FSM can be named as Moore state
machine. The Moore state machine’s block diagram is shown below. The Moore state
machine block diagram consists of two parts namely combinational logic as well as memory.

In this case, the current inputs, as well as current states, will decide the next states. Thus,
depending on further states, this machine will generate the outputs. So, the outputs of this
will be applicable simply after the conversion of the state.

The Moore state machine state diagram is shown below. In the above state, the diagram
includes four states like a mealy state machine namely A, B, C, and D. the four states as well
as individual outputs are placed in the circles.
In this case, the current inputs, as well as current states, will decide the next states. Thus,
depending on further states, this machine will generate the outputs. So, the outputs of this
will be applicable simply after the conversion of the state.

The Moore state machine state diagram is shown below. In the above state, the diagram
includes four states like a mealy state machine namely A, B, C, and D. the four states as well
as individual outputs are placed in the circles. In this case, the current inputs, as well as
current states, will decide the next states. Thus, depending on further states, this machine
will generate the outputs. So, the outputs of this will be applicable simply after the
conversion of the state.
 0

In the above figure, there are four states, namely A, B, C & D. These states and the respective
outputs are labeled inside the circles. Here, simply the input worth is marked on every
conversion. In the above figure includes two conversions from every state depending on the
input value.

Generally, the amount of required states in this machine is greater than otherwise equivalent to
the required number of states in the mealy state machine

Generally, the number of required states in this machine is more than otherwise equivalent to
the required states in MSM (Mealy state machine). For every Moore state machine, there is a
corresponding Mealy state machine. Consequently, depending on the necessity we can utilize
one of them. There is an equal mealy state machine for every Moore state machine. As a result,
based on the necessity we can employ one of them.