CMS COLLEGE OF ENGINEERING & TECHNOLOGY

Coimbatore - 641032.

DEPARTMENT OF
COMPUTER SCIENCE AND ENGINEERING

CS3352–DIGITAL PRINCPLES AND COMPUTER

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(R-2021)

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 CMS
COLLEGE OF ENGINEERING & TECHNOLOGY
Coimbatore - 641032.

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the above student during the year 2023-2024

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Submitted for the Practical Examination held on……………….…………

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 CONTENTS

Name Of Exercise Page

/ Experiment Staff
Ex.No. Date
No Sign.

1 STUDY OF LOGIC GATES

VERIFICATION OF BOOLEAN
2 THEOREMS USING LOGIC
GATES

3 IMPLEMENTATION OF CODE
CONVERTORS

4a IMPLEMENTATION OF ADDER
AND SUBTRACTOR CIRCUITS

4b IMPLEMENTATION OF 4-BIT
BINARY ADDER/SUBTRACTOR
CIRCUITS
IMPLEMENTATION
5
OF FUNCTIONS
USING
MULTIPLEXER

6 IMPLEMENTATION UNIVERSAL
SHIFT REGISTER
IMPLEMENTATION OF
7
SYNCHRONOUS COUNTERS

IMPLEMENTATION OF BCD
8a
ADDER

IMPLEMENTATION OF
8b
ENCODER AND DECODER
CIRCUITS
SIMULATOR BASED STUDY
9 OF COMPUTER
ARCHITECTURE
Ex.No.-1 STUDY OF LOGIC GATES

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14

THEORY:
Circuit that takes the logical decision and the process are called logic gates.
Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level
when any one of the inputs is low.

OR GATE:
The OR gate performs a logical addition commonly known as OR function.
The output is high when any one of the inputs is high. The output is low level when
both the inputs are low.

NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.

AND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both
inputs are high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both
inputs are low. The output is low when one or both inputs are high.
X- OR GATE:
The output is high when any one of the inputs is high. The output is low
when both the inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

AND GATE

SYMBOL PIN DIAGRAM

OR GATE
 NOT GATE

SYMBOL PIN DIAGRAM

EX-OR GATE

SYMBOL PIN DIAGRAM

 2-INPUT NAND GATE

SYMBOL PIN DIAGRAM

3-INPUT NAND GATE

 NOR GATE

RESULT:

The logic gates are studied and its truth tables are verified.
Ex.No.-2 VERIFICATION OF BOOLEAN
THEOREMS USING DIGITAL LOGIC GATES

AIM:
To verify the Boolean Theorems using logic gates.

APPARATUS REQUIRED:

SL. NO. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1
As per
5. CONNECTING WIRES - required

THEORY:

BASIC BOOLEAN LAWS

1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A

2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C

3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law
1. A+AB = A
2. A+AB = A+B

5. Involution (or) Double complement Law

1. A = A

6. Idempotent Law
1. A+A = A
2. `A.A = A
7. Complementary Law
1. A+A' = 1
2. A.A' = 0

8. De Morgan’s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
Demorgan’s Theorem
a) Proof of equation (1):
Construct the two circuits corresponding to the functions A’. B’and (A+B)’
respectively. Show that for all combinations of A and B, the two circuits give identical
results. Connect these circuits and verify their operations.
b) Proof of equation (2)
Construct two circuits corresponding to the functions A’+B’and (A.B)’ A.B,
respectively. Show that, for all combinations of A and B, the two circuits give identical
results. Connect these circuits and verify their operations.
We will also use the following set of postulates:
P1: Boolean algebra is closed under the AND, OR, and NOT operations.
P2: The identity element with respect to • is one and + is zero. There is no identity
element with respect to logical NOT.
P3: The • and + operators are commutative.
P4: • and + are distributive with respect to one another. That is,
A • (B + C) = (A • B) + (A • C) and A + (B • C) = (A + B) • (A + C).
P5: For every value A there exists a value A’ such that A•A’ = 0 and A+A’ = 1.
This value is the logical complement (or NOT) of A.
P6: • and + are both associative. That is, (A•B)•C = A•(B•C) and (A+B)+C = A+(B+C).
You can prove all other theorems in boolean algebra using these postulates.

PROCEDURE:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.

RESULT:
Thus the above stated Boolean laws are verified.
Ex.No.-3 IMPLEMENTATION OF CODE CONVERTOR

AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
SL.NO. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:

The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion circuit
must be inserted between the two systems if each uses different codes for same
information. Thus, code converter is a circuit that makes the two systems compatible even
though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code uses
four bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a
non-weighted code.

The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.

A code converter is a circuit that makes the two systems compatible even though
each uses a different binary code. To convert from binary code to Excess-3 code, the input
lines must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.
 A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that
implements this circuit. Now the OR gate whose output is C+D has been used to
implement partially each of three outputs.

BINARY TO GRAY CODE CONVERTOR

TRUTH TABLE:

Binary Input Gray Code Output

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-Map for G3

G3 = B3
K-Map for G2

K-Map for G1

K-Map for G0
 LOGIC DIAGRAM:

GRAY CODE TO BINARY CONVERTOR

TRUTH TABLE:

GRAY CODE BINARY CODE

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
K-Map for B3:

B3 = G3

K-Map for B2:

K-Map for B1:

K-Map for B0:

LOGIC DIAGRAM:
TRUTH TABLE: BCD TO EXCESS-3 CONVERTOR

| BCD input | Excess – 3 output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x

1 1 0 0 x x x x

1 1 0 1 x x x x

1 1 1 0 x x x x

1 1 1 1 x x x X

K-Map for E3:

E3 = B3 + B2 (B0 + B1)
K-Map for E2:

K-Map for E1:

K-Map for E0:

 EXCESS-3 TO BCD CONVERTOR

TRUTH TABLE:

| Excess – 3 Input | BCD Output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1

LOGIC DIAGRAM:
 EXCESS-3 TO BCD CONVERTOR

K-Map for A:

A = X1 X2 + X3 X4 X1

K-Map for B:

K-Map for C:

2
K-Map for D:

EXCESS-3 TO BCD CONVERTOR

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.
RESULT:

Thus the following 4-bit converters are designed and constructed.

(i) Binary to gray code converter

(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
Ex.No.-4a ADDER AND SUBTRACTOR

AIM:
To design and construct half adder, full adder, half subtractor and full
subtractor circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:
SL.NO. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 23

THEORY:

HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from
the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is
called as a carry signal from the addition of the less significant bits sum from the X-OR
Gate the carry out from the AND gate.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a time but
a half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry
output will be taken from OR Gate.

HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor
has two input and two outputs. The outputs are difference and borrow. The difference can
be applied using X-OR Gate, borrow output can be implemented using an AND Gate and
an inverter.

FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half
subtractor put together gives a full subtractor .The first half subtractor will be C and A B.
The output will be difference output of full subtractor. The expression AB assembles the
borrow output of the half subtractor and the second term is the inverted difference output
of first X-OR.
 HALF ADDER
TRUTH TABLE:

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

1
1

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:
 FULL ADDER

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM

1 1

1 1

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY

CARRY = AB + BC + AC
28
LOGIC DIAGRAM:

FULL ADDER USING TWO HALF ADDER

HALF SUBTRACTOR

TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE

DIFFERENCE = A’B + AB’

K-Map for BORROW

BORROW = A’B

28
 LOGIC DIAGRAM

FULL SUBTRACTOR

TRUTH TABLE:

A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference

1 1

1 1

Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow

28
 Borrow = A’B + BC + A’C

LOGIC DIAGRAM:

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR

PROCEEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus, the half adder, full adder, half subtractor and full subtractor
circuits are designed, constructed and verified the truth table using logic gates.
Ex.No.-4b IMPLEMENTATION OF 4-BIT ADDER AND SUBTRACTOR

AIM:

To design and implement 4-bit adder and subtractor using basic gates and MSI
device IC 7483.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output carry
from each full adder connected to the input carry of next full adder in chain. The augends
bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to
left, with subscript 0 denoting the least significant bits. The carries are connected in chain
through the full adder. The input carry to the adder is C0 and it ripples through the full
adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between
each data input ‘B’ and the corresponding input of full adder. The input carry C 0 must be
equal to 1 when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit is
adder circuit. When M=1, it becomes subtractor.

4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together with an
input carry from a previous stage. Since each input digit does not exceed 9, the output sum
cannot be greater than 19, the 1 in the sum being an input carry. The output of two decimal
digits must be represented in BCD and should appear in the form listed in the columns.
 ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2
decimal digits, together with the input carry, are first added in the top 4 bit adder to
produce the binary sum.

PIN DIAGRAM FOR IC 7483:

4-BIT BINARY ADDER

LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:

4- BIT BINARY ADDER/SUBTRACTOR

LOGIC DIAGRAM:
TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

RESULT:

Thus the 4-bit adder and subtractor using basic gates and MSI device IC 7483 is
designed and implemented.
Ex.No.-5 IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER

AIM:

To design and implement the multiplexer and demultiplexer using logic gates
and study of IC 74150 and IC 74154.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:

MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there
n
are 2 input line and n selection lines whose bit combination determine which input is

selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates.
The data select lines enable only one gate at a time and the data on the data input line will
pass through the selected gate to the associated data output line.
 4:1 MULTIPLEXER

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

TRUTH TABLE:

S1 S0 Y = OUTPUT

0 0 D0

0 1 D1

1 0 D2

1 1 D3
CIRCUIT DIAGRAM FOR MULTIPLEXER:

1:4 DEMULTIPLEXER

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

TRUTH TABLE:

INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

LOGIC DIAGRAM FOR DEMULTIPLEXER:

PIN DIAGRAM FOR IC 74150:

PIN DIAGRAM FOR IC 74154:

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the multiplexer and demultiplexer using logic gates are designed and
implemented.
 Ex.No.-6 UNIVERSAL SHIFT REGISTER

AIM:

To design and implement the Universal shift register

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 4

2. 4X1 MUX 4

3. IC TRAINER KIT - 1

4. PATCH CORDS - 35

THEORY:

A register that can store the data and /shifts the data towards the right and left along
with the parallel load capability is known as a universal shift register. It can be used to
perform input/output operations in both serial and parallel modes. Unidirectional
shift registers and bidirectional shift registers are combined together to get the design of the
universal shift register. It is also known as a parallel-in-parallel-out shift register or shift
register with the parallel load.
Universal shift registers are capable of performing 3 operations as listed below.

 Parallel load operation – stores the data in parallel as well as the data in parallel
 Shift left operation – stores the data and transfers the data shifting towards left in
the serial path
 Shift right operation – stores the data and transfers the data by shifting towards
right in the serial path.
Hence, Universal shift registers can perform input/output operations with both serial and
parallel loads.
 4-BIT UNIVERSAL SHIFT REGISTER

LOGIC DIAGRAM:

TRUTH TABLE:

S0 S1 Mode of Operation
0
0 Locked state (No change)
0
1 Shift-Left
Shift-Right
1 0
Parallel Loading
1 1
OUTPUT WAVEFORM:
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the Universal Shift register is designed and implemented.
Ex.No.-7 IMPLEMENTATION OF SYNCHRONOUS COUNTER

AIM:

To design and implement synchronous counter.

APPARATUS REQUIRED:

S.NO. NAME OF THE APPARATUS RANGE QUANTITY

1. Digital IC trainer kit 1
3. D Flip Flop IC 7474 2
4. NAND gate IC 7400 1
5. Connecting wires As required

THEORY:
.
A counter is a register capable of counting number of clock pulse arriving at its
clock input. Counter represents the number of clock pulses arrived. A specified sequence
of states appears as counter output. This is the main difference between a register and a
counter. There are two types of counter, synchronous and asynchronous. In synchronous
common clock is given to all flip flop and in asynchronous first flip flop is clocked by
external pulse and then each successive flip flop is clocked by Q or Q output of previous
stage. A soon the clock of second stage is triggered by output of first stage. Because of
inherent propagation delay time all flip flops are not activated at same time which results
in asynchronous operation.
PIN DIAGRAM:

SYNCHRONOUS COUNTER

LOGIC DIAGRAM:

TRUTH TABLE:

OUTPUT
CLK DATA
QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus the synchronous counter are designed and implemented.

Ex.No.-8a IMPLEMENTATION OF BCD ADDER

AIM:

To design and implement BCD Adder Circuit.

APPARATUS REQUIRED:

S.NO. NAME OF THE APPARATUS RANGE QUANTITY

1. Digital IC trainer kit 1
2. IC IC 7483 1
3. AND gate 1
4. OR gate 1
5. Connecting wires As required

THEORY:
.
BCD stands for binary coded decimal. It is used to perform the addition of BCD
numbers. A BCD digit can have any of ten possible four-bit representations. Suppose, we
have two 4-bit numbers A and B. The value of A and B can vary from 0(0000 in binary) to
9(1001 in binary) because we are considering decimal numbers.
The output will vary from 0 to 18 if we are not considering the carry from the previous sum.
But if we are considering the carry, then the maximum value of output will be 19 (i.e.
9+9+1 = 19). When we are simply adding A and B, then we get the binary sum. Here, to get
the output in BCD form, we will use BCD Adder.

Example:

Input :
A = 0111 B = 1000
Output :
Y = 1 0101
Explanation: We are adding A(=7) and B(=8).
The value of binary sum will be 1111(=15).
But, the BCD sum will be 1 0101,
where 1 is 0001 in binary and 5 is 0101 in binary.
 BCD ADDER

PIN DIAGRAM:

TRUTH TABLE:
 K-MAP:

LOGIC DIAGRAM:
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus the BCD Adder is designed and implemented.

Ex.No.-8b IMPLEMENTATION OF ENCODER AND DECODER

AIM:

To design and implement Encoder and Decoder Circuits.

APPARATUS REQUIRED:

S.NO. NAME OF THE APPARATUS RANGE QUANTITY

1. Digital IC trainer kit 1
2. NOT gate 2
3. AND gate 3
4. OR gate 3
5. Connecting wires As required

THEORY:
.
An Encoder is a combinational circuit that produces a binary code equivalent to the
input, which is active High. In other words, Encoder is a circuit which converts the analog
signal into the digital signal. Encoders are digital circuit used for encoding.

Characteristics of Encoder:
 It has maximum of 2n input lines and ‘n’ output lines.
 It encodes 2n input lines with ‘n’ bits.
 It performs the reverse operation of Decoder.
 At any time, only one of inputs can be ‘1’ in order to get the respective binary code at the
output and rest of the inputs are zero(0).
 It is used in input system like Keyboards.


A 4 to 2 priority encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. Here,
the input, Y3 has the highest priority, whereas the input, Y0 has the lowest priority. In this
case, even if more than one input is ‘1’ at the same time, the output will be
the binarybinary code corresponding to the input, which is having higher priority.

We considered one more output, V in order to know, whether the code available at outputs is
valid or not.
  If at least one input of the encoder is ‘1’, then the code available at outputs is a valid
one. In this case, the output, V will be equal to 1.
 If all the inputs of encoder are ‘0’, then the code available at outputs is not a valid one.
In this case, the output, V will be equal to 0.

Decoder is a combinational circuit that converts binary code or binary information into
human understandable format.

In other word, Decoder is a combinational circuit which converts the digital signal into analog
signal. Its input will be in digital form while the output will be a continuous sine wave or
analog wave. Decoders are digital circuit which are used for decoding.

Characteristics of Decoder:
 It has ‘n’ input lines and maximum of 2n output lines.
 It performs the reverse operation of Encoder.
 At any time, only one of outputs can be ‘1’ and rest of the outputs are zero(0).
 It is used in output system like display units.
 ENCODER

BLOCK DIAGRAM:

4X2 ENCODER
LOGIC DIAGRAM:

TRUTH TABLE:

From Truth table, we can write the Boolean functions for each output as
A1=Y3+Y2, A0=Y3+Y1
CIRCUIT DIAGRAM:

8X3 ENCODER
LOGIC DIAGRAM:
TRUTH TABLE:

From Truth table, we can write the Boolean functions for each output as

A2=Y7+Y6+Y5+Y4, A1=Y7+Y6+Y3+Y2, A0=Y7+Y5+Y3+Y1

CIRCUIT DIAGRAM:
 PRIORITY ENCODER

TRUTH TABLE:

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0 V

0 0 0 0 0 0 0

0 0 0 1 0 0 1

0 0 1 x 0 1 1

0 1 x x 1 0 1

1 x x x 1 1 1

K-MAP:

A
1
=
Y
3
+
Y
2

A
0
=
Y3+Y2′Y1

V=Y3+Y2+Y1+Y0
LOGIC DIAGRAM:

DECODER

BLOCK DIAGRAM:
 2X4 DECODER
LOGIC DIAGRAM:

TRUTH TABLE:

From Truth table, we can write the Boolean functions for each output as

Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0
 CIRCUIT DIAGRAM:

8X3 DECODER
LOGIC DIAGRAM:
TRUTH TABLE:

From Truth table, The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and
Y7 is as follows:

Y0=A0 '.A1 '.A2'

Y1=A0.A1 '.A2'
Y2=A0 '.A1.A2'
Y3=A0.A1.A2'
Y4=A0 '.A1 '.A2
Y5=A0.A1 '.A2
Y6=A0 '.A1.A2
Y7=A0.A1.A2
CIRCUIT DIAGRAM:
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus the Encoder and Decoder are designed and implemented.

Ex.No.-9 SIMULATOR BASED STUDY OF COMPUTER ARCHITECTURE

AIM:

To Study the Simulator based study of Computer Architecture.

THEORY:
A computer architecture simulator is a program that simulates
the execution of computer architecture.

Computer architecture simulators are used for the following purposes:

 Lowering cost by evaluating hardware designs without building physical hardware

systems.
 Enabling access to unobtainable hardware.
 Increasing the precision and volume of computer performance data.
 Introducing abilities that are not normally possible on real hardware such as running code
backwards when an error is detected or running in faster-than-real time.

Categories

Computer architecture simulators can be classified into many different categories depending
on the context.

 Scope: Microarchitecture simulators model the microprocessor and its components. Full-
system simulators also model the processor, memory systems, and I/O devices.
 Detail: Functional simulators, such as instruction set simulators, achieve the same
function as modeled components. They can be simulated faster if timing is not considered.
Timing simulators are functional simulators that also reproduce timing. Timing simulators
can be further categorized into digital cycle-accurate and analog sub-cycle simulators.
 Workload: Trace-driven simulators (also called event-driven simulators) react to pre-
recorded streams of instructions with some fixed input. Execution-driven simulators allow
dynamic change of instructions to be executed depending on different input data.

Full-system simulators

A full-system simulator is execution-driven architecture simulation at such a level of

detail that complete software stacks from real systems can run on the simulator without any
modification. A full system simulator provides virtual hardware that is independent of the
nature of the host computer. The full-system model typically includes processor
cores, peripheral devices, memories, interconnection buses,
and network connections. Emulators are full system simulators that imitate obsolete hardware
instead of under development hardware.

The defining property of full-system simulation compared to an instruction set simulator is

that the model allows real device drivers and operating systems to be run, not just single
programs. Thus, full-system simulation makes it possible to simulate individual computers
and networked computer nodes with all their software, from network device drivers to
operating systems, network stacks, middleware, servers, and application programs.

Full system simulation can speed the system development process by making it easier to
detect, recreate and repair flaws. The use of multi-core processors is driving the need for full
system simulation, because it can be extremely difficult and time-consuming to recreate and
debug errors without the controlled environment provided by virtual hardware. [1] This also
allows the software development to take place before the hardware is ready, [2] thus helping to
validate design decisions.

Cycle-accurate simulator

A cycle-accurate simulator is a computer program that simulates

a microarchitecture on a cycle-by-cycle basis. In contrast an instruction set
simulator simulates an instruction set architecture usually faster but not cycle-accurate to a
specific implementation of this architecture; they are often used when emulating older
hardware, where time precision is important for legacy reasons. Often, a cycle-accurate
simulator is used when designing new microprocessors – they can be tested, and benchmarked
accurately (including running full operating system, or compilers) without actually building a
physical chip, and easily change design many times to meet expected plan.

Cycle-accurate simulators must ensure that all operations are executed in the proper virtual (or
real if it is possible) time – branch prediction, cache misses, fetches, pipeline stalls, thread
context switching, and many other subtle aspects of microprocessors.
RESULT:

Thus the Simulator based Computer Architecture were studied.