Lab 6 DSD
Lab 6 DSD
Lab 6 DSD
CPE – 344
Lab 6
Class BCE – 7A
-- FunctionSet:
Bit 0 and 1 are arbitrary
Bit 2: Displays font
type(0=5x8, 1=5x11)
Bit 3: Numbers of
display lines (0=1, 1=2)
Bit 4: Data length (0=4
bit, 1=8 bit)
Bit 5-7 are set
-- DisplayCtrlSet:
Bit 0: Blinking cursor
control (0=off, 1=on)
Bit 1: Cursor (0=off,
1=on)
Bit 2: Display (0=off,
1=on)
Bit 3-7 are set
-- DisplayClear:
Bit 1-7 are set */
end
end
end
// stActWr
stActWr : begin
stNext <= stCharDelay;
end
endcase
end
// Assign outputs
assign JB[4] = LCD_CMDS[lcd_cmd_ptr][9];
assign JB[5] = LCD_CMDS[lcd_cmd_ptr][8];
assign JA = LCD_CMDS[lcd_cmd_ptr][7:0];
assign JB[6] = (stCur == stFunctionSet || stCur ==
stDisplayCtrlSet || stCur == stDisplayClear || stCur == stActWr) ? 1'b1
: 1'b0;
endmodule
Post lab:
Main Code:
module PmodCLP( data,
btnr,
CLK,
JA,
JB
);
-- FunctionSet:
Bit 0 and 1 are arbitrary
Bit 2: Displays font
type(0=5x8, 1=5x11)
Bit 3: Numbers of
display lines (0=1, 1=2)
Bit 4: Data length (0=4
bit, 1=8 bit)
Bit 5-7 are set
-- DisplayCtrlSet:
Bit 0: Blinking cursor
control (0=off, 1=on)
Bit 1: Cursor (0=off,
1=on)
Bit 2: Display (0=off,
1=on)
Bit 3-7 are set
-- DisplayClear:
Bit 1-7 are set */
end
end
endcase
end
// Assign outputs
assign JB[4] = LCD_CMDS[lcd_cmd_ptr][9];
assign JB[5] = LCD_CMDS[lcd_cmd_ptr][8];
assign JA = LCD_CMDS[lcd_cmd_ptr][7:0];
assign JB[6] = (stCur == stFunctionSet || stCur ==
stDisplayCtrlSet || stCur == stDisplayClear || stCur == stActWr) ? 1'b1
: 1'b0;
endmodule
Conclusion:
In this lab, we learnt to interface pmod lcd with FPGA and display text.