+ Unit 5

I/O Organization

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+ Roadmap
Input/Output
Chapter
 Interrupt-driven I/O
 External devices
 Interrupt processing
 Keyboard/monitor
 Design issues
 Disk drive
 Direct memory access
 I/O modules  Drawbacks of programmed and
 Module function interrupt-driven I/O
 I/O module structure  DMA function

 Programmed I/O  I/O channels and processors

 The evolution of the I/O function
 Overview of programmed I/O
 Characteristics of I/O channels
 I/O commands/instructions

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 Address Lines

System
Data Lines Bus

Control Lines

I/O Module

Links to
peripheral
devices

Figure 7.1 Generic Model of an I/O Module

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+
1. External Devices

Three
 Provide a means of
exchanging data between the categories:
external environment and the
computer  Human readable
 Suitable for communicating with
the computer user
 Attach to the computer by a  Video display terminals (VDTs),
link to an I/O module printers
 The link is used to exchange
control, status, and data
 Machine readable
between the I/O module and  Suitable for communicating with
equipment
the external device
 Magnetic disk and tape systems,
sensors and actuators
 Peripheral device
 An external device connected  Communication
to an I/O module  Suitable for communicating with
remote devices such as a terminal,
a machine readable device, or
another computer
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 Control Status Data bits
signals from signals to to and from
I/O module I/O module I/O module

Control Buffer
Logic
Transducer

Data (device-unique)
to and from
environment

Figure 7.2 Block Diagram of an External Device

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 Most common means of
+ Keyboard/Monitor computer/user interaction
User provides input through the
keyboard
International Reference Alphabet
(IRA) The monitor displays data
provided by the computer
 Basic unit of exchange is the character
 Associated with each character is a code
 Each character in this code is
Keyboard Codes
represented by a unique 7-bit binary
code  When the user depresses a key it
 128 different characters can be generates an electronic signal that is
represented interpreted by the transducer in the
keyboard and translated into the bit
 Characters are of two types: pattern of the corresponding IRA code
 Printable
 Alphabetic, numeric, and special
 This bit pattern is transmitted to the I/O
characters that can be printed on module in the computer
paper or displayed on a screen
 Control  On output, IRA code characters are
 Have to do with controlling the
transmitted to an external device from the
printing or displaying of characters I/O module
 Example is carriage return
 The transducer interprets the code and
 Other control characters are
sends the required electronic signals to
concerned with communications
procedures the output device either to display the
indicated character or perform the
requested control function
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 The major functions for an I/O
module fall into the following
categories:
Control and timing
• Coordinates the flow of traffic between internal resources and external devices

Processor communication
• Involves command decoding, data, status reporting, address recognition

Device communication
• Involves commands, status information, and data

Data buffering
• Performs the needed buffering operation to balance device and memory speeds

Error detection
• Detects and reports transmission errors

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 Interface to Interface to
System Bus External Device

Data
Data Registers External
Device
Data Status
Interface
Lines
Logic
Status/Control Registers Control

Address
Lines Data
External
I/O Device
Logic Status
Interface
Control Logic
Lines Control

Figure 7.3 Block Diagram of an I/O Module

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+ 2. Programmed I/O
Three techniques are possible for I/O
operations:
 Programmed I/O
 Data are exchanged between the processor and the I/O module
 Processor executes a program that gives it direct control of the I/O
operation
 When the processor issues a command it must wait until the I/O
operation is complete
 If the processor is faster than the I/O module this is wasteful of
processor time
 Interrupt-driven I/O
 Processor issues an I/O command, continues to execute other
instructions, and is interrupted by the I/O module when the latter has
completed its work
 Direct memory access (DMA)
 The I/O module and main memory exchange data directly without
processor involvement
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 Table 7.1
I/O Techniques

No Interrupts Use of Interrupts

I/O-to-memory transfer Programmed I/O Interrupt-driven I/O

through processor

Direct I/O-to-memory Direct memory access (DMA)

transfer

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+
I/O Commands
 There are four types of I/O commands that an I/O module may
receive when it is addressed by a processor:

1) Control
- used to activate a peripheral and tell it what to do

2) Test
- used to test various status conditions associated with an I/O
module and its peripherals

3) Read
- causes the I/O module to obtain an item of data from the
peripheral and place it in an internal buffer

4) Write
- causes the I/O module to take an item of data from the data bus
and subsequently transmit that data item to the peripheral

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 Issue Read Issue Read CPU I/O Issue Read CPU DMA
command to CPU I/O command to Do something block command Do something
I/O module I/O module else to I/O module else

Read status Read status Interrupt Read status Interrupt

of I/O I/O CPU of I/O of DMA
I/O CPU
module module module DMA CPU
Not
ready Next instruction
Check Error Check Error
status condition status condition (c) Direct memory access
Ready Ready
Read word Read word
from I/O I/O CPU from I/O I/O CPU
Module Module

Write word Write word

CPU memory CPU memory
into memory into memory

No No
Done? Done?

Yes Yes
Next instruction Next instruction
(a) Programmed I/O (b) Interrupt-driven I/O
Figure 7.4 Three Techniques for Input of a Block of Data
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 I/O Instructions
With programmed I/O there is a close correspondence between the I/O-related
instructions that the processor fetches from memory and the I/O commands that
the processor issues to an I/O module to execute the instructions

Each I/O device connected through I/O modules is given a

unique identifier or address

The form of the

When the processor
issues an I/O Memory-mapped I/O
instruction depends command, the
on the way in which command contains the
external devices are address of the desired
addressed device

Thus each I/O module There is a single address space for A single read line and a single write
must interpret the memory locations and I/O devices line are needed on the bus
address lines to
determine if the
command is for itself

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+
I/O Mapping Summary

 Memory mapped I/O

 Devices and memory share an address space
 I/O looks just like memory read/write
 No special commands for I/O
 Large selection of memory access commands available

 Isolated I/O
 Separate address spaces
 Need I/O or memory select lines
 Special commands for I/O
 Limited set

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 7 6 5 4 3 2 1 0
516 Keyboard input data register

7 6 5 4 3 2 1 0
Keyboard input status
517
and control register

1 = ready Set to 1 to
0 = busy start read

ADDRESS INSTRUCTION OPERAND COMMENT

200 Load AC "1" Load accumulator
Store AC 517 Initiate keyboard read
202 Load AC 517 Get status byte
Branch if Sign = 0 202 Loop until ready
Load AC 516 Load data byte

(a) Memory-mapped I/O

ADDRESS INSTRUCTION OPERAND COMMENT

200 Load I/O 5 Initiate keyboard read
201 Test I/O 5 Check for completion
Branch Not Ready 201 Loop until complete
In 5 Load data byte

(b) Isolated I/O

Figure 7.5 Memory-Mapped and Isolated I/O

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 3. Interrupt-Driven I/O
The problem with programmed I/O is that the
processor has to wait a long time for the I/O module
to be ready for either reception or transmission of
data

An alternative is for the processor to issue an I/O

command to a module and then go on to do some
other useful work

The I/O module will then interrupt the processor to

request service when it is ready to exchange data
with the processor

The processor executes the data transfer and

resumes its former processing

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 Hardware Software

Device controller or
other system hardware
issues an interrupt
Save remainder of
process state
information
Processor finishes
execution of current
instruction

Process interrupt
Processor signals
acknowledgment
of interrupt
Restore process state
information
Processor pushes PSW
and PC onto control
stack
Restore old PSW
and PC
Processor loads new
PC value based on
interrupt

Figure 7.6 Simple Interrupt Processing

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 T–M T–M
Y N+1
Control Control
Stack Stack
T T
N+1 Y+L
Program Program
Counter Counter

Y Start Y Start
Interrupt General Interrupt General
Service Registers Service Registers
Y + L Return Routine T Y + L Return Routine T–M
Stack Stack
Pointer Pointer

Processor Processor

T–M T

N User's N User's
N+1 N+1
Program Program

Main Main
Memory Memory

(a) Interrupt occurs after instruction

(b) Return from interrupt
at location N

Figure 7.7 Changes in Memory and Registers for an Interrupt

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 Design Issues

• Because there will

be multiple I/O
modules how does
the processor
determine which
Two design device issued the
interrupt?
issues arise in
implementing • If multiple
interrupt I/O: interrupts have
occurred how
does the
processor decide
which one to
process?

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+ Device Identification
Four general categories of techniques are in
common use:
 Multiple interrupt lines
 Between the processor and the I/O modules
 Most straightforward approach to the problem
 Consequently even if multiple lines are used, it is likely that each line will have multiple I/O modules
attached to it

 Software poll
 When processor detects an interrupt it branches to an interrupt-service routine whose job is to poll
each I/O module to determine which module caused the interrupt
 Time consuming

 Daisy chain (hardware poll, vectored)

 The interrupt acknowledge line is daisy chained through the modules
 Vector – address of the I/O module or some other unique identifier
 Vectored interrupt – processor uses the vector as a pointer to the appropriate device-service routine,
avoiding the need to execute a general interrupt-service routine first

 Bus arbitration (vectored)

 An I/O module must first gain control of the bus before it can raise the interrupt request line
 When the processor detects the interrupt it responds on the interrupt acknowledge line
 Then the requesting module places its vector on the data lines

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 Drawbacks of Programmed and
Interrupt-Driven I/O

 Both forms of I/O suffer from two inherent

drawbacks:

1) The I/O transfer rate is limited by the speed

with which the processor can test and service
a device

2) The processor is tied up in managing an I/O

transfer; a number of instructions must be
executed for each I/O transfer

+
 When large volumes of data are to be moved a more
efficient technique is direct memory access (DMA)

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 4. Direct Memory
Access Data
count

Data lines Data

register

Address
Address lines register

Request to DMA
Acknowledge from DMA
Control
Interrupt
logic
Read
Write

Figure 7.12 Typical DMA Block Diagram

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 Time

Instruction Cycle

Processor Processor Processor Processor Processor Processor

Cycle Cycle Cycle Cycle Cycle Cycle

Fetch Decode Fetch Execute Store Process

Instruction Instruction Operand Instruction Result Interrupt

DMA Interrupt
Breakpoints Breakpoint

Figure 7.13 DMA and Interrupt Breakpoints During an Instruction Cycle

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 Processor DMA I/O I/O Memory

(a) Single-bus, detached DMA

Processor DMA DMA Memory

I/O

I/O I/O

(b) Single-bus, Integrated DMA-I/O

System bus

Processor DMA Memory

I/O bus

I/O I/O I/O

(c) I/O bus

Figure 7.14 Alternative DMA Configurations

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 CPU

Data bus

DREQ

HRQ
8237 DMA Main Disk
chip memory controller
HLDA DACK

Address bus

Control bus (IOR, IOW, MEMR, MEMW)

DACK = DMA acknowledge

DREQ = DMA request
HLDA = HOLD acknowledge
HRQ = HOLD request
Figure 7.15 8237 DMA Usage of System Bus

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+
Fly-By DMA Controller

Data does not pass 8237 contains four

through and is not DMA channels
stored in DMA chip • Programmed
• DMA only between independently
I/O port and Can do memory to • Any one active
memory memory via register • Numbered 0, 1, 2,
• Not between two and 3
I/O ports or two
memory locations

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+ 5. I/O channels and processors
Evolution of the I/O Function
1. The CPU directly controls a
4. The I/O module is given direct
peripheral device. access to memory via DMA. It can
now move a block of data to or
2. A controller or I/O module from memory without involving
is added. The CPU uses the CPU, except at the beginning
programmed I/O without and end of the transfer.
interrupts.
5. The I/O module is enhanced to
become a processor in its own
3. Same configuration as in right, with a specialized
step 2 is used, but now instruction set tailored for I/O
interrupts are employed.
The CPU need not spend 6. The I/O module has a local
time waiting for an I/O memory of its own and is, in fact, a
operation to be performed, computer in its own right. With
thus increasing efficiency. this architecture a large set of I/O
devices can be controlled with
minimal CPU involvement.
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 Data and
address channel
to main memory
Selector
channel

Control signal I/O I/O

path to CPU Controller Controller

(a) Selector

Data and
address channel
to main memory
Multi-
plexor
channel
Control signal
path to CPU I/O
Controller

I/O
Controller

I/O
Controller

I/O
Controller

(b) Multiplexor

Figure 7.18 I/O Channel Architecture

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+ Universal Serial Bus (USB)
 Widely used for peripheral connections

 Is the default interface for slower speed devices

 Commonly used high-speed I/O

 Has gone through multiple generations

 USB 1.0
 Defined a Low Speed data rate of 1.5 Mbps and a Full Speed rate of 12 Mbps
 USB 2.0
 Provides a data rate of 480 Mbps
 USB 3.0
 Higher speed bus called SuperSpeed in parallel with the USB 2.0 bus
 Signaling speed of SuperSpeed is 5 Gbps, but due to signaling overhead the
usable data rate is up to 4 Gbps
 USB 3.1
 Includes a faster transfer mode called SuperSpeed+
 This transfer mode achieves a signaling rate of 10 Gbps and a theoretical
usable data rate of 9.7 Gbps

 Is controlled by a root host controller which attaches to devices to

create a local network with a hierarchical tree topology

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+ FireWire Serial Bus
 Was developed as an alternative to small computer system interface
(SCSI) to be used on smaller systems, such as personal computers,
workstations, and servers

 Objective was to meet the increasing demands for high I/O rates while
avoiding the bulky and expensive I/O channel technologies developed
for mainframe and supercomputer systems

 IEEE standard 1394, for a High Performance Serial Bus

 Uses a daisy chain configuration, with up to 63 devices connected off a

single port

 1022 FireWire buses can be interconnected using bridges

 Provides for hot plugging which makes it possible to connect and

disconnect peripherals without having to power the computer system
down or reconfigure the system

 Provides for automatic configuration

 No terminations and the system automatically performs a configuration

function to assign addresses

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+
SCSI
 Small Computer System Interface

 A once common standard for connecting peripheral devices to

small and medium-sized computers

 Has lost popularity to USB and FireWire in smaller systems

 High-speed versions remain popular for mass memory support

on enterprise systems

 Physical organization is a shared bus, which can support up

to 16 or 32 devices, depending on the generation of the
standard
 The bus provides for parallel transmission rather than serial,
with a bus width of 16 bits on earlier generations and 32 bits
on later generations
 Speeds range from 5 Mbps on the original SCSI-1
specification to 160 Mbps on SCSI-3 U3

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+
Thunderbolt

 Most recent and fastest

peripheral connection
technology to become available
for general-purpose use

 Developed by Intel with

collaboration from Apple
 Provides up to 10 Gbps
 The technology combines data, throughput in each direction
video, audio, and power into a and up to 10 Watts of power to
single high-speed connection connected peripherals
for peripherals such as hard
drives, RAID arrays, video-
capture boxes, and network
interfaces

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+
InfiniBand
 I/O specification aimed at the high-end server market

 First version was released in early 2001

 Heavily relied on by IBM zEnterprise series of mainframes

 Standard describes an architecture and specifications for data

flow among processors and intelligent I/O devices

 Has become a popular interface for storage area networking

and other large storage configurations

 Enables servers, remote storage, and other network devices to

be attached in a central fabric of switches and links

 The switch-based architecture can connect up to 64,000

servers, storage systems, and networking devices

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+
SATA
PCI Express

 Serial Advanced Technology

 High-speed bus system for
Attachment
connecting peripherals of a
wide variety of types and  An interface for disk storage
speeds systems

 Provides data rates of up to 6

Gbps, with a maximum per
device of 300 Mbps

 Widely used in desktop

computers and in industrial
and embedded applications

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+
Ethernet
 Predominant wired
networking technology
 Has moved from bus-based to
 Has evolved to support data
switch-based
rates up to 100 Gbps and
distances from a few meters to  Data rate has periodically
tens of km increased by an order of
magnitude
 Has become essential for  There is a central switch
supporting personal with all of the devices
computers, workstations, connected directly to the
servers, and massive data switch
storage devices in
organizations large and small  Ethernet systems are currently
available at speeds up to 100
 Began as an experimental Gbps
bus-based 3-Mbps system

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+ Wi-Fi  As the technology of
antennas, wireless
transmission techniques, and
 Is the predominant wireless
wireless protocol design has
Internet access technology
evolved, the IEEE 802.11
 Now connects computers, committee has been able to
tablets, smart phones, and introduce standards for new
other electronic devices such versions of Wi-Fi at higher
as video cameras TVs and speeds
thermostats
 Current version is 802.11ac
 In the enterprise has become (2014) with a maximum data
an essential means of rate of 3.2 Gbps
enhancing worker productivity
and network effectiveness

 Public hotspots have

expanded dramatically to
provide free Internet access in
most public places

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 Thank You !!!

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