Scribd
Upload
57 views1 page

Verilog HDL Assignment-Module 3

This document contains 10 questions about Verilog HDL concepts like modeling ripple carry adders and counters at the gate level, modeling multiplexers with delays, modeling full adders with carry lookahead, and modeling comparators. It asks students to write Verilog code for various digital circuits using concepts like gates, delays, operators, and test benches, and also asks students to explain digital logic and Verilog concepts.

Uploaded by

kirthi bharadwaj
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
Download as pdf or txt
57 views1 page

Verilog HDL Assignment-Module 3

This document contains 10 questions about Verilog HDL concepts like modeling ripple carry adders and counters at the gate level, modeling multiplexers with delays, modeling full adders with carry lookahead, and modeling comparators. It asks students to write Verilog code for various digital circuits using concepts like gates, delays, operators, and test benches, and also asks students to explain digital logic and Verilog concepts.

Uploaded by

kirthi bharadwaj
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
Download as pdf or txt
Download as pdf or txt
You are on page 1/ 1

A.P.

S College of Engineering
Electronics and Communication Department
Verilog HDL (18EC56)
Module 3

Assignment Questions.

1. a) Design a 4-bit ripple carry full adder using 1-bit full adder. Develop the Verilog
code for a 4-bit ripple carry full adder suing gate level modeling. Verify the
functionality with approiate test bench.
b) Given A = 5’b10101; B = 5’b11101; C = 5’b11001; D = 5’b10011. Evaluate. i. Y
= A & B ii) Y = ∼(&C) iii) Y = C^D iv) Y = C % D v) Y = A + (D >>>1) vi)
{B[3], C[2], A}
2. a) Discuss the gate delays along with its types of delay specification.
b) Design a 4-bit ripple carry counter using TFF. Write the Verilog code using data
flow modelling. Verify the code with appropriate test bench.
3. a) Design a 2x1 MUX using bufif0 and bufif1 gates. Write the Verilog code using
gate level modelling for the given delay specification.
Min Max Typ
Rise 1 3 2
Fall 3 5 4
Turnoff 5 7 6
b) Discuss the types of delays used in the continuous assignment statement.
4. a) Write a Verilog data flow description for 4-bit full adder with carry look ahead.
b) What would be the output of the following: i) a&b ii) a&&b iii) &a iv) a>>1 v)
a>>>1 vi) y-{2{a}} vii) a^b viii) z ={a,b}
5. a) Discuss AND/OR and NOT gates with respect to logic symbols, gate instantiation
and truth table.
b) Define bufif/notif and write gate instantiation of bufif, notif gates.
6. a) What are rise, fall and turn off delays? How they are specified in Verilog?
b) Write gate level description to implement y = ab + c with 5 and 4 time units of
gate delay for AND and OR gate respectively. Also write the stimulus block and
simulation waveforms.
7. Write the dataflow modeling Verilog code for 8 to 1 multiplexer using i) logic
equation ii) conditional operator.
8. Explain assignment delay, implicit assignment delay and net declaration delay for
continuous assignment statements with examples.
9. Write a dataflow level Verilog code using + and {} operators for 4-bit full adders.
10. Write a Verilog code to realize 2-bit comparator (A1A0 & B1B0) in gate level to give
outputs A = B, A >B, A<B. Verify the code with an appropriate test bench

You might also like