DC-DC High-Voltage-Gain Converters With Low Count of Switches and Common Ground

energies
Article
DC-DC High-Voltage-Gain Converters with Low
Count of Switches and Common Ground
Robert Stala , Zbigniew Waradzyn * and Szymon Folmer
Department of Power Electronics and Energy Control Systems, Faculty of Electrical Engineering, Automatics,
Computer Science and Biomedical Engineering, AGH University of Science and Technology, al. Mickiewicza 30,
30-059 Krakow, Poland; [email protected] (R.S.); [email protected] (S.F.)
* Correspondence: [email protected]; Tel.: +48-12-617-2811

Received: 1 September 2020; Accepted: 26 October 2020; Published: 29 October 2020
Abstract: This paper presents a new concept and research results of DC-DC high-voltage-gain,
high-frequency step-up resonant converters. The proposed topologies are optimized towards
minimizing the number of switches and improvements in efficiency. Another relevant advantage of
such type of converters is that they have a common input and output negative point. The proposed
converters are based on the resonant switched-capacitor voltage multiplier circuit, and that is why
they are compared with a classic converter from this family. The included results show the operating
principle, possible switching methods with the consideration of their impact on the voltage gain level,
as well as the voltage and current ripples. The operating concepts and analytical calculations are
confirmed by simulation and experimental results.
Keywords: DC-DC converter; resonant converter; high-voltage-gain converter; switched-capacitor

converter; inductiveless converter
1. Introduction
Switched capacitor (SC) circuits can be effectively used in power electronic converters [1].
The significant advantages of SC-based DC-DC power converters are high-voltage-gain, low volume,
and quasi inductiveless design. To achieve oscillating currents, low-volume inductors can be used in
those converters. They can be designed as air-chokes, or even be based on parasitic inductances of the
circuits, resulting in a decrease in the weight of the converter. The design without ferrite chokes allows
for the use of the converter in high ambient temperature and/or with a low-volume heat sink.
SC DC-DC converters represent one of the classes of non-isolated step-up converters [2–4].
Nowadays, there are a significant number of applications where isolated DC-DC step-up converters
are required [3], due to technical reasons and safety requirements. However, various kinds of
non-isolated converters are extensively developed as well. One of the prospective applications for
non-isolated DC-DC step-up converters proposed in the literature [5–10] are photovoltaic (PV) systems.
High step-up DC-DC converters are often required in grid-connected PV systems to transfer the energy
from a low-voltage PV source to the grid [5,6]. In transformerless PV systems [7,8], as well as in
microinverters [9], dual-stage DC-AC converters are one of the investigated solutions.
The SC step-up DC-DC converter could be a competitive solution to the switch-mode boost
converter. An example of such an idea is presented in Reference [10]. The non-isolated step-up
converter can be used not only for a single stage supply, but as a part of a system composed of
series-connected converters as well. In such systems, isolation can be implemented in another stage of
conversion, e.g., by using a series resonant converter [6,11].
High-voltage-gain in SC-based DC-DC converters can be achieved by applying a suitable
topology concept. In References [12–14], an SC voltage multiplier (SCVM) has been presented. It is
Energies 2020, 13, 5657; doi:10.3390/en13215657 www.mdpi.com/journal/energies

Energies 2020, 13, 5657 2 of 22
a series-parallel converter in that a high-voltage-gain can be obtained, as it is proportional to the

number of switching cells. The advantage of an SCVM is its modular topology; however, the number
of required transistors is relatively high. Series-parallel SC converters have also been presented
in recent publications [15,16]. In Reference [15], a converter with regulated voltage gain has been
discussed. This device utilizes three switches, which means that the voltage gain can reach three.
Reference [16] has presented a very effective method that allows the switch count in high-gain
series-parallel converters to be decreased. However, the converter presented in Reference [16] does not
have a common input and output negative point, and the output voltage is asymmetrically divided.
In Reference [17], a converter that combines Dickson-based and ladder SC converter concepts has
been presented. In the proposed topology, high-voltage-gain is achieved with limited voltage and
current stresses on the switches. The Dickson-based SC concept has also been used in the converter
presented in Reference [18] that is composed of an SC part and an interleaved boost converter.
The converter achieves a very high-voltage-gain with the output voltage regulation and soft switching
operation, using four switches and seven diodes. In Reference [19], high-voltage-gain is achieved
in a converter with switched-capacitor and switched-inductor networks. A concept of a family of
converters composed of a boost stage and switched-capacitor-inductor cells has been presented in
Reference [20]. This increases the voltage gain of the converter significantly with favorable voltage
stress levels, efficiency, and component count. References [21–24] have demonstrated high-voltage-gain
multilevel converters based on typical multilevel converter concepts. When we take into consideration
the number of the utilized components and the reached voltage gain, the multilevel SC converters
can be more beneficial in comparison to the SCVMs. The converter described in Reference [21] is
based on a modified classic multilevel SC topology; however, it is composed of a significant number of
switches. In Reference [22], an improvement in the operation of the multilevel resonant SC converter
(MRSCC) has been proposed. The MRSCC makes it possible to operate with high-voltage-gain and
limited voltage stress on the switches with the ability of bi-directional energy transfer. In Reference [23],
a multilevel structure has been achieved in the converter with two switches and circuits composed
of diodes and capacitors. The converter can operate with zero voltage switching (ZVS) and voltage
regulation. In Reference [24], a DC-DC bidirectional SC converter has been presented that improves
the total device power ratings in comparison to the multilevel modular capacitor clamped converter
(MMCCC) and well-established flying-capacitor converters.
One of the major issues of the SC converters is a large number of switches used in the topology.
This problem can be solved by the concepts of cascaded or series systems composed of SC units [25,26]
or by new concepts of topologies [16,27,28]. In the concept for the switch count reduction presented in
Reference [26], a high-power converter has been analyzed in a multi-section topology. The converter is
composed of the typical SCVM sections separated by LC filters. According to this concept, a significant
reduction in the number of switches has been achieved. However, an increased number of passive
components are utilized as LC filters between the sections in the multi-section converters [26].
The problem of the switch count reduction in an SCVM converter has been analyzed in Reference [29],
where the charging of the switched capacitors is controlled by a single switch. For high-voltage-gain,
the system is significantly simplified. The design of such a cost-effective converter should assume a
much higher current stress of the switch that controls the charging of the switched capacitors.
The converters proposed in this paper are optimized towards a low count of transistors (and they are
called Low Count of Transistors Switched Capacitor Voltage Multipliers—LCSCVMs). The basic concept
of the topology and operation assumes that every second cell has no transistors whatsoever, but the
utilization of all the switched capacitors remains possible, and the effect of voltage gain is comparable
to that of the multipliers (SCVMs) presented in Reference [13,14]. Furthermore, the optimized concept
is introduced into the cost-effective topology presented in Reference [29], which gives a new relevant
converter. Taking into consideration the count of switches, SC converters, such as the SCVM [20],
may not be in competition with the LLC converters or other established topologies. However,
the concepts proposed in this paper demonstrate a development of the SC topologies towards a
Energies 2020, 13, 5657 3 of 22
significant decrease in the number of switches. One of the converters presented in this paper requires
only three switches, which is below the number of transistors used in a full-bridge LLC converter.
Other advantages of the SC converters, such as: high gain, high power density and low weight
(no transformer or bulky choke), fast dynamic response [3], ability for operation in high temperature
(no ferrites), and simple control, can make them an alternative solution for existing topologies intended
for high-voltage-gain non-isolated DC-DC conversion. SC-based topologies can be suitable for the
miniaturization of converters that can be applied in emerging power electronics applications, such as
wearable technology.
For the operational parameters of an SC converter, the switching strategy applied for a given
topology can be essential, which has been demonstrated in Reference [14]. For the optimization
purposes analyzed in this paper, various switching strategies are proposed for the new topologies.
This makes it possible to determine the advantages of the presented topologies, also taking into
consideration a variety of qualities, other than the count of switches.
The proposed converters are nearly pure switched-capacitor circuits, where a vast majority of
energy is transferred via capacitors rather than inductors. The resonant inductors are used to achieve
oscillatory currents. The inductors can be designed as air chokes, which reduces the weight of the
converters and allows them to work in higher temperatures. However, another trend in the development
of very high-voltage-gain converters can be observed in the literature. The concept presented in
Reference [30] is based on coupled inductor (CI) converters that achieve good parameters such as
voltage ratio, efficiency, low number of switches, or low voltage stress on switches. Notwithstanding,
such converters use chokes and, therefore, differ from the presented SC-based concept regarding
admissible ambient temperature of operation, weight, and volume. The design comparison can be
analyzed in particular case studies.
In this paper, the qualities introduced by the new topologies will be compared with those of a
classic SCVM and of other converters discussed in recently published papers.
The paper is organized as follows. Section 2 demonstrates two proposed topologies of the SC
converters and presents the principles of their operation. For both converters, switching strategies are
analyzed. The discussion is supported by the results of computer simulations of their operation in five
cases of switching strategies. Moreover, with the use of the simulation results, a number of parameters
of the converters operating under various switching strategies are compared as well. Section 3 contains
efficiency models of the proposed converters that demonstrate their efficiency as a function of their
parameters. Section 4 presents the laboratory setup and the experimental verification of its operation,
including the efficiency of the converter. All the research results are concluded in Section 5.
2. Operating Principle of the Converters

The operating principle of the converters in Figure 1 is similar to that of other SC multipliers, and is
based on the charging and discharging of the switched capacitors in consecutive stages (time intervals).
However, various switching strategies can be proposed for the new converters, which creates differences
in their parameters. In the SCVM, as well as in the case of the converters proposed in this paper,
the switched capacitors are recharging in resonant circuits composed of a switched capacitor and
a low-volume resonant inductor. This creates ZCS (zero current switching) operating conditions,
and limits the current flow between the capacitors and the voltage source connected in parallel.
Energies 2020, 13, 5657 4 of 22
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(a) (b)
(a)
(a) (b)(b)
Figure 1. Proposed new resonant converters with low count of switches and common input/output
Figure 1. Proposed new resonant converters with low count of switches and common input/output
Figure negative point:
Figure 1. Proposed
Proposed new (a) LCSCVMa,
new resonant
resonant (b) LCSCVMb.
converters
converters with
with low
low count
count of switches and common input/output
input/output
negative point: (a) LCSCVMa, (b) LCSCVMb.
negative
negative point: (a) (a) LCSCVMa,
LCSCVMa, (b) (b) LCSCVMb.
LCSCVMb.
The main difference between the topology of the proposed converters and the classic SCVMs is
The main difference between the topology of the proposed converters and the classic SCVMs is
that in
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SCVM. due
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(Figure 1a) offers a larger number of strategies than the LCSCVMb (Figure 1b),
1 3 The basic switching strategies can
due to the possibility of independent control of switches S1 and S3. The basic switching strategies can
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be composed
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to the possibility of 5independent
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2.1. Switching Strategy Concepts for the LCSCVMa
be composed 2.1. of
Switching
2, 3, orStrategy
5 stages.Concepts for the LCSCVMa
2.1. Switching Strategy
Table 1 Concepts for theswitching
presents three LCSCVMa strategies for the LCSCVMa, and Figures 2–5 depict the
Table 1 presents three switching strategies for the LCSCVMa, and Figures 2–5 depict the
corresponding
2.1. Switching simulation
Strategy Concepts waveforms.
for the LCSCVMa
Table corresponding
1 presents three switching
simulation strategies for the LCSCVMa, and Figures 2–5 depict the
waveforms.
corresponding simulation
Table 1 presents three waveforms.
Table 1.switching strategies
Switching strategy forofthe
concepts LCSCVMa,
the LCSCVMa. and
States FiguresS1–S
of switches 2–5
4. depict the
Table 1. Switching strategy concepts of the LCSCVMa. States of switches S1–S4.
corresponding simulation waveforms.
The Concept for Switching Strategy Description—Stages of Charge Transfer in the
The Concept for Switching
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LCSCVMa. States of of Charge Transfer in the
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Description—Stages Statesofof switches
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Transfer
all the switched. thecapacitors
Converter
1.Simultaneous charging of all the switched capacitors
The Concept for Switching Strategy 2. Discharging
1.Simultaneous
Description—Stages of the capacitor
charging of all
of Charge thethat is
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Transfer nearest
capacitors
in theto the
2. Discharging of the capacitor that is the nearest to the
2. Discharging
source (C1) to theof the capacitor
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branch the
2) nearest to the source
of LCSCVMa source Converter
(C1) to the internal (Cbranch (C2)
Strategy C1 3.(CCharging
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4.4.Discharging
Discharging CC11 to to theinternal
internal branch (as (as
in 2)in 2)
4.(C
source5. Discharging
1) to the internal
C1 tothe
the internal branch
branch (as in 2)
5.Discharging
Discharging andCbranch
CC22 and C3 3totothe (C 2)
theoutput
output
5. Discharging C2 and C3 to the output
Strategy C1 3. Charging C1, and discharging C2 and the next SC
capacitor (C3) to the output
1.1.Simultaneous chargingofof
1. Simultaneous charging
Simultaneous charging allall
of thethe
all the
switched
switched
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capacitors
capacitors
Strategy
Strategy C2 C2 4. Discharging C1 toCCthe
2.2.Discharging
Discharging 11 to
to internal
the
the internal
internal branch
branch (as
branch
(C2(C
) in
2 ) 2)
Strategy C2 2.3.Discharging C 1 to the internal branch (C2)
5. Discharging C2 and
Discharging
3. Discharging C
CC22 and3 to
and 3 the
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(C11and
(C and C
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Strategy
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3. Discharging C2 and discharging of all the switched
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Strategy C3 2.2.Simultaneous
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(C2)
1. Simultaneous charging of all the switched capacitors
(C1 and C3)
Strategy C3 2. Simultaneous discharging of all the switched
capacitors and charging the internal branch capacitor
(C2)
Energies 2020, 13, 5657 5 of 22
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(a)
(a) (b)
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Figure Steady-state
Steady-state operation
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operation ofofLCSCVMa
of the the LCSCVMa
the LCSCVMa
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converter under switching
under
under switching switching
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strategy C1: (a)
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simulationsoftware.
simulation
software.
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4. Steady-state operation
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and
and voltages (in volts) on capacitors C1 , C2 , and C3 . (b) Spectrum of the input current, and currents
currents
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switched capacitors
capacitors and
and output
output capacitor.
capacitor. The The results
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voltages(in (involts)
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theinput
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and
and voltages (in volts) on capacitors C1 , C2 , and C3 . (b) Spectrum of the input current, and currents
of switched capacitors and output capacitor. The results were obtained with the use of ICAP/4
Energies 2020, 13, 5657 7 of 22
To characterize the switching strategies, Table 1 contains the idealized control logic waveforms
of the transistors (signals S1 to S4 ), as well as the description of the particular operation stages.
Dead times have been neglected in Table 1, but they have been taken into account in the simulations
and experiments. Capacitor C2 (Figure 1) is not referred to as a switched capacitor. The maximum
switching frequency (strategy C3) is defined as:
1
fSmax = (1)
2Tpulse
where Tpulse is the sum of the duration time T0 /2 of a single current pulse of any transistor and the
dead time td (any period of time denoted as 1–5 in Table 1),
1 √
T0 = = 2π LC (2)
f0
and L = L1 = L2 = L3 , C = C1 = C2 = C3 (Figure 1).

All the simulation results were obtained for the following parameters: Uin = 50 V, Ln = 620 nH,
Cn = 1.47 µF, f 0 = 166.7 kHz, Tpulse = 4.2 µs (f Smax = 119 kHz), Cout = 100 µF, Pout = 200 W (n = 1, 2, 3).
A resistance of 100 mΩ has been inserted into each branch as an equivalent to parasitic resistances.
The time period Tpulse , as well as the duty cycle of the switching signals of the transistors, remain
constant in each switching strategy. The selection of the switching frequency depends on the power of
the converter, achievable resonant inductance, and switching losses [13]. This parameter, as well as
the others, can be fixed in the following steps. In the ZCS mode, the SC converters’ transistors do not
operate in the ZVS mode, and during their turn-ons, the output charge is shorted (Coss losses). The limit
of Coss losses determines the switching frequency of the transistors taking into consideration their type
and voltage stresses. The oscillation frequency should be nearly equal to the switching frequency to
minimize conduction losses [13]. This frequency depends on the product of Ln Cn , and allows to select
Cn for a known value of Ln . The maximum power of the converter depends on capacitance Cn and the
switching frequency [13], and it should be higher than or equal to the rated power for the selected
parameters. The simulation results presented in this section have been obtained with the use of ICAP/4
simulation package based on the IsSpice4 simulator.
2.1.1. Simulation Results of the Switching Strategy C1

Figure 2 presents steady-state simulation waveforms of the LCSCVMa controlled according to
strategy C1. From all the results, it can be seen that the switched capacitors are recharged by oscillatory
currents and each stage of the switching is longer than the half-period of the oscillations.
The entire switching cycle is composed of five stages (Table 1). According to the principle of
operation, turning on switches S1 and S3 involves the charging of the switched capacitors C1 and C3 .
Capacitor C3 is being charged from capacitor C2 of the internal branch whose voltage is going down
in this stage. The diode D2 remains turned off, as uC2 > uC1 and uC2 > uin (Figure 2). In the next
stage, switch S2 is turned on, and capacitor C2 is being charged from the source uin and capacitor C1
connected in series with it. The charging of the output capacitor, from capacitors C2 and C3 connected
in series, occurs in the next stage when the switch S4 is turned on. At the same time, capacitor C1
is being charged from the source. In the next two stages, capacitor C2 and capacitor Cout are being
charged, consecutively.
The advantage of this switching strategy is reducing the number of the performed switching
operations, which leads to switching losses limitation. In three of five stages of the switching period,
only one switch is affected.
The input current has various values in each switching state, which is a drawback of this strategy.
Therefore, a low-frequency component f S = f ac-in = f Smax /2.5 appears in current iin , as well as in all
other currents and voltages in the circuit. Using this kind of switching requires using a large input
Energies 2020, 13, 5657 8 of 22
filter and a large output capacitor. From the standpoint of the components’ volume and input current
filtering, this strategy is not favorable.
The output voltage used for the voltage gain calculation in relation (3) has been measured as the
average value of the waveform presented in Figure 3 together with the output current. Further results,
given in Equations (4)–(7), were obtained in the same manner.
In this strategy, the measured average value of the output voltage of the converter equals
Uout = 178 V. For the input voltage of the converter Uin = 50 V (maintained by the voltage source in
simulations), the voltage gain of the converter under switching strategy C1 equals:
Uout 178.0
GUC1 = = = 3.56 (3)
Uin 50.0

Figure 4 presents simulation waveforms in the LCSCVMa controlled according to strategy C2.
In this strategy, each switching period consists of three stages. The first two switching stages correspond
to those in strategy C1. In the third stage, only transistor S3 is on. The last two stages of strategy
C1 do not occur here, and capacitor C2 is charged and discharged only once in a switching period.
The number of the switching operations is lower in comparison to that in strategy C1. The spectrum
of currents and voltages shows more favorable qualities in strategy C2 versus C1, as the 50 kHz
components are not present (the lowest frequency is 75 kHz).
Uout = 177 V. For Uin = 50 V, the voltage ratio is
Uout 177.0
GUC2 = = = 3.54 (4)
Uin 50.0

Figure 5 presents simulation waveforms in the LCSCVMa controlled according to strategy C3.
In this strategy, there are only two stages. In the first stage, the charging of the switched capacitors
takes place (switches S1 and S3 are turned on). During the second stage, the output capacitor and C2
are being charged (with switches S2 and S4 turned on).
In this strategy, each switch operates with a much higher frequency than in the case of strategies
C1 and C2. This brings an improvement in the spectrum of the currents and voltages, as the lowest
frequency is 120 kHz. It is favorable from the passive components volume optimization standpoint.
In strategy C3, the measured average value of the output voltage of the converter equals
Uout = 185 V, and for Uin = 50 V, the voltage ratio is
Uout 185.0
GUC3 = = = 3.7 (5)
Uin 50.0
2.2. Switching Strategy Concepts for the LCSCVMb

The LCSCVMb converter is simpler than the LCSCVMa, and contains three switches only. There
is only one stage of charging the switched capacitors, realized by the switch S1 , and two possible
stages of discharging them, controlled by switches S2 and S3 . This creates two switching strategies for
this converter, which are presented in Table 2. Figures 6 and 7 depict simulation waveforms of the
LCSCVMb controlled according to these strategies.
Table 2. Switching
Energies 2020, 13, x strategy
FOR PEERconcepts
REVIEW of the LCSCVMb. States of switches S1, S2, and S4. 9 of 22
Energies 2020, 13, x FOR PEER REVIEW
Energies 2020, 13, 5657 9 of 22 9 of 22
The Concept for Switching Table 2. Switching strategy concepts of the LCSCVMb. States of switches S1, S2, and S4.
Description—Stages of Charge Transfer in the Converter
Strategy of LCSCVMb Table 2. Switching strategy concepts of the LCSCVMb. States of switches S1, S2, and S4.
The Concept for Switching
Similarly
Table 2. Switching strategy
The Concept to of
concepts strategy
the C2 for the
Description—Stages
LCSCVMb. LCSCVMa,
States of Chargestrategy
of switchesTransfer C4 gives
in S
S1 , S2 , and the the
4 . Converter
Strategy of for Switching
LCSCVMb
following Description—Stages
characteristic in the of Charge Transfer in the Converter
LCSCVMb:
Strategy Strategy
The Concept for Switching of LCSCVMb
of LCSCVMb Similarly to strategy C2 for
Description—Stages ofthe LCSCVMa,
Charge Transfer strategy C4 gives the
in the Converter
Strategy C4 1. Simultaneous charging
Similarly
following to of allC2
strategy
characteristic
the forswitched
in theLCSCVMb:
the LCSCVMa, capacitors
strategy C4 gives the
Similarly to strategy C2 for the LCSCVMa, strategy C4 gives
Strategy C4 2. Discharging C 1 to the
following
1. Simultaneous internal
characteristic
the followingcharging
branch
in the (C 2)
LCSCVMb:
of allinthe
characteristic the switched
LCSCVMb:capacitors
Strategy C4
Strategy C4 3. Discharging
2. C1.2 and
1. Discharging
SimultaneousC3 to
Simultaneous the
C1chargingoutput
to charging
the of of
allall
internal the theswitched
branch (C2) capacitors
switched capacitors
2. 2. Discharging
Discharging C
Similarly to3.strategy C3 for2 the1 C
to to
the the internal
internal
and LCSCVMa,
1 C3 to the output branch
branch (C(C2)2 )C5 gives the
strategy
3. Discharging
following characteristic
Similarly inCthe
2 and
to strategy C3for
to the output
LCSCVMb:
C3 LCSCVMa, strategy C5 gives the
Similarly to strategy C3 for the LCSCVMa, strategy C5 gives
Strategy C5 Similarly
following
1. Simultaneous to strategy
characteristic
charging of all C3
the forswitched
in theLCSCVMb:
the LCSCVMa, strategy C5 gives the
capacitors
the following characteristic in the LCSCVMb:
Strategy C5
Strategy C5 following
1. 1. characteristic
Simultaneous
Simultaneouscharging inof
charging theall
of LCSCVMb:
the
all theswitched
switched capacitors
capacitors
2. Simultaneous discharging of all the switched capacitors and
Strategy C5 1. Simultaneous
2. 2. Simultaneous charging
discharging of all
discharging the
ofofall switched
allthe
theswitched
switched capacitors
capacitors
capacitors and
and
charging the internal branch (C 2)
charging the internal branch (C )
2. Simultaneous
charging discharging
the internal branch of
(C2all
) 2 the switched capacitors and
charging the internal branch (C2)
(a) (b)
(a) (b)
Figure 6. Steady-state operation of the LCSCVMb converter under switching strategy C4: (a)
(a)
Figure 6. Steady-state
(b) switching strategy C4: (a)
Waveforms of the input operation of the currents,
current, inductor LCSCVMb andconverter
the currentunder
of the output diode (in amperes).
Waveforms
(b) Voltages
Figure 6.6.Steady-state
Steady-state of the
(in
operation input
volts) oncurrent,
ofLCSCVMb inductor
capacitors
the LCSCVMb C1, C2,currents,
and C .
converter
3 and
The the current
results were of the output
obtained
under switching withdiode
strategy (in of
theC4:
use amperes).
(a)ICAP/4
Figure operation of the converter under switching strategy C4: (a) Waveforms
(b) Voltagessoftware.
simulation (in volts) on capacitors C1, C2, and C3. The results were obtained with the use of ICAP/4
Waveforms
of of the input
the input current, current,
inductor inductor
currents, andcurrents,
the current andofthe
thecurrent
outputofdiode
the output diode (in
(in amperes). (b)amperes).
Voltages
(b) Voltages
(in volts) on(in volts) on capacitors
capacitors C1, C
C1 , C2 , and C23,. and C3. results
The The results
werewere obtained
obtained with
with thetheuse
useof
of ICAP/4
ICAP/4
software.
Energies 2020, 13, 5657 10 of 22
(a) (b)
Figure7.7.Steady-state
Figure Steady-state operation
operation ofLCSCVMb
of the the LCSCVMb converter
under switching strategy
strategy C5: C5: (a)
(a) Waveforms
Waveforms of the input current, inductors currents, and the current of the output diode (in
of the input current, inductors currents, and the current of the output diode (in amperes). (b) Voltagesamperes).
(b) Voltages
(in volts) on(in volts) on capacitors
capacitors C1, C23,. and
C1 , C2 , and C3. results
The The results
werewere obtained
obtained with
with thetheuse
useofof ICAP/4
ICAP/4
2.2.1.
2.2.1. Simulation
Simulation Results
Results of
of the
the Switching
Switching Strategy
Strategy C4
C4
Figure
Figure 66 presents
presents simulation
simulation waveforms
waveforms of of the
the LCSCVMb
LCSCVMb controlled
controlled according
according toto strategy C4.
strategy C4.
The
The current
currentandandvoltage
voltagewaveforms
waveformsin instrategy
strategyC4
C4are
arenearly
nearlyidentical
identicalwith
withthose
thoseininstrategy
strategyC2.
C2.
In
In this strategy, the measured average value of the output voltage of the converter equalsequals
this strategy, the measured average value of the output voltage of the converter Uout =
U
172.1=
out V,172.1
whichV, which
yields yields
(for Uin(for in = 50 V):
= 50UV):
Uout 172.1
172.1
GUC4= = = = = 3.44
= 3.44 (6)
(6)
Uin 50.050.0

Figure 7 presents simulation waveforms for the LCSCVMb controlled according to strategy C5.
Figure 7 presents simulation waveforms for the LCSCVMb controlled according to strategy C5.
The current and voltage waveforms of the strategy C5 are nearly identical with those in strategy C3.
The current and voltage waveforms of the strategy C5 are nearly identical with those in strategy C3.
In this strategy, the measured average value of the output voltage of the converter equals Uout =
Uout = 181.4 V. For Uin = 50 V, the voltage ratio is:
181.4 V. For Uin = 50 V, the voltage ratio is:
Uout 181.4
181.4
GUC5= = = = = 3.63
= 3.63 (7)
(7)
Uin 50.050.0
2.3. Comparison among the Topologies and Switching Strategies

2.3. Comparison among the Topologies and Switching Strategies
In Sections 2 and 2, a significant number of waveforms are presented for the particular strategies.
In Subsections 2.1 and 2.2, a significant number of waveforms are presented for the particular
The differences in the waveforms of the currents and voltages are clear, but to compare the concepts of
strategies. The differences in the waveforms of the currents and voltages are clear, but to compare
the converters and the switching strategies, the following parameters will be taken into consideration
the concepts of the converters and the switching strategies, the following parameters will be taken
and presented in charts:
into consideration and presented in charts:
• Number of components,
• Voltage gain,
Energies 2020, 13, 5657 11 of 22
• Number of components,
• Voltage gain,
• The lowest frequency in the input current (f ac_in ),
• The lowest frequency in the output current (f ac_out ),
• Voltage pulsation on capacitors (UC1p-p , UC2p-p , UC3p-p ),
• rms values of inductor currents (IL1_rms , IL2_rms , IL3_rms ),
• Maximum values of inductor currents (IL1_max , IL2_ max , IL3_ max ),
• Symmetry of inductor currents (Sym_iL ).
The data are

•
presented in Table 3, where the parameters of the SCVM (on the basis of Reference [14]
The lowest frequency in the input current (fac_in),
for an appropriate
• strategy)
The are included
lowest frequency as current
in the output well. (fac_out),
• Voltage pulsation on capacitors (UC1p-p, UC2p-p, UC3p-p),
• rms values of inductor currents (IL1_rms, IL2_rms, IL3_rms),
Table 3. Major
•
parameters comparison among the parameters of LCSCVMa and LCSCVMb converters
Maximum values of inductor currents (IL1_max, IL2_ max, IL3_ max),
in the tests of
• 200 W operation.
Symmetry of inductor currents (Sym_iL).
The data are presented in Table 3, where the parameters of the SCVM (on the basis of Reference
[14] for Parameter
LCSCVMa Strategy
an appropriate strategy) are included as well.
LCSCVMb Strategy
SCVM
C1 C2 C3 C4 C5
Table 3. Major parameters comparison among the parameters of LCSCVMa and LCSCVMb
No. of switches
converters in the tests of 200 W 4
operation. 4 4 3 3 6
No. of diodes 4 4 4 5 5 4
LCSCVMa Strategy LCSCVMb Strategy
Uout , V Parameter 178.0 177.0 185.0 172.1 181.4
SCVM 191.2
C1 C2 C3 C4 C5
TS , µs 21.0 12.6 8.4 12.6 8.4 8.4
No. of switches 4 4 4 3 3 6
f ac_in , kHz 47.6 79.4 238.1 79.4 238.1 238.1
No. of diodes 4 4 4 5 5 4
f ac_out , kHz Uout, V 47.6 178.0 79.4177.0 119.0
185.0
79.4 181.4 119.0
172.1 191.2
119.0
UC1p-p , V TS, μs 21.02 21.0 19.4112.6 12.48.4 19.8
12.6 8.4 12.68.4 5.98
UC2p-p , V fac_in, kHz 21.61 47.6 19.4179.4 6.54
238.1 19.8 238.1 6.65
79.4 238.1 5.98
UC3p-p , V fac_out, kHz 16.08 47.69.7 79.4 6.18
119.0 9.92 119.0 6.29
79.4 119.0 5.98
IL1_rms , A UC1p-p, V 6.75 21.02 7.2519.41 5.65
12.4 7.41 12.6 5.75
19.8 5.98 2.73
IL2_rms , A UC2p-p, V 6.22 21.61 6.2819.41 2.92
6.54 6.42 6.65 2.97
19.8 5.98 2.73
IL3_rms , A UC3p-p, V 4.11 16.08 3.639.7 2.756.18 9.92
3.71 6.29 2.80 5.98 2.73
IL1_max , A IL1_rms, A 16.1 6.7514.87.25 9.46 5.65 7.41
15.1 5.75 9.60 2.73 4.57
IL2_ max , A IL2_rms, A 13.2 6.2214.86.28 5.01 2.92 6.42
15.2 2.97 5.09 2.73 4.57
IL3_ max , A IL3_rms, A 12.3 4.117.433.63 4.74 2.75 3.71
7.56 2.80 4.80 2.73 4.57
I L1_max, A
Symmetry of current iL1 no 16.1
yes 14.8 9.46
yes 15.1yes 9.60 yes4.57 yes
IL2_ max, A
Symmetry of current iL2 no 13.2no 14.8 yes 5.01 15.2
no 5.09
yes4.57 yes
IL3_ max, A 12.3 7.43 4.74 7.56 4.80 4.57
Symmetry of current iL3 no yes yes yes yes yes
Symmetry of current iL2 no no yes no yes yes
Figures 8–10 present a comparison between the values of parameters of the discussed converters,
Figuresparameter
and the corresponding 8–10 present a of
comparison between the values of parameters of the discussed converters,
the SCVM.
and the corresponding parameter of the SCVM.
Figure 8. Comparison of converters’ parameters under strategies C1–C5: Ratios of number of switches
Figure 8. Comparison of converters’
(axis 1) and number of diodes (axisparameters under
2) to those in SCVM strategies
(on the basis of dataC1–C5:
in Table 3). Ratios
Quantity of number of
switches (axis 1) and number of diodes (axis 2) to those in SCVM (on the basis of data in Table 3).
Quantity proportional to undesired output voltage decrease: 0.06·(200 – Uout) (axis 3). Ratios of
the lowest frequencies in the input and output current: 0.4·f ac_in SCVM/f ac_in (axis 4), 0.4·f ac_out
SCVM/f ac_out (axis 5).
proportional to undesired output voltage decrease: 0.06·(200 – Uout) (axis 3). Ratios of the lowest
proportional to undesired output voltage decrease: 0.06·(200 – Uout) (axis 3). Ratios of the lowest
Energies
frequencies
2020, 13, 5657
in the input and output current: 0.4·fac_in SCVM/fac_in (axis 4), 0.4·fac_out SCVM/fac_out (axis 5).
frequencies in the input and output current: 0.4·fac_in SCVM/fac_in (axis 4), 0.4·fac_out SCVM/fac_out (axis 5).12 of 22
(a) (b)
(a) (b)
Figure 9. Ratios of the following parameters of strategies C1–C5 (axes 1–5): (a) Peak-to-peak voltages
Figure
Figure 9. Ratios
Ratios of
of the
the following
following parameters
parameters of
of strategies
strategies C1–C5 (axes 1–5):
C1–C5 (axes 1–5): (a)
(a) Peak-to-peak
Peak-to-peak voltages
voltages
across9.capacitors C 1–C3, (b) rms and maximum values of currents in inductances L1–L3. The results are
across capacitors C –C
C1 –C , (b) rms and maximum values of currents in inductances L –L . The results are
across
basedcapacitors 3. and maximum values of currents in inductances L1 –L3 . The results are
, (b) rms
1 3 1 3
on the data in 3Table
based on the data in Table
based on the data in Table 3. 3.
(a) (b)
(a) (b)
Figure10.10.Ratios
Ratios ofthe
the followingparameters
parameters (strategiesC1–C5)C1–C5)totothe
the correspondingparameter
parameterofof
Figure
Figure 10. Ratios ofof the following
following parameters (strategies
(strategies C1–C5) to the corresponding
corresponding parameter of
SCVM: (a) Peak-to-peak voltages across capacitors C 1–C3, (b) rms (axes 1–3) and maximum values of
SCVM: (a)
SCVM: (a) Peak-to-peak
Peak-to-peak voltages
voltages across capacitors C
across capacitors –C33,, (b)
C11–C (b) rms
rms (axes
(axes 1–3)
1–3) and
and maximum
maximum values
values of
of
currentsinin
currents inductances
inductances L L–L
1–L3 (axes 4–6). The results are based on the data in Table 3.
(axes 4–6). The results are based on the data in Table 3.
currents in inductances L11–L33 (axes 4–6). The results are based on the data in Table 3.
InInFigure
Figure8,8,the
thecoefficients
coefficients0.06 0.06and
and0.40.4are
areused
usedrespectively,
respectively,totobetter bettervisualize
visualizethetheundesired
undesired
In Figure 8, the coefficients 0.06 and 0.4 are used respectively, to better visualize the undesired
outputvoltage
output voltagedecrease
decreaseininregard
regardtotothe thetheoretical
theoreticalvalue
valueofof200 200V,V,and
andthe
thelowest
lowestfrequencies
frequenciesininthethe
output voltage decrease in regard to the theoretical value of 200 V, and the lowest frequencies in the
input and output current of the discussed converters
input and output current of the discussed converters compared to compared to those in the SCVM. In
In each case,a
each case,
input and output current of the discussed converters compared to those in the SCVM. In each case, a
a lower
lower value on the graph is better.
lower value on the graph is better.
Fromthe
From the chart
chart presented
presented in in Figure
Figure 9a,9a, it follows
it follows thatthat
the the lowest
lowest peak-to-peak
peak-to-peak (p-p)(p-p) voltages,
voltages, in allin
From the chart presented in Figure 9a, it follows that the lowest peak-to-peak (p-p) voltages, in
all the strategies, are equal the voltage across capacitor C
the strategies, are equal the voltage across capacitor C3 . Moreover, the strategies C3 and C5 showshow
3 . Moreover, the strategies C3 and C5 the
all the strategies, are equal the voltage across capacitor C3. Moreover, the strategies C3 and C5 show
the lowest
lowest p-p voltages
p-p voltages for allfor allinternal
the the internal capacitors
capacitors (C1 –C(C 1–C
). 3). Figure
Figure 9b 9b demonstrates
demonstrates that that
the the currents
currents of
the lowest p-p voltages for all the internal capacitors (C13–C3). Figure 9b demonstrates that the currents
of inductor L are the lowest, and the strategies with the lowest inductor
inductor L are the lowest, and the strategies with the lowest inductor currents are C3 and C5.
3 currents are C3 and C5.
of inductor3 L3 are the lowest, and the strategies with the lowest inductor currents are C3 and C5.
The same qualities are visible in charts presented in Figure 10, which clearly demonstrate that the
parameters of strategy C4 are nearly the same as those of strategy C2. The same refers to strategies C5
and C3.
The same qualities are visible in charts presented in Figure 10, which clearly demonstrate that
the parameters of strategy C4 are nearly the same as those of strategy C2. The same refers to strategies
C5 and C3.
Energies 2020, 13, 5657 13 of 22
The LCSCVMa and LCSCVMb converters can be further extended to units of higher voltage
gain, similarly as in the case of the converters presented in References [13,22,25,26,29]. Taking into
consideration
The LCSCVMa the number of switchesconverters
and LCSCVMb and diodes, as be
can well as the extended
further frequencytoofunits
the input current,
of higher both
voltage
the proposed
gain, similarlyconverters are very
as in the case attractive
of the for presented
converters high-voltage-gain (Table[13,22,25,26,29].
in References 4). It should be noticed that
Taking into
the converter extension is very effective in the case of the LCSCVMb concept. For voltage
consideration the number of switches and diodes, as well as the frequency of the input current, both the gain G U =
8, it requires only four switches, which is an excellent result in comparison to

proposed converters are very attractive for high-voltage-gain (Table 4). It should be noticed that theother pure SC
converters.extension
converter Other parameters such asin
is very effective voltage stresses
the case of theon the switches
LCSCVMb can beFor
concept. found in the
voltage literature.
gain GU = 8,
it requires only four switches, which is an excellent result in comparison to other pure SC converters.
OtherTable 4. Comparison of the number of switches and diodes, and the lowest frequency of the input
parameters such as voltage stresses on the switches can be found in the literature.
current in selected topologies versus the voltage gain. Ref. = Reference.
Table 4. Comparison of the number of switches and diodes,
Parameter and the lowest frequency of the input
Toplogy
current in selected topologies versus the voltage gain. Ref. = Reference.
Gain LCSCVMaLCSCVMbRef. [13]Ref. [22]Ref. [16]Ref. [25]Ref. [26]Ref. [27]
Parameter 4 4 (4) 3 (5) 6 (4) 8 Toplogy
(0) - 8 (0) 4 (4) 4 (6)
No. of switches
Gain7 -
LCSCVMa LCSCVMb - Ref. 12
[13] (7) Ref.14[22](0) Ref.7[16]
(5) Ref. [25]
- Ref.-[26] 7Ref.
(12)[27]
(and diodes) 48 4 (4) 3 (5) 6 (4) 8 16
(0) (0) - - 8 (0)(0) 4 (6)
(4) 4 (6)
No. of switches 6 (6) 4 (7) 14 (8) 12 6 8 (14)
7 - - 12 (7) 14 (0) 7 (5) - - 7 (12)
(and diodes)
fiin_min /fSmax for all gains8 6 (6) 4 (7) 14 (8) 16 (0) - 12 (0) 6 (6) 8 (14)
1 1 0.5 1 1/4 1 1 0.5
(fSmax/f—in
f iin_min Smax (1))
for all
1 1 0.5 1 1/4 1 1 0.5
gains(f Smax —in (1))
3. Efficiency Model of the LCSCVM Converters

3. Efficiency Model of the LCSCVM Converters
The analysis below concerns the LCSCVMa operating under the strategy C3 (Table 1) and
The analysis
LCSCVMb below
operating concerns
under the LCSCVMa
the strategy operating
C5 (Table 2). under
In both cases, the are
there strategy C3 (Table
two stages 1) and
of operation.
LCSCVMb operating
Figure 11 depicts the under
currentthe strategy
paths C5LCSCVMa.
in the (Table 2). InInboth
the cases, there are
LCSCVMb, the two stages
switch of operation.
S1 conducts the
Figure depicts the current paths in the LCSCVMa. In the LCSCVMb, the switch S
sum of currents iL1 and iL3 in the stage 1, whereas the current paths in the stage 2 are 1the same asthe
11 conducts in
sum of currents iL1 and iL3 in the stage 1, whereas the current paths in the stage 2 are the same as in
the LCSCVMa.
the LCSCVMa.
(a) (b)
Figure 11. Current paths in the LCSCVMa: (a) in the stage 1 and (b) in the stage 2.
Assuming
Assuming ideal
ideal power
power electronic
electronic switches,
switches,and
andaa constant
constantvalue
valueofof the
the input
input (U
(Uinin) and the output
(Uout
out))voltage,
voltage,as
aswell
wellas
asneglecting
neglectingparasitic
parasiticresistances
resistances and
and voltage
voltage drops
drops across
across the
the power
power electronic
electronic
devices, the currents in the stage 1 (Figure
(Figure 11a)
11a) can
can be
be described
described as
as follows:
follows:
1 (t()t=) iC=
U U in
1 (t ) = in
−−UU C11
C11 sinω0t = I1m sinω0t
iL1 (t) = iLiC1 ρ sin ω0 t = I1m sin ω0 t (8)
(8)
ρ
U − U C11 I
iL 3 (t ) = iC 3 (t ) =Uinin− UC11 sin ω0t = 1mI1m
sin ω0t (9)
iL3 (t) = iC3 (t) = 2ρ sin ω0 t =2 sin ω0 t (9)
2ρ 2
(t ) i=C2iC(2t)(t )== −−iiLL33((t t))
iL2 (ti)L2= (10)
(10)
With the characteristic impedance and the angular resonant frequency given by
With the characteristic impedance and the angular resonant frequency given by
p √
ρ = L/C, ω0 = 1/ LC (11)
Energies 2020, 13, 5657 14 of 22
where UC11 is the initial voltage across capacitor C1 , and I1m and I2m /2 are the current amplitudes.
Equation (8) presents the current of a typical series LC circuit supplied from a voltage source,
and Equation (9) was obtained also taking into account the initial values of the capacitor voltages.
The values of the passive components depend on the assumed nominal power (Pnom ), switching
frequency (f S ), and the volume of the resonant inductor. The values of time Tpulse (1), and finally
T0 (2) and ω0 (11), are assumed taking into account the limit of the switching losses in the converter.
The capacitance of the switched capacitors is determined by the charge required to be transferred in
a single switching pulse. The maximum power of the SCVM-type converter is achieved when the
switched capacitors are fully discharged in a switching cycle (and then charged to the voltage equal to
2Uin ). This determines the minimum capacitance, which in the SCVM composed of n switching cells is
defined as follows:
Cmin = 2nf S Uin 2 /Pnom . (12)
In a quasi inductiveless SCVM-type converter, the value of resonant inductance (L) is very small
(L can be designed as a PCB air choke). Therefore, to achieve the assumed switching frequency,
the capacitance of the switched capacitors can be selected considerably bigger than Cmin (as in the case
of the experimental setup presented in this paper). In the stage 2 (Figure 11b), the currents of capacitors
C1 –C3 and inductances L1 –L3 have the same values (Equations (8)–(10)) as in the stage 1, but with the
opposite signs. The voltages across the capacitors C1 , C2 , and C3 in the stage 1 are given by
uC1 (t) = (Uin − UC11 ) (1 − cos ω0 t) + UC11 (13)
(Uin − UC11 )
uC2 (t) = − (1 − cos ω0 t) + UC21 (14)
2
(Uin − UC11 )
uC3 (t) = (1 − cos ω0 t) + UC31 (15)
2
where UC21 and UC31 are the initial voltages across capacitors C2 and C3 , respectively.
In the stage 2 (Figure 11b), the expressions for voltages have similar forms with appropriate signs
and initial values.
Based on the formulas mentioned above, all the voltage initial values and the output voltage can
be computed as a function of UC11 . For example, we obtain
Uout = 5Uin − UC11 (16)
UC11 can be calculated taking into account (8) and the following relation
2 P
Iin−av = IL1av = I1m fSn = in (17)
π Uin
π ρ Pin
UC11 = Uin − (18)
2 fSn Uin
where
fSn = fS / f0 (19)
From Equations (16) and (18), we have
π ρ Pin
Uout = 4Uin + (20)
2 fSn Uin
In practical converters, there are voltage drops across the circuit elements like the diodes and the
transistors, which result in a variation of the output voltage with power and frequency.
The efficiency of an SCVM-type converter is determined by the resistances of its components,
voltage drops on the diodes and transistors, the input voltage, power, and by the relation between the
Energies 2020, 13, 5657 15 of 22
switching period TS and period T0 (2), which can be expressed by f Sn (19). Therefore, it is necessary to
calculate the average and rms values of the currents. It is assumed that transistors S1 and S3 are IGBTs,
and S2 and S4 are MOSFETs.
IL1av 1 Pin IL2av IL3av IL1av Pin

ID1av = ID2av = 2 = π I1m fSn = 2Uin , ID3av = IDout−av = 2 = 2 = 4 = 4Uin (21)
1 p πPin 1 p πPin
IS2 = I1m fSn = p , IS4 = I1m fSn = (22)
2 4
p
4Uin fSn 8Uin fSn
For the LSCVMa, we have:
Pin Pin
IS1av = ID1av = , IS3av = ID3av = (23)
2Uin 4Uin
Conduction losses, ∆Pc, in both converters are

X X X X
2
∆Pc = rk ISk + ∆UDl IDlav + ∆USm ISmav + rT In2 (24)
k l m n
where rk denotes the total resistance of the branch with MOSFET transistor Sk (k = 2, 4), including the
resistance of the transistor. ∆UDl is the voltage drop across diode Dl , ∆USm is the voltage drop across
IGBT transistor Sm , rT is the resistance of each circuit with an IGBT transistor, and In is its rms current.
It is assumed that the voltage drops across the devices remain constant in the conducting state.
We assume that all the resistances and voltage drops are the same, i.e.
r2 = r4 = r, ∆US1 = ∆US2 = ∆US , ∆UD1 = ∆UD2 = ∆UD3 = ∆UD4 = ∆UDout = ∆UD (25)
The efficiency of the LSCVMa converter can be calculated as follows. The resistive losses in the
circuits containing IGBTs are:
2 2
3π2 P2in rT
∆Pc2 = rT IL11 + 2rT IL31 = 2 f
(26)
32Uin Sn
Taking (21)–(26) into account, the conduction losses can be presented as
5π2 P2in r 3π2 P2in rT 3Pin

1

∆Pc = 2 f
+ 2 f
+ ∆UD + ∆US (27)
64Uin Sn 32Uin Sn 2Uin 2
The turn-off switching loss is zero, due to the ZCS switching. However, there is a turn-on switching
loss, associated with charging and discharging the transistors’ output capacitances. The total switching
power loss, ∆Psw , is
∆Psw = ∆Wsw fS = ∆Psw0 fSn (28)
where ∆W sw is the energy lost at turn-on in the transistor’s resistances in a single switching cycle,
and ∆Psw0 = ∆W sw ·f 0 is power loss at resonant frequency. A way of calculating these losses is presented
in Reference [31].
The efficiency is (Equations (27) and (28))
∆Pc ∆Psw 5π2 P2in r 3π2 P2in rT 3Pin

1
∆Wsw fS
η= 1 − − = 1− 2
− 2
− ∆U D + ∆U S − (29)
Pin Pin 64Uin fSn 32Uin fSn 2Uin 2 Pin
Energies 2020, 13, 5657 16 of 22
Introducing normalized quantities:
r rT ∆UD ∆US ∆Psw0

rn = 2 /P
, rTn = 2
, ∆UDn = , ∆USn = , ∆Psw0n = (30)
Uin in Uin /Pin Uin Uin Pin
We can simplify the efficiency formula to the form
5π2 rn 3π2 rTn 3 1

η = 1 − − − ∆UDn + ∆USn − ∆Psw0n fSn (31)
64 fSn 32 fSn 2 2
The efficiency of the LSCVMb can be calculated with the use of the following components:
3Pin P
IS1av = ID1av + ID3av = , ID4av = ID1av = in (32)
4Uin 2Uin
where D4 is the LSCVMb additional diode (Figure 1b).

Conduction losses, ∆Pc, of LSCVMb are as follows:
5π2 P2in r 3π2 P2in rT Pin

3

∆Pc = + 3Pin + 2∆UD P+ in ∆US (33)
I S1av 2= IfD1av + I D32U
64U 3av =
2 f , I DU in= I D1av = 2U 4
4av (32)
in Sn in4USn
in in
where D4 is the LSCVMb additional diode (Figure 1b).

and the efficiency of the LSCVMb is
Conduction losses, ΔPc, of LSCVMb are as follows:
2 2
5π2 rΔnPc = 5π r 3π 2Pin2 rT
3πP2inrTn P  3 3 
η = 1 − − 64U 2 f + − + in+ D + ΔU −
 2ΔU∆U S  ∆P
, (33)
2∆U
2
32U in f Sn DnU in  4
Sn  sw0n fSn (34)
64 fSn 32infSn
Sn 4
and the efficiency of the LSCVMb is
It can be seen from (30), (31), and2(34) that the impact of the voltage drops across the diodes on
5π rn 3π 2 rTn  3 
the efficiency depends only on the ratio η = 1 − − −  2ΔU Dn +dropsΔU Snto −the
ΔPsw0n f Sn . voltage. The (34)
64 f Sn of 32
these
f Sn voltage
 4 
supply impact of
the losses in the resistances is more complex. They increase with rising resistances and rising power,
It can be seen from (30), (31), and (34) that the impact of the voltage drops across the diodes on
and decrease with rising
the efficiency inputonly
depends voltage
on theand ratiofrequency f S . Switching
of these voltage drops to the losses
supplyarevoltage.
proportional to switching
The impact of
frequency thef Slosses
. in the resistances is more complex. They increase with rising resistances and rising power,
Theandrelationship between
decrease with risingthe inputefficiency
voltage and and normalized
frequency fS. frequency f Sn = are
Switching losses f S /fproportional
0 for three values
to of
rn (30): 0.016, 0.0304, and 0.040, ∆UDn (30) = 0.008 for the LCSCVMa and the LCSCVMb is shown
switching frequency fS.
in Figure 12.The relationship between the efficiency and normalized frequency fSn = fS/f0 for three values of rn
The value of rn = 0.0304 corresponds to, e.g., Uin = 50 V, Pin = 200 W, L = 500 nH,
(30): 0.016, 0.0304, and 0.040, ΔUDn (30) = 0.008 for the LCSCVMa and the LCSCVMb is shown in
C = 1.5 µF, r = 380 mΩ, and ∆U 0.0304
Figure 12. The value of rn = Dn
is equal to 0.008 for, e.g., ∆U = 0.40 V and U = 50 V. The value
corresponds to, e.g., Uin = 50 V,DPin = 200 W, L = 500innH, C = 1.5 μF,
of relativer = switching ΔUDn isPsw0n
380 mΩ, andlosses equal (30) = 0.0101
to 0.008 for, e.g.,(Figure
ΔUD = 0.40 12b) is valid,
V and Uin = 50e.g., ∆W sw
forvalue
V. The (28) = 11 µJ,
of relative
f 0 = 183.8switching
kHz, and losses = 200
PinPsw0n (30) W. The(Figure
= 0.0101 efficiency
12b) isofvalid,
the e.g.,
LCSCVMb is slightly
for ΔWsw (28) = 11 μJ, flower. In both
0 = 183.8 kHz, and cases,
P = 200 W. The efficiency of the LCSCVMb is slightly lower. In both cases,
it increases with increasing normalized frequency, f Sn , and strongly depends on the circuit parasitic
in it increases with increasing
normalized
resistances. frequency,
Therefore, fSn, and strongly
it is important depends
to minimize on theand
them, circuit
useparasitic
transistorsresistances.
with low Therefore,
values itofisRDS(on)
important to minimize them, and use transistors with low values of RDS(on) and VCE(on).
and V CE(on) .
LCSCVMa LCSCVMb
(a) (b)
Figure
Figure 12. 12. Theoretical
Theoretical chartscharts of efficiency
of efficiency f SnfSn= =f SfS/f/f00 for
vs. vs. forthree
threevalues of rof
values n: 0.016, 0.0304, and 0.040,
rn : 0.016, 0.0304, and 0.040,
and ΔUDn = 0.008: (a) LCSCVMa at switching losses ΔPsw0n = 0.0138, (b) LCSCVMb at switching losses
and ∆UDn = 0.008: (a) LCSCVMa at switching losses ∆Psw0n = 0.0138, (b) LCSCVMb at switching
ΔPsw0n = 0.0101.
losses ∆Psw0n = 0.0101.
The efficiency can be computed in a similar way for the other switching strategies. However, the
calculations will be more complex in the case of the strategies with more than 2 stages.
4. Experimental Verification
This chapter presents the experimental results of the LCSCVMb converter operation. All the tests
were carried out under switching strategy C5. The experimental verification confirms the proper
Energies 2020, 13, 5657 17 of 22
The efficiency can be computed in a similar way for the other switching strategies. However,
the calculations will be more complex in the case of the strategies with more than 2 stages.
4. Experimental Verification
This chapter presents the experimental results of the LCSCVMb converter operation. All the tests
were carried out under switching strategy C5. The experimental verification confirms the proper
operation of the converter, according to its concept. The measured voltage gain was on the expected
level, and all the relevant waveforms were consistent with the simulation results as well.
4.1. Experimental Setup

All the parameters of the converter used during the experimental research, as well as a photograph
of the investigated converter, are collected in Table 5. The parameters of the experimental setup
correspond to the simulation model, and the major difference can be found in the inductance of the
planar PCB choke. The switching frequency in the experimental measurements has been adjusted
to the oscillation period of the switched capacitor
Energies 2020, 13, x FOR PEERcurrents
REVIEW and differs from the value selected for 17 of 22
the simulation tests. An IGBT switch was selected as S1 in the

setup correspond to the simulation
LSCVMb, as this switch conducts the
model, and the major difference can be found in the inductance
total charging current. This current can
of thebe significant,
planar PCB choke. especially
The switching when the
frequency in converter contains
the experimental a larger
measurements has been
adjusted to the oscillation period of the switched capacitor currents and differs from the value
number of the switching cells. In order to generate appropriate control signals, an FPGA evaluation
selected for the simulation tests. An IGBT switch was selected as S1 in the LSCVMb, as this switch
board (INTEL DE0) was utilized. The basicthe
conducts clock frequency
total charging ofThis
current. thiscurrent
device
can was set at especially
be significant, 200 MHz, whenand the
the converter
contains a larger number of the switching cells. In order to generate appropriate control signals, an
time resolution of the generated signals was 5 ns. The test setup is an example design of the converter
FPGA evaluation board (INTEL DE0) was utilized. The basic clock frequency of this device was set
prepared for the purpose of research, to MHz,
at 200 verify anditsthe concepts and
time resolution feasibility.
of the The
generated signals wastests were
5 ns. The test conducted
setup is an example
with 50 V at the input; however, thedesign
voltageof the converter prepared for the purpose of research, to verify its concepts and feasibility.
range as well as power and the design concept can be
The tests were conducted with 50 V at the input; however, the voltage range as well as power and
rescaled to the parameters of a target application.
the design concept can be Moreover, it is important
rescaled to the parameters that the
of a target application. prospective
Moreover, it is important
that the prospective applications of the non-isolated DC-DC converter should comply with safety
applications of the non-isolated DC-DC converter should comply with safety standards.
standards.
Table 5. The of
Table 5. The most important parameters most important
the parameters
laboratory of the laboratory converter.
converter.
Parameter Value The Laboratory Setup
Parameter Input Value The Laboratory Setup
50 V
voltage
Input voltage 50 V
Output load 200 W
Output load Switching200 W
133 kHz
frequency
Switching frequency 133 kHz
Resonant
1.5 μF (KEMET R76 series)
Resonant capacitors 1.5 capacitors
µF (KEMET R76 series)
Resonant Planar chokes: L = 500 nH,
Resonant inductances = 500 nH, RESR
Planar chokes: Linductances RESR==18
18 mΩ
mΩ @@100 100 kHz
kHz
IKB15N65EH5 (V DS = 650 IKB15N65EH5
V, V CE = 1.65(VV)DS = 650 V,
as S1
Transistors
IPB50R140CP (V DS = 550 V, RDSon =VCE0.14
Transistors
= 1.65 V) as S1
Ω) as S2 and S4
IPB50R140CP (VDS = 550 V,
Diodes STTH30L06G (IF = 30 A, V F = 1.0=V,
RDSon 0.14 Ω) as=
V RRM S2600
and V)
S4
STTH30L06G (IF = 30 A, VF =
PCB 2 layers, 35 µm
Diodes
1.0 V, VRRM = 600 V)
Digital scope: Tektronix
PCB MDO3104, current
2 layers, probes:
35 μm Tektronix TCP0030 150 MHz (input current
Laboratory equipment measurement), Rogowsky coil Digital scope:current
(switch Tektronix MDO3104, current
measurements) probes: probes:
voltage TektronixTektronix
TCP0030 150 MHz
THDP0200 200 Laboratory
MHz, Tektronix (input current
P5205 measurement),
100 MHz, power Rogowsky coilYokogawa
analyzer: (switch current
WTmeasurements)
1801
equipment voltage probes: Tektronix THDP0200 200 MHz, Tektronix P5205 100 MHz, power
analyzer: Yokogawa WT 1801
4.2. Test Results
4.2. Test Results
Figure 13a,b presents the waveforms of13a,

Figure theb presents
switching signals
the waveforms with
of the the input
switching and
signals with theoutput
input and current.
output current.
They confirm that the converter operates correctly according to strategy C5. From the waveforms
They confirm that the converter operates correctly according to strategy C5. From the waveforms
presented in Figure 13c, it follows that the converter boosts the input voltage. The measured voltage
presented in Figure 13c, it follows that
ratiothe converter
is 3.65. Figure 13d, eboosts theinput
presents the input voltage.
current waveformThe measured
and the voltage
voltages across the resonant
capacitors. From the waveforms presented in Figure 13d, the average voltage across the capacitors
ratio is 3.65. Figure 13d,e presents the input current waveform and the voltages across the resonant
can be seen. To demonstrate more clearly the magnitude of the oscillation around the average voltage
capacitors. From the waveforms presented in Figure
value of each resonant 13d, thethe
capacitor, average voltage
voltage traces in ACacross
couplingthe
mode capacitors
were recorded can
as well
(Figure 13e). Figure 13f presents voltage stresses across the switches. From these results, it follows
be seen. To demonstrate more clearlythatthethemagnitude of the oscillation around the average voltage value
voltage stresses on switches are significantly below the output voltage of the converter, which
of each resonant capacitor, the voltage traces
is very in AC
favorable from coupling
the switchingmode were recorded as well (Figure 13e).
losses standpoint.
Figure 13f presents voltage stresses across the switches. From these results, it follows that the voltage
Energies 2020, 13, 5657 18 of 22
stresses on switches are significantly below the output voltage of the converter, which is very favorable
Energies
from the 2020, 13, x FOR losses
switching PEER REVIEW
standpoint. 18 of 22
(a) (b)
(c) (d)
(e) (f)
Figure 13. A set of recorded waveforms during experimental tests: (a) Switching signals of transistors
Figure 13. A set of recorded waveforms during experimental tests: (a) Switching signals of transistors
and the input current, (b) input and output current of the converter on the background of switching
and the input current, (b) input and output current of the converter on the background of switching
signals, (c) input and output waveforms of the converter (current and voltage traces), (d) converter
signals, (c) input and output waveforms of the converter (current and voltage traces), (d) converter
input current and voltages across resonant capacitors recorded in DC coupling mode, (e) converter
input current and voltages across resonant capacitors recorded in DC coupling mode, (e) converter
input current and voltages across resonant capacitors recorded in AC coupling mode, and (f) voltage
input current and voltages across resonant capacitors recorded in AC coupling mode, and (f) voltage
stresses across the switches on the background of converter input current. Switching strategy C5.
stresses across the switches on the background of converter input current. Switching strategy C5.
During the experimental research, the basic operation concept of the investigated converter has
During the experimental research, the basic operation concept of the investigated converter has
been checked. Furthermore, the working correctness of the examined device under different output
been checked. Furthermore, the working correctness of the examined device under different output
loads was verified. The tests were carried out for three output load values: 62, 146, and 290 W, focusing
loads was verified. The tests were carried out for three output load values: 62, 146, and 290 W,
especially on the transistor currents and voltages. Figure 14 present the results of the conducted tests
focusing especially on the transistor currents and voltages. Figure 14 present the results of the
conducted tests for different output load conditions. From the results, it follows that the converter
operates properly in low and medium load conditions.
Energies 2020, 13, 5657 19 of 22

for different output load conditions. From the results, it follows that the converter operates properly in
lowEnergies
and medium Switch S1 conditions.
load Switch S2 Switch S3
2020, 13, x FOR PEER REVIEW 19 of 22
Switch S1 Switch S2 Switch S3
(a) (b) (c)
(a) (b) (c)
(d) (e) (f)

(d) (e) (f)
(g) (h) (i)

(g) (h) (i)
Figure 14. Waveforms of the input current as well as the currents and voltages across switches, during
Figure
14.14.
experimental
Figure Waveforms ofofthe
test proceeded
Waveforms theinput
inputcurrent
with currentas
differentasvalues
well as
well asofthe currents
converter
the and
andvoltages
currentsoutput power:across
voltages (a–c)switches,
across during
out = 62 W,
Pswitches, 2A/div,
during
experimental
100V/div, (d–f)
experimental test proceeded
Pout = 146 with
test proceeded with different
W, 5A/div, values
different100V/div, of converter
values of (g–i) output
Pout =output
converter 290 W,power: (a–c)
10A/div,
power: P out = 62 W, 2A/div,
Pout = 62 W,
(a–c) 100V/div. Switching
2A/div,
100V/div, (d–f) Pout = 146 W, 5A/div, 100V/div, (g–i) Pout = 290 W, 10A/div, 100V/div. Switching
strategy
100V/div, C5.
(d–f) Pout = 146 W, 5A/div, 100V/div, (g–i) Pout = 290 W, 10A/div, 100V/div. Switching
strategy C5.
strategy C5.
Figure 15 presents the results of the spectral analysis calculated for the input and output
Figure
Figure 15 15 presents
presents the the results
results of spectral
of the the spectral analysis
analysis calculated
calculated forinput
for the the and
inputoutput
and output
currents.
currents. The calculations have been carried out with the use of MATLAB software, based on the
currents. The calculations have been carried out with the use of MATLAB software, based on the
The calculations
recorded have been
experimental data.carried outwas
The data with the useby
collected ofthe
MATLAB software, based
digital oscilloscope on theMDO3104)
(Tektronix recorded
recorded experimental data. The data was collected by the digital oscilloscope (Tektronix MDO3104)
experimental data. The
with the sampling rate data was collected by the digital oscilloscope (Tektronix MDO3104) with the
of 1 MS/s.
with the sampling rate of 1 MS/s.
sampling rate of 1 MS/s.
(a)
(a) (b)(b)
Figure15.
Figure 15.Results
Results of
of spectral
spectral analysis for:
analysisfor: (a)
(a)The
for:(a) Theinput
inputcurrent and
current (b)(b)
and thethe
output current.
output current.
Figure 15. Results of spectral analysis The input current and (b) the output current.
Theexperimental
The experimentalresults
results of
of the
the output
outputvoltage
voltageofofthe
theLCSCVMb
LCSCVMb converter and
converter andits its
efficiency are are
efficiency
presented in Figure 16. The efficiency is on an acceptable level. The voltage and efficiency drop versus
power is typical for such SC-based converters, and results from their resistive losses. It should be
power is typical for such SC-based converters, and results from their resistive losses. It should be
Energies 2020, 13, 5657 20 of 22
The
Energies experimental
2020, results
13, x FOR PEER REVIEWof the output voltage of the LCSCVMb converter and its efficiency are
20 of 22
power
noticedisthat
typical for such SC-based
the presented converters,
experimental setup isand results from
optimized theirthe
towards resistive losses.
converter cost It should be
reduction. It
noticed that theon
was designed presented experimental
a two-layer PCB of setup
35 μm.is optimized
To increasetowards the converter
the efficiency cost reduction.
by reducing It was
the parasitic
designed
resistance,ona amore
two-layer PCB PCB
expensive of 35and To increase
µm.switches canthe efficiency by reducing the parasitic resistance,
be selected.
a more expensive PCB and switches can be selected.
(a) (b)
Figure 16. Experimental
Figure Experimentaland andsimulation
simulation results
results for for
LSSCVMb
LSSCVMbunder strategy
under C5 atC5
strategy Uinat UinV,=fS 50
= 50 = 133
V,
S =
fkHz: (a)
133 Measured
kHz: (a) output
Measured voltage
output U
voltage
out vs.
U P
out vs.
out , (b)
P measured
out , (b) efficiency
measured vs.
efficiency P
vs. P
out with
out comparison
with comparison to
theoretical
to results
theoretical obtained
results from
obtained from(34) forr =r =
(34)for 380380 mΩ,
mΩ, = 400
VFV=F400 mV, VCE(on)
mV, =W
= 1 V,
VCE(on) 1 V, = 11
sw W = 11 µJ.
sw μJ.
5. Conclusions
5. Conclusions
The presented concepts of the new topologies, as well as the comparison of parameters presented
The presented concepts of the new topologies, as well as the comparison of parameters
in Table 3, and charts in Figures 8–10, lead to the following conclusions:
presented in Table 3, and charts in Figures 8–10, lead to the following conclusions:
• The major idea of the proposed new converters is based on the elimination of the number
• The major idea of the proposed new converters is based on the elimination of the number of
of switches in a voltage multiplier (SCVM), while maintaining its proper operation. By the
switches in a voltage multiplier (SCVM), while maintaining its proper operation. By the
modification of an SCVM, the new topology concepts LCSCVMa and LCSCVMb were proposed,
modification of an SCVM, the new topology concepts LCSCVMa and LCSCVMb were proposed,
with a reduced number of switching cells and redesigned functions of the diodes. Depending on
with a reduced number of switching cells and redesigned functions of the diodes. Depending
the technology of practical implementation, either of these converters can be more attractive than
on the technology of practical implementation, either of these converters can be more attractive
the other.
than the other.
• Various switching strategies are possible for the converters, which affect the parameters of
• Various switching strategies are possible for the converters, which affect the parameters of
operation related to switching losses and the sizing of the passive components of the converter,
operation related to switching losses and the sizing of the passive components of the converter,
but also the required input and output filters.
but also the required input and output filters.
•• The
The converter
converter operates
operates properly
properlywithwithaawide
widerange
rangeof ofoutput
outputloads.
loads.
•• From the compared results, it follows that the most effective
From the compared results, it follows that the most effective topology,topology, the LCSCVMb, can operate
the LCSCVMb, can
with nearly the lowest parameters of AC component in the voltages on capacitors,
operate with nearly the lowest parameters of AC component in the voltages on capacitors, and the highest
and
frequency
the highest in frequency
the input and output
in the current.
input This allows
and output for aThis
current. reduction
allowsoffor
theaconverter
reductionvolume,
of the
especially by optimizing the input and output filters.
converter volume, especially by optimizing the input and output filters.
•• The
The discussed
discussedconverters
convertersdemonstrated
demonstrated an an
improvement
improvement in the
in SCVM topology,
the SCVM whichwhich
topology, may result
may
in a prospective
result cost reduction.
in a prospective cost reduction.
Author Contributions: Conceptualization, R.S.; methodology, R.S. and Z.W.; software, R.S., Z.W. and S.F.;
Author Contributions: Conceptualization, R.S.; methodology, R.S. and Z.W.; software, R.S., Z.W. and S.F.;
validation, R.S., Z.W.
validation, R.S., Z.W. and
and S.F.;
S.F.; formal
formal analysis,
analysis, R.S.
R.S. and
and Z.W.;
Z.W.; investigation,
investigation, R.S.,
R.S., Z.W. and S.F.;
Z.W. and resources, R.S.;
S.F.; resources, R.S.;
data curation,
data curation, R.S., Z.W.
Z.W. and
and S.F.;
S.F.; writing—original
writing—original draft
draft preparation,
preparation, R.S., Z.W.
Z.W. and
and S.F.;
S.F.; writing—review
writing—review andand
editing,
editing, visualization,
visualization, supervision, R.S., Z.W. and S.F.; S.F.; project
project administration,
administration, R.S.
R.S. All
All authors
authors have
have read
read and
and
agreed
agreed to
to the
the published
published version
version ofof the
the manuscript.
manuscript.
Funding: This research received no external funding.
Funding: This research received no external funding.
Conflicts of Interest: The authors declare no conflict of interest.
Conflicts of Interest: The authors declare no conflict of interest.
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energies

Keywords: DC-DC converter; resonant converter; high-voltage-gain converter; switched-capacitor

Energies 2020, 13, 5657; doi:10.3390/en13215657 www.mdpi.com/journal/energies

a series-parallel converter in that a high-voltage-gain can be obtained, as it is proportional to the

2. Operating Principle of the Converters

and L = L1 = L2 = L3 , C = C1 = C2 = C3 (Figure 1).

2.1.1. Simulation Results of the Switching Strategy C1

2.1.2. Simulation Results of the Switching Strategy C2

2.1.3. Simulation Results of the Switching Strategy C3

2.2. Switching Strategy Concepts for the LCSCVMb

2.2.2. Simulation Results of the Switching Strategy C5

2.3. Comparison among the Topologies and Switching Strategies

The data are

8, it requires only four switches, which is an excellent result in comparison to

3. Efficiency Model of the LCSCVM Converters

uC1 (t) = (Uin − UC11 ) (1 − cos ω0 t) + UC11 (13)

Uout = 5Uin − UC11 (16)

From Equations (16) and (18), we have

IL1av 1 Pin IL2av IL3av IL1av Pin

Conduction losses, ∆Pc, in both converters are

Taking (21)–(26) into account, the conduction losses can be presented as

5π2 P2in r 3π2 P2in rT 3Pin

∆Pc ∆Psw 5π2 P2in r 3π2 P2in rT 3Pin

Introducing normalized quantities:

r rT ∆UD ∆US ∆Psw0

We can simplify the efficiency formula to the form

5π2 rn 3π2 rTn 3 1

where D4 is the LSCVMb additional diode (Figure 1b).

5π2 P2in r 3π2 P2in rT Pin

where D4 is the LSCVMb additional diode (Figure 1b).

4.1. Experimental Setup

the simulation tests. An IGBT switch was selected as S1 in the

Figure 13a,b presents the waveforms of13a,

Energies 2020, 13, x FOR PEER REVIEW 19 of 22

Switch S1 Switch S2 Switch S3

(a) (b) (c)

(a) (b) (c)

(d) (e) (f)

(g) (h) (i)

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