HCK0 Samsung Datasheet DDR3SDRAM

Rev. 1.0, Jan.
2012
K4B4G1646B
4Gb B-die DDR3 SDRAM Olny x16

96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
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-1-
Rev. 1.0
K4B4G1646B datasheet DDR3 SDRAM

Revision History
Revision No. History Draft Date Remark Editor
1.0 - First SPEC. Release Jan. 2012 - J.Y.Lee
-2-
Rev. 1.0

Table Of Contents
4Gb B-die DDR3 SDRAM Olny x16
1. Ordering Information ..................................................................................................................................................... 5
2. Key Features................................................................................................................................................................. 5
3. Package pinout/Mechanical Dimension & Addressing.................................................................................................. 6
3.1 x16 Package Pinout (Top view) : 96ball FBGA Package ........................................................................................ 6
3.2 FBGA Package Dimension (x16)............................................................................................................................. 7
4. Input/Output Functional Description.............................................................................................................................. 8
5. DDR3 SDRAM Addressing ........................................................................................................................................... 9
6. Absolute Maximum Ratings .......................................................................................................................................... 10
6.1 Absolute Maximum DC Ratings............................................................................................................................... 10
6.2 DRAM Component Operating Temperature Range ................................................................................................ 10
7. AC & DC Operating Conditions..................................................................................................................................... 10
7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 10
8. AC & DC Input Measurement Levels ............................................................................................................................ 12
8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 12
8.2 VREF Tolerances...................................................................................................................................................... 13
8.3 AC & DC Logic Input Levels for Differential Signals............................................................................................... 14
8.3.1. Differential signals definition ............................................................................................................................ 14
8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 14
8.3.3. Single-ended requirements for differential signals ........................................................................................... 15
8.4 Differential Input Cross Point Voltage...................................................................................................................... 16
8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 16
8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 16
9. AC & DC Output Measurement Levels ......................................................................................................................... 17
9.1 Single-ended AC & DC Output Levels..................................................................................................................... 17
9.2 Differential AC & DC Output Levels......................................................................................................................... 17
9.3 Single-ended Output Slew Rate .............................................................................................................................. 17
9.4 Differential Output Slew Rate .................................................................................................................................. 18
9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 18
9.6 Overshoot/Undershoot Specification ....................................................................................................................... 19
9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 19
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 19
9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 20
9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 21
9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 21
9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 22
9.8.2. ODT Temperature and Voltage sensitivity ....................................................................................................... 23
9.9 ODT Timing Definitions ........................................................................................................................................... 24
9.9.1. Test Load for ODT Timings .............................................................................................................................. 24
9.9.2. ODT Timing Definitions .................................................................................................................................... 24
10. IDD Current Measure Method ..................................................................................................................................... 27
10.1 IDD Measurement Conditions ............................................................................................................................... 27
11. 4Gb DDR3 SDRAM B-die IDD Specification Table .................................................................................................... 36
12. Input/Output Capacitance ........................................................................................................................................... 37
13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-2133 ...................................................................... 38
13.1 Clock Specification ................................................................................................................................................ 38
13.1.1. Definition for tCK(avg).................................................................................................................................... 38
13.1.2. Definition for tCK(abs).................................................................................................................................... 38
13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 38
13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 38
13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 38
13.1.6. Definition for tERR(nper)................................................................................................................................ 38
13.2 Refresh Parameters by Device Density................................................................................................................. 39
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 39
13.3.1. Speed Bin Table Notes .................................................................................................................................. 45
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Rev. 1.0

14. Timing Parameters by Speed Grade .......................................................................................................................... 46
14.1 Jitter Notes ............................................................................................................................................................ 52
14.2 Timing Parameter Notes........................................................................................................................................ 53
14.3 Address/Command Setup, Hold and Derating : .................................................................................................... 54
14.4 Data Setup, Hold and Slew Rate Derating : .......................................................................................................... 61
-4-
Rev. 1.0

1. Ordering Information
[ Table 1 ] Samsung 4Gb DDR3 B-die ordering information table
Organization DDR3-1066 (7-7-7) DDR3-1333 (9-9-9)6 DDR3-1600 (11-11-11)5 DDR3-1866 (13-13-13)4 DDR3-2133 (14-14-14)3 Package
256Mx16 K4B4G1646B-HCF8 K4B4G1646B-HCH9 K4B4G1646B-HCK0 K4B4G1646B-HCMA K4B4G1646B-HCNB 96 FBGA
256Mx16 - K4B4G1646B-HIH9 K4B4G1646B-HIK0 - - 96 FBGA
256Mx16 - K4B4G1646B-HPH9 K4B4G1646B-HPK0 - - 96 FBGA
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. 13th digit stands for below.
"C" : Comercial temp/Normal power
"I" : Industrial temp/Normal power
"P" : Industrial temp/Low power(IDD6 only)
3. DDR3-2133(14-14-14) is backward compatible to DDR3-1866(13-13-13), DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)
4. DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)
5. DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)
6. DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
2. Key Features
[ Table 2 ] 4Gb DDR3 B-die Speed bins
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133
Speed Unit
6-6-6 7-7-7 9-9-9 11-11-11 13-13-13 14-14-14
tCK(min) 2.5 1.875 1.5 1.25 1.07 0.935 ns
CAS Latency 6 7 9 11 13 14 nCK
tRCD(min) 15 13.125 13.5 13.75 13.91 13.09 ns
tRP(min) 15 13.125 13.5 13.75 13.91 13.09 ns
tRAS(min) 37.5 37.5 36 35 34 33 ns
tRC(min) 52.5 50.625 49.5 48.75 47.91 46.09 ns
• JEDEC standard 1.5V(1.425V~1.575V) The 4Gb DDR3 SDRAM B-die is organized as a 32Mbit x 16 I/Os x 8banks,
• VDDQ = 1.5V(1.425V~1.575V) device. This synchronous device achieves high speed double-data-rate
• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, transfer rates of up to 2133Mb/sec/pin (DDR3-2133) for general applica-
667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin, tions.
933MHz fCK for 1866Mb/sec/pin, 1066 MHz fCK for 2133Mb/sec/pin The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
• 8 Banks
On Die Termination using ODT pin and Asynchronous Reset .
• Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,12,13,14
All of the control and address inputs are synchronized with a pair of exter-
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
(DDR3-1066), 7 (DDR3-1333) , 8 (DDR3-1600), 9 (DDR3-1866) and
10 (DDR3-2133) pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting information in a RAS/CAS multiplexing style. The DDR3 device operates
address “000” only), 4 with tCCD = 4 which does not allow seamless with a single 1.5V(1.425V~1.575V) power supply and
read or write [either On the fly using A12 or MRS] 1.5V(1.425V~1.575V).
• Bi-directional Differential Data-Strobe The 4Gb DDR3 B-die device is available in 96ball FBGAs(x16).
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at
85°C < TCASE < 95 °C
• Support Industrial Temp ( -40 ∼ 85°C )
• Asynchronous Reset
• Package : 96 balls FBGA - x16
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing
Diagram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
-5-
Rev. 1.0

3. Package pinout/Mechanical Dimension & Addressing
3.1 x16 Package Pinout (Top view) : 96ball FBGA Package
1 2 3 4 5 6 7 8 9
A VDDQ DQU5 DQU7 DQU4 VDDQ VSS A

B VSSQ VDD VSS DQSU DQU6 VSSQ B
C VDDQ DQU3 DQU1 DQSU DQU2 VDDQ C
D VSSQ VDDQ DMU DQU0 VSSQ VDD D
E VSS VSSQ DQL0 DML VSSQ VDDQ E
F VDDQ DQL2 DQSL DQL1 DQL3 VSSQ F
G VSSQ DQL6 DQSL VDD VSS VSSQ G
H VREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ H
J NC VSS RAS CK VSS NC J
K ODT VDD CAS CK VDD CKE K
L NC CS WE A10/AP ZQ NC L
M VSS BA0 BA2 NC VREFCA VSS M
N VDD A3 A0 A12/BC BA1 VDD N
P VSS A5 A2 A1 A4 VSS P
R VDD A7 A9 A11 A6 VDD R
T VSS RESET A13 A14 A8 VSS T
1 2 3 4 5 6 7 8 9
Ball Locations (x16) A
B
C
Populated ball D
Ball not populated E
F
G
H
Top view J
(See the balls through the package) K
L
M
N
P
R
T
-6-
Rev. 1.0
3.2 FBGA Package Dimension (x16)
Units : Millimeters
10.00 ± 0.10
A
0.80 x 8 = 6.40
#A1 INDEX MARK
(Datum A)
0.80 1.60 3.20
B
9 8 7 6 5 4 3 2 1
A
B
C
D
6.00
(Datum B) E
0.80 x 15 = 12.00
F
0.40
13.30 ± 0.10
G
H
J
K
L
M
N
0.80
P
R
T
96 - ∅0.45 Solder ball (0.95) MOLDING AREA

(Post Reflow ∅0.50 ± 0.05)
(1.90)
0.2 M A B
BOTTOM VIEW
0.10MAX
#A1 10.00 ± 0.10

13.30 ± 0.10
0.35 ± 0.05
TOP VIEW
1.10 ± 0.10
-7-
Rev. 1.0

4. Input/Output Functional Description
[ Table 3 ] Input/Output function description
Symbol Type Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of
CK, CK Input
the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and
output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or
Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become
CKE Input
stable during the power on and initialization sequence, it must be maintained during all operations (including Self-
Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT
and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on
CS Input
systems with multiple Ranks. CS is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When
enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode
ODT Input
Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is pro-
grammed to disable ODT.
RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-
DM
Input dent with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of
(DMU), (DML)
DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1.
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being
BA0 - BA2 Input applied. Bank address also determines if the mode register or extended mode register is to be accessed during a
MRS cycle.
Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands
to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions,
A0 - A15 Input
see below)
The address inputs also provide the op-code during Mode Register Set commands.
Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be per-
formed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge)
A10 / AP Input
A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or
all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses.
Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be per-
A12 / BC Input
formed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH.
RESET Input RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and
20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low.
DQ Input/Output Data Input/ Output: Bi-directional data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the
x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data
DQS, (DQS) Input/Output strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide dif-
ferential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and
does not support single-ended.
Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When
TDQS, (TDQS) Output
disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/
x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1.
NC No Connect: No internal electrical connection is present.
VDDQ Supply DQ Power Supply: 1.5V +/- 0.075V
VSSQ Supply DQ Ground
VDD Supply Power Supply: 1.5V +/- 0.075V
VSS Supply Ground
VREFDQ Supply Reference voltage for DQ
VREFCA Supply Reference voltage for CA
ZQ Supply Reference Pin for ZQ calibration
NOTE : Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.
-8-
Rev. 1.0

5. DDR3 SDRAM Addressing
1Gb
Configuration 256Mb x 4 128Mb x 8 64Mb x 16
# of Bank 8 8 8
Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2
Auto precharge A10/AP A10/AP A10/AP
Row Address A0 - A13 A0 - A13 A0 - A12
Column Address A0 - A9,A11 A 0 - A9 A0 - A 9
BC switch on the fly A12/BC A12/BC A12/BC
Page size *1 1 KB 1 KB 2 KB
2Gb
Configuration 512Mb x 4 256Mb x 8 128Mb x 16
# of Bank 8 8 8
4Gb
Configuration 1Gb x 4 512Mb x 8 256Mb x 16
# of Bank 8 8 8
8Gb
Configuration 2Gb x 4 1Gb x 8 512Mb x 16
# of Bank 8 8 8
Column Address A0 - A9,A11,A13 A0 - A9,A11 A0 - A 9
NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered.
Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG÷8
where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
-9-
Rev. 1.0

6. Absolute Maximum Ratings
6.1 Absolute Maximum DC Ratings
[ Table 4 ] Absolute Maximum DC Ratings
Symbol Parameter Rating Units NOTE
VDD Voltage on VDD pin relative to Vss -0.4 V ~ 1.975 V V 1,3
VDDQ Voltage on VDDQ pin relative to Vss -0.4 V ~ 1.975 V V 1,3
VIN, VOUT Voltage on any pin relative to Vss -0.4 V ~ 1.975 V V 1
TSTG Storage Temperature -55 to +100 °C 1, 2
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be
equal to or less than 300mV.
6.2 DRAM Component Operating Temperature Range

[ Table 5 ] Temperature Range
Symbol Parameter rating Unit NOTE
Normal 0 to 95 °C 1, 2, 4
TOPER Operating Temperature Range
Industrial -40 to 95 °C 1, 3, 4
NOTE :
1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document
JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-
tained between 0-85°C under all operating conditions
3. The Industrial Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-
tained between -40-85°C under all operating conditions
4. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0b and MR2 A7 = 1b).
7. AC & DC Operating Conditions

7.1 Recommended DC operating Conditions (SSTL_1.5)
[ Table 6 ] Recommended DC Operating Conditions
Rating
Symbol Parameter Units NOTE
Min. Typ. Max.
VDD Supply Voltage 1.425 1.5 1.575 V 1,2
VDDQ Supply Voltage for Output 1.425 1.5 1.575 V 1,2
NOTE :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
- 10 -
Rev. 1.0

8. AC & DC Input Measurement Levels
8.1 AC & DC Logic input levels for single-ended signals
[ Table 7 ] Single-ended AC & DC input levels for Command and Address
DDR3-800/1066/1333/1600 DDR3-1866/2133
Symbol Parameter Unit NOTE
Min. Max. Min. Max.
VIH.CA(DC100) DC input logic high VREF + 100 VDD VREF + 100 VDD mV 1,5
VIL.CA(DC100) DC input logic low VSS VREF - 100 VSS VREF - 100 mV 1,6
VIH.CA(AC175) AC input logic high VREF + 175 Note 2 - - mV 1,2,7
VIL.CA(AC175) AC input logic low Note 2 VREF - 175 - - mV 1,2,8
VIH.CA(AC150) AC input logic high VREF+150 Note 2 - - mV 1,2,7
VIL.CA(AC150) AC input logic low Note 2 VREF-150 - - mV 1,2,8
VIH.CA(AC135) AC input logic high - - VREF + 135 Note 2 mV 1,2,7
VIL.CA(AC135) AC input logic low - - Note 2 VREF - 135 mV 1,2,8
VIH.CA(AC125) AC input logic high - - VREF+125 Note 2 mV 1,2,7
VIL.CA(AC125) AC input logic low - - Note 2 VREF-125 mV 1,2,8
Reference Voltage for ADD,
VREFCA(DC) 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V 3,4
CMD inputs
NOTE :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See ’Overshoot/Undershoot Specification’ on page 19.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135) and VIH.CA(AC125); VIH.CA(AC175) value is used when VREF + 175mV is referenced
, VIH.CA(AC150) value is used when VREF + 150mV is referenced, VIH.CA(AC135) value is used when VREF + 135mV is referenced and VIH.CA(AC125) value is used when
VREF + 125mV is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175) and VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value is used when VREF - 175mV is refer-
enced, VIL.CA(AC150) value is used when VREF - 150mV is referenced, VIL.CA(AC135) value is used when VREF - 135mV is referenced and VIL.CA(AC125) value is used
when VREF - 125mV is referenced.
[ Table 8 ] Single-ended AC & DC input levels for DQ and DM

DDR3-800/1066 DDR3-1333/1600 DDR3-1866/2133
Min. Max. Min. Max. Min. Max.
VIH.DQ(DC100) DC input logic high VREF + 100 VDD VREF + 100 VDD VREF + 100 VDD mV 1,5
VIL.DQ(DC100) DC input logic low VSS VREF - 100 VSS VREF - 100 VSS VREF - 100 mV 1,6
VIH.DQ(AC175) AC input logic high VREF + 175 NOTE 2 - - - - mV 1,2,7
VIL.DQ(AC175) AC input logic low NOTE 2 VREF - 175 - - - - mV 1,2,8
VIH.DQ(AC150) AC input logic high VREF + 150 NOTE 2 VREF + 150 NOTE 2 - - mV 1,2,7
VIL.DQ(AC150) AC input logic low NOTE 2 VREF - 150 NOTE 2 VREF - 150 - - mV 1,2,8
VIH.DQ(AC135) AC input logic high - - - - VREF + 135 NOTE 2 mV 1,2,7
VIL.DQ(AC135) AC input logic low - - - - NOTE 2 VREF - 135 mV 1,2,8
Reference Voltage for DQ,
VREFDQ(DC) 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V 3,4
DM inputs
NOTE :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2. See ’Overshoot/Undershoot Specification’ on page 19.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150) and VIH.DQ(AC135) ; VIH.DQ(AC175) value is used when VREF + 175mV is referenced,
VIH.DQ(AC150) value is used when VREF + 150mV is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150) ; VIL.DQ(AC175) value is used when VREF - 175mV is referenced, VIL.DQ(AC150) value is used when
VREF - 150mV is referenced.
- 11 -
Rev. 1.0

8.2 VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage
VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on
page 12. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.
voltage
VDD
VSS
time
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF.
"VREF" shall be understood as VREF(DC), as defined in Figure 1 .
This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing
and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
- 12 -
Rev. 1.0

8.3 AC & DC Logic Input Levels for Differential Signals
8.3.1 Differential signals definition
tDVAC
VIH.DIFF.AC.MIN
Differential Input Voltage (i.e. DQS-DQS, CK-CK)
VIH.DIFF.MIN
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
[ Table 9 ] Differential AC & DC Input Levels
DDR3-800/1066/1333/1600/1866/2133
Symbol Parameter unit NOTE
min max
VIHdiff differential input high +0.2 NOTE 3 V 1
VILdiff differential input low NOTE 3 -0.2 V 1
VIHdiff(AC) differential input high ac 2 x (VIH(AC) - VREF) NOTE 3 V 2
VILdiff(AC) differential input low ac NOTE 3 2 x (VIL(AC) - VREF) V 2
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low
level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max,
VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification"
[ Table 10 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
tDVAC [ps] @ |VIH/Ldiff(AC)| tDVAC [ps] @ |VIH/Ldiff(AC)| tDVAC [ps] @ |VIH/Ldiff(AC)| tDVAC [ps] @ |VIH/Ldiff(AC)|
Slew Rate [V/ns] = 350mV = 300mV = 270mV = 250mV
min max min max min max min max
> 4.0 75 - 175 - TBD - TBD -
4.0 57 - 170 - TBD - TBD -
3.0 50 - 167 - TBD - TBD -
2.0 38 - 163 - TBD - TBD -
1.8 34 - 162 - TBD - TBD -
1.6 29 - 161 - TBD - TBD -
1.4 22 - 159 - TBD - TBD -
1.2 13 - 155 - TBD - TBD -
1.0 0 - 150 - TBD - TBD -
< 1.0 0 - 150 - TBD - TBD -
- 13 -
Rev. 1.0

8.3.3 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for
single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax [approximately equal to the ac-levels { VIH(AC) / VIL(AC)} for ADD/CMD signals] in every
half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax [approximately the ac-levels { VIH(AC) / VIL(AC)} for DQ signals] in every half-cycle
proceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD sig-
nals, then these ac-levels apply also for the single-ended signals CK and CK .
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSEL max
VSEL
VSS or VSSQ
time
Figure 3. Single-ended requirement for differential signals
Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement
with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode characteristics of these signals.
[ Table 11 ] Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU
DDR3-800/1066/1333/1600/1866/2133
Min Max
Single-ended high-level for strobes (VDD/2)+0.175 NOTE3 V 1, 2
VSEH
Single-ended high-level for CK, CK (VDD/2)+0.175 NOTE3 V 1, 2
Single-ended low-level for strobes NOTE3 (VDD/2)-0.175 V 1, 2
VSEL
Single-ended low-level for CK, CK NOTE3 (VDD/2)-0.175 V 1, 2
NOTE :
1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs.
2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the
reduced level applies also here
3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot
Specification"
- 14 -
Rev. 1.0

8.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signal to the mid level between of VDD and VSS.
VDD
CK, DQS
VIX
VDD/2
VIX VIX
CK, DQS
VSEH VSEL
VSS
Figure 4. VIX Definition
[ Table 12 ] Cross point voltage for differential input signals (CK, DQS)
DDR3-800/1066/1333/1600/1866/2133
Min Max
-150 150 mV 2
VIX Differential Input Cross Point Voltage relative to VDD/2 for CK,CK
-175 175 mV 1
VIX Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS -150 150 mV 2
NOTE :
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CKand CK are monotonic, have a single-ended swing VSEL / VSEH of at least VDD/2
±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns. Refer to Table 11 on page 15 for VSEL and VSEH standard values.
2. The relation between VIX Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + VIX(Min) - VSEL ≥ 25mV
VSEH - ((VDD/2) + VIX(Max)) ≥ 25mV
8.5 Slew rate definition for Differential Input Signals

See 14.3 “Address/Command Setup, Hold and Derating :” on page 48 for single-ended slew rate definitions for address and command signals.
See 14.4 “Data Setup, Hold and Slew Rate Derating :” on page 54 for single-ended slew rate definitions for data signals.
8.6 Slew rate definitions for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table 13 and Figure 5.
[ Table 13 ] Differential input slew rate definition

Measured
Description Defined by
From To
VIHdiffmin - VILdiffmax
Differential input slew rate for rising edge (CK-CK and DQS-DQS) VILdiffmax VIHdiffmin
Delta TRdiff
VIHdiffmin - VILdiffmax
Differential input slew rate for falling edge (CK-CK and DQS-DQS) VIHdiffmin VILdiffmax
Delta TFdiff
NOTE :
The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds.
VIHdiffmin
VILdiffmax
delta TFdiff delta TRdiff
Figure 5. Differential Input Slew Rate definition for DQS, DQS, and CK, CK
- 15 -
Rev. 1.0

9. AC & DC Output Measurement Levels
9.1 Single-ended AC & DC Output Levels
[ Table 14 ] Single-ended AC & DC output levels
Symbol Parameter DDR3-800/1066/1333/1600/1866/2133 Units NOTE
VOH(DC) DC output high measurement level (for IV curve linearity) 0.8 x VDDQ V
VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5 x VDDQ V
VOL(DC) DC output low measurement level (for IV curve linearity) 0.2 x VDDQ V
VOH(AC) AC output high measurement level (for output SR) VTT + 0.1 x VDDQ V 1
VOL(AC) AC output low measurement level (for output SR) VTT - 0.1 x VDDQ V 1
NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
load of 25Ω to VTT=VDDQ/2.
9.2 Differential AC & DC Output Levels

[ Table 15 ] Differential AC & DC output levels
Symbol Parameter DDR3-800/1066/1333/1600/1866/2133 Units NOTE
VOHdiff(AC) AC differential output high measurement level (for output SR) +0.2 x VDDQ V 1
VOLdiff(AC) AC differential output low measurement level (for output SR) -0.2 x VDDQ V 1
NOTE : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
load of 25Ω to VTT=VDDQ/2 at each of the differential outputs.
9.3 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in Table 16 and Figure 6.
[ Table 16 ] Single-ended output slew rate definition
Measured
From To
VOH(AC)-VOL(AC)
Single ended output slew rate for rising edge VOL(AC) VOH(AC)
Delta TRse
VOH(AC)-VOL(AC)
Single ended output slew rate for falling edge VOH(AC) VOL(AC)
Delta TFse
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 17 ] Single-ended output slew rate

Parameter Symbol Units
Min Max Min Max Min Max Min Max Min Max Min Max
Single ended output slew rate SRQse 2.5 5 2.5 5 2.5 5 2.5 5 2.5 51) 2.5 51) V/ns
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ
signals in the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the
remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
VOH(AC)
VTT
VOL(AC)
delta TFse delta TRse
Figure 6. Single-ended Output Slew Rate Definition
- 16 -
Rev. 1.0

9.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOH-
diff(AC) for differential signals as shown in Table 18 and Figure 7.
[ Table 18 ] Differential output slew rate definition

Measured
From To
VOHdiff(AC)-VOLdiff(AC)
Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC)
Delta TRdiff
VOHdiff(AC)-VOLdiff(AC)
Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC)
Delta TFdiff
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 19 ] Differential output slew rate

Parameter Symbol Units
Differential output slew rate SRQdiff 5 10 5 10 5 10 5 10 5 12 5 12 V/ns
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
diff : Differential Signals
For Ron = RZQ/7 setting
VOHdiff(AC)
VTT
VOLdiff(AC)
delta TFdiff delta TRdiff
Figure 7. Differential Output Slew Rate Definition
9.5 Reference Load for AC Timing and Output Slew Rate

Figure 8 represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate
measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. Sys-
tem designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their
production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
VDDQ
DQ
CK/CK DUT DQS VTT = VDDQ/2
DQS
25Ω
Reference
Point
Figure 8. Reference Load for AC Timing and Output Slew Rate
- 17 -
Rev. 1.0

9.6 Overshoot/Undershoot Specification
9.6.1 Address and Control Overshoot and Undershoot specifications
[ Table 20 ] AC overshoot/undershoot specification for Address and Control pins (A0-A12, BA0-BA2. CS. RAS. CAS. WE. CKE, ODT)
Specification
Parameter Unit
Maximum peak amplitude allowed for overshoot area (See Figure 9) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V V
Maximum peak amplitude allowed for undershoot area (See Figure 9) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V V
Maximum overshoot area above VDD (See Figure 9) 0.67V-ns 0.5V-ns 0.4V-ns 0.33V-ns 0.28V-ns 0.25V-ns V-ns
Maximum undershoot area below VSS (See Figure 9) 0.67V-ns 0.5V-ns 0.4V-ns 0.33V-ns 0.28V-ns 0.25V-ns V-ns
Maximum Amplitude
Overshoot Area
VDD
Volts
(V)
VSS
Undershoot Area
Maximum Amplitude
Time (ns)
Figure 9. Address and Control Overshoot and Undershoot Definition
9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
[ Table 21 ] AC overshoot/undershoot specification for Clock, Data, Strobe and Mask (DQ, DQS, DQS, DM, CK, CK)
Specification
Parameter Unit
Maximum peak amplitude allowed for overshoot area (See Figure 10) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V V
Maximum peak amplitude allowed for undershoot area (See Figure 10) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V V
Maximum overshoot area above VDDQ (See Figure 10) 0.25V-ns 0.19V-ns 0.15V-ns 0.13V-ns 0.11V-ns 0.10V-ns V-ns
Maximum undershoot area below VSSQ (See Figure 10) 0.25V-ns 0.19V-ns 0.15V-ns 0.13V-ns 0.11V-ns 0.10V-ns V-ns
Maximum Amplitude
Overshoot Area
VDDQ
Volts
(V)
VSSQ
Undershoot Area
Maximum Amplitude
Time (ns)
Figure 10. Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
- 18 -
Rev. 1.0

9.7 34ohm Output Driver DC Electrical Characteristics
A functional representation of the output buffer is shown below. Output driver impedance RON is defined by the value of external reference resistor RZQ
as follows:
RON34 = RZQ/7 (Nominal 34.3ohms +/- 10% with nominal RZQ=240ohm)
The individual Pull-up and Pull-down resistors (RONpu and RONpd) are defined as follows
VDDQ-VOUT
RONpu = under the condition that RONpd is turned off
l Iout l
VOUT
RONpd = under the condition that RONpu is turned off
l Iout l
Output Driver
VDDQ
Ipu
To
other
RON Pu
circuity
DQ
Iout
RON Pd
Vout
Ipd
VSSQ
Figure 11. Output Driver : Definition of Voltages and Currents
[ Table 22 ] Output Driver DC Electrical Characteristics, assuming RZQ=240ohms ;

entire operating temperature range ; after proper ZQ calibration
RONnom Resistor Vout Min Nom Max Units NOTE
VOLdc = 0.2 x VDDQ 0.6 1.0 1.1 1,2,3
RON34pd VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 1,2,3
VOHdc = 0.8 x VDDQ 0.9 1.0 1.4 1,2,3
34Ohms RZQ/7
VOLdc = 0.2 x VDDQ 0.9 1.0 1.4 1,2,3
RON34pu VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 1,2,3
VOHdc = 0.8 x VDDQ 0.6 1.0 1.1 1,2,3
VOLdc = 0.2 x VDDQ 0.6 1.0 1.1 1,2,3
RON40pd VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 1,2,3
VOHdc = 0.8 x VDDQ 0.9 1.0 1.4 1,2,3
40Ohms RZQ/6
VOLdc = 0.2 x VDDQ 0.9 1.0 1.4 1,2,3
RON40pu VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 1,2,3
VOHdc = 0.8 x VDDQ 0.6 1.0 1.1 1,2,3
Mismatch between Pull-up and Pull-down,
VOMdc = 0.5 x VDDQ -10 10 % 1,2,4
MMpupd
NOTE :
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra-
tion, see following section on voltage and temperature sensitivity
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS
3. Pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 X VDDQ. Other calibration schemes may be used to achieve the linearity spec shown
above, e.g. calibration at 0.2 X VDDQ and 0.8 X VDDQ
4. Measurement definition for mismatch between pull-up and pull-down, MMpupd: Measure RONpu and RONpd. both at 0.5 X VDDQ:
RONpu - RONpd
MMpupd = x 100
RONnom
- 19 -
Rev. 1.0

9.7.1 Output Drive Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to Table 23 and Table 24.
ΔT = T - T(@calibration); ΔV = VDDQ - VDDQ (@calibration); VDD = VDDQ
*dRONdT and dRONdV are not subject to production test but are verified by design and characterization
[ Table 23 ] Output Driver Sensitivity Definition

Min Max Units
RONPU@VOHDC 0.6 - dRONdTH * |ΔT| - dRONdVH * |ΔV| 1.1 + dRONdTH * |ΔT| + dRONdVH * |ΔV| RZQ/7
RON@VOMDC 0.9 - dRONdTM * |ΔT| - dRONdVM * |ΔV| 1.1 + dRONdTM * |ΔT| + dRONdVM * |ΔV| RZQ/7
RONPD@VOLDC 0.6 - dRONdTL * |ΔT| - dRONdVL * |ΔV| 1.1 + dRONdTL * |ΔT| + dRONdVL * |ΔV| RZQ/7
[ Table 24 ] Output Driver Voltage and Temperature Sensitivity

Speed Bin DDR3-800/1066/1333 DDR3-1600/1866/2133
Units
Min Max Min Max
dRONdTM 0 1.5 0 1.5 %/°C
dRONdVM 0 0.15 0 0.13 %/mV

dRONdTL 0 1.5 0 1.5 %/°C
dRONdVL 0 0.15 0 0.13 %/mV

dRONdTH 0 1.5 0 1.5 %/°C
dRONdVH 0 0.15 0 0.13 %/mV
9.8 On-Die Termination (ODT) Levels and I-V Characteristics

On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of MR1 register.
ODT is applied to the DQ,DM, DQS/DQS and TDQS,TDQS (x8 devices only) pins.
A functional representation of the on-die termination is shown below. The individual pull-up and pull-down resistors (RTTpu and RTTpd) are defined as
follows :
VDDQ-VOUT
RTTpu = under the condition that RTTpd is turned off
l Iout l
VOUT
RTTpd = under the condition that RTTpu is turned off
l Iout l
Chip in Termination Mode

ODT
VDDQ
Ipu
Iout=Ipd-Ipu
To
other
RTTPu
circuitry
like DQ
RCV, Iout
... RTTPd
VOUT
Ipd
VSSQ
Figure 12. On-Die Termination : Definition of Voltages and Currents
- 20 -
Rev. 1.0

9.8.1 ODT DC Electrical Characteristics
Table 25 provides and overview of the ODT DC electrical characteristics. They values for RTT60pd120, RTT60pu120, RTT120pd240, RTT120pu240, RTT40pd80,
RTT40pu80, RTT30pd60, RTT30pu60, RTT20pd40, RTT20pu40 are not specification requirements, but can be used as design guide lines:
[ Table 25 ] ODT DC Electrical Characteristics, assuming RZQ=240ohm +/- 1% entire operating temperature range; after proper ZQ calibration
MR1 (A9,A6,A2) RTT RESISTOR Vout Min Nom Max Unit NOTE
VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ 1,2,3,4

RTT120pd240 0.5XVDDQ 0.9 1.0 1.1 RZQ 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ 1,2,3,4
(0,1,0) 120 ohm VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ 1,2,3,4
RTT120pu240 0.5XVDDQ 0.9 1.0 1.1 RZQ 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ 1,2,3,4
RTT120 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/2 1,2,5
VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/2 1,2,3,4
RTT60pd240 0.5XVDDQ 0.9 1.0 1.1 RZQ/2 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/2 1,2,3,4
(0,0,1) 60 ohm VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ/2 1,2,3,4
RTT60pu240 0.5XVDDQ 0.9 1.0 1.1 RZQ/2 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/2 1,2,3,4
VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/3 1,2,3,4
RTT40pd240 0.5XVDDQ 0.9 1.0 1.1 RZQ/3 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/3 1,2,3,4
RTT40pu240 0.5XVDDQ 0.9 1.0 1.1 RZQ/3 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/3 1,2,3,4
VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/4 1,2,3,4
RTT60pd240 0.5XVDDQ 0.9 1.0 1.1 RZQ/4 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/4 1,2,3,4
RTT60pu240 0.5XVDDQ 0.9 1.0 1.1 RZQ/4 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/4 1,2,3,4
VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/6 1,2,3,4
RTT60pd240 0.5XVDDQ 0.9 1.0 1.1 RZQ/6 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/6 1,2,3,4
RTT60pu240 0.5XVDDQ 0.9 1.0 1.1 RZQ/6 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/6 1,2,3,4
Deviation of VM w.r.t VDDQ/2, ΔVM -5 5 % 1,2,5,6
- 21 -
Rev. 1.0

NOTE :
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra-
tion, see following section on voltage and temperature sensitivity
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS
3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XVDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g.
calibration at 0.2XVDDQ and 0.8XVDDQ.
4. Not a specification requirement, but a design guide line
5. Measurement definition for RTT:
Apply VIH(AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current I(VIL(AC)) respectively
VIH(AC) - VIL(AC)
RTT =
I(VIH(AC)) - I(VIL(AC))
6. Measurement definition for VM and ΔVM : Measure voltage (VM) at test pin (midpoint) with no load
2 x VM
Δ VM = -1 x 100
VDDQ
9.8.2 ODT Temperature and Voltage sensitivity

If temperature and/or voltage change after calibration, the tolerance limits widen according to table below
ΔT = T - T(@calibration); ΔV = VDDQ - VDDQ (@calibration); VDD = VDDQ
[ Table 26 ] ODT Sensitivity Definition

Min Max Units
RTT 0.9 - dRTTdT * |ΔT| - dRTTdV * |ΔV| 1.6 + dRTTdT * |ΔT| + dRTTdV * |ΔV| RZQ/2,4,6,8,12
[ Table 27 ] ODT Voltage and Temperature Sensitivity

Min Max Units
dRTTdT 0 1.5 %/°C
dRTTdV 0 0.15 %/mV

NOTE : These parameters may not be subject to production test. They are verified by design and characterization.
- 22 -
Rev. 1.0

9.9 ODT Timing Definitions
9.9.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in Figure 13.
VDDQ
DUT DQ, DM
CK,CK VTT=
DQS , DQS
RTT VSSQ
TDQS , TDQS
=25 ohm
VSSQ
Timing Reference Points
Figure 13. ODT Timing Reference Load
9.9.2 ODT Timing Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 28 and subsequent figures. Measurement reference settings are provided
in Table 29.
[ Table 28 ] ODT Timing Definitions

Symbol Begin Point Definition End Point Definition Figure
tAON Rising edge of CK - CK defined by the end point of ODTLon Extrapolated point at VSSQ Figure 14
tAONPD Rising edge of CK - CK with ODT being first registered high Extrapolated point at VSSQ Figure 15
tAOF Rising edge of CK - CK defined by the end point of ODTLoff End point: Extrapolated point at VRTT_Nom Figure 16
tAOFPD Rising edge of CK - CK with ODT being first registered low End point: Extrapolated point at VRTT_Nom Figure 17
Rising edge of CK - CK defined by the end point of ODTLcnw, End point: Extrapolated point at VRTT_Wr and VRTT_Nom
tADC Figure 18
ODTLcwn4 of ODTLcwn8 respectively
[ Table 29 ] Reference Settings for ODT Timing Measurements

Measured
RTT_Nom Setting RTT_Wr Setting VSW1[V] VSW2[V] NOTE
Parameter
RZQ/4 NA 0.05 0.10
tAON
RZQ/12 NA 0.10 0.20
RZQ/4 NA 0.05 0.10
tAONPD
RZQ/12 NA 0.10 0.20
RZQ/4 NA 0.05 0.10
tAOF
RZQ/12 NA 0.10 0.20
RZQ/4 NA 0.05 0.10
tAOFPD
RZQ/12 NA 0.10 0.20
tADC RZQ/12 RZQ/2 0.20 0.30
- 23 -
Rev. 1.0
Begin point : Rising edge of CK - CK

defined by the end point of ODTLon
CK
VTT
CK
tAON
TSW2
TSW1
DQ, DM
DQS , DQS VSW2
TDQS , TDQS VSW1
VSSQ VSSQ
End point Extrapolated point at VSSQ
Figure 14. Definition of tAON

with ODT being first registered high
CK
VTT
CK
tAONPD
TSW2
TSW1
DQ, DM
DQS , DQS VSW2
TDQS , TDQS VSW1
VSSQ VSSQ
End point Extrapolated point at VSSQ
Figure 15. Definition of tAONPD

defined by the end point of ODTLoff
CK
VTT
CK
tAOF
End point Extrapolated point at VRTT_Nom
VRTT_Nom
TSW2
DQ, DM TSW1
DQS , DQS VSW2
TDQS , TDQS VSW1
VSSQ
TD_TAON_DEF
Figure 16. Definition of tAOF
- 24 -
Rev. 1.0

with ODT being first registered low
CK
VTT
CK
tAOFPD
VRTT_Nom
TSW2
DQ, DM TSW1
DQS , DQS VSW2
TDQS , TDQS VSW1
VSSQ
Figure 17. Definition of tAOFPD
Begin point : Rising edge of CK - CK Begin point : Rising edge of CK - CK defined by

defined by the end point of ODTLcnw the end point of ODTLcwn4 or ODTLcwn8
CK
VTT
CK
tADC tADC
VRTT_Nom
TSW21 VRTT_Nom
DQ, DM End point TSW22
Extrapolated point VSW2
DQS , DQS at VRTT_Nom TSW11
TDQS , TDQS TSW12
VSW1
VRTT_Wr End point Extrapolated point at VRTT_Wr
VSSQ
Figure 18. Definition of tADC
- 25 -
Rev. 1.0

10. IDD Current Measure Method
10.1 IDD Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and
IDDQ measurements.
- IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and
IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in
IDD currents.
- IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied
together. Any IDD current is not included in IDDQ currents.
Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO
power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ
are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply :

- "0" and "LOW" is defined as VIN <= VILAC(max).
- "1" and "HIGH" is defined as VIN >= VIHAC(min).
- "FLOATING" is defined as inputs are VREF = VDD / 2.
- "Timing used for IDD and IDDQ Measured - Loop Patterns" are provided in Table 30
- "Basic IDD and IDDQ Measurement Conditions" are described in Table 31
- Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 31 through Table 39.
- IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
- Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
- Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW}
- Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH}
- RESET Stable time is : During a Cold Bood RESET (Initialization), current reading is valid once power is stable and RESET has been LOW for 1ms;
During Warm Boot RESET(while operating), current reading is valid after RESET has been LOW for 200ns + tRFC
[ Table 30 ] Timing used for IDD and IDDQ Measured - Loop Patterns
Parameter Bin Unit
6-6-6 7-7-7 9-9-9 11-11-11 13-13-13 14-14-14
tCKmin(IDD) 2.5 1.875 1.5 1.25 1.07 0.935 ns
CL(IDD) 6 7 9 11 13 14 nCK
tRCDmin(IDD) 6 7 9 11 13 14 nCK
tRCmin(IDD) 21 27 33 39 45 50 nCK
tRASmin(IDD) 15 20 24 28 32 36 nCK
tRPmin(IDD) 6 7 9 11 13 14 nCK
x4/x8 16 20 20 24 26 27 nCK
tFAW(IDD)
x16 20 27 30 32 33 38 nCK
x4/x8 4 4 4 5 5 6 nCK
tRRD(IDD)
x16 4 6 5 6 6 7 nCK
tRFC(IDD) - 512Mb 36 48 60 72 85 97 nCK
tRFC(IDD) - 1Gb 44 59 74 88 103 118 nCK
tRFC(IDD) - 2Gb 64 86 107 128 150 172 nCK
tRFC(IDD) - 4Gb 120 160 200 240 281 321 nCK
tRFC(IDD) - 8Gb 140 187 234 280 328 375 nCK
- 26 -
Rev. 1.0
IDD IDDQ
VDD VDDQ
RESET
CK/CK
CKE DQS, DQS RTT = 25 Ohm

CS DQ, DM, VDDQ/2
RAS, CAS, WE TDQS, TDQS
A, BA
ODT
ZQ
VSS VSSQ
[NOTE : DIMM level Output test load condition may be different from above]
Figure 19. Measurement Setup and Test Load for IDD and IDDQ Measurements
Application specific
memory channel IDDQ
environment Test Load
Channel
IDDQ IDDQ
IO Power
Simulation Measurement
Simulation
Correlation
Correction
Channel IO Power
Number
Figure 20. Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement.
- 27 -
Rev. 1.0

[ Table 31 ] Basic IDD and IDDQ Measurement Conditions
Symbol Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: High between ACT and PRE; Command, Address,
IDD0
Bank Address Inputs: partially toggling according to Table 32 on page 31 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active
at a time: 0,0,1,1,2,2,... (see Table 32); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 32
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: High between ACT, RD and PRE; Command,
IDD1
Address, Bank Address Inputs, Data IO: partially toggling according to Table 33 on page 32 ; DM:stable at 0; Bank Activity: Cycling with one bank active at
a time: 0,0,1,1,2,2,... (see Table 33); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 33
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-
IDD2N
gling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode
Registers2); ODT Signal: stable at 0; Pattern Details: see Table 34
Precharge Standby ODT Current
IDD2NT
gling according to Table 35 on page 33 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode
Registers2); ODT Signal: toggling according to Table 35 ; Pattern Details: see Table 35
Precharge Standby ODT IDDQ Current
IDDQ2NT
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;
IDD2P0
Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pre-
charge Power Down Mode: Slow Exi3)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 30 on page 27; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;
IDD2P1
Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pre-
charge Power Down Mode: Fast Exit3)
Precharge Quiet Standby Current
IDD2Q CKE: High; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;
Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0
Active Standby Current
IDD3N
gling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode
Registers2); ODT Signal: stable at 0; Pattern Details: see Table 34
Active Power-Down Current
IDD3P CKE: Low; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;
Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: par-
IDD4R tially toggling according to Table 36 on page 33 ; Data IO: seamless read data burst with different data between one burst and the next one according to
Table 36 ; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 12); Output Buffer and
RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 36
Operating Burst Read IDDQ Current
IDDQ4R
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 30 on page 27 ; BL: 81); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: par-
IDD4W tially toggling according to Table 37 on page 34 ; Data IO: seamless write data burst with different data between one burst and the next one according to
Table 37; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 37); Output Buffer and RTT:
Enabled in Mode Registers2); ODT Signal: stable at HIGH; Pattern Details: see Table 37
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 30 on page 27 ; BL: 81); AL: 0; CS: High between REF; Command, Address, Bank Address
IDD5B
Inputs: partially toggling according to Table 38 on page 34 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38);
Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 38
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Normal5); CKE: Low; External clock: Off; CK and CK:
IDD6
LOW; CL: see Table 30 on page 26 ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self-
Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING
- 28 -
Rev. 1.0

[ Table 31 ] Basic IDD and IDDQ Measurement Conditions
Symbol Description
Self Refresh Current: Extended Temperature Range
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Extended5); CKE: Low; External clock: Off; CK and CK#:
IDD6ET
LOW; CL: see Table 30 on page 26 ; BL: 81); AL: 0; CS#, Command, Address, Bank Address, Data IO: MID-LEVEL;DM:stable at 0; Bank Activity:
Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: MID-LEVEL
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 30 on page 27 ; BL: 81); AL: CL-1; CS: High between ACT and RDA;
IDD7 Command, Address, Bank Address Inputs: partially toggling according to Table 39 on page 35 ; Data IO: read data bursts with different data between one
burst and the next one according to Table 39 ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing,
see Table 39 ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 39
RESET Low Current
IDD8 RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :
FLOATING
NOTE :
1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
6) Read Burst type : Nibble Sequential, set MR0 A[3]=0B
- 29 -
Rev. 1.0

[ Table 32 ] IDD0 Measurement - Loop Pattern1)
Command
Sub-Loop
A[15:11]
Number
BA[2:0]
CK/CK
Data2)
A[9:7]
A[6:3]
A[2:0]
Cycle
A[10]
CKE
RAS
CAS
ODT
WE
CS
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC + 0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC + 1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
Static High
1*nRC + 3, 4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
toggling
... repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary

1*nRC + nRAS PRE 0 0 1 0 0 0 00 0 0 F 0
... repeat 1...4 until 2*nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
- 30 -
Rev. 1.0

Command
Sub-Loop
A[15:11]
Number
BA[2:0]
CK/CK
Data2)
A[9:7]
A[6:3]
A[2:0]
Cycle
A[10]
CKE
RAS
CAS
ODT
WE
CS
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRCD- 1, truncate if necessary
nRCD RD 0 1 0 1 0 0 00 0 0 0 0 00000000
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC + 1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
Static High
1*nRC + 3, 4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
toggling
... repeat pattern nRC + 1,..., 4 until nRC + nRCD - 1, truncate if necessary
1*nRC + nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011
... repeat pattern nRC + 1,..., 4 until nRC +nRAS - 1, truncate if necessary
1*nRC + nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern nRC + 1,..., 4 until 2 * nRC - 1, truncate if necessary
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
[ Table 34 ] IDD2 and IDD3N Measurement - Loop Pattern1)

Command
Sub-Loop
A[15:11]
Number
BA[2:0]
CK/CK
Data2)
A[9:7]
A[6:3]
A[2:0]
Cycle
A[10]
CKE
RAS
CAS
ODT
WE
CS
0 0 D 1 0 0 0 0 0 00 0 0 0 0 -
1 D 1 0 0 0 0 0 00 0 0 0 0 -
2 D 1 1 1 1 0 0 00 0 0 F 0 -
3 D 1 1 1 1 0 0 00 0 0 F 0 -
Static High
1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead

toggling

NOTE :
1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL.
- 31 -
Rev. 1.0

[ Table 35 ] IDD2NT and IDDQ2NT Measurement - Loop Pattern1)
Command
Sub-Loop
A[15:11]
Number
BA[2:0]
CK/CK
Data2)
A[9:7]
A[6:3]
A[2:0]
Cycle
A[10]
CKE
RAS
CAS
ODT
WE
CS
0 0 D 1 0 0 0 0 0 00 0 0 0 0 -
1 D 1 0 0 0 0 0 00 0 0 0 0
2 D 1 1 1 1 0 0 00 0 0 F 0
3 D 1 1 1 1 0 0 00 0 0 F 0
Static High
1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1

toggling

NOTE :
1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL.
[ Table 36 ] IDD4R and IDDQ4R Measurement - Loop Pattern1)

Command
Sub-Loop
A[15:11]
Number
BA[2:0]
CK/CK
Data2)
A[9:7]
A[6:3]
A[2:0]
Cycle
A[10]
ODT
CKE
RAS
CAS
WE
CS
0 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000
1 D 1 0 0 0 0 0 00 0 0 0 0 -
2,3 D,D 1 1 1 1 0 0 00 0 0 0 0 -
4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011
5 D 1 0 0 0 0 0 00 0 0 F 0 -
Static High
6,7 D,D 1 1 1 1 0 0 00 0 0 F 0 -
toggling
1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1

NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
- 32 -
Rev. 1.0

[ Table 37 ] IDD4W Measurement - Loop Pattern1)
Command
Sub-Loop
A[15:11]
Number
BA[2:0]
CK/CK
Data2)
A[9:7]
A[6:3]
A[2:0]
Cycle
A[10]
CKE
RAS
CAS
ODT
WE
CS
0 0 WR 0 1 0 0 1 0 00 0 0 0 0 00000000
1 D 1 0 0 0 1 0 00 0 0 0 0 -
2,3 D,D 1 1 1 1 1 0 00 0 0 0 0 -
4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011
5 D 1 0 0 0 1 0 00 0 0 F 0 -
Static High
6,7 D,D 1 1 1 1 1 0 00 0 0 F 0 -
toggling

NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
[ Table 38 ] IDD5B Measurement - Loop Pattern1)

Command
Sub-Loop
A[15:11]
Number
BA[2:0]
CK/CK
Data2)
A[9:7]
A[6:3]
A[2:0]
Cycle
A[10]
ODT
CKE
RAS
CAS
WE
CS
0 0 REF 0 0 0 1 0 0 00 0 0 0 0 -
1 1,2 D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D,D 1 1 1 1 0 0 00 0 0 F 0 -
5...8 repeat cycles 1...4, but BA[2:0] = 1
Static High

toggling

2 33...nRFC - 1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
- 33 -
Rev. 1.0

Command
Sub-Loop
A[15:11]
Number
BA[2:0]
CK/CK
Data2)
A[9:7]
A[6:3]
A[2:0]
Cycle
A[10]
CKE
RAS
CAS
ODT
WE
CS
0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000
0
2 D 1 0 0 0 0 0 00 0 0 0 0 -
... repeat above D Command until nRRD - 1
nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 -
nRRD + 1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011
1
nRRD + 2 D 1 0 0 0 0 1 00 0 0 F 0 -
... repeat above D Command until 2*nRRD-1
2 2 * nRRD repeat Sub-Loop 0, but BA[2:0] = 2
3 3 * nRRD repeat Sub-Loop 1, but BA[2:0] = 3
D 1 0 0 0 0 3 00 0 0 F 0 -
4 4 * nRRD
Assert and repeat above D Command until nFAW - 1, if necessary
5 nFAW repeat Sub-Loop 0, but BA[2:0] = 4
6 nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5
7 nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6
8 nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7
D 1 0 0 0 0 7 00 0 0 F 0 -
Static High
9 nFAW+4*nRRD
toggling
Assert and repeat above D Command until 2*nFAW - 1, if necessary

2*nFAW+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
2*nFAW+1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011
10
D 1 0 0 0 0 0 00 0 0 F 0 -
2*nFAW+2
Repeat above D Command until 2*nFAW + nRRD - 1
2*nFAW+nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 -
2*nFAW+nRRD+1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000
11
D 1 0 0 0 0 1 00 0 0 0 0 -
2*nFAW+nRRD+2
Repeat above D Command until 2*nFAW + 2*nRRD - 1
12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2
D 1 0 0 0 0 3 00 0 0 0 0 -
14 2*nFAW+4*nRRD
15 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4
16 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5
D 1 0 0 0 0 7 00 0 0 0 0 -
19 3*nFAW+4*nRRD
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation. DQ signals are MID-LEVEL.
- 34 -
Rev. 1.0

11. 4Gb DDR3 SDRAM B-die IDD Specification Table
[ Table 40 ] IDD Specification for 4Gb DDR3 B-die
256Mx16 (K4B4G1646B)
Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Unit NOTE
7-7-7 9-9-9 11-11-11 13-13-13 14-14-14
IDD0 45 48 51 TBD TBD mA
IDD2P0(slow exit) 15 15 15 TBD TBD mA
IDD2P1(fast exit) 15 15 15 TBD TBD mA
IDD2N 20 20 20 TBD TBD mA
IDD2NT 20 25 25 TBD TBD mA
IDDQ2NT 145 145 145 TBD TBD mA
IDD2Q 20 20 20 TBD TBD mA
IDD3P 20 22 22 TBD TBD mA
IDD3N 30 30 31 TBD TBD mA
IDD4R 109 131 151 TBD TBD mA
IDDQ4R 105 105 105 TBD TBD mA
IDD4W 130 158 182 TBD TBD mA
IDD5B 142 145 149 TBD TBD mA
IDD6 15 15 15 TBD TBD mA 2
IDD6ET 19 19 19 TBD TBD mA 3
Full Array TBD TBD TBD TBD TBD mA
IDD6 (Low) 4
Half Array TBD TBD TBD TBD TBD mA
NOTE :
1. VDD condition : 1.45V for 1.35V operation, 1.575V for 1.5V operation
2. Applicable for MR2 setting A6=0 and A7=0. Temperature range for IDD6 is 0 - 85°C.
3. Applicable for MR2 setting A6=0 and A7=1. Temperature range for IDD6ET is 0 - 95°C.
4. Temperature range for IDD6(Low) is -40 - 85°C.
- 36 -
Rev. 1.0

12. Input/Output Capacitance
[ Table 41 ] Input/Output Capacitance
Parameter Symbol Units NOTE
Input/output capacitance
CIO 1.4 3.0 1.4 2.7 1.4 2.5 1.4 2.3 1.4 2.2 1.4 2.1 pF 1,2,3
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance
CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 1.3 pF 2,3
(CK and CK)
Input capacitance delta
CDCK 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4
(CK and CK)
Input capacitance
CI 0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pF 2,3,5
(All other input-only pins)
CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,6
(DQS and DQS)
CDI_CTRL -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF 2,3,7,8
(All control input-only pins)
CDI_ADD_CMD -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF 2,3,9,10
(all ADD and CMD input-only pins)
Input/output capacitance delta
CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input/output capacitance of ZQ pin CZQ - 3 - 3 - 3 - 3 - 3 - 3 pF 2, 3, 12
NOTE :
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization.
The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with
VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die
termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
- 37 -
Rev. 1.0

13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-2133
13.1 Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3
SDRAM device.
13.1.1 Definition for tCK(avg)

tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to
rising edge.
∑ j=1
tCKj N N=200
13.1.2 Definition for tCK(abs)

tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to produc-
tion test.
13.1.3 Definition for tCH(avg) and tCL(avg)

tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses:
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses:
N N
∑j=1
tCHj N x tCK(avg) N=200 ∑ tCLj N x tCK(avg) N=200
j=1
13.1.4 Definition for note for tJIT(per), tJIT(per, Ick)

tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not subject to production test.
13.1.5 Definition for tJIT(cc), tJIT(cc, Ick)

tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi}
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not subject to production test.
13.1.6 Definition for tERR(nper)

tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test.
- 38 -
Rev. 1.0

13.2 Refresh Parameters by Device Density
[ Table 42 ] Refresh parameters by device density
Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units NOTE
All Bank Refresh to active/refresh cmd time tRFC 110 160 260 350 ns
0 °C ≤ TCASE ≤ 85°C 7.8 7.8 7.8 7.8 μs
Average periodic refresh interval tREFI -40 °C ≤ TCASE ≤ 85°C 7.8 7.8 7.8 7.8 μs 2
85 °C < TCASE ≤ 95°C 3.9 3.9 3.9 3.9 μs 1
NOTE :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in
this material.
2.Supported only for Industrial Temperature.
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
[ Table 43 ] DDR3-800 Speed Bins

Speed DDR3-800
CL-nRCD-nRP 6-6-6 Units NOTE
Parameter Symbol min max
Internal read command to first data tAA 15 20 ns
ACT to internal read or write delay time tRCD 15 - ns
PRE command period tRP 15 - ns
ACT to ACT or REF command period tRC 52.5 - ns
ACT to PRE command period tRAS 37.5 9*tREFI ns
CL = 5 CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,11,12
CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3
Supported CL Settings 5,6 nCK
Supported CWL Settings 5 nCK
[ Table 44 ] DR3-1066 Speed Bins

Speed DDR3-1066
Internal read command to first data tAA 13.125 20 ns
ACT to internal read or write delay time tRCD 13.125 - ns
PRE command period tRP 13.125 - ns
ACT to PRE command period tRAS 37.5 9*tREFI ns
1,2,3,4,5,11,
CWL = 5 tCK(AVG) 3.0 3.3 ns
CL = 5 12
CWL = 6 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,5
CL = 6
CWL = 6 tCK(AVG) Reserved ns 1,2,3,4
CL = 7
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,10
CL = 8
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3
Supported CL Settings 5,6,7,8 nCK
Supported CWL Settings 5,6 nCK
- 39 -
Rev. 1.0

Speed DDR3-1333
CL-nRCD-nRP 9 -9 - 9 Units NOTE
13.5
Internal read command to first data tAA 20 ns
(13.125)10
13.5
ACT to internal read or write delay time tRCD - ns
(13.125)10
13.5
PRE command period tRP - ns
(13.125)10
49.5
ACT to ACT or REF command period tRC - ns
(49.125)10
ACT to PRE command period tRAS 36 9*tREFI ns
1,2,3,4,6,11,
CL = 5 12
CWL = 6,7 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,6
CL = 6 CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,6
CL = 7 CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,6
CL = 8 CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,6
CL = 9
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,10
CL = 10
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3
Supported CL Settings 5,6,7,8,9,10 nCK
Supported CWL Settings 5,6,7 nCK
- 40 -
Rev. 1.0

Speed DDR3-1600
13.75
(13.125)10
13.75
(13.125)10
13.75
(13.125)10
48.75
(48.125)10
1,2,3,4,7,11,
CL = 5 12
CWL = 6,7,8 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,7
CWL = 7, 8 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,7
CL = 7
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,7
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,7
CL = 8
CL = 9 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,7
CL = 10 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,7
CL = 11
CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3,10
Supported CL Settings 5,6,7,8,9,10,11 nCK
Supported CWL Settings 5,6,7,8 nCK
- 41 -
Rev. 1.0

Speed DDR3-1866
13.91
(13.125)13
13.91
(13.125)13
13.91
(13.125)13
47.91
(47.125)13
1,2,3,4,8,11,
CL = 5 12
CWL = 6,7,8,9 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,8
CL = 7 CWL = 6 tCK(AVG) 1.875 2.5 ns 1,2,3,4,8
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,8
CL = 8
CWL = 7 tCK(AVG) 1.5 1.875 ns 1,2,3,4,8
CL = 9
CL = 10 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,8
CL = 11 CWL = 8 tCK(AVG) 1.25 1.5 ns 1,2,3,4,8
CL = 12
CL = 13
CWL = 9 tCK(AVG) 1.07 <1.25 ns 1,2,3,10
Supported CL Settings 5,6,7,8,9,10,11,13 nCK
Supported CWL Settings 5,6,7,8,9 nCK
- 42 -
Rev. 1.0

Speed DDR3-2133
Internal read command to first data tAA 13.09 20 ns
ACT to internal read or write delay time tRCD 13.09 - ns
PRE command period tRP 13.09 - ns
1,2,3,4,9,11,
CL = 5 12
CWL = 6,7,8,9,10 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,9
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,9
CL = 7
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,9
CL = 8
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,9
CL = 9
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,9
CL = 10
CWL = 8,9 tCK(AVG) Reserved ns 1,2,3,4,9
CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3,9
CL = 11
CL = 13 CWL = 9 tCK(AVG) 1.07 <1.25 ns 1,2,3,9
CWL = 5,6,7,8,9 tCK(AVG) Reserved ns 4
CL = 14
CWL = 10 tCK(AVG) 0.935 <1.07 ns 1,2,3,10
Supported CL Settings 5,6,7,8,9,10,11,13,14 nCK
Supported CWL Settings 5,6,7,8,9,10 nCK
- 43 -
Rev. 1.0

13.3.1 Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
NOTE :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-
anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],
rounding up to the next "Supported CL".
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or
1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. "Reserved" settings are not allowed. User must program a different value.
5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
Characterization.
Characterization.
Characterization.
Characterization.
10. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,
DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte
20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte
18), and tRPmin (Byte 20). DDR3-1866(CL13) devices supporting downshift to DDR3-1600(CL11) or DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in
SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-2133(CL14) devices supporting downshift to DDR3-1866(CL13) or DDR3-1600(CL11) or
DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is pro-
grammed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and
48.125ns (tRASmin+tRPmin=35ns+13.125ns) for DDR3-1600(CL11).
11. DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.
12. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not mandatory in SPD coding.
13. For devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin must be 13.125ns. SPD setting must be programed to match. For example,
DDR3-1866 devices supporting down binning to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in SPD bytes for tAAmin(byte16), tRCDmin(Byte18) and
tRPmin (byte20). Once tRP (Byte20) is programmed to 13.125ns, tRCmin (Byte21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRP-
min = 34ns + 13.125ns)
- 44 -
Rev. 1.0

14. Timing Parameters by Speed Grade
[ Table 49 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333 (Cont.)
Speed DDR3-800 DDR3-1066 DDR3-1333
Units NOTE
Parameter Symbol MIN MAX MIN MAX MIN MAX
Clock Timing
Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OFF) 8 - 8 - 8 - ns 6
Average Clock Period tCK(avg) See Speed Bins Table ps

tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max +
Clock Period tCK(abs) tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max
ps
Average high pulse width tCH(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)
Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)
Clock Period Jitter tJIT(per) -100 100 -90 90 -80 80 ps
Clock Period Jitter during DLL locking period tJIT(per, lck) -90 90 -80 80 -70 70 ps
Cycle to Cycle Period Jitter tJIT(cc) 200 180 160 ps
Cycle to Cycle Period Jitter during DLL locking period tJIT(cc, lck) 180 160 140 ps
Cumulative error across 2 cycles tERR(2per) - 147 147 - 132 132 - 118 118 ps
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
Cumulative error across n = 13, 14 ... 49, 50 cycles tERR(nper) ps 24
tERR(nper)max = (1 + 0.68ln(n))*tJIT(per)max
Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - 0.43 - tCK(avg) 25
Absolute clock Low pulse width tCL(abs) 0.43 - 0.43 - 0.43 - tCK(avg) 26
Data Timing
DQS,DQS to DQ skew, per group, per access tDQSQ - 200 - 150 - 125 ps 13
DQ output hold time from DQS, DQS tQH 0.38 - 0.38 - 0.38 - tCK(avg) 13, g
DQ low-impedance time from CK, CK tLZ(DQ) -800 400 -600 300 -500 250 ps 13,14, f
DQ high-impedance time from CK, CK tHZ(DQ) - 400 - 300 - 250 ps 13,14, f

tDS(base)
AC175
75 - 25 - - - ps d, 17
Data setup time to DQS, DQS referenced
to VIH(AC)VIL(AC) levels tDS(base)
AC150
125 - 75 - 30 - ps d, 17
Data hold time to DQS, DQS referenced tDH(base)

to VIH(DC)VIL(DC) levels DC100
150 - 100 - 65 - ps d, 17
DQ and DM Input pulse width for each input tDIPW 600 - 490 - 400 - ps 28
Data Strobe Timing
DQS, DQS differential READ Preamble tRPRE 0.9 NOTE 19 0.9 NOTE 19 0.9 NOTE 19 tCK 13, 19, g
DQS, DQS differential READ Postamble tRPST 0.3 NOTE 11 0.3 NOTE 11 0.3 NOTE 11 tCK 11, 13, b
DQS, DQS differential output high time tQSH 0.38 - 0.38 - 0.4 - tCK(avg) 13, g
DQS, DQS differential output low time tQSL 0.38 - 0.38 - 0.4 - tCK(avg) 13, g
DQS, DQS differential WRITE Preamble tWPRE 0.9 - 0.9 - 0.9 - tCK
DQS, DQS differential WRITE Postamble tWPST 0.3 - 0.3 - 0.3 - tCK
DQS, DQS rising edge output access time from rising CK, CK tDQSCK -400 400 -300 300 -255 255 ps 13,f
DQS, DQS low-impedance time (Referenced from RL-1) tLZ(DQS) -800 400 -600 300 -500 250 ps 13,14,f
DQS, DQS high-impedance time (Referenced from RL+BL/2) tHZ(DQS) - 400 - 300 - 250 ps 12,13,14
DQS, DQS differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 tCK 29, 31
DQS, DQS differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 tCK 30, 31
DQS, DQS rising edge to CK, CK rising edge tDQSS -0.25 0.25 -0.25 0.25 -0.25 0.25 tCK(avg) c
DQS,DQS falling edge setup time to CK, CK rising edge tDSS 0.2 - 0.2 - 0.2 - tCK(avg) c, 32
DQS,DQS falling edge hold time to CK, CK rising edge tDSH 0.2 - 0.2 - 0.2 - tCK(avg) c, 32
- 45 -
Rev. 1.0

Units NOTE
Command and Address Timing
DLL locking time tDLLK 512 - 512 - 512 - nCK
max max max

internal READ Command to PRECHARGE Command delay tRTP - - - e
(4nCK,7.5ns) (4nCK,7.5ns) (4nCK,7.5ns)
Delay from start of internal write transaction to internal read com- max max max
tWTR - - - e,18
mand (4nCK,7.5ns) (4nCK,7.5ns) (4nCK,7.5ns)
WRITE recovery time tWR 15 - 15 - 15 - ns e
Mode Register Set command cycle time tMRD 4 - 4 - 4 - nCK
max max max

Mode Register Set command update delay tMOD - - -
(12nCK,15ns) (12nCK,15ns) (12nCK,15ns)
CAS to CAS command delay tCCD 4 - 4 - 4 - nCK
Auto precharge write recovery + precharge time tDAL(min) WR + roundup (tRP / tCK(AVG)) nCK
Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - nCK 22
ACTIVE to PRECHARGE command period tRAS See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 42 ns e
max max max

ACTIVE to ACTIVE command period for 1KB page size tRRD - - - e
(4nCK,10ns) (4nCK,7.5ns) (4nCK,6ns)
max max max
(4nCK,10ns) (4nCK,10ns) (4nCK,7.5ns)
Four activate window for 1KB page size tFAW 40 - 37.5 - 30 - ns e
Four activate window for 2KB page size tFAW 50 - 50 - 45 - ns e
tIS(base)
AC175
200 - 125 - 65 - ps b,16
Command and Address setup time to CK, CK referenced to
VIH(AC) / VIL(AC) levels tIS(base)
AC150
200+150 - 125+150 - 65+125 - ps b,16,27
Command and Address hold time from CK, CK referenced to tIH(base)

VIH(DC) / VIL(DC) levels DC100
275 - 200 - 140 - ps b,16
Control & Address Input pulse width for each input tIPW 900 - 780 - 620 - ps 28
Calibration Timing
Power-up and RESET calibration time tZQinitI 512 - 512 - 512 - nCK
Normal operation Full calibration time tZQoper 256 - 256 - 256 - nCK
Normal operation short calibration time tZQCS 64 - 64 - 64 - nCK 23
Reset Timing
max(5nCK, max(5nCK, max(5nCK,

Exit Reset from CKE HIGH to a valid command tXPR - - -
tRFC + 10ns) tRFC + 10ns) tRFC + 10ns)
Self Refresh Timing
max(5nCK,tRF max(5nCK,tRF max(5nCK,tRF

Exit Self Refresh to commands not requiring a locked DLL tXS - - -
C + 10ns) C + 10ns) C + 10ns)
Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min) - tDLLK(min) - tDLLK(min) - nCK
tCKE(min) + tCKE(min) + tCKE(min) +

Minimum CKE low width for Self refresh entry to exit timing tCKESR - - -
1tCK 1tCK 1tCK
Valid Clock Requirement after Self Refresh Entry (SRE) or Power- max(5nCK, max(5nCK, max(5nCK,
tCKSRE - - -
Down Entry (PDE) 10ns) 10ns) 10ns)
Valid Clock Requirement before Self Refresh Exit (SRX) or Power- max(5nCK, max(5nCK, max(5nCK,
tCKSRX - - -
Down Exit (PDX) or Reset Exit 10ns) 10ns) 10ns)
- 46 -
Rev. 1.0

[ Table 49 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333
Units NOTE
Power Down Timing
Exit Power Down with DLL on to any valid command;Exit Pre- max max
max
charge Power Down with DLL tXP (3nCK, - (3nCK, - -
(3nCK,6ns)
frozen to commands not requiring a locked DLL 7.5ns) 7.5ns)
max max max

Exit Precharge Power Down with DLL frozen to commands re-
tXPDLL (10nCK, - (10nCK, - (10nCK, - 2
quiring a locked DLL
24ns) 24ns) 24ns)
max max max
CKE minimum pulse width tCKE (3nCK, - (3nCK, - (3nCK, -
7.5ns) 5.625ns) 5.625ns)
Command pass disable delay tCPDED 1 - 1 - 1 - nCK
Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCK 15
Timing of ACT command to Power Down entry tACTPDEN 1 - 1 - 1 - nCK 20
Timing of PRE command to Power Down entry tPRPDEN 1 - 1 - 1 - nCK 20
Timing of RD/RDA command to Power Down entry tRDPDEN RL + 4 +1 - RL + 4 +1 - RL + 4 +1 -
WL + 4 WL + 4 WL + 4
Timing of WR command to Power Down entry
tWRPDEN +(tWR/ - +(tWR/ - +(tWR/ - nCK 9
(BL8OTF, BL8MRS, BC4OTF)
tCK(avg)) tCK(avg)) tCK(avg))
Timing of WRA command to Power Down entry
tWRAPDEN WL+4+WR +1 - WL+4+WR+1 - WL+4+WR+1 - nCK 10
(BL8OTF, BL8MRS, BC4OTF)
WL + 2 WL + 2 WL + 2
Timing of WR command to Power Down entry
tWRPDEN +(tWR/ - +(tWR/ - +(tWR/ - nCK 9
(BC4MRS)
tCK(avg)) tCK(avg)) tCK(avg))
Timing of WRA command to Power Down entry WL +2 +WR WL +2 +WR WL +2 +WR
tWRAPDEN - - - nCK 10
(BC4MRS) +1 +1 +1
Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 1 - 20,21
Timing of MRS command to Power Down entry tMRSPDEN tMOD(min) - tMOD(min) - tMOD(min) -
ODT Timing
ODT high time without write command or with write command

ODTH4 4 - 4 - 4 - nCK
and BC4
ODT high time with Write command and BL8 ODTH8 6 - 6 - 6 - nCK
Asynchronous RTT turn-on delay (Power-Down with DLL fro-

tAONPD 2 8.5 2 8.5 2 8.5 ns
zen)
Asynchronous RTT turn-off delay (Power-Down with DLL fro-

tAOFPD 2 8.5 2 8.5 2 8.5 ns
zen)
RTT turn-on tAON -400 400 -300 300 -250 250 ps 7,f
RTT_NOM and RTT_WR turn-off time from ODTLoff reference tAOF 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) 8,f
RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) f
Write Leveling Timing
First DQS/DQS rising edge after write leveling mode is tWLMRD 40 - 40 - 40 - tCK 3
programmed
DQS/DQS delay after write leveling mode is programmed tWLDQSEN 25 - 25 - 25 - tCK 3
Write leveling setup time from rising CK, CK crossing to rising

tWLS 325 - 245 - 195 - ps
DQS, DQS crossing
Write leveling hold time from rising DQS, DQS crossing to rising
tWLH 325 - 245 - 195 - ps
CK, CK crossing
Write leveling output delay tWLO 0 9 0 9 0 9 ns
Write leveling output error tWLOE 0 2 0 2 0 2 ns
- 47 -
Rev. 1.0

Units NOTE
Clock Timing
Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OFF) 8 - 8 - 8 - ns 6
Average Clock Period tCK(avg) See Speed Bins Table ps

tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max +
Clock Period tCK(abs) tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max
ps
Average high pulse width tCH(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)
Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)
Clock Period Jitter tJIT(per) -70 70 -60 60 -50 50 ps
Clock Period Jitter during DLL locking period tJIT(per, lck) -60 60 -50 50 -40 40 ps
Cycle to Cycle Period Jitter tJIT(cc) 140 120 100 ps
Cycle to Cycle Period Jitter during DLL locking period tJIT(cc, lck) 120 100 80 ps
Cumulative error across 2 cycles tERR(2per) -103 103 -88 88 -74 74 ps
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
Cumulative error across n = 13, 14 ... 49, 50 cycles tERR(nper) ps 24
tERR(nper)max = (1 + 0.68ln(n))*tJIT(per)max
Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - 0.43 - tCK(avg) 25
Absolute clock Low pulse width tCL(abs) 0.43 - 0.43 - 0.43 - tCK(avg) 26
Data Timing
DQS,DQS to DQ skew, per group, per access tDQSQ - 100 - 85 - 75 ps 13
DQ output hold time from DQS, DQS tQH 0.38 - 0.38 - 0.38 - tCK(avg) 13, g
DQ low-impedance time from CK, CK tLZ(DQ) -450 225 -390 195 -360 180 ps 13,14, f
DQ high-impedance time from CK, CK tHZ(DQ) - 225 - 195 - 180 ps 13,14, f
tDS(base)
AC150
10 - - - - - ps d, 17
Data setup time to DQS, DQS referenced
to VIH(AC)VIL(AC) levels tDS(base)
AC135
- - 0 - -15 - ps d, 17
Data hold time to DQS, DQS referenced tDH(base)

to VIH(DC)VIL(DC) levels DC100
45 - 20 - 5 - ps d, 17
DQ and DM Input pulse width for each input tDIPW 360 - 320 - 280 - ps 28
Data Strobe Timing
DQS, DQS differential READ Preamble tRPRE 0.9 NOTE 19 0.9 NOTE 19 0.9 NOTE 19 tCK 13, 19, g
DQS, DQS differential READ Postamble tRPST 0.3 NOTE 11 0.3 NOTE 11 0.3 NOTE 11 tCK 11, 13, b
DQS, DQS differential output high time tQSH 0.4 - 0.4 - 0.4 - tCK(avg) 13, g
DQS, DQS differential output low time tQSL 0.4 - 0.4 - 0.4 - tCK(avg) 13, g
DQS, DQS differential WRITE Preamble tWPRE 0.9 - 0.9 - 0.9 - tCK
DQS, DQS differential WRITE Postamble tWPST 0.3 - 0.3 - 0.3 - tCK
DQS, DQS rising edge output access time from rising CK, CK tDQSCK -225 225 -195 195 -180 180 ps 13,f
DQS, DQS low-impedance time (Referenced from RL-1) tLZ(DQS) -450 225 -390 195 -360 180 ps 13,14,f
DQS, DQS high-impedance time (Referenced from RL+BL/2) tHZ(DQS) - 225 - 195 - 180 ps 12,13,14
DQS, DQS differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 tCK 29, 31
DQS, DQS differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 tCK 30, 31
DQS, DQS rising edge to CK, CK rising edge tDQSS -0.27 0.27 -0.27 0.27 -0.27 0.27 tCK(avg) c
DQS,DQS falling edge setup time to CK, CK rising edge tDSS 0.18 - 0.18 - 0.18 - tCK(avg) c, 32
DQS,DQS falling edge hold time to CK, CK rising edge tDSH 0.18 - 0.18 - 0.18 - tCK(avg) c, 32
- 48 -
Rev. 1.0

Units NOTE
Command and Address Timing
DLL locking time tDLLK 512 - 512 - 512 - nCK
max max max

internal READ Command to PRECHARGE Command delay tRTP - - - e
(4nCK,7.5ns) (4nCK,7.5ns) (4nCK,7.5ns)
Delay from start of internal write transaction to internal read com- max max max
tWTR - - - e,18
mand (4nCK,7.5ns) (4nCK,7.5ns) (4nCK,7.5ns)
WRITE recovery time tWR 15 - 15 - 15 - ns e
Mode Register Set command cycle time tMRD 4 - 4 - 4 - nCK
max max max

Mode Register Set command update delay tMOD - - -
(12nCK,15ns) (12nCK,15ns) (12nCK,15ns)
CAS to CAS command delay tCCD 4 - 4 - 4 - nCK
Auto precharge write recovery + precharge time tDAL(min) WR + roundup (tRP / tCK(AVG)) nCK
Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - nCK 22
ACTIVE to PRECHARGE command period tRAS See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 42 ns e
max max max

(4nCK,6ns) (4nCK, 5ns) (4nCK, 5ns)
max max max
(4nCK,7.5ns) (4nCK, 6ns) (4nCK, 6ns)
tIS(base)
45 - - - - - ps b,16
AC175
tIS(base)
170 - - - - - ps b,16
Command and Address setup time to CK, CK referenced to AC150
VIH(AC) / VIL(AC) levels tIS(base)
AC135
- - 65 - 60 - ps b,16
tIS(base)
AC125
- - 150 - 135 - ps b,16,27
Command and Address hold time from CK, CK referenced to tIH(base)

VIH(DC) / VIL(DC) levels DC100
120 - 100 - 95 - ps b,16
Control & Address Input pulse width for each input tIPW 560 - 535 - 470 - ps 28
Calibration Timing
max(512nCK,6 max(512nCK,64
Power-up and RESET calibration time tZQinitI 512 - - - nCK
40ns) 0ns)
max(256nCK,3 max(256nCK,32
Normal operation Full calibration time tZQoper 256 - - - nCK
20ns) 0ns)
max(64nCK,80 max(64nCK,80n
Normal operation short calibration time tZQCS 64 - - - nCK 23
ns) s)
Reset Timing
max(5nCK, max(5nCK,
max(5nCK,
Exit Reset from CKE HIGH to a valid command tXPR - tRFC(min) + - tRFC(min) + -
tRFC + 10ns)
10ns) 10ns)
Self Refresh Timing
max(5nCK,tRF max(5nCK,tRF max(5nCK,tRFC

Exit Self Refresh to commands not requiring a locked DLL tXS - - -
C + 10ns) C(min) + 10ns) (min) + 10ns)
Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min) - tDLLK(min) - tDLLK(min) - nCK
tCKE(min) + tCKE(min) + tCKE(min) +

Minimum CKE low width for Self refresh entry to exit timing tCKESR - - -
1tCK 1nCK 1nCK
Valid Clock Requirement after Self Refresh Entry (SRE) or Power- max(5nCK, max(5nCK, max(5nCK,
tCKSRE - - -
Down Entry (PDE) 10ns) 10ns) 10ns)
Valid Clock Requirement before Self Refresh Exit (SRX) or Power- max(5nCK, max(5nCK, max(5nCK,
tCKSRX - - -
Down Exit (PDX) or Reset Exit 10ns) 10ns) 10ns)
- 49 -
Rev. 1.0

[ Table 50 ] Timing Parameters by Speed Bins for DDR3-1600 to DDR3-2133
Units NOTE
Power Down Timing
Exit Power Down with DLL on to any valid command;Exit Pre-

max max(3nCK,6ns max(3nCK,6n
charge Power Down with DLL tXP - - -
(3nCK,6ns) ) s)
frozen to commands not requiring a locked DLL
max
Exit Precharge Power Down with DLL frozen to commands re- max(10nCK,24 max(10nCK,2
tXPDLL (10nCK, - - - 2
quiring a locked DLL ns) 4ns)
24ns)
max max(3nCK,5ns max(3nCK,5n
CKE minimum pulse width tCKE - - -
(3nCK,5ns) ) s)
Command pass disable delay tCPDED 1 - 2 - 2 - nCK
Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCK 15
Timing of ACT command to Power Down entry tACTPDEN 1 - 1 - 2 - nCK 20
Timing of PRE command to Power Down entry tPRPDEN 1 - 1 - 2 - nCK 20
Timing of RD/RDA command to Power Down entry tRDPDEN RL + 4 +1 - RL + 4 +1 - RL + 4 +1 -
WL + 4
Timing of WR command to Power Down entry WL + 4 +(tWR/ WL + 4 +(tWR/
tWRPDEN +(tWR/ - - - nCK 9
(BL8OTF, BL8MRS, BC4OTF) tCK(avg)) tCK(avg))
tCK(avg))
Timing of WRA command to Power Down entry WL + 4 +WR WL + 4 +WR WL + 4 +WR

tWRAPDEN - - - nCK 10
(BL8OTF, BL8MRS, BC4OTF) +1 +1 +1
WL + 2
Timing of WR command to Power Down entry WL + 2 +(tWR/ WL + 2 +(tWR/
tWRPDEN +(tWR/ - - - nCK 9
(BC4MRS) tCK(avg)) tCK(avg))
tCK(avg))
Timing of WRA command to Power Down entry WL +2 +WR WL +2 +WR

tWRAPDEN - WL +2 +WR +1 - - nCK 10
(BC4MRS) +1 +1
Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 2 - 20,21
Timing of MRS command to Power Down entry tMRSPDEN tMOD(min) - tMOD(min) - tMOD(min) -
ODT Timing
ODT high time without write command or with write command

ODTH4 4 - 4 - 4 - nCK
and BC4
ODT high time with Write command and BL8 ODTH8 6 - 6 - 6 - nCK
Asynchronous RTT turn-on delay (Power-Down with DLL fro-

tAONPD 2 8.5 2 8.5 2 8.5 ns
zen)
Asynchronous RTT turn-off delay (Power-Down with DLL fro-

tAOFPD 2 8.5 2 8.5 2 8.5 ns
zen)
RTT turn-on tAON -225 225 -195 195 -180 180 ps 7,f
RTT_NOM and RTT_WR turn-off time from ODTLoff reference tAOF 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) 8,f
RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) f
Write Leveling Timing
First DQS/DQS rising edge after write leveling mode is tWLMRD 40 - 40 - 40 - tCK 3
programmed
DQS/DQS delay after write leveling mode is programmed tWLDQSEN 25 - 25 - 25 - tCK 3
Write leveling setup time from rising CK, CK crossing to rising

tWLS 165 - 140 - 125 - ps
DQS, DQS crossing
Write leveling hold time from rising DQS, DQS crossing to rising
tWLH 165 - 140 - 125 - ps
CK, CK crossing
Write leveling output delay tWLO 0 7.5 0 7.5 0 7.5 ns

Write leveling output error tWLOE 0 2 0 2 0 2 ns
- 50 -
Rev. 1.0

14.1 Jitter Notes
Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the
input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm,
another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Specific Note b These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition
edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is,
these parameters should be met whether clock jitter is present or not.
Specific Note c These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK)
crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative
to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note d These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data
strobe signal (DQS(L/U), DQS(L/U)) crossing.
Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},
which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the
device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge com-
mand at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.
Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input
clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = +
193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(der-
ated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to
tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the
min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=
12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input
clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has
tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min +
tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) =
tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/
max usage!)
- 51 -
Rev. 1.0

14.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register
5. Value must be rounded-up to next higher integer value
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"
8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing
Diagram Datasheet.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated by TBD
13. Value is only valid for RON34
14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.
15. tREFI depends on TOPER
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,
VREF(DC) = VREFDQ(DC). For input only pins except RESET, VREF(DC)=VREFCA(DC).
See "Address/Command Setup, Hold and Derating :" on page 54. .
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,
VREF(DC)= VREFDQ(DC). For input only pins except RESET, VREF(DC)=VREFCA(DC).
See "Data Setup, Hold and Slew Rate Derating :" on page 61.
18. Start of internal write transaction is defined as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram
Datasheet"
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time
such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming
the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-
ject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu-
lated as:
0.5
= 0.133 ~
~ 128ms
(1.5 x 1) + (0.15 x 15)
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125 ps for DDR3-800/1066 or 100ps for DDR3-
1333/1600 of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point [(175mv - 150
mV) / 1 V/ns].
28. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC)
29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.
30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.
31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
33. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75ps for DDR3-1866 and 65ps for DDR3-2133
to accommodate for the lower alternate threshold of 125mV and another 10ps to account for the earlier reference point [(135mv - 125mV) / 1 V/ns].
- 52 -
Rev. 1.0

14.3 Address/Command Setup, Hold and Derating :
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see
Table 51) to the ΔtIS and ΔtIH derating value (see Table 52) respectively.
Example: tIS (total setup time) = tIS(base) + ΔtIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(DC) to ac
region’, use nominal slew rate for derating value (see Figure 21). If the actual signal is later than the nominal slew rate line anywhere between shaded
’VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 23).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC).
Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If
the actual signal is always later than the nominal slew rate line between shaded ’dc to VREF(DC) region’, use nominal slew rate for derating value (see
Figure 22). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line
to the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 24).
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see Table 56).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in Table 52, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[ Table 51 ] ADD/CMD Setup and Hold Base-Values for 1V/ns

[ps] DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 reference
tIS(base) AC175 200 125 65 45 - - VIH/L(AC)
tIS(base) AC150 350 275 190 170 - - VIH/L(AC)
tIS(base)-AC135 - - - - 65 60 VIH/L(AC)
tIS(base)-AC125 - - - - 150 135 VIH/L(AC)
tIH(base)-DC100 275 200 140 120 100 95 VIH/L(DC)
NOTE :
1. AC/DC referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-Ck slew rate
2. The tIS(base)-AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125ps for DDR3-800/1066 or 100ps for
DDR3-1333/1600 of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point
[(175mV-150mV)/1 V/ns]
3. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75ps for DDR3-1866 and 65ps for DDR3-2133 to accommo-
date for the lower alternate threshold of 125mV and another 10ps to account for the earlier reference point [(135mV-125mV)/1V/ns].
[ Table 52 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-AC/DC based AC175 Threshold

ΔtIS, ΔtIH Derating [ps] AC/DC based
Alternate AC175 Threshold -> VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV
CLK,CLK Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100
1.5 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
CMD/
0.9 -2 -4 -2 -4 -2 -4 6 4 14 12 22 20 30 30 38 46
ADD
Slew 0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 18 14 26 24 34 40
rate
0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34
V/ns
0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24
0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10
0.4 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10
- 53 -
Rev. 1.0

[ Table 53 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-AC/DC based - Alternate AC150 Threshold
2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100
1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
CMD/
0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46
ADD
Slew 0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40
rate
0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34
V/ns
0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24
0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10
0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10
[ Table 54 ] Derating values DDR3-1866/2133 tIS/tIH-AC/DC based Alternate AC135 Threshold

2.0 68 50 68 50 68 50 76 58 84 66 92 74 100 84 108 100
1.5 45 34 45 34 45 34 53 42 61 50 69 58 77 68 85 84
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
CMD/
ADD 0.9 2 -4 2 -4 2 -4 10 4 18 12 26 20 34 30 42 46
Slew 0.8 3 -10 3 -10 3 -10 11 -2 19 6 27 14 35 24 43 40
rate 0.7 6 -16 6 -16 6 -16 14 -8 22 0 30 8 38 18 46 34
V/ns
0.6 9 -26 9 -26 9 -26 17 -18 25 -10 33 -2 41 8 49 24
0.5 5 -40 5 -40 5 -40 13 -32 21 -24 29 -16 37 -6 45 10
0.4 -3 -60 -3 -60 -3 -60 6 -52 14 -44 22 -36 30 -26 38 -10
- 54 -
Rev. 1.0

[ Table 55 ] Derating values DDR3-1866/2133 tIS/tIH-AC/DC based - Alternate AC125 Threshold
2.0 63 50 63 50 63 50 71 58 79 66 87 74 95 84 103 100
1.5 42 34 42 34 42 34 50 42 58 50 66 58 74 68 82 84
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
CMD/
0.9 4 -4 4 -4 4 -4 12 4 20 12 28 20 36 30 44 46
ADD
Slew 0.8 6 -10 6 -10 6 -10 14 -2 22 6 30 14 38 24 46 40
rate
0.7 11 -16 11 -16 11 -16 19 -8 27 0 35 8 43 18 51 34
V/ns
0.6 16 -26 16 -26 16 -26 24 -18 32 -10 40 -2 48 8 56 24
0.5 15 -40 15 -40 15 -40 23 -32 31 -24 39 -16 47 -6 55 10
0.4 13 -60 13 -60 13 -60 21 -52 29 -44 37 -36 45 -26 53 -10
[ Table 56 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid ADD/CMD transition
tVAC @175mV [ps] tVAC @150mV [ps] tVAC @135mV [ps] tVAC @125mV [ps]
Slew Rate[V/ns]
>2.0 75 - 175 - 168 - 173 -
2.0 57 - 170 - 168 - 173 -
1.5 50 - 167 - 145 - 152 -
1.0 38 - 130 - 100 - 110 -
0.9 34 - 113 - 85 - 96 -
0.8 29 - 93 - 66 - 79 -
0.7 22 - 66 - 42 - 56 -
0.6 Note - 30 - 10 - 56 -
0.5 Note - Note - Note - Note -
< 0.5 Note - Note - Note - Note -
NOTE : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
- 55 -
Rev. 1.0
NOTE :Clock and Strobe are drawn on a different time scale.
tIS tIH tIS tIH

CK
CK
DQS
DQS
tDS tDH tDS tDH

VDDQ
tVAC
VIH(AC) min
VREF to ac
region
VIH(DC) min
nominal
slew rate
VREF(DC)
nominal slew
rate
VIL(DC) max
VREF to ac
region
VIL(AC) max
tVAC
VSS
Δ TF Δ TR
Setup Slew Rate = VREF(DC) - VIL(AC)max Setup Slew Rate V (AC)min - VREF(DC)
= IH
Falling Signal Δ TF Rising Signal Δ TR
Figure 21. Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
- 56 -
Rev. 1.0
tIS tIH tIS tIH
CK
CK
DQS
DQS
tDS tDH tDS tDH

VDDQ
VIH(AC) min
VIH(DC) min
dc to VREF
region nominal
slew rate
VREF(DC)
nominal
slew rate dc to VREF
region
VIL(DC) max
VIL(AC) max
VSS
Δ TR Δ TF
Hold Slew Rate VREF(DC) - VIL(DC)max Hold Slew Rate VIH(DC)min - VREF(DC)
Rising Signal = Δ TR Falling Signal
=
Δ TF
Figure 22. Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH
- 57 -
Rev. 1.0
tIS tIH tIS tIH
CK
CK
DQS
DQS
tDS tDH tDS tDH

VDDQ
nominal tVAC
line
VIH(AC) min
VREF to ac
region
VIH(DC) min
tangent
line
VREF(DC)
tangent
line
VIL(DC) max
VREF to ac
region
VIL(AC) max
nominal
line
tVAC Δ TR
VSS
Setup Slew Rate tangent line[VIH(AC)min - VREF(DC)]

=
Rising Signal Δ TR
Δ TF
Setup Slew Rate tangent line[VREF(DC) - VIL(AC)max]

Falling Signal = Δ TF
Figure 23. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
- 58 -
Rev. 1.0
tIS tIH tIS tIH
CK
CK
DQS
DQS
tDS tDH tDS tDH

VDDQ
VIH(AC) min
nominal
line
VIH(DC) min
dc to VREF
region tangent
line
VREF(DC)
tangent
dc to VREF line
region nominal
line
VIL(DC) max
VIL(AC) max
VSS
Δ TR Δ TF
Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ]

Rising Signal = Δ TR
Hold Slew Rate tangent line [ VIH(DC)min - VREF(DC) ]
Figure 24. Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH
- 59 -
Rev. 1.0

14.4 Data Setup, Hold and Slew Rate Derating :
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value (see
Table 57) to the Δ tDS and ΔtDH (see Table 55) derating value respectively. Example: tDS (total setup time) = tDS(base) + ΔtDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min.
Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max
(see Figure 25). If the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(DC) to ac region’, use nominal slew rate for
derating value. If the actual signal is later than the nominal slew rate line anywhere
between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see
Figure 27).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC).
Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC)
(see Figure ). If the actual signal is always later than the nominal slew rate line between shaded ’dc level to VREF(DC) region’, use nominal slew rate for
derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent
line to the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 28).
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see Table 56).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[ Table 57 ] Data Setup and Hold Base-Values

[ps] DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 reference
tDS(base) AC175 75 25 - - - - VIH/L(AC)
tDS(base) AC150 125 75 30 10 - - VIH/L(AC)
tDS(base) AC135 - - - - 0 -15 VIH/L(AC)
tDH(base) DC100 150 100 65 45 20 5 VIH/L(DC)
NOTE : AC/DC referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate)
[ Table 58 ] Derating values DDR3-800/1066 tDS/tDH - (AC175)

ΔtDS, ΔtDH Derating in [ps] AC/DC based1
DQS,DQS Differential Slew Rate
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0 88 50 88 50 88 50 - - - - - - - - - -
1.5 59 34 59 34 59 34 67 42 - - - - - - - -
1.0 0 0 0 0 0 0 8 8 16 16 - - - - - -
DDR3 DQ
0.9 - - -2 -4 -2 -4 6 4 14 12 22 20 - - - -
- Slew
0.8 - - - - -6 -10 2 -2 10 6 18 14 26 24 - -
800/ rate
0.7 - - - - - - -3 -8 5 0 13 8 21 18 29 34
1066 V/ns
0.6 - - - - - - - - -1 -10 7 -2 15 8 23 24
0.5 - - - - - - - - - - -11 -16 -2 -6 6 10
0.4 - - - - - - - - - - - - -30 -26 -22 -10
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
[ Table 59 ] Derating values for DDR3-800/1066/1333/1600 tDS/tDH - (AC150)

2.0 75 50 75 50 75 50 - - - - - - - - - -
1.5 50 34 50 34 50 34 58 42 - - - - - - - -
1.0 0 0 0 0 0 0 8 8 16 16 - - - - - -
DQ
0.9 - - 0 -4 0 -4 8 4 16 12 24 20 - - - -
Slew
0.8 - - - - 0 -10 8 -2 16 6 24 14 32 24 - -
rate
0.7 - - - - - - 8 -8 16 0 24 8 32 18 40 34
V/ns
0.6 - - - - - - - - 15 -10 23 -2 31 8 39 24
0.5 - - - - - - - - - - 14 -16 22 -6 30 10
0.4 - - - - - - - - - - - - 7 -26 15 -10
- 60 -
Rev. 1.0

[ Table 60 ] Derating values for DDR3-1866/2133 tDS/tDH - (AC135)
2.0 68 50 68 50 68 50 - - - - - - - - - -
1.5 45 34 45 34 45 34 53 42 - - - - - - - -
1.0 0 0 0 0 0 0 8 8 16 16 - - - - - -
DQ
0.9 - - 2 -4 2 -4 10 4 18 12 26 20 - - - -
Slew
0.8 - - - - 3 -10 11 -2 19 6 27 14 35 24 - -
rate
0.7 - - - - - - 14 -8 22 0 30 8 38 18 46 34
V/ns
0.6 - - - - - - - - 25 -10 33 -2 41 8 49 24
0.5 - - - - - - - - - - 29 -16 37 -6 45 10
0.4 - - - - - - - - - - - - 30 -26 38 -10
[ Table 61 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid DQ transition
tVAC[ps] DDR3-1066 tVAC[ps] DDR3-1066/1333/ tVAC[ps] DDR3-1866 tVAC[ps] DDR3-2133
Slew Rate[V/ns] (AC175) 1600 (AC150) (AC135) (AC135)
>2.0 75 - 105 - TBD - TBD -
2.0 57 - 105 - TBD - TBD -
1.5 50 - 80 - TBD - TBD -
1.0 38 - 30 - TBD - TBD -
0.9 34 - 13 - TBD - TBD -
0.8 29 - Note - TBD - TBD -
0.7 Note - Note - TBD - TBD -
<0.5 Note - Note - TBD - TBD -
NOTE : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
- 61 -
Rev. 1.0
tIS tIH tIS tIH

CK
CK
DQS
DQS
tDS tDH tDS tDH

VDDQ
tVAC
VIH(AC) min
VREF to ac
region
VIH(DC) min
nominal
slew rate
VREF(DC)
nominal slew
rate
VIL(DC) max
VREF to ac
region
VIL(AC) max
tVAC
VSS
Δ TF Δ TR
Setup Slew Rate = VREF(DC) - VIL(AC)max Setup Slew Rate V (AC)min - VREF(DC)
= IH
Falling Signal Δ TF Rising Signal Δ TR
Figure 25. Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
- 62 -
Rev. 1.0
tIS tIH tIS tIH
CK
CK
DQS
DQS
tDS tDH tDS tDH

VDDQ
VIH(AC) min
VIH(DC) min
dc to VREF
region nominal
slew rate
VREF(DC)
nominal
slew rate dc to VREF
region
VIL(DC) max
VIL(AC) max
VSS
Δ TR Δ TF
Hold Slew Rate VREF(DC) - VIL(DC)max Hold Slew Rate V (DC)min - VREF(DC)
Rising Signal = Δ TR Falling Signal
= IH
Δ TF
Figure 26. Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH
- 63 -
Rev. 1.0
tIS tIH tIS tIH
CK
CK
DQS
DQS
tDS tDH tDS tDH

VDDQ
nominal tVAC
line
VIH(AC) min
VREF to ac
region
VIH(DC) min
tangent
line
VREF(DC)
tangent
line
VIL(DC) max
VREF to ac
region
VIL(AC) max
nominal
line
tVAC Δ TR
VSS
Setup Slew Rate tangent line[VIH(AC)min - VREF(DC)]

=
Rising Signal Δ TR
Δ TF
Setup Slew Rate tangent line[VREF(DC) - VIL(AC)max]

Figure 27. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
- 64 -
Rev. 1.0
tIS tIH tIS tIH
CK
CK
DQS
DQS
tDS tDH tDS tDH

VDDQ
VIH(AC) min
nominal
line
VIH(DC) min
dc to VREF
region tangent
line
VREF(DC)
tangent
dc to VREF line
region nominal
line
VIL(DC) max
VIL(AC) max
VSS
Δ TR Δ TF
Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ]

Rising Signal = Δ TR
Hold Slew Rate tangent line [ VIH(DC)min - VREF(DC) ]
Figure 28. Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH
- 65 -

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Rev. 1.0, Jan.

4Gb B-die DDR3 SDRAM Olny x16

ⓒ 2012 Samsung Electronics Co., Ltd. All rights reserved.

K4B4G1646B datasheet DDR3 SDRAM

1.0 - First SPEC. Release Jan. 2012 - J.Y.Lee

K4B4G1646B datasheet DDR3 SDRAM

K4B4G1646B datasheet DDR3 SDRAM

K4B4G1646B datasheet DDR3 SDRAM

K4B4G1646B datasheet DDR3 SDRAM

A VDDQ DQU5 DQU7 DQU4 VDDQ VSS A

K4B4G1646B datasheet DDR3 SDRAM

3.2 FBGA Package Dimension (x16)

96 - ∅0.45 Solder ball (0.95) MOLDING AREA

#A1 10.00 ± 0.10

K4B4G1646B datasheet DDR3 SDRAM

K4B4G1646B datasheet DDR3 SDRAM

K4B4G1646B datasheet DDR3 SDRAM

6.2 DRAM Component Operating Temperature Range

7. AC & DC Operating Conditions

K4B4G1646B datasheet DDR3 SDRAM

[ Table 8 ] Single-ended AC & DC input levels for DQ and DM

K4B4G1646B datasheet DDR3 SDRAM

Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits

"VREF" shall be understood as VREF(DC), as defined in Figure 1 .

K4B4G1646B datasheet DDR3 SDRAM

Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC

K4B4G1646B datasheet DDR3 SDRAM

Figure 3. Single-ended requirement for differential signals

K4B4G1646B datasheet DDR3 SDRAM

Figure 4. VIX Definition

8.5 Slew rate definition for Differential Input Signals

8.6 Slew rate definitions for Differential Input Signals

[ Table 13 ] Differential input slew rate definition

delta TFdiff delta TRdiff

K4B4G1646B datasheet DDR3 SDRAM

9.2 Differential AC & DC Output Levels

9.3 Single-ended Output Slew Rate

[ Table 17 ] Single-ended output slew rate

delta TFse delta TRse

Figure 6. Single-ended Output Slew Rate Definition

K4B4G1646B datasheet DDR3 SDRAM

[ Table 18 ] Differential output slew rate definition

[ Table 19 ] Differential output slew rate

delta TFdiff delta TRdiff

Figure 7. Differential Output Slew Rate Definition

9.5 Reference Load for AC Timing and Output Slew Rate

Figure 8. Reference Load for AC Timing and Output Slew Rate

K4B4G1646B datasheet DDR3 SDRAM

Figure 9. Address and Control Overshoot and Undershoot Definition

K4B4G1646B datasheet DDR3 SDRAM

RON34 = RZQ/7 (Nominal 34.3ohms +/- 10% with nominal RZQ=240ohm)

Figure 11. Output Driver : Definition of Voltages and Currents

[ Table 22 ] Output Driver DC Electrical Characteristics, assuming RZQ=240ohms ;

K4B4G1646B datasheet DDR3 SDRAM

[ Table 23 ] Output Driver Sensitivity Definition

[ Table 24 ] Output Driver Voltage and Temperature Sensitivity

dRONdVM 0 0.15 0 0.13 %/mV

dRONdVL 0 0.15 0 0.13 %/mV

dRONdVH 0 0.15 0 0.13 %/mV