mc33385vw 80fd951059
mc33385vw 80fd951059
mc33385vw 80fd951059
Features
• RDSON of 250m: per Output at 25qC
• Supplied from the main 5V VCC
• Input CMOS Compatible DH SUFFIX
• Diagnostic through SPI VW SUFFIX (PB-FREE)
98ASH70702A
• Nominal Current of 2A per Output 20-PIN HSOP
• Current Limitation at 3A with Automatic Turn Off
• Output Internally Clamped at 50V typ for Inductive Load Drive
ORDERING INFORMATION
• Junction to Case Thermal Resistance of 4.4qC/W
• Individual Output over Temperature Shutdown Temperature
Device Package
Range (TA)
• Pb-Free Packaging Designated by Suffix Code VW
MC33385DH/R2
-40°C to 125°C 20 HSOP
MC33385VW/R2
VPWR
Voltage 33385
Regulator OUT1
VCC OUT2
OUT3
OUT4
NCS
CLK
SDI GND1-4
SDO
MCU NRE
NON1
NON2
NON3
NON4
BLOCK DIAGRAM
VCC
NON2 OUT1
S
OUT2
NON3 URES DRIVER dv/dt control
R OUT3
RES
NON4 OUT4
RES Over-temp. detection
URES
FR Reset ON1
IRES
VCC I-SCB filter
t-ISCB
SDI ON1
VCC
I-OL filter
t-IOL
CLK NON1
VCC
Shift Failure SCG filter
Register Register t-SCG
(FR)
NCS Vref
URES RES OSC
IRES
GND NRES
33385
PIN CONNECTIONS
21
GND2 1 20 GND1
OUT2 2 19 OUT1
N.C 3 18 N.C
NON2 4 17 NON1
SDI 5 16 SDO
Heat sink
CLK 6 15 NRES
NCS 7 14 VCC
NON4 8 13 NON3
OUT4 9 12 OUT3
GND4 10 11 GND3
21
1 GND2 Ground 2
3 NC
10 GND4 Ground 4
11 GND3 Ground 3
18 NC
20 GND1 Ground 1
33385
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL RATINGS
THERMAL RATINGS
Operating Junction Temperature TJ 150 qC
Thermal Resistance : Junction-case (One power stage in use) RTHJC 4.5 k:
Thermal Resistance : Junction-ambient (Device soldered on printed circuit board) RTHJA 50 k:
Peak Package Reflow Temperature During Reflow (1), (2) TPPRT Note 2 °C
Notes
1. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
2. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
33385
STATIC CHARACTERISTICS
SUPPLY VOLTAGE
JUNCTION TEMPERATURE
OUTPUT CURRENT
Output Current Range IOUT ISCBMAX $
RESET BEHAVIOUR
Reset Changeable (at NRES-Pin) VCC VCCRES 5.5 V
Undervoltage Reset (Independent of NRES) VCCRES 3.35 3.95 V
Active for VCC = 0V to VCCPRO
UNDERVOLTAGE PROTECTION
OVER TEMPERATURE
SUPPLY CURRENT
33385
POWERSTAGE PROTECTION
DIAGNOSTIC
33385
DYNAMIC CHARACTERISTIC
INPUTS
OUTPUTS TIMING
DIAGNOSTIC
Short to GND Filter Time TSCG 140 250 Ps
Open Load Filter Time tOL 140 250 Ps
SDI Input Hold Time (SDI data hold after CLK change High/Low) tHCLD 20 ns
CLK Low Before NCS High tSCLCL 150 ns
33385
33385
TIMING DIAGRAMS
NCS
CLK
FR-RESET
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0 FSL
STATUS CHANNEL 4
11 : no failure
01 : open circuit
10: short to battery or overtemperature
00 : short to gnd
STATUS CHANNEL 3
STATUS CHANNEL 2
STATUS CHANNEL 1
NCS
CLK
SDO FSL D0 D7
tHCLD
tCSDV
SDI D0 D1 D7
33385
SCG-failure
VDRAIN
t-SCG (filter-time)
Filter time
Failure detection
Failure store
off
NON on
I-OL
Iload
Diagnostic active
retrigger t filter retrigger filter t < t-ol
t-ol (filter-time)
tol
Sporadic failure-detection
Failure detection
Failure store
33385
350
- 40qC
300
250
Energy (mJ)
200
25qC
150
100
125qC
50
0
0 0,5 1 1,5 2 2,5 3 3,5 4
Pulse-Duration (ms)
Figure 9. Max Clamp- Energy Specification
380
3
375
2,75 VCC=5,5V
370
2,50
365
ICCSTB (mA)
2,25
VINL/VCC
VCC=5,5V 360
2
355 VCC=4,5V
1,75
VCC=5,15V 350
1,50
345
1,25
340
1 -50 -25 0 25 50 75 100 125
-50 -25 0 25 50 75 100 125 T, TEMPERATURE (qC)
T, TEMPERATURE (qC)
Figure 12. Low Threshold Input Voltage versus
Figure 10. Standby Current versus Temperature Temperature
12,50 624
12,00 623
11,50 622
ICCOPM (mA)
11,00 621
VCC=4,5V ou 5,5V
VinH/Vcc
10,50 620
10,00 619
9,50 618
VCC=5,15V
9,00 617
All outputs=2A
8,50 616
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
T, TEMPERATURE (qC) T, TEMPERATURE (qC)
Figure 11. Operating Mode Current versus Temperature
Figure 13. High Threshold Input Voltage versus
Temperature
33385
55,00 3,78
54,50 3,77
54,00 3,76
53,50
VCCMIN (V)
3,75
VCLP (V)
53,00 3,74
IOUT1=1A
52,50 3,73
52,00 3,72
51,50 3,71
51,00 3,70
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
T, TEMPERATURE (qC) T, TEMPERATURE (qC)
Figure 14. Output Clamp Voltage versus Temperature Figure 17. Vcc Undervoltage versus Temperature
400 4,60
VCC=4,5V
375 4,50
IOUT1=3A VCC=5,5V
350 4,40
RDSON (m:)
325 4,30
4,20
ISCB (A)
300
275 4,10
250 4,00
VCC=4,5V
225 3,90
200 3,80
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
T, TEMPERATURE (qC) T, TEMPERATURE (qC)
Figure 15. Rdson versus Temperature Figure 18. Short Current Limit versus Temperature
24,50
24,25
24,00
23,75
IOL (mA)
23,50
23,25
23,00
22,75
22,50
-50 -25 0 25 50 75 100 125
T, TEMPERATURE (qC)
Figure 16. Open Load versus Temperature Figure 19. Inductive Switching
33385
In1 (1V/div)
VOUT1(2V/div)
tDON VOUT1(2V/div)
tDOFFA
tDOFFB
In1 (1V/div)
33385
FUNCTIONAL DESCRIPTION
INTRODUCTION
The device is a Quad Low-side Driver driven by four If the current through the output stage is lower than the
CMOS input stages. Each output power transistor is IOL-reference, after a filter time an OL failure will be
protected against short to VBAT by a zener clamp against recognized. This measurement is active while the power
overvoltage. stage is switched on.
A diagnostic logic recognizes four failure types at the The SCG failure will recognize when the drain voltage is
output stage : overcurrent, short to GND, open-load and lower than the OL reference limit, while the output stage is
overtemperature. switched off. All four outputs have an independent
The failures are individually stored in a byte which can be overtemperature detection and shutdown. All failures are
read out via the serial interface (SPI). stored in individual registers.
They can be read by the microprocessor via the serial
OUTPUT STAGE CONTROL interface. There is no failure detected if the power stage
Each of the four output stages is switched ON and OFF by control time is shorter than the filter time.
an individual control line (NON-Input). The logic level of the
control line is CMOS compatible. The output transistors are DIAGNOSTIC INTERFACE
switched off when the inputs are not connected. The communication between the microprocessor and the
failure register runs via the SPI link. If there is a failure stored
POWER TRANSISTORS in the failure register, the first bit of the shift register is set to
Each of the four output stages has its own zener clamp. a high level. With the High/Low change on the NCS pin, the
This causes a voltage limitation at the power transistors when first bit of the diagnostic shift register will be transmitted to the
inductive loads are switched off. The drain voltage ramp SDO output. The SDO output is the serial output from the
occurring when output is switched on or off, is within defined diagnostic shift register and it is put into a tri-state when the
limits. Output transistors can be connected in parallel to NCS pin is high. The CLK pin clocks the diagnostic shift
increase current capability. In this case, the associated inputs register. New SDO data will appear on every rising edge of
should be connected together. this pin and new SDI data will be latched on every CLK’s
falling edge into the shift register. With the first positive pulse
of the CLK, the failure register will be cleared. There is no bus
SHORT-CIRCUIT AND OVERTEMPERATURE collision at a small spike at the NCS. The CLK is always LOW
PROTECTION while the NCS-signal is changing.
If the output current increases above the short current limit
for a time longer than tSCB or if the temperature increases RESET
above TOFF then the power transistor is immediately
There are two different reset functions realized :
switched off. It remains switched off until the control signal on
the NON-Input is switched off and on again. Under voltage reset : as long as the VCC voltage is lower
than VCCRES, the power stages are switched off and the
failure-registers are reset.
DIAGNOSTICS
Reset pin : as long as the NRES-pin is low, following
The following failures at the output stage are recognized :
circuits are reset :
Short -Circuit to VBAT or overtemp = SCB (Highest priority)
• Power stages
Short -Circuit to GND.................... = SCG
• Failure register
Open Load...................................... = OL (Lowest priority)
The SCB failure is recognized by an overcurrent (current UNDERVOLTAGE PROTECTION
above the short current limit) or an overtemperature. At low VCC voltage, the device remains switched off even
if there is a voltage ramp at the OUT pin.
33385
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
DH SUFFIX
VW (PB-FREE) SUFFIX
20-PIN HSOP
PLASTIC PACKAGE
98ASH70702A
ISSUE B
33385
DH SUFFIX
VW (PB-FREE) SUFFIX
20-PIN HSOP
PLASTIC PACKAGE
98ASH70702A
ISSUE B
33385
REVISION HISTORY
33385
MC33385
Rev. 6.0
11/2006